1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "mac.h" 7 #include "phy.h" 8 #include "reg.h" 9 #include "rtw8852a.h" 10 #include "rtw8852a_rfk.h" 11 #include "rtw8852a_table.h" 12 #include "txrx.h" 13 14 static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = { 15 {128, 1896, grp_0}, /* ACH 0 */ 16 {128, 1896, grp_0}, /* ACH 1 */ 17 {128, 1896, grp_0}, /* ACH 2 */ 18 {128, 1896, grp_0}, /* ACH 3 */ 19 {128, 1896, grp_1}, /* ACH 4 */ 20 {128, 1896, grp_1}, /* ACH 5 */ 21 {128, 1896, grp_1}, /* ACH 6 */ 22 {128, 1896, grp_1}, /* ACH 7 */ 23 {32, 1896, grp_0}, /* B0MGQ */ 24 {128, 1896, grp_0}, /* B0HIQ */ 25 {32, 1896, grp_1}, /* B1MGQ */ 26 {128, 1896, grp_1}, /* B1HIQ */ 27 {40, 0, 0} /* FWCMDQ */ 28 }; 29 30 static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = { 31 1896, /* Group 0 */ 32 1896, /* Group 1 */ 33 3792, /* Public Max */ 34 0 /* WP threshold */ 35 }; 36 37 static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = { 38 [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie, 39 &rtw_hfc_preccfg_pcie, RTW89_HCIFC_POH}, 40 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw_hfc_preccfg_pcie, RTW89_HCIFC_POH}, 41 [RTW89_QTA_INVALID] = {NULL}, 42 }; 43 44 static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = { 45 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &wde_size0, &ple_size0, &wde_qt0, 46 &wde_qt0, &ple_qt4, &ple_qt5}, 47 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &wde_size4, &ple_size4, 48 &wde_qt4, &wde_qt4, &ple_qt13, &ple_qt13}, 49 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 50 NULL}, 51 }; 52 53 static const struct rtw89_reg2_def rtw8852a_pmac_ht20_mcs7_tbl[] = { 54 {0x44AC, 0x00000000}, 55 {0x44B0, 0x00000000}, 56 {0x44B4, 0x00000000}, 57 {0x44B8, 0x00000000}, 58 {0x44BC, 0x00000000}, 59 {0x44C0, 0x00000000}, 60 {0x44C4, 0x00000000}, 61 {0x44C8, 0x00000000}, 62 {0x44CC, 0x00000000}, 63 {0x44D0, 0x00000000}, 64 {0x44D4, 0x00000000}, 65 {0x44D8, 0x00000000}, 66 {0x44DC, 0x00000000}, 67 {0x44E0, 0x00000000}, 68 {0x44E4, 0x00000000}, 69 {0x44E8, 0x00000000}, 70 {0x44EC, 0x00000000}, 71 {0x44F0, 0x00000000}, 72 {0x44F4, 0x00000000}, 73 {0x44F8, 0x00000000}, 74 {0x44FC, 0x00000000}, 75 {0x4500, 0x00000000}, 76 {0x4504, 0x00000000}, 77 {0x4508, 0x00000000}, 78 {0x450C, 0x00000000}, 79 {0x4510, 0x00000000}, 80 {0x4514, 0x00000000}, 81 {0x4518, 0x00000000}, 82 {0x451C, 0x00000000}, 83 {0x4520, 0x00000000}, 84 {0x4524, 0x00000000}, 85 {0x4528, 0x00000000}, 86 {0x452C, 0x00000000}, 87 {0x4530, 0x4E1F3E81}, 88 {0x4534, 0x00000000}, 89 {0x4538, 0x0000005A}, 90 {0x453C, 0x00000000}, 91 {0x4540, 0x00000000}, 92 {0x4544, 0x00000000}, 93 {0x4548, 0x00000000}, 94 {0x454C, 0x00000000}, 95 {0x4550, 0x00000000}, 96 {0x4554, 0x00000000}, 97 {0x4558, 0x00000000}, 98 {0x455C, 0x00000000}, 99 {0x4560, 0x4060001A}, 100 {0x4564, 0x40000000}, 101 {0x4568, 0x00000000}, 102 {0x456C, 0x00000000}, 103 {0x4570, 0x04000007}, 104 {0x4574, 0x0000DC87}, 105 {0x4578, 0x00000BAB}, 106 {0x457C, 0x03E00000}, 107 {0x4580, 0x00000048}, 108 {0x4584, 0x00000000}, 109 {0x4588, 0x000003E8}, 110 {0x458C, 0x30000000}, 111 {0x4590, 0x00000000}, 112 {0x4594, 0x10000000}, 113 {0x4598, 0x00000001}, 114 {0x459C, 0x00030000}, 115 {0x45A0, 0x01000000}, 116 {0x45A4, 0x03000200}, 117 {0x45A8, 0xC00001C0}, 118 {0x45AC, 0x78018000}, 119 {0x45B0, 0x80000000}, 120 {0x45B4, 0x01C80600}, 121 {0x45B8, 0x00000002}, 122 {0x4594, 0x10000000} 123 }; 124 125 static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = { 126 {0x4624, GENMASK(20, 14), 0x40}, 127 {0x46f8, GENMASK(20, 14), 0x40}, 128 {0x4674, GENMASK(20, 19), 0x2}, 129 {0x4748, GENMASK(20, 19), 0x2}, 130 {0x4650, GENMASK(14, 10), 0x18}, 131 {0x4724, GENMASK(14, 10), 0x18}, 132 {0x4688, GENMASK(1, 0), 0x3}, 133 {0x475c, GENMASK(1, 0), 0x3}, 134 }; 135 136 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs); 137 138 static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = { 139 {0x4624, GENMASK(20, 14), 0x1a}, 140 {0x46f8, GENMASK(20, 14), 0x1a}, 141 {0x4674, GENMASK(20, 19), 0x1}, 142 {0x4748, GENMASK(20, 19), 0x1}, 143 {0x4650, GENMASK(14, 10), 0x12}, 144 {0x4724, GENMASK(14, 10), 0x12}, 145 {0x4688, GENMASK(1, 0), 0x0}, 146 {0x475c, GENMASK(1, 0), 0x0}, 147 }; 148 149 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs); 150 151 static const struct rtw89_pwr_cfg rtw8852a_pwron[] = { 152 {0x00C6, 153 PWR_CV_MSK_B, 154 PWR_INTF_MSK_PCIE, 155 PWR_BASE_MAC, 156 PWR_CMD_WRITE, BIT(6), BIT(6)}, 157 {0x1086, 158 PWR_CV_MSK_ALL, 159 PWR_INTF_MSK_SDIO, 160 PWR_BASE_MAC, 161 PWR_CMD_WRITE, BIT(0), 0}, 162 {0x1086, 163 PWR_CV_MSK_ALL, 164 PWR_INTF_MSK_SDIO, 165 PWR_BASE_MAC, 166 PWR_CMD_POLL, BIT(1), BIT(1)}, 167 {0x0005, 168 PWR_CV_MSK_ALL, 169 PWR_INTF_MSK_ALL, 170 PWR_BASE_MAC, 171 PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, 172 {0x0005, 173 PWR_CV_MSK_ALL, 174 PWR_INTF_MSK_ALL, 175 PWR_BASE_MAC, 176 PWR_CMD_WRITE, BIT(7), 0}, 177 {0x0005, 178 PWR_CV_MSK_ALL, 179 PWR_INTF_MSK_ALL, 180 PWR_BASE_MAC, 181 PWR_CMD_WRITE, BIT(2), 0}, 182 {0x0006, 183 PWR_CV_MSK_ALL, 184 PWR_INTF_MSK_ALL, 185 PWR_BASE_MAC, 186 PWR_CMD_POLL, BIT(1), BIT(1)}, 187 {0x0006, 188 PWR_CV_MSK_ALL, 189 PWR_INTF_MSK_ALL, 190 PWR_BASE_MAC, 191 PWR_CMD_WRITE, BIT(0), BIT(0)}, 192 {0x0005, 193 PWR_CV_MSK_ALL, 194 PWR_INTF_MSK_ALL, 195 PWR_BASE_MAC, 196 PWR_CMD_WRITE, BIT(0), BIT(0)}, 197 {0x0005, 198 PWR_CV_MSK_ALL, 199 PWR_INTF_MSK_ALL, 200 PWR_BASE_MAC, 201 PWR_CMD_POLL, BIT(0), 0}, 202 {0x106D, 203 PWR_CV_MSK_B | PWR_CV_MSK_C, 204 PWR_INTF_MSK_USB, 205 PWR_BASE_MAC, 206 PWR_CMD_WRITE, BIT(6), 0}, 207 {0x0088, 208 PWR_CV_MSK_ALL, 209 PWR_INTF_MSK_ALL, 210 PWR_BASE_MAC, 211 PWR_CMD_WRITE, BIT(0), BIT(0)}, 212 {0x0088, 213 PWR_CV_MSK_ALL, 214 PWR_INTF_MSK_ALL, 215 PWR_BASE_MAC, 216 PWR_CMD_WRITE, BIT(0), 0}, 217 {0x0088, 218 PWR_CV_MSK_ALL, 219 PWR_INTF_MSK_ALL, 220 PWR_BASE_MAC, 221 PWR_CMD_WRITE, BIT(0), BIT(0)}, 222 {0x0088, 223 PWR_CV_MSK_ALL, 224 PWR_INTF_MSK_ALL, 225 PWR_BASE_MAC, 226 PWR_CMD_WRITE, BIT(0), 0}, 227 {0x0088, 228 PWR_CV_MSK_ALL, 229 PWR_INTF_MSK_ALL, 230 PWR_BASE_MAC, 231 PWR_CMD_WRITE, BIT(0), BIT(0)}, 232 {0x0083, 233 PWR_CV_MSK_ALL, 234 PWR_INTF_MSK_ALL, 235 PWR_BASE_MAC, 236 PWR_CMD_WRITE, BIT(6), 0}, 237 {0x0080, 238 PWR_CV_MSK_ALL, 239 PWR_INTF_MSK_ALL, 240 PWR_BASE_MAC, 241 PWR_CMD_WRITE, BIT(5), BIT(5)}, 242 {0x0024, 243 PWR_CV_MSK_ALL, 244 PWR_INTF_MSK_ALL, 245 PWR_BASE_MAC, 246 PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0}, 247 {0x02A0, 248 PWR_CV_MSK_ALL, 249 PWR_INTF_MSK_ALL, 250 PWR_BASE_MAC, 251 PWR_CMD_WRITE, BIT(1), BIT(1)}, 252 {0x02A2, 253 PWR_CV_MSK_ALL, 254 PWR_INTF_MSK_ALL, 255 PWR_BASE_MAC, 256 PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0}, 257 {0x0071, 258 PWR_CV_MSK_ALL, 259 PWR_INTF_MSK_PCIE, 260 PWR_BASE_MAC, 261 PWR_CMD_WRITE, BIT(4), 0}, 262 {0x0010, 263 PWR_CV_MSK_A, 264 PWR_INTF_MSK_PCIE, 265 PWR_BASE_MAC, 266 PWR_CMD_WRITE, BIT(2), BIT(2)}, 267 {0x02A0, 268 PWR_CV_MSK_A, 269 PWR_INTF_MSK_ALL, 270 PWR_BASE_MAC, 271 PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 272 {0xFFFF, 273 PWR_CV_MSK_ALL, 274 PWR_INTF_MSK_ALL, 275 0, 276 PWR_CMD_END, 0, 0}, 277 }; 278 279 static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = { 280 {0x02F0, 281 PWR_CV_MSK_ALL, 282 PWR_INTF_MSK_ALL, 283 PWR_BASE_MAC, 284 PWR_CMD_WRITE, 0xFF, 0}, 285 {0x02F1, 286 PWR_CV_MSK_ALL, 287 PWR_INTF_MSK_ALL, 288 PWR_BASE_MAC, 289 PWR_CMD_WRITE, 0xFF, 0}, 290 {0x0006, 291 PWR_CV_MSK_ALL, 292 PWR_INTF_MSK_ALL, 293 PWR_BASE_MAC, 294 PWR_CMD_WRITE, BIT(0), BIT(0)}, 295 {0x0002, 296 PWR_CV_MSK_ALL, 297 PWR_INTF_MSK_ALL, 298 PWR_BASE_MAC, 299 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 300 {0x0082, 301 PWR_CV_MSK_ALL, 302 PWR_INTF_MSK_ALL, 303 PWR_BASE_MAC, 304 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 305 {0x106D, 306 PWR_CV_MSK_B | PWR_CV_MSK_C, 307 PWR_INTF_MSK_USB, 308 PWR_BASE_MAC, 309 PWR_CMD_WRITE, BIT(6), BIT(6)}, 310 {0x0005, 311 PWR_CV_MSK_ALL, 312 PWR_INTF_MSK_ALL, 313 PWR_BASE_MAC, 314 PWR_CMD_WRITE, BIT(1), BIT(1)}, 315 {0x0005, 316 PWR_CV_MSK_ALL, 317 PWR_INTF_MSK_ALL, 318 PWR_BASE_MAC, 319 PWR_CMD_POLL, BIT(1), 0}, 320 {0x0091, 321 PWR_CV_MSK_ALL, 322 PWR_INTF_MSK_PCIE, 323 PWR_BASE_MAC, 324 PWR_CMD_WRITE, BIT(0), 0}, 325 {0x0005, 326 PWR_CV_MSK_ALL, 327 PWR_INTF_MSK_PCIE, 328 PWR_BASE_MAC, 329 PWR_CMD_WRITE, BIT(2), BIT(2)}, 330 {0x0007, 331 PWR_CV_MSK_ALL, 332 PWR_INTF_MSK_USB, 333 PWR_BASE_MAC, 334 PWR_CMD_WRITE, BIT(4), 0}, 335 {0x0007, 336 PWR_CV_MSK_ALL, 337 PWR_INTF_MSK_SDIO, 338 PWR_BASE_MAC, 339 PWR_CMD_WRITE, BIT(6) | BIT(4), 0}, 340 {0x0005, 341 PWR_CV_MSK_ALL, 342 PWR_INTF_MSK_SDIO, 343 PWR_BASE_MAC, 344 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 345 {0x0005, 346 PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F | 347 PWR_CV_MSK_G, 348 PWR_INTF_MSK_USB, 349 PWR_BASE_MAC, 350 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 351 {0x1086, 352 PWR_CV_MSK_ALL, 353 PWR_INTF_MSK_SDIO, 354 PWR_BASE_MAC, 355 PWR_CMD_WRITE, BIT(0), BIT(0)}, 356 {0x1086, 357 PWR_CV_MSK_ALL, 358 PWR_INTF_MSK_SDIO, 359 PWR_BASE_MAC, 360 PWR_CMD_POLL, BIT(1), 0}, 361 {0xFFFF, 362 PWR_CV_MSK_ALL, 363 PWR_INTF_MSK_ALL, 364 0, 365 PWR_CMD_END, 0, 0}, 366 }; 367 368 static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = { 369 rtw8852a_pwron, NULL 370 }; 371 372 static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = { 373 rtw8852a_pwroff, NULL 374 }; 375 376 static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse, 377 struct rtw8852a_efuse *map) 378 { 379 ether_addr_copy(efuse->addr, map->e.mac_addr); 380 efuse->rfe_type = map->rfe_type; 381 efuse->xtal_cap = map->xtal_k; 382 } 383 384 static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 385 struct rtw8852a_efuse *map) 386 { 387 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 388 struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 389 u8 i, j; 390 391 tssi->thermal[RF_PATH_A] = map->path_a_therm; 392 tssi->thermal[RF_PATH_B] = map->path_b_therm; 393 394 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 395 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 396 sizeof(ofst[i]->cck_tssi)); 397 398 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 399 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 400 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 401 i, j, tssi->tssi_cck[i][j]); 402 403 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 404 sizeof(ofst[i]->bw40_tssi)); 405 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 406 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 407 408 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 409 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 410 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 411 i, j, tssi->tssi_mcs[i][j]); 412 } 413 } 414 415 static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map) 416 { 417 struct rtw89_efuse *efuse = &rtwdev->efuse; 418 struct rtw8852a_efuse *map; 419 420 map = (struct rtw8852a_efuse *)log_map; 421 422 efuse->country_code[0] = map->country_code[0]; 423 efuse->country_code[1] = map->country_code[1]; 424 rtw8852a_efuse_parsing_tssi(rtwdev, map); 425 426 switch (rtwdev->hci.type) { 427 case RTW89_HCI_TYPE_PCIE: 428 rtw8852ae_efuse_parsing(efuse, map); 429 break; 430 default: 431 return -ENOTSUPP; 432 } 433 434 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 435 436 return 0; 437 } 438 439 static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 440 { 441 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 442 static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB}; 443 u32 addr = rtwdev->chip->phycap_addr; 444 bool pg = false; 445 u32 ofst; 446 u8 i, j; 447 448 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 449 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 450 /* addrs are in decreasing order */ 451 ofst = tssi_trim_addr[i] - addr - j; 452 tssi->tssi_trim[i][j] = phycap_map[ofst]; 453 454 if (phycap_map[ofst] != 0xff) 455 pg = true; 456 } 457 } 458 459 if (!pg) { 460 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 461 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 462 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 463 } 464 465 for (i = 0; i < RF_PATH_NUM_8852A; i++) 466 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 467 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 468 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 469 i, j, tssi->tssi_trim[i][j], 470 tssi_trim_addr[i] - j); 471 } 472 473 static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 474 u8 *phycap_map) 475 { 476 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 477 static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC}; 478 u32 addr = rtwdev->chip->phycap_addr; 479 u8 i; 480 481 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 482 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 483 484 rtw89_debug(rtwdev, RTW89_DBG_RFK, 485 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 486 i, info->thermal_trim[i]); 487 488 if (info->thermal_trim[i] != 0xff) 489 info->pg_thermal_trim = true; 490 } 491 } 492 493 static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev) 494 { 495 #define __thm_setting(raw) \ 496 ({ \ 497 u8 __v = (raw); \ 498 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 499 }) 500 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 501 u8 i, val; 502 503 if (!info->pg_thermal_trim) { 504 rtw89_debug(rtwdev, RTW89_DBG_RFK, 505 "[THERMAL][TRIM] no PG, do nothing\n"); 506 507 return; 508 } 509 510 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 511 val = __thm_setting(info->thermal_trim[i]); 512 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 513 514 rtw89_debug(rtwdev, RTW89_DBG_RFK, 515 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 516 i, val); 517 } 518 #undef __thm_setting 519 } 520 521 static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 522 u8 *phycap_map) 523 { 524 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 525 static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB}; 526 u32 addr = rtwdev->chip->phycap_addr; 527 u8 i; 528 529 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 530 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 531 532 rtw89_debug(rtwdev, RTW89_DBG_RFK, 533 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 534 i, info->pa_bias_trim[i]); 535 536 if (info->pa_bias_trim[i] != 0xff) 537 info->pg_pa_bias_trim = true; 538 } 539 } 540 541 static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev) 542 { 543 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 544 u8 pabias_2g, pabias_5g; 545 u8 i; 546 547 if (!info->pg_pa_bias_trim) { 548 rtw89_debug(rtwdev, RTW89_DBG_RFK, 549 "[PA_BIAS][TRIM] no PG, do nothing\n"); 550 551 return; 552 } 553 554 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 555 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 556 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 557 558 rtw89_debug(rtwdev, RTW89_DBG_RFK, 559 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 560 i, pabias_2g, pabias_5g); 561 562 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 563 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 564 } 565 } 566 567 static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 568 { 569 rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map); 570 rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map); 571 rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 572 573 return 0; 574 } 575 576 static void rtw8852a_power_trim(struct rtw89_dev *rtwdev) 577 { 578 rtw8852a_thermal_trim(rtwdev); 579 rtw8852a_pa_bias_trim(rtwdev); 580 } 581 582 static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev, 583 struct rtw89_channel_params *param, 584 u8 mac_idx) 585 { 586 u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx); 587 u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, 588 mac_idx); 589 u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx); 590 u8 txsc20 = 0, txsc40 = 0; 591 592 switch (param->bandwidth) { 593 case RTW89_CHANNEL_WIDTH_80: 594 txsc40 = rtw89_phy_get_txsc(rtwdev, param, 595 RTW89_CHANNEL_WIDTH_40); 596 fallthrough; 597 case RTW89_CHANNEL_WIDTH_40: 598 txsc20 = rtw89_phy_get_txsc(rtwdev, param, 599 RTW89_CHANNEL_WIDTH_20); 600 break; 601 default: 602 break; 603 } 604 605 switch (param->bandwidth) { 606 case RTW89_CHANNEL_WIDTH_80: 607 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); 608 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); 609 break; 610 case RTW89_CHANNEL_WIDTH_40: 611 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); 612 rtw89_write32(rtwdev, sub_carr, txsc20); 613 break; 614 case RTW89_CHANNEL_WIDTH_20: 615 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); 616 rtw89_write32(rtwdev, sub_carr, 0); 617 break; 618 default: 619 break; 620 } 621 622 if (param->center_chan > 14) 623 rtw89_write8_set(rtwdev, chk_rate, 624 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 625 else 626 rtw89_write8_clr(rtwdev, chk_rate, 627 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 628 } 629 630 static const u32 rtw8852a_sco_barker_threshold[14] = { 631 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, 632 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 633 }; 634 635 static const u32 rtw8852a_sco_cck_threshold[14] = { 636 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, 637 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed 638 }; 639 640 static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 641 u8 primary_ch, enum rtw89_bandwidth bw) 642 { 643 u8 ch_element; 644 645 if (bw == RTW89_CHANNEL_WIDTH_20) { 646 ch_element = central_ch - 1; 647 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 648 if (primary_ch == 1) 649 ch_element = central_ch - 1 + 2; 650 else 651 ch_element = central_ch - 1 - 2; 652 } else { 653 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 654 return -EINVAL; 655 } 656 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, 657 rtw8852a_sco_barker_threshold[ch_element]); 658 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, 659 rtw8852a_sco_cck_threshold[ch_element]); 660 661 return 0; 662 } 663 664 static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch, 665 u8 path) 666 { 667 u32 val; 668 669 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 670 if (val == INV_RF_DATA) { 671 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 672 return; 673 } 674 val &= ~0x303ff; 675 val |= central_ch; 676 if (central_ch > 14) 677 val |= (BIT(16) | BIT(8)); 678 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 679 } 680 681 static u8 rtw8852a_sco_mapping(u8 central_ch) 682 { 683 if (central_ch == 1) 684 return 109; 685 else if (central_ch >= 2 && central_ch <= 6) 686 return 108; 687 else if (central_ch >= 7 && central_ch <= 10) 688 return 107; 689 else if (central_ch >= 11 && central_ch <= 14) 690 return 106; 691 else if (central_ch == 36 || central_ch == 38) 692 return 51; 693 else if (central_ch >= 40 && central_ch <= 58) 694 return 50; 695 else if (central_ch >= 60 && central_ch <= 64) 696 return 49; 697 else if (central_ch == 100 || central_ch == 102) 698 return 48; 699 else if (central_ch >= 104 && central_ch <= 126) 700 return 47; 701 else if (central_ch >= 128 && central_ch <= 151) 702 return 46; 703 else if (central_ch >= 153 && central_ch <= 177) 704 return 45; 705 else 706 return 0; 707 } 708 709 static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch, 710 enum rtw89_phy_idx phy_idx) 711 { 712 u8 sco_comp; 713 bool is_2g = central_ch <= 14; 714 715 if (phy_idx == RTW89_PHY_0) { 716 /* Path A */ 717 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A); 718 if (is_2g) 719 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 720 B_PATH0_TIA_ERR_G1_SEL, 1, 721 phy_idx); 722 else 723 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 724 B_PATH0_TIA_ERR_G1_SEL, 0, 725 phy_idx); 726 727 /* Path B */ 728 if (!rtwdev->dbcc_en) { 729 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 730 if (is_2g) 731 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 732 B_P1_MODE_SEL, 733 1, phy_idx); 734 else 735 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 736 B_P1_MODE_SEL, 737 0, phy_idx); 738 } else { 739 if (is_2g) 740 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, 741 B_2P4G_BAND_SEL); 742 else 743 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, 744 B_2P4G_BAND_SEL); 745 } 746 /* SCO compensate FC setting */ 747 sco_comp = rtw8852a_sco_mapping(central_ch); 748 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 749 sco_comp, phy_idx); 750 } else { 751 /* Path B */ 752 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 753 if (is_2g) 754 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 755 B_P1_MODE_SEL, 756 1, phy_idx); 757 else 758 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 759 B_P1_MODE_SEL, 760 0, phy_idx); 761 /* SCO compensate FC setting */ 762 sco_comp = rtw8852a_sco_mapping(central_ch); 763 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 764 sco_comp, phy_idx); 765 } 766 767 /* Band edge */ 768 if (is_2g) 769 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1, 770 phy_idx); 771 else 772 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0, 773 phy_idx); 774 775 /* CCK parameters */ 776 if (central_ch == 14) { 777 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 778 0x3b13ff); 779 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 780 0x1c42de); 781 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 782 0xfdb0ad); 783 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 784 0xf60f6e); 785 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 786 0xfd8f92); 787 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); 788 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); 789 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 790 0xfff00a); 791 } else { 792 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 793 0x3d23ff); 794 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 795 0x29b354); 796 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); 797 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 798 0xfdb053); 799 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 800 0xf86f9a); 801 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 802 0xfaef92); 803 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 804 0xfe5fcc); 805 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 806 0xffdff5); 807 } 808 } 809 810 static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 811 { 812 u32 val = 0; 813 u32 adc_sel[2] = {0x12d0, 0x32d0}; 814 u32 wbadc_sel[2] = {0x12ec, 0x32ec}; 815 816 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 817 if (val == INV_RF_DATA) { 818 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 819 return; 820 } 821 val &= ~(BIT(11) | BIT(10)); 822 switch (bw) { 823 case RTW89_CHANNEL_WIDTH_5: 824 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 825 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 826 val |= (BIT(11) | BIT(10)); 827 break; 828 case RTW89_CHANNEL_WIDTH_10: 829 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 830 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 831 val |= (BIT(11) | BIT(10)); 832 break; 833 case RTW89_CHANNEL_WIDTH_20: 834 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 835 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 836 val |= (BIT(11) | BIT(10)); 837 break; 838 case RTW89_CHANNEL_WIDTH_40: 839 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 840 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 841 val |= BIT(11); 842 break; 843 case RTW89_CHANNEL_WIDTH_80: 844 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 845 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 846 val |= BIT(10); 847 break; 848 default: 849 rtw89_warn(rtwdev, "Fail to set ADC\n"); 850 } 851 852 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 853 } 854 855 static void 856 rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 857 enum rtw89_phy_idx phy_idx) 858 { 859 /* Switch bandwidth */ 860 switch (bw) { 861 case RTW89_CHANNEL_WIDTH_5: 862 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 863 phy_idx); 864 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1, 865 phy_idx); 866 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 867 0x0, phy_idx); 868 break; 869 case RTW89_CHANNEL_WIDTH_10: 870 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 871 phy_idx); 872 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2, 873 phy_idx); 874 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 875 0x0, phy_idx); 876 break; 877 case RTW89_CHANNEL_WIDTH_20: 878 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 879 phy_idx); 880 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 881 phy_idx); 882 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 883 0x0, phy_idx); 884 break; 885 case RTW89_CHANNEL_WIDTH_40: 886 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 887 phy_idx); 888 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 889 phy_idx); 890 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 891 pri_ch, 892 phy_idx); 893 if (pri_ch == RTW89_SC_20_UPPER) 894 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); 895 else 896 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); 897 break; 898 case RTW89_CHANNEL_WIDTH_80: 899 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 900 phy_idx); 901 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 902 phy_idx); 903 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 904 pri_ch, 905 phy_idx); 906 break; 907 default: 908 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 909 pri_ch); 910 } 911 912 if (phy_idx == RTW89_PHY_0) { 913 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A); 914 if (!rtwdev->dbcc_en) 915 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 916 } else { 917 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 918 } 919 } 920 921 static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch) 922 { 923 if (central_ch == 153) { 924 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 925 0x210); 926 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 927 0x210); 928 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x7c0); 929 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 930 B_P0_NBIIDX_NOTCH_EN, 0x1); 931 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 932 B_P1_NBIIDX_NOTCH_EN, 0x1); 933 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 934 0x1); 935 } else if (central_ch == 151) { 936 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 937 0x210); 938 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 939 0x210); 940 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x40); 941 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 942 B_P0_NBIIDX_NOTCH_EN, 0x1); 943 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 944 B_P1_NBIIDX_NOTCH_EN, 0x1); 945 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 946 0x1); 947 } else if (central_ch == 155) { 948 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 949 0x2d0); 950 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 951 0x2d0); 952 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x740); 953 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 954 B_P0_NBIIDX_NOTCH_EN, 0x1); 955 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 956 B_P1_NBIIDX_NOTCH_EN, 0x1); 957 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 958 0x1); 959 } else { 960 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 961 B_P0_NBIIDX_NOTCH_EN, 0x0); 962 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 963 B_P1_NBIIDX_NOTCH_EN, 0x0); 964 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 965 0x0); 966 } 967 } 968 969 static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev, 970 enum rtw89_phy_idx phy_idx) 971 { 972 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 973 phy_idx); 974 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 975 phy_idx); 976 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 977 phy_idx); 978 } 979 980 static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev, 981 enum rtw89_phy_idx phy_idx, bool en) 982 { 983 if (en) 984 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 985 1, 986 phy_idx); 987 else 988 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 989 0, 990 phy_idx); 991 } 992 993 static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev, 994 enum rtw89_phy_idx phy_idx) 995 { 996 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 997 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 998 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 999 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1000 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1001 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1002 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1003 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1004 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1005 } 1006 1007 static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1008 enum rtw89_phy_idx phy_idx) 1009 { 1010 u32 addr; 1011 1012 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1013 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1014 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1015 } 1016 1017 static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev) 1018 { 1019 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); 1020 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP); 1021 1022 if (rtwdev->hal.cv <= CHIP_CCV) { 1023 rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG); 1024 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000); 1025 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x3F); 1026 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF); 1027 rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST); 1028 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1029 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1030 } 1031 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f); 1032 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c); 1033 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); 1034 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1); 1035 rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK); 1036 rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK); 1037 1038 rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1039 } 1040 1041 static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev, 1042 enum rtw89_phy_idx phy_idx) 1043 { 1044 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1045 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1046 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1047 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1048 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1049 udelay(1); 1050 } 1051 1052 static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev, 1053 struct rtw89_channel_params *param, 1054 enum rtw89_phy_idx phy_idx) 1055 { 1056 bool cck_en = param->center_chan > 14 ? false : true; 1057 u8 pri_ch_idx = param->pri_ch_idx; 1058 1059 if (param->center_chan <= 14) 1060 rtw8852a_ctrl_sco_cck(rtwdev, param->center_chan, 1061 param->primary_chan, param->bandwidth); 1062 1063 rtw8852a_ctrl_ch(rtwdev, param->center_chan, phy_idx); 1064 rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, param->bandwidth, phy_idx); 1065 if (cck_en) { 1066 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); 1067 } else { 1068 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); 1069 rtw8852a_bbrst_for_rfk(rtwdev, phy_idx); 1070 } 1071 rtw8852a_spur_elimination(rtwdev, param->center_chan); 1072 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1073 } 1074 1075 static void rtw8852a_set_channel(struct rtw89_dev *rtwdev, 1076 struct rtw89_channel_params *params) 1077 { 1078 rtw8852a_set_channel_mac(rtwdev, params, RTW89_MAC_0); 1079 rtw8852a_set_channel_bb(rtwdev, params, RTW89_PHY_0); 1080 } 1081 1082 static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en) 1083 { 1084 if (en) 1085 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1086 else 1087 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1088 } 1089 1090 static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 1091 enum rtw89_rf_path path) 1092 { 1093 static const u32 tssi_trk[2] = {0x5818, 0x7818}; 1094 static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc}; 1095 1096 if (en) { 1097 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0); 1098 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0); 1099 } else { 1100 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1); 1101 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1); 1102 } 1103 } 1104 1105 static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, 1106 u8 phy_idx) 1107 { 1108 if (!rtwdev->dbcc_en) { 1109 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1110 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1111 } else { 1112 if (phy_idx == RTW89_PHY_0) 1113 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1114 else 1115 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1116 } 1117 } 1118 1119 static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en) 1120 { 1121 if (en) 1122 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1123 0x0); 1124 else 1125 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1126 0xf); 1127 } 1128 1129 static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1130 struct rtw89_channel_help_params *p) 1131 { 1132 u8 phy_idx = RTW89_PHY_0; 1133 1134 if (enter) { 1135 rtw89_mac_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL); 1136 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 1137 rtw8852a_dfs_en(rtwdev, false); 1138 rtw8852a_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0); 1139 rtw8852a_adc_en(rtwdev, false); 1140 fsleep(40); 1141 rtw8852a_bb_reset_en(rtwdev, phy_idx, false); 1142 } else { 1143 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 1144 rtw8852a_adc_en(rtwdev, true); 1145 rtw8852a_dfs_en(rtwdev, true); 1146 rtw8852a_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0); 1147 rtw8852a_bb_reset_en(rtwdev, phy_idx, true); 1148 rtw89_mac_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en); 1149 } 1150 } 1151 1152 static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev) 1153 { 1154 struct rtw89_efuse *efuse = &rtwdev->efuse; 1155 1156 switch (efuse->rfe_type) { 1157 case 11: 1158 case 12: 1159 case 17: 1160 case 18: 1161 case 51: 1162 case 53: 1163 rtwdev->fem.epa_2g = true; 1164 rtwdev->fem.elna_2g = true; 1165 fallthrough; 1166 case 9: 1167 case 10: 1168 case 15: 1169 case 16: 1170 rtwdev->fem.epa_5g = true; 1171 rtwdev->fem.elna_5g = true; 1172 break; 1173 default: 1174 break; 1175 } 1176 } 1177 1178 static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev) 1179 { 1180 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1181 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1182 1183 rtw8852a_rck(rtwdev); 1184 rtw8852a_dack(rtwdev); 1185 rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true); 1186 } 1187 1188 static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev) 1189 { 1190 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 1191 1192 rtw8852a_rx_dck(rtwdev, phy_idx, true); 1193 rtw8852a_iqk(rtwdev, phy_idx); 1194 rtw8852a_tssi(rtwdev, phy_idx); 1195 rtw8852a_dpk(rtwdev, phy_idx); 1196 } 1197 1198 static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev) 1199 { 1200 rtw8852a_tssi_scan(rtwdev, RTW89_PHY_0); 1201 } 1202 1203 static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, bool start) 1204 { 1205 rtw8852a_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); 1206 } 1207 1208 static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev) 1209 { 1210 rtw8852a_dpk_track(rtwdev); 1211 rtw8852a_iqk_track(rtwdev); 1212 rtw8852a_tssi_track(rtwdev); 1213 } 1214 1215 static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1216 enum rtw89_phy_idx phy_idx, s16 ref) 1217 { 1218 s8 ofst_int = 0; 1219 u8 base_cw_0db = 0x27; 1220 u16 tssi_16dbm_cw = 0x12c; 1221 s16 pwr_s10_3 = 0; 1222 s16 rf_pwr_cw = 0; 1223 u16 bb_pwr_cw = 0; 1224 u32 pwr_cw = 0; 1225 u32 tssi_ofst_cw = 0; 1226 1227 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1228 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1229 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1230 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1231 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1232 1233 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1234 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1235 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1236 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1237 1238 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1239 } 1240 1241 static 1242 void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1243 s16 pw_ofst, enum rtw89_mac_idx mac_idx) 1244 { 1245 s32 val_1t = 0; 1246 s32 val_2t = 0; 1247 u32 reg; 1248 1249 if (pw_ofst < -16 || pw_ofst > 15) { 1250 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n", 1251 pw_ofst); 1252 return; 1253 } 1254 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx); 1255 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); 1256 val_1t = (s32)pw_ofst; 1257 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx); 1258 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t); 1259 val_2t = max(val_1t - 3, -16); 1260 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx); 1261 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t); 1262 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n", 1263 val_1t, val_2t); 1264 } 1265 1266 static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev, 1267 enum rtw89_phy_idx phy_idx) 1268 { 1269 static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800}; 1270 const u32 mask = 0x7FFFFFF; 1271 const u8 ofst_ofdm = 0x4; 1272 const u8 ofst_cck = 0x8; 1273 s16 ref_ofdm = 0; 1274 s16 ref_cck = 0; 1275 u32 val; 1276 u8 i; 1277 1278 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1279 1280 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1281 GENMASK(27, 10), 0x0); 1282 1283 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1284 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1285 1286 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1287 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1288 phy_idx); 1289 1290 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1291 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1292 1293 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1294 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1295 phy_idx); 1296 } 1297 1298 static void rtw8852a_set_txpwr_byrate(struct rtw89_dev *rtwdev, 1299 enum rtw89_phy_idx phy_idx) 1300 { 1301 u8 ch = rtwdev->hal.current_channel; 1302 static const u8 rs[] = { 1303 RTW89_RS_CCK, 1304 RTW89_RS_OFDM, 1305 RTW89_RS_MCS, 1306 RTW89_RS_HEDCM, 1307 }; 1308 s8 tmp; 1309 u8 i, j; 1310 u32 val, shf, addr = R_AX_PWR_BY_RATE; 1311 struct rtw89_rate_desc cur; 1312 1313 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1314 "[TXPWR] set txpwr byrate with ch=%d\n", ch); 1315 1316 for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) { 1317 for (i = 0; i < ARRAY_SIZE(rs); i++) { 1318 if (cur.nss >= rtw89_rs_nss_max[rs[i]]) 1319 continue; 1320 1321 val = 0; 1322 cur.rs = rs[i]; 1323 1324 for (j = 0; j < rtw89_rs_idx_max[rs[i]]; j++) { 1325 cur.idx = j; 1326 shf = (j % 4) * 8; 1327 tmp = rtw89_phy_read_txpwr_byrate(rtwdev, &cur); 1328 val |= (tmp << shf); 1329 1330 if ((j + 1) % 4) 1331 continue; 1332 1333 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 1334 val = 0; 1335 addr += 4; 1336 } 1337 } 1338 } 1339 } 1340 1341 static void rtw8852a_set_txpwr_offset(struct rtw89_dev *rtwdev, 1342 enum rtw89_phy_idx phy_idx) 1343 { 1344 struct rtw89_rate_desc desc = { 1345 .nss = RTW89_NSS_1, 1346 .rs = RTW89_RS_OFFSET, 1347 }; 1348 u32 val = 0; 1349 s8 v; 1350 1351 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n"); 1352 1353 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++) { 1354 v = rtw89_phy_read_txpwr_byrate(rtwdev, &desc); 1355 val |= ((v & 0xf) << (4 * desc.idx)); 1356 } 1357 1358 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL, 1359 GENMASK(19, 0), val); 1360 } 1361 1362 static void rtw8852a_set_txpwr_limit(struct rtw89_dev *rtwdev, 1363 enum rtw89_phy_idx phy_idx) 1364 { 1365 #define __MAC_TXPWR_LMT_PAGE_SIZE 40 1366 u8 ch = rtwdev->hal.current_channel; 1367 u8 bw = rtwdev->hal.current_band_width; 1368 struct rtw89_txpwr_limit lmt[NTX_NUM_8852A]; 1369 u32 addr, val; 1370 const s8 *ptr; 1371 u8 i, j, k; 1372 1373 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1374 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw); 1375 1376 for (i = 0; i < NTX_NUM_8852A; i++) { 1377 rtw89_phy_fill_txpwr_limit(rtwdev, &lmt[i], i); 1378 1379 for (j = 0; j < __MAC_TXPWR_LMT_PAGE_SIZE; j += 4) { 1380 addr = R_AX_PWR_LMT + j + __MAC_TXPWR_LMT_PAGE_SIZE * i; 1381 ptr = (s8 *)&lmt[i] + j; 1382 val = 0; 1383 1384 for (k = 0; k < 4; k++) 1385 val |= (ptr[k] << (8 * k)); 1386 1387 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 1388 } 1389 } 1390 #undef __MAC_TXPWR_LMT_PAGE_SIZE 1391 } 1392 1393 static void rtw8852a_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, 1394 enum rtw89_phy_idx phy_idx) 1395 { 1396 #define __MAC_TXPWR_LMT_RU_PAGE_SIZE 24 1397 u8 ch = rtwdev->hal.current_channel; 1398 u8 bw = rtwdev->hal.current_band_width; 1399 struct rtw89_txpwr_limit_ru lmt_ru[NTX_NUM_8852A]; 1400 u32 addr, val; 1401 const s8 *ptr; 1402 u8 i, j, k; 1403 1404 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1405 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); 1406 1407 for (i = 0; i < NTX_NUM_8852A; i++) { 1408 rtw89_phy_fill_txpwr_limit_ru(rtwdev, &lmt_ru[i], i); 1409 1410 for (j = 0; j < __MAC_TXPWR_LMT_RU_PAGE_SIZE; j += 4) { 1411 addr = R_AX_PWR_RU_LMT + j + 1412 __MAC_TXPWR_LMT_RU_PAGE_SIZE * i; 1413 ptr = (s8 *)&lmt_ru[i] + j; 1414 val = 0; 1415 1416 for (k = 0; k < 4; k++) 1417 val |= (ptr[k] << (8 * k)); 1418 1419 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 1420 } 1421 } 1422 1423 #undef __MAC_TXPWR_LMT_RU_PAGE_SIZE 1424 } 1425 1426 static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev) 1427 { 1428 rtw8852a_set_txpwr_byrate(rtwdev, RTW89_PHY_0); 1429 rtw8852a_set_txpwr_limit(rtwdev, RTW89_PHY_0); 1430 rtw8852a_set_txpwr_limit_ru(rtwdev, RTW89_PHY_0); 1431 } 1432 1433 static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 1434 { 1435 rtw8852a_set_txpwr_ref(rtwdev, RTW89_PHY_0); 1436 rtw8852a_set_txpwr_offset(rtwdev, RTW89_PHY_0); 1437 } 1438 1439 static int 1440 rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1441 { 1442 int ret; 1443 1444 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 1445 if (ret) 1446 return ret; 1447 1448 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004); 1449 if (ret) 1450 return ret; 1451 1452 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 1453 if (ret) 1454 return ret; 1455 1456 return 0; 1457 } 1458 1459 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev) 1460 { 1461 u8 i = 0; 1462 u32 addr, val; 1463 1464 for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) { 1465 addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr; 1466 val = rtw8852a_pmac_ht20_mcs7_tbl[i].data; 1467 rtw89_phy_write32(rtwdev, addr, val); 1468 } 1469 } 1470 1471 static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev, 1472 struct rtw8852a_bb_pmac_info *tx_info, 1473 enum rtw89_phy_idx idx) 1474 { 1475 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx"); 1476 if (tx_info->mode == CONT_TX) 1477 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, 1478 idx); 1479 else if (tx_info->mode == PKTS_TX) 1480 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, 1481 idx); 1482 } 1483 1484 static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev, 1485 struct rtw8852a_bb_pmac_info *tx_info, 1486 enum rtw89_phy_idx idx) 1487 { 1488 enum rtw8852a_pmac_mode mode = tx_info->mode; 1489 u32 pkt_cnt = tx_info->tx_cnt; 1490 u16 period = tx_info->period; 1491 1492 if (mode == CONT_TX && !tx_info->is_cck) { 1493 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, 1494 idx); 1495 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start"); 1496 } else if (mode == PKTS_TX) { 1497 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, 1498 idx); 1499 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, 1500 B_PMAC_TX_PRD_MSK, period, idx); 1501 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK, 1502 pkt_cnt, idx); 1503 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start"); 1504 } 1505 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx); 1506 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx); 1507 } 1508 1509 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev, 1510 struct rtw8852a_bb_pmac_info *tx_info, 1511 enum rtw89_phy_idx idx) 1512 { 1513 if (!tx_info->en_pmac_tx) { 1514 rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx); 1515 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx); 1516 if (rtwdev->hal.current_band_type == RTW89_BAND_2G) 1517 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS); 1518 return; 1519 } 1520 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable"); 1521 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx); 1522 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx); 1523 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, 1524 idx); 1525 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx); 1526 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx); 1527 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); 1528 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx); 1529 rtw8852a_start_pmac_tx(rtwdev, tx_info, idx); 1530 } 1531 1532 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, 1533 u16 tx_cnt, u16 period, u16 tx_time, 1534 enum rtw89_phy_idx idx) 1535 { 1536 struct rtw8852a_bb_pmac_info tx_info = {0}; 1537 1538 tx_info.en_pmac_tx = enable; 1539 tx_info.is_cck = 0; 1540 tx_info.mode = PKTS_TX; 1541 tx_info.tx_cnt = tx_cnt; 1542 tx_info.period = period; 1543 tx_info.tx_time = tx_time; 1544 rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx); 1545 } 1546 1547 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, 1548 enum rtw89_phy_idx idx) 1549 { 1550 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm); 1551 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); 1552 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx); 1553 } 1554 1555 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) 1556 { 1557 u32 rst_mask0 = 0; 1558 u32 rst_mask1 = 0; 1559 1560 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0); 1561 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1); 1562 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path); 1563 if (!rtwdev->dbcc_en) { 1564 if (tx_path == RF_PATH_A) { 1565 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1566 B_TXPATH_SEL_MSK, 1); 1567 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1568 B_TXNSS_MAP_MSK, 0); 1569 } else if (tx_path == RF_PATH_B) { 1570 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1571 B_TXPATH_SEL_MSK, 2); 1572 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1573 B_TXNSS_MAP_MSK, 0); 1574 } else if (tx_path == RF_PATH_AB) { 1575 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1576 B_TXPATH_SEL_MSK, 3); 1577 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1578 B_TXNSS_MAP_MSK, 4); 1579 } else { 1580 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path"); 1581 } 1582 } else { 1583 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1584 1); 1585 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2, 1586 RTW89_PHY_1); 1587 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 1588 0); 1589 rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4, 1590 RTW89_PHY_1); 1591 } 1592 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 1593 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 1594 if (tx_path == RF_PATH_A) { 1595 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 1596 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 1597 } else { 1598 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 1599 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 1600 } 1601 } 1602 1603 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev, 1604 enum rtw89_phy_idx idx, u8 mode) 1605 { 1606 if (mode != 0) 1607 return; 1608 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch"); 1609 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx); 1610 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx); 1611 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx); 1612 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx); 1613 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx); 1614 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx); 1615 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx); 1616 } 1617 1618 static void rtw8852a_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en) 1619 { 1620 rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8852a_btc_preagc_en_defs_tbl : 1621 &rtw8852a_btc_preagc_dis_defs_tbl); 1622 } 1623 1624 static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 1625 { 1626 if (rtwdev->is_tssi_mode[rf_path]) { 1627 u32 addr = 0x1c10 + (rf_path << 13); 1628 1629 return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000); 1630 } 1631 1632 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1633 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 1634 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1635 1636 fsleep(200); 1637 1638 return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 1639 } 1640 1641 static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev) 1642 { 1643 struct rtw89_btc *btc = &rtwdev->btc; 1644 struct rtw89_btc_module *module = &btc->mdinfo; 1645 1646 module->rfe_type = rtwdev->efuse.rfe_type; 1647 module->cv = rtwdev->hal.cv; 1648 module->bt_solo = 0; 1649 module->switch_type = BTC_SWITCH_INTERNAL; 1650 1651 if (module->rfe_type > 0) 1652 module->ant.num = (module->rfe_type % 2 ? 2 : 3); 1653 else 1654 module->ant.num = 2; 1655 1656 module->ant.diversity = 0; 1657 module->ant.isolation = 10; 1658 1659 if (module->ant.num == 3) { 1660 module->ant.type = BTC_ANT_DEDICATED; 1661 module->bt_pos = BTC_BT_ALONE; 1662 } else { 1663 module->ant.type = BTC_ANT_SHARED; 1664 module->bt_pos = BTC_BT_BTG; 1665 } 1666 } 1667 1668 static 1669 void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 1670 { 1671 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000); 1672 rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group); 1673 rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val); 1674 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0); 1675 } 1676 1677 static void rtw8852a_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 1678 { 1679 if (btg) { 1680 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1); 1681 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3); 1682 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 1683 } else { 1684 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0); 1685 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0); 1686 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 1687 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 1688 } 1689 } 1690 1691 static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev) 1692 { 1693 struct rtw89_btc *btc = &rtwdev->btc; 1694 struct rtw89_btc_module *module = &btc->mdinfo; 1695 const struct rtw89_chip_info *chip = rtwdev->chip; 1696 const struct rtw89_mac_ax_coex coex_params = { 1697 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 1698 .direction = RTW89_MAC_AX_COEX_INNER, 1699 }; 1700 1701 /* PTA init */ 1702 rtw89_mac_coex_init(rtwdev, &coex_params); 1703 1704 /* set WL Tx response = Hi-Pri */ 1705 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 1706 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 1707 1708 /* set rf gnt debug off */ 1709 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0); 1710 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0); 1711 1712 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 1713 if (module->ant.type == BTC_ANT_SHARED) { 1714 rtw8852a_set_trx_mask(rtwdev, 1715 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 1716 rtw8852a_set_trx_mask(rtwdev, 1717 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 1718 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 1719 rtw8852a_set_trx_mask(rtwdev, 1720 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 1721 rtw8852a_set_trx_mask(rtwdev, 1722 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 1723 } 1724 1725 /* set PTA break table */ 1726 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); 1727 1728 /* enable BT counter 0xda40[16,2] = 2b'11 */ 1729 rtw89_write32_set(rtwdev, 1730 R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); 1731 btc->cx.wl.status.map.init_ok = true; 1732 } 1733 1734 static 1735 void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 1736 { 1737 u32 bitmap = 0; 1738 u32 reg = 0; 1739 1740 switch (map) { 1741 case BTC_PRI_MASK_TX_RESP: 1742 reg = R_BTC_BT_COEX_MSK_TABLE; 1743 bitmap = B_BTC_PRI_MASK_TX_RESP_V1; 1744 break; 1745 case BTC_PRI_MASK_BEACON: 1746 reg = R_AX_WL_PRI_MSK; 1747 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; 1748 break; 1749 default: 1750 return; 1751 } 1752 1753 if (state) 1754 rtw89_write32_set(rtwdev, reg, bitmap); 1755 else 1756 rtw89_write32_clr(rtwdev, reg, bitmap); 1757 } 1758 1759 static inline u32 __btc_ctrl_val_all_time(u32 ctrl) 1760 { 1761 return FIELD_GET(GENMASK(15, 0), ctrl); 1762 } 1763 1764 static inline u32 __btc_ctrl_rst_all_time(u32 cur) 1765 { 1766 return cur & ~B_AX_FORCE_PWR_BY_RATE_EN; 1767 } 1768 1769 static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val) 1770 { 1771 u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1772 u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1773 1774 return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN; 1775 } 1776 1777 static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl) 1778 { 1779 return FIELD_GET(GENMASK(31, 16), ctrl); 1780 } 1781 1782 static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur) 1783 { 1784 return cur & ~B_AX_TXAGC_BT_EN; 1785 } 1786 1787 static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val) 1788 { 1789 u32 ov = cur & ~B_AX_TXAGC_BT_MASK; 1790 u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val); 1791 1792 return ov | iv | B_AX_TXAGC_BT_EN; 1793 } 1794 1795 static void 1796 rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 1797 { 1798 const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL; 1799 const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL; 1800 1801 #define __do_clr(_chk) ((_chk) == GENMASK(15, 0)) 1802 #define __handle(_case) \ 1803 do { \ 1804 const u32 _reg = __btc_cr_ ## _case; \ 1805 u32 _val = __btc_ctrl_val_ ## _case(txpwr_val); \ 1806 u32 _cur, _wrt; \ 1807 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1808 "btc ctrl %s: 0x%x\n", #_case, _val); \ 1809 rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur);\ 1810 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1811 "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur); \ 1812 _wrt = __do_clr(_val) ? \ 1813 __btc_ctrl_rst_ ## _case(_cur) : \ 1814 __btc_ctrl_gen_ ## _case(_cur, _val); \ 1815 rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\ 1816 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1817 "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt); \ 1818 } while (0) 1819 1820 __handle(all_time); 1821 __handle(gnt_bt); 1822 1823 #undef __handle 1824 #undef __do_clr 1825 } 1826 1827 static 1828 s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 1829 { 1830 return clamp_t(s8, val, -100, 0) + 100; 1831 } 1832 1833 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = { 1834 {255, 0, 0, 7}, /* 0 -> original */ 1835 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 1836 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1837 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1838 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1839 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1840 {6, 1, 0, 7}, 1841 {13, 1, 0, 7}, 1842 {13, 1, 0, 7} 1843 }; 1844 1845 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = { 1846 {255, 0, 0, 7}, /* 0 -> original */ 1847 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 1848 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1849 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1850 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1851 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1852 {255, 1, 0, 7}, 1853 {255, 1, 0, 7}, 1854 {255, 1, 0, 7} 1855 }; 1856 1857 static const 1858 u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 1859 static const 1860 u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 1861 1862 static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = { 1863 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 1864 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), 1865 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), 1866 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 1867 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 1868 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), 1869 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), 1870 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 1871 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), 1872 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), 1873 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 1874 RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178), 1875 }; 1876 1877 static 1878 void rtw8852a_btc_bt_aci_imp(struct rtw89_dev *rtwdev) 1879 { 1880 struct rtw89_btc *btc = &rtwdev->btc; 1881 struct rtw89_btc_dm *dm = &btc->dm; 1882 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 1883 struct rtw89_btc_bt_link_info *b = &bt->link_info; 1884 1885 /* fix LNA2 = level-5 for BT ACI issue at BTG */ 1886 if (btc->dm.wl_btg_rx && b->profile_cnt.now != 0) 1887 dm->trx_para_level = 1; 1888 } 1889 1890 static 1891 void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 1892 { 1893 struct rtw89_btc *btc = &rtwdev->btc; 1894 struct rtw89_btc_cx *cx = &btc->cx; 1895 u32 val; 1896 1897 val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH); 1898 cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val); 1899 cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val); 1900 1901 val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW); 1902 cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val); 1903 cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val); 1904 1905 /* clock-gate off before reset counter*/ 1906 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 1907 rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 1908 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 1909 rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 1910 } 1911 1912 static 1913 void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 1914 { 1915 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 1916 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 1917 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1); 1918 1919 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 1920 if (state) 1921 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 1922 RFREG_MASK, 0xa2d7c); 1923 else 1924 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 1925 RFREG_MASK, 0xa2020); 1926 1927 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 1928 } 1929 1930 static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev, 1931 struct rtw89_rx_phy_ppdu *phy_ppdu, 1932 struct ieee80211_rx_status *status) 1933 { 1934 u8 path; 1935 s8 *rx_power = phy_ppdu->rssi; 1936 1937 status->signal = max_t(s8, rx_power[RF_PATH_A], rx_power[RF_PATH_B]); 1938 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 1939 status->chains |= BIT(path); 1940 status->chain_signal[path] = rx_power[path]; 1941 } 1942 } 1943 1944 static const struct rtw89_chip_ops rtw8852a_chip_ops = { 1945 .bb_reset = rtw8852a_bb_reset, 1946 .bb_sethw = rtw8852a_bb_sethw, 1947 .read_rf = rtw89_phy_read_rf, 1948 .write_rf = rtw89_phy_write_rf, 1949 .set_channel = rtw8852a_set_channel, 1950 .set_channel_help = rtw8852a_set_channel_help, 1951 .read_efuse = rtw8852a_read_efuse, 1952 .read_phycap = rtw8852a_read_phycap, 1953 .fem_setup = rtw8852a_fem_setup, 1954 .rfk_init = rtw8852a_rfk_init, 1955 .rfk_channel = rtw8852a_rfk_channel, 1956 .rfk_band_changed = rtw8852a_rfk_band_changed, 1957 .rfk_scan = rtw8852a_rfk_scan, 1958 .rfk_track = rtw8852a_rfk_track, 1959 .power_trim = rtw8852a_power_trim, 1960 .set_txpwr = rtw8852a_set_txpwr, 1961 .set_txpwr_ctrl = rtw8852a_set_txpwr_ctrl, 1962 .init_txpwr_unit = rtw8852a_init_txpwr_unit, 1963 .get_thermal = rtw8852a_get_thermal, 1964 .ctrl_btg = rtw8852a_ctrl_btg, 1965 .query_ppdu = rtw8852a_query_ppdu, 1966 .bb_ctrl_btc_preagc = rtw8852a_bb_ctrl_btc_preagc, 1967 .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset, 1968 1969 .btc_set_rfe = rtw8852a_btc_set_rfe, 1970 .btc_init_cfg = rtw8852a_btc_init_cfg, 1971 .btc_set_wl_pri = rtw8852a_btc_set_wl_pri, 1972 .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl, 1973 .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi, 1974 .btc_bt_aci_imp = rtw8852a_btc_bt_aci_imp, 1975 .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt, 1976 .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby, 1977 }; 1978 1979 const struct rtw89_chip_info rtw8852a_chip_info = { 1980 .chip_id = RTL8852A, 1981 .ops = &rtw8852a_chip_ops, 1982 .fw_name = "rtw89/rtw8852a_fw.bin", 1983 .fifo_size = 458752, 1984 .max_amsdu_limit = 3500, 1985 .dis_2g_40m_ul_ofdma = true, 1986 .hfc_param_ini = rtw8852a_hfc_param_ini_pcie, 1987 .dle_mem = rtw8852a_dle_mem_pcie, 1988 .rf_base_addr = {0xc000, 0xd000}, 1989 .pwr_on_seq = pwr_on_seq_8852a, 1990 .pwr_off_seq = pwr_off_seq_8852a, 1991 .bb_table = &rtw89_8852a_phy_bb_table, 1992 .rf_table = {&rtw89_8852a_phy_radioa_table, 1993 &rtw89_8852a_phy_radiob_table,}, 1994 .nctl_table = &rtw89_8852a_phy_nctl_table, 1995 .byr_table = &rtw89_8852a_byr_table, 1996 .txpwr_lmt_2g = &rtw89_8852a_txpwr_lmt_2g, 1997 .txpwr_lmt_5g = &rtw89_8852a_txpwr_lmt_5g, 1998 .txpwr_lmt_ru_2g = &rtw89_8852a_txpwr_lmt_ru_2g, 1999 .txpwr_lmt_ru_5g = &rtw89_8852a_txpwr_lmt_ru_5g, 2000 .txpwr_factor_rf = 2, 2001 .txpwr_factor_mac = 1, 2002 .dig_table = &rtw89_8852a_phy_dig_table, 2003 .rf_path_num = 2, 2004 .tx_nss = 2, 2005 .rx_nss = 2, 2006 .acam_num = 128, 2007 .bcam_num = 10, 2008 .scam_num = 128, 2009 .sec_ctrl_efuse_size = 4, 2010 .physical_efuse_size = 1216, 2011 .logical_efuse_size = 1536, 2012 .limit_efuse_size = 1152, 2013 .phycap_addr = 0x580, 2014 .phycap_size = 128, 2015 .para_ver = 0x05050764, 2016 .wlcx_desired = 0x05050000, 2017 .btcx_desired = 0x5, 2018 .scbd = 0x1, 2019 .mailbox = 0x1, 2020 .afh_guard_ch = 6, 2021 .wl_rssi_thres = rtw89_btc_8852a_wl_rssi_thres, 2022 .bt_rssi_thres = rtw89_btc_8852a_bt_rssi_thres, 2023 .rssi_tol = 2, 2024 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852a_mon_reg), 2025 .mon_reg = rtw89_btc_8852a_mon_reg, 2026 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_ul), 2027 .rf_para_ulink = rtw89_btc_8852a_rf_ul, 2028 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_dl), 2029 .rf_para_dlink = rtw89_btc_8852a_rf_dl, 2030 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2031 BIT(RTW89_PS_MODE_CLK_GATED) | 2032 BIT(RTW89_PS_MODE_PWR_GATED), 2033 }; 2034 EXPORT_SYMBOL(rtw8852a_chip_info); 2035 2036 MODULE_FIRMWARE("rtw89/rtw8852a_fw.bin"); 2037