1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "reg.h" 10 #include "rtw8852a.h" 11 #include "rtw8852a_rfk.h" 12 #include "rtw8852a_table.h" 13 #include "txrx.h" 14 15 static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = { 16 {128, 1896, grp_0}, /* ACH 0 */ 17 {128, 1896, grp_0}, /* ACH 1 */ 18 {128, 1896, grp_0}, /* ACH 2 */ 19 {128, 1896, grp_0}, /* ACH 3 */ 20 {128, 1896, grp_1}, /* ACH 4 */ 21 {128, 1896, grp_1}, /* ACH 5 */ 22 {128, 1896, grp_1}, /* ACH 6 */ 23 {128, 1896, grp_1}, /* ACH 7 */ 24 {32, 1896, grp_0}, /* B0MGQ */ 25 {128, 1896, grp_0}, /* B0HIQ */ 26 {32, 1896, grp_1}, /* B1MGQ */ 27 {128, 1896, grp_1}, /* B1HIQ */ 28 {40, 0, 0} /* FWCMDQ */ 29 }; 30 31 static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = { 32 1896, /* Group 0 */ 33 1896, /* Group 1 */ 34 3792, /* Public Max */ 35 0 /* WP threshold */ 36 }; 37 38 static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = { 39 [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie, 40 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 41 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 42 RTW89_HCIFC_POH}, 43 [RTW89_QTA_INVALID] = {NULL}, 44 }; 45 46 static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = { 47 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0, 48 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0, 49 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4, 50 &rtw89_mac_size.ple_qt5}, 51 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4, 52 &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4, 53 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 54 &rtw89_mac_size.ple_qt13}, 55 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 56 NULL}, 57 }; 58 59 static const struct rtw89_reg2_def rtw8852a_pmac_ht20_mcs7_tbl[] = { 60 {0x44AC, 0x00000000}, 61 {0x44B0, 0x00000000}, 62 {0x44B4, 0x00000000}, 63 {0x44B8, 0x00000000}, 64 {0x44BC, 0x00000000}, 65 {0x44C0, 0x00000000}, 66 {0x44C4, 0x00000000}, 67 {0x44C8, 0x00000000}, 68 {0x44CC, 0x00000000}, 69 {0x44D0, 0x00000000}, 70 {0x44D4, 0x00000000}, 71 {0x44D8, 0x00000000}, 72 {0x44DC, 0x00000000}, 73 {0x44E0, 0x00000000}, 74 {0x44E4, 0x00000000}, 75 {0x44E8, 0x00000000}, 76 {0x44EC, 0x00000000}, 77 {0x44F0, 0x00000000}, 78 {0x44F4, 0x00000000}, 79 {0x44F8, 0x00000000}, 80 {0x44FC, 0x00000000}, 81 {0x4500, 0x00000000}, 82 {0x4504, 0x00000000}, 83 {0x4508, 0x00000000}, 84 {0x450C, 0x00000000}, 85 {0x4510, 0x00000000}, 86 {0x4514, 0x00000000}, 87 {0x4518, 0x00000000}, 88 {0x451C, 0x00000000}, 89 {0x4520, 0x00000000}, 90 {0x4524, 0x00000000}, 91 {0x4528, 0x00000000}, 92 {0x452C, 0x00000000}, 93 {0x4530, 0x4E1F3E81}, 94 {0x4534, 0x00000000}, 95 {0x4538, 0x0000005A}, 96 {0x453C, 0x00000000}, 97 {0x4540, 0x00000000}, 98 {0x4544, 0x00000000}, 99 {0x4548, 0x00000000}, 100 {0x454C, 0x00000000}, 101 {0x4550, 0x00000000}, 102 {0x4554, 0x00000000}, 103 {0x4558, 0x00000000}, 104 {0x455C, 0x00000000}, 105 {0x4560, 0x4060001A}, 106 {0x4564, 0x40000000}, 107 {0x4568, 0x00000000}, 108 {0x456C, 0x00000000}, 109 {0x4570, 0x04000007}, 110 {0x4574, 0x0000DC87}, 111 {0x4578, 0x00000BAB}, 112 {0x457C, 0x03E00000}, 113 {0x4580, 0x00000048}, 114 {0x4584, 0x00000000}, 115 {0x4588, 0x000003E8}, 116 {0x458C, 0x30000000}, 117 {0x4590, 0x00000000}, 118 {0x4594, 0x10000000}, 119 {0x4598, 0x00000001}, 120 {0x459C, 0x00030000}, 121 {0x45A0, 0x01000000}, 122 {0x45A4, 0x03000200}, 123 {0x45A8, 0xC00001C0}, 124 {0x45AC, 0x78018000}, 125 {0x45B0, 0x80000000}, 126 {0x45B4, 0x01C80600}, 127 {0x45B8, 0x00000002}, 128 {0x4594, 0x10000000} 129 }; 130 131 static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = { 132 {0x4624, GENMASK(20, 14), 0x40}, 133 {0x46f8, GENMASK(20, 14), 0x40}, 134 {0x4674, GENMASK(20, 19), 0x2}, 135 {0x4748, GENMASK(20, 19), 0x2}, 136 {0x4650, GENMASK(14, 10), 0x18}, 137 {0x4724, GENMASK(14, 10), 0x18}, 138 {0x4688, GENMASK(1, 0), 0x3}, 139 {0x475c, GENMASK(1, 0), 0x3}, 140 }; 141 142 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs); 143 144 static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = { 145 {0x4624, GENMASK(20, 14), 0x1a}, 146 {0x46f8, GENMASK(20, 14), 0x1a}, 147 {0x4674, GENMASK(20, 19), 0x1}, 148 {0x4748, GENMASK(20, 19), 0x1}, 149 {0x4650, GENMASK(14, 10), 0x12}, 150 {0x4724, GENMASK(14, 10), 0x12}, 151 {0x4688, GENMASK(1, 0), 0x0}, 152 {0x475c, GENMASK(1, 0), 0x0}, 153 }; 154 155 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs); 156 157 static const struct rtw89_pwr_cfg rtw8852a_pwron[] = { 158 {0x00C6, 159 PWR_CV_MSK_B, 160 PWR_INTF_MSK_PCIE, 161 PWR_BASE_MAC, 162 PWR_CMD_WRITE, BIT(6), BIT(6)}, 163 {0x1086, 164 PWR_CV_MSK_ALL, 165 PWR_INTF_MSK_SDIO, 166 PWR_BASE_MAC, 167 PWR_CMD_WRITE, BIT(0), 0}, 168 {0x1086, 169 PWR_CV_MSK_ALL, 170 PWR_INTF_MSK_SDIO, 171 PWR_BASE_MAC, 172 PWR_CMD_POLL, BIT(1), BIT(1)}, 173 {0x0005, 174 PWR_CV_MSK_ALL, 175 PWR_INTF_MSK_ALL, 176 PWR_BASE_MAC, 177 PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, 178 {0x0005, 179 PWR_CV_MSK_ALL, 180 PWR_INTF_MSK_ALL, 181 PWR_BASE_MAC, 182 PWR_CMD_WRITE, BIT(7), 0}, 183 {0x0005, 184 PWR_CV_MSK_ALL, 185 PWR_INTF_MSK_ALL, 186 PWR_BASE_MAC, 187 PWR_CMD_WRITE, BIT(2), 0}, 188 {0x0006, 189 PWR_CV_MSK_ALL, 190 PWR_INTF_MSK_ALL, 191 PWR_BASE_MAC, 192 PWR_CMD_POLL, BIT(1), BIT(1)}, 193 {0x0006, 194 PWR_CV_MSK_ALL, 195 PWR_INTF_MSK_ALL, 196 PWR_BASE_MAC, 197 PWR_CMD_WRITE, BIT(0), BIT(0)}, 198 {0x0005, 199 PWR_CV_MSK_ALL, 200 PWR_INTF_MSK_ALL, 201 PWR_BASE_MAC, 202 PWR_CMD_WRITE, BIT(0), BIT(0)}, 203 {0x0005, 204 PWR_CV_MSK_ALL, 205 PWR_INTF_MSK_ALL, 206 PWR_BASE_MAC, 207 PWR_CMD_POLL, BIT(0), 0}, 208 {0x106D, 209 PWR_CV_MSK_B | PWR_CV_MSK_C, 210 PWR_INTF_MSK_USB, 211 PWR_BASE_MAC, 212 PWR_CMD_WRITE, BIT(6), 0}, 213 {0x0088, 214 PWR_CV_MSK_ALL, 215 PWR_INTF_MSK_ALL, 216 PWR_BASE_MAC, 217 PWR_CMD_WRITE, BIT(0), BIT(0)}, 218 {0x0088, 219 PWR_CV_MSK_ALL, 220 PWR_INTF_MSK_ALL, 221 PWR_BASE_MAC, 222 PWR_CMD_WRITE, BIT(0), 0}, 223 {0x0088, 224 PWR_CV_MSK_ALL, 225 PWR_INTF_MSK_ALL, 226 PWR_BASE_MAC, 227 PWR_CMD_WRITE, BIT(0), BIT(0)}, 228 {0x0088, 229 PWR_CV_MSK_ALL, 230 PWR_INTF_MSK_ALL, 231 PWR_BASE_MAC, 232 PWR_CMD_WRITE, BIT(0), 0}, 233 {0x0088, 234 PWR_CV_MSK_ALL, 235 PWR_INTF_MSK_ALL, 236 PWR_BASE_MAC, 237 PWR_CMD_WRITE, BIT(0), BIT(0)}, 238 {0x0083, 239 PWR_CV_MSK_ALL, 240 PWR_INTF_MSK_ALL, 241 PWR_BASE_MAC, 242 PWR_CMD_WRITE, BIT(6), 0}, 243 {0x0080, 244 PWR_CV_MSK_ALL, 245 PWR_INTF_MSK_ALL, 246 PWR_BASE_MAC, 247 PWR_CMD_WRITE, BIT(5), BIT(5)}, 248 {0x0024, 249 PWR_CV_MSK_ALL, 250 PWR_INTF_MSK_ALL, 251 PWR_BASE_MAC, 252 PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0}, 253 {0x02A0, 254 PWR_CV_MSK_ALL, 255 PWR_INTF_MSK_ALL, 256 PWR_BASE_MAC, 257 PWR_CMD_WRITE, BIT(1), BIT(1)}, 258 {0x02A2, 259 PWR_CV_MSK_ALL, 260 PWR_INTF_MSK_ALL, 261 PWR_BASE_MAC, 262 PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0}, 263 {0x0071, 264 PWR_CV_MSK_ALL, 265 PWR_INTF_MSK_PCIE, 266 PWR_BASE_MAC, 267 PWR_CMD_WRITE, BIT(4), 0}, 268 {0x0010, 269 PWR_CV_MSK_A, 270 PWR_INTF_MSK_PCIE, 271 PWR_BASE_MAC, 272 PWR_CMD_WRITE, BIT(2), BIT(2)}, 273 {0x02A0, 274 PWR_CV_MSK_A, 275 PWR_INTF_MSK_ALL, 276 PWR_BASE_MAC, 277 PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 278 {0xFFFF, 279 PWR_CV_MSK_ALL, 280 PWR_INTF_MSK_ALL, 281 0, 282 PWR_CMD_END, 0, 0}, 283 }; 284 285 static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = { 286 {0x02F0, 287 PWR_CV_MSK_ALL, 288 PWR_INTF_MSK_ALL, 289 PWR_BASE_MAC, 290 PWR_CMD_WRITE, 0xFF, 0}, 291 {0x02F1, 292 PWR_CV_MSK_ALL, 293 PWR_INTF_MSK_ALL, 294 PWR_BASE_MAC, 295 PWR_CMD_WRITE, 0xFF, 0}, 296 {0x0006, 297 PWR_CV_MSK_ALL, 298 PWR_INTF_MSK_ALL, 299 PWR_BASE_MAC, 300 PWR_CMD_WRITE, BIT(0), BIT(0)}, 301 {0x0002, 302 PWR_CV_MSK_ALL, 303 PWR_INTF_MSK_ALL, 304 PWR_BASE_MAC, 305 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 306 {0x0082, 307 PWR_CV_MSK_ALL, 308 PWR_INTF_MSK_ALL, 309 PWR_BASE_MAC, 310 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 311 {0x106D, 312 PWR_CV_MSK_B | PWR_CV_MSK_C, 313 PWR_INTF_MSK_USB, 314 PWR_BASE_MAC, 315 PWR_CMD_WRITE, BIT(6), BIT(6)}, 316 {0x0005, 317 PWR_CV_MSK_ALL, 318 PWR_INTF_MSK_ALL, 319 PWR_BASE_MAC, 320 PWR_CMD_WRITE, BIT(1), BIT(1)}, 321 {0x0005, 322 PWR_CV_MSK_ALL, 323 PWR_INTF_MSK_ALL, 324 PWR_BASE_MAC, 325 PWR_CMD_POLL, BIT(1), 0}, 326 {0x0091, 327 PWR_CV_MSK_ALL, 328 PWR_INTF_MSK_PCIE, 329 PWR_BASE_MAC, 330 PWR_CMD_WRITE, BIT(0), 0}, 331 {0x0005, 332 PWR_CV_MSK_ALL, 333 PWR_INTF_MSK_PCIE, 334 PWR_BASE_MAC, 335 PWR_CMD_WRITE, BIT(2), BIT(2)}, 336 {0x0007, 337 PWR_CV_MSK_ALL, 338 PWR_INTF_MSK_USB, 339 PWR_BASE_MAC, 340 PWR_CMD_WRITE, BIT(4), 0}, 341 {0x0007, 342 PWR_CV_MSK_ALL, 343 PWR_INTF_MSK_SDIO, 344 PWR_BASE_MAC, 345 PWR_CMD_WRITE, BIT(6) | BIT(4), 0}, 346 {0x0005, 347 PWR_CV_MSK_ALL, 348 PWR_INTF_MSK_SDIO, 349 PWR_BASE_MAC, 350 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 351 {0x0005, 352 PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F | 353 PWR_CV_MSK_G, 354 PWR_INTF_MSK_USB, 355 PWR_BASE_MAC, 356 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 357 {0x1086, 358 PWR_CV_MSK_ALL, 359 PWR_INTF_MSK_SDIO, 360 PWR_BASE_MAC, 361 PWR_CMD_WRITE, BIT(0), BIT(0)}, 362 {0x1086, 363 PWR_CV_MSK_ALL, 364 PWR_INTF_MSK_SDIO, 365 PWR_BASE_MAC, 366 PWR_CMD_POLL, BIT(1), 0}, 367 {0xFFFF, 368 PWR_CV_MSK_ALL, 369 PWR_INTF_MSK_ALL, 370 0, 371 PWR_CMD_END, 0, 0}, 372 }; 373 374 static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = { 375 rtw8852a_pwron, NULL 376 }; 377 378 static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = { 379 rtw8852a_pwroff, NULL 380 }; 381 382 static const u32 rtw8852a_h2c_regs[RTW89_H2CREG_MAX] = { 383 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2, 384 R_AX_H2CREG_DATA3 385 }; 386 387 static const u32 rtw8852a_c2h_regs[RTW89_C2HREG_MAX] = { 388 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2, 389 R_AX_C2HREG_DATA3 390 }; 391 392 static const struct rtw89_page_regs rtw8852a_page_regs = { 393 .hci_fc_ctrl = R_AX_HCI_FC_CTRL, 394 .ch_page_ctrl = R_AX_CH_PAGE_CTRL, 395 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL, 396 .ach_page_info = R_AX_ACH0_PAGE_INFO, 397 .pub_page_info3 = R_AX_PUB_PAGE_INFO3, 398 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1, 399 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2, 400 .pub_page_info1 = R_AX_PUB_PAGE_INFO1, 401 .pub_page_info2 = R_AX_PUB_PAGE_INFO2, 402 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1, 403 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2, 404 .wp_page_info1 = R_AX_WP_PAGE_INFO1, 405 }; 406 407 static const struct rtw89_reg_def rtw8852a_dcfo_comp = { 408 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK 409 }; 410 411 static const struct rtw89_imr_info rtw8852a_imr_info = { 412 .wdrls_imr_set = B_AX_WDRLS_IMR_SET, 413 .wsec_imr_reg = R_AX_SEC_DEBUG, 414 .wsec_imr_set = B_AX_IMR_ERROR, 415 .mpdu_tx_imr_set = 0, 416 .mpdu_rx_imr_set = 0, 417 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 418 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR, 419 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR, 420 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET, 421 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1, 422 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR, 423 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET, 424 .wde_imr_clr = B_AX_WDE_IMR_CLR, 425 .wde_imr_set = B_AX_WDE_IMR_SET, 426 .ple_imr_clr = B_AX_PLE_IMR_CLR, 427 .ple_imr_set = B_AX_PLE_IMR_SET, 428 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR, 429 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET, 430 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR, 431 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET, 432 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR, 433 .other_disp_imr_set = 0, 434 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR, 435 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR, 436 .bbrpt_err_imr_set = 0, 437 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR, 438 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR, 439 .ptcl_imr_set = B_AX_PTCL_IMR_SET, 440 .cdma_imr_0_reg = R_AX_DLE_CTRL, 441 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR, 442 .cdma_imr_0_set = B_AX_DLE_IMR_SET, 443 .cdma_imr_1_reg = 0, 444 .cdma_imr_1_clr = 0, 445 .cdma_imr_1_set = 0, 446 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR, 447 .phy_intf_imr_clr = 0, 448 .phy_intf_imr_set = 0, 449 .rmac_imr_reg = R_AX_RMAC_ERR_ISR, 450 .rmac_imr_clr = B_AX_RMAC_IMR_CLR, 451 .rmac_imr_set = B_AX_RMAC_IMR_SET, 452 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR, 453 .tmac_imr_clr = B_AX_TMAC_IMR_CLR, 454 .tmac_imr_set = B_AX_TMAC_IMR_SET, 455 }; 456 457 static const struct rtw89_rrsr_cfgs rtw8852a_rrsr_cfgs = { 458 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 459 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2}, 460 }; 461 462 static const struct rtw89_dig_regs rtw8852a_dig_regs = { 463 .seg0_pd_reg = R_SEG0R_PD, 464 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 465 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, 466 .p0_lna_init = {R_PATH0_LNA_INIT, B_PATH0_LNA_INIT_IDX_MSK}, 467 .p1_lna_init = {R_PATH1_LNA_INIT, B_PATH1_LNA_INIT_IDX_MSK}, 468 .p0_tia_init = {R_PATH0_TIA_INIT, B_PATH0_TIA_INIT_IDX_MSK}, 469 .p1_tia_init = {R_PATH1_TIA_INIT, B_PATH1_TIA_INIT_IDX_MSK}, 470 .p0_rxb_init = {R_PATH0_RXB_INIT, B_PATH0_RXB_INIT_IDX_MSK}, 471 .p1_rxb_init = {R_PATH1_RXB_INIT, B_PATH1_RXB_INIT_IDX_MSK}, 472 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC, 473 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 474 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC, 475 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 476 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC, 477 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 478 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC, 479 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 480 }; 481 482 static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse, 483 struct rtw8852a_efuse *map) 484 { 485 ether_addr_copy(efuse->addr, map->e.mac_addr); 486 efuse->rfe_type = map->rfe_type; 487 efuse->xtal_cap = map->xtal_k; 488 } 489 490 static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 491 struct rtw8852a_efuse *map) 492 { 493 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 494 struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 495 u8 i, j; 496 497 tssi->thermal[RF_PATH_A] = map->path_a_therm; 498 tssi->thermal[RF_PATH_B] = map->path_b_therm; 499 500 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 501 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 502 sizeof(ofst[i]->cck_tssi)); 503 504 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 505 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 506 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 507 i, j, tssi->tssi_cck[i][j]); 508 509 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 510 sizeof(ofst[i]->bw40_tssi)); 511 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 512 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 513 514 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 515 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 516 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 517 i, j, tssi->tssi_mcs[i][j]); 518 } 519 } 520 521 static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map) 522 { 523 struct rtw89_efuse *efuse = &rtwdev->efuse; 524 struct rtw8852a_efuse *map; 525 526 map = (struct rtw8852a_efuse *)log_map; 527 528 efuse->country_code[0] = map->country_code[0]; 529 efuse->country_code[1] = map->country_code[1]; 530 rtw8852a_efuse_parsing_tssi(rtwdev, map); 531 532 switch (rtwdev->hci.type) { 533 case RTW89_HCI_TYPE_PCIE: 534 rtw8852ae_efuse_parsing(efuse, map); 535 break; 536 default: 537 return -ENOTSUPP; 538 } 539 540 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 541 542 return 0; 543 } 544 545 static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 546 { 547 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 548 static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB}; 549 u32 addr = rtwdev->chip->phycap_addr; 550 bool pg = false; 551 u32 ofst; 552 u8 i, j; 553 554 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 555 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 556 /* addrs are in decreasing order */ 557 ofst = tssi_trim_addr[i] - addr - j; 558 tssi->tssi_trim[i][j] = phycap_map[ofst]; 559 560 if (phycap_map[ofst] != 0xff) 561 pg = true; 562 } 563 } 564 565 if (!pg) { 566 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 567 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 568 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 569 } 570 571 for (i = 0; i < RF_PATH_NUM_8852A; i++) 572 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 573 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 574 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 575 i, j, tssi->tssi_trim[i][j], 576 tssi_trim_addr[i] - j); 577 } 578 579 static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 580 u8 *phycap_map) 581 { 582 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 583 static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC}; 584 u32 addr = rtwdev->chip->phycap_addr; 585 u8 i; 586 587 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 588 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 589 590 rtw89_debug(rtwdev, RTW89_DBG_RFK, 591 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 592 i, info->thermal_trim[i]); 593 594 if (info->thermal_trim[i] != 0xff) 595 info->pg_thermal_trim = true; 596 } 597 } 598 599 static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev) 600 { 601 #define __thm_setting(raw) \ 602 ({ \ 603 u8 __v = (raw); \ 604 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 605 }) 606 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 607 u8 i, val; 608 609 if (!info->pg_thermal_trim) { 610 rtw89_debug(rtwdev, RTW89_DBG_RFK, 611 "[THERMAL][TRIM] no PG, do nothing\n"); 612 613 return; 614 } 615 616 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 617 val = __thm_setting(info->thermal_trim[i]); 618 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 619 620 rtw89_debug(rtwdev, RTW89_DBG_RFK, 621 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 622 i, val); 623 } 624 #undef __thm_setting 625 } 626 627 static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 628 u8 *phycap_map) 629 { 630 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 631 static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB}; 632 u32 addr = rtwdev->chip->phycap_addr; 633 u8 i; 634 635 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 636 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 637 638 rtw89_debug(rtwdev, RTW89_DBG_RFK, 639 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 640 i, info->pa_bias_trim[i]); 641 642 if (info->pa_bias_trim[i] != 0xff) 643 info->pg_pa_bias_trim = true; 644 } 645 } 646 647 static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev) 648 { 649 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 650 u8 pabias_2g, pabias_5g; 651 u8 i; 652 653 if (!info->pg_pa_bias_trim) { 654 rtw89_debug(rtwdev, RTW89_DBG_RFK, 655 "[PA_BIAS][TRIM] no PG, do nothing\n"); 656 657 return; 658 } 659 660 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 661 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 662 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 663 664 rtw89_debug(rtwdev, RTW89_DBG_RFK, 665 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 666 i, pabias_2g, pabias_5g); 667 668 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 669 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 670 } 671 } 672 673 static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 674 { 675 rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map); 676 rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map); 677 rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 678 679 return 0; 680 } 681 682 static void rtw8852a_power_trim(struct rtw89_dev *rtwdev) 683 { 684 rtw8852a_thermal_trim(rtwdev); 685 rtw8852a_pa_bias_trim(rtwdev); 686 } 687 688 static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev, 689 const struct rtw89_chan *chan, 690 u8 mac_idx) 691 { 692 u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx); 693 u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, 694 mac_idx); 695 u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx); 696 u8 txsc20 = 0, txsc40 = 0; 697 698 switch (chan->band_width) { 699 case RTW89_CHANNEL_WIDTH_80: 700 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, 701 RTW89_CHANNEL_WIDTH_40); 702 fallthrough; 703 case RTW89_CHANNEL_WIDTH_40: 704 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, 705 RTW89_CHANNEL_WIDTH_20); 706 break; 707 default: 708 break; 709 } 710 711 switch (chan->band_width) { 712 case RTW89_CHANNEL_WIDTH_80: 713 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); 714 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); 715 break; 716 case RTW89_CHANNEL_WIDTH_40: 717 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); 718 rtw89_write32(rtwdev, sub_carr, txsc20); 719 break; 720 case RTW89_CHANNEL_WIDTH_20: 721 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); 722 rtw89_write32(rtwdev, sub_carr, 0); 723 break; 724 default: 725 break; 726 } 727 728 if (chan->channel > 14) 729 rtw89_write8_set(rtwdev, chk_rate, 730 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 731 else 732 rtw89_write8_clr(rtwdev, chk_rate, 733 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 734 } 735 736 static const u32 rtw8852a_sco_barker_threshold[14] = { 737 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, 738 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 739 }; 740 741 static const u32 rtw8852a_sco_cck_threshold[14] = { 742 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, 743 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed 744 }; 745 746 static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 747 u8 primary_ch, enum rtw89_bandwidth bw) 748 { 749 u8 ch_element; 750 751 if (bw == RTW89_CHANNEL_WIDTH_20) { 752 ch_element = central_ch - 1; 753 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 754 if (primary_ch == 1) 755 ch_element = central_ch - 1 + 2; 756 else 757 ch_element = central_ch - 1 - 2; 758 } else { 759 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 760 return -EINVAL; 761 } 762 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, 763 rtw8852a_sco_barker_threshold[ch_element]); 764 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, 765 rtw8852a_sco_cck_threshold[ch_element]); 766 767 return 0; 768 } 769 770 static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch, 771 u8 path) 772 { 773 u32 val; 774 775 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 776 if (val == INV_RF_DATA) { 777 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 778 return; 779 } 780 val &= ~0x303ff; 781 val |= central_ch; 782 if (central_ch > 14) 783 val |= (BIT(16) | BIT(8)); 784 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 785 } 786 787 static u8 rtw8852a_sco_mapping(u8 central_ch) 788 { 789 if (central_ch == 1) 790 return 109; 791 else if (central_ch >= 2 && central_ch <= 6) 792 return 108; 793 else if (central_ch >= 7 && central_ch <= 10) 794 return 107; 795 else if (central_ch >= 11 && central_ch <= 14) 796 return 106; 797 else if (central_ch == 36 || central_ch == 38) 798 return 51; 799 else if (central_ch >= 40 && central_ch <= 58) 800 return 50; 801 else if (central_ch >= 60 && central_ch <= 64) 802 return 49; 803 else if (central_ch == 100 || central_ch == 102) 804 return 48; 805 else if (central_ch >= 104 && central_ch <= 126) 806 return 47; 807 else if (central_ch >= 128 && central_ch <= 151) 808 return 46; 809 else if (central_ch >= 153 && central_ch <= 177) 810 return 45; 811 else 812 return 0; 813 } 814 815 static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch, 816 enum rtw89_phy_idx phy_idx) 817 { 818 u8 sco_comp; 819 bool is_2g = central_ch <= 14; 820 821 if (phy_idx == RTW89_PHY_0) { 822 /* Path A */ 823 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A); 824 if (is_2g) 825 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 826 B_PATH0_TIA_ERR_G1_SEL, 1, 827 phy_idx); 828 else 829 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 830 B_PATH0_TIA_ERR_G1_SEL, 0, 831 phy_idx); 832 833 /* Path B */ 834 if (!rtwdev->dbcc_en) { 835 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 836 if (is_2g) 837 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 838 B_P1_MODE_SEL, 839 1, phy_idx); 840 else 841 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 842 B_P1_MODE_SEL, 843 0, phy_idx); 844 } else { 845 if (is_2g) 846 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, 847 B_2P4G_BAND_SEL); 848 else 849 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, 850 B_2P4G_BAND_SEL); 851 } 852 /* SCO compensate FC setting */ 853 sco_comp = rtw8852a_sco_mapping(central_ch); 854 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 855 sco_comp, phy_idx); 856 } else { 857 /* Path B */ 858 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 859 if (is_2g) 860 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 861 B_P1_MODE_SEL, 862 1, phy_idx); 863 else 864 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 865 B_P1_MODE_SEL, 866 0, phy_idx); 867 /* SCO compensate FC setting */ 868 sco_comp = rtw8852a_sco_mapping(central_ch); 869 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 870 sco_comp, phy_idx); 871 } 872 873 /* Band edge */ 874 if (is_2g) 875 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1, 876 phy_idx); 877 else 878 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0, 879 phy_idx); 880 881 /* CCK parameters */ 882 if (central_ch == 14) { 883 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 884 0x3b13ff); 885 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 886 0x1c42de); 887 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 888 0xfdb0ad); 889 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 890 0xf60f6e); 891 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 892 0xfd8f92); 893 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); 894 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); 895 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 896 0xfff00a); 897 } else { 898 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 899 0x3d23ff); 900 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 901 0x29b354); 902 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); 903 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 904 0xfdb053); 905 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 906 0xf86f9a); 907 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 908 0xfaef92); 909 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 910 0xfe5fcc); 911 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 912 0xffdff5); 913 } 914 } 915 916 static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 917 { 918 u32 val = 0; 919 u32 adc_sel[2] = {0x12d0, 0x32d0}; 920 u32 wbadc_sel[2] = {0x12ec, 0x32ec}; 921 922 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 923 if (val == INV_RF_DATA) { 924 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 925 return; 926 } 927 val &= ~(BIT(11) | BIT(10)); 928 switch (bw) { 929 case RTW89_CHANNEL_WIDTH_5: 930 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 931 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 932 val |= (BIT(11) | BIT(10)); 933 break; 934 case RTW89_CHANNEL_WIDTH_10: 935 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 936 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 937 val |= (BIT(11) | BIT(10)); 938 break; 939 case RTW89_CHANNEL_WIDTH_20: 940 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 941 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 942 val |= (BIT(11) | BIT(10)); 943 break; 944 case RTW89_CHANNEL_WIDTH_40: 945 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 946 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 947 val |= BIT(11); 948 break; 949 case RTW89_CHANNEL_WIDTH_80: 950 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 951 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 952 val |= BIT(10); 953 break; 954 default: 955 rtw89_warn(rtwdev, "Fail to set ADC\n"); 956 } 957 958 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 959 } 960 961 static void 962 rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 963 enum rtw89_phy_idx phy_idx) 964 { 965 /* Switch bandwidth */ 966 switch (bw) { 967 case RTW89_CHANNEL_WIDTH_5: 968 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 969 phy_idx); 970 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1, 971 phy_idx); 972 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 973 0x0, phy_idx); 974 break; 975 case RTW89_CHANNEL_WIDTH_10: 976 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 977 phy_idx); 978 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2, 979 phy_idx); 980 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 981 0x0, phy_idx); 982 break; 983 case RTW89_CHANNEL_WIDTH_20: 984 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 985 phy_idx); 986 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 987 phy_idx); 988 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 989 0x0, phy_idx); 990 break; 991 case RTW89_CHANNEL_WIDTH_40: 992 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 993 phy_idx); 994 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 995 phy_idx); 996 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 997 pri_ch, 998 phy_idx); 999 if (pri_ch == RTW89_SC_20_UPPER) 1000 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); 1001 else 1002 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); 1003 break; 1004 case RTW89_CHANNEL_WIDTH_80: 1005 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 1006 phy_idx); 1007 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1008 phy_idx); 1009 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1010 pri_ch, 1011 phy_idx); 1012 break; 1013 default: 1014 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1015 pri_ch); 1016 } 1017 1018 if (phy_idx == RTW89_PHY_0) { 1019 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A); 1020 if (!rtwdev->dbcc_en) 1021 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 1022 } else { 1023 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 1024 } 1025 } 1026 1027 static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch) 1028 { 1029 if (central_ch == 153) { 1030 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1031 0x210); 1032 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1033 0x210); 1034 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x7c0); 1035 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1036 B_P0_NBIIDX_NOTCH_EN, 0x1); 1037 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1038 B_P1_NBIIDX_NOTCH_EN, 0x1); 1039 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1040 0x1); 1041 } else if (central_ch == 151) { 1042 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1043 0x210); 1044 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1045 0x210); 1046 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x40); 1047 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1048 B_P0_NBIIDX_NOTCH_EN, 0x1); 1049 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1050 B_P1_NBIIDX_NOTCH_EN, 0x1); 1051 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1052 0x1); 1053 } else if (central_ch == 155) { 1054 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1055 0x2d0); 1056 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1057 0x2d0); 1058 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, 0xfff, 0x740); 1059 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1060 B_P0_NBIIDX_NOTCH_EN, 0x1); 1061 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1062 B_P1_NBIIDX_NOTCH_EN, 0x1); 1063 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1064 0x1); 1065 } else { 1066 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1067 B_P0_NBIIDX_NOTCH_EN, 0x0); 1068 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1069 B_P1_NBIIDX_NOTCH_EN, 0x0); 1070 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1071 0x0); 1072 } 1073 } 1074 1075 static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev, 1076 enum rtw89_phy_idx phy_idx) 1077 { 1078 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1079 phy_idx); 1080 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1081 phy_idx); 1082 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1083 phy_idx); 1084 } 1085 1086 static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev, 1087 enum rtw89_phy_idx phy_idx, bool en) 1088 { 1089 if (en) 1090 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1091 1, 1092 phy_idx); 1093 else 1094 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1095 0, 1096 phy_idx); 1097 } 1098 1099 static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev, 1100 enum rtw89_phy_idx phy_idx) 1101 { 1102 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1103 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1104 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1105 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1106 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1107 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1108 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1109 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1110 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1111 } 1112 1113 static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1114 enum rtw89_phy_idx phy_idx) 1115 { 1116 u32 addr; 1117 1118 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1119 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1120 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1121 } 1122 1123 static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev) 1124 { 1125 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); 1126 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP); 1127 1128 if (rtwdev->hal.cv <= CHIP_CCV) { 1129 rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG); 1130 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000); 1131 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x43F); 1132 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF); 1133 rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST); 1134 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1135 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1136 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, B_STS_PARSING_TIME); 1137 } 1138 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f); 1139 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c); 1140 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); 1141 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1); 1142 rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK); 1143 rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK); 1144 1145 rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1146 } 1147 1148 static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev, 1149 enum rtw89_phy_idx phy_idx) 1150 { 1151 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1152 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1153 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1154 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1155 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1156 udelay(1); 1157 } 1158 1159 static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev, 1160 const struct rtw89_chan *chan, 1161 enum rtw89_phy_idx phy_idx) 1162 { 1163 bool cck_en = chan->channel <= 14; 1164 u8 pri_ch_idx = chan->pri_ch_idx; 1165 1166 if (cck_en) 1167 rtw8852a_ctrl_sco_cck(rtwdev, chan->channel, 1168 chan->primary_channel, 1169 chan->band_width); 1170 1171 rtw8852a_ctrl_ch(rtwdev, chan->channel, phy_idx); 1172 rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1173 if (cck_en) { 1174 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); 1175 } else { 1176 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); 1177 rtw8852a_bbrst_for_rfk(rtwdev, phy_idx); 1178 } 1179 rtw8852a_spur_elimination(rtwdev, chan->channel); 1180 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, 1181 chan->primary_channel); 1182 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1183 } 1184 1185 static void rtw8852a_set_channel(struct rtw89_dev *rtwdev, 1186 const struct rtw89_chan *chan, 1187 enum rtw89_mac_idx mac_idx, 1188 enum rtw89_phy_idx phy_idx) 1189 { 1190 rtw8852a_set_channel_mac(rtwdev, chan, mac_idx); 1191 rtw8852a_set_channel_bb(rtwdev, chan, phy_idx); 1192 } 1193 1194 static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en) 1195 { 1196 if (en) 1197 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1198 else 1199 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1200 } 1201 1202 static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 1203 enum rtw89_rf_path path) 1204 { 1205 static const u32 tssi_trk[2] = {0x5818, 0x7818}; 1206 static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc}; 1207 1208 if (en) { 1209 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0); 1210 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0); 1211 } else { 1212 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1); 1213 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1); 1214 } 1215 } 1216 1217 static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, 1218 u8 phy_idx) 1219 { 1220 if (!rtwdev->dbcc_en) { 1221 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1222 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1223 } else { 1224 if (phy_idx == RTW89_PHY_0) 1225 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1226 else 1227 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1228 } 1229 } 1230 1231 static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en) 1232 { 1233 if (en) 1234 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1235 0x0); 1236 else 1237 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1238 0xf); 1239 } 1240 1241 static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1242 struct rtw89_channel_help_params *p, 1243 const struct rtw89_chan *chan, 1244 enum rtw89_mac_idx mac_idx, 1245 enum rtw89_phy_idx phy_idx) 1246 { 1247 if (enter) { 1248 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en, 1249 RTW89_SCH_TX_SEL_ALL); 1250 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false); 1251 rtw8852a_dfs_en(rtwdev, false); 1252 rtw8852a_tssi_cont_en_phyidx(rtwdev, false, phy_idx); 1253 rtw8852a_adc_en(rtwdev, false); 1254 fsleep(40); 1255 rtw8852a_bb_reset_en(rtwdev, phy_idx, false); 1256 } else { 1257 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true); 1258 rtw8852a_adc_en(rtwdev, true); 1259 rtw8852a_dfs_en(rtwdev, true); 1260 rtw8852a_tssi_cont_en_phyidx(rtwdev, true, phy_idx); 1261 rtw8852a_bb_reset_en(rtwdev, phy_idx, true); 1262 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en); 1263 } 1264 } 1265 1266 static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev) 1267 { 1268 struct rtw89_efuse *efuse = &rtwdev->efuse; 1269 1270 switch (efuse->rfe_type) { 1271 case 11: 1272 case 12: 1273 case 17: 1274 case 18: 1275 case 51: 1276 case 53: 1277 rtwdev->fem.epa_2g = true; 1278 rtwdev->fem.elna_2g = true; 1279 fallthrough; 1280 case 9: 1281 case 10: 1282 case 15: 1283 case 16: 1284 rtwdev->fem.epa_5g = true; 1285 rtwdev->fem.elna_5g = true; 1286 break; 1287 default: 1288 break; 1289 } 1290 } 1291 1292 static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev) 1293 { 1294 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1295 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1296 1297 rtw8852a_rck(rtwdev); 1298 rtw8852a_dack(rtwdev); 1299 rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true); 1300 } 1301 1302 static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev) 1303 { 1304 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 1305 1306 rtw8852a_rx_dck(rtwdev, phy_idx, true); 1307 rtw8852a_iqk(rtwdev, phy_idx); 1308 rtw8852a_tssi(rtwdev, phy_idx); 1309 rtw8852a_dpk(rtwdev, phy_idx); 1310 } 1311 1312 static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev, 1313 enum rtw89_phy_idx phy_idx) 1314 { 1315 rtw8852a_tssi_scan(rtwdev, phy_idx); 1316 } 1317 1318 static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, bool start) 1319 { 1320 rtw8852a_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); 1321 } 1322 1323 static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev) 1324 { 1325 rtw8852a_dpk_track(rtwdev); 1326 rtw8852a_iqk_track(rtwdev); 1327 rtw8852a_tssi_track(rtwdev); 1328 } 1329 1330 static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1331 enum rtw89_phy_idx phy_idx, s16 ref) 1332 { 1333 s8 ofst_int = 0; 1334 u8 base_cw_0db = 0x27; 1335 u16 tssi_16dbm_cw = 0x12c; 1336 s16 pwr_s10_3 = 0; 1337 s16 rf_pwr_cw = 0; 1338 u16 bb_pwr_cw = 0; 1339 u32 pwr_cw = 0; 1340 u32 tssi_ofst_cw = 0; 1341 1342 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1343 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1344 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1345 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1346 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1347 1348 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1349 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1350 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1351 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1352 1353 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1354 } 1355 1356 static 1357 void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1358 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1359 { 1360 s8 val_1t = 0; 1361 s8 val_2t = 0; 1362 u32 reg; 1363 1364 if (pw_ofst < -16 || pw_ofst > 15) { 1365 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n", 1366 pw_ofst); 1367 return; 1368 } 1369 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx); 1370 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); 1371 val_1t = pw_ofst; 1372 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx); 1373 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t); 1374 val_2t = max(val_1t - 3, -16); 1375 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx); 1376 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t); 1377 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n", 1378 val_1t, val_2t); 1379 } 1380 1381 static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev, 1382 enum rtw89_phy_idx phy_idx) 1383 { 1384 static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800}; 1385 const u32 mask = 0x7FFFFFF; 1386 const u8 ofst_ofdm = 0x4; 1387 const u8 ofst_cck = 0x8; 1388 s16 ref_ofdm = 0; 1389 s16 ref_cck = 0; 1390 u32 val; 1391 u8 i; 1392 1393 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1394 1395 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1396 GENMASK(27, 10), 0x0); 1397 1398 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1399 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1400 1401 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1402 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1403 phy_idx); 1404 1405 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1406 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1407 1408 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1409 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1410 phy_idx); 1411 } 1412 1413 static void rtw8852a_set_txpwr_byrate(struct rtw89_dev *rtwdev, 1414 const struct rtw89_chan *chan, 1415 enum rtw89_phy_idx phy_idx) 1416 { 1417 u8 band = chan->band_type; 1418 u8 ch = chan->channel; 1419 static const u8 rs[] = { 1420 RTW89_RS_CCK, 1421 RTW89_RS_OFDM, 1422 RTW89_RS_MCS, 1423 RTW89_RS_HEDCM, 1424 }; 1425 s8 tmp; 1426 u8 i, j; 1427 u32 val, shf, addr = R_AX_PWR_BY_RATE; 1428 struct rtw89_rate_desc cur; 1429 1430 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1431 "[TXPWR] set txpwr byrate with ch=%d\n", ch); 1432 1433 for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) { 1434 for (i = 0; i < ARRAY_SIZE(rs); i++) { 1435 if (cur.nss >= rtw89_rs_nss_max[rs[i]]) 1436 continue; 1437 1438 val = 0; 1439 cur.rs = rs[i]; 1440 1441 for (j = 0; j < rtw89_rs_idx_max[rs[i]]; j++) { 1442 cur.idx = j; 1443 shf = (j % 4) * 8; 1444 tmp = rtw89_phy_read_txpwr_byrate(rtwdev, band, 1445 &cur); 1446 val |= (tmp << shf); 1447 1448 if ((j + 1) % 4) 1449 continue; 1450 1451 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 1452 val = 0; 1453 addr += 4; 1454 } 1455 } 1456 } 1457 } 1458 1459 static void rtw8852a_set_txpwr_offset(struct rtw89_dev *rtwdev, 1460 const struct rtw89_chan *chan, 1461 enum rtw89_phy_idx phy_idx) 1462 { 1463 u8 band = chan->band_type; 1464 struct rtw89_rate_desc desc = { 1465 .nss = RTW89_NSS_1, 1466 .rs = RTW89_RS_OFFSET, 1467 }; 1468 u32 val = 0; 1469 s8 v; 1470 1471 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n"); 1472 1473 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++) { 1474 v = rtw89_phy_read_txpwr_byrate(rtwdev, band, &desc); 1475 val |= ((v & 0xf) << (4 * desc.idx)); 1476 } 1477 1478 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL, 1479 GENMASK(19, 0), val); 1480 } 1481 1482 static void rtw8852a_set_txpwr_limit(struct rtw89_dev *rtwdev, 1483 const struct rtw89_chan *chan, 1484 enum rtw89_phy_idx phy_idx) 1485 { 1486 #define __MAC_TXPWR_LMT_PAGE_SIZE 40 1487 u8 ch = chan->channel; 1488 u8 bw = chan->band_width; 1489 struct rtw89_txpwr_limit lmt[NTX_NUM_8852A]; 1490 u32 addr, val; 1491 const s8 *ptr; 1492 u8 i, j; 1493 1494 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1495 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw); 1496 1497 for (i = 0; i < NTX_NUM_8852A; i++) { 1498 rtw89_phy_fill_txpwr_limit(rtwdev, chan, &lmt[i], i); 1499 1500 for (j = 0; j < __MAC_TXPWR_LMT_PAGE_SIZE; j += 4) { 1501 addr = R_AX_PWR_LMT + j + __MAC_TXPWR_LMT_PAGE_SIZE * i; 1502 ptr = (s8 *)&lmt[i] + j; 1503 1504 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 1505 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 1506 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 1507 FIELD_PREP(GENMASK(31, 24), ptr[3]); 1508 1509 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 1510 } 1511 } 1512 #undef __MAC_TXPWR_LMT_PAGE_SIZE 1513 } 1514 1515 static void rtw8852a_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, 1516 const struct rtw89_chan *chan, 1517 enum rtw89_phy_idx phy_idx) 1518 { 1519 #define __MAC_TXPWR_LMT_RU_PAGE_SIZE 24 1520 u8 ch = chan->channel; 1521 u8 bw = chan->band_width; 1522 struct rtw89_txpwr_limit_ru lmt_ru[NTX_NUM_8852A]; 1523 u32 addr, val; 1524 const s8 *ptr; 1525 u8 i, j; 1526 1527 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1528 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); 1529 1530 for (i = 0; i < NTX_NUM_8852A; i++) { 1531 rtw89_phy_fill_txpwr_limit_ru(rtwdev, chan, &lmt_ru[i], i); 1532 1533 for (j = 0; j < __MAC_TXPWR_LMT_RU_PAGE_SIZE; j += 4) { 1534 addr = R_AX_PWR_RU_LMT + j + 1535 __MAC_TXPWR_LMT_RU_PAGE_SIZE * i; 1536 ptr = (s8 *)&lmt_ru[i] + j; 1537 1538 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 1539 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 1540 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 1541 FIELD_PREP(GENMASK(31, 24), ptr[3]); 1542 1543 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 1544 } 1545 } 1546 1547 #undef __MAC_TXPWR_LMT_RU_PAGE_SIZE 1548 } 1549 1550 static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev, 1551 const struct rtw89_chan *chan, 1552 enum rtw89_phy_idx phy_idx) 1553 { 1554 rtw8852a_set_txpwr_byrate(rtwdev, chan, phy_idx); 1555 rtw8852a_set_txpwr_offset(rtwdev, chan, phy_idx); 1556 rtw8852a_set_txpwr_limit(rtwdev, chan, phy_idx); 1557 rtw8852a_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 1558 } 1559 1560 static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 1561 enum rtw89_phy_idx phy_idx) 1562 { 1563 rtw8852a_set_txpwr_ref(rtwdev, phy_idx); 1564 } 1565 1566 static int 1567 rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1568 { 1569 int ret; 1570 1571 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 1572 if (ret) 1573 return ret; 1574 1575 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004); 1576 if (ret) 1577 return ret; 1578 1579 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 1580 if (ret) 1581 return ret; 1582 1583 return 0; 1584 } 1585 1586 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev) 1587 { 1588 u8 i = 0; 1589 u32 addr, val; 1590 1591 for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) { 1592 addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr; 1593 val = rtw8852a_pmac_ht20_mcs7_tbl[i].data; 1594 rtw89_phy_write32(rtwdev, addr, val); 1595 } 1596 } 1597 1598 static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev, 1599 struct rtw8852a_bb_pmac_info *tx_info, 1600 enum rtw89_phy_idx idx) 1601 { 1602 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx"); 1603 if (tx_info->mode == CONT_TX) 1604 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, 1605 idx); 1606 else if (tx_info->mode == PKTS_TX) 1607 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, 1608 idx); 1609 } 1610 1611 static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev, 1612 struct rtw8852a_bb_pmac_info *tx_info, 1613 enum rtw89_phy_idx idx) 1614 { 1615 enum rtw8852a_pmac_mode mode = tx_info->mode; 1616 u32 pkt_cnt = tx_info->tx_cnt; 1617 u16 period = tx_info->period; 1618 1619 if (mode == CONT_TX && !tx_info->is_cck) { 1620 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, 1621 idx); 1622 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start"); 1623 } else if (mode == PKTS_TX) { 1624 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, 1625 idx); 1626 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, 1627 B_PMAC_TX_PRD_MSK, period, idx); 1628 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK, 1629 pkt_cnt, idx); 1630 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start"); 1631 } 1632 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx); 1633 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx); 1634 } 1635 1636 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev, 1637 struct rtw8852a_bb_pmac_info *tx_info, 1638 enum rtw89_phy_idx idx) 1639 { 1640 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 1641 1642 if (!tx_info->en_pmac_tx) { 1643 rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx); 1644 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx); 1645 if (chan->band_type == RTW89_BAND_2G) 1646 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS); 1647 return; 1648 } 1649 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable"); 1650 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx); 1651 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx); 1652 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, 1653 idx); 1654 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx); 1655 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx); 1656 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); 1657 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx); 1658 rtw8852a_start_pmac_tx(rtwdev, tx_info, idx); 1659 } 1660 1661 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, 1662 u16 tx_cnt, u16 period, u16 tx_time, 1663 enum rtw89_phy_idx idx) 1664 { 1665 struct rtw8852a_bb_pmac_info tx_info = {0}; 1666 1667 tx_info.en_pmac_tx = enable; 1668 tx_info.is_cck = 0; 1669 tx_info.mode = PKTS_TX; 1670 tx_info.tx_cnt = tx_cnt; 1671 tx_info.period = period; 1672 tx_info.tx_time = tx_time; 1673 rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx); 1674 } 1675 1676 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, 1677 enum rtw89_phy_idx idx) 1678 { 1679 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm); 1680 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); 1681 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx); 1682 } 1683 1684 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) 1685 { 1686 u32 rst_mask0 = 0; 1687 u32 rst_mask1 = 0; 1688 1689 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0); 1690 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1); 1691 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path); 1692 if (!rtwdev->dbcc_en) { 1693 if (tx_path == RF_PATH_A) { 1694 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1695 B_TXPATH_SEL_MSK, 1); 1696 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1697 B_TXNSS_MAP_MSK, 0); 1698 } else if (tx_path == RF_PATH_B) { 1699 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1700 B_TXPATH_SEL_MSK, 2); 1701 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1702 B_TXNSS_MAP_MSK, 0); 1703 } else if (tx_path == RF_PATH_AB) { 1704 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1705 B_TXPATH_SEL_MSK, 3); 1706 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1707 B_TXNSS_MAP_MSK, 4); 1708 } else { 1709 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path"); 1710 } 1711 } else { 1712 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1713 1); 1714 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2, 1715 RTW89_PHY_1); 1716 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 1717 0); 1718 rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4, 1719 RTW89_PHY_1); 1720 } 1721 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 1722 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 1723 if (tx_path == RF_PATH_A) { 1724 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 1725 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 1726 } else { 1727 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 1728 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 1729 } 1730 } 1731 1732 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev, 1733 enum rtw89_phy_idx idx, u8 mode) 1734 { 1735 if (mode != 0) 1736 return; 1737 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch"); 1738 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx); 1739 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx); 1740 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx); 1741 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx); 1742 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx); 1743 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx); 1744 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx); 1745 } 1746 1747 static void rtw8852a_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en) 1748 { 1749 rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8852a_btc_preagc_en_defs_tbl : 1750 &rtw8852a_btc_preagc_dis_defs_tbl); 1751 } 1752 1753 static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 1754 { 1755 if (rtwdev->is_tssi_mode[rf_path]) { 1756 u32 addr = 0x1c10 + (rf_path << 13); 1757 1758 return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000); 1759 } 1760 1761 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1762 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 1763 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1764 1765 fsleep(200); 1766 1767 return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 1768 } 1769 1770 static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev) 1771 { 1772 struct rtw89_btc *btc = &rtwdev->btc; 1773 struct rtw89_btc_module *module = &btc->mdinfo; 1774 1775 module->rfe_type = rtwdev->efuse.rfe_type; 1776 module->cv = rtwdev->hal.cv; 1777 module->bt_solo = 0; 1778 module->switch_type = BTC_SWITCH_INTERNAL; 1779 1780 if (module->rfe_type > 0) 1781 module->ant.num = (module->rfe_type % 2 ? 2 : 3); 1782 else 1783 module->ant.num = 2; 1784 1785 module->ant.diversity = 0; 1786 module->ant.isolation = 10; 1787 1788 if (module->ant.num == 3) { 1789 module->ant.type = BTC_ANT_DEDICATED; 1790 module->bt_pos = BTC_BT_ALONE; 1791 } else { 1792 module->ant.type = BTC_ANT_SHARED; 1793 module->bt_pos = BTC_BT_BTG; 1794 } 1795 } 1796 1797 static 1798 void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 1799 { 1800 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000); 1801 rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group); 1802 rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val); 1803 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0); 1804 } 1805 1806 static void rtw8852a_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 1807 { 1808 if (btg) { 1809 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1); 1810 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3); 1811 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 1812 } else { 1813 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0); 1814 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0); 1815 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 1816 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 1817 } 1818 } 1819 1820 static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev) 1821 { 1822 struct rtw89_btc *btc = &rtwdev->btc; 1823 struct rtw89_btc_module *module = &btc->mdinfo; 1824 const struct rtw89_chip_info *chip = rtwdev->chip; 1825 const struct rtw89_mac_ax_coex coex_params = { 1826 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 1827 .direction = RTW89_MAC_AX_COEX_INNER, 1828 }; 1829 1830 /* PTA init */ 1831 rtw89_mac_coex_init(rtwdev, &coex_params); 1832 1833 /* set WL Tx response = Hi-Pri */ 1834 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 1835 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 1836 1837 /* set rf gnt debug off */ 1838 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0); 1839 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0); 1840 1841 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 1842 if (module->ant.type == BTC_ANT_SHARED) { 1843 rtw8852a_set_trx_mask(rtwdev, 1844 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 1845 rtw8852a_set_trx_mask(rtwdev, 1846 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 1847 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 1848 rtw8852a_set_trx_mask(rtwdev, 1849 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 1850 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 1851 rtw8852a_set_trx_mask(rtwdev, 1852 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 1853 rtw8852a_set_trx_mask(rtwdev, 1854 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 1855 } 1856 1857 /* set PTA break table */ 1858 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); 1859 1860 /* enable BT counter 0xda40[16,2] = 2b'11 */ 1861 rtw89_write32_set(rtwdev, 1862 R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); 1863 btc->cx.wl.status.map.init_ok = true; 1864 } 1865 1866 static 1867 void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 1868 { 1869 u32 bitmap = 0; 1870 u32 reg = 0; 1871 1872 switch (map) { 1873 case BTC_PRI_MASK_TX_RESP: 1874 reg = R_BTC_BT_COEX_MSK_TABLE; 1875 bitmap = B_BTC_PRI_MASK_TX_RESP_V1; 1876 break; 1877 case BTC_PRI_MASK_BEACON: 1878 reg = R_AX_WL_PRI_MSK; 1879 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; 1880 break; 1881 default: 1882 return; 1883 } 1884 1885 if (state) 1886 rtw89_write32_set(rtwdev, reg, bitmap); 1887 else 1888 rtw89_write32_clr(rtwdev, reg, bitmap); 1889 } 1890 1891 static inline u32 __btc_ctrl_val_all_time(u32 ctrl) 1892 { 1893 return FIELD_GET(GENMASK(15, 0), ctrl); 1894 } 1895 1896 static inline u32 __btc_ctrl_rst_all_time(u32 cur) 1897 { 1898 return cur & ~B_AX_FORCE_PWR_BY_RATE_EN; 1899 } 1900 1901 static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val) 1902 { 1903 u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1904 u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1905 1906 return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN; 1907 } 1908 1909 static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl) 1910 { 1911 return FIELD_GET(GENMASK(31, 16), ctrl); 1912 } 1913 1914 static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur) 1915 { 1916 return cur & ~B_AX_TXAGC_BT_EN; 1917 } 1918 1919 static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val) 1920 { 1921 u32 ov = cur & ~B_AX_TXAGC_BT_MASK; 1922 u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val); 1923 1924 return ov | iv | B_AX_TXAGC_BT_EN; 1925 } 1926 1927 static void 1928 rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 1929 { 1930 const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL; 1931 const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL; 1932 1933 #define __do_clr(_chk) ((_chk) == GENMASK(15, 0)) 1934 #define __handle(_case) \ 1935 do { \ 1936 const u32 _reg = __btc_cr_ ## _case; \ 1937 u32 _val = __btc_ctrl_val_ ## _case(txpwr_val); \ 1938 u32 _cur, _wrt; \ 1939 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1940 "btc ctrl %s: 0x%x\n", #_case, _val); \ 1941 if (rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur))\ 1942 break; \ 1943 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1944 "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur); \ 1945 _wrt = __do_clr(_val) ? \ 1946 __btc_ctrl_rst_ ## _case(_cur) : \ 1947 __btc_ctrl_gen_ ## _case(_cur, _val); \ 1948 rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\ 1949 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1950 "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt); \ 1951 } while (0) 1952 1953 __handle(all_time); 1954 __handle(gnt_bt); 1955 1956 #undef __handle 1957 #undef __do_clr 1958 } 1959 1960 static 1961 s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 1962 { 1963 return clamp_t(s8, val, -100, 0) + 100; 1964 } 1965 1966 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = { 1967 {255, 0, 0, 7}, /* 0 -> original */ 1968 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 1969 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1970 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1971 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1972 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1973 {6, 1, 0, 7}, 1974 {13, 1, 0, 7}, 1975 {13, 1, 0, 7} 1976 }; 1977 1978 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = { 1979 {255, 0, 0, 7}, /* 0 -> original */ 1980 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 1981 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1982 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1983 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1984 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1985 {255, 1, 0, 7}, 1986 {255, 1, 0, 7}, 1987 {255, 1, 0, 7} 1988 }; 1989 1990 static const 1991 u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 1992 static const 1993 u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 1994 1995 static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = { 1996 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 1997 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), 1998 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), 1999 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 2000 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 2001 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), 2002 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), 2003 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 2004 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), 2005 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), 2006 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 2007 RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178), 2008 }; 2009 2010 static 2011 void rtw8852a_btc_bt_aci_imp(struct rtw89_dev *rtwdev) 2012 { 2013 struct rtw89_btc *btc = &rtwdev->btc; 2014 struct rtw89_btc_dm *dm = &btc->dm; 2015 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 2016 struct rtw89_btc_bt_link_info *b = &bt->link_info; 2017 2018 /* fix LNA2 = level-5 for BT ACI issue at BTG */ 2019 if (btc->dm.wl_btg_rx && b->profile_cnt.now != 0) 2020 dm->trx_para_level = 1; 2021 } 2022 2023 static 2024 void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 2025 { 2026 struct rtw89_btc *btc = &rtwdev->btc; 2027 struct rtw89_btc_cx *cx = &btc->cx; 2028 u32 val; 2029 2030 val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH); 2031 cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val); 2032 cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val); 2033 2034 val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW); 2035 cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val); 2036 cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val); 2037 2038 /* clock-gate off before reset counter*/ 2039 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 2040 rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 2041 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 2042 rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 2043 } 2044 2045 static 2046 void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 2047 { 2048 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 2049 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2050 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1); 2051 2052 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 2053 if (state) 2054 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2055 RFREG_MASK, 0xa2d7c); 2056 else 2057 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2058 RFREG_MASK, 0xa2020); 2059 2060 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2061 } 2062 2063 static void rtw8852a_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 2064 { 2065 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB 2066 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB 2067 * To improve BT ACI in co-rx 2068 */ 2069 2070 switch (level) { 2071 case 0: /* default */ 2072 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2073 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2074 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2075 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2076 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2077 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2078 break; 2079 case 1: /* Fix LNA2=5 */ 2080 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2081 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2082 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2083 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2084 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2085 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2086 break; 2087 } 2088 } 2089 2090 static void rtw8852a_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2091 { 2092 switch (level) { 2093 case 0: /* original */ 2094 rtw8852a_bb_ctrl_btc_preagc(rtwdev, false); 2095 rtw8852a_set_wl_lna2(rtwdev, 0); 2096 break; 2097 case 1: /* for FDD free-run */ 2098 rtw8852a_bb_ctrl_btc_preagc(rtwdev, true); 2099 rtw8852a_set_wl_lna2(rtwdev, 0); 2100 break; 2101 case 2: /* for BTG Co-Rx*/ 2102 rtw8852a_bb_ctrl_btc_preagc(rtwdev, false); 2103 rtw8852a_set_wl_lna2(rtwdev, 1); 2104 break; 2105 } 2106 } 2107 2108 static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2109 struct rtw89_rx_phy_ppdu *phy_ppdu, 2110 struct ieee80211_rx_status *status) 2111 { 2112 u16 chan = phy_ppdu->chan_idx; 2113 u8 band; 2114 2115 if (chan == 0) 2116 return; 2117 2118 band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 2119 status->freq = ieee80211_channel_to_frequency(chan, band); 2120 status->band = band; 2121 } 2122 2123 static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev, 2124 struct rtw89_rx_phy_ppdu *phy_ppdu, 2125 struct ieee80211_rx_status *status) 2126 { 2127 u8 path; 2128 u8 *rx_power = phy_ppdu->rssi; 2129 2130 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B])); 2131 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2132 status->chains |= BIT(path); 2133 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2134 } 2135 if (phy_ppdu->valid) 2136 rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2137 } 2138 2139 static const struct rtw89_chip_ops rtw8852a_chip_ops = { 2140 .enable_bb_rf = rtw89_mac_enable_bb_rf, 2141 .disable_bb_rf = rtw89_mac_disable_bb_rf, 2142 .bb_reset = rtw8852a_bb_reset, 2143 .bb_sethw = rtw8852a_bb_sethw, 2144 .read_rf = rtw89_phy_read_rf, 2145 .write_rf = rtw89_phy_write_rf, 2146 .set_channel = rtw8852a_set_channel, 2147 .set_channel_help = rtw8852a_set_channel_help, 2148 .read_efuse = rtw8852a_read_efuse, 2149 .read_phycap = rtw8852a_read_phycap, 2150 .fem_setup = rtw8852a_fem_setup, 2151 .rfk_init = rtw8852a_rfk_init, 2152 .rfk_channel = rtw8852a_rfk_channel, 2153 .rfk_band_changed = rtw8852a_rfk_band_changed, 2154 .rfk_scan = rtw8852a_rfk_scan, 2155 .rfk_track = rtw8852a_rfk_track, 2156 .power_trim = rtw8852a_power_trim, 2157 .set_txpwr = rtw8852a_set_txpwr, 2158 .set_txpwr_ctrl = rtw8852a_set_txpwr_ctrl, 2159 .init_txpwr_unit = rtw8852a_init_txpwr_unit, 2160 .get_thermal = rtw8852a_get_thermal, 2161 .ctrl_btg = rtw8852a_ctrl_btg, 2162 .query_ppdu = rtw8852a_query_ppdu, 2163 .bb_ctrl_btc_preagc = rtw8852a_bb_ctrl_btc_preagc, 2164 .cfg_txrx_path = NULL, 2165 .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset, 2166 .pwr_on_func = NULL, 2167 .pwr_off_func = NULL, 2168 .fill_txdesc = rtw89_core_fill_txdesc, 2169 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 2170 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 2171 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 2172 .stop_sch_tx = rtw89_mac_stop_sch_tx, 2173 .resume_sch_tx = rtw89_mac_resume_sch_tx, 2174 .h2c_dctl_sec_cam = NULL, 2175 2176 .btc_set_rfe = rtw8852a_btc_set_rfe, 2177 .btc_init_cfg = rtw8852a_btc_init_cfg, 2178 .btc_set_wl_pri = rtw8852a_btc_set_wl_pri, 2179 .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl, 2180 .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi, 2181 .btc_bt_aci_imp = rtw8852a_btc_bt_aci_imp, 2182 .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt, 2183 .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby, 2184 .btc_set_wl_rx_gain = rtw8852a_btc_set_wl_rx_gain, 2185 .btc_set_policy = rtw89_btc_set_policy, 2186 }; 2187 2188 const struct rtw89_chip_info rtw8852a_chip_info = { 2189 .chip_id = RTL8852A, 2190 .ops = &rtw8852a_chip_ops, 2191 .fw_name = "rtw89/rtw8852a_fw.bin", 2192 .fifo_size = 458752, 2193 .dle_scc_rsvd_size = 0, 2194 .max_amsdu_limit = 3500, 2195 .dis_2g_40m_ul_ofdma = true, 2196 .rsvd_ple_ofst = 0x6f800, 2197 .hfc_param_ini = rtw8852a_hfc_param_ini_pcie, 2198 .dle_mem = rtw8852a_dle_mem_pcie, 2199 .rf_base_addr = {0xc000, 0xd000}, 2200 .pwr_on_seq = pwr_on_seq_8852a, 2201 .pwr_off_seq = pwr_off_seq_8852a, 2202 .bb_table = &rtw89_8852a_phy_bb_table, 2203 .bb_gain_table = NULL, 2204 .rf_table = {&rtw89_8852a_phy_radioa_table, 2205 &rtw89_8852a_phy_radiob_table,}, 2206 .nctl_table = &rtw89_8852a_phy_nctl_table, 2207 .byr_table = &rtw89_8852a_byr_table, 2208 .txpwr_lmt_2g = &rtw89_8852a_txpwr_lmt_2g, 2209 .txpwr_lmt_5g = &rtw89_8852a_txpwr_lmt_5g, 2210 .txpwr_lmt_ru_2g = &rtw89_8852a_txpwr_lmt_ru_2g, 2211 .txpwr_lmt_ru_5g = &rtw89_8852a_txpwr_lmt_ru_5g, 2212 .txpwr_factor_rf = 2, 2213 .txpwr_factor_mac = 1, 2214 .dig_table = &rtw89_8852a_phy_dig_table, 2215 .dig_regs = &rtw8852a_dig_regs, 2216 .tssi_dbw_table = NULL, 2217 .support_chanctx_num = 1, 2218 .support_bands = BIT(NL80211_BAND_2GHZ) | 2219 BIT(NL80211_BAND_5GHZ), 2220 .support_bw160 = false, 2221 .hw_sec_hdr = false, 2222 .rf_path_num = 2, 2223 .tx_nss = 2, 2224 .rx_nss = 2, 2225 .acam_num = 128, 2226 .bcam_num = 10, 2227 .scam_num = 128, 2228 .bacam_num = 2, 2229 .bacam_dynamic_num = 4, 2230 .bacam_v1 = false, 2231 .sec_ctrl_efuse_size = 4, 2232 .physical_efuse_size = 1216, 2233 .logical_efuse_size = 1536, 2234 .limit_efuse_size = 1152, 2235 .dav_phy_efuse_size = 0, 2236 .dav_log_efuse_size = 0, 2237 .phycap_addr = 0x580, 2238 .phycap_size = 128, 2239 .para_ver = 0x0, 2240 .wlcx_desired = 0x06000000, 2241 .btcx_desired = 0x7, 2242 .scbd = 0x1, 2243 .mailbox = 0x1, 2244 .btc_fwinfo_buf = 1024, 2245 2246 .fcxbtcrpt_ver = 1, 2247 .fcxtdma_ver = 1, 2248 .fcxslots_ver = 1, 2249 .fcxcysta_ver = 2, 2250 .fcxstep_ver = 2, 2251 .fcxnullsta_ver = 1, 2252 .fcxmreg_ver = 1, 2253 .fcxgpiodbg_ver = 1, 2254 .fcxbtver_ver = 1, 2255 .fcxbtscan_ver = 1, 2256 .fcxbtafh_ver = 1, 2257 .fcxbtdevinfo_ver = 1, 2258 2259 .afh_guard_ch = 6, 2260 .wl_rssi_thres = rtw89_btc_8852a_wl_rssi_thres, 2261 .bt_rssi_thres = rtw89_btc_8852a_bt_rssi_thres, 2262 .rssi_tol = 2, 2263 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852a_mon_reg), 2264 .mon_reg = rtw89_btc_8852a_mon_reg, 2265 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_ul), 2266 .rf_para_ulink = rtw89_btc_8852a_rf_ul, 2267 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_dl), 2268 .rf_para_dlink = rtw89_btc_8852a_rf_dl, 2269 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2270 BIT(RTW89_PS_MODE_CLK_GATED) | 2271 BIT(RTW89_PS_MODE_PWR_GATED), 2272 .low_power_hci_modes = 0, 2273 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD, 2274 .hci_func_en_addr = R_AX_HCI_FUNC_EN, 2275 .h2c_desc_size = sizeof(struct rtw89_txwd_body), 2276 .txwd_body_size = sizeof(struct rtw89_txwd_body), 2277 .h2c_ctrl_reg = R_AX_H2CREG_CTRL, 2278 .h2c_regs = rtw8852a_h2c_regs, 2279 .c2h_ctrl_reg = R_AX_C2HREG_CTRL, 2280 .c2h_regs = rtw8852a_c2h_regs, 2281 .page_regs = &rtw8852a_page_regs, 2282 .dcfo_comp = &rtw8852a_dcfo_comp, 2283 .dcfo_comp_sft = 3, 2284 .imr_info = &rtw8852a_imr_info, 2285 .rrsr_cfgs = &rtw8852a_rrsr_cfgs, 2286 .dma_ch_mask = 0, 2287 }; 2288 EXPORT_SYMBOL(rtw8852a_chip_info); 2289 2290 MODULE_FIRMWARE("rtw89/rtw8852a_fw.bin"); 2291 MODULE_AUTHOR("Realtek Corporation"); 2292 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852A driver"); 2293 MODULE_LICENSE("Dual BSD/GPL"); 2294