1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2022-2023 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "reg.h" 10 #include "rtw8851b.h" 11 #include "rtw8851b_rfk_table.h" 12 #include "rtw8851b_table.h" 13 #include "txrx.h" 14 #include "util.h" 15 16 #define RTW8851B_FW_FORMAT_MAX 0 17 #define RTW8851B_FW_BASENAME "rtw89/rtw8851b_fw" 18 #define RTW8851B_MODULE_FIRMWARE \ 19 RTW8851B_FW_BASENAME ".bin" 20 21 static const struct rtw89_hfc_ch_cfg rtw8851b_hfc_chcfg_pcie[] = { 22 {5, 343, grp_0}, /* ACH 0 */ 23 {5, 343, grp_0}, /* ACH 1 */ 24 {5, 343, grp_0}, /* ACH 2 */ 25 {5, 343, grp_0}, /* ACH 3 */ 26 {0, 0, grp_0}, /* ACH 4 */ 27 {0, 0, grp_0}, /* ACH 5 */ 28 {0, 0, grp_0}, /* ACH 6 */ 29 {0, 0, grp_0}, /* ACH 7 */ 30 {4, 344, grp_0}, /* B0MGQ */ 31 {4, 344, grp_0}, /* B0HIQ */ 32 {0, 0, grp_0}, /* B1MGQ */ 33 {0, 0, grp_0}, /* B1HIQ */ 34 {40, 0, 0} /* FWCMDQ */ 35 }; 36 37 static const struct rtw89_hfc_pub_cfg rtw8851b_hfc_pubcfg_pcie = { 38 448, /* Group 0 */ 39 0, /* Group 1 */ 40 448, /* Public Max */ 41 0 /* WP threshold */ 42 }; 43 44 static const struct rtw89_hfc_param_ini rtw8851b_hfc_param_ini_pcie[] = { 45 [RTW89_QTA_SCC] = {rtw8851b_hfc_chcfg_pcie, &rtw8851b_hfc_pubcfg_pcie, 46 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 47 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 48 RTW89_HCIFC_POH}, 49 [RTW89_QTA_INVALID] = {NULL}, 50 }; 51 52 static const struct rtw89_dle_mem rtw8851b_dle_mem_pcie[] = { 53 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size6, 54 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6, 55 &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18, 56 &rtw89_mac_size.ple_qt58}, 57 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size6, 58 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6, 59 &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18, 60 &rtw89_mac_size.ple_qt_51b_wow}, 61 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9, 62 &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4, 63 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 64 &rtw89_mac_size.ple_qt13}, 65 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 66 NULL}, 67 }; 68 69 static const struct rtw89_xtal_info rtw8851b_xtal_info = { 70 .xcap_reg = R_AX_XTAL_ON_CTRL3, 71 .sc_xo_mask = B_AX_XTAL_SC_XO_A_BLOCK_MASK, 72 .sc_xi_mask = B_AX_XTAL_SC_XI_A_BLOCK_MASK, 73 }; 74 75 static const struct rtw89_chip_ops rtw8851b_chip_ops = { 76 .fem_setup = NULL, 77 .fill_txdesc = rtw89_core_fill_txdesc, 78 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 79 .h2c_dctl_sec_cam = NULL, 80 }; 81 82 #ifdef CONFIG_PM 83 static const struct wiphy_wowlan_support rtw_wowlan_stub_8851b = { 84 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 85 .n_patterns = RTW89_MAX_PATTERN_NUM, 86 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 87 .pattern_min_len = 1, 88 }; 89 #endif 90 91 const struct rtw89_chip_info rtw8851b_chip_info = { 92 .chip_id = RTL8851B, 93 .ops = &rtw8851b_chip_ops, 94 .fw_basename = RTW8851B_FW_BASENAME, 95 .fw_format_max = RTW8851B_FW_FORMAT_MAX, 96 .try_ce_fw = true, 97 .fifo_size = 196608, 98 .small_fifo_size = true, 99 .dle_scc_rsvd_size = 98304, 100 .max_amsdu_limit = 3500, 101 .dis_2g_40m_ul_ofdma = true, 102 .rsvd_ple_ofst = 0x2f800, 103 .hfc_param_ini = rtw8851b_hfc_param_ini_pcie, 104 .dle_mem = rtw8851b_dle_mem_pcie, 105 .wde_qempty_acq_num = 4, 106 .wde_qempty_mgq_sel = 4, 107 .rf_base_addr = {0xe000}, 108 .pwr_on_seq = NULL, 109 .pwr_off_seq = NULL, 110 .bb_table = &rtw89_8851b_phy_bb_table, 111 .bb_gain_table = &rtw89_8851b_phy_bb_gain_table, 112 .rf_table = {&rtw89_8851b_phy_radioa_table,}, 113 .nctl_table = &rtw89_8851b_phy_nctl_table, 114 .nctl_post_table = &rtw8851b_nctl_post_defs_tbl, 115 .byr_table = &rtw89_8851b_byr_table, 116 .dflt_parms = &rtw89_8851b_dflt_parms, 117 .rfe_parms_conf = rtw89_8851b_rfe_parms_conf, 118 .txpwr_factor_rf = 2, 119 .txpwr_factor_mac = 1, 120 .dig_table = NULL, 121 .tssi_dbw_table = NULL, 122 .support_chanctx_num = 0, 123 .support_bands = BIT(NL80211_BAND_2GHZ) | 124 BIT(NL80211_BAND_5GHZ), 125 .support_bw160 = false, 126 .support_unii4 = true, 127 .support_ul_tb_ctrl = true, 128 .hw_sec_hdr = false, 129 .rf_path_num = 1, 130 .tx_nss = 1, 131 .rx_nss = 1, 132 .acam_num = 32, 133 .bcam_num = 20, 134 .scam_num = 128, 135 .bacam_num = 2, 136 .bacam_dynamic_num = 4, 137 .bacam_ver = RTW89_BACAM_V0, 138 .sec_ctrl_efuse_size = 4, 139 .physical_efuse_size = 1216, 140 .logical_efuse_size = 2048, 141 .limit_efuse_size = 1280, 142 .dav_phy_efuse_size = 0, 143 .dav_log_efuse_size = 0, 144 .phycap_addr = 0x580, 145 .phycap_size = 128, 146 .para_ver = 0, 147 .wlcx_desired = 0x06000000, 148 .btcx_desired = 0x7, 149 .scbd = 0x1, 150 .mailbox = 0x1, 151 152 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 153 BIT(RTW89_PS_MODE_CLK_GATED), 154 .low_power_hci_modes = 0, 155 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD, 156 .hci_func_en_addr = R_AX_HCI_FUNC_EN, 157 .h2c_desc_size = sizeof(struct rtw89_txwd_body), 158 .txwd_body_size = sizeof(struct rtw89_txwd_body), 159 .bss_clr_map_reg = R_BSS_CLR_MAP_V1, 160 .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) | 161 BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) | 162 BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI), 163 .edcca_lvl_reg = R_SEG0R_EDCCA_LVL_V1, 164 #ifdef CONFIG_PM 165 .wowlan_stub = &rtw_wowlan_stub_8851b, 166 #endif 167 .xtal_info = &rtw8851b_xtal_info, 168 }; 169 EXPORT_SYMBOL(rtw8851b_chip_info); 170 171 MODULE_FIRMWARE(RTW8851B_MODULE_FIRMWARE); 172 MODULE_AUTHOR("Realtek Corporation"); 173 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8851B driver"); 174 MODULE_LICENSE("Dual BSD/GPL"); 175