1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2022-2023  Realtek Corporation
3  */
4 
5 #include "coex.h"
6 #include "efuse.h"
7 #include "fw.h"
8 #include "mac.h"
9 #include "phy.h"
10 #include "reg.h"
11 #include "rtw8851b.h"
12 #include "rtw8851b_rfk.h"
13 #include "rtw8851b_rfk_table.h"
14 #include "rtw8851b_table.h"
15 #include "txrx.h"
16 #include "util.h"
17 
18 #define RTW8851B_FW_FORMAT_MAX 0
19 #define RTW8851B_FW_BASENAME "rtw89/rtw8851b_fw"
20 #define RTW8851B_MODULE_FIRMWARE \
21 	RTW8851B_FW_BASENAME ".bin"
22 
23 static const struct rtw89_hfc_ch_cfg rtw8851b_hfc_chcfg_pcie[] = {
24 	{5, 343, grp_0}, /* ACH 0 */
25 	{5, 343, grp_0}, /* ACH 1 */
26 	{5, 343, grp_0}, /* ACH 2 */
27 	{5, 343, grp_0}, /* ACH 3 */
28 	{0, 0, grp_0}, /* ACH 4 */
29 	{0, 0, grp_0}, /* ACH 5 */
30 	{0, 0, grp_0}, /* ACH 6 */
31 	{0, 0, grp_0}, /* ACH 7 */
32 	{4, 344, grp_0}, /* B0MGQ */
33 	{4, 344, grp_0}, /* B0HIQ */
34 	{0, 0, grp_0}, /* B1MGQ */
35 	{0, 0, grp_0}, /* B1HIQ */
36 	{40, 0, 0} /* FWCMDQ */
37 };
38 
39 static const struct rtw89_hfc_pub_cfg rtw8851b_hfc_pubcfg_pcie = {
40 	448, /* Group 0 */
41 	0, /* Group 1 */
42 	448, /* Public Max */
43 	0 /* WP threshold */
44 };
45 
46 static const struct rtw89_hfc_param_ini rtw8851b_hfc_param_ini_pcie[] = {
47 	[RTW89_QTA_SCC] = {rtw8851b_hfc_chcfg_pcie, &rtw8851b_hfc_pubcfg_pcie,
48 			   &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
49 	[RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
50 			    RTW89_HCIFC_POH},
51 	[RTW89_QTA_INVALID] = {NULL},
52 };
53 
54 static const struct rtw89_dle_mem rtw8851b_dle_mem_pcie[] = {
55 	[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size6,
56 			   &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6,
57 			   &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18,
58 			   &rtw89_mac_size.ple_qt58},
59 	[RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size6,
60 			   &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6,
61 			   &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18,
62 			   &rtw89_mac_size.ple_qt_51b_wow},
63 	[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
64 			    &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
65 			    &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
66 			    &rtw89_mac_size.ple_qt13},
67 	[RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
68 			       NULL},
69 };
70 
71 static const struct rtw89_reg3_def rtw8851b_btc_preagc_en_defs[] = {
72 	{0x46D0, GENMASK(1, 0), 0x3},
73 	{0x4AD4, GENMASK(31, 0), 0xf},
74 	{0x4688, GENMASK(23, 16), 0x80},
75 	{0x4688, GENMASK(31, 24), 0x80},
76 	{0x4694, GENMASK(7, 0), 0x80},
77 	{0x4694, GENMASK(15, 8), 0x80},
78 	{0x4AE4, GENMASK(11, 6), 0x34},
79 	{0x4AE4, GENMASK(17, 12), 0x0},
80 	{0x469C, GENMASK(31, 26), 0x34},
81 };
82 
83 static DECLARE_PHY_REG3_TBL(rtw8851b_btc_preagc_en_defs);
84 
85 static const struct rtw89_reg3_def rtw8851b_btc_preagc_dis_defs[] = {
86 	{0x46D0, GENMASK(1, 0), 0x0},
87 	{0x4AD4, GENMASK(31, 0), 0x60},
88 	{0x4688, GENMASK(23, 16), 0x10},
89 	{0x4690, GENMASK(31, 24), 0x2a},
90 	{0x4694, GENMASK(15, 8), 0x2a},
91 	{0x4AE4, GENMASK(11, 6), 0x26},
92 	{0x4AE4, GENMASK(17, 12), 0x1e},
93 	{0x469C, GENMASK(31, 26), 0x26},
94 };
95 
96 static DECLARE_PHY_REG3_TBL(rtw8851b_btc_preagc_dis_defs);
97 
98 static const u32 rtw8851b_h2c_regs[RTW89_H2CREG_MAX] = {
99 	R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1,  R_AX_H2CREG_DATA2,
100 	R_AX_H2CREG_DATA3
101 };
102 
103 static const u32 rtw8851b_c2h_regs[RTW89_C2HREG_MAX] = {
104 	R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2,
105 	R_AX_C2HREG_DATA3
106 };
107 
108 static const struct rtw89_page_regs rtw8851b_page_regs = {
109 	.hci_fc_ctrl	= R_AX_HCI_FC_CTRL,
110 	.ch_page_ctrl	= R_AX_CH_PAGE_CTRL,
111 	.ach_page_ctrl	= R_AX_ACH0_PAGE_CTRL,
112 	.ach_page_info	= R_AX_ACH0_PAGE_INFO,
113 	.pub_page_info3	= R_AX_PUB_PAGE_INFO3,
114 	.pub_page_ctrl1	= R_AX_PUB_PAGE_CTRL1,
115 	.pub_page_ctrl2	= R_AX_PUB_PAGE_CTRL2,
116 	.pub_page_info1	= R_AX_PUB_PAGE_INFO1,
117 	.pub_page_info2 = R_AX_PUB_PAGE_INFO2,
118 	.wp_page_ctrl1	= R_AX_WP_PAGE_CTRL1,
119 	.wp_page_ctrl2	= R_AX_WP_PAGE_CTRL2,
120 	.wp_page_info1	= R_AX_WP_PAGE_INFO1,
121 };
122 
123 static const struct rtw89_reg_def rtw8851b_dcfo_comp = {
124 	R_DCFO_COMP_S0_V2, B_DCFO_COMP_S0_MSK_V2
125 };
126 
127 static const struct rtw89_imr_info rtw8851b_imr_info = {
128 	.wdrls_imr_set		= B_AX_WDRLS_IMR_SET,
129 	.wsec_imr_reg		= R_AX_SEC_DEBUG,
130 	.wsec_imr_set		= B_AX_IMR_ERROR,
131 	.mpdu_tx_imr_set	= 0,
132 	.mpdu_rx_imr_set	= 0,
133 	.sta_sch_imr_set	= B_AX_STA_SCHEDULER_IMR_SET,
134 	.txpktctl_imr_b0_reg	= R_AX_TXPKTCTL_ERR_IMR_ISR,
135 	.txpktctl_imr_b0_clr	= B_AX_TXPKTCTL_IMR_B0_CLR,
136 	.txpktctl_imr_b0_set	= B_AX_TXPKTCTL_IMR_B0_SET,
137 	.txpktctl_imr_b1_reg	= R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
138 	.txpktctl_imr_b1_clr	= B_AX_TXPKTCTL_IMR_B1_CLR,
139 	.txpktctl_imr_b1_set	= B_AX_TXPKTCTL_IMR_B1_SET,
140 	.wde_imr_clr		= B_AX_WDE_IMR_CLR,
141 	.wde_imr_set		= B_AX_WDE_IMR_SET,
142 	.ple_imr_clr		= B_AX_PLE_IMR_CLR,
143 	.ple_imr_set		= B_AX_PLE_IMR_SET,
144 	.host_disp_imr_clr	= B_AX_HOST_DISP_IMR_CLR,
145 	.host_disp_imr_set	= B_AX_HOST_DISP_IMR_SET,
146 	.cpu_disp_imr_clr	= B_AX_CPU_DISP_IMR_CLR,
147 	.cpu_disp_imr_set	= B_AX_CPU_DISP_IMR_SET,
148 	.other_disp_imr_clr	= B_AX_OTHER_DISP_IMR_CLR,
149 	.other_disp_imr_set	= 0,
150 	.bbrpt_com_err_imr_reg	= R_AX_BBRPT_COM_ERR_IMR_ISR,
151 	.bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
152 	.bbrpt_err_imr_set	= 0,
153 	.bbrpt_dfs_err_imr_reg	= R_AX_BBRPT_DFS_ERR_IMR_ISR,
154 	.ptcl_imr_clr		= B_AX_PTCL_IMR_CLR_ALL,
155 	.ptcl_imr_set		= B_AX_PTCL_IMR_SET,
156 	.cdma_imr_0_reg		= R_AX_DLE_CTRL,
157 	.cdma_imr_0_clr		= B_AX_DLE_IMR_CLR,
158 	.cdma_imr_0_set		= B_AX_DLE_IMR_SET,
159 	.cdma_imr_1_reg		= 0,
160 	.cdma_imr_1_clr		= 0,
161 	.cdma_imr_1_set		= 0,
162 	.phy_intf_imr_reg	= R_AX_PHYINFO_ERR_IMR,
163 	.phy_intf_imr_clr	= 0,
164 	.phy_intf_imr_set	= 0,
165 	.rmac_imr_reg		= R_AX_RMAC_ERR_ISR,
166 	.rmac_imr_clr		= B_AX_RMAC_IMR_CLR,
167 	.rmac_imr_set		= B_AX_RMAC_IMR_SET,
168 	.tmac_imr_reg		= R_AX_TMAC_ERR_IMR_ISR,
169 	.tmac_imr_clr		= B_AX_TMAC_IMR_CLR,
170 	.tmac_imr_set		= B_AX_TMAC_IMR_SET,
171 };
172 
173 static const struct rtw89_xtal_info rtw8851b_xtal_info = {
174 	.xcap_reg		= R_AX_XTAL_ON_CTRL3,
175 	.sc_xo_mask		= B_AX_XTAL_SC_XO_A_BLOCK_MASK,
176 	.sc_xi_mask		= B_AX_XTAL_SC_XI_A_BLOCK_MASK,
177 };
178 
179 static const struct rtw89_rrsr_cfgs rtw8851b_rrsr_cfgs = {
180 	.ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
181 	.rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
182 };
183 
184 static const struct rtw89_dig_regs rtw8851b_dig_regs = {
185 	.seg0_pd_reg = R_SEG0R_PD_V1,
186 	.pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
187 	.pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1,
188 	.p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
189 	.p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
190 	.p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},
191 	.p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1},
192 	.p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1},
193 	.p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1},
194 	.p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2,
195 			      B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
196 	.p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2,
197 			      B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
198 	.p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2,
199 			      B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
200 	.p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2,
201 			      B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
202 };
203 
204 static const struct rtw89_btc_rf_trx_para rtw89_btc_8851b_rf_ul[] = {
205 	{255, 0, 0, 7}, /* 0 -> original */
206 	{255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
207 	{255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
208 	{255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
209 	{255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
210 	{255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
211 	{6, 1, 0, 7},
212 	{13, 1, 0, 7},
213 	{13, 1, 0, 7}
214 };
215 
216 static const struct rtw89_btc_rf_trx_para rtw89_btc_8851b_rf_dl[] = {
217 	{255, 0, 0, 7}, /* 0 -> original */
218 	{255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
219 	{255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
220 	{255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
221 	{255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
222 	{255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
223 	{255, 1, 0, 7},
224 	{255, 1, 0, 7},
225 	{255, 1, 0, 7}
226 };
227 
228 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8851b_mon_reg[] = {
229 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
230 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
231 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
232 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
233 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
234 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
235 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
236 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
237 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
238 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
239 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200),
240 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220),
241 	RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
242 	RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4738),
243 	RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4688),
244 	RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4694),
245 };
246 
247 static const u8 rtw89_btc_8851b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40};
248 static const u8 rtw89_btc_8851b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20};
249 
250 static int rtw8851b_pwr_on_func(struct rtw89_dev *rtwdev)
251 {
252 	u32 val32;
253 	u8 val8;
254 	u32 ret;
255 
256 	rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
257 						    B_AX_AFSM_PCIE_SUS_EN);
258 	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
259 	rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
260 	rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
261 	rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
262 
263 	ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR,
264 				1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
265 	if (ret)
266 		return ret;
267 
268 	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
269 	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
270 
271 	ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC),
272 				1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
273 	if (ret)
274 		return ret;
275 
276 	rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
277 	rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
278 	rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
279 	rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
280 
281 	rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
282 	rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
283 
284 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
285 				      XTAL_SI_OFF_WEI);
286 	if (ret)
287 		return ret;
288 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
289 				      XTAL_SI_OFF_EI);
290 	if (ret)
291 		return ret;
292 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
293 	if (ret)
294 		return ret;
295 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
296 				      XTAL_SI_PON_WEI);
297 	if (ret)
298 		return ret;
299 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
300 				      XTAL_SI_PON_EI);
301 	if (ret)
302 		return ret;
303 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
304 	if (ret)
305 		return ret;
306 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);
307 	if (ret)
308 		return ret;
309 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
310 	if (ret)
311 		return ret;
312 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
313 	if (ret)
314 		return ret;
315 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_DRV, 0, XTAL_SI_DRV_LATCH);
316 	if (ret)
317 		return ret;
318 
319 	rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
320 	rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
321 	rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
322 
323 	fsleep(1000);
324 
325 	rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
326 	rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
327 	rtw89_write32_set(rtwdev, R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN,
328 			  B_AX_GPIO10_PULL_LOW_EN | B_AX_GPIO16_PULL_LOW_EN_V1);
329 
330 	if (rtwdev->hal.cv == CHIP_CAV) {
331 		ret = rtw89_read_efuse_ver(rtwdev, &val8);
332 		if (!ret)
333 			rtwdev->hal.cv = val8;
334 	}
335 
336 	rtw89_write32_clr(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG,
337 			  B_AX_XTAL_SI_ADDR_NOT_CHK);
338 	if (rtwdev->hal.cv != CHIP_CAV) {
339 		rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY);
340 		rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY);
341 	}
342 
343 	rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
344 			  B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |
345 			  B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN |
346 			  B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN |
347 			  B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN |
348 			  B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN |
349 			  B_AX_DMACREG_GCKEN);
350 	rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
351 			  B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
352 			  B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN |
353 			  B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN |
354 			  B_AX_RMAC_EN);
355 
356 	rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK,
357 			   PINMUX_EESK_FUNC_SEL_BT_LOG);
358 
359 	return 0;
360 }
361 
362 static void rtw8851b_patch_swr_pfm2pwm(struct rtw89_dev *rtwdev)
363 {
364 	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_PWMM_DSWR);
365 	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_ASWRM);
366 	rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_DSWRM);
367 	rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_ASWRM);
368 }
369 
370 static int rtw8851b_pwr_off_func(struct rtw89_dev *rtwdev)
371 {
372 	u32 val32;
373 	u32 ret;
374 
375 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
376 				      XTAL_SI_RFC2RF);
377 	if (ret)
378 		return ret;
379 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
380 	if (ret)
381 		return ret;
382 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
383 	if (ret)
384 		return ret;
385 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
386 	if (ret)
387 		return ret;
388 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
389 				      XTAL_SI_SRAM2RFC);
390 	if (ret)
391 		return ret;
392 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
393 	if (ret)
394 		return ret;
395 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
396 	if (ret)
397 		return ret;
398 
399 	rtw89_write32_set(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG,
400 			  B_AX_XTAL_SI_ADDR_NOT_CHK);
401 	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
402 	rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
403 	rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
404 
405 	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
406 
407 	ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC),
408 				1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
409 	if (ret)
410 		return ret;
411 
412 	rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
413 
414 	if (rtwdev->hal.cv == CHIP_CAV) {
415 		rtw8851b_patch_swr_pfm2pwm(rtwdev);
416 	} else {
417 		rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY);
418 		rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY);
419 	}
420 
421 	rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
422 
423 	return 0;
424 }
425 
426 static void rtw8851b_efuse_parsing(struct rtw89_efuse *efuse,
427 				   struct rtw8851b_efuse *map)
428 {
429 	ether_addr_copy(efuse->addr, map->e.mac_addr);
430 	efuse->rfe_type = map->rfe_type;
431 	efuse->xtal_cap = map->xtal_k;
432 }
433 
434 static void rtw8851b_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
435 					struct rtw8851b_efuse *map)
436 {
437 	struct rtw89_tssi_info *tssi = &rtwdev->tssi;
438 	struct rtw8851b_tssi_offset *ofst[] = {&map->path_a_tssi};
439 	u8 i, j;
440 
441 	tssi->thermal[RF_PATH_A] = map->path_a_therm;
442 
443 	for (i = 0; i < RF_PATH_NUM_8851B; i++) {
444 		memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
445 		       sizeof(ofst[i]->cck_tssi));
446 
447 		for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
448 			rtw89_debug(rtwdev, RTW89_DBG_TSSI,
449 				    "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
450 				    i, j, tssi->tssi_cck[i][j]);
451 
452 		memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
453 		       sizeof(ofst[i]->bw40_tssi));
454 		memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
455 		       ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
456 
457 		for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
458 			rtw89_debug(rtwdev, RTW89_DBG_TSSI,
459 				    "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
460 				    i, j, tssi->tssi_mcs[i][j]);
461 	}
462 }
463 
464 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low)
465 {
466 	if (high)
467 		*high = sign_extend32(u8_get_bits(data, GENMASK(7,  4)), 3);
468 	if (low)
469 		*low = sign_extend32(u8_get_bits(data, GENMASK(3,  0)), 3);
470 
471 	return data != 0xff;
472 }
473 
474 static void rtw8851b_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
475 					       struct rtw8851b_efuse *map)
476 {
477 	struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
478 	bool valid = false;
479 
480 	valid |= _decode_efuse_gain(map->rx_gain_2g_cck,
481 				    &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK],
482 				    NULL);
483 	valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm,
484 				    &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM],
485 				    NULL);
486 	valid |= _decode_efuse_gain(map->rx_gain_5g_low,
487 				    &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW],
488 				    NULL);
489 	valid |= _decode_efuse_gain(map->rx_gain_5g_mid,
490 				    &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID],
491 				   NULL);
492 	valid |= _decode_efuse_gain(map->rx_gain_5g_high,
493 				    &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH],
494 				    NULL);
495 
496 	gain->offset_valid = valid;
497 }
498 
499 static int rtw8851b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map)
500 {
501 	struct rtw89_efuse *efuse = &rtwdev->efuse;
502 	struct rtw8851b_efuse *map;
503 
504 	map = (struct rtw8851b_efuse *)log_map;
505 
506 	efuse->country_code[0] = map->country_code[0];
507 	efuse->country_code[1] = map->country_code[1];
508 	rtw8851b_efuse_parsing_tssi(rtwdev, map);
509 	rtw8851b_efuse_parsing_gain_offset(rtwdev, map);
510 
511 	switch (rtwdev->hci.type) {
512 	case RTW89_HCI_TYPE_PCIE:
513 		rtw8851b_efuse_parsing(efuse, map);
514 		break;
515 	default:
516 		return -EOPNOTSUPP;
517 	}
518 
519 	rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
520 
521 	return 0;
522 }
523 
524 static void rtw8851b_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
525 {
526 	struct rtw89_tssi_info *tssi = &rtwdev->tssi;
527 	static const u32 tssi_trim_addr[RF_PATH_NUM_8851B] = {0x5D6};
528 	u32 addr = rtwdev->chip->phycap_addr;
529 	bool pg = false;
530 	u32 ofst;
531 	u8 i, j;
532 
533 	for (i = 0; i < RF_PATH_NUM_8851B; i++) {
534 		for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
535 			/* addrs are in decreasing order */
536 			ofst = tssi_trim_addr[i] - addr - j;
537 			tssi->tssi_trim[i][j] = phycap_map[ofst];
538 
539 			if (phycap_map[ofst] != 0xff)
540 				pg = true;
541 		}
542 	}
543 
544 	if (!pg) {
545 		memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
546 		rtw89_debug(rtwdev, RTW89_DBG_TSSI,
547 			    "[TSSI][TRIM] no PG, set all trim info to 0\n");
548 	}
549 
550 	for (i = 0; i < RF_PATH_NUM_8851B; i++)
551 		for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
552 			rtw89_debug(rtwdev, RTW89_DBG_TSSI,
553 				    "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
554 				    i, j, tssi->tssi_trim[i][j],
555 				    tssi_trim_addr[i] - j);
556 }
557 
558 static void rtw8851b_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
559 						 u8 *phycap_map)
560 {
561 	struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
562 	static const u32 thm_trim_addr[RF_PATH_NUM_8851B] = {0x5DF};
563 	u32 addr = rtwdev->chip->phycap_addr;
564 	u8 i;
565 
566 	for (i = 0; i < RF_PATH_NUM_8851B; i++) {
567 		info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
568 
569 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
570 			    "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
571 			    i, info->thermal_trim[i]);
572 
573 		if (info->thermal_trim[i] != 0xff)
574 			info->pg_thermal_trim = true;
575 	}
576 }
577 
578 static void rtw8851b_thermal_trim(struct rtw89_dev *rtwdev)
579 {
580 #define __thm_setting(raw)				\
581 ({							\
582 	u8 __v = (raw);					\
583 	((__v & 0x1) << 3) | ((__v & 0x1f) >> 1);	\
584 })
585 	struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
586 	u8 i, val;
587 
588 	if (!info->pg_thermal_trim) {
589 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
590 			    "[THERMAL][TRIM] no PG, do nothing\n");
591 
592 		return;
593 	}
594 
595 	for (i = 0; i < RF_PATH_NUM_8851B; i++) {
596 		val = __thm_setting(info->thermal_trim[i]);
597 		rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
598 
599 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
600 			    "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
601 			    i, val);
602 	}
603 #undef __thm_setting
604 }
605 
606 static void rtw8851b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
607 						 u8 *phycap_map)
608 {
609 	struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
610 	static const u32 pabias_trim_addr[] = {0x5DE};
611 	u32 addr = rtwdev->chip->phycap_addr;
612 	u8 i;
613 
614 	for (i = 0; i < RF_PATH_NUM_8851B; i++) {
615 		info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
616 
617 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
618 			    "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
619 			    i, info->pa_bias_trim[i]);
620 
621 		if (info->pa_bias_trim[i] != 0xff)
622 			info->pg_pa_bias_trim = true;
623 	}
624 }
625 
626 static void rtw8851b_pa_bias_trim(struct rtw89_dev *rtwdev)
627 {
628 	struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
629 	u8 pabias_2g, pabias_5g;
630 	u8 i;
631 
632 	if (!info->pg_pa_bias_trim) {
633 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
634 			    "[PA_BIAS][TRIM] no PG, do nothing\n");
635 
636 		return;
637 	}
638 
639 	for (i = 0; i < RF_PATH_NUM_8851B; i++) {
640 		pabias_2g = u8_get_bits(info->pa_bias_trim[i], GENMASK(3, 0));
641 		pabias_5g = u8_get_bits(info->pa_bias_trim[i], GENMASK(7, 4));
642 
643 		rtw89_debug(rtwdev, RTW89_DBG_RFK,
644 			    "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
645 			    i, pabias_2g, pabias_5g);
646 
647 		rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
648 		rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
649 	}
650 }
651 
652 static void rtw8851b_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map)
653 {
654 	static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = {
655 		{0x5BB, 0x5BA, 0, 0x5B9, 0x5B8},
656 	};
657 	struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
658 	u32 phycap_addr = rtwdev->chip->phycap_addr;
659 	bool valid = false;
660 	int path, i;
661 	u8 data;
662 
663 	for (path = 0; path < BB_PATH_NUM_8851B; path++)
664 		for (i = 0; i < RTW89_SUBBAND_2GHZ_5GHZ_NR; i++) {
665 			if (comp_addrs[path][i] == 0)
666 				continue;
667 
668 			data = phycap_map[comp_addrs[path][i] - phycap_addr];
669 			valid |= _decode_efuse_gain(data, NULL,
670 						    &gain->comp[path][i]);
671 		}
672 
673 	gain->comp_valid = valid;
674 }
675 
676 static int rtw8851b_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
677 {
678 	rtw8851b_phycap_parsing_tssi(rtwdev, phycap_map);
679 	rtw8851b_phycap_parsing_thermal_trim(rtwdev, phycap_map);
680 	rtw8851b_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
681 	rtw8851b_phycap_parsing_gain_comp(rtwdev, phycap_map);
682 
683 	return 0;
684 }
685 
686 static void rtw8851b_set_bb_gpio(struct rtw89_dev *rtwdev, u8 gpio_idx, bool inv,
687 				 u8 src_sel)
688 {
689 	u32 addr, mask;
690 
691 	if (gpio_idx >= 32)
692 		return;
693 
694 	/* 2 continual 32-bit registers for 32 GPIOs, and each GPIO occupies 2 bits */
695 	addr = R_RFE_SEL0_A2 + (gpio_idx / 16) * sizeof(u32);
696 	mask = B_RFE_SEL0_MASK << (gpio_idx % 16) * 2;
697 
698 	rtw89_phy_write32_mask(rtwdev, addr, mask, RF_PATH_A);
699 	rtw89_phy_write32_mask(rtwdev, R_RFE_INV0, BIT(gpio_idx), inv);
700 
701 	/* 4 continual 32-bit registers for 32 GPIOs, and each GPIO occupies 4 bits */
702 	addr = R_RFE_SEL0_BASE + (gpio_idx / 8) * sizeof(u32);
703 	mask = B_RFE_SEL0_SRC_MASK << (gpio_idx % 8) * 4;
704 
705 	rtw89_phy_write32_mask(rtwdev, addr, mask, src_sel);
706 }
707 
708 static void rtw8851b_set_mac_gpio(struct rtw89_dev *rtwdev, u8 func)
709 {
710 	static const struct rtw89_reg3_def func16 = {
711 		R_AX_GPIO16_23_FUNC_SEL, B_AX_PINMUX_GPIO16_FUNC_SEL_MASK, BIT(3)
712 	};
713 	static const struct rtw89_reg3_def func17 = {
714 		R_AX_GPIO16_23_FUNC_SEL, B_AX_PINMUX_GPIO17_FUNC_SEL_MASK, BIT(7) >> 4,
715 	};
716 	const struct rtw89_reg3_def *def;
717 
718 	switch (func) {
719 	case 16:
720 		def = &func16;
721 		break;
722 	case 17:
723 		def = &func17;
724 		break;
725 	default:
726 		rtw89_warn(rtwdev, "undefined gpio func %d\n", func);
727 		return;
728 	}
729 
730 	rtw89_write8_mask(rtwdev, def->addr, def->mask, def->data);
731 }
732 
733 static void rtw8851b_rfe_gpio(struct rtw89_dev *rtwdev)
734 {
735 	u8 rfe_type = rtwdev->efuse.rfe_type;
736 
737 	if (rfe_type > 50)
738 		return;
739 
740 	if (rfe_type % 3 == 2) {
741 		rtw8851b_set_bb_gpio(rtwdev, 16, true, RFE_SEL0_SRC_ANTSEL_0);
742 		rtw8851b_set_bb_gpio(rtwdev, 17, false, RFE_SEL0_SRC_ANTSEL_0);
743 
744 		rtw8851b_set_mac_gpio(rtwdev, 16);
745 		rtw8851b_set_mac_gpio(rtwdev, 17);
746 	}
747 }
748 
749 static void rtw8851b_power_trim(struct rtw89_dev *rtwdev)
750 {
751 	rtw8851b_thermal_trim(rtwdev);
752 	rtw8851b_pa_bias_trim(rtwdev);
753 }
754 
755 static void rtw8851b_set_channel_mac(struct rtw89_dev *rtwdev,
756 				     const struct rtw89_chan *chan,
757 				     u8 mac_idx)
758 {
759 	u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
760 	u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx);
761 	u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx);
762 	u8 txsc20 = 0, txsc40 = 0;
763 
764 	switch (chan->band_width) {
765 	case RTW89_CHANNEL_WIDTH_80:
766 		txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40);
767 		fallthrough;
768 	case RTW89_CHANNEL_WIDTH_40:
769 		txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20);
770 		break;
771 	default:
772 		break;
773 	}
774 
775 	switch (chan->band_width) {
776 	case RTW89_CHANNEL_WIDTH_80:
777 		rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
778 		rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
779 		break;
780 	case RTW89_CHANNEL_WIDTH_40:
781 		rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
782 		rtw89_write32(rtwdev, sub_carr, txsc20);
783 		break;
784 	case RTW89_CHANNEL_WIDTH_20:
785 		rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
786 		rtw89_write32(rtwdev, sub_carr, 0);
787 		break;
788 	default:
789 		break;
790 	}
791 
792 	if (chan->channel > 14) {
793 		rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE);
794 		rtw89_write8_set(rtwdev, chk_rate,
795 				 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
796 	} else {
797 		rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE);
798 		rtw89_write8_clr(rtwdev, chk_rate,
799 				 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
800 	}
801 }
802 
803 static const u32 rtw8851b_sco_barker_threshold[14] = {
804 	0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
805 	0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4
806 };
807 
808 static const u32 rtw8851b_sco_cck_threshold[14] = {
809 	0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724,
810 	0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed
811 };
812 
813 static void rtw8851b_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch)
814 {
815 	u8 ch_element = primary_ch - 1;
816 
817 	rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
818 			       rtw8851b_sco_barker_threshold[ch_element]);
819 	rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
820 			       rtw8851b_sco_cck_threshold[ch_element]);
821 }
822 
823 static u8 rtw8851b_sco_mapping(u8 central_ch)
824 {
825 	if (central_ch == 1)
826 		return 109;
827 	else if (central_ch >= 2 && central_ch <= 6)
828 		return 108;
829 	else if (central_ch >= 7 && central_ch <= 10)
830 		return 107;
831 	else if (central_ch >= 11 && central_ch <= 14)
832 		return 106;
833 	else if (central_ch == 36 || central_ch == 38)
834 		return 51;
835 	else if (central_ch >= 40 && central_ch <= 58)
836 		return 50;
837 	else if (central_ch >= 60 && central_ch <= 64)
838 		return 49;
839 	else if (central_ch == 100 || central_ch == 102)
840 		return 48;
841 	else if (central_ch >= 104 && central_ch <= 126)
842 		return 47;
843 	else if (central_ch >= 128 && central_ch <= 151)
844 		return 46;
845 	else if (central_ch >= 153 && central_ch <= 177)
846 		return 45;
847 	else
848 		return 0;
849 }
850 
851 struct rtw8851b_bb_gain {
852 	u32 gain_g[BB_PATH_NUM_8851B];
853 	u32 gain_a[BB_PATH_NUM_8851B];
854 	u32 gain_mask;
855 };
856 
857 static const struct rtw8851b_bb_gain bb_gain_lna[LNA_GAIN_NUM] = {
858 	{ .gain_g = {0x4678}, .gain_a = {0x45DC},
859 	  .gain_mask = 0x00ff0000 },
860 	{ .gain_g = {0x4678}, .gain_a = {0x45DC},
861 	  .gain_mask = 0xff000000 },
862 	{ .gain_g = {0x467C}, .gain_a = {0x4660},
863 	  .gain_mask = 0x000000ff },
864 	{ .gain_g = {0x467C}, .gain_a = {0x4660},
865 	  .gain_mask = 0x0000ff00 },
866 	{ .gain_g = {0x467C}, .gain_a = {0x4660},
867 	  .gain_mask = 0x00ff0000 },
868 	{ .gain_g = {0x467C}, .gain_a = {0x4660},
869 	  .gain_mask = 0xff000000 },
870 	{ .gain_g = {0x4680}, .gain_a = {0x4664},
871 	  .gain_mask = 0x000000ff },
872 };
873 
874 static const struct rtw8851b_bb_gain bb_gain_tia[TIA_GAIN_NUM] = {
875 	{ .gain_g = {0x4680}, .gain_a = {0x4664},
876 	  .gain_mask = 0x00ff0000 },
877 	{ .gain_g = {0x4680}, .gain_a = {0x4664},
878 	  .gain_mask = 0xff000000 },
879 };
880 
881 static void rtw8851b_set_gain_error(struct rtw89_dev *rtwdev,
882 				    enum rtw89_subband subband,
883 				    enum rtw89_rf_path path)
884 {
885 	const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
886 	u8 gain_band = rtw89_subband_to_bb_gain_band(subband);
887 	s32 val;
888 	u32 reg;
889 	u32 mask;
890 	int i;
891 
892 	for (i = 0; i < LNA_GAIN_NUM; i++) {
893 		if (subband == RTW89_CH_2G)
894 			reg = bb_gain_lna[i].gain_g[path];
895 		else
896 			reg = bb_gain_lna[i].gain_a[path];
897 
898 		mask = bb_gain_lna[i].gain_mask;
899 		val = gain->lna_gain[gain_band][path][i];
900 		rtw89_phy_write32_mask(rtwdev, reg, mask, val);
901 	}
902 
903 	for (i = 0; i < TIA_GAIN_NUM; i++) {
904 		if (subband == RTW89_CH_2G)
905 			reg = bb_gain_tia[i].gain_g[path];
906 		else
907 			reg = bb_gain_tia[i].gain_a[path];
908 
909 		mask = bb_gain_tia[i].gain_mask;
910 		val = gain->tia_gain[gain_band][path][i];
911 		rtw89_phy_write32_mask(rtwdev, reg, mask, val);
912 	}
913 }
914 
915 static void rtw8851b_set_gain_offset(struct rtw89_dev *rtwdev,
916 				     enum rtw89_subband subband,
917 				     enum rtw89_phy_idx phy_idx)
918 {
919 	static const u32 rssi_ofst_addr[] = {R_PATH0_G_TIA1_LNA6_OP1DB_V1};
920 	static const u32 gain_err_addr[] = {R_P0_AGC_RSVD};
921 	struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
922 	enum rtw89_gain_offset gain_ofdm_band;
923 	s32 offset_ofdm, offset_cck;
924 	s32 offset_a;
925 	s32 tmp;
926 	u8 path;
927 
928 	if (!efuse_gain->comp_valid)
929 		goto next;
930 
931 	for (path = RF_PATH_A; path < BB_PATH_NUM_8851B; path++) {
932 		tmp = efuse_gain->comp[path][subband];
933 		tmp = clamp_t(s32, tmp << 2, S8_MIN, S8_MAX);
934 		rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp);
935 	}
936 
937 next:
938 	if (!efuse_gain->offset_valid)
939 		return;
940 
941 	gain_ofdm_band = rtw89_subband_to_gain_offset_band_of_ofdm(subband);
942 
943 	offset_a = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
944 
945 	tmp = -((offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2));
946 	tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
947 	rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp);
948 
949 	offset_ofdm = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
950 	offset_cck = -efuse_gain->offset[RF_PATH_A][0];
951 
952 	tmp = (offset_ofdm << 4) + efuse_gain->offset_base[RTW89_PHY_0];
953 	tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
954 	rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
955 
956 	tmp = (offset_ofdm << 4) + efuse_gain->rssi_base[RTW89_PHY_0];
957 	tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
958 	rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
959 
960 	if (subband == RTW89_CH_2G) {
961 		tmp = (offset_cck << 3) + (efuse_gain->offset_base[RTW89_PHY_0] >> 1);
962 		tmp = clamp_t(s32, tmp, S8_MIN >> 1, S8_MAX >> 1);
963 		rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST,
964 				       B_RX_RPL_OFST_CCK_MASK, tmp);
965 	}
966 }
967 
968 static
969 void rtw8851b_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband)
970 {
971 	const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
972 	u8 band = rtw89_subband_to_bb_gain_band(subband);
973 	u32 val;
974 
975 	val = u32_encode_bits(gain->rpl_ofst_20[band][RF_PATH_A], B_P0_RPL1_20_MASK) |
976 	      u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][0], B_P0_RPL1_40_MASK) |
977 	      u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][1], B_P0_RPL1_41_MASK);
978 	val >>= B_P0_RPL1_SHIFT;
979 	rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val);
980 	rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val);
981 
982 	val = u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][2], B_P0_RTL2_42_MASK) |
983 	      u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][0], B_P0_RTL2_80_MASK) |
984 	      u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][1], B_P0_RTL2_81_MASK) |
985 	      u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][10], B_P0_RTL2_8A_MASK);
986 	rtw89_phy_write32(rtwdev, R_P0_RPL2, val);
987 	rtw89_phy_write32(rtwdev, R_P1_RPL2, val);
988 
989 	val = u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][2], B_P0_RTL3_82_MASK) |
990 	      u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][3], B_P0_RTL3_83_MASK) |
991 	      u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][4], B_P0_RTL3_84_MASK) |
992 	      u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][9], B_P0_RTL3_89_MASK);
993 	rtw89_phy_write32(rtwdev, R_P0_RPL3, val);
994 	rtw89_phy_write32(rtwdev, R_P1_RPL3, val);
995 }
996 
997 static void rtw8851b_ctrl_ch(struct rtw89_dev *rtwdev,
998 			     const struct rtw89_chan *chan,
999 			     enum rtw89_phy_idx phy_idx)
1000 {
1001 	u8 subband = chan->subband_type;
1002 	u8 central_ch = chan->channel;
1003 	bool is_2g = central_ch <= 14;
1004 	u8 sco_comp;
1005 
1006 	if (is_2g)
1007 		rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1008 				      B_PATH0_BAND_SEL_MSK_V1, 1, phy_idx);
1009 	else
1010 		rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1011 				      B_PATH0_BAND_SEL_MSK_V1, 0, phy_idx);
1012 	/* SCO compensate FC setting */
1013 	sco_comp = rtw8851b_sco_mapping(central_ch);
1014 	rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx);
1015 
1016 	if (chan->band_type == RTW89_BAND_6G)
1017 		return;
1018 
1019 	/* CCK parameters */
1020 	if (central_ch == 14) {
1021 		rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff);
1022 		rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de);
1023 		rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad);
1024 		rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e);
1025 		rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92);
1026 		rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
1027 		rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
1028 		rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a);
1029 	} else {
1030 		rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff);
1031 		rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354);
1032 		rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
1033 		rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053);
1034 		rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a);
1035 		rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92);
1036 		rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc);
1037 		rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5);
1038 	}
1039 
1040 	rtw8851b_set_gain_error(rtwdev, subband, RF_PATH_A);
1041 	rtw8851b_set_gain_offset(rtwdev, subband, phy_idx);
1042 	rtw8851b_set_rxsc_rpl_comp(rtwdev, subband);
1043 }
1044 
1045 static void rtw8851b_bw_setting(struct rtw89_dev *rtwdev, u8 bw)
1046 {
1047 	rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_CTL, 0x8);
1048 	rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_EN, 0x2);
1049 	rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_BW0, 0x2);
1050 	rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_BW1, 0x4);
1051 	rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_MUL, 0xf);
1052 	rtw89_phy_write32_mask(rtwdev, R_ADCMOD, B_ADCMOD_LP, 0xa);
1053 	rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ADJ, 0x92);
1054 
1055 	switch (bw) {
1056 	case RTW89_CHANNEL_WIDTH_5:
1057 		rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1);
1058 		rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x0);
1059 		rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x1);
1060 		break;
1061 	case RTW89_CHANNEL_WIDTH_10:
1062 		rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1);
1063 		rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x1);
1064 		rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1065 		break;
1066 	case RTW89_CHANNEL_WIDTH_20:
1067 		rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2);
1068 		rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1069 		rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1070 		break;
1071 	case RTW89_CHANNEL_WIDTH_40:
1072 		rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2);
1073 		rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1074 		rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1075 		break;
1076 	case RTW89_CHANNEL_WIDTH_80:
1077 		rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x0);
1078 		rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1079 		rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1080 		break;
1081 	default:
1082 		rtw89_warn(rtwdev, "Fail to set ADC\n");
1083 	}
1084 }
1085 
1086 static void rtw8851b_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
1087 			     enum rtw89_phy_idx phy_idx)
1088 {
1089 	switch (bw) {
1090 	case RTW89_CHANNEL_WIDTH_5:
1091 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1092 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx);
1093 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1094 		break;
1095 	case RTW89_CHANNEL_WIDTH_10:
1096 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1097 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx);
1098 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1099 		break;
1100 	case RTW89_CHANNEL_WIDTH_20:
1101 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1102 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1103 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1104 		break;
1105 	case RTW89_CHANNEL_WIDTH_40:
1106 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx);
1107 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1108 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
1109 				      pri_ch, phy_idx);
1110 		/* CCK primary channel */
1111 		if (pri_ch == RTW89_SC_20_UPPER)
1112 			rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
1113 		else
1114 			rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
1115 
1116 		break;
1117 	case RTW89_CHANNEL_WIDTH_80:
1118 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx);
1119 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1120 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
1121 				      pri_ch, phy_idx);
1122 		break;
1123 	default:
1124 		rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1125 			   pri_ch);
1126 	}
1127 
1128 	rtw8851b_bw_setting(rtwdev, bw);
1129 }
1130 
1131 static void rtw8851b_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en)
1132 {
1133 	if (cck_en) {
1134 		rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
1135 		rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF,
1136 				       B_PD_ARBITER_OFF, 0);
1137 		rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1);
1138 	} else {
1139 		rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
1140 		rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF,
1141 				       B_PD_ARBITER_OFF, 1);
1142 		rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0);
1143 	}
1144 }
1145 
1146 static u32 rtw8851b_spur_freq(struct rtw89_dev *rtwdev,
1147 			      const struct rtw89_chan *chan)
1148 {
1149 	u8 center_chan = chan->channel;
1150 
1151 	switch (chan->band_type) {
1152 	case RTW89_BAND_5G:
1153 		if (center_chan == 151 || center_chan == 153 ||
1154 		    center_chan == 155 || center_chan == 163)
1155 			return 5760;
1156 		else if (center_chan == 54 || center_chan == 58)
1157 			return 5280;
1158 		break;
1159 	default:
1160 		break;
1161 	}
1162 
1163 	return 0;
1164 }
1165 
1166 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */
1167 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */
1168 #define MAX_TONE_NUM 2048
1169 
1170 static void rtw8851b_set_csi_tone_idx(struct rtw89_dev *rtwdev,
1171 				      const struct rtw89_chan *chan,
1172 				      enum rtw89_phy_idx phy_idx)
1173 {
1174 	u32 spur_freq;
1175 	s32 freq_diff, csi_idx, csi_tone_idx;
1176 
1177 	spur_freq = rtw8851b_spur_freq(rtwdev, chan);
1178 	if (spur_freq == 0) {
1179 		rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN,
1180 				      0, phy_idx);
1181 		return;
1182 	}
1183 
1184 	freq_diff = (spur_freq - chan->freq) * 1000000;
1185 	csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125);
1186 	s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx);
1187 
1188 	rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_V1, B_SEG0CSI_IDX,
1189 			      csi_tone_idx, phy_idx);
1190 	rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN, 1, phy_idx);
1191 }
1192 
1193 static const struct rtw89_nbi_reg_def rtw8851b_nbi_reg_def = {
1194 	.notch1_idx = {0x46E4, 0xFF},
1195 	.notch1_frac_idx = {0x46E4, 0xC00},
1196 	.notch1_en = {0x46E4, 0x1000},
1197 	.notch2_idx = {0x47A4, 0xFF},
1198 	.notch2_frac_idx = {0x47A4, 0xC00},
1199 	.notch2_en = {0x47A4, 0x1000},
1200 };
1201 
1202 static void rtw8851b_set_nbi_tone_idx(struct rtw89_dev *rtwdev,
1203 				      const struct rtw89_chan *chan)
1204 {
1205 	const struct rtw89_nbi_reg_def *nbi = &rtw8851b_nbi_reg_def;
1206 	s32 nbi_frac_idx, nbi_frac_tone_idx;
1207 	s32 nbi_idx, nbi_tone_idx;
1208 	bool notch2_chk = false;
1209 	u32 spur_freq, fc;
1210 	s32 freq_diff;
1211 
1212 	spur_freq = rtw8851b_spur_freq(rtwdev, chan);
1213 	if (spur_freq == 0) {
1214 		rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1215 				       nbi->notch1_en.mask, 0);
1216 		rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1217 				       nbi->notch2_en.mask, 0);
1218 		return;
1219 	}
1220 
1221 	fc = chan->freq;
1222 	if (chan->band_width == RTW89_CHANNEL_WIDTH_160) {
1223 		fc = (spur_freq > fc) ? fc + 40 : fc - 40;
1224 		if ((fc > spur_freq &&
1225 		     chan->channel < chan->primary_channel) ||
1226 		    (fc < spur_freq &&
1227 		     chan->channel > chan->primary_channel))
1228 			notch2_chk = true;
1229 	}
1230 
1231 	freq_diff = (spur_freq - fc) * 1000000;
1232 	nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5,
1233 					 &nbi_frac_idx);
1234 
1235 	if (chan->band_width == RTW89_CHANNEL_WIDTH_20) {
1236 		s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx);
1237 	} else {
1238 		u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ?
1239 				128 : 256;
1240 
1241 		s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx);
1242 	}
1243 	nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx,
1244 						      CARRIER_SPACING_78_125);
1245 
1246 	if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) {
1247 		rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr,
1248 				       nbi->notch2_idx.mask, nbi_tone_idx);
1249 		rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr,
1250 				       nbi->notch2_frac_idx.mask, nbi_frac_tone_idx);
1251 		rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1252 				       nbi->notch2_en.mask, 0);
1253 		rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1254 				       nbi->notch2_en.mask, 1);
1255 		rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1256 				       nbi->notch1_en.mask, 0);
1257 	} else {
1258 		rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr,
1259 				       nbi->notch1_idx.mask, nbi_tone_idx);
1260 		rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr,
1261 				       nbi->notch1_frac_idx.mask, nbi_frac_tone_idx);
1262 		rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1263 				       nbi->notch1_en.mask, 0);
1264 		rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1265 				       nbi->notch1_en.mask, 1);
1266 		rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1267 				       nbi->notch2_en.mask, 0);
1268 	}
1269 }
1270 
1271 static void rtw8851b_set_cfr(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan)
1272 {
1273 	if (chan->band_type == RTW89_BAND_2G &&
1274 	    chan->band_width == RTW89_CHANNEL_WIDTH_20 &&
1275 	    (chan->channel == 1 || chan->channel == 13)) {
1276 		rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1277 				       B_PATH0_TX_CFR_LGC0, 0xf8);
1278 		rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1279 				       B_PATH0_TX_CFR_LGC1, 0x120);
1280 		rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1281 				       B_PATH0_TX_POLAR_CLIPPING_LGC0, 0x0);
1282 		rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1283 				       B_PATH0_TX_POLAR_CLIPPING_LGC1, 0x3);
1284 	} else {
1285 		rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1286 				       B_PATH0_TX_CFR_LGC0, 0x120);
1287 		rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1288 				       B_PATH0_TX_CFR_LGC1, 0x3ff);
1289 		rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1290 				       B_PATH0_TX_POLAR_CLIPPING_LGC0, 0x3);
1291 		rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1292 				       B_PATH0_TX_POLAR_CLIPPING_LGC1, 0x7);
1293 	}
1294 }
1295 
1296 static void rtw8851b_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1297 			     enum rtw89_phy_idx phy_idx)
1298 {
1299 	u8 pri_ch = chan->pri_ch_idx;
1300 	bool mask_5m_low;
1301 	bool mask_5m_en;
1302 
1303 	switch (chan->band_width) {
1304 	case RTW89_CHANNEL_WIDTH_40:
1305 		/* Prich=1: Mask 5M High, Prich=2: Mask 5M Low */
1306 		mask_5m_en = true;
1307 		mask_5m_low = pri_ch == RTW89_SC_20_LOWER;
1308 		break;
1309 	case RTW89_CHANNEL_WIDTH_80:
1310 		/* Prich=3: Mask 5M High, Prich=4: Mask 5M Low, Else: Disable */
1311 		mask_5m_en = pri_ch == RTW89_SC_20_UPMOST ||
1312 			     pri_ch == RTW89_SC_20_LOWEST;
1313 		mask_5m_low = pri_ch == RTW89_SC_20_LOWEST;
1314 		break;
1315 	default:
1316 		mask_5m_en = false;
1317 		break;
1318 	}
1319 
1320 	if (!mask_5m_en) {
1321 		rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0);
1322 		rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1323 				      B_ASSIGN_SBD_OPT_EN_V1, 0x0, phy_idx);
1324 		return;
1325 	}
1326 
1327 	if (mask_5m_low) {
1328 		rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5);
1329 		rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1330 		rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0);
1331 		rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1);
1332 	} else {
1333 		rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5);
1334 		rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1335 		rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1);
1336 		rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0);
1337 	}
1338 	rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1339 			      B_ASSIGN_SBD_OPT_EN_V1, 0x1, phy_idx);
1340 }
1341 
1342 static void rtw8851b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1343 {
1344 	rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1345 	fsleep(1);
1346 	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1347 	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1348 	rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1349 	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1350 }
1351 
1352 static void rtw8851b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
1353 				 enum rtw89_phy_idx phy_idx, bool en)
1354 {
1355 	if (en) {
1356 		rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1357 				      B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1358 		rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1359 		if (band == RTW89_BAND_2G)
1360 			rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0);
1361 		rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
1362 	} else {
1363 		rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1);
1364 		rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
1365 		rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1366 				      B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1367 		fsleep(1);
1368 		rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1369 	}
1370 }
1371 
1372 static void rtw8851b_bb_reset(struct rtw89_dev *rtwdev,
1373 			      enum rtw89_phy_idx phy_idx)
1374 {
1375 	rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
1376 			       B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x1);
1377 	rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1378 	rtw8851b_bb_reset_all(rtwdev, phy_idx);
1379 	rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
1380 			       B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x3);
1381 	rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1382 }
1383 
1384 static
1385 void rtw8851b_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1386 			   u8 tx_path_en, u8 trsw_tx,
1387 			   u8 trsw_rx, u8 trsw_a, u8 trsw_b)
1388 {
1389 	u32 mask_ofst = 16;
1390 	u32 val;
1391 
1392 	if (path != RF_PATH_A)
1393 		return;
1394 
1395 	mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2;
1396 	val = u32_encode_bits(trsw_a, B_P0_TRSW_A) |
1397 	      u32_encode_bits(trsw_b, B_P0_TRSW_B);
1398 
1399 	rtw89_phy_write32_mask(rtwdev, R_P0_TRSW,
1400 			       (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val);
1401 }
1402 
1403 static void rtw8851b_bb_gpio_init(struct rtw89_dev *rtwdev)
1404 {
1405 	rtw89_phy_write32_set(rtwdev, R_P0_TRSW, B_P0_TRSW_A);
1406 	rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_X);
1407 	rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_SO_A2);
1408 	rtw89_phy_write32(rtwdev, R_RFE_SEL0_BASE, 0x77777777);
1409 	rtw89_phy_write32(rtwdev, R_RFE_SEL32_BASE, 0x77777777);
1410 
1411 	rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff);
1412 	rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0);
1413 	rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0);
1414 	rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0);
1415 
1416 	rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1);
1417 	rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0);
1418 	rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0);
1419 	rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0);
1420 	rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1);
1421 	rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0);
1422 	rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0);
1423 	rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0);
1424 }
1425 
1426 static void rtw8851b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1427 					enum rtw89_phy_idx phy_idx)
1428 {
1429 	u32 addr;
1430 
1431 	for (addr = R_AX_PWR_MACID_LMT_TABLE0;
1432 	     addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
1433 		rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1434 }
1435 
1436 static void rtw8851b_bb_sethw(struct rtw89_dev *rtwdev)
1437 {
1438 	struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1439 
1440 	rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
1441 
1442 	rtw8851b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1443 	rtw8851b_bb_gpio_init(rtwdev);
1444 
1445 	rtw89_write32_clr(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_VALUE);
1446 	rtw89_write32_set(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_EN);
1447 
1448 	/* read these registers after loading BB parameters */
1449 	gain->offset_base[RTW89_PHY_0] =
1450 		rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK);
1451 	gain->rssi_base[RTW89_PHY_0] =
1452 		rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK);
1453 }
1454 
1455 static void rtw8851b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1456 				    enum rtw89_phy_idx phy_idx)
1457 {
1458 	u8 band = chan->band_type, chan_idx;
1459 	bool cck_en = chan->channel <= 14;
1460 	u8 pri_ch_idx = chan->pri_ch_idx;
1461 
1462 	if (cck_en)
1463 		rtw8851b_ctrl_sco_cck(rtwdev,  chan->primary_channel);
1464 
1465 	rtw8851b_ctrl_ch(rtwdev, chan, phy_idx);
1466 	rtw8851b_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1467 	rtw8851b_ctrl_cck_en(rtwdev, cck_en);
1468 	rtw8851b_set_nbi_tone_idx(rtwdev, chan);
1469 	rtw8851b_set_csi_tone_idx(rtwdev, chan, phy_idx);
1470 
1471 	if (chan->band_type == RTW89_BAND_5G) {
1472 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1473 				       B_PATH0_BT_SHARE_V1, 0x0);
1474 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1475 				       B_PATH0_BTG_PATH_V1, 0x0);
1476 		rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1477 		rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1478 		rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1479 				       B_BT_DYN_DC_EST_EN_MSK, 0x0);
1480 		rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1481 	}
1482 
1483 	chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band);
1484 	rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx);
1485 	rtw8851b_5m_mask(rtwdev, chan, phy_idx);
1486 	rtw8851b_set_cfr(rtwdev, chan);
1487 	rtw8851b_bb_reset_all(rtwdev, phy_idx);
1488 }
1489 
1490 static void rtw8851b_set_channel(struct rtw89_dev *rtwdev,
1491 				 const struct rtw89_chan *chan,
1492 				 enum rtw89_mac_idx mac_idx,
1493 				 enum rtw89_phy_idx phy_idx)
1494 {
1495 	rtw8851b_set_channel_mac(rtwdev, chan, mac_idx);
1496 	rtw8851b_set_channel_bb(rtwdev, chan, phy_idx);
1497 	rtw8851b_set_channel_rf(rtwdev, chan, phy_idx);
1498 }
1499 
1500 static void rtw8851b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
1501 				  enum rtw89_rf_path path)
1502 {
1503 	if (en) {
1504 		rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x0);
1505 		rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x0);
1506 	} else {
1507 		rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x1);
1508 		rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x1);
1509 	}
1510 }
1511 
1512 static void rtw8851b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
1513 					 u8 phy_idx)
1514 {
1515 	rtw8851b_tssi_cont_en(rtwdev, en, RF_PATH_A);
1516 }
1517 
1518 static void rtw8851b_adc_en(struct rtw89_dev *rtwdev, bool en)
1519 {
1520 	if (en)
1521 		rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0);
1522 	else
1523 		rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf);
1524 }
1525 
1526 static void rtw8851b_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1527 				      struct rtw89_channel_help_params *p,
1528 				      const struct rtw89_chan *chan,
1529 				      enum rtw89_mac_idx mac_idx,
1530 				      enum rtw89_phy_idx phy_idx)
1531 {
1532 	if (enter) {
1533 		rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL);
1534 		rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
1535 		rtw8851b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0);
1536 		rtw8851b_adc_en(rtwdev, false);
1537 		fsleep(40);
1538 		rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
1539 	} else {
1540 		rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
1541 		rtw8851b_adc_en(rtwdev, true);
1542 		rtw8851b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0);
1543 		rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
1544 		rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en);
1545 	}
1546 }
1547 
1548 static void rtw8851b_rfk_init(struct rtw89_dev *rtwdev)
1549 {
1550 	rtwdev->is_tssi_mode[RF_PATH_A] = false;
1551 	rtwdev->is_tssi_mode[RF_PATH_B] = false;
1552 	rtw8851b_lck_init(rtwdev);
1553 
1554 	rtw8851b_dpk_init(rtwdev);
1555 	rtw8851b_aack(rtwdev);
1556 	rtw8851b_rck(rtwdev);
1557 	rtw8851b_dack(rtwdev);
1558 	rtw8851b_rx_dck(rtwdev, RTW89_PHY_0);
1559 }
1560 
1561 static void rtw8851b_rfk_channel(struct rtw89_dev *rtwdev)
1562 {
1563 	enum rtw89_phy_idx phy_idx = RTW89_PHY_0;
1564 
1565 	rtw8851b_rx_dck(rtwdev, phy_idx);
1566 	rtw8851b_iqk(rtwdev, phy_idx);
1567 	rtw8851b_tssi(rtwdev, phy_idx, true);
1568 	rtw8851b_dpk(rtwdev, phy_idx);
1569 }
1570 
1571 static void rtw8851b_rfk_band_changed(struct rtw89_dev *rtwdev,
1572 				      enum rtw89_phy_idx phy_idx)
1573 {
1574 	rtw8851b_tssi_scan(rtwdev, phy_idx);
1575 }
1576 
1577 static void rtw8851b_rfk_scan(struct rtw89_dev *rtwdev, bool start)
1578 {
1579 	rtw8851b_wifi_scan_notify(rtwdev, start, RTW89_PHY_0);
1580 }
1581 
1582 static void rtw8851b_rfk_track(struct rtw89_dev *rtwdev)
1583 {
1584 	rtw8851b_dpk_track(rtwdev);
1585 	rtw8851b_lck_track(rtwdev);
1586 }
1587 
1588 static u32 rtw8851b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1589 				     enum rtw89_phy_idx phy_idx, s16 ref)
1590 {
1591 	const u16 tssi_16dbm_cw = 0x12c;
1592 	const u8 base_cw_0db = 0x27;
1593 	const s8 ofst_int = 0;
1594 	s16 pwr_s10_3;
1595 	s16 rf_pwr_cw;
1596 	u16 bb_pwr_cw;
1597 	u32 pwr_cw;
1598 	u32 tssi_ofst_cw;
1599 
1600 	pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
1601 	bb_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(2, 0));
1602 	rf_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(8, 3));
1603 	rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
1604 	pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
1605 
1606 	tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
1607 	rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1608 		    "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
1609 		    tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
1610 
1611 	return u32_encode_bits(tssi_ofst_cw, B_DPD_TSSI_CW) |
1612 	       u32_encode_bits(pwr_cw, B_DPD_PWR_CW) |
1613 	       u32_encode_bits(ref, B_DPD_REF);
1614 }
1615 
1616 static void rtw8851b_set_txpwr_ref(struct rtw89_dev *rtwdev,
1617 				   enum rtw89_phy_idx phy_idx)
1618 {
1619 	static const u32 addr[RF_PATH_NUM_8851B] = {0x5800};
1620 	const u32 mask = B_DPD_TSSI_CW | B_DPD_PWR_CW | B_DPD_REF;
1621 	const u8 ofst_ofdm = 0x4;
1622 	const u8 ofst_cck = 0x8;
1623 	const s16 ref_ofdm = 0;
1624 	const s16 ref_cck = 0;
1625 	u32 val;
1626 	u8 i;
1627 
1628 	rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1629 
1630 	rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1631 				     B_AX_PWR_REF, 0x0);
1632 
1633 	rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1634 	val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1635 
1636 	for (i = 0; i < RF_PATH_NUM_8851B; i++)
1637 		rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1638 				      phy_idx);
1639 
1640 	rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1641 	val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1642 
1643 	for (i = 0; i < RF_PATH_NUM_8851B; i++)
1644 		rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1645 				      phy_idx);
1646 }
1647 
1648 static void rtw8851b_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
1649 					  const struct rtw89_chan *chan,
1650 					  u8 tx_shape_idx,
1651 					  enum rtw89_phy_idx phy_idx)
1652 {
1653 #define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2))
1654 #define __DFIR_CFG_MASK 0xffffffff
1655 #define __DFIR_CFG_NR 8
1656 #define __DECL_DFIR_PARAM(_name, _val...) \
1657 	static const u32 param_ ## _name[] = {_val}; \
1658 	static_assert(ARRAY_SIZE(param_ ## _name) == __DFIR_CFG_NR)
1659 
1660 	__DECL_DFIR_PARAM(flat,
1661 			  0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053,
1662 			  0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5);
1663 	__DECL_DFIR_PARAM(sharp,
1664 			  0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090,
1665 			  0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5);
1666 	__DECL_DFIR_PARAM(sharp_14,
1667 			  0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E,
1668 			  0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A);
1669 	u8 ch = chan->channel;
1670 	const u32 *param;
1671 	u32 addr;
1672 	int i;
1673 
1674 	if (ch > 14) {
1675 		rtw89_warn(rtwdev,
1676 			   "set tx shape dfir by unknown ch: %d on 2G\n", ch);
1677 		return;
1678 	}
1679 
1680 	if (ch == 14)
1681 		param = param_sharp_14;
1682 	else
1683 		param = tx_shape_idx == 0 ? param_flat : param_sharp;
1684 
1685 	for (i = 0; i < __DFIR_CFG_NR; i++) {
1686 		addr = __DFIR_CFG_ADDR(i);
1687 		rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1688 			    "set tx shape dfir: 0x%x: 0x%x\n", addr, param[i]);
1689 		rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i],
1690 				      phy_idx);
1691 	}
1692 
1693 #undef __DECL_DFIR_PARAM
1694 #undef __DFIR_CFG_NR
1695 #undef __DFIR_CFG_MASK
1696 #undef __DECL_CFG_ADDR
1697 }
1698 
1699 static void rtw8851b_set_tx_shape(struct rtw89_dev *rtwdev,
1700 				  const struct rtw89_chan *chan,
1701 				  enum rtw89_phy_idx phy_idx)
1702 {
1703 	u8 band = chan->band_type;
1704 	u8 regd = rtw89_regd_get(rtwdev, band);
1705 	u8 tx_shape_cck = rtw89_8851b_tx_shape[band][RTW89_RS_CCK][regd];
1706 	u8 tx_shape_ofdm = rtw89_8851b_tx_shape[band][RTW89_RS_OFDM][regd];
1707 
1708 	if (band == RTW89_BAND_2G)
1709 		rtw8851b_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx);
1710 
1711 	rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG,
1712 			       tx_shape_ofdm);
1713 }
1714 
1715 static void rtw8851b_set_txpwr(struct rtw89_dev *rtwdev,
1716 			       const struct rtw89_chan *chan,
1717 			       enum rtw89_phy_idx phy_idx)
1718 {
1719 	rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
1720 	rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
1721 	rtw8851b_set_tx_shape(rtwdev, chan, phy_idx);
1722 	rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
1723 	rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1724 }
1725 
1726 static void rtw8851b_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
1727 				    enum rtw89_phy_idx phy_idx)
1728 {
1729 	rtw8851b_set_txpwr_ref(rtwdev, phy_idx);
1730 }
1731 
1732 static
1733 void rtw8851b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1734 				     s8 pw_ofst, enum rtw89_mac_idx mac_idx)
1735 {
1736 	u32 reg;
1737 
1738 	if (pw_ofst < -16 || pw_ofst > 15) {
1739 		rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
1740 		return;
1741 	}
1742 
1743 	reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx);
1744 	rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
1745 
1746 	reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx);
1747 	rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst);
1748 
1749 	pw_ofst = max_t(s8, pw_ofst - 3, -16);
1750 	reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx);
1751 	rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst);
1752 }
1753 
1754 static int
1755 rtw8851b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1756 {
1757 	int ret;
1758 
1759 	ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
1760 	if (ret)
1761 		return ret;
1762 
1763 	ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
1764 	if (ret)
1765 		return ret;
1766 
1767 	ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
1768 	if (ret)
1769 		return ret;
1770 
1771 	rtw8851b_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
1772 						   RTW89_MAC_1 : RTW89_MAC_0);
1773 
1774 	return 0;
1775 }
1776 
1777 static void rtw8851b_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en)
1778 {
1779 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1780 
1781 	rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8851b_btc_preagc_en_defs_tbl :
1782 						 &rtw8851b_btc_preagc_dis_defs_tbl);
1783 
1784 	if (!bt_en) {
1785 		if (chan->band_type == RTW89_BAND_2G) {
1786 			rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1787 					       B_PATH0_G_LNA6_OP1DB_V1, 0x20);
1788 			rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1789 					       B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x30);
1790 		} else {
1791 			rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1792 					       B_PATH0_G_LNA6_OP1DB_V1, 0x1a);
1793 			rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1794 					       B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a);
1795 		}
1796 	}
1797 }
1798 
1799 static void rtw8851b_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
1800 {
1801 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1802 
1803 	if (btg) {
1804 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1805 				       B_PATH0_BT_SHARE_V1, 0x1);
1806 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1807 				       B_PATH0_BTG_PATH_V1, 0x1);
1808 		rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1809 				       B_PATH0_G_LNA6_OP1DB_V1, 0x20);
1810 		rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1811 				       B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x30);
1812 		rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
1813 		rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1);
1814 		rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x1);
1815 		rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1816 				       B_BT_DYN_DC_EST_EN_MSK, 0x1);
1817 		rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1);
1818 	} else {
1819 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1820 				       B_PATH0_BT_SHARE_V1, 0x0);
1821 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1822 				       B_PATH0_BTG_PATH_V1, 0x0);
1823 		if (chan->band_type == RTW89_BAND_2G) {
1824 			rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1825 					       B_PATH0_G_LNA6_OP1DB_V1, 0x80);
1826 			rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1827 					       B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80);
1828 		} else {
1829 			rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1830 					       B_PATH0_G_LNA6_OP1DB_V1, 0x1a);
1831 			rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1832 					       B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a);
1833 		}
1834 		rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc);
1835 		rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1836 		rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1837 		rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1838 				       B_BT_DYN_DC_EST_EN_MSK, 0x1);
1839 		rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1840 	}
1841 }
1842 
1843 static void rtw8851b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev,
1844 				     enum rtw89_rf_path_bit rx_path)
1845 {
1846 	const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1847 	u32 rst_mask0;
1848 
1849 	if (rx_path == RF_A) {
1850 		rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1);
1851 		rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1);
1852 		rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1);
1853 		rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1854 		rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1855 		rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
1856 		rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1857 		rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1858 	}
1859 
1860 	rtw8851b_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0);
1861 
1862 	rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
1863 	if (rx_path == RF_A) {
1864 		rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
1865 		rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
1866 	}
1867 }
1868 
1869 static void rtw8851b_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
1870 {
1871 	rtw8851b_bb_ctrl_rx_path(rtwdev, RF_A);
1872 
1873 	if (rtwdev->hal.rx_nss == 1) {
1874 		rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1875 		rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1876 		rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1877 		rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1878 	}
1879 
1880 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
1881 }
1882 
1883 static u8 rtw8851b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
1884 {
1885 	if (rtwdev->is_tssi_mode[rf_path]) {
1886 		u32 addr = R_TSSI_THER + (rf_path << 13);
1887 
1888 		return rtw89_phy_read32_mask(rtwdev, addr, B_TSSI_THER);
1889 	}
1890 
1891 	rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1892 	rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
1893 	rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1894 
1895 	fsleep(200);
1896 
1897 	return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
1898 }
1899 
1900 static void rtw8851b_btc_set_rfe(struct rtw89_dev *rtwdev)
1901 {
1902 	struct rtw89_btc *btc = &rtwdev->btc;
1903 	struct rtw89_btc_module *module = &btc->mdinfo;
1904 
1905 	module->rfe_type = rtwdev->efuse.rfe_type;
1906 	module->cv = rtwdev->hal.cv;
1907 	module->bt_solo = 0;
1908 	module->switch_type = BTC_SWITCH_INTERNAL;
1909 	module->ant.isolation = 10;
1910 	module->kt_ver_adie = rtwdev->hal.acv;
1911 
1912 	if (module->rfe_type == 0)
1913 		return;
1914 
1915 	/* rfe_type 3*n+1: 1-Ant(shared),
1916 	 *	    3*n+2: 2-Ant+Div(non-shared),
1917 	 *	    3*n+3: 2-Ant+no-Div(non-shared)
1918 	 */
1919 	module->ant.num = (module->rfe_type % 3 == 1) ? 1 : 2;
1920 	/* WL-1ss at S0, btg at s0 (On 1 WL RF) */
1921 	module->ant.single_pos = RF_PATH_A;
1922 	module->ant.btg_pos = RF_PATH_A;
1923 	module->ant.stream_cnt = 1;
1924 
1925 	if (module->ant.num == 1) {
1926 		module->ant.type = BTC_ANT_SHARED;
1927 		module->bt_pos = BTC_BT_BTG;
1928 		module->wa_type = 1;
1929 		module->ant.diversity = 0;
1930 	} else { /* ant.num == 2 */
1931 		module->ant.type = BTC_ANT_DEDICATED;
1932 		module->bt_pos = BTC_BT_ALONE;
1933 		module->switch_type = BTC_SWITCH_EXTERNAL;
1934 		module->wa_type = 0;
1935 		if (module->rfe_type % 3 == 2)
1936 			module->ant.diversity = 1;
1937 	}
1938 }
1939 
1940 static
1941 void rtw8851b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
1942 {
1943 	if (group > BTC_BT_SS_GROUP)
1944 		group--; /* Tx-group=1, Rx-group=2 */
1945 
1946 	if (rtwdev->btc.mdinfo.ant.type == BTC_ANT_SHARED) /* 1-Ant */
1947 		group += 3;
1948 
1949 	rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
1950 	rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
1951 }
1952 
1953 static void rtw8851b_btc_init_cfg(struct rtw89_dev *rtwdev)
1954 {
1955 	static const struct rtw89_mac_ax_coex coex_params = {
1956 		.pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
1957 		.direction = RTW89_MAC_AX_COEX_INNER,
1958 	};
1959 	const struct rtw89_chip_info *chip = rtwdev->chip;
1960 	struct rtw89_btc *btc = &rtwdev->btc;
1961 	struct rtw89_btc_module *module = &btc->mdinfo;
1962 	struct rtw89_btc_ant_info *ant = &module->ant;
1963 	u8 path, path_min, path_max;
1964 
1965 	/* PTA init  */
1966 	rtw89_mac_coex_init(rtwdev, &coex_params);
1967 
1968 	/* set WL Tx response = Hi-Pri */
1969 	chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
1970 	chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
1971 
1972 	/* for 1-Ant && 1-ss case: only 1-path */
1973 	if (ant->stream_cnt == 1) {
1974 		path_min = ant->single_pos;
1975 		path_max = path_min;
1976 	} else {
1977 		path_min = RF_PATH_A;
1978 		path_max = RF_PATH_B;
1979 	}
1980 
1981 	for (path = path_min; path <= path_max; path++) {
1982 		/* set rf gnt-debug off */
1983 		rtw89_write_rf(rtwdev, path, RR_WLSEL, RFREG_MASK, 0x0);
1984 
1985 		/* set DEBUG_LUT_RFMODE_MASK = 1 to start trx-mask-setup */
1986 		rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, BIT(17));
1987 
1988 		/* if GNT_WL=0 && BT=SS_group --> WL Tx/Rx = THRU  */
1989 		rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_SS_GROUP, 0x5ff);
1990 
1991 		/* if GNT_WL=0 && BT=Rx_group --> WL-Rx = THRU + WL-Tx = MASK */
1992 		rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_RX_GROUP, 0x5df);
1993 
1994 		/* if GNT_WL = 0 && BT = Tx_group -->
1995 		 * Shared-Ant && BTG-path:WL mask(0x55f), others:WL THRU(0x5ff)
1996 		 */
1997 		if (ant->type == BTC_ANT_SHARED && ant->btg_pos == path)
1998 			rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x55f);
1999 		else
2000 			rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x5ff);
2001 
2002 		/* set DEBUG_LUT_RFMODE_MASK = 0 to stop trx-mask-setup */
2003 		rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0);
2004 	}
2005 
2006 	/* set PTA break table */
2007 	rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
2008 
2009 	/* enable BT counter 0xda40[16,2] = 2b'11 */
2010 	rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
2011 
2012 	btc->cx.wl.status.map.init_ok = true;
2013 }
2014 
2015 static
2016 void rtw8851b_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
2017 {
2018 	u32 bitmap;
2019 	u32 reg;
2020 
2021 	switch (map) {
2022 	case BTC_PRI_MASK_TX_RESP:
2023 		reg = R_BTC_BT_COEX_MSK_TABLE;
2024 		bitmap = B_BTC_PRI_MASK_TX_RESP_V1;
2025 		break;
2026 	case BTC_PRI_MASK_BEACON:
2027 		reg = R_AX_WL_PRI_MSK;
2028 		bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ;
2029 		break;
2030 	case BTC_PRI_MASK_RX_CCK:
2031 		reg = R_BTC_BT_COEX_MSK_TABLE;
2032 		bitmap = B_BTC_PRI_MASK_RXCCK_V1;
2033 		break;
2034 	default:
2035 		return;
2036 	}
2037 
2038 	if (state)
2039 		rtw89_write32_set(rtwdev, reg, bitmap);
2040 	else
2041 		rtw89_write32_clr(rtwdev, reg, bitmap);
2042 }
2043 
2044 union rtw8851b_btc_wl_txpwr_ctrl {
2045 	u32 txpwr_val;
2046 	struct {
2047 		union {
2048 			u16 ctrl_all_time;
2049 			struct {
2050 				s16 data:9;
2051 				u16 rsvd:6;
2052 				u16 flag:1;
2053 			} all_time;
2054 		};
2055 		union {
2056 			u16 ctrl_gnt_bt;
2057 			struct {
2058 				s16 data:9;
2059 				u16 rsvd:7;
2060 			} gnt_bt;
2061 		};
2062 	};
2063 } __packed;
2064 
2065 static void
2066 rtw8851b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
2067 {
2068 	union rtw8851b_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val };
2069 	s32 val;
2070 
2071 #define __write_ctrl(_reg, _msk, _val, _en, _cond)		\
2072 do {								\
2073 	u32 _wrt = FIELD_PREP(_msk, _val);			\
2074 	BUILD_BUG_ON(!!(_msk & _en));				\
2075 	if (_cond)						\
2076 		_wrt |= _en;					\
2077 	else							\
2078 		_wrt &= ~_en;					\
2079 	rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg,	\
2080 				     _msk | _en, _wrt);		\
2081 } while (0)
2082 
2083 	switch (arg.ctrl_all_time) {
2084 	case 0xffff:
2085 		val = 0;
2086 		break;
2087 	default:
2088 		val = arg.all_time.data;
2089 		break;
2090 	}
2091 
2092 	__write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK,
2093 		     val, B_AX_FORCE_PWR_BY_RATE_EN,
2094 		     arg.ctrl_all_time != 0xffff);
2095 
2096 	switch (arg.ctrl_gnt_bt) {
2097 	case 0xffff:
2098 		val = 0;
2099 		break;
2100 	default:
2101 		val = arg.gnt_bt.data;
2102 		break;
2103 	}
2104 
2105 	__write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val,
2106 		     B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff);
2107 
2108 #undef __write_ctrl
2109 }
2110 
2111 static
2112 s8 rtw8851b_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
2113 {
2114 	val = clamp_t(s8, val, -100, 0) + 100;
2115 	val = min(val + 6, 100); /* compensate offset */
2116 
2117 	return val;
2118 }
2119 
2120 static
2121 void rtw8851b_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
2122 {
2123 	/* Feature move to firmware */
2124 }
2125 
2126 static void rtw8851b_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
2127 {
2128 	struct rtw89_btc *btc = &rtwdev->btc;
2129 	struct rtw89_btc_ant_info *ant = &btc->mdinfo.ant;
2130 
2131 	rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWE, RFREG_MASK, 0x80000);
2132 	rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWA, RFREG_MASK, 0x1);
2133 	rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWD1, RFREG_MASK, 0x110);
2134 
2135 	/* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
2136 	if (state)
2137 		rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWD0, RFREG_MASK, 0x179c);
2138 	else
2139 		rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWD0, RFREG_MASK, 0x208);
2140 
2141 	rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWE, RFREG_MASK, 0x0);
2142 }
2143 
2144 #define LNA2_51B_MA 0x700
2145 
2146 static const struct rtw89_reg2_def btc_8851b_rf_0[] = {{0x2, 0x0}};
2147 static const struct rtw89_reg2_def btc_8851b_rf_1[] = {{0x2, 0x1}};
2148 
2149 static void rtw8851b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
2150 {
2151 	/* To improve BT ACI in co-rx
2152 	 * level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB
2153 	 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB
2154 	 */
2155 	struct rtw89_btc *btc = &rtwdev->btc;
2156 	struct rtw89_btc_ant_info *ant = &btc->mdinfo.ant;
2157 	const struct rtw89_reg2_def *rf;
2158 	u32 n, i, val;
2159 
2160 	switch (level) {
2161 	case 0: /* original */
2162 	default:
2163 		btc->dm.wl_lna2 = 0;
2164 		break;
2165 	case 1: /* for FDD free-run */
2166 		btc->dm.wl_lna2 = 0;
2167 		break;
2168 	case 2: /* for BTG Co-Rx*/
2169 		btc->dm.wl_lna2 = 1;
2170 		break;
2171 	}
2172 
2173 	if (btc->dm.wl_lna2 == 0) {
2174 		rf = btc_8851b_rf_0;
2175 		n = ARRAY_SIZE(btc_8851b_rf_0);
2176 	} else {
2177 		rf = btc_8851b_rf_1;
2178 		n = ARRAY_SIZE(btc_8851b_rf_1);
2179 	}
2180 
2181 	for (i = 0; i < n; i++, rf++) {
2182 		val = rf->data;
2183 		/* bit[10] = 1 if non-shared-ant for 8851b */
2184 		if (btc->mdinfo.ant.type == BTC_ANT_DEDICATED)
2185 			val |= 0x4;
2186 
2187 		rtw89_write_rf(rtwdev, ant->btg_pos, rf->addr, LNA2_51B_MA, val);
2188 	}
2189 }
2190 
2191 static void rtw8851b_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2192 					 struct rtw89_rx_phy_ppdu *phy_ppdu,
2193 					 struct ieee80211_rx_status *status)
2194 {
2195 	u16 chan = phy_ppdu->chan_idx;
2196 	enum nl80211_band band;
2197 	u8 ch;
2198 
2199 	if (chan == 0)
2200 		return;
2201 
2202 	rtw89_decode_chan_idx(rtwdev, chan, &ch, &band);
2203 	status->freq = ieee80211_channel_to_frequency(ch, band);
2204 	status->band = band;
2205 }
2206 
2207 static void rtw8851b_query_ppdu(struct rtw89_dev *rtwdev,
2208 				struct rtw89_rx_phy_ppdu *phy_ppdu,
2209 				struct ieee80211_rx_status *status)
2210 {
2211 	u8 path;
2212 	u8 *rx_power = phy_ppdu->rssi;
2213 
2214 	status->signal = RTW89_RSSI_RAW_TO_DBM(rx_power[RF_PATH_A]);
2215 
2216 	for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2217 		status->chains |= BIT(path);
2218 		status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
2219 	}
2220 	if (phy_ppdu->valid)
2221 		rtw8851b_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2222 }
2223 
2224 static int rtw8851b_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
2225 {
2226 	int ret;
2227 
2228 	rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
2229 			 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2230 	rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2231 	rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2232 	rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2233 
2234 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7,
2235 				      FULL_BIT_MASK);
2236 	if (ret)
2237 		return ret;
2238 
2239 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7,
2240 				      FULL_BIT_MASK);
2241 	if (ret)
2242 		return ret;
2243 
2244 	rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE);
2245 
2246 	return 0;
2247 }
2248 
2249 static int rtw8851b_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
2250 {
2251 	u8 wl_rfc_s0;
2252 	u8 wl_rfc_s1;
2253 	int ret;
2254 
2255 	rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
2256 			 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2257 
2258 	ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0);
2259 	if (ret)
2260 		return ret;
2261 	wl_rfc_s0 &= ~XTAL_SI_RF00S_EN;
2262 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0,
2263 				      FULL_BIT_MASK);
2264 	if (ret)
2265 		return ret;
2266 
2267 	ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1);
2268 	if (ret)
2269 		return ret;
2270 	wl_rfc_s1 &= ~XTAL_SI_RF10S_EN;
2271 	ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1,
2272 				      FULL_BIT_MASK);
2273 	return ret;
2274 }
2275 
2276 static const struct rtw89_chip_ops rtw8851b_chip_ops = {
2277 	.enable_bb_rf		= rtw8851b_mac_enable_bb_rf,
2278 	.disable_bb_rf		= rtw8851b_mac_disable_bb_rf,
2279 	.bb_reset		= rtw8851b_bb_reset,
2280 	.bb_sethw		= rtw8851b_bb_sethw,
2281 	.read_rf		= rtw89_phy_read_rf_v1,
2282 	.write_rf		= rtw89_phy_write_rf_v1,
2283 	.set_channel		= rtw8851b_set_channel,
2284 	.set_channel_help	= rtw8851b_set_channel_help,
2285 	.read_efuse		= rtw8851b_read_efuse,
2286 	.read_phycap		= rtw8851b_read_phycap,
2287 	.fem_setup		= NULL,
2288 	.rfe_gpio		= rtw8851b_rfe_gpio,
2289 	.rfk_init		= rtw8851b_rfk_init,
2290 	.rfk_channel		= rtw8851b_rfk_channel,
2291 	.rfk_band_changed	= rtw8851b_rfk_band_changed,
2292 	.rfk_scan		= rtw8851b_rfk_scan,
2293 	.rfk_track		= rtw8851b_rfk_track,
2294 	.power_trim		= rtw8851b_power_trim,
2295 	.set_txpwr		= rtw8851b_set_txpwr,
2296 	.set_txpwr_ctrl		= rtw8851b_set_txpwr_ctrl,
2297 	.init_txpwr_unit	= rtw8851b_init_txpwr_unit,
2298 	.get_thermal		= rtw8851b_get_thermal,
2299 	.ctrl_btg		= rtw8851b_ctrl_btg,
2300 	.query_ppdu		= rtw8851b_query_ppdu,
2301 	.bb_ctrl_btc_preagc	= rtw8851b_bb_ctrl_btc_preagc,
2302 	.cfg_txrx_path		= rtw8851b_bb_cfg_txrx_path,
2303 	.set_txpwr_ul_tb_offset	= rtw8851b_set_txpwr_ul_tb_offset,
2304 	.pwr_on_func		= rtw8851b_pwr_on_func,
2305 	.pwr_off_func		= rtw8851b_pwr_off_func,
2306 	.query_rxdesc		= rtw89_core_query_rxdesc,
2307 	.fill_txdesc		= rtw89_core_fill_txdesc,
2308 	.fill_txdesc_fwcmd	= rtw89_core_fill_txdesc,
2309 	.cfg_ctrl_path		= rtw89_mac_cfg_ctrl_path,
2310 	.mac_cfg_gnt		= rtw89_mac_cfg_gnt,
2311 	.stop_sch_tx		= rtw89_mac_stop_sch_tx,
2312 	.resume_sch_tx		= rtw89_mac_resume_sch_tx,
2313 	.h2c_dctl_sec_cam	= NULL,
2314 
2315 	.btc_set_rfe		= rtw8851b_btc_set_rfe,
2316 	.btc_init_cfg		= rtw8851b_btc_init_cfg,
2317 	.btc_set_wl_pri		= rtw8851b_btc_set_wl_pri,
2318 	.btc_set_wl_txpwr_ctrl	= rtw8851b_btc_set_wl_txpwr_ctrl,
2319 	.btc_get_bt_rssi	= rtw8851b_btc_get_bt_rssi,
2320 	.btc_update_bt_cnt	= rtw8851b_btc_update_bt_cnt,
2321 	.btc_wl_s1_standby	= rtw8851b_btc_wl_s1_standby,
2322 	.btc_set_wl_rx_gain	= rtw8851b_btc_set_wl_rx_gain,
2323 	.btc_set_policy		= rtw89_btc_set_policy_v1,
2324 };
2325 
2326 #ifdef CONFIG_PM
2327 static const struct wiphy_wowlan_support rtw_wowlan_stub_8851b = {
2328 	.flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
2329 	.n_patterns = RTW89_MAX_PATTERN_NUM,
2330 	.pattern_max_len = RTW89_MAX_PATTERN_SIZE,
2331 	.pattern_min_len = 1,
2332 };
2333 #endif
2334 
2335 const struct rtw89_chip_info rtw8851b_chip_info = {
2336 	.chip_id		= RTL8851B,
2337 	.ops			= &rtw8851b_chip_ops,
2338 	.fw_basename		= RTW8851B_FW_BASENAME,
2339 	.fw_format_max		= RTW8851B_FW_FORMAT_MAX,
2340 	.try_ce_fw		= true,
2341 	.fifo_size		= 196608,
2342 	.small_fifo_size	= true,
2343 	.dle_scc_rsvd_size	= 98304,
2344 	.max_amsdu_limit	= 3500,
2345 	.dis_2g_40m_ul_ofdma	= true,
2346 	.rsvd_ple_ofst		= 0x2f800,
2347 	.hfc_param_ini		= rtw8851b_hfc_param_ini_pcie,
2348 	.dle_mem		= rtw8851b_dle_mem_pcie,
2349 	.wde_qempty_acq_num     = 4,
2350 	.wde_qempty_mgq_sel     = 4,
2351 	.rf_base_addr		= {0xe000},
2352 	.pwr_on_seq		= NULL,
2353 	.pwr_off_seq		= NULL,
2354 	.bb_table		= &rtw89_8851b_phy_bb_table,
2355 	.bb_gain_table		= &rtw89_8851b_phy_bb_gain_table,
2356 	.rf_table		= {&rtw89_8851b_phy_radioa_table,},
2357 	.nctl_table		= &rtw89_8851b_phy_nctl_table,
2358 	.nctl_post_table	= &rtw8851b_nctl_post_defs_tbl,
2359 	.byr_table		= &rtw89_8851b_byr_table,
2360 	.dflt_parms		= &rtw89_8851b_dflt_parms,
2361 	.rfe_parms_conf		= rtw89_8851b_rfe_parms_conf,
2362 	.txpwr_factor_rf	= 2,
2363 	.txpwr_factor_mac	= 1,
2364 	.dig_table		= NULL,
2365 	.dig_regs		= &rtw8851b_dig_regs,
2366 	.tssi_dbw_table		= NULL,
2367 	.support_chanctx_num	= 0,
2368 	.support_bands		= BIT(NL80211_BAND_2GHZ) |
2369 				  BIT(NL80211_BAND_5GHZ),
2370 	.support_bw160		= false,
2371 	.support_unii4		= true,
2372 	.support_ul_tb_ctrl	= true,
2373 	.hw_sec_hdr		= false,
2374 	.rf_path_num		= 1,
2375 	.tx_nss			= 1,
2376 	.rx_nss			= 1,
2377 	.acam_num		= 32,
2378 	.bcam_num		= 20,
2379 	.scam_num		= 128,
2380 	.bacam_num		= 2,
2381 	.bacam_dynamic_num	= 4,
2382 	.bacam_ver		= RTW89_BACAM_V0,
2383 	.sec_ctrl_efuse_size	= 4,
2384 	.physical_efuse_size	= 1216,
2385 	.logical_efuse_size	= 2048,
2386 	.limit_efuse_size	= 1280,
2387 	.dav_phy_efuse_size	= 0,
2388 	.dav_log_efuse_size	= 0,
2389 	.phycap_addr		= 0x580,
2390 	.phycap_size		= 128,
2391 	.para_ver		= 0,
2392 	.wlcx_desired		= 0x06000000,
2393 	.btcx_desired		= 0x7,
2394 	.scbd			= 0x1,
2395 	.mailbox		= 0x1,
2396 
2397 	.afh_guard_ch		= 6,
2398 	.wl_rssi_thres		= rtw89_btc_8851b_wl_rssi_thres,
2399 	.bt_rssi_thres		= rtw89_btc_8851b_bt_rssi_thres,
2400 	.rssi_tol		= 2,
2401 	.mon_reg_num		= ARRAY_SIZE(rtw89_btc_8851b_mon_reg),
2402 	.mon_reg		= rtw89_btc_8851b_mon_reg,
2403 	.rf_para_ulink_num	= ARRAY_SIZE(rtw89_btc_8851b_rf_ul),
2404 	.rf_para_ulink		= rtw89_btc_8851b_rf_ul,
2405 	.rf_para_dlink_num	= ARRAY_SIZE(rtw89_btc_8851b_rf_dl),
2406 	.rf_para_dlink		= rtw89_btc_8851b_rf_dl,
2407 	.ps_mode_supported	= BIT(RTW89_PS_MODE_RFOFF) |
2408 				  BIT(RTW89_PS_MODE_CLK_GATED),
2409 	.low_power_hci_modes	= 0,
2410 	.h2c_cctl_func_id	= H2C_FUNC_MAC_CCTLINFO_UD,
2411 	.hci_func_en_addr	= R_AX_HCI_FUNC_EN,
2412 	.h2c_desc_size		= sizeof(struct rtw89_txwd_body),
2413 	.txwd_body_size		= sizeof(struct rtw89_txwd_body),
2414 	.h2c_ctrl_reg		= R_AX_H2CREG_CTRL,
2415 	.h2c_counter_reg	= {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
2416 	.h2c_regs		= rtw8851b_h2c_regs,
2417 	.c2h_ctrl_reg		= R_AX_C2HREG_CTRL,
2418 	.c2h_counter_reg	= {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
2419 	.c2h_regs		= rtw8851b_c2h_regs,
2420 	.page_regs		= &rtw8851b_page_regs,
2421 	.cfo_src_fd		= true,
2422 	.cfo_hw_comp		= true,
2423 	.dcfo_comp		= &rtw8851b_dcfo_comp,
2424 	.dcfo_comp_sft		= 12,
2425 	.imr_info		= &rtw8851b_imr_info,
2426 	.rrsr_cfgs		= &rtw8851b_rrsr_cfgs,
2427 	.bss_clr_map_reg	= R_BSS_CLR_MAP_V1,
2428 	.dma_ch_mask		= BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |
2429 				  BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
2430 				  BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
2431 	.edcca_lvl_reg		= R_SEG0R_EDCCA_LVL_V1,
2432 #ifdef CONFIG_PM
2433 	.wowlan_stub		= &rtw_wowlan_stub_8851b,
2434 #endif
2435 	.xtal_info		= &rtw8851b_xtal_info,
2436 };
2437 EXPORT_SYMBOL(rtw8851b_chip_info);
2438 
2439 MODULE_FIRMWARE(RTW8851B_MODULE_FIRMWARE);
2440 MODULE_AUTHOR("Realtek Corporation");
2441 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8851B driver");
2442 MODULE_LICENSE("Dual BSD/GPL");
2443