1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "debug.h" 7 #include "fw.h" 8 #include "mac.h" 9 #include "phy.h" 10 #include "ps.h" 11 #include "reg.h" 12 #include "sar.h" 13 #include "util.h" 14 15 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, 16 const struct rtw89_ra_report *report) 17 { 18 u32 bit_rate = report->bit_rate; 19 20 /* lower than ofdm, do not aggregate */ 21 if (bit_rate < 550) 22 return 1; 23 24 /* avoid AMSDU for legacy rate */ 25 if (report->might_fallback_legacy) 26 return 1; 27 28 /* lower than 20M vht 2ss mcs8, make it small */ 29 if (bit_rate < 1800) 30 return 1200; 31 32 /* lower than 40M vht 2ss mcs9, make it medium */ 33 if (bit_rate < 4000) 34 return 2600; 35 36 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ 37 if (bit_rate < 7000) 38 return 3500; 39 40 return rtwdev->chip->max_amsdu_limit; 41 } 42 43 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) 44 { 45 u64 ra_mask = 0; 46 u8 mcs_cap; 47 int i, nss; 48 49 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { 50 mcs_cap = mcs_map & 0x3; 51 switch (mcs_cap) { 52 case 2: 53 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; 54 break; 55 case 1: 56 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; 57 break; 58 case 0: 59 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; 60 break; 61 default: 62 break; 63 } 64 } 65 66 return ra_mask; 67 } 68 69 static u64 get_he_ra_mask(struct ieee80211_sta *sta) 70 { 71 struct ieee80211_sta_he_cap cap = sta->deflink.he_cap; 72 u16 mcs_map; 73 74 switch (sta->deflink.bandwidth) { 75 case IEEE80211_STA_RX_BW_160: 76 if (cap.he_cap_elem.phy_cap_info[0] & 77 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) 78 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); 79 else 80 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); 81 break; 82 default: 83 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); 84 } 85 86 /* MCS11, MCS9, MCS7 */ 87 return get_mcs_ra_mask(mcs_map, 11, 2); 88 } 89 90 #define RA_FLOOR_TABLE_SIZE 7 91 #define RA_FLOOR_UP_GAP 3 92 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, 93 u8 ratr_state) 94 { 95 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; 96 u8 rssi_lv = 0; 97 u8 i; 98 99 rssi >>= 1; 100 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 101 if (i >= ratr_state) 102 rssi_lv_t[i] += RA_FLOOR_UP_GAP; 103 if (rssi < rssi_lv_t[i]) { 104 rssi_lv = i; 105 break; 106 } 107 } 108 if (rssi_lv == 0) 109 return 0xffffffffffffffffULL; 110 else if (rssi_lv == 1) 111 return 0xfffffffffffffff0ULL; 112 else if (rssi_lv == 2) 113 return 0xffffffffffffefe0ULL; 114 else if (rssi_lv == 3) 115 return 0xffffffffffffcfc0ULL; 116 else if (rssi_lv == 4) 117 return 0xffffffffffff8f80ULL; 118 else if (rssi_lv >= 5) 119 return 0xffffffffffff0f00ULL; 120 121 return 0xffffffffffffffffULL; 122 } 123 124 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak) 125 { 126 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 127 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 128 129 if (ra_mask == 0) 130 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 131 132 return ra_mask; 133 } 134 135 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 136 { 137 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 138 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 139 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 140 enum nl80211_band band; 141 u64 cfg_mask; 142 143 if (!rtwsta->use_cfg_mask) 144 return -1; 145 146 switch (chan->band_type) { 147 case RTW89_BAND_2G: 148 band = NL80211_BAND_2GHZ; 149 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, 150 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); 151 break; 152 case RTW89_BAND_5G: 153 band = NL80211_BAND_5GHZ; 154 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, 155 RA_MASK_OFDM_RATES); 156 break; 157 case RTW89_BAND_6G: 158 band = NL80211_BAND_6GHZ; 159 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy, 160 RA_MASK_OFDM_RATES); 161 break; 162 default: 163 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type); 164 return -1; 165 } 166 167 if (sta->deflink.he_cap.has_he) { 168 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], 169 RA_MASK_HE_1SS_RATES); 170 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], 171 RA_MASK_HE_2SS_RATES); 172 } else if (sta->deflink.vht_cap.vht_supported) { 173 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 174 RA_MASK_VHT_1SS_RATES); 175 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 176 RA_MASK_VHT_2SS_RATES); 177 } else if (sta->deflink.ht_cap.ht_supported) { 178 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 179 RA_MASK_HT_1SS_RATES); 180 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 181 RA_MASK_HT_2SS_RATES); 182 } 183 184 return cfg_mask; 185 } 186 187 static const u64 188 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, 189 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; 190 static const u64 191 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 192 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; 193 static const u64 194 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, 195 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; 196 197 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev, 198 struct rtw89_sta *rtwsta, 199 bool *fix_giltf_en, u8 *fix_giltf) 200 { 201 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 202 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 203 u8 band = chan->band_type; 204 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 205 u8 he_gi = mask->control[nl_band].he_gi; 206 u8 he_ltf = mask->control[nl_band].he_ltf; 207 208 if (!rtwsta->use_cfg_mask) 209 return; 210 211 if (he_ltf == 2 && he_gi == 2) { 212 *fix_giltf = RTW89_GILTF_LGI_4XHE32; 213 } else if (he_ltf == 2 && he_gi == 0) { 214 *fix_giltf = RTW89_GILTF_SGI_4XHE08; 215 } else if (he_ltf == 1 && he_gi == 1) { 216 *fix_giltf = RTW89_GILTF_2XHE16; 217 } else if (he_ltf == 1 && he_gi == 0) { 218 *fix_giltf = RTW89_GILTF_2XHE08; 219 } else if (he_ltf == 0 && he_gi == 1) { 220 *fix_giltf = RTW89_GILTF_1XHE16; 221 } else if (he_ltf == 0 && he_gi == 0) { 222 *fix_giltf = RTW89_GILTF_1XHE08; 223 } else { 224 *fix_giltf_en = false; 225 return; 226 } 227 228 *fix_giltf_en = true; 229 } 230 231 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 232 struct ieee80211_sta *sta, bool csi) 233 { 234 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 235 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 236 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 237 struct rtw89_ra_info *ra = &rtwsta->ra; 238 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 239 struct ieee80211_vif *vif = rtwvif_to_vif(rtwsta->rtwvif); 240 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; 241 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 242 u64 ra_mask = 0; 243 u64 ra_mask_bak; 244 u8 mode = 0; 245 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; 246 u8 bw_mode = 0; 247 u8 stbc_en = 0; 248 u8 ldpc_en = 0; 249 u8 fix_giltf = 0; 250 u8 i; 251 bool sgi = false; 252 bool fix_giltf_en = false; 253 254 memset(ra, 0, sizeof(*ra)); 255 /* Set the ra mask from sta's capability */ 256 if (sta->deflink.he_cap.has_he) { 257 mode |= RTW89_RA_MODE_HE; 258 csi_mode = RTW89_RA_RPT_MODE_HE; 259 ra_mask |= get_he_ra_mask(sta); 260 high_rate_masks = rtw89_ra_mask_he_rates; 261 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[2] & 262 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) 263 stbc_en = 1; 264 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[1] & 265 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) 266 ldpc_en = 1; 267 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta, &fix_giltf_en, &fix_giltf); 268 } else if (sta->deflink.vht_cap.vht_supported) { 269 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 270 271 mode |= RTW89_RA_MODE_VHT; 272 csi_mode = RTW89_RA_RPT_MODE_VHT; 273 /* MCS9, MCS8, MCS7 */ 274 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); 275 high_rate_masks = rtw89_ra_mask_vht_rates; 276 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 277 stbc_en = 1; 278 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 279 ldpc_en = 1; 280 } else if (sta->deflink.ht_cap.ht_supported) { 281 mode |= RTW89_RA_MODE_HT; 282 csi_mode = RTW89_RA_RPT_MODE_HT; 283 ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 48) | 284 ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 36) | 285 (sta->deflink.ht_cap.mcs.rx_mask[1] << 24) | 286 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 287 high_rate_masks = rtw89_ra_mask_ht_rates; 288 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 289 stbc_en = 1; 290 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 291 ldpc_en = 1; 292 } 293 294 switch (chan->band_type) { 295 case RTW89_BAND_2G: 296 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 297 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xf) 298 mode |= RTW89_RA_MODE_CCK; 299 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xff0) 300 mode |= RTW89_RA_MODE_OFDM; 301 break; 302 case RTW89_BAND_5G: 303 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 304 mode |= RTW89_RA_MODE_OFDM; 305 break; 306 case RTW89_BAND_6G: 307 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_6GHZ] << 4; 308 mode |= RTW89_RA_MODE_OFDM; 309 break; 310 default: 311 rtw89_err(rtwdev, "Unknown band type\n"); 312 break; 313 } 314 315 ra_mask_bak = ra_mask; 316 317 if (mode >= RTW89_RA_MODE_HT) { 318 u64 mask = 0; 319 for (i = 0; i < rtwdev->hal.tx_nss; i++) 320 mask |= high_rate_masks[i]; 321 if (mode & RTW89_RA_MODE_OFDM) 322 mask |= RA_MASK_SUBOFDM_RATES; 323 if (mode & RTW89_RA_MODE_CCK) 324 mask |= RA_MASK_SUBCCK_RATES; 325 ra_mask &= mask; 326 } else if (mode & RTW89_RA_MODE_OFDM) { 327 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES); 328 } 329 330 if (mode != RTW89_RA_MODE_CCK) 331 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); 332 333 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak); 334 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 335 336 switch (sta->deflink.bandwidth) { 337 case IEEE80211_STA_RX_BW_160: 338 bw_mode = RTW89_CHANNEL_WIDTH_160; 339 sgi = sta->deflink.vht_cap.vht_supported && 340 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160); 341 break; 342 case IEEE80211_STA_RX_BW_80: 343 bw_mode = RTW89_CHANNEL_WIDTH_80; 344 sgi = sta->deflink.vht_cap.vht_supported && 345 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 346 break; 347 case IEEE80211_STA_RX_BW_40: 348 bw_mode = RTW89_CHANNEL_WIDTH_40; 349 sgi = sta->deflink.ht_cap.ht_supported && 350 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 351 break; 352 default: 353 bw_mode = RTW89_CHANNEL_WIDTH_20; 354 sgi = sta->deflink.ht_cap.ht_supported && 355 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 356 break; 357 } 358 359 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 360 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) 361 ra->dcm_cap = 1; 362 363 if (rate_pattern->enable && !vif->p2p) { 364 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 365 ra_mask &= rate_pattern->ra_mask; 366 mode = rate_pattern->ra_mode; 367 } 368 369 ra->bw_cap = bw_mode; 370 ra->mode_ctrl = mode; 371 ra->macid = rtwsta->mac_id; 372 ra->stbc_cap = stbc_en; 373 ra->ldpc_cap = ldpc_en; 374 ra->ss_num = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1; 375 ra->en_sgi = sgi; 376 ra->ra_mask = ra_mask; 377 ra->fix_giltf_en = fix_giltf_en; 378 ra->fix_giltf = fix_giltf; 379 380 if (!csi) 381 return; 382 383 ra->fixed_csi_rate_en = false; 384 ra->ra_csi_rate_en = true; 385 ra->cr_tbl_sel = false; 386 ra->band_num = rtwvif->phy_idx; 387 ra->csi_bw = bw_mode; 388 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; 389 ra->csi_mcs_ss_idx = 5; 390 ra->csi_mode = csi_mode; 391 } 392 393 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 394 u32 changed) 395 { 396 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 397 struct rtw89_ra_info *ra = &rtwsta->ra; 398 399 rtw89_phy_ra_sta_update(rtwdev, sta, false); 400 401 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) 402 ra->upd_mask = 1; 403 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED)) 404 ra->upd_bw_nss_mask = 1; 405 406 rtw89_debug(rtwdev, RTW89_DBG_RA, 407 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", 408 ra->macid, 409 ra->bw_cap, 410 ra->ss_num, 411 ra->en_sgi, 412 ra->giltf); 413 414 rtw89_fw_h2c_ra(rtwdev, ra, false); 415 } 416 417 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, 418 u16 rate_base, u64 ra_mask, u8 ra_mode, 419 u32 rate_ctrl, u32 ctrl_skip, bool force) 420 { 421 u8 n, c; 422 423 if (rate_ctrl == ctrl_skip) 424 return true; 425 426 n = hweight32(rate_ctrl); 427 if (n == 0) 428 return true; 429 430 if (force && n != 1) 431 return false; 432 433 if (next->enable) 434 return false; 435 436 c = __fls(rate_ctrl); 437 next->rate = rate_base + c; 438 next->ra_mode = ra_mode; 439 next->ra_mask = ra_mask; 440 next->enable = true; 441 442 return true; 443 } 444 445 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 446 struct ieee80211_vif *vif, 447 const struct cfg80211_bitrate_mask *mask) 448 { 449 struct ieee80211_supported_band *sband; 450 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 451 struct rtw89_phy_rate_pattern next_pattern = {0}; 452 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 453 static const u16 hw_rate_he[] = {RTW89_HW_RATE_HE_NSS1_MCS0, 454 RTW89_HW_RATE_HE_NSS2_MCS0, 455 RTW89_HW_RATE_HE_NSS3_MCS0, 456 RTW89_HW_RATE_HE_NSS4_MCS0}; 457 static const u16 hw_rate_vht[] = {RTW89_HW_RATE_VHT_NSS1_MCS0, 458 RTW89_HW_RATE_VHT_NSS2_MCS0, 459 RTW89_HW_RATE_VHT_NSS3_MCS0, 460 RTW89_HW_RATE_VHT_NSS4_MCS0}; 461 static const u16 hw_rate_ht[] = {RTW89_HW_RATE_MCS0, 462 RTW89_HW_RATE_MCS8, 463 RTW89_HW_RATE_MCS16, 464 RTW89_HW_RATE_MCS24}; 465 u8 band = chan->band_type; 466 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 467 u8 tx_nss = rtwdev->hal.tx_nss; 468 u8 i; 469 470 for (i = 0; i < tx_nss; i++) 471 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i], 472 RA_MASK_HE_RATES, RTW89_RA_MODE_HE, 473 mask->control[nl_band].he_mcs[i], 474 0, true)) 475 goto out; 476 477 for (i = 0; i < tx_nss; i++) 478 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i], 479 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, 480 mask->control[nl_band].vht_mcs[i], 481 0, true)) 482 goto out; 483 484 for (i = 0; i < tx_nss; i++) 485 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i], 486 RA_MASK_HT_RATES, RTW89_RA_MODE_HT, 487 mask->control[nl_band].ht_mcs[i], 488 0, true)) 489 goto out; 490 491 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and 492 * require at least one basic rate for ieee80211_set_bitrate_mask, 493 * so the decision just depends on if all bitrates are set or not. 494 */ 495 sband = rtwdev->hw->wiphy->bands[nl_band]; 496 if (band == RTW89_BAND_2G) { 497 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, 498 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, 499 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, 500 mask->control[nl_band].legacy, 501 BIT(sband->n_bitrates) - 1, false)) 502 goto out; 503 } else { 504 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, 505 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, 506 mask->control[nl_band].legacy, 507 BIT(sband->n_bitrates) - 1, false)) 508 goto out; 509 } 510 511 if (!next_pattern.enable) 512 goto out; 513 514 rtwvif->rate_pattern = next_pattern; 515 rtw89_debug(rtwdev, RTW89_DBG_RA, 516 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", 517 next_pattern.rate, 518 next_pattern.ra_mask, 519 next_pattern.ra_mode); 520 return; 521 522 out: 523 rtwvif->rate_pattern.enable = false; 524 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); 525 } 526 527 static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta) 528 { 529 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; 530 531 rtw89_phy_ra_updata_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED); 532 } 533 534 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) 535 { 536 ieee80211_iterate_stations_atomic(rtwdev->hw, 537 rtw89_phy_ra_updata_sta_iter, 538 rtwdev); 539 } 540 541 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) 542 { 543 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 544 struct rtw89_ra_info *ra = &rtwsta->ra; 545 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; 546 bool csi = rtw89_sta_has_beamformer_cap(sta); 547 548 rtw89_phy_ra_sta_update(rtwdev, sta, csi); 549 550 if (rssi > 40) 551 ra->init_rate_lv = 1; 552 else if (rssi > 20) 553 ra->init_rate_lv = 2; 554 else if (rssi > 1) 555 ra->init_rate_lv = 3; 556 else 557 ra->init_rate_lv = 0; 558 ra->upd_all = 1; 559 rtw89_debug(rtwdev, RTW89_DBG_RA, 560 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", 561 ra->macid, 562 ra->mode_ctrl, 563 ra->bw_cap, 564 ra->ss_num, 565 ra->init_rate_lv); 566 rtw89_debug(rtwdev, RTW89_DBG_RA, 567 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", 568 ra->dcm_cap, 569 ra->er_cap, 570 ra->ldpc_cap, 571 ra->stbc_cap, 572 ra->en_sgi, 573 ra->giltf); 574 575 rtw89_fw_h2c_ra(rtwdev, ra, csi); 576 } 577 578 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 579 const struct rtw89_chan *chan, 580 enum rtw89_bandwidth dbw) 581 { 582 enum rtw89_bandwidth cbw = chan->band_width; 583 u8 pri_ch = chan->primary_channel; 584 u8 central_ch = chan->channel; 585 u8 txsc_idx = 0; 586 u8 tmp = 0; 587 588 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 589 return txsc_idx; 590 591 switch (cbw) { 592 case RTW89_CHANNEL_WIDTH_40: 593 txsc_idx = pri_ch > central_ch ? 1 : 2; 594 break; 595 case RTW89_CHANNEL_WIDTH_80: 596 if (dbw == RTW89_CHANNEL_WIDTH_20) { 597 if (pri_ch > central_ch) 598 txsc_idx = (pri_ch - central_ch) >> 1; 599 else 600 txsc_idx = ((central_ch - pri_ch) >> 1) + 1; 601 } else { 602 txsc_idx = pri_ch > central_ch ? 9 : 10; 603 } 604 break; 605 case RTW89_CHANNEL_WIDTH_160: 606 if (pri_ch > central_ch) 607 tmp = (pri_ch - central_ch) >> 1; 608 else 609 tmp = ((central_ch - pri_ch) >> 1) + 1; 610 611 if (dbw == RTW89_CHANNEL_WIDTH_20) { 612 txsc_idx = tmp; 613 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 614 if (tmp == 1 || tmp == 3) 615 txsc_idx = 9; 616 else if (tmp == 5 || tmp == 7) 617 txsc_idx = 11; 618 else if (tmp == 2 || tmp == 4) 619 txsc_idx = 10; 620 else if (tmp == 6 || tmp == 8) 621 txsc_idx = 12; 622 else 623 return 0xff; 624 } else { 625 txsc_idx = pri_ch > central_ch ? 13 : 14; 626 } 627 break; 628 case RTW89_CHANNEL_WIDTH_80_80: 629 if (dbw == RTW89_CHANNEL_WIDTH_20) { 630 if (pri_ch > central_ch) 631 txsc_idx = (10 - (pri_ch - central_ch)) >> 1; 632 else 633 txsc_idx = ((central_ch - pri_ch) >> 1) + 5; 634 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 635 txsc_idx = pri_ch > central_ch ? 10 : 12; 636 } else { 637 txsc_idx = 14; 638 } 639 break; 640 default: 641 break; 642 } 643 644 return txsc_idx; 645 } 646 EXPORT_SYMBOL(rtw89_phy_get_txsc); 647 648 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev) 649 { 650 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) || 651 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1); 652 } 653 654 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 655 u32 addr, u32 mask) 656 { 657 const struct rtw89_chip_info *chip = rtwdev->chip; 658 const u32 *base_addr = chip->rf_base_addr; 659 u32 val, direct_addr; 660 661 if (rf_path >= rtwdev->chip->rf_path_num) { 662 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 663 return INV_RF_DATA; 664 } 665 666 addr &= 0xff; 667 direct_addr = base_addr[rf_path] + (addr << 2); 668 mask &= RFREG_MASK; 669 670 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); 671 672 return val; 673 } 674 EXPORT_SYMBOL(rtw89_phy_read_rf); 675 676 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev, 677 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 678 { 679 bool busy; 680 bool done; 681 u32 val; 682 int ret; 683 684 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 685 1, 30, false, rtwdev); 686 if (ret) { 687 rtw89_err(rtwdev, "read rf busy swsi\n"); 688 return INV_RF_DATA; 689 } 690 691 mask &= RFREG_MASK; 692 693 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) | 694 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr); 695 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val); 696 udelay(2); 697 698 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1, 699 30, false, rtwdev, R_SWSI_V1, 700 B_SWSI_R_DATA_DONE_V1); 701 if (ret) { 702 rtw89_err(rtwdev, "read swsi busy\n"); 703 return INV_RF_DATA; 704 } 705 706 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask); 707 } 708 709 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 710 u32 addr, u32 mask) 711 { 712 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 713 714 if (rf_path >= rtwdev->chip->rf_path_num) { 715 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 716 return INV_RF_DATA; 717 } 718 719 if (ad_sel) 720 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 721 else 722 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask); 723 } 724 EXPORT_SYMBOL(rtw89_phy_read_rf_v1); 725 726 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 727 u32 addr, u32 mask, u32 data) 728 { 729 const struct rtw89_chip_info *chip = rtwdev->chip; 730 const u32 *base_addr = chip->rf_base_addr; 731 u32 direct_addr; 732 733 if (rf_path >= rtwdev->chip->rf_path_num) { 734 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 735 return false; 736 } 737 738 addr &= 0xff; 739 direct_addr = base_addr[rf_path] + (addr << 2); 740 mask &= RFREG_MASK; 741 742 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); 743 744 /* delay to ensure writing properly */ 745 udelay(1); 746 747 return true; 748 } 749 EXPORT_SYMBOL(rtw89_phy_write_rf); 750 751 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev, 752 enum rtw89_rf_path rf_path, u32 addr, u32 mask, 753 u32 data) 754 { 755 u8 bit_shift; 756 u32 val; 757 bool busy, b_msk_en = false; 758 int ret; 759 760 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 761 1, 30, false, rtwdev); 762 if (ret) { 763 rtw89_err(rtwdev, "write rf busy swsi\n"); 764 return false; 765 } 766 767 data &= RFREG_MASK; 768 mask &= RFREG_MASK; 769 770 if (mask != RFREG_MASK) { 771 b_msk_en = true; 772 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK, 773 mask); 774 bit_shift = __ffs(mask); 775 data = (data << bit_shift) & RFREG_MASK; 776 } 777 778 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) | 779 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) | 780 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) | 781 FIELD_PREP(B_SWSI_DATA_VAL_V1, data); 782 783 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val); 784 785 return true; 786 } 787 788 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 789 u32 addr, u32 mask, u32 data) 790 { 791 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 792 793 if (rf_path >= rtwdev->chip->rf_path_num) { 794 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 795 return false; 796 } 797 798 if (ad_sel) 799 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 800 else 801 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data); 802 } 803 EXPORT_SYMBOL(rtw89_phy_write_rf_v1); 804 805 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev) 806 { 807 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1; 808 } 809 810 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, 811 enum rtw89_phy_idx phy_idx) 812 { 813 const struct rtw89_chip_info *chip = rtwdev->chip; 814 815 chip->ops->bb_reset(rtwdev, phy_idx); 816 } 817 818 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, 819 const struct rtw89_reg2_def *reg, 820 enum rtw89_rf_path rf_path, 821 void *extra_data) 822 { 823 if (reg->addr == 0xfe) 824 mdelay(50); 825 else if (reg->addr == 0xfd) 826 mdelay(5); 827 else if (reg->addr == 0xfc) 828 mdelay(1); 829 else if (reg->addr == 0xfb) 830 udelay(50); 831 else if (reg->addr == 0xfa) 832 udelay(5); 833 else if (reg->addr == 0xf9) 834 udelay(1); 835 else 836 rtw89_phy_write32(rtwdev, reg->addr, reg->data); 837 } 838 839 union rtw89_phy_bb_gain_arg { 840 u32 addr; 841 struct { 842 union { 843 u8 type; 844 struct { 845 u8 rxsc_start:4; 846 u8 bw:4; 847 }; 848 }; 849 u8 path; 850 u8 gain_band; 851 u8 cfg_type; 852 }; 853 } __packed; 854 855 static void 856 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev, 857 union rtw89_phy_bb_gain_arg arg, u32 data) 858 { 859 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 860 u8 type = arg.type; 861 u8 path = arg.path; 862 u8 gband = arg.gain_band; 863 int i; 864 865 switch (type) { 866 case 0: 867 for (i = 0; i < 4; i++, data >>= 8) 868 gain->lna_gain[gband][path][i] = data & 0xff; 869 break; 870 case 1: 871 for (i = 4; i < 7; i++, data >>= 8) 872 gain->lna_gain[gband][path][i] = data & 0xff; 873 break; 874 case 2: 875 for (i = 0; i < 2; i++, data >>= 8) 876 gain->tia_gain[gband][path][i] = data & 0xff; 877 break; 878 default: 879 rtw89_warn(rtwdev, 880 "bb gain error {0x%x:0x%x} with unknown type: %d\n", 881 arg.addr, data, type); 882 break; 883 } 884 } 885 886 enum rtw89_phy_bb_rxsc_start_idx { 887 RTW89_BB_RXSC_START_IDX_FULL = 0, 888 RTW89_BB_RXSC_START_IDX_20 = 1, 889 RTW89_BB_RXSC_START_IDX_20_1 = 5, 890 RTW89_BB_RXSC_START_IDX_40 = 9, 891 RTW89_BB_RXSC_START_IDX_80 = 13, 892 }; 893 894 static void 895 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev, 896 union rtw89_phy_bb_gain_arg arg, u32 data) 897 { 898 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 899 u8 rxsc_start = arg.rxsc_start; 900 u8 bw = arg.bw; 901 u8 path = arg.path; 902 u8 gband = arg.gain_band; 903 u8 rxsc; 904 s8 ofst; 905 int i; 906 907 switch (bw) { 908 case RTW89_CHANNEL_WIDTH_20: 909 gain->rpl_ofst_20[gband][path] = (s8)data; 910 break; 911 case RTW89_CHANNEL_WIDTH_40: 912 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 913 gain->rpl_ofst_40[gband][path][0] = (s8)data; 914 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 915 for (i = 0; i < 2; i++, data >>= 8) { 916 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 917 ofst = (s8)(data & 0xff); 918 gain->rpl_ofst_40[gband][path][rxsc] = ofst; 919 } 920 } 921 break; 922 case RTW89_CHANNEL_WIDTH_80: 923 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 924 gain->rpl_ofst_80[gband][path][0] = (s8)data; 925 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 926 for (i = 0; i < 4; i++, data >>= 8) { 927 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 928 ofst = (s8)(data & 0xff); 929 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 930 } 931 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 932 for (i = 0; i < 2; i++, data >>= 8) { 933 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 934 ofst = (s8)(data & 0xff); 935 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 936 } 937 } 938 break; 939 case RTW89_CHANNEL_WIDTH_160: 940 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 941 gain->rpl_ofst_160[gband][path][0] = (s8)data; 942 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 943 for (i = 0; i < 4; i++, data >>= 8) { 944 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 945 ofst = (s8)(data & 0xff); 946 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 947 } 948 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) { 949 for (i = 0; i < 4; i++, data >>= 8) { 950 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i; 951 ofst = (s8)(data & 0xff); 952 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 953 } 954 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 955 for (i = 0; i < 4; i++, data >>= 8) { 956 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 957 ofst = (s8)(data & 0xff); 958 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 959 } 960 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) { 961 for (i = 0; i < 2; i++, data >>= 8) { 962 rxsc = RTW89_BB_RXSC_START_IDX_80 + i; 963 ofst = (s8)(data & 0xff); 964 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 965 } 966 } 967 break; 968 default: 969 rtw89_warn(rtwdev, 970 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n", 971 arg.addr, data, bw); 972 break; 973 } 974 } 975 976 static void 977 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev, 978 union rtw89_phy_bb_gain_arg arg, u32 data) 979 { 980 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 981 u8 type = arg.type; 982 u8 path = arg.path; 983 u8 gband = arg.gain_band; 984 int i; 985 986 switch (type) { 987 case 0: 988 for (i = 0; i < 4; i++, data >>= 8) 989 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 990 break; 991 case 1: 992 for (i = 4; i < 7; i++, data >>= 8) 993 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 994 break; 995 default: 996 rtw89_warn(rtwdev, 997 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n", 998 arg.addr, data, type); 999 break; 1000 } 1001 } 1002 1003 static void 1004 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev, 1005 union rtw89_phy_bb_gain_arg arg, u32 data) 1006 { 1007 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 1008 u8 type = arg.type; 1009 u8 path = arg.path; 1010 u8 gband = arg.gain_band; 1011 int i; 1012 1013 switch (type) { 1014 case 0: 1015 for (i = 0; i < 4; i++, data >>= 8) 1016 gain->lna_op1db[gband][path][i] = data & 0xff; 1017 break; 1018 case 1: 1019 for (i = 4; i < 7; i++, data >>= 8) 1020 gain->lna_op1db[gband][path][i] = data & 0xff; 1021 break; 1022 case 2: 1023 for (i = 0; i < 4; i++, data >>= 8) 1024 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1025 break; 1026 case 3: 1027 for (i = 4; i < 8; i++, data >>= 8) 1028 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1029 break; 1030 default: 1031 rtw89_warn(rtwdev, 1032 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n", 1033 arg.addr, data, type); 1034 break; 1035 } 1036 } 1037 1038 static void rtw89_phy_config_bb_gain(struct rtw89_dev *rtwdev, 1039 const struct rtw89_reg2_def *reg, 1040 enum rtw89_rf_path rf_path, 1041 void *extra_data) 1042 { 1043 const struct rtw89_chip_info *chip = rtwdev->chip; 1044 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr }; 1045 struct rtw89_efuse *efuse = &rtwdev->efuse; 1046 1047 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR) 1048 return; 1049 1050 if (arg.path >= chip->rf_path_num) 1051 return; 1052 1053 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) { 1054 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n"); 1055 return; 1056 } 1057 1058 switch (arg.cfg_type) { 1059 case 0: 1060 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data); 1061 break; 1062 case 1: 1063 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data); 1064 break; 1065 case 2: 1066 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data); 1067 break; 1068 case 3: 1069 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data); 1070 break; 1071 case 4: 1072 /* This cfg_type is only used by rfe_type >= 50 with eFEM */ 1073 if (efuse->rfe_type < 50) 1074 break; 1075 fallthrough; 1076 default: 1077 rtw89_warn(rtwdev, 1078 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n", 1079 arg.addr, reg->data, arg.cfg_type); 1080 break; 1081 } 1082 } 1083 1084 static void 1085 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, 1086 const struct rtw89_reg2_def *reg, 1087 enum rtw89_rf_path rf_path, 1088 struct rtw89_fw_h2c_rf_reg_info *info) 1089 { 1090 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; 1091 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 1092 1093 if (page >= RTW89_H2C_RF_PAGE_NUM) { 1094 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d", 1095 rf_path, info->curr_idx); 1096 return; 1097 } 1098 1099 info->rtw89_phy_config_rf_h2c[page][idx] = 1100 cpu_to_le32((reg->addr << 20) | reg->data); 1101 info->curr_idx++; 1102 } 1103 1104 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, 1105 struct rtw89_fw_h2c_rf_reg_info *info) 1106 { 1107 u16 remain = info->curr_idx; 1108 u16 len = 0; 1109 u8 i; 1110 int ret = 0; 1111 1112 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) { 1113 rtw89_warn(rtwdev, 1114 "rf reg h2c total len %d larger than %d\n", 1115 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE); 1116 ret = -EINVAL; 1117 goto out; 1118 } 1119 1120 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) { 1121 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain; 1122 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i); 1123 if (ret) 1124 goto out; 1125 } 1126 out: 1127 info->curr_idx = 0; 1128 1129 return ret; 1130 } 1131 1132 static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev, 1133 const struct rtw89_reg2_def *reg, 1134 enum rtw89_rf_path rf_path, 1135 void *extra_data) 1136 { 1137 u32 addr = reg->addr; 1138 1139 if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb || 1140 addr == 0xfa || addr == 0xf9) 1141 return; 1142 1143 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100) 1144 return; 1145 1146 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1147 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1148 } 1149 1150 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, 1151 const struct rtw89_reg2_def *reg, 1152 enum rtw89_rf_path rf_path, 1153 void *extra_data) 1154 { 1155 if (reg->addr == 0xfe) { 1156 mdelay(50); 1157 } else if (reg->addr == 0xfd) { 1158 mdelay(5); 1159 } else if (reg->addr == 0xfc) { 1160 mdelay(1); 1161 } else if (reg->addr == 0xfb) { 1162 udelay(50); 1163 } else if (reg->addr == 0xfa) { 1164 udelay(5); 1165 } else if (reg->addr == 0xf9) { 1166 udelay(1); 1167 } else { 1168 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); 1169 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1170 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1171 } 1172 } 1173 1174 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 1175 const struct rtw89_reg2_def *reg, 1176 enum rtw89_rf_path rf_path, 1177 void *extra_data) 1178 { 1179 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data); 1180 1181 if (reg->addr < 0x100) 1182 return; 1183 1184 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1185 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1186 } 1187 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1); 1188 1189 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, 1190 const struct rtw89_phy_table *table, 1191 u32 *headline_size, u32 *headline_idx, 1192 u8 rfe, u8 cv) 1193 { 1194 const struct rtw89_reg2_def *reg; 1195 u32 headline; 1196 u32 compare, target; 1197 u8 rfe_para, cv_para; 1198 u8 cv_max = 0; 1199 bool case_matched = false; 1200 u32 i; 1201 1202 for (i = 0; i < table->n_regs; i++) { 1203 reg = &table->regs[i]; 1204 headline = get_phy_headline(reg->addr); 1205 if (headline != PHY_HEADLINE_VALID) 1206 break; 1207 } 1208 *headline_size = i; 1209 if (*headline_size == 0) 1210 return 0; 1211 1212 /* case 1: RFE match, CV match */ 1213 compare = get_phy_compare(rfe, cv); 1214 for (i = 0; i < *headline_size; i++) { 1215 reg = &table->regs[i]; 1216 target = get_phy_target(reg->addr); 1217 if (target == compare) { 1218 *headline_idx = i; 1219 return 0; 1220 } 1221 } 1222 1223 /* case 2: RFE match, CV don't care */ 1224 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); 1225 for (i = 0; i < *headline_size; i++) { 1226 reg = &table->regs[i]; 1227 target = get_phy_target(reg->addr); 1228 if (target == compare) { 1229 *headline_idx = i; 1230 return 0; 1231 } 1232 } 1233 1234 /* case 3: RFE match, CV max in table */ 1235 for (i = 0; i < *headline_size; i++) { 1236 reg = &table->regs[i]; 1237 rfe_para = get_phy_cond_rfe(reg->addr); 1238 cv_para = get_phy_cond_cv(reg->addr); 1239 if (rfe_para == rfe) { 1240 if (cv_para >= cv_max) { 1241 cv_max = cv_para; 1242 *headline_idx = i; 1243 case_matched = true; 1244 } 1245 } 1246 } 1247 1248 if (case_matched) 1249 return 0; 1250 1251 /* case 4: RFE don't care, CV max in table */ 1252 for (i = 0; i < *headline_size; i++) { 1253 reg = &table->regs[i]; 1254 rfe_para = get_phy_cond_rfe(reg->addr); 1255 cv_para = get_phy_cond_cv(reg->addr); 1256 if (rfe_para == PHY_COND_DONT_CARE) { 1257 if (cv_para >= cv_max) { 1258 cv_max = cv_para; 1259 *headline_idx = i; 1260 case_matched = true; 1261 } 1262 } 1263 } 1264 1265 if (case_matched) 1266 return 0; 1267 1268 return -EINVAL; 1269 } 1270 1271 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, 1272 const struct rtw89_phy_table *table, 1273 void (*config)(struct rtw89_dev *rtwdev, 1274 const struct rtw89_reg2_def *reg, 1275 enum rtw89_rf_path rf_path, 1276 void *data), 1277 void *extra_data) 1278 { 1279 const struct rtw89_reg2_def *reg; 1280 enum rtw89_rf_path rf_path = table->rf_path; 1281 u8 rfe = rtwdev->efuse.rfe_type; 1282 u8 cv = rtwdev->hal.cv; 1283 u32 i; 1284 u32 headline_size = 0, headline_idx = 0; 1285 u32 target = 0, cfg_target; 1286 u8 cond; 1287 bool is_matched = true; 1288 bool target_found = false; 1289 int ret; 1290 1291 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, 1292 &headline_idx, rfe, cv); 1293 if (ret) { 1294 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); 1295 return; 1296 } 1297 1298 cfg_target = get_phy_target(table->regs[headline_idx].addr); 1299 for (i = headline_size; i < table->n_regs; i++) { 1300 reg = &table->regs[i]; 1301 cond = get_phy_cond(reg->addr); 1302 switch (cond) { 1303 case PHY_COND_BRANCH_IF: 1304 case PHY_COND_BRANCH_ELIF: 1305 target = get_phy_target(reg->addr); 1306 break; 1307 case PHY_COND_BRANCH_ELSE: 1308 is_matched = false; 1309 if (!target_found) { 1310 rtw89_warn(rtwdev, "failed to load CR %x/%x\n", 1311 reg->addr, reg->data); 1312 return; 1313 } 1314 break; 1315 case PHY_COND_BRANCH_END: 1316 is_matched = true; 1317 target_found = false; 1318 break; 1319 case PHY_COND_CHECK: 1320 if (target_found) { 1321 is_matched = false; 1322 break; 1323 } 1324 1325 if (target == cfg_target) { 1326 is_matched = true; 1327 target_found = true; 1328 } else { 1329 is_matched = false; 1330 target_found = false; 1331 } 1332 break; 1333 default: 1334 if (is_matched) 1335 config(rtwdev, reg, rf_path, extra_data); 1336 break; 1337 } 1338 } 1339 } 1340 1341 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) 1342 { 1343 const struct rtw89_chip_info *chip = rtwdev->chip; 1344 const struct rtw89_phy_table *bb_table = chip->bb_table; 1345 const struct rtw89_phy_table *bb_gain_table = chip->bb_gain_table; 1346 1347 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); 1348 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 1349 if (bb_gain_table) 1350 rtw89_phy_init_reg(rtwdev, bb_gain_table, 1351 rtw89_phy_config_bb_gain, NULL); 1352 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); 1353 } 1354 1355 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 1356 { 1357 rtw89_phy_write32(rtwdev, 0x8080, 0x4); 1358 udelay(1); 1359 return rtw89_phy_read32(rtwdev, 0x8080); 1360 } 1361 1362 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio) 1363 { 1364 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 1365 enum rtw89_rf_path rf_path, void *data); 1366 const struct rtw89_chip_info *chip = rtwdev->chip; 1367 const struct rtw89_phy_table *rf_table; 1368 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; 1369 u8 path; 1370 1371 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); 1372 if (!rf_reg_info) 1373 return; 1374 1375 for (path = RF_PATH_A; path < chip->rf_path_num; path++) { 1376 rf_table = chip->rf_table[path]; 1377 rf_reg_info->rf_path = rf_table->rf_path; 1378 if (noio) 1379 config = rtw89_phy_config_rf_reg_noio; 1380 else 1381 config = rf_table->config ? rf_table->config : 1382 rtw89_phy_config_rf_reg; 1383 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info); 1384 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) 1385 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", 1386 rf_reg_info->rf_path); 1387 } 1388 kfree(rf_reg_info); 1389 } 1390 1391 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) 1392 { 1393 const struct rtw89_chip_info *chip = rtwdev->chip; 1394 const struct rtw89_phy_table *nctl_table; 1395 u32 val; 1396 int ret; 1397 1398 /* IQK/DPK clock & reset */ 1399 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3); 1400 rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1); 1401 rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000); 1402 rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000); 1403 if (chip->chip_id == RTL8852B) 1404 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2); 1405 1406 /* check 0x8080 */ 1407 rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8); 1408 1409 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, 1410 1000, false, rtwdev); 1411 if (ret) 1412 rtw89_err(rtwdev, "failed to poll nctl block\n"); 1413 1414 nctl_table = chip->nctl_table; 1415 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); 1416 } 1417 1418 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) 1419 { 1420 u32 phy_page = addr >> 8; 1421 u32 ofst = 0; 1422 1423 switch (phy_page) { 1424 case 0x6: 1425 case 0x7: 1426 case 0x8: 1427 case 0x9: 1428 case 0xa: 1429 case 0xb: 1430 case 0xc: 1431 case 0xd: 1432 case 0x19: 1433 case 0x1a: 1434 case 0x1b: 1435 ofst = 0x2000; 1436 break; 1437 default: 1438 /* warning case */ 1439 ofst = 0; 1440 break; 1441 } 1442 1443 if (phy_page >= 0x40 && phy_page <= 0x4f) 1444 ofst = 0x2000; 1445 1446 return ofst; 1447 } 1448 1449 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1450 u32 data, enum rtw89_phy_idx phy_idx) 1451 { 1452 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1453 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1454 rtw89_phy_write32_mask(rtwdev, addr, mask, data); 1455 } 1456 EXPORT_SYMBOL(rtw89_phy_write32_idx); 1457 1458 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1459 enum rtw89_phy_idx phy_idx) 1460 { 1461 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1462 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1463 return rtw89_phy_read32_mask(rtwdev, addr, mask); 1464 } 1465 EXPORT_SYMBOL(rtw89_phy_read32_idx); 1466 1467 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1468 u32 val) 1469 { 1470 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 1471 1472 if (!rtwdev->dbcc_en) 1473 return; 1474 1475 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 1476 } 1477 1478 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 1479 const struct rtw89_phy_reg3_tbl *tbl) 1480 { 1481 const struct rtw89_reg3_def *reg3; 1482 int i; 1483 1484 for (i = 0; i < tbl->size; i++) { 1485 reg3 = &tbl->reg3[i]; 1486 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); 1487 } 1488 } 1489 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl); 1490 1491 static const u8 rtw89_rs_idx_max[] = { 1492 [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX, 1493 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX, 1494 [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX, 1495 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX, 1496 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX, 1497 }; 1498 1499 static const u8 rtw89_rs_nss_max[] = { 1500 [RTW89_RS_CCK] = 1, 1501 [RTW89_RS_OFDM] = 1, 1502 [RTW89_RS_MCS] = RTW89_NSS_MAX, 1503 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX, 1504 [RTW89_RS_OFFSET] = 1, 1505 }; 1506 1507 static const u8 _byr_of_rs[] = { 1508 [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck), 1509 [RTW89_RS_OFDM] = offsetof(struct rtw89_txpwr_byrate, ofdm), 1510 [RTW89_RS_MCS] = offsetof(struct rtw89_txpwr_byrate, mcs), 1511 [RTW89_RS_HEDCM] = offsetof(struct rtw89_txpwr_byrate, hedcm), 1512 [RTW89_RS_OFFSET] = offsetof(struct rtw89_txpwr_byrate, offset), 1513 }; 1514 1515 #define _byr_seek(rs, raw) ((s8 *)(raw) + _byr_of_rs[rs]) 1516 #define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_max[rs] + (idx)) 1517 #define _byr_chk(rs, nss, idx) \ 1518 ((nss) < rtw89_rs_nss_max[rs] && (idx) < rtw89_rs_idx_max[rs]) 1519 1520 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 1521 const struct rtw89_txpwr_table *tbl) 1522 { 1523 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; 1524 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; 1525 s8 *byr; 1526 u32 data; 1527 u8 i, idx; 1528 1529 for (; cfg < end; cfg++) { 1530 byr = _byr_seek(cfg->rs, &rtwdev->byr[cfg->band]); 1531 data = cfg->data; 1532 1533 for (i = 0; i < cfg->len; i++, data >>= 8) { 1534 idx = _byr_idx(cfg->rs, cfg->nss, (cfg->shf + i)); 1535 byr[idx] = (s8)(data & 0xff); 1536 } 1537 } 1538 } 1539 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate); 1540 1541 #define _phy_txpwr_rf_to_mac(rtwdev, txpwr_rf) \ 1542 ({ \ 1543 const struct rtw89_chip_info *__c = (rtwdev)->chip; \ 1544 (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \ 1545 }) 1546 1547 static 1548 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, 1549 const struct rtw89_rate_desc *rate_desc) 1550 { 1551 s8 *byr; 1552 u8 idx; 1553 1554 if (rate_desc->rs == RTW89_RS_CCK) 1555 band = RTW89_BAND_2G; 1556 1557 if (!_byr_chk(rate_desc->rs, rate_desc->nss, rate_desc->idx)) { 1558 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1559 "[TXPWR] unknown byrate desc rs=%d nss=%d idx=%d\n", 1560 rate_desc->rs, rate_desc->nss, rate_desc->idx); 1561 1562 return 0; 1563 } 1564 1565 byr = _byr_seek(rate_desc->rs, &rtwdev->byr[band]); 1566 idx = _byr_idx(rate_desc->rs, rate_desc->nss, rate_desc->idx); 1567 1568 return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]); 1569 } 1570 1571 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g) 1572 { 1573 switch (channel_6g) { 1574 case 1 ... 29: 1575 return (channel_6g - 1) / 2; 1576 case 33 ... 61: 1577 return (channel_6g - 3) / 2; 1578 case 65 ... 93: 1579 return (channel_6g - 5) / 2; 1580 case 97 ... 125: 1581 return (channel_6g - 7) / 2; 1582 case 129 ... 157: 1583 return (channel_6g - 9) / 2; 1584 case 161 ... 189: 1585 return (channel_6g - 11) / 2; 1586 case 193 ... 221: 1587 return (channel_6g - 13) / 2; 1588 case 225 ... 253: 1589 return (channel_6g - 15) / 2; 1590 default: 1591 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g); 1592 return 0; 1593 } 1594 } 1595 1596 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel) 1597 { 1598 if (band == RTW89_BAND_6G) 1599 return rtw89_channel_6g_to_idx(rtwdev, channel); 1600 1601 switch (channel) { 1602 case 1 ... 14: 1603 return channel - 1; 1604 case 36 ... 64: 1605 return (channel - 36) / 2; 1606 case 100 ... 144: 1607 return ((channel - 100) / 2) + 15; 1608 case 149 ... 177: 1609 return ((channel - 149) / 2) + 38; 1610 default: 1611 rtw89_warn(rtwdev, "unknown channel: %d\n", channel); 1612 return 0; 1613 } 1614 } 1615 1616 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 1617 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) 1618 { 1619 const struct rtw89_chip_info *chip = rtwdev->chip; 1620 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1621 u8 regd = rtw89_regd_get(rtwdev, band); 1622 s8 lmt = 0, sar; 1623 1624 switch (band) { 1625 case RTW89_BAND_2G: 1626 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf][regd][ch_idx]; 1627 if (!lmt) 1628 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf] 1629 [RTW89_WW][ch_idx]; 1630 break; 1631 case RTW89_BAND_5G: 1632 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf][regd][ch_idx]; 1633 if (!lmt) 1634 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf] 1635 [RTW89_WW][ch_idx]; 1636 break; 1637 case RTW89_BAND_6G: 1638 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf][regd][ch_idx]; 1639 if (!lmt) 1640 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf] 1641 [RTW89_WW][ch_idx]; 1642 break; 1643 default: 1644 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1645 return 0; 1646 } 1647 1648 lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt); 1649 sar = rtw89_query_sar(rtwdev); 1650 1651 return min(lmt, sar); 1652 } 1653 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit); 1654 1655 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \ 1656 do { \ 1657 u8 __i; \ 1658 for (__i = 0; __i < RTW89_BF_NUM; __i++) \ 1659 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ 1660 band, \ 1661 bw, ntx, \ 1662 rs, __i, \ 1663 (ch)); \ 1664 } while (0) 1665 1666 static void rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev *rtwdev, 1667 struct rtw89_txpwr_limit *lmt, 1668 u8 band, u8 ntx, u8 ch) 1669 { 1670 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1671 ntx, RTW89_RS_CCK, ch); 1672 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1673 ntx, RTW89_RS_CCK, ch); 1674 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1675 ntx, RTW89_RS_OFDM, ch); 1676 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1677 RTW89_CHANNEL_WIDTH_20, 1678 ntx, RTW89_RS_MCS, ch); 1679 } 1680 1681 static void rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev *rtwdev, 1682 struct rtw89_txpwr_limit *lmt, 1683 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1684 { 1685 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1686 ntx, RTW89_RS_CCK, ch - 2); 1687 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1688 ntx, RTW89_RS_CCK, ch); 1689 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1690 ntx, RTW89_RS_OFDM, pri_ch); 1691 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1692 RTW89_CHANNEL_WIDTH_20, 1693 ntx, RTW89_RS_MCS, ch - 2); 1694 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1695 RTW89_CHANNEL_WIDTH_20, 1696 ntx, RTW89_RS_MCS, ch + 2); 1697 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1698 RTW89_CHANNEL_WIDTH_40, 1699 ntx, RTW89_RS_MCS, ch); 1700 } 1701 1702 static void rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev *rtwdev, 1703 struct rtw89_txpwr_limit *lmt, 1704 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1705 { 1706 s8 val_0p5_n[RTW89_BF_NUM]; 1707 s8 val_0p5_p[RTW89_BF_NUM]; 1708 u8 i; 1709 1710 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1711 ntx, RTW89_RS_OFDM, pri_ch); 1712 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1713 RTW89_CHANNEL_WIDTH_20, 1714 ntx, RTW89_RS_MCS, ch - 6); 1715 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1716 RTW89_CHANNEL_WIDTH_20, 1717 ntx, RTW89_RS_MCS, ch - 2); 1718 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1719 RTW89_CHANNEL_WIDTH_20, 1720 ntx, RTW89_RS_MCS, ch + 2); 1721 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1722 RTW89_CHANNEL_WIDTH_20, 1723 ntx, RTW89_RS_MCS, ch + 6); 1724 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1725 RTW89_CHANNEL_WIDTH_40, 1726 ntx, RTW89_RS_MCS, ch - 4); 1727 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1728 RTW89_CHANNEL_WIDTH_40, 1729 ntx, RTW89_RS_MCS, ch + 4); 1730 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1731 RTW89_CHANNEL_WIDTH_80, 1732 ntx, RTW89_RS_MCS, ch); 1733 1734 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1735 ntx, RTW89_RS_MCS, ch - 4); 1736 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1737 ntx, RTW89_RS_MCS, ch + 4); 1738 1739 for (i = 0; i < RTW89_BF_NUM; i++) 1740 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1741 } 1742 1743 static void rtw89_phy_fill_txpwr_limit_160m(struct rtw89_dev *rtwdev, 1744 struct rtw89_txpwr_limit *lmt, 1745 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1746 { 1747 s8 val_0p5_n[RTW89_BF_NUM]; 1748 s8 val_0p5_p[RTW89_BF_NUM]; 1749 s8 val_2p5_n[RTW89_BF_NUM]; 1750 s8 val_2p5_p[RTW89_BF_NUM]; 1751 u8 i; 1752 1753 /* fill ofdm section */ 1754 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1755 ntx, RTW89_RS_OFDM, pri_ch); 1756 1757 /* fill mcs 20m section */ 1758 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1759 RTW89_CHANNEL_WIDTH_20, 1760 ntx, RTW89_RS_MCS, ch - 14); 1761 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1762 RTW89_CHANNEL_WIDTH_20, 1763 ntx, RTW89_RS_MCS, ch - 10); 1764 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1765 RTW89_CHANNEL_WIDTH_20, 1766 ntx, RTW89_RS_MCS, ch - 6); 1767 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1768 RTW89_CHANNEL_WIDTH_20, 1769 ntx, RTW89_RS_MCS, ch - 2); 1770 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band, 1771 RTW89_CHANNEL_WIDTH_20, 1772 ntx, RTW89_RS_MCS, ch + 2); 1773 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band, 1774 RTW89_CHANNEL_WIDTH_20, 1775 ntx, RTW89_RS_MCS, ch + 6); 1776 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band, 1777 RTW89_CHANNEL_WIDTH_20, 1778 ntx, RTW89_RS_MCS, ch + 10); 1779 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band, 1780 RTW89_CHANNEL_WIDTH_20, 1781 ntx, RTW89_RS_MCS, ch + 14); 1782 1783 /* fill mcs 40m section */ 1784 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1785 RTW89_CHANNEL_WIDTH_40, 1786 ntx, RTW89_RS_MCS, ch - 12); 1787 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1788 RTW89_CHANNEL_WIDTH_40, 1789 ntx, RTW89_RS_MCS, ch - 4); 1790 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band, 1791 RTW89_CHANNEL_WIDTH_40, 1792 ntx, RTW89_RS_MCS, ch + 4); 1793 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band, 1794 RTW89_CHANNEL_WIDTH_40, 1795 ntx, RTW89_RS_MCS, ch + 12); 1796 1797 /* fill mcs 80m section */ 1798 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1799 RTW89_CHANNEL_WIDTH_80, 1800 ntx, RTW89_RS_MCS, ch - 8); 1801 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band, 1802 RTW89_CHANNEL_WIDTH_80, 1803 ntx, RTW89_RS_MCS, ch + 8); 1804 1805 /* fill mcs 160m section */ 1806 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band, 1807 RTW89_CHANNEL_WIDTH_160, 1808 ntx, RTW89_RS_MCS, ch); 1809 1810 /* fill mcs 40m 0p5 section */ 1811 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1812 ntx, RTW89_RS_MCS, ch - 4); 1813 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1814 ntx, RTW89_RS_MCS, ch + 4); 1815 1816 for (i = 0; i < RTW89_BF_NUM; i++) 1817 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1818 1819 /* fill mcs 40m 2p5 section */ 1820 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40, 1821 ntx, RTW89_RS_MCS, ch - 8); 1822 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40, 1823 ntx, RTW89_RS_MCS, ch + 8); 1824 1825 for (i = 0; i < RTW89_BF_NUM; i++) 1826 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]); 1827 } 1828 1829 static 1830 void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev, 1831 const struct rtw89_chan *chan, 1832 struct rtw89_txpwr_limit *lmt, 1833 u8 ntx) 1834 { 1835 u8 band = chan->band_type; 1836 u8 pri_ch = chan->primary_channel; 1837 u8 ch = chan->channel; 1838 u8 bw = chan->band_width; 1839 1840 memset(lmt, 0, sizeof(*lmt)); 1841 1842 switch (bw) { 1843 case RTW89_CHANNEL_WIDTH_20: 1844 rtw89_phy_fill_txpwr_limit_20m(rtwdev, lmt, band, ntx, ch); 1845 break; 1846 case RTW89_CHANNEL_WIDTH_40: 1847 rtw89_phy_fill_txpwr_limit_40m(rtwdev, lmt, band, ntx, ch, 1848 pri_ch); 1849 break; 1850 case RTW89_CHANNEL_WIDTH_80: 1851 rtw89_phy_fill_txpwr_limit_80m(rtwdev, lmt, band, ntx, ch, 1852 pri_ch); 1853 break; 1854 case RTW89_CHANNEL_WIDTH_160: 1855 rtw89_phy_fill_txpwr_limit_160m(rtwdev, lmt, band, ntx, ch, 1856 pri_ch); 1857 break; 1858 } 1859 } 1860 1861 static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 1862 u8 ru, u8 ntx, u8 ch) 1863 { 1864 const struct rtw89_chip_info *chip = rtwdev->chip; 1865 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1866 u8 regd = rtw89_regd_get(rtwdev, band); 1867 s8 lmt_ru = 0, sar; 1868 1869 switch (band) { 1870 case RTW89_BAND_2G: 1871 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx][regd][ch_idx]; 1872 if (!lmt_ru) 1873 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx] 1874 [RTW89_WW][ch_idx]; 1875 break; 1876 case RTW89_BAND_5G: 1877 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx][regd][ch_idx]; 1878 if (!lmt_ru) 1879 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx] 1880 [RTW89_WW][ch_idx]; 1881 break; 1882 case RTW89_BAND_6G: 1883 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx][regd][ch_idx]; 1884 if (!lmt_ru) 1885 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx] 1886 [RTW89_WW][ch_idx]; 1887 break; 1888 default: 1889 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1890 return 0; 1891 } 1892 1893 lmt_ru = _phy_txpwr_rf_to_mac(rtwdev, lmt_ru); 1894 sar = rtw89_query_sar(rtwdev); 1895 1896 return min(lmt_ru, sar); 1897 } 1898 1899 static void 1900 rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev, 1901 struct rtw89_txpwr_limit_ru *lmt_ru, 1902 u8 band, u8 ntx, u8 ch) 1903 { 1904 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1905 RTW89_RU26, 1906 ntx, ch); 1907 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1908 RTW89_RU52, 1909 ntx, ch); 1910 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1911 RTW89_RU106, 1912 ntx, ch); 1913 } 1914 1915 static void 1916 rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev, 1917 struct rtw89_txpwr_limit_ru *lmt_ru, 1918 u8 band, u8 ntx, u8 ch) 1919 { 1920 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1921 RTW89_RU26, 1922 ntx, ch - 2); 1923 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1924 RTW89_RU26, 1925 ntx, ch + 2); 1926 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1927 RTW89_RU52, 1928 ntx, ch - 2); 1929 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1930 RTW89_RU52, 1931 ntx, ch + 2); 1932 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1933 RTW89_RU106, 1934 ntx, ch - 2); 1935 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1936 RTW89_RU106, 1937 ntx, ch + 2); 1938 } 1939 1940 static void 1941 rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev, 1942 struct rtw89_txpwr_limit_ru *lmt_ru, 1943 u8 band, u8 ntx, u8 ch) 1944 { 1945 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1946 RTW89_RU26, 1947 ntx, ch - 6); 1948 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1949 RTW89_RU26, 1950 ntx, ch - 2); 1951 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1952 RTW89_RU26, 1953 ntx, ch + 2); 1954 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1955 RTW89_RU26, 1956 ntx, ch + 6); 1957 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1958 RTW89_RU52, 1959 ntx, ch - 6); 1960 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1961 RTW89_RU52, 1962 ntx, ch - 2); 1963 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1964 RTW89_RU52, 1965 ntx, ch + 2); 1966 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1967 RTW89_RU52, 1968 ntx, ch + 6); 1969 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1970 RTW89_RU106, 1971 ntx, ch - 6); 1972 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1973 RTW89_RU106, 1974 ntx, ch - 2); 1975 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1976 RTW89_RU106, 1977 ntx, ch + 2); 1978 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1979 RTW89_RU106, 1980 ntx, ch + 6); 1981 } 1982 1983 static void 1984 rtw89_phy_fill_txpwr_limit_ru_160m(struct rtw89_dev *rtwdev, 1985 struct rtw89_txpwr_limit_ru *lmt_ru, 1986 u8 band, u8 ntx, u8 ch) 1987 { 1988 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 }; 1989 int i; 1990 1991 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM); 1992 for (i = 0; i < RTW89_RU_SEC_NUM; i++) { 1993 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1994 RTW89_RU26, 1995 ntx, 1996 ch + ofst[i]); 1997 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1998 RTW89_RU52, 1999 ntx, 2000 ch + ofst[i]); 2001 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2002 RTW89_RU106, 2003 ntx, 2004 ch + ofst[i]); 2005 } 2006 } 2007 2008 static 2009 void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, 2010 const struct rtw89_chan *chan, 2011 struct rtw89_txpwr_limit_ru *lmt_ru, 2012 u8 ntx) 2013 { 2014 u8 band = chan->band_type; 2015 u8 ch = chan->channel; 2016 u8 bw = chan->band_width; 2017 2018 memset(lmt_ru, 0, sizeof(*lmt_ru)); 2019 2020 switch (bw) { 2021 case RTW89_CHANNEL_WIDTH_20: 2022 rtw89_phy_fill_txpwr_limit_ru_20m(rtwdev, lmt_ru, band, ntx, 2023 ch); 2024 break; 2025 case RTW89_CHANNEL_WIDTH_40: 2026 rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, band, ntx, 2027 ch); 2028 break; 2029 case RTW89_CHANNEL_WIDTH_80: 2030 rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, band, ntx, 2031 ch); 2032 break; 2033 case RTW89_CHANNEL_WIDTH_160: 2034 rtw89_phy_fill_txpwr_limit_ru_160m(rtwdev, lmt_ru, band, ntx, 2035 ch); 2036 break; 2037 } 2038 } 2039 2040 void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev, 2041 const struct rtw89_chan *chan, 2042 enum rtw89_phy_idx phy_idx) 2043 { 2044 static const u8 rs[] = { 2045 RTW89_RS_CCK, 2046 RTW89_RS_OFDM, 2047 RTW89_RS_MCS, 2048 RTW89_RS_HEDCM, 2049 }; 2050 struct rtw89_rate_desc cur; 2051 u8 band = chan->band_type; 2052 u8 ch = chan->channel; 2053 u32 addr, val; 2054 s8 v[4] = {}; 2055 u8 i; 2056 2057 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2058 "[TXPWR] set txpwr byrate with ch=%d\n", ch); 2059 2060 BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_CCK] % 4); 2061 BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_OFDM] % 4); 2062 BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_MCS] % 4); 2063 BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_HEDCM] % 4); 2064 2065 addr = R_AX_PWR_BY_RATE; 2066 for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) { 2067 for (i = 0; i < ARRAY_SIZE(rs); i++) { 2068 if (cur.nss >= rtw89_rs_nss_max[rs[i]]) 2069 continue; 2070 2071 cur.rs = rs[i]; 2072 for (cur.idx = 0; cur.idx < rtw89_rs_idx_max[rs[i]]; 2073 cur.idx++) { 2074 v[cur.idx % 4] = 2075 rtw89_phy_read_txpwr_byrate(rtwdev, 2076 band, 2077 &cur); 2078 2079 if ((cur.idx + 1) % 4) 2080 continue; 2081 2082 val = FIELD_PREP(GENMASK(7, 0), v[0]) | 2083 FIELD_PREP(GENMASK(15, 8), v[1]) | 2084 FIELD_PREP(GENMASK(23, 16), v[2]) | 2085 FIELD_PREP(GENMASK(31, 24), v[3]); 2086 2087 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 2088 val); 2089 addr += 4; 2090 } 2091 } 2092 } 2093 } 2094 EXPORT_SYMBOL(rtw89_phy_set_txpwr_byrate); 2095 2096 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev, 2097 const struct rtw89_chan *chan, 2098 enum rtw89_phy_idx phy_idx) 2099 { 2100 struct rtw89_rate_desc desc = { 2101 .nss = RTW89_NSS_1, 2102 .rs = RTW89_RS_OFFSET, 2103 }; 2104 u8 band = chan->band_type; 2105 s8 v[RTW89_RATE_OFFSET_MAX] = {}; 2106 u32 val; 2107 2108 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n"); 2109 2110 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++) 2111 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, &desc); 2112 2113 BUILD_BUG_ON(RTW89_RATE_OFFSET_MAX != 5); 2114 val = FIELD_PREP(GENMASK(3, 0), v[0]) | 2115 FIELD_PREP(GENMASK(7, 4), v[1]) | 2116 FIELD_PREP(GENMASK(11, 8), v[2]) | 2117 FIELD_PREP(GENMASK(15, 12), v[3]) | 2118 FIELD_PREP(GENMASK(19, 16), v[4]); 2119 2120 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL, 2121 GENMASK(19, 0), val); 2122 } 2123 EXPORT_SYMBOL(rtw89_phy_set_txpwr_offset); 2124 2125 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev, 2126 const struct rtw89_chan *chan, 2127 enum rtw89_phy_idx phy_idx) 2128 { 2129 struct rtw89_txpwr_limit lmt; 2130 u8 ch = chan->channel; 2131 u8 bw = chan->band_width; 2132 const s8 *ptr; 2133 u32 addr, val; 2134 u8 i, j; 2135 2136 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2137 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw); 2138 2139 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit) != 2140 RTW89_TXPWR_LMT_PAGE_SIZE); 2141 2142 addr = R_AX_PWR_LMT; 2143 for (i = 0; i < RTW89_NTX_NUM; i++) { 2144 rtw89_phy_fill_txpwr_limit(rtwdev, chan, &lmt, i); 2145 2146 ptr = (s8 *)&lmt; 2147 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE; 2148 j += 4, addr += 4, ptr += 4) { 2149 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2150 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2151 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2152 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2153 2154 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2155 } 2156 } 2157 } 2158 EXPORT_SYMBOL(rtw89_phy_set_txpwr_limit); 2159 2160 void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, 2161 const struct rtw89_chan *chan, 2162 enum rtw89_phy_idx phy_idx) 2163 { 2164 struct rtw89_txpwr_limit_ru lmt_ru; 2165 u8 ch = chan->channel; 2166 u8 bw = chan->band_width; 2167 const s8 *ptr; 2168 u32 addr, val; 2169 u8 i, j; 2170 2171 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2172 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); 2173 2174 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru) != 2175 RTW89_TXPWR_LMT_RU_PAGE_SIZE); 2176 2177 addr = R_AX_PWR_RU_LMT; 2178 for (i = 0; i < RTW89_NTX_NUM; i++) { 2179 rtw89_phy_fill_txpwr_limit_ru(rtwdev, chan, &lmt_ru, i); 2180 2181 ptr = (s8 *)&lmt_ru; 2182 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE; 2183 j += 4, addr += 4, ptr += 4) { 2184 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2185 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2186 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2187 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2188 2189 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2190 } 2191 } 2192 } 2193 EXPORT_SYMBOL(rtw89_phy_set_txpwr_limit_ru); 2194 2195 struct rtw89_phy_iter_ra_data { 2196 struct rtw89_dev *rtwdev; 2197 struct sk_buff *c2h; 2198 }; 2199 2200 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) 2201 { 2202 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; 2203 struct rtw89_dev *rtwdev = ra_data->rtwdev; 2204 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2205 struct rtw89_ra_report *ra_report = &rtwsta->ra_report; 2206 struct sk_buff *c2h = ra_data->c2h; 2207 u8 mode, rate, bw, giltf, mac_id; 2208 u16 legacy_bitrate; 2209 bool valid; 2210 u8 mcs = 0; 2211 2212 mac_id = RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h->data); 2213 if (mac_id != rtwsta->mac_id) 2214 return; 2215 2216 rate = RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h->data); 2217 bw = RTW89_GET_PHY_C2H_RA_RPT_BW(c2h->data); 2218 giltf = RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h->data); 2219 mode = RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h->data); 2220 2221 if (mode == RTW89_RA_RPT_MODE_LEGACY) { 2222 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate); 2223 if (!valid) 2224 return; 2225 } 2226 2227 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate)); 2228 2229 switch (mode) { 2230 case RTW89_RA_RPT_MODE_LEGACY: 2231 ra_report->txrate.legacy = legacy_bitrate; 2232 break; 2233 case RTW89_RA_RPT_MODE_HT: 2234 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; 2235 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw)) 2236 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), 2237 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); 2238 else 2239 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); 2240 ra_report->txrate.mcs = rate; 2241 if (giltf) 2242 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2243 mcs = ra_report->txrate.mcs & 0x07; 2244 break; 2245 case RTW89_RA_RPT_MODE_VHT: 2246 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; 2247 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 2248 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 2249 if (giltf) 2250 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2251 mcs = ra_report->txrate.mcs; 2252 break; 2253 case RTW89_RA_RPT_MODE_HE: 2254 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; 2255 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 2256 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 2257 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2258 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; 2259 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2260 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; 2261 else 2262 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; 2263 mcs = ra_report->txrate.mcs; 2264 break; 2265 } 2266 2267 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw); 2268 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); 2269 ra_report->hw_rate = FIELD_PREP(RTW89_HW_RATE_MASK_MOD, mode) | 2270 FIELD_PREP(RTW89_HW_RATE_MASK_VAL, rate); 2271 ra_report->might_fallback_legacy = mcs <= 2; 2272 sta->deflink.agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); 2273 rtwsta->max_agg_wait = sta->deflink.agg.max_rc_amsdu_len / 1500 - 1; 2274 } 2275 2276 static void 2277 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2278 { 2279 struct rtw89_phy_iter_ra_data ra_data; 2280 2281 ra_data.rtwdev = rtwdev; 2282 ra_data.c2h = c2h; 2283 ieee80211_iterate_stations_atomic(rtwdev->hw, 2284 rtw89_phy_c2h_ra_rpt_iter, 2285 &ra_data); 2286 } 2287 2288 static 2289 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, 2290 struct sk_buff *c2h, u32 len) = { 2291 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 2292 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 2293 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 2294 }; 2295 2296 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 2297 u32 len, u8 class, u8 func) 2298 { 2299 void (*handler)(struct rtw89_dev *rtwdev, 2300 struct sk_buff *c2h, u32 len) = NULL; 2301 2302 switch (class) { 2303 case RTW89_PHY_C2H_CLASS_RA: 2304 if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 2305 handler = rtw89_phy_c2h_ra_handler[func]; 2306 break; 2307 case RTW89_PHY_C2H_CLASS_DM: 2308 if (func == RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY) 2309 return; 2310 fallthrough; 2311 default: 2312 rtw89_info(rtwdev, "c2h class %d not support\n", class); 2313 return; 2314 } 2315 if (!handler) { 2316 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 2317 func); 2318 return; 2319 } 2320 handler(rtwdev, skb, len); 2321 } 2322 2323 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) 2324 { 2325 u32 reg_mask; 2326 2327 if (sc_xo) 2328 reg_mask = B_AX_XTAL_SC_XO_MASK; 2329 else 2330 reg_mask = B_AX_XTAL_SC_XI_MASK; 2331 2332 return (u8)rtw89_read32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask); 2333 } 2334 2335 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, 2336 u8 val) 2337 { 2338 u32 reg_mask; 2339 2340 if (sc_xo) 2341 reg_mask = B_AX_XTAL_SC_XO_MASK; 2342 else 2343 reg_mask = B_AX_XTAL_SC_XI_MASK; 2344 2345 rtw89_write32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask, val); 2346 } 2347 2348 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, 2349 u8 crystal_cap, bool force) 2350 { 2351 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2352 const struct rtw89_chip_info *chip = rtwdev->chip; 2353 u8 sc_xi_val, sc_xo_val; 2354 2355 if (!force && cfo->crystal_cap == crystal_cap) 2356 return; 2357 crystal_cap = clamp_t(u8, crystal_cap, 0, 127); 2358 if (chip->chip_id == RTL8852A) { 2359 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); 2360 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); 2361 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); 2362 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); 2363 } else { 2364 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, 2365 crystal_cap, XTAL_SC_XO_MASK); 2366 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, 2367 crystal_cap, XTAL_SC_XI_MASK); 2368 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val); 2369 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val); 2370 } 2371 cfo->crystal_cap = sc_xi_val; 2372 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); 2373 2374 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); 2375 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); 2376 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", 2377 cfo->x_cap_ofst); 2378 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); 2379 } 2380 2381 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) 2382 { 2383 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2384 u8 cap; 2385 2386 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; 2387 cfo->is_adjust = false; 2388 if (cfo->crystal_cap == cfo->def_x_cap) 2389 return; 2390 cap = cfo->crystal_cap; 2391 cap += (cap > cfo->def_x_cap ? -1 : 1); 2392 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); 2393 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2394 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, 2395 cfo->def_x_cap); 2396 } 2397 2398 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) 2399 { 2400 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp; 2401 bool is_linked = rtwdev->total_sta_assoc > 0; 2402 s32 cfo_avg_312; 2403 s32 dcfo_comp_val; 2404 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft; 2405 int sign; 2406 2407 if (!is_linked) { 2408 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", 2409 is_linked); 2410 return; 2411 } 2412 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); 2413 if (curr_cfo == 0) 2414 return; 2415 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); 2416 sign = curr_cfo > 0 ? 1 : -1; 2417 cfo_avg_312 = (curr_cfo << dcfo_comp_sft) / 5 + sign * dcfo_comp_val; 2418 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: avg_cfo=%d\n", cfo_avg_312); 2419 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 2420 cfo_avg_312 = -cfo_avg_312; 2421 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask, 2422 cfo_avg_312); 2423 } 2424 2425 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) 2426 { 2427 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_OPT, B_DCFO_OPT_EN, 1); 2428 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_WEIGHT, B_DCFO_WEIGHT_MSK, 8); 2429 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, B_AX_PWR_UL_CFO_MASK); 2430 } 2431 2432 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) 2433 { 2434 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2435 struct rtw89_efuse *efuse = &rtwdev->efuse; 2436 2437 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; 2438 cfo->crystal_cap = cfo->crystal_cap_default; 2439 cfo->def_x_cap = cfo->crystal_cap; 2440 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f); 2441 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1); 2442 cfo->is_adjust = false; 2443 cfo->divergence_lock_en = false; 2444 cfo->x_cap_ofst = 0; 2445 cfo->lock_cnt = 0; 2446 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; 2447 cfo->apply_compensation = false; 2448 cfo->residual_cfo_acc = 0; 2449 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", 2450 cfo->crystal_cap_default); 2451 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); 2452 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); 2453 rtw89_dcfo_comp_init(rtwdev); 2454 cfo->cfo_timer_ms = 2000; 2455 cfo->cfo_trig_by_timer_en = false; 2456 cfo->phy_cfo_trk_cnt = 0; 2457 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2458 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE; 2459 } 2460 2461 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, 2462 s32 curr_cfo) 2463 { 2464 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2465 s8 crystal_cap = cfo->crystal_cap; 2466 s32 cfo_abs = abs(curr_cfo); 2467 int sign; 2468 2469 if (!cfo->is_adjust) { 2470 if (cfo_abs > CFO_TRK_ENABLE_TH) 2471 cfo->is_adjust = true; 2472 } else { 2473 if (cfo_abs < CFO_TRK_STOP_TH) 2474 cfo->is_adjust = false; 2475 } 2476 if (!cfo->is_adjust) { 2477 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); 2478 return; 2479 } 2480 sign = curr_cfo > 0 ? 1 : -1; 2481 if (cfo_abs > CFO_TRK_STOP_TH_4) 2482 crystal_cap += 7 * sign; 2483 else if (cfo_abs > CFO_TRK_STOP_TH_3) 2484 crystal_cap += 5 * sign; 2485 else if (cfo_abs > CFO_TRK_STOP_TH_2) 2486 crystal_cap += 3 * sign; 2487 else if (cfo_abs > CFO_TRK_STOP_TH_1) 2488 crystal_cap += 1 * sign; 2489 else 2490 return; 2491 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); 2492 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2493 "X_cap{Curr,Default}={0x%x,0x%x}\n", 2494 cfo->crystal_cap, cfo->def_x_cap); 2495 } 2496 2497 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) 2498 { 2499 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2500 s32 cfo_khz_all = 0; 2501 s32 cfo_cnt_all = 0; 2502 s32 cfo_all_avg = 0; 2503 u8 i; 2504 2505 if (rtwdev->total_sta_assoc != 1) 2506 return 0; 2507 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); 2508 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2509 if (cfo->cfo_cnt[i] == 0) 2510 continue; 2511 cfo_khz_all += cfo->cfo_tail[i]; 2512 cfo_cnt_all += cfo->cfo_cnt[i]; 2513 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); 2514 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2515 } 2516 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2517 "CFO track for macid = %d\n", i); 2518 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2519 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", 2520 cfo_khz_all, cfo_cnt_all, cfo_all_avg); 2521 return cfo_all_avg; 2522 } 2523 2524 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) 2525 { 2526 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2527 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2528 s32 target_cfo = 0; 2529 s32 cfo_khz_all = 0; 2530 s32 cfo_khz_all_tp_wgt = 0; 2531 s32 cfo_avg = 0; 2532 s32 max_cfo_lb = BIT(31); 2533 s32 min_cfo_ub = GENMASK(30, 0); 2534 u16 cfo_cnt_all = 0; 2535 u8 active_entry_cnt = 0; 2536 u8 sta_cnt = 0; 2537 u32 tp_all = 0; 2538 u8 i; 2539 u8 cfo_tol = 0; 2540 2541 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); 2542 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { 2543 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); 2544 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2545 if (cfo->cfo_cnt[i] == 0) 2546 continue; 2547 cfo_khz_all += cfo->cfo_tail[i]; 2548 cfo_cnt_all += cfo->cfo_cnt[i]; 2549 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); 2550 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2551 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", 2552 cfo_khz_all, cfo_cnt_all, cfo_avg); 2553 target_cfo = cfo_avg; 2554 } 2555 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { 2556 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); 2557 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2558 if (cfo->cfo_cnt[i] == 0) 2559 continue; 2560 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2561 (s32)cfo->cfo_cnt[i]); 2562 cfo_khz_all += cfo->cfo_avg[i]; 2563 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2564 "Macid=%d, cfo_avg=%d\n", i, 2565 cfo->cfo_avg[i]); 2566 } 2567 sta_cnt = rtwdev->total_sta_assoc; 2568 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); 2569 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2570 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", 2571 cfo_khz_all, sta_cnt, cfo_avg); 2572 target_cfo = cfo_avg; 2573 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { 2574 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); 2575 cfo_tol = cfo->sta_cfo_tolerance; 2576 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2577 sta_cnt++; 2578 if (cfo->cfo_cnt[i] != 0) { 2579 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2580 (s32)cfo->cfo_cnt[i]); 2581 active_entry_cnt++; 2582 } else { 2583 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; 2584 } 2585 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); 2586 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); 2587 cfo_khz_all += cfo->cfo_avg[i]; 2588 /* need tp for each entry */ 2589 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2590 "[%d] cfo_avg=%d, tp=tbd\n", 2591 i, cfo->cfo_avg[i]); 2592 if (sta_cnt >= rtwdev->total_sta_assoc) 2593 break; 2594 } 2595 tp_all = stats->rx_throughput; /* need tp for each entry */ 2596 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); 2597 2598 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", 2599 sta_cnt); 2600 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", 2601 active_entry_cnt); 2602 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2603 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", 2604 cfo_khz_all_tp_wgt, cfo_avg); 2605 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", 2606 max_cfo_lb, min_cfo_ub); 2607 if (max_cfo_lb <= min_cfo_ub) { 2608 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2609 "cfo win_size=%d\n", 2610 min_cfo_ub - max_cfo_lb); 2611 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); 2612 } else { 2613 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2614 "No intersection of cfo tolerance windows\n"); 2615 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); 2616 } 2617 for (i = 0; i < CFO_TRACK_MAX_USER; i++) 2618 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2619 } 2620 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); 2621 return target_cfo; 2622 } 2623 2624 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) 2625 { 2626 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2627 2628 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); 2629 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); 2630 cfo->packet_count = 0; 2631 cfo->packet_count_pre = 0; 2632 cfo->cfo_avg_pre = 0; 2633 } 2634 2635 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) 2636 { 2637 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2638 s32 new_cfo = 0; 2639 bool x_cap_update = false; 2640 u8 pre_x_cap = cfo->crystal_cap; 2641 2642 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", 2643 rtwdev->total_sta_assoc); 2644 if (rtwdev->total_sta_assoc == 0) { 2645 rtw89_phy_cfo_reset(rtwdev); 2646 return; 2647 } 2648 if (cfo->packet_count == 0) { 2649 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); 2650 return; 2651 } 2652 if (cfo->packet_count == cfo->packet_count_pre) { 2653 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); 2654 return; 2655 } 2656 if (rtwdev->total_sta_assoc == 1) 2657 new_cfo = rtw89_phy_average_cfo_calc(rtwdev); 2658 else 2659 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); 2660 if (new_cfo == 0) { 2661 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); 2662 return; 2663 } 2664 if (cfo->divergence_lock_en) { 2665 cfo->lock_cnt++; 2666 if (cfo->lock_cnt > CFO_PERIOD_CNT) { 2667 cfo->divergence_lock_en = false; 2668 cfo->lock_cnt = 0; 2669 } else { 2670 rtw89_phy_cfo_reset(rtwdev); 2671 } 2672 return; 2673 } 2674 if (cfo->crystal_cap >= cfo->x_cap_ub || 2675 cfo->crystal_cap <= cfo->x_cap_lb) { 2676 cfo->divergence_lock_en = true; 2677 rtw89_phy_cfo_reset(rtwdev); 2678 return; 2679 } 2680 2681 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); 2682 cfo->cfo_avg_pre = new_cfo; 2683 x_cap_update = cfo->crystal_cap != pre_x_cap; 2684 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); 2685 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", 2686 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, 2687 cfo->x_cap_ofst); 2688 if (x_cap_update) { 2689 if (new_cfo > 0) 2690 new_cfo -= CFO_SW_COMP_FINE_TUNE; 2691 else 2692 new_cfo += CFO_SW_COMP_FINE_TUNE; 2693 } 2694 rtw89_dcfo_comp(rtwdev, new_cfo); 2695 rtw89_phy_cfo_statistics_reset(rtwdev); 2696 } 2697 2698 void rtw89_phy_cfo_track_work(struct work_struct *work) 2699 { 2700 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2701 cfo_track_work.work); 2702 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2703 2704 mutex_lock(&rtwdev->mutex); 2705 if (!cfo->cfo_trig_by_timer_en) 2706 goto out; 2707 rtw89_leave_ps_mode(rtwdev); 2708 rtw89_phy_cfo_dm(rtwdev); 2709 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2710 msecs_to_jiffies(cfo->cfo_timer_ms)); 2711 out: 2712 mutex_unlock(&rtwdev->mutex); 2713 } 2714 2715 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) 2716 { 2717 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2718 2719 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2720 msecs_to_jiffies(cfo->cfo_timer_ms)); 2721 } 2722 2723 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) 2724 { 2725 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2726 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2727 bool is_ul_ofdma = false, ofdma_acc_en = false; 2728 2729 if (stats->rx_tf_periodic > CFO_TF_CNT_TH) 2730 is_ul_ofdma = true; 2731 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE && 2732 is_ul_ofdma) 2733 ofdma_acc_en = true; 2734 2735 switch (cfo->phy_cfo_status) { 2736 case RTW89_PHY_DCFO_STATE_NORMAL: 2737 if (stats->tx_throughput >= CFO_TP_UPPER) { 2738 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; 2739 cfo->cfo_trig_by_timer_en = true; 2740 cfo->cfo_timer_ms = CFO_COMP_PERIOD; 2741 rtw89_phy_cfo_start_work(rtwdev); 2742 } 2743 break; 2744 case RTW89_PHY_DCFO_STATE_ENHANCE: 2745 if (stats->tx_throughput <= CFO_TP_LOWER) 2746 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2747 else if (ofdma_acc_en && 2748 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) 2749 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD; 2750 else 2751 cfo->phy_cfo_trk_cnt++; 2752 2753 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) { 2754 cfo->phy_cfo_trk_cnt = 0; 2755 cfo->cfo_trig_by_timer_en = false; 2756 } 2757 break; 2758 case RTW89_PHY_DCFO_STATE_HOLD: 2759 if (stats->tx_throughput <= CFO_TP_LOWER) { 2760 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2761 cfo->phy_cfo_trk_cnt = 0; 2762 cfo->cfo_trig_by_timer_en = false; 2763 } else { 2764 cfo->phy_cfo_trk_cnt++; 2765 } 2766 break; 2767 default: 2768 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2769 cfo->phy_cfo_trk_cnt = 0; 2770 break; 2771 } 2772 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2773 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", 2774 stats->tx_throughput, cfo->phy_cfo_status, 2775 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, 2776 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); 2777 if (cfo->cfo_trig_by_timer_en) 2778 return; 2779 rtw89_phy_cfo_dm(rtwdev); 2780 } 2781 2782 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 2783 struct rtw89_rx_phy_ppdu *phy_ppdu) 2784 { 2785 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2786 u8 macid = phy_ppdu->mac_id; 2787 2788 if (macid >= CFO_TRACK_MAX_USER) { 2789 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid); 2790 return; 2791 } 2792 2793 cfo->cfo_tail[macid] += cfo_val; 2794 cfo->cfo_cnt[macid]++; 2795 cfo->packet_count++; 2796 } 2797 2798 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2799 { 2800 const struct rtw89_chip_info *chip = rtwdev->chip; 2801 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 2802 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 2803 2804 if (!chip->support_ul_tb_ctrl) 2805 return; 2806 2807 rtwvif->def_tri_idx = 2808 rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG); 2809 2810 if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV) 2811 rtwvif->dyn_tb_bedge_en = false; 2812 else if (chan->band_type >= RTW89_BAND_5G && 2813 chan->band_width >= RTW89_CHANNEL_WIDTH_40) 2814 rtwvif->dyn_tb_bedge_en = true; 2815 else 2816 rtwvif->dyn_tb_bedge_en = false; 2817 2818 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2819 "[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n", 2820 ul_tb_info->def_if_bandedge, rtwvif->def_tri_idx); 2821 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2822 "[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n", 2823 rtwvif->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en); 2824 } 2825 2826 struct rtw89_phy_ul_tb_check_data { 2827 bool valid; 2828 bool high_tf_client; 2829 bool low_tf_client; 2830 bool dyn_tb_bedge_en; 2831 u8 def_tri_idx; 2832 }; 2833 2834 static 2835 void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev, 2836 struct rtw89_vif *rtwvif, 2837 struct rtw89_phy_ul_tb_check_data *ul_tb_data) 2838 { 2839 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2840 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2841 2842 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 2843 return; 2844 2845 if (!vif->cfg.assoc) 2846 return; 2847 2848 if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH) 2849 ul_tb_data->high_tf_client = true; 2850 else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH) 2851 ul_tb_data->low_tf_client = true; 2852 2853 ul_tb_data->valid = true; 2854 ul_tb_data->def_tri_idx = rtwvif->def_tri_idx; 2855 ul_tb_data->dyn_tb_bedge_en = rtwvif->dyn_tb_bedge_en; 2856 } 2857 2858 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev) 2859 { 2860 const struct rtw89_chip_info *chip = rtwdev->chip; 2861 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 2862 struct rtw89_phy_ul_tb_check_data ul_tb_data = {}; 2863 struct rtw89_vif *rtwvif; 2864 2865 if (!chip->support_ul_tb_ctrl) 2866 return; 2867 2868 if (rtwdev->total_sta_assoc != 1) 2869 return; 2870 2871 rtw89_for_each_rtwvif(rtwdev, rtwvif) 2872 rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif, &ul_tb_data); 2873 2874 if (!ul_tb_data.valid) 2875 return; 2876 2877 if (ul_tb_data.dyn_tb_bedge_en) { 2878 if (ul_tb_data.high_tf_client) { 2879 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0); 2880 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2881 "[ULTB] Turn off if_bandedge\n"); 2882 } else if (ul_tb_data.low_tf_client) { 2883 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 2884 ul_tb_info->def_if_bandedge); 2885 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2886 "[ULTB] Set to default if_bandedge = %d\n", 2887 ul_tb_info->def_if_bandedge); 2888 } 2889 } 2890 2891 if (ul_tb_info->dyn_tb_tri_en) { 2892 if (ul_tb_data.high_tf_client) { 2893 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 2894 B_TXSHAPE_TRIANGULAR_CFG, 0); 2895 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2896 "[ULTB] Turn off Tx triangle\n"); 2897 } else if (ul_tb_data.low_tf_client) { 2898 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 2899 B_TXSHAPE_TRIANGULAR_CFG, 2900 ul_tb_data.def_tri_idx); 2901 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2902 "[ULTB] Set to default tx_shap_idx = %d\n", 2903 ul_tb_data.def_tri_idx); 2904 } 2905 } 2906 } 2907 2908 static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev) 2909 { 2910 const struct rtw89_chip_info *chip = rtwdev->chip; 2911 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 2912 2913 if (!chip->support_ul_tb_ctrl) 2914 return; 2915 2916 ul_tb_info->dyn_tb_tri_en = true; 2917 ul_tb_info->def_if_bandedge = 2918 rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN); 2919 } 2920 2921 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) 2922 { 2923 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2924 int i; 2925 u8 th; 2926 2927 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 2928 th = rtw89_chip_get_thermal(rtwdev, i); 2929 if (th) 2930 ewma_thermal_add(&phystat->avg_thermal[i], th); 2931 2932 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 2933 "path(%d) thermal cur=%u avg=%ld", i, th, 2934 ewma_thermal_read(&phystat->avg_thermal[i])); 2935 } 2936 } 2937 2938 struct rtw89_phy_iter_rssi_data { 2939 struct rtw89_dev *rtwdev; 2940 struct rtw89_phy_ch_info *ch_info; 2941 bool rssi_changed; 2942 }; 2943 2944 static void rtw89_phy_stat_rssi_update_iter(void *data, 2945 struct ieee80211_sta *sta) 2946 { 2947 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2948 struct rtw89_phy_iter_rssi_data *rssi_data = 2949 (struct rtw89_phy_iter_rssi_data *)data; 2950 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info; 2951 unsigned long rssi_curr; 2952 2953 rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi); 2954 2955 if (rssi_curr < ch_info->rssi_min) { 2956 ch_info->rssi_min = rssi_curr; 2957 ch_info->rssi_min_macid = rtwsta->mac_id; 2958 } 2959 2960 if (rtwsta->prev_rssi == 0) { 2961 rtwsta->prev_rssi = rssi_curr; 2962 } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) { 2963 rtwsta->prev_rssi = rssi_curr; 2964 rssi_data->rssi_changed = true; 2965 } 2966 } 2967 2968 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) 2969 { 2970 struct rtw89_phy_iter_rssi_data rssi_data = {0}; 2971 2972 rssi_data.rtwdev = rtwdev; 2973 rssi_data.ch_info = &rtwdev->ch_info; 2974 rssi_data.ch_info->rssi_min = U8_MAX; 2975 ieee80211_iterate_stations_atomic(rtwdev->hw, 2976 rtw89_phy_stat_rssi_update_iter, 2977 &rssi_data); 2978 if (rssi_data.rssi_changed) 2979 rtw89_btc_ntfy_wl_sta(rtwdev); 2980 } 2981 2982 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) 2983 { 2984 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2985 int i; 2986 2987 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 2988 ewma_thermal_init(&phystat->avg_thermal[i]); 2989 2990 rtw89_phy_stat_thermal_update(rtwdev); 2991 2992 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 2993 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); 2994 } 2995 2996 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) 2997 { 2998 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2999 3000 rtw89_phy_stat_thermal_update(rtwdev); 3001 rtw89_phy_stat_rssi_update(rtwdev); 3002 3003 phystat->last_pkt_stat = phystat->cur_pkt_stat; 3004 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 3005 } 3006 3007 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us) 3008 { 3009 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3010 3011 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 3012 } 3013 3014 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) 3015 { 3016 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3017 3018 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 3019 } 3020 3021 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) 3022 { 3023 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3024 3025 env->ccx_manual_ctrl = false; 3026 env->ccx_ongoing = false; 3027 env->ccx_rac_lv = RTW89_RAC_RELEASE; 3028 env->ccx_rpt_stamp = 0; 3029 env->ccx_period = 0; 3030 env->ccx_unit_idx = RTW89_CCX_32_US; 3031 env->ccx_trigger_time = 0; 3032 env->ccx_edcca_opt_bw_idx = RTW89_CCX_EDCCA_BW20_0; 3033 3034 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1); 3035 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1); 3036 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 3037 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EDCCA_OPT_MSK, 3038 RTW89_CCX_EDCCA_BW20_0); 3039 } 3040 3041 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report, 3042 u16 score) 3043 { 3044 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3045 u32 numer = 0; 3046 u16 ret = 0; 3047 3048 numer = report * score + (env->ccx_period >> 1); 3049 if (env->ccx_period) 3050 ret = numer / env->ccx_period; 3051 3052 return ret >= score ? score - 1 : ret; 3053 } 3054 3055 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, 3056 u16 time_ms, u32 *period, 3057 u32 *unit_idx) 3058 { 3059 u32 idx; 3060 u8 quotient; 3061 3062 if (time_ms >= CCX_MAX_PERIOD) 3063 time_ms = CCX_MAX_PERIOD; 3064 3065 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; 3066 3067 if (quotient < 4) 3068 idx = RTW89_CCX_4_US; 3069 else if (quotient < 8) 3070 idx = RTW89_CCX_8_US; 3071 else if (quotient < 16) 3072 idx = RTW89_CCX_16_US; 3073 else 3074 idx = RTW89_CCX_32_US; 3075 3076 *unit_idx = idx; 3077 *period = (time_ms * MS_TO_4US_RATIO) >> idx; 3078 3079 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3080 "[Trigger Time] period:%d, unit_idx:%d\n", 3081 *period, *unit_idx); 3082 } 3083 3084 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev) 3085 { 3086 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3087 3088 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3089 "lv:(%d)->(0)\n", env->ccx_rac_lv); 3090 3091 env->ccx_ongoing = false; 3092 env->ccx_rac_lv = RTW89_RAC_RELEASE; 3093 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3094 } 3095 3096 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, 3097 struct rtw89_ccx_para_info *para) 3098 { 3099 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3100 bool is_update = env->ifs_clm_app != para->ifs_clm_app; 3101 u8 i = 0; 3102 u16 *ifs_th_l = env->ifs_clm_th_l; 3103 u16 *ifs_th_h = env->ifs_clm_th_h; 3104 u32 ifs_th0_us = 0, ifs_th_times = 0; 3105 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; 3106 3107 if (!is_update) 3108 goto ifs_update_finished; 3109 3110 switch (para->ifs_clm_app) { 3111 case RTW89_IFS_CLM_INIT: 3112 case RTW89_IFS_CLM_BACKGROUND: 3113 case RTW89_IFS_CLM_ACS: 3114 case RTW89_IFS_CLM_DBG: 3115 case RTW89_IFS_CLM_DIG: 3116 case RTW89_IFS_CLM_TDMA_DIG: 3117 ifs_th0_us = IFS_CLM_TH0_UPPER; 3118 ifs_th_times = IFS_CLM_TH_MUL; 3119 break; 3120 case RTW89_IFS_CLM_DBG_MANUAL: 3121 ifs_th0_us = para->ifs_clm_manual_th0; 3122 ifs_th_times = para->ifs_clm_manual_th_times; 3123 break; 3124 default: 3125 break; 3126 } 3127 3128 /* Set sampling threshold for 4 different regions, unit in idx_cnt. 3129 * low[i] = high[i-1] + 1 3130 * high[i] = high[i-1] * ifs_th_times 3131 */ 3132 ifs_th_l[IFS_CLM_TH_START_IDX] = 0; 3133 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; 3134 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, 3135 ifs_th0_us); 3136 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { 3137 ifs_th_l[i] = ifs_th_h[i - 1] + 1; 3138 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; 3139 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]); 3140 } 3141 3142 ifs_update_finished: 3143 if (!is_update) 3144 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3145 "No need to update IFS_TH\n"); 3146 3147 return is_update; 3148 } 3149 3150 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) 3151 { 3152 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3153 u8 i = 0; 3154 3155 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_LOW_MSK, 3156 env->ifs_clm_th_l[0]); 3157 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_LOW_MSK, 3158 env->ifs_clm_th_l[1]); 3159 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_LOW_MSK, 3160 env->ifs_clm_th_l[2]); 3161 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_LOW_MSK, 3162 env->ifs_clm_th_l[3]); 3163 3164 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_HIGH_MSK, 3165 env->ifs_clm_th_h[0]); 3166 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_HIGH_MSK, 3167 env->ifs_clm_th_h[1]); 3168 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_HIGH_MSK, 3169 env->ifs_clm_th_h[2]); 3170 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_HIGH_MSK, 3171 env->ifs_clm_th_h[3]); 3172 3173 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3174 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3175 "Update IFS_T%d_th{low, high} : {%d, %d}\n", 3176 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 3177 } 3178 3179 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) 3180 { 3181 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3182 struct rtw89_ccx_para_info para = {0}; 3183 3184 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3185 env->ifs_clm_mntr_time = 0; 3186 3187 para.ifs_clm_app = RTW89_IFS_CLM_INIT; 3188 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) 3189 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 3190 3191 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COLLECT_EN, 3192 true); 3193 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_EN_MSK, true); 3194 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_EN_MSK, true); 3195 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_EN_MSK, true); 3196 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_EN_MSK, true); 3197 } 3198 3199 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, 3200 enum rtw89_env_racing_lv level) 3201 { 3202 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3203 int ret = 0; 3204 3205 if (level >= RTW89_RAC_MAX_NUM) { 3206 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3207 "[WARNING] Wrong LV=%d\n", level); 3208 return -EINVAL; 3209 } 3210 3211 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3212 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, 3213 env->ccx_rac_lv, level); 3214 3215 if (env->ccx_ongoing) { 3216 if (level <= env->ccx_rac_lv) 3217 ret = -EINVAL; 3218 else 3219 env->ccx_ongoing = false; 3220 } 3221 3222 if (ret == 0) 3223 env->ccx_rac_lv = level; 3224 3225 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", 3226 !ret); 3227 3228 return ret; 3229 } 3230 3231 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) 3232 { 3233 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3234 3235 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 0); 3236 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 0); 3237 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1); 3238 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 3239 3240 env->ccx_rpt_stamp++; 3241 env->ccx_ongoing = true; 3242 } 3243 3244 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) 3245 { 3246 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3247 u8 i = 0; 3248 u32 res = 0; 3249 3250 env->ifs_clm_tx_ratio = 3251 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT); 3252 env->ifs_clm_edcca_excl_cca_ratio = 3253 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca, 3254 PERCENT); 3255 env->ifs_clm_cck_fa_ratio = 3256 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT); 3257 env->ifs_clm_ofdm_fa_ratio = 3258 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT); 3259 env->ifs_clm_cck_cca_excl_fa_ratio = 3260 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa, 3261 PERCENT); 3262 env->ifs_clm_ofdm_cca_excl_fa_ratio = 3263 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa, 3264 PERCENT); 3265 env->ifs_clm_cck_fa_permil = 3266 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL); 3267 env->ifs_clm_ofdm_fa_permil = 3268 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL); 3269 3270 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { 3271 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { 3272 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; 3273 } else { 3274 env->ifs_clm_ifs_avg[i] = 3275 rtw89_phy_ccx_idx_to_us(rtwdev, 3276 env->ifs_clm_avg[i]); 3277 } 3278 3279 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]); 3280 res += env->ifs_clm_his[i] >> 1; 3281 if (env->ifs_clm_his[i]) 3282 res /= env->ifs_clm_his[i]; 3283 else 3284 res = 0; 3285 env->ifs_clm_cca_avg[i] = res; 3286 } 3287 3288 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3289 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", 3290 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); 3291 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3292 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", 3293 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); 3294 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3295 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", 3296 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); 3297 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3298 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", 3299 env->ifs_clm_cck_cca_excl_fa_ratio, 3300 env->ifs_clm_ofdm_cca_excl_fa_ratio); 3301 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3302 "Time:[his, ifs_avg(us), cca_avg(us)]\n"); 3303 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3304 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 3305 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 3306 env->ifs_clm_cca_avg[i]); 3307 } 3308 3309 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) 3310 { 3311 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3312 u8 i = 0; 3313 3314 if (rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_DONE_MSK) == 0) { 3315 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3316 "Get IFS_CLM report Fail\n"); 3317 return false; 3318 } 3319 3320 env->ifs_clm_tx = 3321 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 3322 B_IFS_CLM_TX_CNT_MSK); 3323 env->ifs_clm_edcca_excl_cca = 3324 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 3325 B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK); 3326 env->ifs_clm_cckcca_excl_fa = 3327 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 3328 B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK); 3329 env->ifs_clm_ofdmcca_excl_fa = 3330 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 3331 B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK); 3332 env->ifs_clm_cckfa = 3333 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 3334 B_IFS_CLM_CCK_FA_MSK); 3335 env->ifs_clm_ofdmfa = 3336 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 3337 B_IFS_CLM_OFDM_FA_MSK); 3338 3339 env->ifs_clm_his[0] = 3340 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T1_HIS_MSK); 3341 env->ifs_clm_his[1] = 3342 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T2_HIS_MSK); 3343 env->ifs_clm_his[2] = 3344 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T3_HIS_MSK); 3345 env->ifs_clm_his[3] = 3346 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T4_HIS_MSK); 3347 3348 env->ifs_clm_avg[0] = 3349 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T1_AVG_MSK); 3350 env->ifs_clm_avg[1] = 3351 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T2_AVG_MSK); 3352 env->ifs_clm_avg[2] = 3353 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T3_AVG_MSK); 3354 env->ifs_clm_avg[3] = 3355 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T4_AVG_MSK); 3356 3357 env->ifs_clm_cca[0] = 3358 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T1_CCA_MSK); 3359 env->ifs_clm_cca[1] = 3360 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T2_CCA_MSK); 3361 env->ifs_clm_cca[2] = 3362 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T3_CCA_MSK); 3363 env->ifs_clm_cca[3] = 3364 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T4_CCA_MSK); 3365 3366 env->ifs_clm_total_ifs = 3367 rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_TOTAL_CNT_MSK); 3368 3369 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", 3370 env->ifs_clm_total_ifs); 3371 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3372 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", 3373 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); 3374 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3375 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", 3376 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); 3377 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3378 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", 3379 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); 3380 3381 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); 3382 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3383 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3384 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], 3385 env->ifs_clm_avg[i], env->ifs_clm_cca[i]); 3386 3387 rtw89_phy_ifs_clm_get_utility(rtwdev); 3388 3389 return true; 3390 } 3391 3392 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 3393 struct rtw89_ccx_para_info *para) 3394 { 3395 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3396 u32 period = 0; 3397 u32 unit_idx = 0; 3398 3399 if (para->mntr_time == 0) { 3400 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3401 "[WARN] MNTR_TIME is 0\n"); 3402 return -EINVAL; 3403 } 3404 3405 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv)) 3406 return -EINVAL; 3407 3408 if (para->mntr_time != env->ifs_clm_mntr_time) { 3409 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 3410 &period, &unit_idx); 3411 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 3412 B_IFS_CLM_PERIOD_MSK, period); 3413 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 3414 B_IFS_CLM_COUNTER_UNIT_MSK, unit_idx); 3415 3416 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3417 "Update IFS-CLM time ((%d)) -> ((%d))\n", 3418 env->ifs_clm_mntr_time, para->mntr_time); 3419 3420 env->ifs_clm_mntr_time = para->mntr_time; 3421 env->ccx_period = (u16)period; 3422 env->ccx_unit_idx = (u8)unit_idx; 3423 } 3424 3425 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) { 3426 env->ifs_clm_app = para->ifs_clm_app; 3427 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 3428 } 3429 3430 return 0; 3431 } 3432 3433 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) 3434 { 3435 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3436 struct rtw89_ccx_para_info para = {0}; 3437 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3438 3439 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3440 if (env->ccx_manual_ctrl) { 3441 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3442 "CCX in manual ctrl\n"); 3443 return; 3444 } 3445 3446 /* only ifs_clm for now */ 3447 if (rtw89_phy_ifs_clm_get_result(rtwdev)) 3448 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3449 3450 rtw89_phy_ccx_racing_release(rtwdev); 3451 para.mntr_time = 1900; 3452 para.rac_lv = RTW89_RAC_LV_1; 3453 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3454 3455 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0) 3456 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3457 if (chk_result) 3458 rtw89_phy_ccx_trigger(rtwdev); 3459 3460 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3461 "get_result=0x%x, chk_result:0x%x\n", 3462 env->ccx_watchdog_result, chk_result); 3463 } 3464 3465 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page) 3466 { 3467 if (*ie_page >= RTW89_PHYSTS_BITMAP_NUM || 3468 *ie_page == RTW89_RSVD_9) 3469 return false; 3470 else if (*ie_page > RTW89_RSVD_9) 3471 *ie_page -= 1; 3472 3473 return true; 3474 } 3475 3476 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) 3477 { 3478 static const u8 ie_page_shift = 2; 3479 3480 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); 3481 } 3482 3483 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, 3484 enum rtw89_phy_status_bitmap ie_page) 3485 { 3486 u32 addr; 3487 3488 if (!rtw89_physts_ie_page_valid(&ie_page)) 3489 return 0; 3490 3491 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3492 3493 return rtw89_phy_read32(rtwdev, addr); 3494 } 3495 3496 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, 3497 enum rtw89_phy_status_bitmap ie_page, 3498 u32 val) 3499 { 3500 const struct rtw89_chip_info *chip = rtwdev->chip; 3501 u32 addr; 3502 3503 if (!rtw89_physts_ie_page_valid(&ie_page)) 3504 return; 3505 3506 if (chip->chip_id == RTL8852A) 3507 val &= B_PHY_STS_BITMAP_MSK_52A; 3508 3509 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3510 rtw89_phy_write32(rtwdev, addr, val); 3511 } 3512 3513 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev, 3514 enum rtw89_phy_status_bitmap bitmap, 3515 enum rtw89_phy_status_ie_type ie, 3516 bool enable) 3517 { 3518 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap); 3519 3520 if (enable) 3521 val |= BIT(ie); 3522 else 3523 val &= ~BIT(ie); 3524 3525 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val); 3526 } 3527 3528 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, 3529 bool enable, 3530 enum rtw89_phy_idx phy_idx) 3531 { 3532 if (enable) { 3533 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3534 B_STS_DIS_TRIG_BY_FAIL); 3535 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3536 B_STS_DIS_TRIG_BY_BRK); 3537 } else { 3538 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3539 B_STS_DIS_TRIG_BY_FAIL); 3540 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3541 B_STS_DIS_TRIG_BY_BRK); 3542 } 3543 } 3544 3545 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev) 3546 { 3547 u8 i; 3548 3549 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0); 3550 3551 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { 3552 if (i >= RTW89_CCK_PKT) 3553 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3554 RTW89_PHYSTS_IE09_FTR_0, 3555 true); 3556 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) || 3557 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT)) 3558 continue; 3559 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3560 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A, 3561 true); 3562 } 3563 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT, 3564 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3565 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT, 3566 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3567 3568 /* force IE01 for channel index, only channel field is valid */ 3569 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT, 3570 RTW89_PHYSTS_IE01_CMN_OFDM, true); 3571 } 3572 3573 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) 3574 { 3575 const struct rtw89_chip_info *chip = rtwdev->chip; 3576 struct rtw89_dig_info *dig = &rtwdev->dig; 3577 const struct rtw89_phy_dig_gain_cfg *cfg; 3578 const char *msg; 3579 u8 i; 3580 s8 gain_base; 3581 s8 *gain_arr; 3582 u32 tmp; 3583 3584 switch (type) { 3585 case RTW89_DIG_GAIN_LNA_G: 3586 gain_arr = dig->lna_gain_g; 3587 gain_base = LNA0_GAIN; 3588 cfg = chip->dig_table->cfg_lna_g; 3589 msg = "lna_gain_g"; 3590 break; 3591 case RTW89_DIG_GAIN_TIA_G: 3592 gain_arr = dig->tia_gain_g; 3593 gain_base = TIA0_GAIN_G; 3594 cfg = chip->dig_table->cfg_tia_g; 3595 msg = "tia_gain_g"; 3596 break; 3597 case RTW89_DIG_GAIN_LNA_A: 3598 gain_arr = dig->lna_gain_a; 3599 gain_base = LNA0_GAIN; 3600 cfg = chip->dig_table->cfg_lna_a; 3601 msg = "lna_gain_a"; 3602 break; 3603 case RTW89_DIG_GAIN_TIA_A: 3604 gain_arr = dig->tia_gain_a; 3605 gain_base = TIA0_GAIN_A; 3606 cfg = chip->dig_table->cfg_tia_a; 3607 msg = "tia_gain_a"; 3608 break; 3609 default: 3610 return; 3611 } 3612 3613 for (i = 0; i < cfg->size; i++) { 3614 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr, 3615 cfg->table[i].mask); 3616 tmp >>= DIG_GAIN_SHIFT; 3617 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; 3618 gain_base += DIG_GAIN; 3619 3620 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", 3621 msg, i, gain_arr[i]); 3622 } 3623 } 3624 3625 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev) 3626 { 3627 struct rtw89_dig_info *dig = &rtwdev->dig; 3628 u32 tmp; 3629 u8 i; 3630 3631 if (!rtwdev->hal.support_igi) 3632 return; 3633 3634 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW, 3635 B_PATH0_IB_PKPW_MSK); 3636 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); 3637 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK, 3638 B_PATH0_IB_PBK_MSK); 3639 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", 3640 dig->ib_pkpwr, dig->ib_pbk); 3641 3642 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) 3643 rtw89_phy_dig_read_gain_table(rtwdev, i); 3644 } 3645 3646 static const u8 rssi_nolink = 22; 3647 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; 3648 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; 3649 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; 3650 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; 3651 3652 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev) 3653 { 3654 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 3655 struct rtw89_dig_info *dig = &rtwdev->dig; 3656 bool is_linked = rtwdev->total_sta_assoc > 0; 3657 3658 if (is_linked) { 3659 dig->igi_rssi = ch_info->rssi_min >> 1; 3660 } else { 3661 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); 3662 dig->igi_rssi = rssi_nolink; 3663 } 3664 } 3665 3666 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev) 3667 { 3668 struct rtw89_dig_info *dig = &rtwdev->dig; 3669 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3670 bool is_linked = rtwdev->total_sta_assoc > 0; 3671 const u16 *fa_th_src = NULL; 3672 3673 switch (chan->band_type) { 3674 case RTW89_BAND_2G: 3675 dig->lna_gain = dig->lna_gain_g; 3676 dig->tia_gain = dig->tia_gain_g; 3677 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; 3678 dig->force_gaincode_idx_en = false; 3679 dig->dyn_pd_th_en = true; 3680 break; 3681 case RTW89_BAND_5G: 3682 default: 3683 dig->lna_gain = dig->lna_gain_a; 3684 dig->tia_gain = dig->tia_gain_a; 3685 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; 3686 dig->force_gaincode_idx_en = true; 3687 dig->dyn_pd_th_en = true; 3688 break; 3689 } 3690 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); 3691 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); 3692 } 3693 3694 static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20; 3695 static const u8 igi_max_performance_mode = 0x5a; 3696 static const u8 dynamic_pd_threshold_max; 3697 3698 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev) 3699 { 3700 struct rtw89_dig_info *dig = &rtwdev->dig; 3701 3702 dig->cur_gaincode.lna_idx = LNA_IDX_MAX; 3703 dig->cur_gaincode.tia_idx = TIA_IDX_MAX; 3704 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; 3705 dig->force_gaincode.lna_idx = LNA_IDX_MAX; 3706 dig->force_gaincode.tia_idx = TIA_IDX_MAX; 3707 dig->force_gaincode.rxb_idx = RXB_IDX_MAX; 3708 3709 dig->dyn_igi_max = igi_max_performance_mode; 3710 dig->dyn_igi_min = dynamic_igi_min; 3711 dig->dyn_pd_th_max = dynamic_pd_threshold_max; 3712 dig->pd_low_th_ofst = pd_low_th_offset; 3713 dig->is_linked_pre = false; 3714 } 3715 3716 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) 3717 { 3718 rtw89_phy_dig_update_gain_para(rtwdev); 3719 rtw89_phy_dig_reset(rtwdev); 3720 } 3721 3722 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3723 { 3724 struct rtw89_dig_info *dig = &rtwdev->dig; 3725 u8 lna_idx; 3726 3727 if (rssi < dig->igi_rssi_th[0]) 3728 lna_idx = RTW89_DIG_GAIN_LNA_IDX6; 3729 else if (rssi < dig->igi_rssi_th[1]) 3730 lna_idx = RTW89_DIG_GAIN_LNA_IDX5; 3731 else if (rssi < dig->igi_rssi_th[2]) 3732 lna_idx = RTW89_DIG_GAIN_LNA_IDX4; 3733 else if (rssi < dig->igi_rssi_th[3]) 3734 lna_idx = RTW89_DIG_GAIN_LNA_IDX3; 3735 else if (rssi < dig->igi_rssi_th[4]) 3736 lna_idx = RTW89_DIG_GAIN_LNA_IDX2; 3737 else 3738 lna_idx = RTW89_DIG_GAIN_LNA_IDX1; 3739 3740 return lna_idx; 3741 } 3742 3743 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3744 { 3745 struct rtw89_dig_info *dig = &rtwdev->dig; 3746 u8 tia_idx; 3747 3748 if (rssi < dig->igi_rssi_th[0]) 3749 tia_idx = RTW89_DIG_GAIN_TIA_IDX1; 3750 else 3751 tia_idx = RTW89_DIG_GAIN_TIA_IDX0; 3752 3753 return tia_idx; 3754 } 3755 3756 #define IB_PBK_BASE 110 3757 #define WB_RSSI_BASE 10 3758 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3759 struct rtw89_agc_gaincode_set *set) 3760 { 3761 struct rtw89_dig_info *dig = &rtwdev->dig; 3762 s8 lna_gain = dig->lna_gain[set->lna_idx]; 3763 s8 tia_gain = dig->tia_gain[set->tia_idx]; 3764 s32 wb_rssi = rssi + lna_gain + tia_gain; 3765 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; 3766 u8 rxb_idx; 3767 3768 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; 3769 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); 3770 3771 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", 3772 wb_rssi, rxb_idx_tmp); 3773 3774 return rxb_idx; 3775 } 3776 3777 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3778 struct rtw89_agc_gaincode_set *set) 3779 { 3780 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi); 3781 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi); 3782 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set); 3783 3784 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3785 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", 3786 rssi, set->lna_idx, set->tia_idx, set->rxb_idx); 3787 } 3788 3789 #define IGI_OFFSET_MAX 25 3790 #define IGI_OFFSET_MUL 2 3791 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev) 3792 { 3793 struct rtw89_dig_info *dig = &rtwdev->dig; 3794 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3795 enum rtw89_dig_noisy_level noisy_lv; 3796 u8 igi_offset = dig->fa_rssi_ofst; 3797 u16 fa_ratio = 0; 3798 3799 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; 3800 3801 if (fa_ratio < dig->fa_th[0]) 3802 noisy_lv = RTW89_DIG_NOISY_LEVEL0; 3803 else if (fa_ratio < dig->fa_th[1]) 3804 noisy_lv = RTW89_DIG_NOISY_LEVEL1; 3805 else if (fa_ratio < dig->fa_th[2]) 3806 noisy_lv = RTW89_DIG_NOISY_LEVEL2; 3807 else if (fa_ratio < dig->fa_th[3]) 3808 noisy_lv = RTW89_DIG_NOISY_LEVEL3; 3809 else 3810 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; 3811 3812 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) 3813 igi_offset = 0; 3814 else 3815 igi_offset += noisy_lv * IGI_OFFSET_MUL; 3816 3817 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); 3818 dig->fa_rssi_ofst = igi_offset; 3819 3820 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3821 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", 3822 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); 3823 3824 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3825 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", 3826 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, 3827 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, 3828 noisy_lv, igi_offset); 3829 } 3830 3831 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx) 3832 { 3833 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3834 3835 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_lna_init.addr, 3836 dig_regs->p0_lna_init.mask, lna_idx); 3837 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_lna_init.addr, 3838 dig_regs->p1_lna_init.mask, lna_idx); 3839 } 3840 3841 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx) 3842 { 3843 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3844 3845 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_tia_init.addr, 3846 dig_regs->p0_tia_init.mask, tia_idx); 3847 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_tia_init.addr, 3848 dig_regs->p1_tia_init.mask, tia_idx); 3849 } 3850 3851 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx) 3852 { 3853 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3854 3855 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_rxb_init.addr, 3856 dig_regs->p0_rxb_init.mask, rxb_idx); 3857 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_rxb_init.addr, 3858 dig_regs->p1_rxb_init.mask, rxb_idx); 3859 } 3860 3861 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, 3862 const struct rtw89_agc_gaincode_set set) 3863 { 3864 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx); 3865 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx); 3866 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx); 3867 3868 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", 3869 set.lna_idx, set.tia_idx, set.rxb_idx); 3870 } 3871 3872 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, 3873 bool enable) 3874 { 3875 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3876 3877 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_p20_pagcugc_en.addr, 3878 dig_regs->p0_p20_pagcugc_en.mask, enable); 3879 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_s20_pagcugc_en.addr, 3880 dig_regs->p0_s20_pagcugc_en.mask, enable); 3881 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_p20_pagcugc_en.addr, 3882 dig_regs->p1_p20_pagcugc_en.mask, enable); 3883 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_s20_pagcugc_en.addr, 3884 dig_regs->p1_s20_pagcugc_en.mask, enable); 3885 3886 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); 3887 } 3888 3889 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev) 3890 { 3891 struct rtw89_dig_info *dig = &rtwdev->dig; 3892 3893 if (!rtwdev->hal.support_igi) 3894 return; 3895 3896 if (dig->force_gaincode_idx_en) { 3897 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 3898 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3899 "Force gaincode index enabled.\n"); 3900 } else { 3901 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi, 3902 &dig->cur_gaincode); 3903 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode); 3904 } 3905 } 3906 3907 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, 3908 bool enable) 3909 { 3910 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3911 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3912 enum rtw89_bandwidth cbw = chan->band_width; 3913 struct rtw89_dig_info *dig = &rtwdev->dig; 3914 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; 3915 u8 ofdm_cca_th; 3916 s8 cck_cca_th; 3917 u32 pd_val = 0; 3918 3919 under_region += PD_TH_SB_FLTR_CMP_VAL; 3920 3921 switch (cbw) { 3922 case RTW89_CHANNEL_WIDTH_40: 3923 under_region += PD_TH_BW40_CMP_VAL; 3924 break; 3925 case RTW89_CHANNEL_WIDTH_80: 3926 under_region += PD_TH_BW80_CMP_VAL; 3927 break; 3928 case RTW89_CHANNEL_WIDTH_160: 3929 under_region += PD_TH_BW160_CMP_VAL; 3930 break; 3931 case RTW89_CHANNEL_WIDTH_20: 3932 fallthrough; 3933 default: 3934 under_region += PD_TH_BW20_CMP_VAL; 3935 break; 3936 } 3937 3938 dig->dyn_pd_th_max = dig->igi_rssi; 3939 3940 final_rssi = min_t(u8, rssi, dig->igi_rssi); 3941 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, 3942 PD_TH_MAX_RSSI + under_region); 3943 3944 if (enable) { 3945 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1; 3946 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3947 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n", 3948 final_rssi, ofdm_cca_th, under_region, pd_val); 3949 } else { 3950 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3951 "Dynamic PD th disabled, Set PD_low_bd=0\n"); 3952 } 3953 3954 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 3955 dig_regs->pd_lower_bound_mask, pd_val); 3956 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 3957 dig_regs->pd_spatial_reuse_en, enable); 3958 3959 if (!rtwdev->hal.support_cckpd) 3960 return; 3961 3962 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI); 3963 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX); 3964 3965 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3966 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n", 3967 final_rssi, cck_cca_th, under_region, pd_val); 3968 3969 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_EN_V1, 3970 B_BMODE_PDTH_LIMIT_EN_MSK_V1, enable); 3971 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_V1, 3972 B_BMODE_PDTH_LOWER_BOUND_MSK_V1, pd_val); 3973 } 3974 3975 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) 3976 { 3977 struct rtw89_dig_info *dig = &rtwdev->dig; 3978 3979 dig->bypass_dig = false; 3980 rtw89_phy_dig_para_reset(rtwdev); 3981 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 3982 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false); 3983 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 3984 rtw89_phy_dig_update_para(rtwdev); 3985 } 3986 3987 #define IGI_RSSI_MIN 10 3988 void rtw89_phy_dig(struct rtw89_dev *rtwdev) 3989 { 3990 struct rtw89_dig_info *dig = &rtwdev->dig; 3991 bool is_linked = rtwdev->total_sta_assoc > 0; 3992 3993 if (unlikely(dig->bypass_dig)) { 3994 dig->bypass_dig = false; 3995 return; 3996 } 3997 3998 if (!dig->is_linked_pre && is_linked) { 3999 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); 4000 rtw89_phy_dig_update_para(rtwdev); 4001 } else if (dig->is_linked_pre && !is_linked) { 4002 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); 4003 rtw89_phy_dig_update_para(rtwdev); 4004 } 4005 dig->is_linked_pre = is_linked; 4006 4007 rtw89_phy_dig_igi_offset_by_env(rtwdev); 4008 rtw89_phy_dig_update_rssi_info(rtwdev); 4009 4010 dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ? 4011 dig->igi_rssi - IGI_RSSI_MIN : 0; 4012 dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX; 4013 dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst; 4014 4015 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, 4016 dig->dyn_igi_max); 4017 4018 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4019 "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n", 4020 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, 4021 dig->igi_fa_rssi); 4022 4023 rtw89_phy_dig_config_igi(rtwdev); 4024 4025 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en); 4026 4027 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) 4028 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true); 4029 else 4030 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 4031 } 4032 4033 static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta) 4034 { 4035 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 4036 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 4037 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 4038 struct rtw89_hal *hal = &rtwdev->hal; 4039 bool *done = data; 4040 u8 rssi_a, rssi_b; 4041 u32 candidate; 4042 4043 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || sta->tdls) 4044 return; 4045 4046 if (*done) 4047 return; 4048 4049 *done = true; 4050 4051 rssi_a = ewma_rssi_read(&rtwsta->rssi[RF_PATH_A]); 4052 rssi_b = ewma_rssi_read(&rtwsta->rssi[RF_PATH_B]); 4053 4054 if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH) 4055 candidate = RF_A; 4056 else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH) 4057 candidate = RF_B; 4058 else 4059 return; 4060 4061 if (hal->antenna_tx == candidate) 4062 return; 4063 4064 hal->antenna_tx = candidate; 4065 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta); 4066 4067 if (hal->antenna_tx == RF_A) { 4068 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12); 4069 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11); 4070 } else if (hal->antenna_tx == RF_B) { 4071 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11); 4072 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12); 4073 } 4074 } 4075 4076 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev) 4077 { 4078 struct rtw89_hal *hal = &rtwdev->hal; 4079 bool done = false; 4080 4081 if (!hal->tx_path_diversity) 4082 return; 4083 4084 ieee80211_iterate_stations_atomic(rtwdev->hw, 4085 rtw89_phy_tx_path_div_sta_iter, 4086 &done); 4087 } 4088 4089 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) 4090 { 4091 rtw89_phy_ccx_top_setting_init(rtwdev); 4092 rtw89_phy_ifs_clm_setting_init(rtwdev); 4093 } 4094 4095 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 4096 { 4097 const struct rtw89_chip_info *chip = rtwdev->chip; 4098 4099 rtw89_phy_stat_init(rtwdev); 4100 4101 rtw89_chip_bb_sethw(rtwdev); 4102 4103 rtw89_phy_env_monitor_init(rtwdev); 4104 rtw89_physts_parsing_init(rtwdev); 4105 rtw89_phy_dig_init(rtwdev); 4106 rtw89_phy_cfo_init(rtwdev); 4107 rtw89_phy_ul_tb_info_init(rtwdev); 4108 4109 rtw89_phy_init_rf_nctl(rtwdev); 4110 rtw89_chip_rfk_init(rtwdev); 4111 rtw89_load_txpwr_table(rtwdev, chip->byr_table); 4112 rtw89_chip_set_txpwr_ctrl(rtwdev); 4113 rtw89_chip_power_trim(rtwdev); 4114 rtw89_chip_cfg_txrx_path(rtwdev); 4115 } 4116 4117 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 4118 { 4119 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 4120 u8 bss_color; 4121 4122 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 4123 return; 4124 4125 bss_color = vif->bss_conf.he_bss_color.color; 4126 4127 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0, 0x1, 4128 phy_idx); 4129 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_TGT, bss_color, 4130 phy_idx); 4131 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_STAID, 4132 vif->cfg.aid, phy_idx); 4133 } 4134 4135 static void 4136 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4137 { 4138 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); 4139 } 4140 4141 static void 4142 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4143 { 4144 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 4145 } 4146 4147 static void 4148 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4149 { 4150 rtw89_phy_write32_set(rtwdev, def->addr, def->mask); 4151 } 4152 4153 static void 4154 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4155 { 4156 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); 4157 } 4158 4159 static void 4160 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4161 { 4162 udelay(def->data); 4163 } 4164 4165 static void 4166 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { 4167 [RTW89_RFK_F_WRF] = _rfk_write_rf, 4168 [RTW89_RFK_F_WM] = _rfk_write32_mask, 4169 [RTW89_RFK_F_WS] = _rfk_write32_set, 4170 [RTW89_RFK_F_WC] = _rfk_write32_clr, 4171 [RTW89_RFK_F_DELAY] = _rfk_delay, 4172 }; 4173 4174 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 4175 4176 void 4177 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) 4178 { 4179 const struct rtw89_reg5_def *p = tbl->defs; 4180 const struct rtw89_reg5_def *end = tbl->defs + tbl->size; 4181 4182 for (; p < end; p++) 4183 _rfk_handler[p->flag](rtwdev, p); 4184 } 4185 EXPORT_SYMBOL(rtw89_rfk_parser); 4186 4187 #define RTW89_TSSI_FAST_MODE_NUM 4 4188 4189 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = { 4190 {0xD934, 0xff0000}, 4191 {0xD934, 0xff000000}, 4192 {0xD938, 0xff}, 4193 {0xD934, 0xff00}, 4194 }; 4195 4196 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = { 4197 {0xD930, 0xff0000}, 4198 {0xD930, 0xff000000}, 4199 {0xD934, 0xff}, 4200 {0xD930, 0xff00}, 4201 }; 4202 4203 static 4204 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev, 4205 enum rtw89_mac_idx mac_idx, 4206 enum rtw89_tssi_bandedge_cfg bandedge_cfg, 4207 u32 val) 4208 { 4209 const struct rtw89_reg_def *regs; 4210 u32 reg; 4211 int i; 4212 4213 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 4214 regs = rtw89_tssi_fastmode_regs_flat; 4215 else 4216 regs = rtw89_tssi_fastmode_regs_level; 4217 4218 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) { 4219 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 4220 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); 4221 } 4222 } 4223 4224 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = { 4225 {0xD91C, 0xff000000}, 4226 {0xD920, 0xff}, 4227 {0xD920, 0xff00}, 4228 {0xD920, 0xff0000}, 4229 {0xD920, 0xff000000}, 4230 {0xD924, 0xff}, 4231 {0xD924, 0xff00}, 4232 {0xD914, 0xff000000}, 4233 {0xD918, 0xff}, 4234 {0xD918, 0xff00}, 4235 {0xD918, 0xff0000}, 4236 {0xD918, 0xff000000}, 4237 {0xD91C, 0xff}, 4238 {0xD91C, 0xff00}, 4239 {0xD91C, 0xff0000}, 4240 }; 4241 4242 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = { 4243 {0xD910, 0xff}, 4244 {0xD910, 0xff00}, 4245 {0xD910, 0xff0000}, 4246 {0xD910, 0xff000000}, 4247 {0xD914, 0xff}, 4248 {0xD914, 0xff00}, 4249 {0xD914, 0xff0000}, 4250 {0xD908, 0xff}, 4251 {0xD908, 0xff00}, 4252 {0xD908, 0xff0000}, 4253 {0xD908, 0xff000000}, 4254 {0xD90C, 0xff}, 4255 {0xD90C, 0xff00}, 4256 {0xD90C, 0xff0000}, 4257 {0xD90C, 0xff000000}, 4258 }; 4259 4260 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 4261 enum rtw89_mac_idx mac_idx, 4262 enum rtw89_tssi_bandedge_cfg bandedge_cfg) 4263 { 4264 const struct rtw89_chip_info *chip = rtwdev->chip; 4265 const struct rtw89_reg_def *regs; 4266 const u32 *data; 4267 u32 reg; 4268 int i; 4269 4270 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM) 4271 return; 4272 4273 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 4274 regs = rtw89_tssi_bandedge_regs_flat; 4275 else 4276 regs = rtw89_tssi_bandedge_regs_level; 4277 4278 data = chip->tssi_dbw_table->data[bandedge_cfg]; 4279 4280 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) { 4281 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 4282 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); 4283 } 4284 4285 reg = rtw89_mac_reg_by_idx(R_AX_BANDEDGE_CFG, mac_idx); 4286 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); 4287 4288 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg, 4289 data[RTW89_TSSI_SBW20]); 4290 } 4291 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg); 4292