1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "debug.h" 7 #include "fw.h" 8 #include "mac.h" 9 #include "phy.h" 10 #include "ps.h" 11 #include "reg.h" 12 #include "sar.h" 13 #include "txrx.h" 14 #include "util.h" 15 16 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, 17 const struct rtw89_ra_report *report) 18 { 19 u32 bit_rate = report->bit_rate; 20 21 /* lower than ofdm, do not aggregate */ 22 if (bit_rate < 550) 23 return 1; 24 25 /* avoid AMSDU for legacy rate */ 26 if (report->might_fallback_legacy) 27 return 1; 28 29 /* lower than 20M vht 2ss mcs8, make it small */ 30 if (bit_rate < 1800) 31 return 1200; 32 33 /* lower than 40M vht 2ss mcs9, make it medium */ 34 if (bit_rate < 4000) 35 return 2600; 36 37 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ 38 if (bit_rate < 7000) 39 return 3500; 40 41 return rtwdev->chip->max_amsdu_limit; 42 } 43 44 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) 45 { 46 u64 ra_mask = 0; 47 u8 mcs_cap; 48 int i, nss; 49 50 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { 51 mcs_cap = mcs_map & 0x3; 52 switch (mcs_cap) { 53 case 2: 54 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; 55 break; 56 case 1: 57 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; 58 break; 59 case 0: 60 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; 61 break; 62 default: 63 break; 64 } 65 } 66 67 return ra_mask; 68 } 69 70 static u64 get_he_ra_mask(struct ieee80211_sta *sta) 71 { 72 struct ieee80211_sta_he_cap cap = sta->deflink.he_cap; 73 u16 mcs_map; 74 75 switch (sta->deflink.bandwidth) { 76 case IEEE80211_STA_RX_BW_160: 77 if (cap.he_cap_elem.phy_cap_info[0] & 78 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) 79 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); 80 else 81 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); 82 break; 83 default: 84 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); 85 } 86 87 /* MCS11, MCS9, MCS7 */ 88 return get_mcs_ra_mask(mcs_map, 11, 2); 89 } 90 91 #define RA_FLOOR_TABLE_SIZE 7 92 #define RA_FLOOR_UP_GAP 3 93 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, 94 u8 ratr_state) 95 { 96 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; 97 u8 rssi_lv = 0; 98 u8 i; 99 100 rssi >>= 1; 101 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 102 if (i >= ratr_state) 103 rssi_lv_t[i] += RA_FLOOR_UP_GAP; 104 if (rssi < rssi_lv_t[i]) { 105 rssi_lv = i; 106 break; 107 } 108 } 109 if (rssi_lv == 0) 110 return 0xffffffffffffffffULL; 111 else if (rssi_lv == 1) 112 return 0xfffffffffffffff0ULL; 113 else if (rssi_lv == 2) 114 return 0xffffffffffffefe0ULL; 115 else if (rssi_lv == 3) 116 return 0xffffffffffffcfc0ULL; 117 else if (rssi_lv == 4) 118 return 0xffffffffffff8f80ULL; 119 else if (rssi_lv >= 5) 120 return 0xffffffffffff0f00ULL; 121 122 return 0xffffffffffffffffULL; 123 } 124 125 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak) 126 { 127 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 128 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 129 130 if (ra_mask == 0) 131 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 132 133 return ra_mask; 134 } 135 136 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 137 { 138 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 139 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 140 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 141 enum nl80211_band band; 142 u64 cfg_mask; 143 144 if (!rtwsta->use_cfg_mask) 145 return -1; 146 147 switch (chan->band_type) { 148 case RTW89_BAND_2G: 149 band = NL80211_BAND_2GHZ; 150 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, 151 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); 152 break; 153 case RTW89_BAND_5G: 154 band = NL80211_BAND_5GHZ; 155 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, 156 RA_MASK_OFDM_RATES); 157 break; 158 case RTW89_BAND_6G: 159 band = NL80211_BAND_6GHZ; 160 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy, 161 RA_MASK_OFDM_RATES); 162 break; 163 default: 164 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type); 165 return -1; 166 } 167 168 if (sta->deflink.he_cap.has_he) { 169 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], 170 RA_MASK_HE_1SS_RATES); 171 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], 172 RA_MASK_HE_2SS_RATES); 173 } else if (sta->deflink.vht_cap.vht_supported) { 174 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 175 RA_MASK_VHT_1SS_RATES); 176 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 177 RA_MASK_VHT_2SS_RATES); 178 } else if (sta->deflink.ht_cap.ht_supported) { 179 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 180 RA_MASK_HT_1SS_RATES); 181 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 182 RA_MASK_HT_2SS_RATES); 183 } 184 185 return cfg_mask; 186 } 187 188 static const u64 189 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, 190 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; 191 static const u64 192 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 193 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; 194 static const u64 195 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, 196 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; 197 198 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev, 199 struct rtw89_sta *rtwsta, 200 bool *fix_giltf_en, u8 *fix_giltf) 201 { 202 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 203 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 204 u8 band = chan->band_type; 205 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 206 u8 he_gi = mask->control[nl_band].he_gi; 207 u8 he_ltf = mask->control[nl_band].he_ltf; 208 209 if (!rtwsta->use_cfg_mask) 210 return; 211 212 if (he_ltf == 2 && he_gi == 2) { 213 *fix_giltf = RTW89_GILTF_LGI_4XHE32; 214 } else if (he_ltf == 2 && he_gi == 0) { 215 *fix_giltf = RTW89_GILTF_SGI_4XHE08; 216 } else if (he_ltf == 1 && he_gi == 1) { 217 *fix_giltf = RTW89_GILTF_2XHE16; 218 } else if (he_ltf == 1 && he_gi == 0) { 219 *fix_giltf = RTW89_GILTF_2XHE08; 220 } else if (he_ltf == 0 && he_gi == 1) { 221 *fix_giltf = RTW89_GILTF_1XHE16; 222 } else if (he_ltf == 0 && he_gi == 0) { 223 *fix_giltf = RTW89_GILTF_1XHE08; 224 } else { 225 *fix_giltf_en = false; 226 return; 227 } 228 229 *fix_giltf_en = true; 230 } 231 232 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 233 struct ieee80211_sta *sta, bool csi) 234 { 235 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 236 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 237 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 238 struct rtw89_ra_info *ra = &rtwsta->ra; 239 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 240 struct ieee80211_vif *vif = rtwvif_to_vif(rtwsta->rtwvif); 241 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; 242 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 243 u64 ra_mask = 0; 244 u64 ra_mask_bak; 245 u8 mode = 0; 246 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; 247 u8 bw_mode = 0; 248 u8 stbc_en = 0; 249 u8 ldpc_en = 0; 250 u8 fix_giltf = 0; 251 u8 i; 252 bool sgi = false; 253 bool fix_giltf_en = false; 254 255 memset(ra, 0, sizeof(*ra)); 256 /* Set the ra mask from sta's capability */ 257 if (sta->deflink.he_cap.has_he) { 258 mode |= RTW89_RA_MODE_HE; 259 csi_mode = RTW89_RA_RPT_MODE_HE; 260 ra_mask |= get_he_ra_mask(sta); 261 high_rate_masks = rtw89_ra_mask_he_rates; 262 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[2] & 263 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) 264 stbc_en = 1; 265 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[1] & 266 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) 267 ldpc_en = 1; 268 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta, &fix_giltf_en, &fix_giltf); 269 } else if (sta->deflink.vht_cap.vht_supported) { 270 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 271 272 mode |= RTW89_RA_MODE_VHT; 273 csi_mode = RTW89_RA_RPT_MODE_VHT; 274 /* MCS9, MCS8, MCS7 */ 275 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); 276 high_rate_masks = rtw89_ra_mask_vht_rates; 277 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 278 stbc_en = 1; 279 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 280 ldpc_en = 1; 281 } else if (sta->deflink.ht_cap.ht_supported) { 282 mode |= RTW89_RA_MODE_HT; 283 csi_mode = RTW89_RA_RPT_MODE_HT; 284 ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 48) | 285 ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 36) | 286 (sta->deflink.ht_cap.mcs.rx_mask[1] << 24) | 287 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 288 high_rate_masks = rtw89_ra_mask_ht_rates; 289 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 290 stbc_en = 1; 291 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 292 ldpc_en = 1; 293 } 294 295 switch (chan->band_type) { 296 case RTW89_BAND_2G: 297 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 298 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xf) 299 mode |= RTW89_RA_MODE_CCK; 300 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xff0) 301 mode |= RTW89_RA_MODE_OFDM; 302 break; 303 case RTW89_BAND_5G: 304 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 305 mode |= RTW89_RA_MODE_OFDM; 306 break; 307 case RTW89_BAND_6G: 308 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_6GHZ] << 4; 309 mode |= RTW89_RA_MODE_OFDM; 310 break; 311 default: 312 rtw89_err(rtwdev, "Unknown band type\n"); 313 break; 314 } 315 316 ra_mask_bak = ra_mask; 317 318 if (mode >= RTW89_RA_MODE_HT) { 319 u64 mask = 0; 320 for (i = 0; i < rtwdev->hal.tx_nss; i++) 321 mask |= high_rate_masks[i]; 322 if (mode & RTW89_RA_MODE_OFDM) 323 mask |= RA_MASK_SUBOFDM_RATES; 324 if (mode & RTW89_RA_MODE_CCK) 325 mask |= RA_MASK_SUBCCK_RATES; 326 ra_mask &= mask; 327 } else if (mode & RTW89_RA_MODE_OFDM) { 328 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES); 329 } 330 331 if (mode != RTW89_RA_MODE_CCK) 332 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); 333 334 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak); 335 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 336 337 switch (sta->deflink.bandwidth) { 338 case IEEE80211_STA_RX_BW_160: 339 bw_mode = RTW89_CHANNEL_WIDTH_160; 340 sgi = sta->deflink.vht_cap.vht_supported && 341 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160); 342 break; 343 case IEEE80211_STA_RX_BW_80: 344 bw_mode = RTW89_CHANNEL_WIDTH_80; 345 sgi = sta->deflink.vht_cap.vht_supported && 346 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 347 break; 348 case IEEE80211_STA_RX_BW_40: 349 bw_mode = RTW89_CHANNEL_WIDTH_40; 350 sgi = sta->deflink.ht_cap.ht_supported && 351 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 352 break; 353 default: 354 bw_mode = RTW89_CHANNEL_WIDTH_20; 355 sgi = sta->deflink.ht_cap.ht_supported && 356 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 357 break; 358 } 359 360 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 361 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) 362 ra->dcm_cap = 1; 363 364 if (rate_pattern->enable && !vif->p2p) { 365 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 366 ra_mask &= rate_pattern->ra_mask; 367 mode = rate_pattern->ra_mode; 368 } 369 370 ra->bw_cap = bw_mode; 371 ra->er_cap = rtwsta->er_cap; 372 ra->mode_ctrl = mode; 373 ra->macid = rtwsta->mac_id; 374 ra->stbc_cap = stbc_en; 375 ra->ldpc_cap = ldpc_en; 376 ra->ss_num = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1; 377 ra->en_sgi = sgi; 378 ra->ra_mask = ra_mask; 379 ra->fix_giltf_en = fix_giltf_en; 380 ra->fix_giltf = fix_giltf; 381 382 if (!csi) 383 return; 384 385 ra->fixed_csi_rate_en = false; 386 ra->ra_csi_rate_en = true; 387 ra->cr_tbl_sel = false; 388 ra->band_num = rtwvif->phy_idx; 389 ra->csi_bw = bw_mode; 390 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; 391 ra->csi_mcs_ss_idx = 5; 392 ra->csi_mode = csi_mode; 393 } 394 395 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 396 u32 changed) 397 { 398 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 399 struct rtw89_ra_info *ra = &rtwsta->ra; 400 401 rtw89_phy_ra_sta_update(rtwdev, sta, false); 402 403 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) 404 ra->upd_mask = 1; 405 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED)) 406 ra->upd_bw_nss_mask = 1; 407 408 rtw89_debug(rtwdev, RTW89_DBG_RA, 409 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", 410 ra->macid, 411 ra->bw_cap, 412 ra->ss_num, 413 ra->en_sgi, 414 ra->giltf); 415 416 rtw89_fw_h2c_ra(rtwdev, ra, false); 417 } 418 419 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, 420 u16 rate_base, u64 ra_mask, u8 ra_mode, 421 u32 rate_ctrl, u32 ctrl_skip, bool force) 422 { 423 u8 n, c; 424 425 if (rate_ctrl == ctrl_skip) 426 return true; 427 428 n = hweight32(rate_ctrl); 429 if (n == 0) 430 return true; 431 432 if (force && n != 1) 433 return false; 434 435 if (next->enable) 436 return false; 437 438 c = __fls(rate_ctrl); 439 next->rate = rate_base + c; 440 next->ra_mode = ra_mode; 441 next->ra_mask = ra_mask; 442 next->enable = true; 443 444 return true; 445 } 446 447 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 448 struct ieee80211_vif *vif, 449 const struct cfg80211_bitrate_mask *mask) 450 { 451 struct ieee80211_supported_band *sband; 452 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 453 struct rtw89_phy_rate_pattern next_pattern = {0}; 454 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 455 static const u16 hw_rate_he[] = {RTW89_HW_RATE_HE_NSS1_MCS0, 456 RTW89_HW_RATE_HE_NSS2_MCS0, 457 RTW89_HW_RATE_HE_NSS3_MCS0, 458 RTW89_HW_RATE_HE_NSS4_MCS0}; 459 static const u16 hw_rate_vht[] = {RTW89_HW_RATE_VHT_NSS1_MCS0, 460 RTW89_HW_RATE_VHT_NSS2_MCS0, 461 RTW89_HW_RATE_VHT_NSS3_MCS0, 462 RTW89_HW_RATE_VHT_NSS4_MCS0}; 463 static const u16 hw_rate_ht[] = {RTW89_HW_RATE_MCS0, 464 RTW89_HW_RATE_MCS8, 465 RTW89_HW_RATE_MCS16, 466 RTW89_HW_RATE_MCS24}; 467 u8 band = chan->band_type; 468 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 469 u8 tx_nss = rtwdev->hal.tx_nss; 470 u8 i; 471 472 for (i = 0; i < tx_nss; i++) 473 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i], 474 RA_MASK_HE_RATES, RTW89_RA_MODE_HE, 475 mask->control[nl_band].he_mcs[i], 476 0, true)) 477 goto out; 478 479 for (i = 0; i < tx_nss; i++) 480 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i], 481 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, 482 mask->control[nl_band].vht_mcs[i], 483 0, true)) 484 goto out; 485 486 for (i = 0; i < tx_nss; i++) 487 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i], 488 RA_MASK_HT_RATES, RTW89_RA_MODE_HT, 489 mask->control[nl_band].ht_mcs[i], 490 0, true)) 491 goto out; 492 493 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and 494 * require at least one basic rate for ieee80211_set_bitrate_mask, 495 * so the decision just depends on if all bitrates are set or not. 496 */ 497 sband = rtwdev->hw->wiphy->bands[nl_band]; 498 if (band == RTW89_BAND_2G) { 499 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, 500 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, 501 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, 502 mask->control[nl_band].legacy, 503 BIT(sband->n_bitrates) - 1, false)) 504 goto out; 505 } else { 506 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, 507 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, 508 mask->control[nl_band].legacy, 509 BIT(sband->n_bitrates) - 1, false)) 510 goto out; 511 } 512 513 if (!next_pattern.enable) 514 goto out; 515 516 rtwvif->rate_pattern = next_pattern; 517 rtw89_debug(rtwdev, RTW89_DBG_RA, 518 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", 519 next_pattern.rate, 520 next_pattern.ra_mask, 521 next_pattern.ra_mode); 522 return; 523 524 out: 525 rtwvif->rate_pattern.enable = false; 526 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); 527 } 528 529 static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta) 530 { 531 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; 532 533 rtw89_phy_ra_updata_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED); 534 } 535 536 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) 537 { 538 ieee80211_iterate_stations_atomic(rtwdev->hw, 539 rtw89_phy_ra_updata_sta_iter, 540 rtwdev); 541 } 542 543 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) 544 { 545 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 546 struct rtw89_ra_info *ra = &rtwsta->ra; 547 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; 548 bool csi = rtw89_sta_has_beamformer_cap(sta); 549 550 rtw89_phy_ra_sta_update(rtwdev, sta, csi); 551 552 if (rssi > 40) 553 ra->init_rate_lv = 1; 554 else if (rssi > 20) 555 ra->init_rate_lv = 2; 556 else if (rssi > 1) 557 ra->init_rate_lv = 3; 558 else 559 ra->init_rate_lv = 0; 560 ra->upd_all = 1; 561 rtw89_debug(rtwdev, RTW89_DBG_RA, 562 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", 563 ra->macid, 564 ra->mode_ctrl, 565 ra->bw_cap, 566 ra->ss_num, 567 ra->init_rate_lv); 568 rtw89_debug(rtwdev, RTW89_DBG_RA, 569 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", 570 ra->dcm_cap, 571 ra->er_cap, 572 ra->ldpc_cap, 573 ra->stbc_cap, 574 ra->en_sgi, 575 ra->giltf); 576 577 rtw89_fw_h2c_ra(rtwdev, ra, csi); 578 } 579 580 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 581 const struct rtw89_chan *chan, 582 enum rtw89_bandwidth dbw) 583 { 584 enum rtw89_bandwidth cbw = chan->band_width; 585 u8 pri_ch = chan->primary_channel; 586 u8 central_ch = chan->channel; 587 u8 txsc_idx = 0; 588 u8 tmp = 0; 589 590 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 591 return txsc_idx; 592 593 switch (cbw) { 594 case RTW89_CHANNEL_WIDTH_40: 595 txsc_idx = pri_ch > central_ch ? 1 : 2; 596 break; 597 case RTW89_CHANNEL_WIDTH_80: 598 if (dbw == RTW89_CHANNEL_WIDTH_20) { 599 if (pri_ch > central_ch) 600 txsc_idx = (pri_ch - central_ch) >> 1; 601 else 602 txsc_idx = ((central_ch - pri_ch) >> 1) + 1; 603 } else { 604 txsc_idx = pri_ch > central_ch ? 9 : 10; 605 } 606 break; 607 case RTW89_CHANNEL_WIDTH_160: 608 if (pri_ch > central_ch) 609 tmp = (pri_ch - central_ch) >> 1; 610 else 611 tmp = ((central_ch - pri_ch) >> 1) + 1; 612 613 if (dbw == RTW89_CHANNEL_WIDTH_20) { 614 txsc_idx = tmp; 615 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 616 if (tmp == 1 || tmp == 3) 617 txsc_idx = 9; 618 else if (tmp == 5 || tmp == 7) 619 txsc_idx = 11; 620 else if (tmp == 2 || tmp == 4) 621 txsc_idx = 10; 622 else if (tmp == 6 || tmp == 8) 623 txsc_idx = 12; 624 else 625 return 0xff; 626 } else { 627 txsc_idx = pri_ch > central_ch ? 13 : 14; 628 } 629 break; 630 case RTW89_CHANNEL_WIDTH_80_80: 631 if (dbw == RTW89_CHANNEL_WIDTH_20) { 632 if (pri_ch > central_ch) 633 txsc_idx = (10 - (pri_ch - central_ch)) >> 1; 634 else 635 txsc_idx = ((central_ch - pri_ch) >> 1) + 5; 636 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 637 txsc_idx = pri_ch > central_ch ? 10 : 12; 638 } else { 639 txsc_idx = 14; 640 } 641 break; 642 default: 643 break; 644 } 645 646 return txsc_idx; 647 } 648 EXPORT_SYMBOL(rtw89_phy_get_txsc); 649 650 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev) 651 { 652 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) || 653 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1); 654 } 655 656 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 657 u32 addr, u32 mask) 658 { 659 const struct rtw89_chip_info *chip = rtwdev->chip; 660 const u32 *base_addr = chip->rf_base_addr; 661 u32 val, direct_addr; 662 663 if (rf_path >= rtwdev->chip->rf_path_num) { 664 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 665 return INV_RF_DATA; 666 } 667 668 addr &= 0xff; 669 direct_addr = base_addr[rf_path] + (addr << 2); 670 mask &= RFREG_MASK; 671 672 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); 673 674 return val; 675 } 676 EXPORT_SYMBOL(rtw89_phy_read_rf); 677 678 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev, 679 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 680 { 681 bool busy; 682 bool done; 683 u32 val; 684 int ret; 685 686 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 687 1, 30, false, rtwdev); 688 if (ret) { 689 rtw89_err(rtwdev, "read rf busy swsi\n"); 690 return INV_RF_DATA; 691 } 692 693 mask &= RFREG_MASK; 694 695 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) | 696 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr); 697 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val); 698 udelay(2); 699 700 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1, 701 30, false, rtwdev, R_SWSI_V1, 702 B_SWSI_R_DATA_DONE_V1); 703 if (ret) { 704 rtw89_err(rtwdev, "read swsi busy\n"); 705 return INV_RF_DATA; 706 } 707 708 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask); 709 } 710 711 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 712 u32 addr, u32 mask) 713 { 714 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 715 716 if (rf_path >= rtwdev->chip->rf_path_num) { 717 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 718 return INV_RF_DATA; 719 } 720 721 if (ad_sel) 722 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 723 else 724 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask); 725 } 726 EXPORT_SYMBOL(rtw89_phy_read_rf_v1); 727 728 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 729 u32 addr, u32 mask, u32 data) 730 { 731 const struct rtw89_chip_info *chip = rtwdev->chip; 732 const u32 *base_addr = chip->rf_base_addr; 733 u32 direct_addr; 734 735 if (rf_path >= rtwdev->chip->rf_path_num) { 736 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 737 return false; 738 } 739 740 addr &= 0xff; 741 direct_addr = base_addr[rf_path] + (addr << 2); 742 mask &= RFREG_MASK; 743 744 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); 745 746 /* delay to ensure writing properly */ 747 udelay(1); 748 749 return true; 750 } 751 EXPORT_SYMBOL(rtw89_phy_write_rf); 752 753 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev, 754 enum rtw89_rf_path rf_path, u32 addr, u32 mask, 755 u32 data) 756 { 757 u8 bit_shift; 758 u32 val; 759 bool busy, b_msk_en = false; 760 int ret; 761 762 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 763 1, 30, false, rtwdev); 764 if (ret) { 765 rtw89_err(rtwdev, "write rf busy swsi\n"); 766 return false; 767 } 768 769 data &= RFREG_MASK; 770 mask &= RFREG_MASK; 771 772 if (mask != RFREG_MASK) { 773 b_msk_en = true; 774 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK, 775 mask); 776 bit_shift = __ffs(mask); 777 data = (data << bit_shift) & RFREG_MASK; 778 } 779 780 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) | 781 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) | 782 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) | 783 FIELD_PREP(B_SWSI_DATA_VAL_V1, data); 784 785 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val); 786 787 return true; 788 } 789 790 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 791 u32 addr, u32 mask, u32 data) 792 { 793 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 794 795 if (rf_path >= rtwdev->chip->rf_path_num) { 796 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 797 return false; 798 } 799 800 if (ad_sel) 801 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 802 else 803 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data); 804 } 805 EXPORT_SYMBOL(rtw89_phy_write_rf_v1); 806 807 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev) 808 { 809 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1; 810 } 811 812 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, 813 enum rtw89_phy_idx phy_idx) 814 { 815 const struct rtw89_chip_info *chip = rtwdev->chip; 816 817 chip->ops->bb_reset(rtwdev, phy_idx); 818 } 819 820 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, 821 const struct rtw89_reg2_def *reg, 822 enum rtw89_rf_path rf_path, 823 void *extra_data) 824 { 825 if (reg->addr == 0xfe) 826 mdelay(50); 827 else if (reg->addr == 0xfd) 828 mdelay(5); 829 else if (reg->addr == 0xfc) 830 mdelay(1); 831 else if (reg->addr == 0xfb) 832 udelay(50); 833 else if (reg->addr == 0xfa) 834 udelay(5); 835 else if (reg->addr == 0xf9) 836 udelay(1); 837 else 838 rtw89_phy_write32(rtwdev, reg->addr, reg->data); 839 } 840 841 union rtw89_phy_bb_gain_arg { 842 u32 addr; 843 struct { 844 union { 845 u8 type; 846 struct { 847 u8 rxsc_start:4; 848 u8 bw:4; 849 }; 850 }; 851 u8 path; 852 u8 gain_band; 853 u8 cfg_type; 854 }; 855 } __packed; 856 857 static void 858 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev, 859 union rtw89_phy_bb_gain_arg arg, u32 data) 860 { 861 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 862 u8 type = arg.type; 863 u8 path = arg.path; 864 u8 gband = arg.gain_band; 865 int i; 866 867 switch (type) { 868 case 0: 869 for (i = 0; i < 4; i++, data >>= 8) 870 gain->lna_gain[gband][path][i] = data & 0xff; 871 break; 872 case 1: 873 for (i = 4; i < 7; i++, data >>= 8) 874 gain->lna_gain[gband][path][i] = data & 0xff; 875 break; 876 case 2: 877 for (i = 0; i < 2; i++, data >>= 8) 878 gain->tia_gain[gband][path][i] = data & 0xff; 879 break; 880 default: 881 rtw89_warn(rtwdev, 882 "bb gain error {0x%x:0x%x} with unknown type: %d\n", 883 arg.addr, data, type); 884 break; 885 } 886 } 887 888 enum rtw89_phy_bb_rxsc_start_idx { 889 RTW89_BB_RXSC_START_IDX_FULL = 0, 890 RTW89_BB_RXSC_START_IDX_20 = 1, 891 RTW89_BB_RXSC_START_IDX_20_1 = 5, 892 RTW89_BB_RXSC_START_IDX_40 = 9, 893 RTW89_BB_RXSC_START_IDX_80 = 13, 894 }; 895 896 static void 897 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev, 898 union rtw89_phy_bb_gain_arg arg, u32 data) 899 { 900 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 901 u8 rxsc_start = arg.rxsc_start; 902 u8 bw = arg.bw; 903 u8 path = arg.path; 904 u8 gband = arg.gain_band; 905 u8 rxsc; 906 s8 ofst; 907 int i; 908 909 switch (bw) { 910 case RTW89_CHANNEL_WIDTH_20: 911 gain->rpl_ofst_20[gband][path] = (s8)data; 912 break; 913 case RTW89_CHANNEL_WIDTH_40: 914 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 915 gain->rpl_ofst_40[gband][path][0] = (s8)data; 916 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 917 for (i = 0; i < 2; i++, data >>= 8) { 918 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 919 ofst = (s8)(data & 0xff); 920 gain->rpl_ofst_40[gband][path][rxsc] = ofst; 921 } 922 } 923 break; 924 case RTW89_CHANNEL_WIDTH_80: 925 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 926 gain->rpl_ofst_80[gband][path][0] = (s8)data; 927 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 928 for (i = 0; i < 4; i++, data >>= 8) { 929 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 930 ofst = (s8)(data & 0xff); 931 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 932 } 933 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 934 for (i = 0; i < 2; i++, data >>= 8) { 935 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 936 ofst = (s8)(data & 0xff); 937 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 938 } 939 } 940 break; 941 case RTW89_CHANNEL_WIDTH_160: 942 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 943 gain->rpl_ofst_160[gband][path][0] = (s8)data; 944 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 945 for (i = 0; i < 4; i++, data >>= 8) { 946 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 947 ofst = (s8)(data & 0xff); 948 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 949 } 950 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) { 951 for (i = 0; i < 4; i++, data >>= 8) { 952 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i; 953 ofst = (s8)(data & 0xff); 954 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 955 } 956 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 957 for (i = 0; i < 4; i++, data >>= 8) { 958 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 959 ofst = (s8)(data & 0xff); 960 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 961 } 962 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) { 963 for (i = 0; i < 2; i++, data >>= 8) { 964 rxsc = RTW89_BB_RXSC_START_IDX_80 + i; 965 ofst = (s8)(data & 0xff); 966 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 967 } 968 } 969 break; 970 default: 971 rtw89_warn(rtwdev, 972 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n", 973 arg.addr, data, bw); 974 break; 975 } 976 } 977 978 static void 979 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev, 980 union rtw89_phy_bb_gain_arg arg, u32 data) 981 { 982 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 983 u8 type = arg.type; 984 u8 path = arg.path; 985 u8 gband = arg.gain_band; 986 int i; 987 988 switch (type) { 989 case 0: 990 for (i = 0; i < 4; i++, data >>= 8) 991 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 992 break; 993 case 1: 994 for (i = 4; i < 7; i++, data >>= 8) 995 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 996 break; 997 default: 998 rtw89_warn(rtwdev, 999 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n", 1000 arg.addr, data, type); 1001 break; 1002 } 1003 } 1004 1005 static void 1006 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev, 1007 union rtw89_phy_bb_gain_arg arg, u32 data) 1008 { 1009 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 1010 u8 type = arg.type; 1011 u8 path = arg.path; 1012 u8 gband = arg.gain_band; 1013 int i; 1014 1015 switch (type) { 1016 case 0: 1017 for (i = 0; i < 4; i++, data >>= 8) 1018 gain->lna_op1db[gband][path][i] = data & 0xff; 1019 break; 1020 case 1: 1021 for (i = 4; i < 7; i++, data >>= 8) 1022 gain->lna_op1db[gband][path][i] = data & 0xff; 1023 break; 1024 case 2: 1025 for (i = 0; i < 4; i++, data >>= 8) 1026 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1027 break; 1028 case 3: 1029 for (i = 4; i < 8; i++, data >>= 8) 1030 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1031 break; 1032 default: 1033 rtw89_warn(rtwdev, 1034 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n", 1035 arg.addr, data, type); 1036 break; 1037 } 1038 } 1039 1040 static void rtw89_phy_config_bb_gain(struct rtw89_dev *rtwdev, 1041 const struct rtw89_reg2_def *reg, 1042 enum rtw89_rf_path rf_path, 1043 void *extra_data) 1044 { 1045 const struct rtw89_chip_info *chip = rtwdev->chip; 1046 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr }; 1047 struct rtw89_efuse *efuse = &rtwdev->efuse; 1048 1049 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR) 1050 return; 1051 1052 if (arg.path >= chip->rf_path_num) 1053 return; 1054 1055 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) { 1056 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n"); 1057 return; 1058 } 1059 1060 switch (arg.cfg_type) { 1061 case 0: 1062 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data); 1063 break; 1064 case 1: 1065 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data); 1066 break; 1067 case 2: 1068 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data); 1069 break; 1070 case 3: 1071 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data); 1072 break; 1073 case 4: 1074 /* This cfg_type is only used by rfe_type >= 50 with eFEM */ 1075 if (efuse->rfe_type < 50) 1076 break; 1077 fallthrough; 1078 default: 1079 rtw89_warn(rtwdev, 1080 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n", 1081 arg.addr, reg->data, arg.cfg_type); 1082 break; 1083 } 1084 } 1085 1086 static void 1087 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, 1088 const struct rtw89_reg2_def *reg, 1089 enum rtw89_rf_path rf_path, 1090 struct rtw89_fw_h2c_rf_reg_info *info) 1091 { 1092 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; 1093 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 1094 1095 if (page >= RTW89_H2C_RF_PAGE_NUM) { 1096 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d", 1097 rf_path, info->curr_idx); 1098 return; 1099 } 1100 1101 info->rtw89_phy_config_rf_h2c[page][idx] = 1102 cpu_to_le32((reg->addr << 20) | reg->data); 1103 info->curr_idx++; 1104 } 1105 1106 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, 1107 struct rtw89_fw_h2c_rf_reg_info *info) 1108 { 1109 u16 remain = info->curr_idx; 1110 u16 len = 0; 1111 u8 i; 1112 int ret = 0; 1113 1114 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) { 1115 rtw89_warn(rtwdev, 1116 "rf reg h2c total len %d larger than %d\n", 1117 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE); 1118 ret = -EINVAL; 1119 goto out; 1120 } 1121 1122 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) { 1123 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain; 1124 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i); 1125 if (ret) 1126 goto out; 1127 } 1128 out: 1129 info->curr_idx = 0; 1130 1131 return ret; 1132 } 1133 1134 static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev, 1135 const struct rtw89_reg2_def *reg, 1136 enum rtw89_rf_path rf_path, 1137 void *extra_data) 1138 { 1139 u32 addr = reg->addr; 1140 1141 if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb || 1142 addr == 0xfa || addr == 0xf9) 1143 return; 1144 1145 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100) 1146 return; 1147 1148 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1149 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1150 } 1151 1152 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, 1153 const struct rtw89_reg2_def *reg, 1154 enum rtw89_rf_path rf_path, 1155 void *extra_data) 1156 { 1157 if (reg->addr == 0xfe) { 1158 mdelay(50); 1159 } else if (reg->addr == 0xfd) { 1160 mdelay(5); 1161 } else if (reg->addr == 0xfc) { 1162 mdelay(1); 1163 } else if (reg->addr == 0xfb) { 1164 udelay(50); 1165 } else if (reg->addr == 0xfa) { 1166 udelay(5); 1167 } else if (reg->addr == 0xf9) { 1168 udelay(1); 1169 } else { 1170 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); 1171 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1172 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1173 } 1174 } 1175 1176 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 1177 const struct rtw89_reg2_def *reg, 1178 enum rtw89_rf_path rf_path, 1179 void *extra_data) 1180 { 1181 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data); 1182 1183 if (reg->addr < 0x100) 1184 return; 1185 1186 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1187 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1188 } 1189 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1); 1190 1191 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, 1192 const struct rtw89_phy_table *table, 1193 u32 *headline_size, u32 *headline_idx, 1194 u8 rfe, u8 cv) 1195 { 1196 const struct rtw89_reg2_def *reg; 1197 u32 headline; 1198 u32 compare, target; 1199 u8 rfe_para, cv_para; 1200 u8 cv_max = 0; 1201 bool case_matched = false; 1202 u32 i; 1203 1204 for (i = 0; i < table->n_regs; i++) { 1205 reg = &table->regs[i]; 1206 headline = get_phy_headline(reg->addr); 1207 if (headline != PHY_HEADLINE_VALID) 1208 break; 1209 } 1210 *headline_size = i; 1211 if (*headline_size == 0) 1212 return 0; 1213 1214 /* case 1: RFE match, CV match */ 1215 compare = get_phy_compare(rfe, cv); 1216 for (i = 0; i < *headline_size; i++) { 1217 reg = &table->regs[i]; 1218 target = get_phy_target(reg->addr); 1219 if (target == compare) { 1220 *headline_idx = i; 1221 return 0; 1222 } 1223 } 1224 1225 /* case 2: RFE match, CV don't care */ 1226 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); 1227 for (i = 0; i < *headline_size; i++) { 1228 reg = &table->regs[i]; 1229 target = get_phy_target(reg->addr); 1230 if (target == compare) { 1231 *headline_idx = i; 1232 return 0; 1233 } 1234 } 1235 1236 /* case 3: RFE match, CV max in table */ 1237 for (i = 0; i < *headline_size; i++) { 1238 reg = &table->regs[i]; 1239 rfe_para = get_phy_cond_rfe(reg->addr); 1240 cv_para = get_phy_cond_cv(reg->addr); 1241 if (rfe_para == rfe) { 1242 if (cv_para >= cv_max) { 1243 cv_max = cv_para; 1244 *headline_idx = i; 1245 case_matched = true; 1246 } 1247 } 1248 } 1249 1250 if (case_matched) 1251 return 0; 1252 1253 /* case 4: RFE don't care, CV max in table */ 1254 for (i = 0; i < *headline_size; i++) { 1255 reg = &table->regs[i]; 1256 rfe_para = get_phy_cond_rfe(reg->addr); 1257 cv_para = get_phy_cond_cv(reg->addr); 1258 if (rfe_para == PHY_COND_DONT_CARE) { 1259 if (cv_para >= cv_max) { 1260 cv_max = cv_para; 1261 *headline_idx = i; 1262 case_matched = true; 1263 } 1264 } 1265 } 1266 1267 if (case_matched) 1268 return 0; 1269 1270 return -EINVAL; 1271 } 1272 1273 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, 1274 const struct rtw89_phy_table *table, 1275 void (*config)(struct rtw89_dev *rtwdev, 1276 const struct rtw89_reg2_def *reg, 1277 enum rtw89_rf_path rf_path, 1278 void *data), 1279 void *extra_data) 1280 { 1281 const struct rtw89_reg2_def *reg; 1282 enum rtw89_rf_path rf_path = table->rf_path; 1283 u8 rfe = rtwdev->efuse.rfe_type; 1284 u8 cv = rtwdev->hal.cv; 1285 u32 i; 1286 u32 headline_size = 0, headline_idx = 0; 1287 u32 target = 0, cfg_target; 1288 u8 cond; 1289 bool is_matched = true; 1290 bool target_found = false; 1291 int ret; 1292 1293 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, 1294 &headline_idx, rfe, cv); 1295 if (ret) { 1296 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); 1297 return; 1298 } 1299 1300 cfg_target = get_phy_target(table->regs[headline_idx].addr); 1301 for (i = headline_size; i < table->n_regs; i++) { 1302 reg = &table->regs[i]; 1303 cond = get_phy_cond(reg->addr); 1304 switch (cond) { 1305 case PHY_COND_BRANCH_IF: 1306 case PHY_COND_BRANCH_ELIF: 1307 target = get_phy_target(reg->addr); 1308 break; 1309 case PHY_COND_BRANCH_ELSE: 1310 is_matched = false; 1311 if (!target_found) { 1312 rtw89_warn(rtwdev, "failed to load CR %x/%x\n", 1313 reg->addr, reg->data); 1314 return; 1315 } 1316 break; 1317 case PHY_COND_BRANCH_END: 1318 is_matched = true; 1319 target_found = false; 1320 break; 1321 case PHY_COND_CHECK: 1322 if (target_found) { 1323 is_matched = false; 1324 break; 1325 } 1326 1327 if (target == cfg_target) { 1328 is_matched = true; 1329 target_found = true; 1330 } else { 1331 is_matched = false; 1332 target_found = false; 1333 } 1334 break; 1335 default: 1336 if (is_matched) 1337 config(rtwdev, reg, rf_path, extra_data); 1338 break; 1339 } 1340 } 1341 } 1342 1343 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) 1344 { 1345 const struct rtw89_chip_info *chip = rtwdev->chip; 1346 const struct rtw89_phy_table *bb_table = chip->bb_table; 1347 const struct rtw89_phy_table *bb_gain_table = chip->bb_gain_table; 1348 1349 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); 1350 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 1351 if (bb_gain_table) 1352 rtw89_phy_init_reg(rtwdev, bb_gain_table, 1353 rtw89_phy_config_bb_gain, NULL); 1354 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); 1355 } 1356 1357 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 1358 { 1359 rtw89_phy_write32(rtwdev, 0x8080, 0x4); 1360 udelay(1); 1361 return rtw89_phy_read32(rtwdev, 0x8080); 1362 } 1363 1364 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio) 1365 { 1366 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 1367 enum rtw89_rf_path rf_path, void *data); 1368 const struct rtw89_chip_info *chip = rtwdev->chip; 1369 const struct rtw89_phy_table *rf_table; 1370 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; 1371 u8 path; 1372 1373 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); 1374 if (!rf_reg_info) 1375 return; 1376 1377 for (path = RF_PATH_A; path < chip->rf_path_num; path++) { 1378 rf_table = chip->rf_table[path]; 1379 rf_reg_info->rf_path = rf_table->rf_path; 1380 if (noio) 1381 config = rtw89_phy_config_rf_reg_noio; 1382 else 1383 config = rf_table->config ? rf_table->config : 1384 rtw89_phy_config_rf_reg; 1385 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info); 1386 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) 1387 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", 1388 rf_reg_info->rf_path); 1389 } 1390 kfree(rf_reg_info); 1391 } 1392 1393 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) 1394 { 1395 const struct rtw89_chip_info *chip = rtwdev->chip; 1396 const struct rtw89_phy_table *nctl_table; 1397 u32 val; 1398 int ret; 1399 1400 /* IQK/DPK clock & reset */ 1401 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3); 1402 rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1); 1403 rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000); 1404 rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000); 1405 if (chip->chip_id == RTL8852B) 1406 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2); 1407 1408 /* check 0x8080 */ 1409 rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8); 1410 1411 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, 1412 1000, false, rtwdev); 1413 if (ret) 1414 rtw89_err(rtwdev, "failed to poll nctl block\n"); 1415 1416 nctl_table = chip->nctl_table; 1417 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); 1418 } 1419 1420 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) 1421 { 1422 u32 phy_page = addr >> 8; 1423 u32 ofst = 0; 1424 1425 switch (phy_page) { 1426 case 0x6: 1427 case 0x7: 1428 case 0x8: 1429 case 0x9: 1430 case 0xa: 1431 case 0xb: 1432 case 0xc: 1433 case 0xd: 1434 case 0x19: 1435 case 0x1a: 1436 case 0x1b: 1437 ofst = 0x2000; 1438 break; 1439 default: 1440 /* warning case */ 1441 ofst = 0; 1442 break; 1443 } 1444 1445 if (phy_page >= 0x40 && phy_page <= 0x4f) 1446 ofst = 0x2000; 1447 1448 return ofst; 1449 } 1450 1451 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1452 u32 data, enum rtw89_phy_idx phy_idx) 1453 { 1454 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1455 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1456 rtw89_phy_write32_mask(rtwdev, addr, mask, data); 1457 } 1458 EXPORT_SYMBOL(rtw89_phy_write32_idx); 1459 1460 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1461 enum rtw89_phy_idx phy_idx) 1462 { 1463 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1464 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1465 return rtw89_phy_read32_mask(rtwdev, addr, mask); 1466 } 1467 EXPORT_SYMBOL(rtw89_phy_read32_idx); 1468 1469 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1470 u32 val) 1471 { 1472 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 1473 1474 if (!rtwdev->dbcc_en) 1475 return; 1476 1477 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 1478 } 1479 1480 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 1481 const struct rtw89_phy_reg3_tbl *tbl) 1482 { 1483 const struct rtw89_reg3_def *reg3; 1484 int i; 1485 1486 for (i = 0; i < tbl->size; i++) { 1487 reg3 = &tbl->reg3[i]; 1488 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); 1489 } 1490 } 1491 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl); 1492 1493 static const u8 rtw89_rs_idx_max[] = { 1494 [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX, 1495 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX, 1496 [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX, 1497 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX, 1498 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX, 1499 }; 1500 1501 static const u8 rtw89_rs_nss_max[] = { 1502 [RTW89_RS_CCK] = 1, 1503 [RTW89_RS_OFDM] = 1, 1504 [RTW89_RS_MCS] = RTW89_NSS_MAX, 1505 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX, 1506 [RTW89_RS_OFFSET] = 1, 1507 }; 1508 1509 static const u8 _byr_of_rs[] = { 1510 [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck), 1511 [RTW89_RS_OFDM] = offsetof(struct rtw89_txpwr_byrate, ofdm), 1512 [RTW89_RS_MCS] = offsetof(struct rtw89_txpwr_byrate, mcs), 1513 [RTW89_RS_HEDCM] = offsetof(struct rtw89_txpwr_byrate, hedcm), 1514 [RTW89_RS_OFFSET] = offsetof(struct rtw89_txpwr_byrate, offset), 1515 }; 1516 1517 #define _byr_seek(rs, raw) ((s8 *)(raw) + _byr_of_rs[rs]) 1518 #define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_max[rs] + (idx)) 1519 #define _byr_chk(rs, nss, idx) \ 1520 ((nss) < rtw89_rs_nss_max[rs] && (idx) < rtw89_rs_idx_max[rs]) 1521 1522 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 1523 const struct rtw89_txpwr_table *tbl) 1524 { 1525 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; 1526 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; 1527 s8 *byr; 1528 u32 data; 1529 u8 i, idx; 1530 1531 for (; cfg < end; cfg++) { 1532 byr = _byr_seek(cfg->rs, &rtwdev->byr[cfg->band]); 1533 data = cfg->data; 1534 1535 for (i = 0; i < cfg->len; i++, data >>= 8) { 1536 idx = _byr_idx(cfg->rs, cfg->nss, (cfg->shf + i)); 1537 byr[idx] = (s8)(data & 0xff); 1538 } 1539 } 1540 } 1541 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate); 1542 1543 #define _phy_txpwr_rf_to_mac(rtwdev, txpwr_rf) \ 1544 ({ \ 1545 const struct rtw89_chip_info *__c = (rtwdev)->chip; \ 1546 (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \ 1547 }) 1548 1549 static 1550 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, 1551 const struct rtw89_rate_desc *rate_desc) 1552 { 1553 s8 *byr; 1554 u8 idx; 1555 1556 if (rate_desc->rs == RTW89_RS_CCK) 1557 band = RTW89_BAND_2G; 1558 1559 if (!_byr_chk(rate_desc->rs, rate_desc->nss, rate_desc->idx)) { 1560 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1561 "[TXPWR] unknown byrate desc rs=%d nss=%d idx=%d\n", 1562 rate_desc->rs, rate_desc->nss, rate_desc->idx); 1563 1564 return 0; 1565 } 1566 1567 byr = _byr_seek(rate_desc->rs, &rtwdev->byr[band]); 1568 idx = _byr_idx(rate_desc->rs, rate_desc->nss, rate_desc->idx); 1569 1570 return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]); 1571 } 1572 1573 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g) 1574 { 1575 switch (channel_6g) { 1576 case 1 ... 29: 1577 return (channel_6g - 1) / 2; 1578 case 33 ... 61: 1579 return (channel_6g - 3) / 2; 1580 case 65 ... 93: 1581 return (channel_6g - 5) / 2; 1582 case 97 ... 125: 1583 return (channel_6g - 7) / 2; 1584 case 129 ... 157: 1585 return (channel_6g - 9) / 2; 1586 case 161 ... 189: 1587 return (channel_6g - 11) / 2; 1588 case 193 ... 221: 1589 return (channel_6g - 13) / 2; 1590 case 225 ... 253: 1591 return (channel_6g - 15) / 2; 1592 default: 1593 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g); 1594 return 0; 1595 } 1596 } 1597 1598 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel) 1599 { 1600 if (band == RTW89_BAND_6G) 1601 return rtw89_channel_6g_to_idx(rtwdev, channel); 1602 1603 switch (channel) { 1604 case 1 ... 14: 1605 return channel - 1; 1606 case 36 ... 64: 1607 return (channel - 36) / 2; 1608 case 100 ... 144: 1609 return ((channel - 100) / 2) + 15; 1610 case 149 ... 177: 1611 return ((channel - 149) / 2) + 38; 1612 default: 1613 rtw89_warn(rtwdev, "unknown channel: %d\n", channel); 1614 return 0; 1615 } 1616 } 1617 1618 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 1619 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) 1620 { 1621 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 1622 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; 1623 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; 1624 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; 1625 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1626 u8 regd = rtw89_regd_get(rtwdev, band); 1627 s8 lmt = 0, sar; 1628 1629 switch (band) { 1630 case RTW89_BAND_2G: 1631 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 1632 if (lmt) 1633 break; 1634 1635 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 1636 break; 1637 case RTW89_BAND_5G: 1638 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 1639 if (lmt) 1640 break; 1641 1642 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 1643 break; 1644 case RTW89_BAND_6G: 1645 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 1646 if (lmt) 1647 break; 1648 1649 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 1650 break; 1651 default: 1652 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1653 return 0; 1654 } 1655 1656 lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt); 1657 sar = rtw89_query_sar(rtwdev); 1658 1659 return min(lmt, sar); 1660 } 1661 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit); 1662 1663 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \ 1664 do { \ 1665 u8 __i; \ 1666 for (__i = 0; __i < RTW89_BF_NUM; __i++) \ 1667 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ 1668 band, \ 1669 bw, ntx, \ 1670 rs, __i, \ 1671 (ch)); \ 1672 } while (0) 1673 1674 static void rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev *rtwdev, 1675 struct rtw89_txpwr_limit *lmt, 1676 u8 band, u8 ntx, u8 ch) 1677 { 1678 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1679 ntx, RTW89_RS_CCK, ch); 1680 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1681 ntx, RTW89_RS_CCK, ch); 1682 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1683 ntx, RTW89_RS_OFDM, ch); 1684 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1685 RTW89_CHANNEL_WIDTH_20, 1686 ntx, RTW89_RS_MCS, ch); 1687 } 1688 1689 static void rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev *rtwdev, 1690 struct rtw89_txpwr_limit *lmt, 1691 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1692 { 1693 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1694 ntx, RTW89_RS_CCK, ch - 2); 1695 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1696 ntx, RTW89_RS_CCK, ch); 1697 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1698 ntx, RTW89_RS_OFDM, pri_ch); 1699 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1700 RTW89_CHANNEL_WIDTH_20, 1701 ntx, RTW89_RS_MCS, ch - 2); 1702 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1703 RTW89_CHANNEL_WIDTH_20, 1704 ntx, RTW89_RS_MCS, ch + 2); 1705 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1706 RTW89_CHANNEL_WIDTH_40, 1707 ntx, RTW89_RS_MCS, ch); 1708 } 1709 1710 static void rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev *rtwdev, 1711 struct rtw89_txpwr_limit *lmt, 1712 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1713 { 1714 s8 val_0p5_n[RTW89_BF_NUM]; 1715 s8 val_0p5_p[RTW89_BF_NUM]; 1716 u8 i; 1717 1718 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1719 ntx, RTW89_RS_OFDM, pri_ch); 1720 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1721 RTW89_CHANNEL_WIDTH_20, 1722 ntx, RTW89_RS_MCS, ch - 6); 1723 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1724 RTW89_CHANNEL_WIDTH_20, 1725 ntx, RTW89_RS_MCS, ch - 2); 1726 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1727 RTW89_CHANNEL_WIDTH_20, 1728 ntx, RTW89_RS_MCS, ch + 2); 1729 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1730 RTW89_CHANNEL_WIDTH_20, 1731 ntx, RTW89_RS_MCS, ch + 6); 1732 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1733 RTW89_CHANNEL_WIDTH_40, 1734 ntx, RTW89_RS_MCS, ch - 4); 1735 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1736 RTW89_CHANNEL_WIDTH_40, 1737 ntx, RTW89_RS_MCS, ch + 4); 1738 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1739 RTW89_CHANNEL_WIDTH_80, 1740 ntx, RTW89_RS_MCS, ch); 1741 1742 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1743 ntx, RTW89_RS_MCS, ch - 4); 1744 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1745 ntx, RTW89_RS_MCS, ch + 4); 1746 1747 for (i = 0; i < RTW89_BF_NUM; i++) 1748 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1749 } 1750 1751 static void rtw89_phy_fill_txpwr_limit_160m(struct rtw89_dev *rtwdev, 1752 struct rtw89_txpwr_limit *lmt, 1753 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1754 { 1755 s8 val_0p5_n[RTW89_BF_NUM]; 1756 s8 val_0p5_p[RTW89_BF_NUM]; 1757 s8 val_2p5_n[RTW89_BF_NUM]; 1758 s8 val_2p5_p[RTW89_BF_NUM]; 1759 u8 i; 1760 1761 /* fill ofdm section */ 1762 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1763 ntx, RTW89_RS_OFDM, pri_ch); 1764 1765 /* fill mcs 20m section */ 1766 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1767 RTW89_CHANNEL_WIDTH_20, 1768 ntx, RTW89_RS_MCS, ch - 14); 1769 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1770 RTW89_CHANNEL_WIDTH_20, 1771 ntx, RTW89_RS_MCS, ch - 10); 1772 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1773 RTW89_CHANNEL_WIDTH_20, 1774 ntx, RTW89_RS_MCS, ch - 6); 1775 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1776 RTW89_CHANNEL_WIDTH_20, 1777 ntx, RTW89_RS_MCS, ch - 2); 1778 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band, 1779 RTW89_CHANNEL_WIDTH_20, 1780 ntx, RTW89_RS_MCS, ch + 2); 1781 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band, 1782 RTW89_CHANNEL_WIDTH_20, 1783 ntx, RTW89_RS_MCS, ch + 6); 1784 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band, 1785 RTW89_CHANNEL_WIDTH_20, 1786 ntx, RTW89_RS_MCS, ch + 10); 1787 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band, 1788 RTW89_CHANNEL_WIDTH_20, 1789 ntx, RTW89_RS_MCS, ch + 14); 1790 1791 /* fill mcs 40m section */ 1792 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1793 RTW89_CHANNEL_WIDTH_40, 1794 ntx, RTW89_RS_MCS, ch - 12); 1795 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1796 RTW89_CHANNEL_WIDTH_40, 1797 ntx, RTW89_RS_MCS, ch - 4); 1798 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band, 1799 RTW89_CHANNEL_WIDTH_40, 1800 ntx, RTW89_RS_MCS, ch + 4); 1801 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band, 1802 RTW89_CHANNEL_WIDTH_40, 1803 ntx, RTW89_RS_MCS, ch + 12); 1804 1805 /* fill mcs 80m section */ 1806 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1807 RTW89_CHANNEL_WIDTH_80, 1808 ntx, RTW89_RS_MCS, ch - 8); 1809 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band, 1810 RTW89_CHANNEL_WIDTH_80, 1811 ntx, RTW89_RS_MCS, ch + 8); 1812 1813 /* fill mcs 160m section */ 1814 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band, 1815 RTW89_CHANNEL_WIDTH_160, 1816 ntx, RTW89_RS_MCS, ch); 1817 1818 /* fill mcs 40m 0p5 section */ 1819 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1820 ntx, RTW89_RS_MCS, ch - 4); 1821 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1822 ntx, RTW89_RS_MCS, ch + 4); 1823 1824 for (i = 0; i < RTW89_BF_NUM; i++) 1825 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1826 1827 /* fill mcs 40m 2p5 section */ 1828 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40, 1829 ntx, RTW89_RS_MCS, ch - 8); 1830 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40, 1831 ntx, RTW89_RS_MCS, ch + 8); 1832 1833 for (i = 0; i < RTW89_BF_NUM; i++) 1834 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]); 1835 } 1836 1837 static 1838 void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev, 1839 const struct rtw89_chan *chan, 1840 struct rtw89_txpwr_limit *lmt, 1841 u8 ntx) 1842 { 1843 u8 band = chan->band_type; 1844 u8 pri_ch = chan->primary_channel; 1845 u8 ch = chan->channel; 1846 u8 bw = chan->band_width; 1847 1848 memset(lmt, 0, sizeof(*lmt)); 1849 1850 switch (bw) { 1851 case RTW89_CHANNEL_WIDTH_20: 1852 rtw89_phy_fill_txpwr_limit_20m(rtwdev, lmt, band, ntx, ch); 1853 break; 1854 case RTW89_CHANNEL_WIDTH_40: 1855 rtw89_phy_fill_txpwr_limit_40m(rtwdev, lmt, band, ntx, ch, 1856 pri_ch); 1857 break; 1858 case RTW89_CHANNEL_WIDTH_80: 1859 rtw89_phy_fill_txpwr_limit_80m(rtwdev, lmt, band, ntx, ch, 1860 pri_ch); 1861 break; 1862 case RTW89_CHANNEL_WIDTH_160: 1863 rtw89_phy_fill_txpwr_limit_160m(rtwdev, lmt, band, ntx, ch, 1864 pri_ch); 1865 break; 1866 } 1867 } 1868 1869 static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 1870 u8 ru, u8 ntx, u8 ch) 1871 { 1872 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 1873 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; 1874 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; 1875 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; 1876 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1877 u8 regd = rtw89_regd_get(rtwdev, band); 1878 s8 lmt_ru = 0, sar; 1879 1880 switch (band) { 1881 case RTW89_BAND_2G: 1882 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 1883 if (lmt_ru) 1884 break; 1885 1886 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 1887 break; 1888 case RTW89_BAND_5G: 1889 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 1890 if (lmt_ru) 1891 break; 1892 1893 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 1894 break; 1895 case RTW89_BAND_6G: 1896 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 1897 if (lmt_ru) 1898 break; 1899 1900 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 1901 break; 1902 default: 1903 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1904 return 0; 1905 } 1906 1907 lmt_ru = _phy_txpwr_rf_to_mac(rtwdev, lmt_ru); 1908 sar = rtw89_query_sar(rtwdev); 1909 1910 return min(lmt_ru, sar); 1911 } 1912 1913 static void 1914 rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev, 1915 struct rtw89_txpwr_limit_ru *lmt_ru, 1916 u8 band, u8 ntx, u8 ch) 1917 { 1918 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1919 RTW89_RU26, 1920 ntx, ch); 1921 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1922 RTW89_RU52, 1923 ntx, ch); 1924 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1925 RTW89_RU106, 1926 ntx, ch); 1927 } 1928 1929 static void 1930 rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev, 1931 struct rtw89_txpwr_limit_ru *lmt_ru, 1932 u8 band, u8 ntx, u8 ch) 1933 { 1934 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1935 RTW89_RU26, 1936 ntx, ch - 2); 1937 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1938 RTW89_RU26, 1939 ntx, ch + 2); 1940 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1941 RTW89_RU52, 1942 ntx, ch - 2); 1943 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1944 RTW89_RU52, 1945 ntx, ch + 2); 1946 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1947 RTW89_RU106, 1948 ntx, ch - 2); 1949 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1950 RTW89_RU106, 1951 ntx, ch + 2); 1952 } 1953 1954 static void 1955 rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev, 1956 struct rtw89_txpwr_limit_ru *lmt_ru, 1957 u8 band, u8 ntx, u8 ch) 1958 { 1959 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1960 RTW89_RU26, 1961 ntx, ch - 6); 1962 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1963 RTW89_RU26, 1964 ntx, ch - 2); 1965 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1966 RTW89_RU26, 1967 ntx, ch + 2); 1968 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1969 RTW89_RU26, 1970 ntx, ch + 6); 1971 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1972 RTW89_RU52, 1973 ntx, ch - 6); 1974 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1975 RTW89_RU52, 1976 ntx, ch - 2); 1977 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1978 RTW89_RU52, 1979 ntx, ch + 2); 1980 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1981 RTW89_RU52, 1982 ntx, ch + 6); 1983 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1984 RTW89_RU106, 1985 ntx, ch - 6); 1986 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1987 RTW89_RU106, 1988 ntx, ch - 2); 1989 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1990 RTW89_RU106, 1991 ntx, ch + 2); 1992 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1993 RTW89_RU106, 1994 ntx, ch + 6); 1995 } 1996 1997 static void 1998 rtw89_phy_fill_txpwr_limit_ru_160m(struct rtw89_dev *rtwdev, 1999 struct rtw89_txpwr_limit_ru *lmt_ru, 2000 u8 band, u8 ntx, u8 ch) 2001 { 2002 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 }; 2003 int i; 2004 2005 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM); 2006 for (i = 0; i < RTW89_RU_SEC_NUM; i++) { 2007 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2008 RTW89_RU26, 2009 ntx, 2010 ch + ofst[i]); 2011 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2012 RTW89_RU52, 2013 ntx, 2014 ch + ofst[i]); 2015 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2016 RTW89_RU106, 2017 ntx, 2018 ch + ofst[i]); 2019 } 2020 } 2021 2022 static 2023 void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, 2024 const struct rtw89_chan *chan, 2025 struct rtw89_txpwr_limit_ru *lmt_ru, 2026 u8 ntx) 2027 { 2028 u8 band = chan->band_type; 2029 u8 ch = chan->channel; 2030 u8 bw = chan->band_width; 2031 2032 memset(lmt_ru, 0, sizeof(*lmt_ru)); 2033 2034 switch (bw) { 2035 case RTW89_CHANNEL_WIDTH_20: 2036 rtw89_phy_fill_txpwr_limit_ru_20m(rtwdev, lmt_ru, band, ntx, 2037 ch); 2038 break; 2039 case RTW89_CHANNEL_WIDTH_40: 2040 rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, band, ntx, 2041 ch); 2042 break; 2043 case RTW89_CHANNEL_WIDTH_80: 2044 rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, band, ntx, 2045 ch); 2046 break; 2047 case RTW89_CHANNEL_WIDTH_160: 2048 rtw89_phy_fill_txpwr_limit_ru_160m(rtwdev, lmt_ru, band, ntx, 2049 ch); 2050 break; 2051 } 2052 } 2053 2054 void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev, 2055 const struct rtw89_chan *chan, 2056 enum rtw89_phy_idx phy_idx) 2057 { 2058 u8 max_nss_num = rtwdev->chip->rf_path_num; 2059 static const u8 rs[] = { 2060 RTW89_RS_CCK, 2061 RTW89_RS_OFDM, 2062 RTW89_RS_MCS, 2063 RTW89_RS_HEDCM, 2064 }; 2065 struct rtw89_rate_desc cur; 2066 u8 band = chan->band_type; 2067 u8 ch = chan->channel; 2068 u32 addr, val; 2069 s8 v[4] = {}; 2070 u8 i; 2071 2072 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2073 "[TXPWR] set txpwr byrate with ch=%d\n", ch); 2074 2075 BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_CCK] % 4); 2076 BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_OFDM] % 4); 2077 BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_MCS] % 4); 2078 BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_HEDCM] % 4); 2079 2080 addr = R_AX_PWR_BY_RATE; 2081 for (cur.nss = 0; cur.nss < max_nss_num; cur.nss++) { 2082 for (i = 0; i < ARRAY_SIZE(rs); i++) { 2083 if (cur.nss >= rtw89_rs_nss_max[rs[i]]) 2084 continue; 2085 2086 cur.rs = rs[i]; 2087 for (cur.idx = 0; cur.idx < rtw89_rs_idx_max[rs[i]]; 2088 cur.idx++) { 2089 v[cur.idx % 4] = 2090 rtw89_phy_read_txpwr_byrate(rtwdev, 2091 band, 2092 &cur); 2093 2094 if ((cur.idx + 1) % 4) 2095 continue; 2096 2097 val = FIELD_PREP(GENMASK(7, 0), v[0]) | 2098 FIELD_PREP(GENMASK(15, 8), v[1]) | 2099 FIELD_PREP(GENMASK(23, 16), v[2]) | 2100 FIELD_PREP(GENMASK(31, 24), v[3]); 2101 2102 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 2103 val); 2104 addr += 4; 2105 } 2106 } 2107 } 2108 } 2109 EXPORT_SYMBOL(rtw89_phy_set_txpwr_byrate); 2110 2111 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev, 2112 const struct rtw89_chan *chan, 2113 enum rtw89_phy_idx phy_idx) 2114 { 2115 struct rtw89_rate_desc desc = { 2116 .nss = RTW89_NSS_1, 2117 .rs = RTW89_RS_OFFSET, 2118 }; 2119 u8 band = chan->band_type; 2120 s8 v[RTW89_RATE_OFFSET_MAX] = {}; 2121 u32 val; 2122 2123 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n"); 2124 2125 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++) 2126 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, &desc); 2127 2128 BUILD_BUG_ON(RTW89_RATE_OFFSET_MAX != 5); 2129 val = FIELD_PREP(GENMASK(3, 0), v[0]) | 2130 FIELD_PREP(GENMASK(7, 4), v[1]) | 2131 FIELD_PREP(GENMASK(11, 8), v[2]) | 2132 FIELD_PREP(GENMASK(15, 12), v[3]) | 2133 FIELD_PREP(GENMASK(19, 16), v[4]); 2134 2135 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL, 2136 GENMASK(19, 0), val); 2137 } 2138 EXPORT_SYMBOL(rtw89_phy_set_txpwr_offset); 2139 2140 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev, 2141 const struct rtw89_chan *chan, 2142 enum rtw89_phy_idx phy_idx) 2143 { 2144 u8 max_ntx_num = rtwdev->chip->rf_path_num; 2145 struct rtw89_txpwr_limit lmt; 2146 u8 ch = chan->channel; 2147 u8 bw = chan->band_width; 2148 const s8 *ptr; 2149 u32 addr, val; 2150 u8 i, j; 2151 2152 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2153 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw); 2154 2155 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit) != 2156 RTW89_TXPWR_LMT_PAGE_SIZE); 2157 2158 addr = R_AX_PWR_LMT; 2159 for (i = 0; i < max_ntx_num; i++) { 2160 rtw89_phy_fill_txpwr_limit(rtwdev, chan, &lmt, i); 2161 2162 ptr = (s8 *)&lmt; 2163 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE; 2164 j += 4, addr += 4, ptr += 4) { 2165 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2166 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2167 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2168 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2169 2170 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2171 } 2172 } 2173 } 2174 EXPORT_SYMBOL(rtw89_phy_set_txpwr_limit); 2175 2176 void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, 2177 const struct rtw89_chan *chan, 2178 enum rtw89_phy_idx phy_idx) 2179 { 2180 u8 max_ntx_num = rtwdev->chip->rf_path_num; 2181 struct rtw89_txpwr_limit_ru lmt_ru; 2182 u8 ch = chan->channel; 2183 u8 bw = chan->band_width; 2184 const s8 *ptr; 2185 u32 addr, val; 2186 u8 i, j; 2187 2188 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2189 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); 2190 2191 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru) != 2192 RTW89_TXPWR_LMT_RU_PAGE_SIZE); 2193 2194 addr = R_AX_PWR_RU_LMT; 2195 for (i = 0; i < max_ntx_num; i++) { 2196 rtw89_phy_fill_txpwr_limit_ru(rtwdev, chan, &lmt_ru, i); 2197 2198 ptr = (s8 *)&lmt_ru; 2199 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE; 2200 j += 4, addr += 4, ptr += 4) { 2201 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2202 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2203 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2204 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2205 2206 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2207 } 2208 } 2209 } 2210 EXPORT_SYMBOL(rtw89_phy_set_txpwr_limit_ru); 2211 2212 struct rtw89_phy_iter_ra_data { 2213 struct rtw89_dev *rtwdev; 2214 struct sk_buff *c2h; 2215 }; 2216 2217 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) 2218 { 2219 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; 2220 struct rtw89_dev *rtwdev = ra_data->rtwdev; 2221 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2222 struct rtw89_ra_report *ra_report = &rtwsta->ra_report; 2223 struct sk_buff *c2h = ra_data->c2h; 2224 u8 mode, rate, bw, giltf, mac_id; 2225 u16 legacy_bitrate; 2226 bool valid; 2227 u8 mcs = 0; 2228 2229 mac_id = RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h->data); 2230 if (mac_id != rtwsta->mac_id) 2231 return; 2232 2233 rate = RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h->data); 2234 bw = RTW89_GET_PHY_C2H_RA_RPT_BW(c2h->data); 2235 giltf = RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h->data); 2236 mode = RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h->data); 2237 2238 if (mode == RTW89_RA_RPT_MODE_LEGACY) { 2239 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate); 2240 if (!valid) 2241 return; 2242 } 2243 2244 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate)); 2245 2246 switch (mode) { 2247 case RTW89_RA_RPT_MODE_LEGACY: 2248 ra_report->txrate.legacy = legacy_bitrate; 2249 break; 2250 case RTW89_RA_RPT_MODE_HT: 2251 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; 2252 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw)) 2253 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), 2254 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); 2255 else 2256 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); 2257 ra_report->txrate.mcs = rate; 2258 if (giltf) 2259 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2260 mcs = ra_report->txrate.mcs & 0x07; 2261 break; 2262 case RTW89_RA_RPT_MODE_VHT: 2263 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; 2264 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 2265 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 2266 if (giltf) 2267 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2268 mcs = ra_report->txrate.mcs; 2269 break; 2270 case RTW89_RA_RPT_MODE_HE: 2271 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; 2272 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 2273 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 2274 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2275 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; 2276 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2277 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; 2278 else 2279 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; 2280 mcs = ra_report->txrate.mcs; 2281 break; 2282 } 2283 2284 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw); 2285 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); 2286 ra_report->hw_rate = FIELD_PREP(RTW89_HW_RATE_MASK_MOD, mode) | 2287 FIELD_PREP(RTW89_HW_RATE_MASK_VAL, rate); 2288 ra_report->might_fallback_legacy = mcs <= 2; 2289 sta->deflink.agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); 2290 rtwsta->max_agg_wait = sta->deflink.agg.max_rc_amsdu_len / 1500 - 1; 2291 } 2292 2293 static void 2294 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2295 { 2296 struct rtw89_phy_iter_ra_data ra_data; 2297 2298 ra_data.rtwdev = rtwdev; 2299 ra_data.c2h = c2h; 2300 ieee80211_iterate_stations_atomic(rtwdev->hw, 2301 rtw89_phy_c2h_ra_rpt_iter, 2302 &ra_data); 2303 } 2304 2305 static 2306 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, 2307 struct sk_buff *c2h, u32 len) = { 2308 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 2309 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 2310 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 2311 }; 2312 2313 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 2314 u32 len, u8 class, u8 func) 2315 { 2316 void (*handler)(struct rtw89_dev *rtwdev, 2317 struct sk_buff *c2h, u32 len) = NULL; 2318 2319 switch (class) { 2320 case RTW89_PHY_C2H_CLASS_RA: 2321 if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 2322 handler = rtw89_phy_c2h_ra_handler[func]; 2323 break; 2324 case RTW89_PHY_C2H_CLASS_DM: 2325 if (func == RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY) 2326 return; 2327 fallthrough; 2328 default: 2329 rtw89_info(rtwdev, "c2h class %d not support\n", class); 2330 return; 2331 } 2332 if (!handler) { 2333 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 2334 func); 2335 return; 2336 } 2337 handler(rtwdev, skb, len); 2338 } 2339 2340 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) 2341 { 2342 u32 reg_mask; 2343 2344 if (sc_xo) 2345 reg_mask = B_AX_XTAL_SC_XO_MASK; 2346 else 2347 reg_mask = B_AX_XTAL_SC_XI_MASK; 2348 2349 return (u8)rtw89_read32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask); 2350 } 2351 2352 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, 2353 u8 val) 2354 { 2355 u32 reg_mask; 2356 2357 if (sc_xo) 2358 reg_mask = B_AX_XTAL_SC_XO_MASK; 2359 else 2360 reg_mask = B_AX_XTAL_SC_XI_MASK; 2361 2362 rtw89_write32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask, val); 2363 } 2364 2365 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, 2366 u8 crystal_cap, bool force) 2367 { 2368 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2369 const struct rtw89_chip_info *chip = rtwdev->chip; 2370 u8 sc_xi_val, sc_xo_val; 2371 2372 if (!force && cfo->crystal_cap == crystal_cap) 2373 return; 2374 crystal_cap = clamp_t(u8, crystal_cap, 0, 127); 2375 if (chip->chip_id == RTL8852A) { 2376 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); 2377 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); 2378 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); 2379 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); 2380 } else { 2381 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, 2382 crystal_cap, XTAL_SC_XO_MASK); 2383 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, 2384 crystal_cap, XTAL_SC_XI_MASK); 2385 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val); 2386 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val); 2387 } 2388 cfo->crystal_cap = sc_xi_val; 2389 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); 2390 2391 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); 2392 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); 2393 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", 2394 cfo->x_cap_ofst); 2395 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); 2396 } 2397 2398 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) 2399 { 2400 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2401 u8 cap; 2402 2403 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; 2404 cfo->is_adjust = false; 2405 if (cfo->crystal_cap == cfo->def_x_cap) 2406 return; 2407 cap = cfo->crystal_cap; 2408 cap += (cap > cfo->def_x_cap ? -1 : 1); 2409 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); 2410 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2411 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, 2412 cfo->def_x_cap); 2413 } 2414 2415 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) 2416 { 2417 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp; 2418 bool is_linked = rtwdev->total_sta_assoc > 0; 2419 s32 cfo_avg_312; 2420 s32 dcfo_comp_val; 2421 int sign; 2422 2423 if (!is_linked) { 2424 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", 2425 is_linked); 2426 return; 2427 } 2428 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); 2429 if (curr_cfo == 0) 2430 return; 2431 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); 2432 sign = curr_cfo > 0 ? 1 : -1; 2433 cfo_avg_312 = curr_cfo / 625 + sign * dcfo_comp_val; 2434 rtw89_debug(rtwdev, RTW89_DBG_CFO, "avg_cfo_312=%d step\n", cfo_avg_312); 2435 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 2436 cfo_avg_312 = -cfo_avg_312; 2437 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask, 2438 cfo_avg_312); 2439 } 2440 2441 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) 2442 { 2443 const struct rtw89_chip_info *chip = rtwdev->chip; 2444 2445 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_OPT, B_DCFO_OPT_EN, 1); 2446 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_WEIGHT, B_DCFO_WEIGHT_MSK, 8); 2447 2448 if (chip->cfo_hw_comp) 2449 rtw89_write32_mask(rtwdev, R_AX_PWR_UL_CTRL2, 2450 B_AX_PWR_UL_CFO_MASK, 0x6); 2451 else 2452 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, B_AX_PWR_UL_CFO_MASK); 2453 } 2454 2455 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) 2456 { 2457 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2458 struct rtw89_efuse *efuse = &rtwdev->efuse; 2459 2460 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; 2461 cfo->crystal_cap = cfo->crystal_cap_default; 2462 cfo->def_x_cap = cfo->crystal_cap; 2463 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f); 2464 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1); 2465 cfo->is_adjust = false; 2466 cfo->divergence_lock_en = false; 2467 cfo->x_cap_ofst = 0; 2468 cfo->lock_cnt = 0; 2469 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; 2470 cfo->apply_compensation = false; 2471 cfo->residual_cfo_acc = 0; 2472 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", 2473 cfo->crystal_cap_default); 2474 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); 2475 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); 2476 rtw89_dcfo_comp_init(rtwdev); 2477 cfo->cfo_timer_ms = 2000; 2478 cfo->cfo_trig_by_timer_en = false; 2479 cfo->phy_cfo_trk_cnt = 0; 2480 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2481 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE; 2482 } 2483 2484 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, 2485 s32 curr_cfo) 2486 { 2487 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2488 s8 crystal_cap = cfo->crystal_cap; 2489 s32 cfo_abs = abs(curr_cfo); 2490 int sign; 2491 2492 if (!cfo->is_adjust) { 2493 if (cfo_abs > CFO_TRK_ENABLE_TH) 2494 cfo->is_adjust = true; 2495 } else { 2496 if (cfo_abs < CFO_TRK_STOP_TH) 2497 cfo->is_adjust = false; 2498 } 2499 if (!cfo->is_adjust) { 2500 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); 2501 return; 2502 } 2503 sign = curr_cfo > 0 ? 1 : -1; 2504 if (cfo_abs > CFO_TRK_STOP_TH_4) 2505 crystal_cap += 7 * sign; 2506 else if (cfo_abs > CFO_TRK_STOP_TH_3) 2507 crystal_cap += 5 * sign; 2508 else if (cfo_abs > CFO_TRK_STOP_TH_2) 2509 crystal_cap += 3 * sign; 2510 else if (cfo_abs > CFO_TRK_STOP_TH_1) 2511 crystal_cap += 1 * sign; 2512 else 2513 return; 2514 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); 2515 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2516 "X_cap{Curr,Default}={0x%x,0x%x}\n", 2517 cfo->crystal_cap, cfo->def_x_cap); 2518 } 2519 2520 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) 2521 { 2522 const struct rtw89_chip_info *chip = rtwdev->chip; 2523 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2524 s32 cfo_khz_all = 0; 2525 s32 cfo_cnt_all = 0; 2526 s32 cfo_all_avg = 0; 2527 u8 i; 2528 2529 if (rtwdev->total_sta_assoc != 1) 2530 return 0; 2531 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); 2532 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2533 if (cfo->cfo_cnt[i] == 0) 2534 continue; 2535 cfo_khz_all += cfo->cfo_tail[i]; 2536 cfo_cnt_all += cfo->cfo_cnt[i]; 2537 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); 2538 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2539 cfo->dcfo_avg = phy_div(cfo_khz_all << chip->dcfo_comp_sft, 2540 cfo_cnt_all); 2541 } 2542 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2543 "CFO track for macid = %d\n", i); 2544 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2545 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", 2546 cfo_khz_all, cfo_cnt_all, cfo_all_avg); 2547 return cfo_all_avg; 2548 } 2549 2550 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) 2551 { 2552 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2553 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2554 s32 target_cfo = 0; 2555 s32 cfo_khz_all = 0; 2556 s32 cfo_khz_all_tp_wgt = 0; 2557 s32 cfo_avg = 0; 2558 s32 max_cfo_lb = BIT(31); 2559 s32 min_cfo_ub = GENMASK(30, 0); 2560 u16 cfo_cnt_all = 0; 2561 u8 active_entry_cnt = 0; 2562 u8 sta_cnt = 0; 2563 u32 tp_all = 0; 2564 u8 i; 2565 u8 cfo_tol = 0; 2566 2567 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); 2568 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { 2569 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); 2570 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2571 if (cfo->cfo_cnt[i] == 0) 2572 continue; 2573 cfo_khz_all += cfo->cfo_tail[i]; 2574 cfo_cnt_all += cfo->cfo_cnt[i]; 2575 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); 2576 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2577 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", 2578 cfo_khz_all, cfo_cnt_all, cfo_avg); 2579 target_cfo = cfo_avg; 2580 } 2581 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { 2582 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); 2583 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2584 if (cfo->cfo_cnt[i] == 0) 2585 continue; 2586 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2587 (s32)cfo->cfo_cnt[i]); 2588 cfo_khz_all += cfo->cfo_avg[i]; 2589 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2590 "Macid=%d, cfo_avg=%d\n", i, 2591 cfo->cfo_avg[i]); 2592 } 2593 sta_cnt = rtwdev->total_sta_assoc; 2594 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); 2595 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2596 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", 2597 cfo_khz_all, sta_cnt, cfo_avg); 2598 target_cfo = cfo_avg; 2599 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { 2600 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); 2601 cfo_tol = cfo->sta_cfo_tolerance; 2602 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2603 sta_cnt++; 2604 if (cfo->cfo_cnt[i] != 0) { 2605 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2606 (s32)cfo->cfo_cnt[i]); 2607 active_entry_cnt++; 2608 } else { 2609 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; 2610 } 2611 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); 2612 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); 2613 cfo_khz_all += cfo->cfo_avg[i]; 2614 /* need tp for each entry */ 2615 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2616 "[%d] cfo_avg=%d, tp=tbd\n", 2617 i, cfo->cfo_avg[i]); 2618 if (sta_cnt >= rtwdev->total_sta_assoc) 2619 break; 2620 } 2621 tp_all = stats->rx_throughput; /* need tp for each entry */ 2622 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); 2623 2624 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", 2625 sta_cnt); 2626 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", 2627 active_entry_cnt); 2628 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2629 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", 2630 cfo_khz_all_tp_wgt, cfo_avg); 2631 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", 2632 max_cfo_lb, min_cfo_ub); 2633 if (max_cfo_lb <= min_cfo_ub) { 2634 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2635 "cfo win_size=%d\n", 2636 min_cfo_ub - max_cfo_lb); 2637 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); 2638 } else { 2639 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2640 "No intersection of cfo tolerance windows\n"); 2641 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); 2642 } 2643 for (i = 0; i < CFO_TRACK_MAX_USER; i++) 2644 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2645 } 2646 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); 2647 return target_cfo; 2648 } 2649 2650 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) 2651 { 2652 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2653 2654 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); 2655 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); 2656 cfo->packet_count = 0; 2657 cfo->packet_count_pre = 0; 2658 cfo->cfo_avg_pre = 0; 2659 } 2660 2661 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) 2662 { 2663 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2664 s32 new_cfo = 0; 2665 bool x_cap_update = false; 2666 u8 pre_x_cap = cfo->crystal_cap; 2667 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft; 2668 2669 cfo->dcfo_avg = 0; 2670 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", 2671 rtwdev->total_sta_assoc); 2672 if (rtwdev->total_sta_assoc == 0) { 2673 rtw89_phy_cfo_reset(rtwdev); 2674 return; 2675 } 2676 if (cfo->packet_count == 0) { 2677 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); 2678 return; 2679 } 2680 if (cfo->packet_count == cfo->packet_count_pre) { 2681 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); 2682 return; 2683 } 2684 if (rtwdev->total_sta_assoc == 1) 2685 new_cfo = rtw89_phy_average_cfo_calc(rtwdev); 2686 else 2687 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); 2688 if (new_cfo == 0) { 2689 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); 2690 return; 2691 } 2692 if (cfo->divergence_lock_en) { 2693 cfo->lock_cnt++; 2694 if (cfo->lock_cnt > CFO_PERIOD_CNT) { 2695 cfo->divergence_lock_en = false; 2696 cfo->lock_cnt = 0; 2697 } else { 2698 rtw89_phy_cfo_reset(rtwdev); 2699 } 2700 return; 2701 } 2702 if (cfo->crystal_cap >= cfo->x_cap_ub || 2703 cfo->crystal_cap <= cfo->x_cap_lb) { 2704 cfo->divergence_lock_en = true; 2705 rtw89_phy_cfo_reset(rtwdev); 2706 return; 2707 } 2708 2709 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); 2710 cfo->cfo_avg_pre = new_cfo; 2711 cfo->dcfo_avg_pre = cfo->dcfo_avg; 2712 x_cap_update = cfo->crystal_cap != pre_x_cap; 2713 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); 2714 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", 2715 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, 2716 cfo->x_cap_ofst); 2717 if (x_cap_update) { 2718 if (cfo->dcfo_avg > 0) 2719 cfo->dcfo_avg -= CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft; 2720 else 2721 cfo->dcfo_avg += CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft; 2722 } 2723 rtw89_dcfo_comp(rtwdev, cfo->dcfo_avg); 2724 rtw89_phy_cfo_statistics_reset(rtwdev); 2725 } 2726 2727 void rtw89_phy_cfo_track_work(struct work_struct *work) 2728 { 2729 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2730 cfo_track_work.work); 2731 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2732 2733 mutex_lock(&rtwdev->mutex); 2734 if (!cfo->cfo_trig_by_timer_en) 2735 goto out; 2736 rtw89_leave_ps_mode(rtwdev); 2737 rtw89_phy_cfo_dm(rtwdev); 2738 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2739 msecs_to_jiffies(cfo->cfo_timer_ms)); 2740 out: 2741 mutex_unlock(&rtwdev->mutex); 2742 } 2743 2744 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) 2745 { 2746 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2747 2748 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2749 msecs_to_jiffies(cfo->cfo_timer_ms)); 2750 } 2751 2752 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) 2753 { 2754 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2755 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2756 bool is_ul_ofdma = false, ofdma_acc_en = false; 2757 2758 if (stats->rx_tf_periodic > CFO_TF_CNT_TH) 2759 is_ul_ofdma = true; 2760 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE && 2761 is_ul_ofdma) 2762 ofdma_acc_en = true; 2763 2764 switch (cfo->phy_cfo_status) { 2765 case RTW89_PHY_DCFO_STATE_NORMAL: 2766 if (stats->tx_throughput >= CFO_TP_UPPER) { 2767 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; 2768 cfo->cfo_trig_by_timer_en = true; 2769 cfo->cfo_timer_ms = CFO_COMP_PERIOD; 2770 rtw89_phy_cfo_start_work(rtwdev); 2771 } 2772 break; 2773 case RTW89_PHY_DCFO_STATE_ENHANCE: 2774 if (stats->tx_throughput <= CFO_TP_LOWER) 2775 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2776 else if (ofdma_acc_en && 2777 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) 2778 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD; 2779 else 2780 cfo->phy_cfo_trk_cnt++; 2781 2782 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) { 2783 cfo->phy_cfo_trk_cnt = 0; 2784 cfo->cfo_trig_by_timer_en = false; 2785 } 2786 break; 2787 case RTW89_PHY_DCFO_STATE_HOLD: 2788 if (stats->tx_throughput <= CFO_TP_LOWER) { 2789 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2790 cfo->phy_cfo_trk_cnt = 0; 2791 cfo->cfo_trig_by_timer_en = false; 2792 } else { 2793 cfo->phy_cfo_trk_cnt++; 2794 } 2795 break; 2796 default: 2797 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2798 cfo->phy_cfo_trk_cnt = 0; 2799 break; 2800 } 2801 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2802 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", 2803 stats->tx_throughput, cfo->phy_cfo_status, 2804 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, 2805 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); 2806 if (cfo->cfo_trig_by_timer_en) 2807 return; 2808 rtw89_phy_cfo_dm(rtwdev); 2809 } 2810 2811 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 2812 struct rtw89_rx_phy_ppdu *phy_ppdu) 2813 { 2814 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2815 u8 macid = phy_ppdu->mac_id; 2816 2817 if (macid >= CFO_TRACK_MAX_USER) { 2818 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid); 2819 return; 2820 } 2821 2822 cfo->cfo_tail[macid] += cfo_val; 2823 cfo->cfo_cnt[macid]++; 2824 cfo->packet_count++; 2825 } 2826 2827 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2828 { 2829 const struct rtw89_chip_info *chip = rtwdev->chip; 2830 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 2831 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 2832 2833 if (!chip->support_ul_tb_ctrl) 2834 return; 2835 2836 rtwvif->def_tri_idx = 2837 rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG); 2838 2839 if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV) 2840 rtwvif->dyn_tb_bedge_en = false; 2841 else if (chan->band_type >= RTW89_BAND_5G && 2842 chan->band_width >= RTW89_CHANNEL_WIDTH_40) 2843 rtwvif->dyn_tb_bedge_en = true; 2844 else 2845 rtwvif->dyn_tb_bedge_en = false; 2846 2847 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2848 "[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n", 2849 ul_tb_info->def_if_bandedge, rtwvif->def_tri_idx); 2850 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2851 "[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n", 2852 rtwvif->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en); 2853 } 2854 2855 struct rtw89_phy_ul_tb_check_data { 2856 bool valid; 2857 bool high_tf_client; 2858 bool low_tf_client; 2859 bool dyn_tb_bedge_en; 2860 u8 def_tri_idx; 2861 }; 2862 2863 static 2864 void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev, 2865 struct rtw89_vif *rtwvif, 2866 struct rtw89_phy_ul_tb_check_data *ul_tb_data) 2867 { 2868 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2869 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2870 2871 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 2872 return; 2873 2874 if (!vif->cfg.assoc) 2875 return; 2876 2877 if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH) 2878 ul_tb_data->high_tf_client = true; 2879 else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH) 2880 ul_tb_data->low_tf_client = true; 2881 2882 ul_tb_data->valid = true; 2883 ul_tb_data->def_tri_idx = rtwvif->def_tri_idx; 2884 ul_tb_data->dyn_tb_bedge_en = rtwvif->dyn_tb_bedge_en; 2885 } 2886 2887 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev) 2888 { 2889 const struct rtw89_chip_info *chip = rtwdev->chip; 2890 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 2891 struct rtw89_phy_ul_tb_check_data ul_tb_data = {}; 2892 struct rtw89_vif *rtwvif; 2893 2894 if (!chip->support_ul_tb_ctrl) 2895 return; 2896 2897 if (rtwdev->total_sta_assoc != 1) 2898 return; 2899 2900 rtw89_for_each_rtwvif(rtwdev, rtwvif) 2901 rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif, &ul_tb_data); 2902 2903 if (!ul_tb_data.valid) 2904 return; 2905 2906 if (ul_tb_data.dyn_tb_bedge_en) { 2907 if (ul_tb_data.high_tf_client) { 2908 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0); 2909 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2910 "[ULTB] Turn off if_bandedge\n"); 2911 } else if (ul_tb_data.low_tf_client) { 2912 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 2913 ul_tb_info->def_if_bandedge); 2914 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2915 "[ULTB] Set to default if_bandedge = %d\n", 2916 ul_tb_info->def_if_bandedge); 2917 } 2918 } 2919 2920 if (ul_tb_info->dyn_tb_tri_en) { 2921 if (ul_tb_data.high_tf_client) { 2922 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 2923 B_TXSHAPE_TRIANGULAR_CFG, 0); 2924 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2925 "[ULTB] Turn off Tx triangle\n"); 2926 } else if (ul_tb_data.low_tf_client) { 2927 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 2928 B_TXSHAPE_TRIANGULAR_CFG, 2929 ul_tb_data.def_tri_idx); 2930 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2931 "[ULTB] Set to default tx_shap_idx = %d\n", 2932 ul_tb_data.def_tri_idx); 2933 } 2934 } 2935 } 2936 2937 static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev) 2938 { 2939 const struct rtw89_chip_info *chip = rtwdev->chip; 2940 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 2941 2942 if (!chip->support_ul_tb_ctrl) 2943 return; 2944 2945 ul_tb_info->dyn_tb_tri_en = true; 2946 ul_tb_info->def_if_bandedge = 2947 rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN); 2948 } 2949 2950 static 2951 void rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats *antdiv_sts) 2952 { 2953 ewma_rssi_init(&antdiv_sts->cck_rssi_avg); 2954 ewma_rssi_init(&antdiv_sts->ofdm_rssi_avg); 2955 ewma_rssi_init(&antdiv_sts->non_legacy_rssi_avg); 2956 antdiv_sts->pkt_cnt_cck = 0; 2957 antdiv_sts->pkt_cnt_ofdm = 0; 2958 antdiv_sts->pkt_cnt_non_legacy = 0; 2959 } 2960 2961 static void rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev *rtwdev, 2962 struct rtw89_rx_phy_ppdu *phy_ppdu, 2963 struct rtw89_antdiv_stats *stats) 2964 { 2965 if (GET_DATA_RATE_MODE(phy_ppdu->rate) == DATA_RATE_MODE_NON_HT) { 2966 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) { 2967 ewma_rssi_add(&stats->cck_rssi_avg, phy_ppdu->rssi_avg); 2968 stats->pkt_cnt_cck++; 2969 } else { 2970 ewma_rssi_add(&stats->ofdm_rssi_avg, phy_ppdu->rssi_avg); 2971 stats->pkt_cnt_ofdm++; 2972 } 2973 } else { 2974 ewma_rssi_add(&stats->non_legacy_rssi_avg, phy_ppdu->rssi_avg); 2975 stats->pkt_cnt_non_legacy++; 2976 } 2977 } 2978 2979 static u8 rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats *stats) 2980 { 2981 if (stats->pkt_cnt_non_legacy >= stats->pkt_cnt_cck && 2982 stats->pkt_cnt_non_legacy >= stats->pkt_cnt_ofdm) 2983 return ewma_rssi_read(&stats->non_legacy_rssi_avg); 2984 else if (stats->pkt_cnt_ofdm >= stats->pkt_cnt_cck && 2985 stats->pkt_cnt_ofdm >= stats->pkt_cnt_non_legacy) 2986 return ewma_rssi_read(&stats->ofdm_rssi_avg); 2987 else 2988 return ewma_rssi_read(&stats->cck_rssi_avg); 2989 } 2990 2991 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev, 2992 struct rtw89_rx_phy_ppdu *phy_ppdu) 2993 { 2994 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 2995 struct rtw89_hal *hal = &rtwdev->hal; 2996 2997 if (!hal->ant_diversity || hal->ant_diversity_fixed) 2998 return; 2999 3000 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->target_stats); 3001 3002 if (!antdiv->get_stats) 3003 return; 3004 3005 if (hal->antenna_rx == RF_A) 3006 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->main_stats); 3007 else if (hal->antenna_rx == RF_B) 3008 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->aux_stats); 3009 } 3010 3011 static void rtw89_phy_antdiv_reg_init(struct rtw89_dev *rtwdev) 3012 { 3013 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_ANT_TRAIN_EN, 3014 0x0, RTW89_PHY_0); 3015 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_TX_ANT_SEL, 3016 0x0, RTW89_PHY_0); 3017 3018 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_TRSW_TX_EXTEND, 3019 0x0, RTW89_PHY_0); 3020 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_HW_ANTSW_DIS_BY_GNT_BT, 3021 0x0, RTW89_PHY_0); 3022 3023 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_BT_FORCE_ANTIDX_EN, 3024 0x0, RTW89_PHY_0); 3025 3026 rtw89_phy_write32_idx(rtwdev, R_RFSW_CTRL_ANT0_BASE, B_RFSW_CTRL_ANT_MAPPING, 3027 0x0100, RTW89_PHY_0); 3028 3029 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_BTG_TRX, 3030 0x1, RTW89_PHY_0); 3031 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_HW_CTRL, 3032 0x0, RTW89_PHY_0); 3033 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_2G, 3034 0x0, RTW89_PHY_0); 3035 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_5G, 3036 0x0, RTW89_PHY_0); 3037 } 3038 3039 static void rtw89_phy_antdiv_sts_reset(struct rtw89_dev *rtwdev) 3040 { 3041 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 3042 3043 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats); 3044 rtw89_phy_antdiv_sts_instance_reset(&antdiv->main_stats); 3045 rtw89_phy_antdiv_sts_instance_reset(&antdiv->aux_stats); 3046 } 3047 3048 static void rtw89_phy_antdiv_init(struct rtw89_dev *rtwdev) 3049 { 3050 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 3051 struct rtw89_hal *hal = &rtwdev->hal; 3052 3053 if (!hal->ant_diversity) 3054 return; 3055 3056 antdiv->get_stats = false; 3057 antdiv->rssi_pre = 0; 3058 rtw89_phy_antdiv_sts_reset(rtwdev); 3059 rtw89_phy_antdiv_reg_init(rtwdev); 3060 } 3061 3062 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) 3063 { 3064 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 3065 int i; 3066 u8 th; 3067 3068 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 3069 th = rtw89_chip_get_thermal(rtwdev, i); 3070 if (th) 3071 ewma_thermal_add(&phystat->avg_thermal[i], th); 3072 3073 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 3074 "path(%d) thermal cur=%u avg=%ld", i, th, 3075 ewma_thermal_read(&phystat->avg_thermal[i])); 3076 } 3077 } 3078 3079 struct rtw89_phy_iter_rssi_data { 3080 struct rtw89_dev *rtwdev; 3081 struct rtw89_phy_ch_info *ch_info; 3082 bool rssi_changed; 3083 }; 3084 3085 static void rtw89_phy_stat_rssi_update_iter(void *data, 3086 struct ieee80211_sta *sta) 3087 { 3088 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3089 struct rtw89_phy_iter_rssi_data *rssi_data = 3090 (struct rtw89_phy_iter_rssi_data *)data; 3091 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info; 3092 unsigned long rssi_curr; 3093 3094 rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi); 3095 3096 if (rssi_curr < ch_info->rssi_min) { 3097 ch_info->rssi_min = rssi_curr; 3098 ch_info->rssi_min_macid = rtwsta->mac_id; 3099 } 3100 3101 if (rtwsta->prev_rssi == 0) { 3102 rtwsta->prev_rssi = rssi_curr; 3103 } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) { 3104 rtwsta->prev_rssi = rssi_curr; 3105 rssi_data->rssi_changed = true; 3106 } 3107 } 3108 3109 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) 3110 { 3111 struct rtw89_phy_iter_rssi_data rssi_data = {0}; 3112 3113 rssi_data.rtwdev = rtwdev; 3114 rssi_data.ch_info = &rtwdev->ch_info; 3115 rssi_data.ch_info->rssi_min = U8_MAX; 3116 ieee80211_iterate_stations_atomic(rtwdev->hw, 3117 rtw89_phy_stat_rssi_update_iter, 3118 &rssi_data); 3119 if (rssi_data.rssi_changed) 3120 rtw89_btc_ntfy_wl_sta(rtwdev); 3121 } 3122 3123 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) 3124 { 3125 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 3126 int i; 3127 3128 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 3129 ewma_thermal_init(&phystat->avg_thermal[i]); 3130 3131 rtw89_phy_stat_thermal_update(rtwdev); 3132 3133 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 3134 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); 3135 } 3136 3137 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) 3138 { 3139 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 3140 3141 rtw89_phy_stat_thermal_update(rtwdev); 3142 rtw89_phy_stat_rssi_update(rtwdev); 3143 3144 phystat->last_pkt_stat = phystat->cur_pkt_stat; 3145 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 3146 } 3147 3148 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us) 3149 { 3150 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3151 3152 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 3153 } 3154 3155 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) 3156 { 3157 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3158 3159 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 3160 } 3161 3162 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) 3163 { 3164 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3165 3166 env->ccx_manual_ctrl = false; 3167 env->ccx_ongoing = false; 3168 env->ccx_rac_lv = RTW89_RAC_RELEASE; 3169 env->ccx_rpt_stamp = 0; 3170 env->ccx_period = 0; 3171 env->ccx_unit_idx = RTW89_CCX_32_US; 3172 env->ccx_trigger_time = 0; 3173 env->ccx_edcca_opt_bw_idx = RTW89_CCX_EDCCA_BW20_0; 3174 3175 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1); 3176 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1); 3177 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 3178 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EDCCA_OPT_MSK, 3179 RTW89_CCX_EDCCA_BW20_0); 3180 } 3181 3182 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report, 3183 u16 score) 3184 { 3185 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3186 u32 numer = 0; 3187 u16 ret = 0; 3188 3189 numer = report * score + (env->ccx_period >> 1); 3190 if (env->ccx_period) 3191 ret = numer / env->ccx_period; 3192 3193 return ret >= score ? score - 1 : ret; 3194 } 3195 3196 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, 3197 u16 time_ms, u32 *period, 3198 u32 *unit_idx) 3199 { 3200 u32 idx; 3201 u8 quotient; 3202 3203 if (time_ms >= CCX_MAX_PERIOD) 3204 time_ms = CCX_MAX_PERIOD; 3205 3206 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; 3207 3208 if (quotient < 4) 3209 idx = RTW89_CCX_4_US; 3210 else if (quotient < 8) 3211 idx = RTW89_CCX_8_US; 3212 else if (quotient < 16) 3213 idx = RTW89_CCX_16_US; 3214 else 3215 idx = RTW89_CCX_32_US; 3216 3217 *unit_idx = idx; 3218 *period = (time_ms * MS_TO_4US_RATIO) >> idx; 3219 3220 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3221 "[Trigger Time] period:%d, unit_idx:%d\n", 3222 *period, *unit_idx); 3223 } 3224 3225 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev) 3226 { 3227 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3228 3229 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3230 "lv:(%d)->(0)\n", env->ccx_rac_lv); 3231 3232 env->ccx_ongoing = false; 3233 env->ccx_rac_lv = RTW89_RAC_RELEASE; 3234 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3235 } 3236 3237 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, 3238 struct rtw89_ccx_para_info *para) 3239 { 3240 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3241 bool is_update = env->ifs_clm_app != para->ifs_clm_app; 3242 u8 i = 0; 3243 u16 *ifs_th_l = env->ifs_clm_th_l; 3244 u16 *ifs_th_h = env->ifs_clm_th_h; 3245 u32 ifs_th0_us = 0, ifs_th_times = 0; 3246 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; 3247 3248 if (!is_update) 3249 goto ifs_update_finished; 3250 3251 switch (para->ifs_clm_app) { 3252 case RTW89_IFS_CLM_INIT: 3253 case RTW89_IFS_CLM_BACKGROUND: 3254 case RTW89_IFS_CLM_ACS: 3255 case RTW89_IFS_CLM_DBG: 3256 case RTW89_IFS_CLM_DIG: 3257 case RTW89_IFS_CLM_TDMA_DIG: 3258 ifs_th0_us = IFS_CLM_TH0_UPPER; 3259 ifs_th_times = IFS_CLM_TH_MUL; 3260 break; 3261 case RTW89_IFS_CLM_DBG_MANUAL: 3262 ifs_th0_us = para->ifs_clm_manual_th0; 3263 ifs_th_times = para->ifs_clm_manual_th_times; 3264 break; 3265 default: 3266 break; 3267 } 3268 3269 /* Set sampling threshold for 4 different regions, unit in idx_cnt. 3270 * low[i] = high[i-1] + 1 3271 * high[i] = high[i-1] * ifs_th_times 3272 */ 3273 ifs_th_l[IFS_CLM_TH_START_IDX] = 0; 3274 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; 3275 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, 3276 ifs_th0_us); 3277 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { 3278 ifs_th_l[i] = ifs_th_h[i - 1] + 1; 3279 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; 3280 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]); 3281 } 3282 3283 ifs_update_finished: 3284 if (!is_update) 3285 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3286 "No need to update IFS_TH\n"); 3287 3288 return is_update; 3289 } 3290 3291 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) 3292 { 3293 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3294 u8 i = 0; 3295 3296 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_LOW_MSK, 3297 env->ifs_clm_th_l[0]); 3298 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_LOW_MSK, 3299 env->ifs_clm_th_l[1]); 3300 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_LOW_MSK, 3301 env->ifs_clm_th_l[2]); 3302 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_LOW_MSK, 3303 env->ifs_clm_th_l[3]); 3304 3305 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_HIGH_MSK, 3306 env->ifs_clm_th_h[0]); 3307 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_HIGH_MSK, 3308 env->ifs_clm_th_h[1]); 3309 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_HIGH_MSK, 3310 env->ifs_clm_th_h[2]); 3311 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_HIGH_MSK, 3312 env->ifs_clm_th_h[3]); 3313 3314 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3315 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3316 "Update IFS_T%d_th{low, high} : {%d, %d}\n", 3317 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 3318 } 3319 3320 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) 3321 { 3322 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3323 struct rtw89_ccx_para_info para = {0}; 3324 3325 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3326 env->ifs_clm_mntr_time = 0; 3327 3328 para.ifs_clm_app = RTW89_IFS_CLM_INIT; 3329 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) 3330 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 3331 3332 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COLLECT_EN, 3333 true); 3334 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_EN_MSK, true); 3335 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_EN_MSK, true); 3336 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_EN_MSK, true); 3337 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_EN_MSK, true); 3338 } 3339 3340 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, 3341 enum rtw89_env_racing_lv level) 3342 { 3343 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3344 int ret = 0; 3345 3346 if (level >= RTW89_RAC_MAX_NUM) { 3347 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3348 "[WARNING] Wrong LV=%d\n", level); 3349 return -EINVAL; 3350 } 3351 3352 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3353 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, 3354 env->ccx_rac_lv, level); 3355 3356 if (env->ccx_ongoing) { 3357 if (level <= env->ccx_rac_lv) 3358 ret = -EINVAL; 3359 else 3360 env->ccx_ongoing = false; 3361 } 3362 3363 if (ret == 0) 3364 env->ccx_rac_lv = level; 3365 3366 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", 3367 !ret); 3368 3369 return ret; 3370 } 3371 3372 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) 3373 { 3374 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3375 3376 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 0); 3377 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 0); 3378 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1); 3379 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 3380 3381 env->ccx_rpt_stamp++; 3382 env->ccx_ongoing = true; 3383 } 3384 3385 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) 3386 { 3387 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3388 u8 i = 0; 3389 u32 res = 0; 3390 3391 env->ifs_clm_tx_ratio = 3392 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT); 3393 env->ifs_clm_edcca_excl_cca_ratio = 3394 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca, 3395 PERCENT); 3396 env->ifs_clm_cck_fa_ratio = 3397 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT); 3398 env->ifs_clm_ofdm_fa_ratio = 3399 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT); 3400 env->ifs_clm_cck_cca_excl_fa_ratio = 3401 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa, 3402 PERCENT); 3403 env->ifs_clm_ofdm_cca_excl_fa_ratio = 3404 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa, 3405 PERCENT); 3406 env->ifs_clm_cck_fa_permil = 3407 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL); 3408 env->ifs_clm_ofdm_fa_permil = 3409 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL); 3410 3411 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { 3412 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { 3413 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; 3414 } else { 3415 env->ifs_clm_ifs_avg[i] = 3416 rtw89_phy_ccx_idx_to_us(rtwdev, 3417 env->ifs_clm_avg[i]); 3418 } 3419 3420 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]); 3421 res += env->ifs_clm_his[i] >> 1; 3422 if (env->ifs_clm_his[i]) 3423 res /= env->ifs_clm_his[i]; 3424 else 3425 res = 0; 3426 env->ifs_clm_cca_avg[i] = res; 3427 } 3428 3429 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3430 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", 3431 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); 3432 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3433 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", 3434 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); 3435 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3436 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", 3437 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); 3438 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3439 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", 3440 env->ifs_clm_cck_cca_excl_fa_ratio, 3441 env->ifs_clm_ofdm_cca_excl_fa_ratio); 3442 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3443 "Time:[his, ifs_avg(us), cca_avg(us)]\n"); 3444 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3445 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 3446 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 3447 env->ifs_clm_cca_avg[i]); 3448 } 3449 3450 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) 3451 { 3452 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3453 u8 i = 0; 3454 3455 if (rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_DONE_MSK) == 0) { 3456 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3457 "Get IFS_CLM report Fail\n"); 3458 return false; 3459 } 3460 3461 env->ifs_clm_tx = 3462 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 3463 B_IFS_CLM_TX_CNT_MSK); 3464 env->ifs_clm_edcca_excl_cca = 3465 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 3466 B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK); 3467 env->ifs_clm_cckcca_excl_fa = 3468 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 3469 B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK); 3470 env->ifs_clm_ofdmcca_excl_fa = 3471 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 3472 B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK); 3473 env->ifs_clm_cckfa = 3474 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 3475 B_IFS_CLM_CCK_FA_MSK); 3476 env->ifs_clm_ofdmfa = 3477 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 3478 B_IFS_CLM_OFDM_FA_MSK); 3479 3480 env->ifs_clm_his[0] = 3481 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T1_HIS_MSK); 3482 env->ifs_clm_his[1] = 3483 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T2_HIS_MSK); 3484 env->ifs_clm_his[2] = 3485 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T3_HIS_MSK); 3486 env->ifs_clm_his[3] = 3487 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T4_HIS_MSK); 3488 3489 env->ifs_clm_avg[0] = 3490 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T1_AVG_MSK); 3491 env->ifs_clm_avg[1] = 3492 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T2_AVG_MSK); 3493 env->ifs_clm_avg[2] = 3494 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T3_AVG_MSK); 3495 env->ifs_clm_avg[3] = 3496 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T4_AVG_MSK); 3497 3498 env->ifs_clm_cca[0] = 3499 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T1_CCA_MSK); 3500 env->ifs_clm_cca[1] = 3501 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T2_CCA_MSK); 3502 env->ifs_clm_cca[2] = 3503 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T3_CCA_MSK); 3504 env->ifs_clm_cca[3] = 3505 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T4_CCA_MSK); 3506 3507 env->ifs_clm_total_ifs = 3508 rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_TOTAL_CNT_MSK); 3509 3510 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", 3511 env->ifs_clm_total_ifs); 3512 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3513 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", 3514 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); 3515 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3516 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", 3517 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); 3518 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3519 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", 3520 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); 3521 3522 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); 3523 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3524 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3525 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], 3526 env->ifs_clm_avg[i], env->ifs_clm_cca[i]); 3527 3528 rtw89_phy_ifs_clm_get_utility(rtwdev); 3529 3530 return true; 3531 } 3532 3533 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 3534 struct rtw89_ccx_para_info *para) 3535 { 3536 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3537 u32 period = 0; 3538 u32 unit_idx = 0; 3539 3540 if (para->mntr_time == 0) { 3541 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3542 "[WARN] MNTR_TIME is 0\n"); 3543 return -EINVAL; 3544 } 3545 3546 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv)) 3547 return -EINVAL; 3548 3549 if (para->mntr_time != env->ifs_clm_mntr_time) { 3550 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 3551 &period, &unit_idx); 3552 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 3553 B_IFS_CLM_PERIOD_MSK, period); 3554 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 3555 B_IFS_CLM_COUNTER_UNIT_MSK, unit_idx); 3556 3557 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3558 "Update IFS-CLM time ((%d)) -> ((%d))\n", 3559 env->ifs_clm_mntr_time, para->mntr_time); 3560 3561 env->ifs_clm_mntr_time = para->mntr_time; 3562 env->ccx_period = (u16)period; 3563 env->ccx_unit_idx = (u8)unit_idx; 3564 } 3565 3566 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) { 3567 env->ifs_clm_app = para->ifs_clm_app; 3568 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 3569 } 3570 3571 return 0; 3572 } 3573 3574 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) 3575 { 3576 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3577 struct rtw89_ccx_para_info para = {0}; 3578 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3579 3580 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3581 if (env->ccx_manual_ctrl) { 3582 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3583 "CCX in manual ctrl\n"); 3584 return; 3585 } 3586 3587 /* only ifs_clm for now */ 3588 if (rtw89_phy_ifs_clm_get_result(rtwdev)) 3589 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3590 3591 rtw89_phy_ccx_racing_release(rtwdev); 3592 para.mntr_time = 1900; 3593 para.rac_lv = RTW89_RAC_LV_1; 3594 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3595 3596 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0) 3597 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3598 if (chk_result) 3599 rtw89_phy_ccx_trigger(rtwdev); 3600 3601 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3602 "get_result=0x%x, chk_result:0x%x\n", 3603 env->ccx_watchdog_result, chk_result); 3604 } 3605 3606 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page) 3607 { 3608 if (*ie_page >= RTW89_PHYSTS_BITMAP_NUM || 3609 *ie_page == RTW89_RSVD_9) 3610 return false; 3611 else if (*ie_page > RTW89_RSVD_9) 3612 *ie_page -= 1; 3613 3614 return true; 3615 } 3616 3617 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) 3618 { 3619 static const u8 ie_page_shift = 2; 3620 3621 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); 3622 } 3623 3624 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, 3625 enum rtw89_phy_status_bitmap ie_page) 3626 { 3627 u32 addr; 3628 3629 if (!rtw89_physts_ie_page_valid(&ie_page)) 3630 return 0; 3631 3632 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3633 3634 return rtw89_phy_read32(rtwdev, addr); 3635 } 3636 3637 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, 3638 enum rtw89_phy_status_bitmap ie_page, 3639 u32 val) 3640 { 3641 const struct rtw89_chip_info *chip = rtwdev->chip; 3642 u32 addr; 3643 3644 if (!rtw89_physts_ie_page_valid(&ie_page)) 3645 return; 3646 3647 if (chip->chip_id == RTL8852A) 3648 val &= B_PHY_STS_BITMAP_MSK_52A; 3649 3650 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3651 rtw89_phy_write32(rtwdev, addr, val); 3652 } 3653 3654 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev, 3655 enum rtw89_phy_status_bitmap bitmap, 3656 enum rtw89_phy_status_ie_type ie, 3657 bool enable) 3658 { 3659 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap); 3660 3661 if (enable) 3662 val |= BIT(ie); 3663 else 3664 val &= ~BIT(ie); 3665 3666 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val); 3667 } 3668 3669 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, 3670 bool enable, 3671 enum rtw89_phy_idx phy_idx) 3672 { 3673 if (enable) { 3674 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3675 B_STS_DIS_TRIG_BY_FAIL); 3676 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3677 B_STS_DIS_TRIG_BY_BRK); 3678 } else { 3679 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3680 B_STS_DIS_TRIG_BY_FAIL); 3681 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3682 B_STS_DIS_TRIG_BY_BRK); 3683 } 3684 } 3685 3686 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev) 3687 { 3688 u8 i; 3689 3690 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0); 3691 3692 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { 3693 if (i >= RTW89_CCK_PKT) 3694 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3695 RTW89_PHYSTS_IE09_FTR_0, 3696 true); 3697 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) || 3698 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT)) 3699 continue; 3700 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3701 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A, 3702 true); 3703 } 3704 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT, 3705 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3706 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT, 3707 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3708 3709 /* force IE01 for channel index, only channel field is valid */ 3710 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT, 3711 RTW89_PHYSTS_IE01_CMN_OFDM, true); 3712 } 3713 3714 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) 3715 { 3716 const struct rtw89_chip_info *chip = rtwdev->chip; 3717 struct rtw89_dig_info *dig = &rtwdev->dig; 3718 const struct rtw89_phy_dig_gain_cfg *cfg; 3719 const char *msg; 3720 u8 i; 3721 s8 gain_base; 3722 s8 *gain_arr; 3723 u32 tmp; 3724 3725 switch (type) { 3726 case RTW89_DIG_GAIN_LNA_G: 3727 gain_arr = dig->lna_gain_g; 3728 gain_base = LNA0_GAIN; 3729 cfg = chip->dig_table->cfg_lna_g; 3730 msg = "lna_gain_g"; 3731 break; 3732 case RTW89_DIG_GAIN_TIA_G: 3733 gain_arr = dig->tia_gain_g; 3734 gain_base = TIA0_GAIN_G; 3735 cfg = chip->dig_table->cfg_tia_g; 3736 msg = "tia_gain_g"; 3737 break; 3738 case RTW89_DIG_GAIN_LNA_A: 3739 gain_arr = dig->lna_gain_a; 3740 gain_base = LNA0_GAIN; 3741 cfg = chip->dig_table->cfg_lna_a; 3742 msg = "lna_gain_a"; 3743 break; 3744 case RTW89_DIG_GAIN_TIA_A: 3745 gain_arr = dig->tia_gain_a; 3746 gain_base = TIA0_GAIN_A; 3747 cfg = chip->dig_table->cfg_tia_a; 3748 msg = "tia_gain_a"; 3749 break; 3750 default: 3751 return; 3752 } 3753 3754 for (i = 0; i < cfg->size; i++) { 3755 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr, 3756 cfg->table[i].mask); 3757 tmp >>= DIG_GAIN_SHIFT; 3758 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; 3759 gain_base += DIG_GAIN; 3760 3761 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", 3762 msg, i, gain_arr[i]); 3763 } 3764 } 3765 3766 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev) 3767 { 3768 struct rtw89_dig_info *dig = &rtwdev->dig; 3769 u32 tmp; 3770 u8 i; 3771 3772 if (!rtwdev->hal.support_igi) 3773 return; 3774 3775 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW, 3776 B_PATH0_IB_PKPW_MSK); 3777 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); 3778 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK, 3779 B_PATH0_IB_PBK_MSK); 3780 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", 3781 dig->ib_pkpwr, dig->ib_pbk); 3782 3783 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) 3784 rtw89_phy_dig_read_gain_table(rtwdev, i); 3785 } 3786 3787 static const u8 rssi_nolink = 22; 3788 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; 3789 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; 3790 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; 3791 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; 3792 3793 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev) 3794 { 3795 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 3796 struct rtw89_dig_info *dig = &rtwdev->dig; 3797 bool is_linked = rtwdev->total_sta_assoc > 0; 3798 3799 if (is_linked) { 3800 dig->igi_rssi = ch_info->rssi_min >> 1; 3801 } else { 3802 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); 3803 dig->igi_rssi = rssi_nolink; 3804 } 3805 } 3806 3807 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev) 3808 { 3809 struct rtw89_dig_info *dig = &rtwdev->dig; 3810 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3811 bool is_linked = rtwdev->total_sta_assoc > 0; 3812 const u16 *fa_th_src = NULL; 3813 3814 switch (chan->band_type) { 3815 case RTW89_BAND_2G: 3816 dig->lna_gain = dig->lna_gain_g; 3817 dig->tia_gain = dig->tia_gain_g; 3818 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; 3819 dig->force_gaincode_idx_en = false; 3820 dig->dyn_pd_th_en = true; 3821 break; 3822 case RTW89_BAND_5G: 3823 default: 3824 dig->lna_gain = dig->lna_gain_a; 3825 dig->tia_gain = dig->tia_gain_a; 3826 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; 3827 dig->force_gaincode_idx_en = true; 3828 dig->dyn_pd_th_en = true; 3829 break; 3830 } 3831 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); 3832 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); 3833 } 3834 3835 static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20; 3836 static const u8 igi_max_performance_mode = 0x5a; 3837 static const u8 dynamic_pd_threshold_max; 3838 3839 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev) 3840 { 3841 struct rtw89_dig_info *dig = &rtwdev->dig; 3842 3843 dig->cur_gaincode.lna_idx = LNA_IDX_MAX; 3844 dig->cur_gaincode.tia_idx = TIA_IDX_MAX; 3845 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; 3846 dig->force_gaincode.lna_idx = LNA_IDX_MAX; 3847 dig->force_gaincode.tia_idx = TIA_IDX_MAX; 3848 dig->force_gaincode.rxb_idx = RXB_IDX_MAX; 3849 3850 dig->dyn_igi_max = igi_max_performance_mode; 3851 dig->dyn_igi_min = dynamic_igi_min; 3852 dig->dyn_pd_th_max = dynamic_pd_threshold_max; 3853 dig->pd_low_th_ofst = pd_low_th_offset; 3854 dig->is_linked_pre = false; 3855 } 3856 3857 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) 3858 { 3859 rtw89_phy_dig_update_gain_para(rtwdev); 3860 rtw89_phy_dig_reset(rtwdev); 3861 } 3862 3863 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3864 { 3865 struct rtw89_dig_info *dig = &rtwdev->dig; 3866 u8 lna_idx; 3867 3868 if (rssi < dig->igi_rssi_th[0]) 3869 lna_idx = RTW89_DIG_GAIN_LNA_IDX6; 3870 else if (rssi < dig->igi_rssi_th[1]) 3871 lna_idx = RTW89_DIG_GAIN_LNA_IDX5; 3872 else if (rssi < dig->igi_rssi_th[2]) 3873 lna_idx = RTW89_DIG_GAIN_LNA_IDX4; 3874 else if (rssi < dig->igi_rssi_th[3]) 3875 lna_idx = RTW89_DIG_GAIN_LNA_IDX3; 3876 else if (rssi < dig->igi_rssi_th[4]) 3877 lna_idx = RTW89_DIG_GAIN_LNA_IDX2; 3878 else 3879 lna_idx = RTW89_DIG_GAIN_LNA_IDX1; 3880 3881 return lna_idx; 3882 } 3883 3884 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3885 { 3886 struct rtw89_dig_info *dig = &rtwdev->dig; 3887 u8 tia_idx; 3888 3889 if (rssi < dig->igi_rssi_th[0]) 3890 tia_idx = RTW89_DIG_GAIN_TIA_IDX1; 3891 else 3892 tia_idx = RTW89_DIG_GAIN_TIA_IDX0; 3893 3894 return tia_idx; 3895 } 3896 3897 #define IB_PBK_BASE 110 3898 #define WB_RSSI_BASE 10 3899 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3900 struct rtw89_agc_gaincode_set *set) 3901 { 3902 struct rtw89_dig_info *dig = &rtwdev->dig; 3903 s8 lna_gain = dig->lna_gain[set->lna_idx]; 3904 s8 tia_gain = dig->tia_gain[set->tia_idx]; 3905 s32 wb_rssi = rssi + lna_gain + tia_gain; 3906 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; 3907 u8 rxb_idx; 3908 3909 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; 3910 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); 3911 3912 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", 3913 wb_rssi, rxb_idx_tmp); 3914 3915 return rxb_idx; 3916 } 3917 3918 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3919 struct rtw89_agc_gaincode_set *set) 3920 { 3921 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi); 3922 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi); 3923 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set); 3924 3925 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3926 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", 3927 rssi, set->lna_idx, set->tia_idx, set->rxb_idx); 3928 } 3929 3930 #define IGI_OFFSET_MAX 25 3931 #define IGI_OFFSET_MUL 2 3932 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev) 3933 { 3934 struct rtw89_dig_info *dig = &rtwdev->dig; 3935 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3936 enum rtw89_dig_noisy_level noisy_lv; 3937 u8 igi_offset = dig->fa_rssi_ofst; 3938 u16 fa_ratio = 0; 3939 3940 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; 3941 3942 if (fa_ratio < dig->fa_th[0]) 3943 noisy_lv = RTW89_DIG_NOISY_LEVEL0; 3944 else if (fa_ratio < dig->fa_th[1]) 3945 noisy_lv = RTW89_DIG_NOISY_LEVEL1; 3946 else if (fa_ratio < dig->fa_th[2]) 3947 noisy_lv = RTW89_DIG_NOISY_LEVEL2; 3948 else if (fa_ratio < dig->fa_th[3]) 3949 noisy_lv = RTW89_DIG_NOISY_LEVEL3; 3950 else 3951 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; 3952 3953 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) 3954 igi_offset = 0; 3955 else 3956 igi_offset += noisy_lv * IGI_OFFSET_MUL; 3957 3958 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); 3959 dig->fa_rssi_ofst = igi_offset; 3960 3961 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3962 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", 3963 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); 3964 3965 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3966 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", 3967 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, 3968 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, 3969 noisy_lv, igi_offset); 3970 } 3971 3972 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx) 3973 { 3974 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3975 3976 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_lna_init.addr, 3977 dig_regs->p0_lna_init.mask, lna_idx); 3978 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_lna_init.addr, 3979 dig_regs->p1_lna_init.mask, lna_idx); 3980 } 3981 3982 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx) 3983 { 3984 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3985 3986 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_tia_init.addr, 3987 dig_regs->p0_tia_init.mask, tia_idx); 3988 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_tia_init.addr, 3989 dig_regs->p1_tia_init.mask, tia_idx); 3990 } 3991 3992 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx) 3993 { 3994 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3995 3996 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_rxb_init.addr, 3997 dig_regs->p0_rxb_init.mask, rxb_idx); 3998 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_rxb_init.addr, 3999 dig_regs->p1_rxb_init.mask, rxb_idx); 4000 } 4001 4002 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, 4003 const struct rtw89_agc_gaincode_set set) 4004 { 4005 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx); 4006 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx); 4007 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx); 4008 4009 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", 4010 set.lna_idx, set.tia_idx, set.rxb_idx); 4011 } 4012 4013 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, 4014 bool enable) 4015 { 4016 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4017 4018 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_p20_pagcugc_en.addr, 4019 dig_regs->p0_p20_pagcugc_en.mask, enable); 4020 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_s20_pagcugc_en.addr, 4021 dig_regs->p0_s20_pagcugc_en.mask, enable); 4022 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_p20_pagcugc_en.addr, 4023 dig_regs->p1_p20_pagcugc_en.mask, enable); 4024 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_s20_pagcugc_en.addr, 4025 dig_regs->p1_s20_pagcugc_en.mask, enable); 4026 4027 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); 4028 } 4029 4030 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev) 4031 { 4032 struct rtw89_dig_info *dig = &rtwdev->dig; 4033 4034 if (!rtwdev->hal.support_igi) 4035 return; 4036 4037 if (dig->force_gaincode_idx_en) { 4038 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 4039 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4040 "Force gaincode index enabled.\n"); 4041 } else { 4042 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi, 4043 &dig->cur_gaincode); 4044 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode); 4045 } 4046 } 4047 4048 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, 4049 bool enable) 4050 { 4051 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 4052 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4053 enum rtw89_bandwidth cbw = chan->band_width; 4054 struct rtw89_dig_info *dig = &rtwdev->dig; 4055 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; 4056 u8 ofdm_cca_th; 4057 s8 cck_cca_th; 4058 u32 pd_val = 0; 4059 4060 under_region += PD_TH_SB_FLTR_CMP_VAL; 4061 4062 switch (cbw) { 4063 case RTW89_CHANNEL_WIDTH_40: 4064 under_region += PD_TH_BW40_CMP_VAL; 4065 break; 4066 case RTW89_CHANNEL_WIDTH_80: 4067 under_region += PD_TH_BW80_CMP_VAL; 4068 break; 4069 case RTW89_CHANNEL_WIDTH_160: 4070 under_region += PD_TH_BW160_CMP_VAL; 4071 break; 4072 case RTW89_CHANNEL_WIDTH_20: 4073 fallthrough; 4074 default: 4075 under_region += PD_TH_BW20_CMP_VAL; 4076 break; 4077 } 4078 4079 dig->dyn_pd_th_max = dig->igi_rssi; 4080 4081 final_rssi = min_t(u8, rssi, dig->igi_rssi); 4082 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, 4083 PD_TH_MAX_RSSI + under_region); 4084 4085 if (enable) { 4086 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1; 4087 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4088 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n", 4089 final_rssi, ofdm_cca_th, under_region, pd_val); 4090 } else { 4091 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4092 "Dynamic PD th disabled, Set PD_low_bd=0\n"); 4093 } 4094 4095 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 4096 dig_regs->pd_lower_bound_mask, pd_val); 4097 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 4098 dig_regs->pd_spatial_reuse_en, enable); 4099 4100 if (!rtwdev->hal.support_cckpd) 4101 return; 4102 4103 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI); 4104 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX); 4105 4106 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4107 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n", 4108 final_rssi, cck_cca_th, under_region, pd_val); 4109 4110 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_EN_V1, 4111 B_BMODE_PDTH_LIMIT_EN_MSK_V1, enable); 4112 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_V1, 4113 B_BMODE_PDTH_LOWER_BOUND_MSK_V1, pd_val); 4114 } 4115 4116 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) 4117 { 4118 struct rtw89_dig_info *dig = &rtwdev->dig; 4119 4120 dig->bypass_dig = false; 4121 rtw89_phy_dig_para_reset(rtwdev); 4122 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 4123 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false); 4124 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 4125 rtw89_phy_dig_update_para(rtwdev); 4126 } 4127 4128 #define IGI_RSSI_MIN 10 4129 void rtw89_phy_dig(struct rtw89_dev *rtwdev) 4130 { 4131 struct rtw89_dig_info *dig = &rtwdev->dig; 4132 bool is_linked = rtwdev->total_sta_assoc > 0; 4133 4134 if (unlikely(dig->bypass_dig)) { 4135 dig->bypass_dig = false; 4136 return; 4137 } 4138 4139 if (!dig->is_linked_pre && is_linked) { 4140 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); 4141 rtw89_phy_dig_update_para(rtwdev); 4142 } else if (dig->is_linked_pre && !is_linked) { 4143 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); 4144 rtw89_phy_dig_update_para(rtwdev); 4145 } 4146 dig->is_linked_pre = is_linked; 4147 4148 rtw89_phy_dig_igi_offset_by_env(rtwdev); 4149 rtw89_phy_dig_update_rssi_info(rtwdev); 4150 4151 dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ? 4152 dig->igi_rssi - IGI_RSSI_MIN : 0; 4153 dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX; 4154 dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst; 4155 4156 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, 4157 dig->dyn_igi_max); 4158 4159 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4160 "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n", 4161 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, 4162 dig->igi_fa_rssi); 4163 4164 rtw89_phy_dig_config_igi(rtwdev); 4165 4166 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en); 4167 4168 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) 4169 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true); 4170 else 4171 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 4172 } 4173 4174 static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta) 4175 { 4176 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 4177 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 4178 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 4179 struct rtw89_hal *hal = &rtwdev->hal; 4180 bool *done = data; 4181 u8 rssi_a, rssi_b; 4182 u32 candidate; 4183 4184 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || sta->tdls) 4185 return; 4186 4187 if (*done) 4188 return; 4189 4190 *done = true; 4191 4192 rssi_a = ewma_rssi_read(&rtwsta->rssi[RF_PATH_A]); 4193 rssi_b = ewma_rssi_read(&rtwsta->rssi[RF_PATH_B]); 4194 4195 if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH) 4196 candidate = RF_A; 4197 else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH) 4198 candidate = RF_B; 4199 else 4200 return; 4201 4202 if (hal->antenna_tx == candidate) 4203 return; 4204 4205 hal->antenna_tx = candidate; 4206 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta); 4207 4208 if (hal->antenna_tx == RF_A) { 4209 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12); 4210 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11); 4211 } else if (hal->antenna_tx == RF_B) { 4212 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11); 4213 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12); 4214 } 4215 } 4216 4217 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev) 4218 { 4219 struct rtw89_hal *hal = &rtwdev->hal; 4220 bool done = false; 4221 4222 if (!hal->tx_path_diversity) 4223 return; 4224 4225 ieee80211_iterate_stations_atomic(rtwdev->hw, 4226 rtw89_phy_tx_path_div_sta_iter, 4227 &done); 4228 } 4229 4230 #define ANTDIV_MAIN 0 4231 #define ANTDIV_AUX 1 4232 4233 static void rtw89_phy_antdiv_set_ant(struct rtw89_dev *rtwdev) 4234 { 4235 struct rtw89_hal *hal = &rtwdev->hal; 4236 u8 default_ant, optional_ant; 4237 4238 if (!hal->ant_diversity || hal->antenna_tx == 0) 4239 return; 4240 4241 if (hal->antenna_tx == RF_B) { 4242 default_ant = ANTDIV_AUX; 4243 optional_ant = ANTDIV_MAIN; 4244 } else { 4245 default_ant = ANTDIV_MAIN; 4246 optional_ant = ANTDIV_AUX; 4247 } 4248 4249 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_CGCS_CTRL, 4250 default_ant, RTW89_PHY_0); 4251 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ORI, 4252 default_ant, RTW89_PHY_0); 4253 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ALT, 4254 optional_ant, RTW89_PHY_0); 4255 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_TX_ORI, 4256 default_ant, RTW89_PHY_0); 4257 } 4258 4259 static void rtw89_phy_swap_hal_antenna(struct rtw89_dev *rtwdev) 4260 { 4261 struct rtw89_hal *hal = &rtwdev->hal; 4262 4263 hal->antenna_rx = hal->antenna_rx == RF_A ? RF_B : RF_A; 4264 hal->antenna_tx = hal->antenna_rx; 4265 } 4266 4267 static void rtw89_phy_antdiv_decision_state(struct rtw89_dev *rtwdev) 4268 { 4269 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4270 struct rtw89_hal *hal = &rtwdev->hal; 4271 bool no_change = false; 4272 u8 main_rssi, aux_rssi; 4273 u32 candidate; 4274 4275 antdiv->get_stats = false; 4276 antdiv->training_count = 0; 4277 4278 main_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->main_stats); 4279 aux_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->aux_stats); 4280 4281 if (main_rssi > aux_rssi + RTW89_TX_DIV_RSSI_RAW_TH) 4282 candidate = RF_A; 4283 else if (aux_rssi > main_rssi + RTW89_TX_DIV_RSSI_RAW_TH) 4284 candidate = RF_B; 4285 else 4286 no_change = true; 4287 4288 if (no_change) { 4289 /* swap back from training antenna to original */ 4290 rtw89_phy_swap_hal_antenna(rtwdev); 4291 return; 4292 } 4293 4294 hal->antenna_tx = candidate; 4295 hal->antenna_rx = candidate; 4296 } 4297 4298 static void rtw89_phy_antdiv_training_state(struct rtw89_dev *rtwdev) 4299 { 4300 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4301 u64 state_period; 4302 4303 if (antdiv->training_count % 2 == 0) { 4304 if (antdiv->training_count == 0) 4305 rtw89_phy_antdiv_sts_reset(rtwdev); 4306 4307 antdiv->get_stats = true; 4308 state_period = msecs_to_jiffies(ANTDIV_TRAINNING_INTVL); 4309 } else { 4310 antdiv->get_stats = false; 4311 state_period = msecs_to_jiffies(ANTDIV_DELAY); 4312 4313 rtw89_phy_swap_hal_antenna(rtwdev); 4314 rtw89_phy_antdiv_set_ant(rtwdev); 4315 } 4316 4317 antdiv->training_count++; 4318 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 4319 state_period); 4320 } 4321 4322 void rtw89_phy_antdiv_work(struct work_struct *work) 4323 { 4324 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 4325 antdiv_work.work); 4326 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4327 4328 mutex_lock(&rtwdev->mutex); 4329 4330 if (antdiv->training_count <= ANTDIV_TRAINNING_CNT) { 4331 rtw89_phy_antdiv_training_state(rtwdev); 4332 } else { 4333 rtw89_phy_antdiv_decision_state(rtwdev); 4334 rtw89_phy_antdiv_set_ant(rtwdev); 4335 } 4336 4337 mutex_unlock(&rtwdev->mutex); 4338 } 4339 4340 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev) 4341 { 4342 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4343 struct rtw89_hal *hal = &rtwdev->hal; 4344 u8 rssi, rssi_pre; 4345 4346 if (!hal->ant_diversity || hal->ant_diversity_fixed) 4347 return; 4348 4349 rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->target_stats); 4350 rssi_pre = antdiv->rssi_pre; 4351 antdiv->rssi_pre = rssi; 4352 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats); 4353 4354 if (abs((int)rssi - (int)rssi_pre) < ANTDIV_RSSI_DIFF_TH) 4355 return; 4356 4357 antdiv->training_count = 0; 4358 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 0); 4359 } 4360 4361 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) 4362 { 4363 rtw89_phy_ccx_top_setting_init(rtwdev); 4364 rtw89_phy_ifs_clm_setting_init(rtwdev); 4365 } 4366 4367 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 4368 { 4369 const struct rtw89_chip_info *chip = rtwdev->chip; 4370 4371 rtw89_phy_stat_init(rtwdev); 4372 4373 rtw89_chip_bb_sethw(rtwdev); 4374 4375 rtw89_phy_env_monitor_init(rtwdev); 4376 rtw89_physts_parsing_init(rtwdev); 4377 rtw89_phy_dig_init(rtwdev); 4378 rtw89_phy_cfo_init(rtwdev); 4379 rtw89_phy_ul_tb_info_init(rtwdev); 4380 rtw89_phy_antdiv_init(rtwdev); 4381 rtw89_phy_antdiv_set_ant(rtwdev); 4382 4383 rtw89_phy_init_rf_nctl(rtwdev); 4384 rtw89_chip_rfk_init(rtwdev); 4385 rtw89_load_txpwr_table(rtwdev, chip->byr_table); 4386 rtw89_chip_set_txpwr_ctrl(rtwdev); 4387 rtw89_chip_power_trim(rtwdev); 4388 rtw89_chip_cfg_txrx_path(rtwdev); 4389 } 4390 4391 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 4392 { 4393 const struct rtw89_chip_info *chip = rtwdev->chip; 4394 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 4395 u8 bss_color; 4396 4397 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 4398 return; 4399 4400 bss_color = vif->bss_conf.he_bss_color.color; 4401 4402 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_VLD0, 0x1, 4403 phy_idx); 4404 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT, 4405 bss_color, phy_idx); 4406 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID, 4407 vif->cfg.aid, phy_idx); 4408 } 4409 4410 static void 4411 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4412 { 4413 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); 4414 } 4415 4416 static void 4417 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4418 { 4419 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 4420 } 4421 4422 static void 4423 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4424 { 4425 rtw89_phy_write32_set(rtwdev, def->addr, def->mask); 4426 } 4427 4428 static void 4429 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4430 { 4431 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); 4432 } 4433 4434 static void 4435 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4436 { 4437 udelay(def->data); 4438 } 4439 4440 static void 4441 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { 4442 [RTW89_RFK_F_WRF] = _rfk_write_rf, 4443 [RTW89_RFK_F_WM] = _rfk_write32_mask, 4444 [RTW89_RFK_F_WS] = _rfk_write32_set, 4445 [RTW89_RFK_F_WC] = _rfk_write32_clr, 4446 [RTW89_RFK_F_DELAY] = _rfk_delay, 4447 }; 4448 4449 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 4450 4451 void 4452 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) 4453 { 4454 const struct rtw89_reg5_def *p = tbl->defs; 4455 const struct rtw89_reg5_def *end = tbl->defs + tbl->size; 4456 4457 for (; p < end; p++) 4458 _rfk_handler[p->flag](rtwdev, p); 4459 } 4460 EXPORT_SYMBOL(rtw89_rfk_parser); 4461 4462 #define RTW89_TSSI_FAST_MODE_NUM 4 4463 4464 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = { 4465 {0xD934, 0xff0000}, 4466 {0xD934, 0xff000000}, 4467 {0xD938, 0xff}, 4468 {0xD934, 0xff00}, 4469 }; 4470 4471 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = { 4472 {0xD930, 0xff0000}, 4473 {0xD930, 0xff000000}, 4474 {0xD934, 0xff}, 4475 {0xD930, 0xff00}, 4476 }; 4477 4478 static 4479 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev, 4480 enum rtw89_mac_idx mac_idx, 4481 enum rtw89_tssi_bandedge_cfg bandedge_cfg, 4482 u32 val) 4483 { 4484 const struct rtw89_reg_def *regs; 4485 u32 reg; 4486 int i; 4487 4488 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 4489 regs = rtw89_tssi_fastmode_regs_flat; 4490 else 4491 regs = rtw89_tssi_fastmode_regs_level; 4492 4493 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) { 4494 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 4495 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); 4496 } 4497 } 4498 4499 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = { 4500 {0xD91C, 0xff000000}, 4501 {0xD920, 0xff}, 4502 {0xD920, 0xff00}, 4503 {0xD920, 0xff0000}, 4504 {0xD920, 0xff000000}, 4505 {0xD924, 0xff}, 4506 {0xD924, 0xff00}, 4507 {0xD914, 0xff000000}, 4508 {0xD918, 0xff}, 4509 {0xD918, 0xff00}, 4510 {0xD918, 0xff0000}, 4511 {0xD918, 0xff000000}, 4512 {0xD91C, 0xff}, 4513 {0xD91C, 0xff00}, 4514 {0xD91C, 0xff0000}, 4515 }; 4516 4517 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = { 4518 {0xD910, 0xff}, 4519 {0xD910, 0xff00}, 4520 {0xD910, 0xff0000}, 4521 {0xD910, 0xff000000}, 4522 {0xD914, 0xff}, 4523 {0xD914, 0xff00}, 4524 {0xD914, 0xff0000}, 4525 {0xD908, 0xff}, 4526 {0xD908, 0xff00}, 4527 {0xD908, 0xff0000}, 4528 {0xD908, 0xff000000}, 4529 {0xD90C, 0xff}, 4530 {0xD90C, 0xff00}, 4531 {0xD90C, 0xff0000}, 4532 {0xD90C, 0xff000000}, 4533 }; 4534 4535 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 4536 enum rtw89_mac_idx mac_idx, 4537 enum rtw89_tssi_bandedge_cfg bandedge_cfg) 4538 { 4539 const struct rtw89_chip_info *chip = rtwdev->chip; 4540 const struct rtw89_reg_def *regs; 4541 const u32 *data; 4542 u32 reg; 4543 int i; 4544 4545 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM) 4546 return; 4547 4548 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 4549 regs = rtw89_tssi_bandedge_regs_flat; 4550 else 4551 regs = rtw89_tssi_bandedge_regs_level; 4552 4553 data = chip->tssi_dbw_table->data[bandedge_cfg]; 4554 4555 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) { 4556 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 4557 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); 4558 } 4559 4560 reg = rtw89_mac_reg_by_idx(R_AX_BANDEDGE_CFG, mac_idx); 4561 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); 4562 4563 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg, 4564 data[RTW89_TSSI_SBW20]); 4565 } 4566 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg); 4567 4568 static 4569 const u8 rtw89_ch_base_table[16] = {1, 0xff, 4570 36, 100, 132, 149, 0xff, 4571 1, 33, 65, 97, 129, 161, 193, 225, 0xff}; 4572 #define RTW89_CH_BASE_IDX_2G 0 4573 #define RTW89_CH_BASE_IDX_5G_FIRST 2 4574 #define RTW89_CH_BASE_IDX_5G_LAST 5 4575 #define RTW89_CH_BASE_IDX_6G_FIRST 7 4576 #define RTW89_CH_BASE_IDX_6G_LAST 14 4577 4578 #define RTW89_CH_BASE_IDX_MASK GENMASK(7, 4) 4579 #define RTW89_CH_OFFSET_MASK GENMASK(3, 0) 4580 4581 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band) 4582 { 4583 u8 chan_idx; 4584 u8 last, first; 4585 u8 idx; 4586 4587 switch (band) { 4588 case RTW89_BAND_2G: 4589 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, RTW89_CH_BASE_IDX_2G) | 4590 FIELD_PREP(RTW89_CH_OFFSET_MASK, central_ch); 4591 return chan_idx; 4592 case RTW89_BAND_5G: 4593 first = RTW89_CH_BASE_IDX_5G_FIRST; 4594 last = RTW89_CH_BASE_IDX_5G_LAST; 4595 break; 4596 case RTW89_BAND_6G: 4597 first = RTW89_CH_BASE_IDX_6G_FIRST; 4598 last = RTW89_CH_BASE_IDX_6G_LAST; 4599 break; 4600 default: 4601 rtw89_warn(rtwdev, "Unsupported band %d\n", band); 4602 return 0; 4603 } 4604 4605 for (idx = last; idx >= first; idx--) 4606 if (central_ch >= rtw89_ch_base_table[idx]) 4607 break; 4608 4609 if (idx < first) { 4610 rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch); 4611 return 0; 4612 } 4613 4614 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, idx) | 4615 FIELD_PREP(RTW89_CH_OFFSET_MASK, 4616 (central_ch - rtw89_ch_base_table[idx]) >> 1); 4617 return chan_idx; 4618 } 4619 EXPORT_SYMBOL(rtw89_encode_chan_idx); 4620 4621 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, 4622 u8 *ch, enum nl80211_band *band) 4623 { 4624 u8 idx, offset; 4625 4626 idx = FIELD_GET(RTW89_CH_BASE_IDX_MASK, chan_idx); 4627 offset = FIELD_GET(RTW89_CH_OFFSET_MASK, chan_idx); 4628 4629 if (idx == RTW89_CH_BASE_IDX_2G) { 4630 *band = NL80211_BAND_2GHZ; 4631 *ch = offset; 4632 return; 4633 } 4634 4635 *band = idx <= RTW89_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ; 4636 *ch = rtw89_ch_base_table[idx] + (offset << 1); 4637 } 4638 EXPORT_SYMBOL(rtw89_decode_chan_idx); 4639 4640 #define EDCCA_DEFAULT 249 4641 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan) 4642 { 4643 u32 reg = rtwdev->chip->edcca_lvl_reg; 4644 struct rtw89_hal *hal = &rtwdev->hal; 4645 u32 val; 4646 4647 if (scan) { 4648 hal->edcca_bak = rtw89_phy_read32(rtwdev, reg); 4649 val = hal->edcca_bak; 4650 u32p_replace_bits(&val, EDCCA_DEFAULT, B_SEG0R_EDCCA_LVL_A_MSK); 4651 u32p_replace_bits(&val, EDCCA_DEFAULT, B_SEG0R_EDCCA_LVL_P_MSK); 4652 u32p_replace_bits(&val, EDCCA_DEFAULT, B_SEG0R_PPDU_LVL_MSK); 4653 rtw89_phy_write32(rtwdev, reg, val); 4654 } else { 4655 rtw89_phy_write32(rtwdev, reg, hal->edcca_bak); 4656 } 4657 } 4658