1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "debug.h" 7 #include "fw.h" 8 #include "mac.h" 9 #include "phy.h" 10 #include "ps.h" 11 #include "reg.h" 12 #include "sar.h" 13 #include "txrx.h" 14 #include "util.h" 15 16 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, 17 const struct rtw89_ra_report *report) 18 { 19 u32 bit_rate = report->bit_rate; 20 21 /* lower than ofdm, do not aggregate */ 22 if (bit_rate < 550) 23 return 1; 24 25 /* avoid AMSDU for legacy rate */ 26 if (report->might_fallback_legacy) 27 return 1; 28 29 /* lower than 20M vht 2ss mcs8, make it small */ 30 if (bit_rate < 1800) 31 return 1200; 32 33 /* lower than 40M vht 2ss mcs9, make it medium */ 34 if (bit_rate < 4000) 35 return 2600; 36 37 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ 38 if (bit_rate < 7000) 39 return 3500; 40 41 return rtwdev->chip->max_amsdu_limit; 42 } 43 44 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) 45 { 46 u64 ra_mask = 0; 47 u8 mcs_cap; 48 int i, nss; 49 50 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { 51 mcs_cap = mcs_map & 0x3; 52 switch (mcs_cap) { 53 case 2: 54 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; 55 break; 56 case 1: 57 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; 58 break; 59 case 0: 60 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; 61 break; 62 default: 63 break; 64 } 65 } 66 67 return ra_mask; 68 } 69 70 static u64 get_he_ra_mask(struct ieee80211_sta *sta) 71 { 72 struct ieee80211_sta_he_cap cap = sta->deflink.he_cap; 73 u16 mcs_map; 74 75 switch (sta->deflink.bandwidth) { 76 case IEEE80211_STA_RX_BW_160: 77 if (cap.he_cap_elem.phy_cap_info[0] & 78 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) 79 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); 80 else 81 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); 82 break; 83 default: 84 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); 85 } 86 87 /* MCS11, MCS9, MCS7 */ 88 return get_mcs_ra_mask(mcs_map, 11, 2); 89 } 90 91 #define RA_FLOOR_TABLE_SIZE 7 92 #define RA_FLOOR_UP_GAP 3 93 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, 94 u8 ratr_state) 95 { 96 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; 97 u8 rssi_lv = 0; 98 u8 i; 99 100 rssi >>= 1; 101 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 102 if (i >= ratr_state) 103 rssi_lv_t[i] += RA_FLOOR_UP_GAP; 104 if (rssi < rssi_lv_t[i]) { 105 rssi_lv = i; 106 break; 107 } 108 } 109 if (rssi_lv == 0) 110 return 0xffffffffffffffffULL; 111 else if (rssi_lv == 1) 112 return 0xfffffffffffffff0ULL; 113 else if (rssi_lv == 2) 114 return 0xffffffffffffefe0ULL; 115 else if (rssi_lv == 3) 116 return 0xffffffffffffcfc0ULL; 117 else if (rssi_lv == 4) 118 return 0xffffffffffff8f80ULL; 119 else if (rssi_lv >= 5) 120 return 0xffffffffffff0f00ULL; 121 122 return 0xffffffffffffffffULL; 123 } 124 125 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak) 126 { 127 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 128 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 129 130 if (ra_mask == 0) 131 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 132 133 return ra_mask; 134 } 135 136 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 137 { 138 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 139 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 140 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 141 enum nl80211_band band; 142 u64 cfg_mask; 143 144 if (!rtwsta->use_cfg_mask) 145 return -1; 146 147 switch (chan->band_type) { 148 case RTW89_BAND_2G: 149 band = NL80211_BAND_2GHZ; 150 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, 151 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); 152 break; 153 case RTW89_BAND_5G: 154 band = NL80211_BAND_5GHZ; 155 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, 156 RA_MASK_OFDM_RATES); 157 break; 158 case RTW89_BAND_6G: 159 band = NL80211_BAND_6GHZ; 160 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy, 161 RA_MASK_OFDM_RATES); 162 break; 163 default: 164 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type); 165 return -1; 166 } 167 168 if (sta->deflink.he_cap.has_he) { 169 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], 170 RA_MASK_HE_1SS_RATES); 171 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], 172 RA_MASK_HE_2SS_RATES); 173 } else if (sta->deflink.vht_cap.vht_supported) { 174 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 175 RA_MASK_VHT_1SS_RATES); 176 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 177 RA_MASK_VHT_2SS_RATES); 178 } else if (sta->deflink.ht_cap.ht_supported) { 179 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 180 RA_MASK_HT_1SS_RATES); 181 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 182 RA_MASK_HT_2SS_RATES); 183 } 184 185 return cfg_mask; 186 } 187 188 static const u64 189 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, 190 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; 191 static const u64 192 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 193 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; 194 static const u64 195 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, 196 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; 197 198 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev, 199 struct rtw89_sta *rtwsta, 200 bool *fix_giltf_en, u8 *fix_giltf) 201 { 202 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 203 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 204 u8 band = chan->band_type; 205 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 206 u8 he_gi = mask->control[nl_band].he_gi; 207 u8 he_ltf = mask->control[nl_band].he_ltf; 208 209 if (!rtwsta->use_cfg_mask) 210 return; 211 212 if (he_ltf == 2 && he_gi == 2) { 213 *fix_giltf = RTW89_GILTF_LGI_4XHE32; 214 } else if (he_ltf == 2 && he_gi == 0) { 215 *fix_giltf = RTW89_GILTF_SGI_4XHE08; 216 } else if (he_ltf == 1 && he_gi == 1) { 217 *fix_giltf = RTW89_GILTF_2XHE16; 218 } else if (he_ltf == 1 && he_gi == 0) { 219 *fix_giltf = RTW89_GILTF_2XHE08; 220 } else if (he_ltf == 0 && he_gi == 1) { 221 *fix_giltf = RTW89_GILTF_1XHE16; 222 } else if (he_ltf == 0 && he_gi == 0) { 223 *fix_giltf = RTW89_GILTF_1XHE08; 224 } else { 225 *fix_giltf_en = false; 226 return; 227 } 228 229 *fix_giltf_en = true; 230 } 231 232 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 233 struct ieee80211_sta *sta, bool csi) 234 { 235 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 236 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 237 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 238 struct rtw89_ra_info *ra = &rtwsta->ra; 239 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 240 struct ieee80211_vif *vif = rtwvif_to_vif(rtwsta->rtwvif); 241 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; 242 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 243 u64 ra_mask = 0; 244 u64 ra_mask_bak; 245 u8 mode = 0; 246 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; 247 u8 bw_mode = 0; 248 u8 stbc_en = 0; 249 u8 ldpc_en = 0; 250 u8 fix_giltf = 0; 251 u8 i; 252 bool sgi = false; 253 bool fix_giltf_en = false; 254 255 memset(ra, 0, sizeof(*ra)); 256 /* Set the ra mask from sta's capability */ 257 if (sta->deflink.he_cap.has_he) { 258 mode |= RTW89_RA_MODE_HE; 259 csi_mode = RTW89_RA_RPT_MODE_HE; 260 ra_mask |= get_he_ra_mask(sta); 261 high_rate_masks = rtw89_ra_mask_he_rates; 262 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[2] & 263 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) 264 stbc_en = 1; 265 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[1] & 266 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) 267 ldpc_en = 1; 268 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta, &fix_giltf_en, &fix_giltf); 269 } else if (sta->deflink.vht_cap.vht_supported) { 270 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 271 272 mode |= RTW89_RA_MODE_VHT; 273 csi_mode = RTW89_RA_RPT_MODE_VHT; 274 /* MCS9, MCS8, MCS7 */ 275 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); 276 high_rate_masks = rtw89_ra_mask_vht_rates; 277 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 278 stbc_en = 1; 279 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 280 ldpc_en = 1; 281 } else if (sta->deflink.ht_cap.ht_supported) { 282 mode |= RTW89_RA_MODE_HT; 283 csi_mode = RTW89_RA_RPT_MODE_HT; 284 ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 48) | 285 ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 36) | 286 (sta->deflink.ht_cap.mcs.rx_mask[1] << 24) | 287 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 288 high_rate_masks = rtw89_ra_mask_ht_rates; 289 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 290 stbc_en = 1; 291 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 292 ldpc_en = 1; 293 } 294 295 switch (chan->band_type) { 296 case RTW89_BAND_2G: 297 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 298 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xf) 299 mode |= RTW89_RA_MODE_CCK; 300 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xff0) 301 mode |= RTW89_RA_MODE_OFDM; 302 break; 303 case RTW89_BAND_5G: 304 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 305 mode |= RTW89_RA_MODE_OFDM; 306 break; 307 case RTW89_BAND_6G: 308 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_6GHZ] << 4; 309 mode |= RTW89_RA_MODE_OFDM; 310 break; 311 default: 312 rtw89_err(rtwdev, "Unknown band type\n"); 313 break; 314 } 315 316 ra_mask_bak = ra_mask; 317 318 if (mode >= RTW89_RA_MODE_HT) { 319 u64 mask = 0; 320 for (i = 0; i < rtwdev->hal.tx_nss; i++) 321 mask |= high_rate_masks[i]; 322 if (mode & RTW89_RA_MODE_OFDM) 323 mask |= RA_MASK_SUBOFDM_RATES; 324 if (mode & RTW89_RA_MODE_CCK) 325 mask |= RA_MASK_SUBCCK_RATES; 326 ra_mask &= mask; 327 } else if (mode & RTW89_RA_MODE_OFDM) { 328 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES); 329 } 330 331 if (mode != RTW89_RA_MODE_CCK) 332 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); 333 334 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak); 335 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 336 337 switch (sta->deflink.bandwidth) { 338 case IEEE80211_STA_RX_BW_160: 339 bw_mode = RTW89_CHANNEL_WIDTH_160; 340 sgi = sta->deflink.vht_cap.vht_supported && 341 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160); 342 break; 343 case IEEE80211_STA_RX_BW_80: 344 bw_mode = RTW89_CHANNEL_WIDTH_80; 345 sgi = sta->deflink.vht_cap.vht_supported && 346 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 347 break; 348 case IEEE80211_STA_RX_BW_40: 349 bw_mode = RTW89_CHANNEL_WIDTH_40; 350 sgi = sta->deflink.ht_cap.ht_supported && 351 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 352 break; 353 default: 354 bw_mode = RTW89_CHANNEL_WIDTH_20; 355 sgi = sta->deflink.ht_cap.ht_supported && 356 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 357 break; 358 } 359 360 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 361 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) 362 ra->dcm_cap = 1; 363 364 if (rate_pattern->enable && !vif->p2p) { 365 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 366 ra_mask &= rate_pattern->ra_mask; 367 mode = rate_pattern->ra_mode; 368 } 369 370 ra->bw_cap = bw_mode; 371 ra->er_cap = rtwsta->er_cap; 372 ra->mode_ctrl = mode; 373 ra->macid = rtwsta->mac_id; 374 ra->stbc_cap = stbc_en; 375 ra->ldpc_cap = ldpc_en; 376 ra->ss_num = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1; 377 ra->en_sgi = sgi; 378 ra->ra_mask = ra_mask; 379 ra->fix_giltf_en = fix_giltf_en; 380 ra->fix_giltf = fix_giltf; 381 382 if (!csi) 383 return; 384 385 ra->fixed_csi_rate_en = false; 386 ra->ra_csi_rate_en = true; 387 ra->cr_tbl_sel = false; 388 ra->band_num = rtwvif->phy_idx; 389 ra->csi_bw = bw_mode; 390 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; 391 ra->csi_mcs_ss_idx = 5; 392 ra->csi_mode = csi_mode; 393 } 394 395 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 396 u32 changed) 397 { 398 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 399 struct rtw89_ra_info *ra = &rtwsta->ra; 400 401 rtw89_phy_ra_sta_update(rtwdev, sta, false); 402 403 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) 404 ra->upd_mask = 1; 405 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED)) 406 ra->upd_bw_nss_mask = 1; 407 408 rtw89_debug(rtwdev, RTW89_DBG_RA, 409 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", 410 ra->macid, 411 ra->bw_cap, 412 ra->ss_num, 413 ra->en_sgi, 414 ra->giltf); 415 416 rtw89_fw_h2c_ra(rtwdev, ra, false); 417 } 418 419 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, 420 u16 rate_base, u64 ra_mask, u8 ra_mode, 421 u32 rate_ctrl, u32 ctrl_skip, bool force) 422 { 423 u8 n, c; 424 425 if (rate_ctrl == ctrl_skip) 426 return true; 427 428 n = hweight32(rate_ctrl); 429 if (n == 0) 430 return true; 431 432 if (force && n != 1) 433 return false; 434 435 if (next->enable) 436 return false; 437 438 c = __fls(rate_ctrl); 439 next->rate = rate_base + c; 440 next->ra_mode = ra_mode; 441 next->ra_mask = ra_mask; 442 next->enable = true; 443 444 return true; 445 } 446 447 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 448 struct ieee80211_vif *vif, 449 const struct cfg80211_bitrate_mask *mask) 450 { 451 struct ieee80211_supported_band *sband; 452 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 453 struct rtw89_phy_rate_pattern next_pattern = {0}; 454 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 455 static const u16 hw_rate_he[] = {RTW89_HW_RATE_HE_NSS1_MCS0, 456 RTW89_HW_RATE_HE_NSS2_MCS0, 457 RTW89_HW_RATE_HE_NSS3_MCS0, 458 RTW89_HW_RATE_HE_NSS4_MCS0}; 459 static const u16 hw_rate_vht[] = {RTW89_HW_RATE_VHT_NSS1_MCS0, 460 RTW89_HW_RATE_VHT_NSS2_MCS0, 461 RTW89_HW_RATE_VHT_NSS3_MCS0, 462 RTW89_HW_RATE_VHT_NSS4_MCS0}; 463 static const u16 hw_rate_ht[] = {RTW89_HW_RATE_MCS0, 464 RTW89_HW_RATE_MCS8, 465 RTW89_HW_RATE_MCS16, 466 RTW89_HW_RATE_MCS24}; 467 u8 band = chan->band_type; 468 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 469 u8 tx_nss = rtwdev->hal.tx_nss; 470 u8 i; 471 472 for (i = 0; i < tx_nss; i++) 473 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i], 474 RA_MASK_HE_RATES, RTW89_RA_MODE_HE, 475 mask->control[nl_band].he_mcs[i], 476 0, true)) 477 goto out; 478 479 for (i = 0; i < tx_nss; i++) 480 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i], 481 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, 482 mask->control[nl_band].vht_mcs[i], 483 0, true)) 484 goto out; 485 486 for (i = 0; i < tx_nss; i++) 487 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i], 488 RA_MASK_HT_RATES, RTW89_RA_MODE_HT, 489 mask->control[nl_band].ht_mcs[i], 490 0, true)) 491 goto out; 492 493 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and 494 * require at least one basic rate for ieee80211_set_bitrate_mask, 495 * so the decision just depends on if all bitrates are set or not. 496 */ 497 sband = rtwdev->hw->wiphy->bands[nl_band]; 498 if (band == RTW89_BAND_2G) { 499 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, 500 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, 501 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, 502 mask->control[nl_band].legacy, 503 BIT(sband->n_bitrates) - 1, false)) 504 goto out; 505 } else { 506 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, 507 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, 508 mask->control[nl_band].legacy, 509 BIT(sband->n_bitrates) - 1, false)) 510 goto out; 511 } 512 513 if (!next_pattern.enable) 514 goto out; 515 516 rtwvif->rate_pattern = next_pattern; 517 rtw89_debug(rtwdev, RTW89_DBG_RA, 518 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", 519 next_pattern.rate, 520 next_pattern.ra_mask, 521 next_pattern.ra_mode); 522 return; 523 524 out: 525 rtwvif->rate_pattern.enable = false; 526 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); 527 } 528 529 static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta) 530 { 531 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; 532 533 rtw89_phy_ra_updata_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED); 534 } 535 536 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) 537 { 538 ieee80211_iterate_stations_atomic(rtwdev->hw, 539 rtw89_phy_ra_updata_sta_iter, 540 rtwdev); 541 } 542 543 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) 544 { 545 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 546 struct rtw89_ra_info *ra = &rtwsta->ra; 547 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; 548 bool csi = rtw89_sta_has_beamformer_cap(sta); 549 550 rtw89_phy_ra_sta_update(rtwdev, sta, csi); 551 552 if (rssi > 40) 553 ra->init_rate_lv = 1; 554 else if (rssi > 20) 555 ra->init_rate_lv = 2; 556 else if (rssi > 1) 557 ra->init_rate_lv = 3; 558 else 559 ra->init_rate_lv = 0; 560 ra->upd_all = 1; 561 rtw89_debug(rtwdev, RTW89_DBG_RA, 562 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", 563 ra->macid, 564 ra->mode_ctrl, 565 ra->bw_cap, 566 ra->ss_num, 567 ra->init_rate_lv); 568 rtw89_debug(rtwdev, RTW89_DBG_RA, 569 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", 570 ra->dcm_cap, 571 ra->er_cap, 572 ra->ldpc_cap, 573 ra->stbc_cap, 574 ra->en_sgi, 575 ra->giltf); 576 577 rtw89_fw_h2c_ra(rtwdev, ra, csi); 578 } 579 580 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 581 const struct rtw89_chan *chan, 582 enum rtw89_bandwidth dbw) 583 { 584 enum rtw89_bandwidth cbw = chan->band_width; 585 u8 pri_ch = chan->primary_channel; 586 u8 central_ch = chan->channel; 587 u8 txsc_idx = 0; 588 u8 tmp = 0; 589 590 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 591 return txsc_idx; 592 593 switch (cbw) { 594 case RTW89_CHANNEL_WIDTH_40: 595 txsc_idx = pri_ch > central_ch ? 1 : 2; 596 break; 597 case RTW89_CHANNEL_WIDTH_80: 598 if (dbw == RTW89_CHANNEL_WIDTH_20) { 599 if (pri_ch > central_ch) 600 txsc_idx = (pri_ch - central_ch) >> 1; 601 else 602 txsc_idx = ((central_ch - pri_ch) >> 1) + 1; 603 } else { 604 txsc_idx = pri_ch > central_ch ? 9 : 10; 605 } 606 break; 607 case RTW89_CHANNEL_WIDTH_160: 608 if (pri_ch > central_ch) 609 tmp = (pri_ch - central_ch) >> 1; 610 else 611 tmp = ((central_ch - pri_ch) >> 1) + 1; 612 613 if (dbw == RTW89_CHANNEL_WIDTH_20) { 614 txsc_idx = tmp; 615 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 616 if (tmp == 1 || tmp == 3) 617 txsc_idx = 9; 618 else if (tmp == 5 || tmp == 7) 619 txsc_idx = 11; 620 else if (tmp == 2 || tmp == 4) 621 txsc_idx = 10; 622 else if (tmp == 6 || tmp == 8) 623 txsc_idx = 12; 624 else 625 return 0xff; 626 } else { 627 txsc_idx = pri_ch > central_ch ? 13 : 14; 628 } 629 break; 630 case RTW89_CHANNEL_WIDTH_80_80: 631 if (dbw == RTW89_CHANNEL_WIDTH_20) { 632 if (pri_ch > central_ch) 633 txsc_idx = (10 - (pri_ch - central_ch)) >> 1; 634 else 635 txsc_idx = ((central_ch - pri_ch) >> 1) + 5; 636 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 637 txsc_idx = pri_ch > central_ch ? 10 : 12; 638 } else { 639 txsc_idx = 14; 640 } 641 break; 642 default: 643 break; 644 } 645 646 return txsc_idx; 647 } 648 EXPORT_SYMBOL(rtw89_phy_get_txsc); 649 650 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev) 651 { 652 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) || 653 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1); 654 } 655 656 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 657 u32 addr, u32 mask) 658 { 659 const struct rtw89_chip_info *chip = rtwdev->chip; 660 const u32 *base_addr = chip->rf_base_addr; 661 u32 val, direct_addr; 662 663 if (rf_path >= rtwdev->chip->rf_path_num) { 664 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 665 return INV_RF_DATA; 666 } 667 668 addr &= 0xff; 669 direct_addr = base_addr[rf_path] + (addr << 2); 670 mask &= RFREG_MASK; 671 672 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); 673 674 return val; 675 } 676 EXPORT_SYMBOL(rtw89_phy_read_rf); 677 678 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev, 679 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 680 { 681 bool busy; 682 bool done; 683 u32 val; 684 int ret; 685 686 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 687 1, 30, false, rtwdev); 688 if (ret) { 689 rtw89_err(rtwdev, "read rf busy swsi\n"); 690 return INV_RF_DATA; 691 } 692 693 mask &= RFREG_MASK; 694 695 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) | 696 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr); 697 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val); 698 udelay(2); 699 700 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1, 701 30, false, rtwdev, R_SWSI_V1, 702 B_SWSI_R_DATA_DONE_V1); 703 if (ret) { 704 rtw89_err(rtwdev, "read swsi busy\n"); 705 return INV_RF_DATA; 706 } 707 708 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask); 709 } 710 711 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 712 u32 addr, u32 mask) 713 { 714 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 715 716 if (rf_path >= rtwdev->chip->rf_path_num) { 717 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 718 return INV_RF_DATA; 719 } 720 721 if (ad_sel) 722 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 723 else 724 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask); 725 } 726 EXPORT_SYMBOL(rtw89_phy_read_rf_v1); 727 728 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 729 u32 addr, u32 mask, u32 data) 730 { 731 const struct rtw89_chip_info *chip = rtwdev->chip; 732 const u32 *base_addr = chip->rf_base_addr; 733 u32 direct_addr; 734 735 if (rf_path >= rtwdev->chip->rf_path_num) { 736 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 737 return false; 738 } 739 740 addr &= 0xff; 741 direct_addr = base_addr[rf_path] + (addr << 2); 742 mask &= RFREG_MASK; 743 744 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); 745 746 /* delay to ensure writing properly */ 747 udelay(1); 748 749 return true; 750 } 751 EXPORT_SYMBOL(rtw89_phy_write_rf); 752 753 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev, 754 enum rtw89_rf_path rf_path, u32 addr, u32 mask, 755 u32 data) 756 { 757 u8 bit_shift; 758 u32 val; 759 bool busy, b_msk_en = false; 760 int ret; 761 762 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 763 1, 30, false, rtwdev); 764 if (ret) { 765 rtw89_err(rtwdev, "write rf busy swsi\n"); 766 return false; 767 } 768 769 data &= RFREG_MASK; 770 mask &= RFREG_MASK; 771 772 if (mask != RFREG_MASK) { 773 b_msk_en = true; 774 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK, 775 mask); 776 bit_shift = __ffs(mask); 777 data = (data << bit_shift) & RFREG_MASK; 778 } 779 780 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) | 781 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) | 782 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) | 783 FIELD_PREP(B_SWSI_DATA_VAL_V1, data); 784 785 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val); 786 787 return true; 788 } 789 790 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 791 u32 addr, u32 mask, u32 data) 792 { 793 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 794 795 if (rf_path >= rtwdev->chip->rf_path_num) { 796 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 797 return false; 798 } 799 800 if (ad_sel) 801 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 802 else 803 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data); 804 } 805 EXPORT_SYMBOL(rtw89_phy_write_rf_v1); 806 807 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev) 808 { 809 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1; 810 } 811 812 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, 813 enum rtw89_phy_idx phy_idx) 814 { 815 const struct rtw89_chip_info *chip = rtwdev->chip; 816 817 chip->ops->bb_reset(rtwdev, phy_idx); 818 } 819 820 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, 821 const struct rtw89_reg2_def *reg, 822 enum rtw89_rf_path rf_path, 823 void *extra_data) 824 { 825 if (reg->addr == 0xfe) 826 mdelay(50); 827 else if (reg->addr == 0xfd) 828 mdelay(5); 829 else if (reg->addr == 0xfc) 830 mdelay(1); 831 else if (reg->addr == 0xfb) 832 udelay(50); 833 else if (reg->addr == 0xfa) 834 udelay(5); 835 else if (reg->addr == 0xf9) 836 udelay(1); 837 else 838 rtw89_phy_write32(rtwdev, reg->addr, reg->data); 839 } 840 841 union rtw89_phy_bb_gain_arg { 842 u32 addr; 843 struct { 844 union { 845 u8 type; 846 struct { 847 u8 rxsc_start:4; 848 u8 bw:4; 849 }; 850 }; 851 u8 path; 852 u8 gain_band; 853 u8 cfg_type; 854 }; 855 } __packed; 856 857 static void 858 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev, 859 union rtw89_phy_bb_gain_arg arg, u32 data) 860 { 861 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 862 u8 type = arg.type; 863 u8 path = arg.path; 864 u8 gband = arg.gain_band; 865 int i; 866 867 switch (type) { 868 case 0: 869 for (i = 0; i < 4; i++, data >>= 8) 870 gain->lna_gain[gband][path][i] = data & 0xff; 871 break; 872 case 1: 873 for (i = 4; i < 7; i++, data >>= 8) 874 gain->lna_gain[gband][path][i] = data & 0xff; 875 break; 876 case 2: 877 for (i = 0; i < 2; i++, data >>= 8) 878 gain->tia_gain[gband][path][i] = data & 0xff; 879 break; 880 default: 881 rtw89_warn(rtwdev, 882 "bb gain error {0x%x:0x%x} with unknown type: %d\n", 883 arg.addr, data, type); 884 break; 885 } 886 } 887 888 enum rtw89_phy_bb_rxsc_start_idx { 889 RTW89_BB_RXSC_START_IDX_FULL = 0, 890 RTW89_BB_RXSC_START_IDX_20 = 1, 891 RTW89_BB_RXSC_START_IDX_20_1 = 5, 892 RTW89_BB_RXSC_START_IDX_40 = 9, 893 RTW89_BB_RXSC_START_IDX_80 = 13, 894 }; 895 896 static void 897 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev, 898 union rtw89_phy_bb_gain_arg arg, u32 data) 899 { 900 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 901 u8 rxsc_start = arg.rxsc_start; 902 u8 bw = arg.bw; 903 u8 path = arg.path; 904 u8 gband = arg.gain_band; 905 u8 rxsc; 906 s8 ofst; 907 int i; 908 909 switch (bw) { 910 case RTW89_CHANNEL_WIDTH_20: 911 gain->rpl_ofst_20[gband][path] = (s8)data; 912 break; 913 case RTW89_CHANNEL_WIDTH_40: 914 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 915 gain->rpl_ofst_40[gband][path][0] = (s8)data; 916 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 917 for (i = 0; i < 2; i++, data >>= 8) { 918 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 919 ofst = (s8)(data & 0xff); 920 gain->rpl_ofst_40[gband][path][rxsc] = ofst; 921 } 922 } 923 break; 924 case RTW89_CHANNEL_WIDTH_80: 925 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 926 gain->rpl_ofst_80[gband][path][0] = (s8)data; 927 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 928 for (i = 0; i < 4; i++, data >>= 8) { 929 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 930 ofst = (s8)(data & 0xff); 931 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 932 } 933 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 934 for (i = 0; i < 2; i++, data >>= 8) { 935 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 936 ofst = (s8)(data & 0xff); 937 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 938 } 939 } 940 break; 941 case RTW89_CHANNEL_WIDTH_160: 942 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 943 gain->rpl_ofst_160[gband][path][0] = (s8)data; 944 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 945 for (i = 0; i < 4; i++, data >>= 8) { 946 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 947 ofst = (s8)(data & 0xff); 948 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 949 } 950 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) { 951 for (i = 0; i < 4; i++, data >>= 8) { 952 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i; 953 ofst = (s8)(data & 0xff); 954 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 955 } 956 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 957 for (i = 0; i < 4; i++, data >>= 8) { 958 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 959 ofst = (s8)(data & 0xff); 960 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 961 } 962 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) { 963 for (i = 0; i < 2; i++, data >>= 8) { 964 rxsc = RTW89_BB_RXSC_START_IDX_80 + i; 965 ofst = (s8)(data & 0xff); 966 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 967 } 968 } 969 break; 970 default: 971 rtw89_warn(rtwdev, 972 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n", 973 arg.addr, data, bw); 974 break; 975 } 976 } 977 978 static void 979 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev, 980 union rtw89_phy_bb_gain_arg arg, u32 data) 981 { 982 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 983 u8 type = arg.type; 984 u8 path = arg.path; 985 u8 gband = arg.gain_band; 986 int i; 987 988 switch (type) { 989 case 0: 990 for (i = 0; i < 4; i++, data >>= 8) 991 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 992 break; 993 case 1: 994 for (i = 4; i < 7; i++, data >>= 8) 995 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 996 break; 997 default: 998 rtw89_warn(rtwdev, 999 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n", 1000 arg.addr, data, type); 1001 break; 1002 } 1003 } 1004 1005 static void 1006 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev, 1007 union rtw89_phy_bb_gain_arg arg, u32 data) 1008 { 1009 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 1010 u8 type = arg.type; 1011 u8 path = arg.path; 1012 u8 gband = arg.gain_band; 1013 int i; 1014 1015 switch (type) { 1016 case 0: 1017 for (i = 0; i < 4; i++, data >>= 8) 1018 gain->lna_op1db[gband][path][i] = data & 0xff; 1019 break; 1020 case 1: 1021 for (i = 4; i < 7; i++, data >>= 8) 1022 gain->lna_op1db[gband][path][i] = data & 0xff; 1023 break; 1024 case 2: 1025 for (i = 0; i < 4; i++, data >>= 8) 1026 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1027 break; 1028 case 3: 1029 for (i = 4; i < 8; i++, data >>= 8) 1030 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1031 break; 1032 default: 1033 rtw89_warn(rtwdev, 1034 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n", 1035 arg.addr, data, type); 1036 break; 1037 } 1038 } 1039 1040 static void rtw89_phy_config_bb_gain(struct rtw89_dev *rtwdev, 1041 const struct rtw89_reg2_def *reg, 1042 enum rtw89_rf_path rf_path, 1043 void *extra_data) 1044 { 1045 const struct rtw89_chip_info *chip = rtwdev->chip; 1046 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr }; 1047 struct rtw89_efuse *efuse = &rtwdev->efuse; 1048 1049 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR) 1050 return; 1051 1052 if (arg.path >= chip->rf_path_num) 1053 return; 1054 1055 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) { 1056 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n"); 1057 return; 1058 } 1059 1060 switch (arg.cfg_type) { 1061 case 0: 1062 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data); 1063 break; 1064 case 1: 1065 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data); 1066 break; 1067 case 2: 1068 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data); 1069 break; 1070 case 3: 1071 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data); 1072 break; 1073 case 4: 1074 /* This cfg_type is only used by rfe_type >= 50 with eFEM */ 1075 if (efuse->rfe_type < 50) 1076 break; 1077 fallthrough; 1078 default: 1079 rtw89_warn(rtwdev, 1080 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n", 1081 arg.addr, reg->data, arg.cfg_type); 1082 break; 1083 } 1084 } 1085 1086 static void 1087 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, 1088 const struct rtw89_reg2_def *reg, 1089 enum rtw89_rf_path rf_path, 1090 struct rtw89_fw_h2c_rf_reg_info *info) 1091 { 1092 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; 1093 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 1094 1095 if (page >= RTW89_H2C_RF_PAGE_NUM) { 1096 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d", 1097 rf_path, info->curr_idx); 1098 return; 1099 } 1100 1101 info->rtw89_phy_config_rf_h2c[page][idx] = 1102 cpu_to_le32((reg->addr << 20) | reg->data); 1103 info->curr_idx++; 1104 } 1105 1106 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, 1107 struct rtw89_fw_h2c_rf_reg_info *info) 1108 { 1109 u16 remain = info->curr_idx; 1110 u16 len = 0; 1111 u8 i; 1112 int ret = 0; 1113 1114 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) { 1115 rtw89_warn(rtwdev, 1116 "rf reg h2c total len %d larger than %d\n", 1117 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE); 1118 ret = -EINVAL; 1119 goto out; 1120 } 1121 1122 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) { 1123 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain; 1124 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i); 1125 if (ret) 1126 goto out; 1127 } 1128 out: 1129 info->curr_idx = 0; 1130 1131 return ret; 1132 } 1133 1134 static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev, 1135 const struct rtw89_reg2_def *reg, 1136 enum rtw89_rf_path rf_path, 1137 void *extra_data) 1138 { 1139 u32 addr = reg->addr; 1140 1141 if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb || 1142 addr == 0xfa || addr == 0xf9) 1143 return; 1144 1145 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100) 1146 return; 1147 1148 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1149 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1150 } 1151 1152 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, 1153 const struct rtw89_reg2_def *reg, 1154 enum rtw89_rf_path rf_path, 1155 void *extra_data) 1156 { 1157 if (reg->addr == 0xfe) { 1158 mdelay(50); 1159 } else if (reg->addr == 0xfd) { 1160 mdelay(5); 1161 } else if (reg->addr == 0xfc) { 1162 mdelay(1); 1163 } else if (reg->addr == 0xfb) { 1164 udelay(50); 1165 } else if (reg->addr == 0xfa) { 1166 udelay(5); 1167 } else if (reg->addr == 0xf9) { 1168 udelay(1); 1169 } else { 1170 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); 1171 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1172 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1173 } 1174 } 1175 1176 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 1177 const struct rtw89_reg2_def *reg, 1178 enum rtw89_rf_path rf_path, 1179 void *extra_data) 1180 { 1181 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data); 1182 1183 if (reg->addr < 0x100) 1184 return; 1185 1186 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1187 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1188 } 1189 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1); 1190 1191 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, 1192 const struct rtw89_phy_table *table, 1193 u32 *headline_size, u32 *headline_idx, 1194 u8 rfe, u8 cv) 1195 { 1196 const struct rtw89_reg2_def *reg; 1197 u32 headline; 1198 u32 compare, target; 1199 u8 rfe_para, cv_para; 1200 u8 cv_max = 0; 1201 bool case_matched = false; 1202 u32 i; 1203 1204 for (i = 0; i < table->n_regs; i++) { 1205 reg = &table->regs[i]; 1206 headline = get_phy_headline(reg->addr); 1207 if (headline != PHY_HEADLINE_VALID) 1208 break; 1209 } 1210 *headline_size = i; 1211 if (*headline_size == 0) 1212 return 0; 1213 1214 /* case 1: RFE match, CV match */ 1215 compare = get_phy_compare(rfe, cv); 1216 for (i = 0; i < *headline_size; i++) { 1217 reg = &table->regs[i]; 1218 target = get_phy_target(reg->addr); 1219 if (target == compare) { 1220 *headline_idx = i; 1221 return 0; 1222 } 1223 } 1224 1225 /* case 2: RFE match, CV don't care */ 1226 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); 1227 for (i = 0; i < *headline_size; i++) { 1228 reg = &table->regs[i]; 1229 target = get_phy_target(reg->addr); 1230 if (target == compare) { 1231 *headline_idx = i; 1232 return 0; 1233 } 1234 } 1235 1236 /* case 3: RFE match, CV max in table */ 1237 for (i = 0; i < *headline_size; i++) { 1238 reg = &table->regs[i]; 1239 rfe_para = get_phy_cond_rfe(reg->addr); 1240 cv_para = get_phy_cond_cv(reg->addr); 1241 if (rfe_para == rfe) { 1242 if (cv_para >= cv_max) { 1243 cv_max = cv_para; 1244 *headline_idx = i; 1245 case_matched = true; 1246 } 1247 } 1248 } 1249 1250 if (case_matched) 1251 return 0; 1252 1253 /* case 4: RFE don't care, CV max in table */ 1254 for (i = 0; i < *headline_size; i++) { 1255 reg = &table->regs[i]; 1256 rfe_para = get_phy_cond_rfe(reg->addr); 1257 cv_para = get_phy_cond_cv(reg->addr); 1258 if (rfe_para == PHY_COND_DONT_CARE) { 1259 if (cv_para >= cv_max) { 1260 cv_max = cv_para; 1261 *headline_idx = i; 1262 case_matched = true; 1263 } 1264 } 1265 } 1266 1267 if (case_matched) 1268 return 0; 1269 1270 return -EINVAL; 1271 } 1272 1273 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, 1274 const struct rtw89_phy_table *table, 1275 void (*config)(struct rtw89_dev *rtwdev, 1276 const struct rtw89_reg2_def *reg, 1277 enum rtw89_rf_path rf_path, 1278 void *data), 1279 void *extra_data) 1280 { 1281 const struct rtw89_reg2_def *reg; 1282 enum rtw89_rf_path rf_path = table->rf_path; 1283 u8 rfe = rtwdev->efuse.rfe_type; 1284 u8 cv = rtwdev->hal.cv; 1285 u32 i; 1286 u32 headline_size = 0, headline_idx = 0; 1287 u32 target = 0, cfg_target; 1288 u8 cond; 1289 bool is_matched = true; 1290 bool target_found = false; 1291 int ret; 1292 1293 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, 1294 &headline_idx, rfe, cv); 1295 if (ret) { 1296 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); 1297 return; 1298 } 1299 1300 cfg_target = get_phy_target(table->regs[headline_idx].addr); 1301 for (i = headline_size; i < table->n_regs; i++) { 1302 reg = &table->regs[i]; 1303 cond = get_phy_cond(reg->addr); 1304 switch (cond) { 1305 case PHY_COND_BRANCH_IF: 1306 case PHY_COND_BRANCH_ELIF: 1307 target = get_phy_target(reg->addr); 1308 break; 1309 case PHY_COND_BRANCH_ELSE: 1310 is_matched = false; 1311 if (!target_found) { 1312 rtw89_warn(rtwdev, "failed to load CR %x/%x\n", 1313 reg->addr, reg->data); 1314 return; 1315 } 1316 break; 1317 case PHY_COND_BRANCH_END: 1318 is_matched = true; 1319 target_found = false; 1320 break; 1321 case PHY_COND_CHECK: 1322 if (target_found) { 1323 is_matched = false; 1324 break; 1325 } 1326 1327 if (target == cfg_target) { 1328 is_matched = true; 1329 target_found = true; 1330 } else { 1331 is_matched = false; 1332 target_found = false; 1333 } 1334 break; 1335 default: 1336 if (is_matched) 1337 config(rtwdev, reg, rf_path, extra_data); 1338 break; 1339 } 1340 } 1341 } 1342 1343 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) 1344 { 1345 const struct rtw89_chip_info *chip = rtwdev->chip; 1346 const struct rtw89_phy_table *bb_table = chip->bb_table; 1347 const struct rtw89_phy_table *bb_gain_table = chip->bb_gain_table; 1348 1349 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); 1350 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 1351 if (bb_gain_table) 1352 rtw89_phy_init_reg(rtwdev, bb_gain_table, 1353 rtw89_phy_config_bb_gain, NULL); 1354 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); 1355 } 1356 1357 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 1358 { 1359 rtw89_phy_write32(rtwdev, 0x8080, 0x4); 1360 udelay(1); 1361 return rtw89_phy_read32(rtwdev, 0x8080); 1362 } 1363 1364 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio) 1365 { 1366 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 1367 enum rtw89_rf_path rf_path, void *data); 1368 const struct rtw89_chip_info *chip = rtwdev->chip; 1369 const struct rtw89_phy_table *rf_table; 1370 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; 1371 u8 path; 1372 1373 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); 1374 if (!rf_reg_info) 1375 return; 1376 1377 for (path = RF_PATH_A; path < chip->rf_path_num; path++) { 1378 rf_table = chip->rf_table[path]; 1379 rf_reg_info->rf_path = rf_table->rf_path; 1380 if (noio) 1381 config = rtw89_phy_config_rf_reg_noio; 1382 else 1383 config = rf_table->config ? rf_table->config : 1384 rtw89_phy_config_rf_reg; 1385 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info); 1386 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) 1387 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", 1388 rf_reg_info->rf_path); 1389 } 1390 kfree(rf_reg_info); 1391 } 1392 1393 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) 1394 { 1395 const struct rtw89_chip_info *chip = rtwdev->chip; 1396 const struct rtw89_phy_table *nctl_table; 1397 u32 val; 1398 int ret; 1399 1400 /* IQK/DPK clock & reset */ 1401 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3); 1402 rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1); 1403 rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000); 1404 if (chip->chip_id != RTL8851B) 1405 rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000); 1406 if (chip->chip_id == RTL8852B) 1407 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2); 1408 1409 /* check 0x8080 */ 1410 rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8); 1411 1412 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, 1413 1000, false, rtwdev); 1414 if (ret) 1415 rtw89_err(rtwdev, "failed to poll nctl block\n"); 1416 1417 nctl_table = chip->nctl_table; 1418 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); 1419 1420 if (chip->nctl_post_table) 1421 rtw89_rfk_parser(rtwdev, chip->nctl_post_table); 1422 } 1423 1424 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) 1425 { 1426 u32 phy_page = addr >> 8; 1427 u32 ofst = 0; 1428 1429 switch (phy_page) { 1430 case 0x6: 1431 case 0x7: 1432 case 0x8: 1433 case 0x9: 1434 case 0xa: 1435 case 0xb: 1436 case 0xc: 1437 case 0xd: 1438 case 0x19: 1439 case 0x1a: 1440 case 0x1b: 1441 ofst = 0x2000; 1442 break; 1443 default: 1444 /* warning case */ 1445 ofst = 0; 1446 break; 1447 } 1448 1449 if (phy_page >= 0x40 && phy_page <= 0x4f) 1450 ofst = 0x2000; 1451 1452 return ofst; 1453 } 1454 1455 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1456 u32 data, enum rtw89_phy_idx phy_idx) 1457 { 1458 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1459 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1460 rtw89_phy_write32_mask(rtwdev, addr, mask, data); 1461 } 1462 EXPORT_SYMBOL(rtw89_phy_write32_idx); 1463 1464 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1465 enum rtw89_phy_idx phy_idx) 1466 { 1467 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1468 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1469 return rtw89_phy_read32_mask(rtwdev, addr, mask); 1470 } 1471 EXPORT_SYMBOL(rtw89_phy_read32_idx); 1472 1473 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1474 u32 val) 1475 { 1476 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 1477 1478 if (!rtwdev->dbcc_en) 1479 return; 1480 1481 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 1482 } 1483 1484 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 1485 const struct rtw89_phy_reg3_tbl *tbl) 1486 { 1487 const struct rtw89_reg3_def *reg3; 1488 int i; 1489 1490 for (i = 0; i < tbl->size; i++) { 1491 reg3 = &tbl->reg3[i]; 1492 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); 1493 } 1494 } 1495 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl); 1496 1497 static const u8 rtw89_rs_idx_max[] = { 1498 [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX, 1499 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX, 1500 [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX, 1501 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX, 1502 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX, 1503 }; 1504 1505 static const u8 rtw89_rs_nss_max[] = { 1506 [RTW89_RS_CCK] = 1, 1507 [RTW89_RS_OFDM] = 1, 1508 [RTW89_RS_MCS] = RTW89_NSS_MAX, 1509 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX, 1510 [RTW89_RS_OFFSET] = 1, 1511 }; 1512 1513 static const u8 _byr_of_rs[] = { 1514 [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck), 1515 [RTW89_RS_OFDM] = offsetof(struct rtw89_txpwr_byrate, ofdm), 1516 [RTW89_RS_MCS] = offsetof(struct rtw89_txpwr_byrate, mcs), 1517 [RTW89_RS_HEDCM] = offsetof(struct rtw89_txpwr_byrate, hedcm), 1518 [RTW89_RS_OFFSET] = offsetof(struct rtw89_txpwr_byrate, offset), 1519 }; 1520 1521 #define _byr_seek(rs, raw) ((s8 *)(raw) + _byr_of_rs[rs]) 1522 #define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_max[rs] + (idx)) 1523 #define _byr_chk(rs, nss, idx) \ 1524 ((nss) < rtw89_rs_nss_max[rs] && (idx) < rtw89_rs_idx_max[rs]) 1525 1526 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 1527 const struct rtw89_txpwr_table *tbl) 1528 { 1529 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; 1530 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; 1531 s8 *byr; 1532 u32 data; 1533 u8 i, idx; 1534 1535 for (; cfg < end; cfg++) { 1536 byr = _byr_seek(cfg->rs, &rtwdev->byr[cfg->band]); 1537 data = cfg->data; 1538 1539 for (i = 0; i < cfg->len; i++, data >>= 8) { 1540 idx = _byr_idx(cfg->rs, cfg->nss, (cfg->shf + i)); 1541 byr[idx] = (s8)(data & 0xff); 1542 } 1543 } 1544 } 1545 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate); 1546 1547 #define _phy_txpwr_rf_to_mac(rtwdev, txpwr_rf) \ 1548 ({ \ 1549 const struct rtw89_chip_info *__c = (rtwdev)->chip; \ 1550 (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \ 1551 }) 1552 1553 static 1554 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, 1555 const struct rtw89_rate_desc *rate_desc) 1556 { 1557 s8 *byr; 1558 u8 idx; 1559 1560 if (rate_desc->rs == RTW89_RS_CCK) 1561 band = RTW89_BAND_2G; 1562 1563 if (!_byr_chk(rate_desc->rs, rate_desc->nss, rate_desc->idx)) { 1564 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1565 "[TXPWR] unknown byrate desc rs=%d nss=%d idx=%d\n", 1566 rate_desc->rs, rate_desc->nss, rate_desc->idx); 1567 1568 return 0; 1569 } 1570 1571 byr = _byr_seek(rate_desc->rs, &rtwdev->byr[band]); 1572 idx = _byr_idx(rate_desc->rs, rate_desc->nss, rate_desc->idx); 1573 1574 return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]); 1575 } 1576 1577 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g) 1578 { 1579 switch (channel_6g) { 1580 case 1 ... 29: 1581 return (channel_6g - 1) / 2; 1582 case 33 ... 61: 1583 return (channel_6g - 3) / 2; 1584 case 65 ... 93: 1585 return (channel_6g - 5) / 2; 1586 case 97 ... 125: 1587 return (channel_6g - 7) / 2; 1588 case 129 ... 157: 1589 return (channel_6g - 9) / 2; 1590 case 161 ... 189: 1591 return (channel_6g - 11) / 2; 1592 case 193 ... 221: 1593 return (channel_6g - 13) / 2; 1594 case 225 ... 253: 1595 return (channel_6g - 15) / 2; 1596 default: 1597 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g); 1598 return 0; 1599 } 1600 } 1601 1602 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel) 1603 { 1604 if (band == RTW89_BAND_6G) 1605 return rtw89_channel_6g_to_idx(rtwdev, channel); 1606 1607 switch (channel) { 1608 case 1 ... 14: 1609 return channel - 1; 1610 case 36 ... 64: 1611 return (channel - 36) / 2; 1612 case 100 ... 144: 1613 return ((channel - 100) / 2) + 15; 1614 case 149 ... 177: 1615 return ((channel - 149) / 2) + 38; 1616 default: 1617 rtw89_warn(rtwdev, "unknown channel: %d\n", channel); 1618 return 0; 1619 } 1620 } 1621 1622 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 1623 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) 1624 { 1625 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 1626 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; 1627 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; 1628 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; 1629 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 1630 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1631 u8 regd = rtw89_regd_get(rtwdev, band); 1632 u8 reg6 = regulatory->reg_6ghz_power; 1633 s8 lmt = 0, sar; 1634 1635 switch (band) { 1636 case RTW89_BAND_2G: 1637 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 1638 if (lmt) 1639 break; 1640 1641 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 1642 break; 1643 case RTW89_BAND_5G: 1644 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 1645 if (lmt) 1646 break; 1647 1648 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 1649 break; 1650 case RTW89_BAND_6G: 1651 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx]; 1652 if (lmt) 1653 break; 1654 1655 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][RTW89_WW] 1656 [RTW89_REG_6GHZ_POWER_DFLT] 1657 [ch_idx]; 1658 break; 1659 default: 1660 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1661 return 0; 1662 } 1663 1664 lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt); 1665 sar = rtw89_query_sar(rtwdev); 1666 1667 return min(lmt, sar); 1668 } 1669 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit); 1670 1671 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \ 1672 do { \ 1673 u8 __i; \ 1674 for (__i = 0; __i < RTW89_BF_NUM; __i++) \ 1675 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ 1676 band, \ 1677 bw, ntx, \ 1678 rs, __i, \ 1679 (ch)); \ 1680 } while (0) 1681 1682 static void rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev *rtwdev, 1683 struct rtw89_txpwr_limit *lmt, 1684 u8 band, u8 ntx, u8 ch) 1685 { 1686 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1687 ntx, RTW89_RS_CCK, ch); 1688 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1689 ntx, RTW89_RS_CCK, ch); 1690 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1691 ntx, RTW89_RS_OFDM, ch); 1692 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1693 RTW89_CHANNEL_WIDTH_20, 1694 ntx, RTW89_RS_MCS, ch); 1695 } 1696 1697 static void rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev *rtwdev, 1698 struct rtw89_txpwr_limit *lmt, 1699 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1700 { 1701 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1702 ntx, RTW89_RS_CCK, ch - 2); 1703 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1704 ntx, RTW89_RS_CCK, ch); 1705 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1706 ntx, RTW89_RS_OFDM, pri_ch); 1707 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1708 RTW89_CHANNEL_WIDTH_20, 1709 ntx, RTW89_RS_MCS, ch - 2); 1710 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1711 RTW89_CHANNEL_WIDTH_20, 1712 ntx, RTW89_RS_MCS, ch + 2); 1713 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1714 RTW89_CHANNEL_WIDTH_40, 1715 ntx, RTW89_RS_MCS, ch); 1716 } 1717 1718 static void rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev *rtwdev, 1719 struct rtw89_txpwr_limit *lmt, 1720 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1721 { 1722 s8 val_0p5_n[RTW89_BF_NUM]; 1723 s8 val_0p5_p[RTW89_BF_NUM]; 1724 u8 i; 1725 1726 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1727 ntx, RTW89_RS_OFDM, pri_ch); 1728 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1729 RTW89_CHANNEL_WIDTH_20, 1730 ntx, RTW89_RS_MCS, ch - 6); 1731 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1732 RTW89_CHANNEL_WIDTH_20, 1733 ntx, RTW89_RS_MCS, ch - 2); 1734 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1735 RTW89_CHANNEL_WIDTH_20, 1736 ntx, RTW89_RS_MCS, ch + 2); 1737 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1738 RTW89_CHANNEL_WIDTH_20, 1739 ntx, RTW89_RS_MCS, ch + 6); 1740 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1741 RTW89_CHANNEL_WIDTH_40, 1742 ntx, RTW89_RS_MCS, ch - 4); 1743 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1744 RTW89_CHANNEL_WIDTH_40, 1745 ntx, RTW89_RS_MCS, ch + 4); 1746 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1747 RTW89_CHANNEL_WIDTH_80, 1748 ntx, RTW89_RS_MCS, ch); 1749 1750 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1751 ntx, RTW89_RS_MCS, ch - 4); 1752 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1753 ntx, RTW89_RS_MCS, ch + 4); 1754 1755 for (i = 0; i < RTW89_BF_NUM; i++) 1756 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1757 } 1758 1759 static void rtw89_phy_fill_txpwr_limit_160m(struct rtw89_dev *rtwdev, 1760 struct rtw89_txpwr_limit *lmt, 1761 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1762 { 1763 s8 val_0p5_n[RTW89_BF_NUM]; 1764 s8 val_0p5_p[RTW89_BF_NUM]; 1765 s8 val_2p5_n[RTW89_BF_NUM]; 1766 s8 val_2p5_p[RTW89_BF_NUM]; 1767 u8 i; 1768 1769 /* fill ofdm section */ 1770 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1771 ntx, RTW89_RS_OFDM, pri_ch); 1772 1773 /* fill mcs 20m section */ 1774 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1775 RTW89_CHANNEL_WIDTH_20, 1776 ntx, RTW89_RS_MCS, ch - 14); 1777 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1778 RTW89_CHANNEL_WIDTH_20, 1779 ntx, RTW89_RS_MCS, ch - 10); 1780 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1781 RTW89_CHANNEL_WIDTH_20, 1782 ntx, RTW89_RS_MCS, ch - 6); 1783 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1784 RTW89_CHANNEL_WIDTH_20, 1785 ntx, RTW89_RS_MCS, ch - 2); 1786 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band, 1787 RTW89_CHANNEL_WIDTH_20, 1788 ntx, RTW89_RS_MCS, ch + 2); 1789 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band, 1790 RTW89_CHANNEL_WIDTH_20, 1791 ntx, RTW89_RS_MCS, ch + 6); 1792 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band, 1793 RTW89_CHANNEL_WIDTH_20, 1794 ntx, RTW89_RS_MCS, ch + 10); 1795 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band, 1796 RTW89_CHANNEL_WIDTH_20, 1797 ntx, RTW89_RS_MCS, ch + 14); 1798 1799 /* fill mcs 40m section */ 1800 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1801 RTW89_CHANNEL_WIDTH_40, 1802 ntx, RTW89_RS_MCS, ch - 12); 1803 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1804 RTW89_CHANNEL_WIDTH_40, 1805 ntx, RTW89_RS_MCS, ch - 4); 1806 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band, 1807 RTW89_CHANNEL_WIDTH_40, 1808 ntx, RTW89_RS_MCS, ch + 4); 1809 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band, 1810 RTW89_CHANNEL_WIDTH_40, 1811 ntx, RTW89_RS_MCS, ch + 12); 1812 1813 /* fill mcs 80m section */ 1814 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1815 RTW89_CHANNEL_WIDTH_80, 1816 ntx, RTW89_RS_MCS, ch - 8); 1817 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band, 1818 RTW89_CHANNEL_WIDTH_80, 1819 ntx, RTW89_RS_MCS, ch + 8); 1820 1821 /* fill mcs 160m section */ 1822 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band, 1823 RTW89_CHANNEL_WIDTH_160, 1824 ntx, RTW89_RS_MCS, ch); 1825 1826 /* fill mcs 40m 0p5 section */ 1827 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1828 ntx, RTW89_RS_MCS, ch - 4); 1829 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1830 ntx, RTW89_RS_MCS, ch + 4); 1831 1832 for (i = 0; i < RTW89_BF_NUM; i++) 1833 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1834 1835 /* fill mcs 40m 2p5 section */ 1836 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40, 1837 ntx, RTW89_RS_MCS, ch - 8); 1838 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40, 1839 ntx, RTW89_RS_MCS, ch + 8); 1840 1841 for (i = 0; i < RTW89_BF_NUM; i++) 1842 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]); 1843 } 1844 1845 static 1846 void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev, 1847 const struct rtw89_chan *chan, 1848 struct rtw89_txpwr_limit *lmt, 1849 u8 ntx) 1850 { 1851 u8 band = chan->band_type; 1852 u8 pri_ch = chan->primary_channel; 1853 u8 ch = chan->channel; 1854 u8 bw = chan->band_width; 1855 1856 memset(lmt, 0, sizeof(*lmt)); 1857 1858 switch (bw) { 1859 case RTW89_CHANNEL_WIDTH_20: 1860 rtw89_phy_fill_txpwr_limit_20m(rtwdev, lmt, band, ntx, ch); 1861 break; 1862 case RTW89_CHANNEL_WIDTH_40: 1863 rtw89_phy_fill_txpwr_limit_40m(rtwdev, lmt, band, ntx, ch, 1864 pri_ch); 1865 break; 1866 case RTW89_CHANNEL_WIDTH_80: 1867 rtw89_phy_fill_txpwr_limit_80m(rtwdev, lmt, band, ntx, ch, 1868 pri_ch); 1869 break; 1870 case RTW89_CHANNEL_WIDTH_160: 1871 rtw89_phy_fill_txpwr_limit_160m(rtwdev, lmt, band, ntx, ch, 1872 pri_ch); 1873 break; 1874 } 1875 } 1876 1877 static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 1878 u8 ru, u8 ntx, u8 ch) 1879 { 1880 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 1881 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; 1882 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; 1883 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; 1884 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 1885 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1886 u8 regd = rtw89_regd_get(rtwdev, band); 1887 u8 reg6 = regulatory->reg_6ghz_power; 1888 s8 lmt_ru = 0, sar; 1889 1890 switch (band) { 1891 case RTW89_BAND_2G: 1892 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 1893 if (lmt_ru) 1894 break; 1895 1896 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 1897 break; 1898 case RTW89_BAND_5G: 1899 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 1900 if (lmt_ru) 1901 break; 1902 1903 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 1904 break; 1905 case RTW89_BAND_6G: 1906 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx]; 1907 if (lmt_ru) 1908 break; 1909 1910 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][RTW89_WW] 1911 [RTW89_REG_6GHZ_POWER_DFLT] 1912 [ch_idx]; 1913 break; 1914 default: 1915 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1916 return 0; 1917 } 1918 1919 lmt_ru = _phy_txpwr_rf_to_mac(rtwdev, lmt_ru); 1920 sar = rtw89_query_sar(rtwdev); 1921 1922 return min(lmt_ru, sar); 1923 } 1924 1925 static void 1926 rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev, 1927 struct rtw89_txpwr_limit_ru *lmt_ru, 1928 u8 band, u8 ntx, u8 ch) 1929 { 1930 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1931 RTW89_RU26, 1932 ntx, ch); 1933 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1934 RTW89_RU52, 1935 ntx, ch); 1936 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1937 RTW89_RU106, 1938 ntx, ch); 1939 } 1940 1941 static void 1942 rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev, 1943 struct rtw89_txpwr_limit_ru *lmt_ru, 1944 u8 band, u8 ntx, u8 ch) 1945 { 1946 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1947 RTW89_RU26, 1948 ntx, ch - 2); 1949 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1950 RTW89_RU26, 1951 ntx, ch + 2); 1952 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1953 RTW89_RU52, 1954 ntx, ch - 2); 1955 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1956 RTW89_RU52, 1957 ntx, ch + 2); 1958 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1959 RTW89_RU106, 1960 ntx, ch - 2); 1961 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1962 RTW89_RU106, 1963 ntx, ch + 2); 1964 } 1965 1966 static void 1967 rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev, 1968 struct rtw89_txpwr_limit_ru *lmt_ru, 1969 u8 band, u8 ntx, u8 ch) 1970 { 1971 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1972 RTW89_RU26, 1973 ntx, ch - 6); 1974 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1975 RTW89_RU26, 1976 ntx, ch - 2); 1977 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1978 RTW89_RU26, 1979 ntx, ch + 2); 1980 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1981 RTW89_RU26, 1982 ntx, ch + 6); 1983 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1984 RTW89_RU52, 1985 ntx, ch - 6); 1986 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1987 RTW89_RU52, 1988 ntx, ch - 2); 1989 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1990 RTW89_RU52, 1991 ntx, ch + 2); 1992 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1993 RTW89_RU52, 1994 ntx, ch + 6); 1995 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1996 RTW89_RU106, 1997 ntx, ch - 6); 1998 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1999 RTW89_RU106, 2000 ntx, ch - 2); 2001 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2002 RTW89_RU106, 2003 ntx, ch + 2); 2004 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2005 RTW89_RU106, 2006 ntx, ch + 6); 2007 } 2008 2009 static void 2010 rtw89_phy_fill_txpwr_limit_ru_160m(struct rtw89_dev *rtwdev, 2011 struct rtw89_txpwr_limit_ru *lmt_ru, 2012 u8 band, u8 ntx, u8 ch) 2013 { 2014 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 }; 2015 int i; 2016 2017 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM); 2018 for (i = 0; i < RTW89_RU_SEC_NUM; i++) { 2019 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2020 RTW89_RU26, 2021 ntx, 2022 ch + ofst[i]); 2023 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2024 RTW89_RU52, 2025 ntx, 2026 ch + ofst[i]); 2027 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2028 RTW89_RU106, 2029 ntx, 2030 ch + ofst[i]); 2031 } 2032 } 2033 2034 static 2035 void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, 2036 const struct rtw89_chan *chan, 2037 struct rtw89_txpwr_limit_ru *lmt_ru, 2038 u8 ntx) 2039 { 2040 u8 band = chan->band_type; 2041 u8 ch = chan->channel; 2042 u8 bw = chan->band_width; 2043 2044 memset(lmt_ru, 0, sizeof(*lmt_ru)); 2045 2046 switch (bw) { 2047 case RTW89_CHANNEL_WIDTH_20: 2048 rtw89_phy_fill_txpwr_limit_ru_20m(rtwdev, lmt_ru, band, ntx, 2049 ch); 2050 break; 2051 case RTW89_CHANNEL_WIDTH_40: 2052 rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, band, ntx, 2053 ch); 2054 break; 2055 case RTW89_CHANNEL_WIDTH_80: 2056 rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, band, ntx, 2057 ch); 2058 break; 2059 case RTW89_CHANNEL_WIDTH_160: 2060 rtw89_phy_fill_txpwr_limit_ru_160m(rtwdev, lmt_ru, band, ntx, 2061 ch); 2062 break; 2063 } 2064 } 2065 2066 void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev, 2067 const struct rtw89_chan *chan, 2068 enum rtw89_phy_idx phy_idx) 2069 { 2070 u8 max_nss_num = rtwdev->chip->rf_path_num; 2071 static const u8 rs[] = { 2072 RTW89_RS_CCK, 2073 RTW89_RS_OFDM, 2074 RTW89_RS_MCS, 2075 RTW89_RS_HEDCM, 2076 }; 2077 struct rtw89_rate_desc cur; 2078 u8 band = chan->band_type; 2079 u8 ch = chan->channel; 2080 u32 addr, val; 2081 s8 v[4] = {}; 2082 u8 i; 2083 2084 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2085 "[TXPWR] set txpwr byrate with ch=%d\n", ch); 2086 2087 BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_CCK] % 4); 2088 BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_OFDM] % 4); 2089 BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_MCS] % 4); 2090 BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_HEDCM] % 4); 2091 2092 addr = R_AX_PWR_BY_RATE; 2093 for (cur.nss = 0; cur.nss < max_nss_num; cur.nss++) { 2094 for (i = 0; i < ARRAY_SIZE(rs); i++) { 2095 if (cur.nss >= rtw89_rs_nss_max[rs[i]]) 2096 continue; 2097 2098 cur.rs = rs[i]; 2099 for (cur.idx = 0; cur.idx < rtw89_rs_idx_max[rs[i]]; 2100 cur.idx++) { 2101 v[cur.idx % 4] = 2102 rtw89_phy_read_txpwr_byrate(rtwdev, 2103 band, 2104 &cur); 2105 2106 if ((cur.idx + 1) % 4) 2107 continue; 2108 2109 val = FIELD_PREP(GENMASK(7, 0), v[0]) | 2110 FIELD_PREP(GENMASK(15, 8), v[1]) | 2111 FIELD_PREP(GENMASK(23, 16), v[2]) | 2112 FIELD_PREP(GENMASK(31, 24), v[3]); 2113 2114 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 2115 val); 2116 addr += 4; 2117 } 2118 } 2119 } 2120 } 2121 EXPORT_SYMBOL(rtw89_phy_set_txpwr_byrate); 2122 2123 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev, 2124 const struct rtw89_chan *chan, 2125 enum rtw89_phy_idx phy_idx) 2126 { 2127 struct rtw89_rate_desc desc = { 2128 .nss = RTW89_NSS_1, 2129 .rs = RTW89_RS_OFFSET, 2130 }; 2131 u8 band = chan->band_type; 2132 s8 v[RTW89_RATE_OFFSET_MAX] = {}; 2133 u32 val; 2134 2135 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n"); 2136 2137 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++) 2138 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, &desc); 2139 2140 BUILD_BUG_ON(RTW89_RATE_OFFSET_MAX != 5); 2141 val = FIELD_PREP(GENMASK(3, 0), v[0]) | 2142 FIELD_PREP(GENMASK(7, 4), v[1]) | 2143 FIELD_PREP(GENMASK(11, 8), v[2]) | 2144 FIELD_PREP(GENMASK(15, 12), v[3]) | 2145 FIELD_PREP(GENMASK(19, 16), v[4]); 2146 2147 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL, 2148 GENMASK(19, 0), val); 2149 } 2150 EXPORT_SYMBOL(rtw89_phy_set_txpwr_offset); 2151 2152 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev, 2153 const struct rtw89_chan *chan, 2154 enum rtw89_phy_idx phy_idx) 2155 { 2156 u8 max_ntx_num = rtwdev->chip->rf_path_num; 2157 struct rtw89_txpwr_limit lmt; 2158 u8 ch = chan->channel; 2159 u8 bw = chan->band_width; 2160 const s8 *ptr; 2161 u32 addr, val; 2162 u8 i, j; 2163 2164 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2165 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw); 2166 2167 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit) != 2168 RTW89_TXPWR_LMT_PAGE_SIZE); 2169 2170 addr = R_AX_PWR_LMT; 2171 for (i = 0; i < max_ntx_num; i++) { 2172 rtw89_phy_fill_txpwr_limit(rtwdev, chan, &lmt, i); 2173 2174 ptr = (s8 *)&lmt; 2175 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE; 2176 j += 4, addr += 4, ptr += 4) { 2177 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2178 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2179 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2180 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2181 2182 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2183 } 2184 } 2185 } 2186 EXPORT_SYMBOL(rtw89_phy_set_txpwr_limit); 2187 2188 void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, 2189 const struct rtw89_chan *chan, 2190 enum rtw89_phy_idx phy_idx) 2191 { 2192 u8 max_ntx_num = rtwdev->chip->rf_path_num; 2193 struct rtw89_txpwr_limit_ru lmt_ru; 2194 u8 ch = chan->channel; 2195 u8 bw = chan->band_width; 2196 const s8 *ptr; 2197 u32 addr, val; 2198 u8 i, j; 2199 2200 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2201 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); 2202 2203 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru) != 2204 RTW89_TXPWR_LMT_RU_PAGE_SIZE); 2205 2206 addr = R_AX_PWR_RU_LMT; 2207 for (i = 0; i < max_ntx_num; i++) { 2208 rtw89_phy_fill_txpwr_limit_ru(rtwdev, chan, &lmt_ru, i); 2209 2210 ptr = (s8 *)&lmt_ru; 2211 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE; 2212 j += 4, addr += 4, ptr += 4) { 2213 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2214 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2215 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2216 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2217 2218 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2219 } 2220 } 2221 } 2222 EXPORT_SYMBOL(rtw89_phy_set_txpwr_limit_ru); 2223 2224 struct rtw89_phy_iter_ra_data { 2225 struct rtw89_dev *rtwdev; 2226 struct sk_buff *c2h; 2227 }; 2228 2229 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) 2230 { 2231 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; 2232 struct rtw89_dev *rtwdev = ra_data->rtwdev; 2233 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2234 struct rtw89_ra_report *ra_report = &rtwsta->ra_report; 2235 struct sk_buff *c2h = ra_data->c2h; 2236 u8 mode, rate, bw, giltf, mac_id; 2237 u16 legacy_bitrate; 2238 bool valid; 2239 u8 mcs = 0; 2240 2241 mac_id = RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h->data); 2242 if (mac_id != rtwsta->mac_id) 2243 return; 2244 2245 rate = RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h->data); 2246 bw = RTW89_GET_PHY_C2H_RA_RPT_BW(c2h->data); 2247 giltf = RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h->data); 2248 mode = RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h->data); 2249 2250 if (mode == RTW89_RA_RPT_MODE_LEGACY) { 2251 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate); 2252 if (!valid) 2253 return; 2254 } 2255 2256 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate)); 2257 2258 switch (mode) { 2259 case RTW89_RA_RPT_MODE_LEGACY: 2260 ra_report->txrate.legacy = legacy_bitrate; 2261 break; 2262 case RTW89_RA_RPT_MODE_HT: 2263 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; 2264 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw)) 2265 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), 2266 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); 2267 else 2268 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); 2269 ra_report->txrate.mcs = rate; 2270 if (giltf) 2271 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2272 mcs = ra_report->txrate.mcs & 0x07; 2273 break; 2274 case RTW89_RA_RPT_MODE_VHT: 2275 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; 2276 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 2277 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 2278 if (giltf) 2279 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2280 mcs = ra_report->txrate.mcs; 2281 break; 2282 case RTW89_RA_RPT_MODE_HE: 2283 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; 2284 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 2285 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 2286 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2287 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; 2288 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2289 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; 2290 else 2291 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; 2292 mcs = ra_report->txrate.mcs; 2293 break; 2294 } 2295 2296 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw); 2297 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); 2298 ra_report->hw_rate = FIELD_PREP(RTW89_HW_RATE_MASK_MOD, mode) | 2299 FIELD_PREP(RTW89_HW_RATE_MASK_VAL, rate); 2300 ra_report->might_fallback_legacy = mcs <= 2; 2301 sta->deflink.agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); 2302 rtwsta->max_agg_wait = sta->deflink.agg.max_rc_amsdu_len / 1500 - 1; 2303 } 2304 2305 static void 2306 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2307 { 2308 struct rtw89_phy_iter_ra_data ra_data; 2309 2310 ra_data.rtwdev = rtwdev; 2311 ra_data.c2h = c2h; 2312 ieee80211_iterate_stations_atomic(rtwdev->hw, 2313 rtw89_phy_c2h_ra_rpt_iter, 2314 &ra_data); 2315 } 2316 2317 static 2318 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, 2319 struct sk_buff *c2h, u32 len) = { 2320 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 2321 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 2322 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 2323 }; 2324 2325 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 2326 u32 len, u8 class, u8 func) 2327 { 2328 void (*handler)(struct rtw89_dev *rtwdev, 2329 struct sk_buff *c2h, u32 len) = NULL; 2330 2331 switch (class) { 2332 case RTW89_PHY_C2H_CLASS_RA: 2333 if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 2334 handler = rtw89_phy_c2h_ra_handler[func]; 2335 break; 2336 case RTW89_PHY_C2H_CLASS_DM: 2337 if (func == RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY) 2338 return; 2339 fallthrough; 2340 default: 2341 rtw89_info(rtwdev, "c2h class %d not support\n", class); 2342 return; 2343 } 2344 if (!handler) { 2345 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 2346 func); 2347 return; 2348 } 2349 handler(rtwdev, skb, len); 2350 } 2351 2352 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) 2353 { 2354 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info; 2355 u32 reg_mask; 2356 2357 if (sc_xo) 2358 reg_mask = xtal->sc_xo_mask; 2359 else 2360 reg_mask = xtal->sc_xi_mask; 2361 2362 return (u8)rtw89_read32_mask(rtwdev, xtal->xcap_reg, reg_mask); 2363 } 2364 2365 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, 2366 u8 val) 2367 { 2368 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info; 2369 u32 reg_mask; 2370 2371 if (sc_xo) 2372 reg_mask = xtal->sc_xo_mask; 2373 else 2374 reg_mask = xtal->sc_xi_mask; 2375 2376 rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val); 2377 } 2378 2379 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, 2380 u8 crystal_cap, bool force) 2381 { 2382 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2383 const struct rtw89_chip_info *chip = rtwdev->chip; 2384 u8 sc_xi_val, sc_xo_val; 2385 2386 if (!force && cfo->crystal_cap == crystal_cap) 2387 return; 2388 crystal_cap = clamp_t(u8, crystal_cap, 0, 127); 2389 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8851B) { 2390 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); 2391 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); 2392 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); 2393 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); 2394 } else { 2395 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, 2396 crystal_cap, XTAL_SC_XO_MASK); 2397 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, 2398 crystal_cap, XTAL_SC_XI_MASK); 2399 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val); 2400 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val); 2401 } 2402 cfo->crystal_cap = sc_xi_val; 2403 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); 2404 2405 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); 2406 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); 2407 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", 2408 cfo->x_cap_ofst); 2409 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); 2410 } 2411 2412 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) 2413 { 2414 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2415 u8 cap; 2416 2417 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; 2418 cfo->is_adjust = false; 2419 if (cfo->crystal_cap == cfo->def_x_cap) 2420 return; 2421 cap = cfo->crystal_cap; 2422 cap += (cap > cfo->def_x_cap ? -1 : 1); 2423 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); 2424 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2425 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, 2426 cfo->def_x_cap); 2427 } 2428 2429 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) 2430 { 2431 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp; 2432 bool is_linked = rtwdev->total_sta_assoc > 0; 2433 s32 cfo_avg_312; 2434 s32 dcfo_comp_val; 2435 int sign; 2436 2437 if (!is_linked) { 2438 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", 2439 is_linked); 2440 return; 2441 } 2442 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); 2443 if (curr_cfo == 0) 2444 return; 2445 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); 2446 sign = curr_cfo > 0 ? 1 : -1; 2447 cfo_avg_312 = curr_cfo / 625 + sign * dcfo_comp_val; 2448 rtw89_debug(rtwdev, RTW89_DBG_CFO, "avg_cfo_312=%d step\n", cfo_avg_312); 2449 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 2450 cfo_avg_312 = -cfo_avg_312; 2451 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask, 2452 cfo_avg_312); 2453 } 2454 2455 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) 2456 { 2457 const struct rtw89_chip_info *chip = rtwdev->chip; 2458 2459 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_OPT, B_DCFO_OPT_EN, 1); 2460 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_WEIGHT, B_DCFO_WEIGHT_MSK, 8); 2461 2462 if (chip->cfo_hw_comp) 2463 rtw89_write32_mask(rtwdev, R_AX_PWR_UL_CTRL2, 2464 B_AX_PWR_UL_CFO_MASK, 0x6); 2465 else 2466 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, B_AX_PWR_UL_CFO_MASK); 2467 } 2468 2469 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) 2470 { 2471 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2472 struct rtw89_efuse *efuse = &rtwdev->efuse; 2473 2474 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; 2475 cfo->crystal_cap = cfo->crystal_cap_default; 2476 cfo->def_x_cap = cfo->crystal_cap; 2477 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f); 2478 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1); 2479 cfo->is_adjust = false; 2480 cfo->divergence_lock_en = false; 2481 cfo->x_cap_ofst = 0; 2482 cfo->lock_cnt = 0; 2483 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; 2484 cfo->apply_compensation = false; 2485 cfo->residual_cfo_acc = 0; 2486 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", 2487 cfo->crystal_cap_default); 2488 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); 2489 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); 2490 rtw89_dcfo_comp_init(rtwdev); 2491 cfo->cfo_timer_ms = 2000; 2492 cfo->cfo_trig_by_timer_en = false; 2493 cfo->phy_cfo_trk_cnt = 0; 2494 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2495 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE; 2496 } 2497 2498 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, 2499 s32 curr_cfo) 2500 { 2501 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2502 s8 crystal_cap = cfo->crystal_cap; 2503 s32 cfo_abs = abs(curr_cfo); 2504 int sign; 2505 2506 if (!cfo->is_adjust) { 2507 if (cfo_abs > CFO_TRK_ENABLE_TH) 2508 cfo->is_adjust = true; 2509 } else { 2510 if (cfo_abs < CFO_TRK_STOP_TH) 2511 cfo->is_adjust = false; 2512 } 2513 if (!cfo->is_adjust) { 2514 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); 2515 return; 2516 } 2517 sign = curr_cfo > 0 ? 1 : -1; 2518 if (cfo_abs > CFO_TRK_STOP_TH_4) 2519 crystal_cap += 7 * sign; 2520 else if (cfo_abs > CFO_TRK_STOP_TH_3) 2521 crystal_cap += 5 * sign; 2522 else if (cfo_abs > CFO_TRK_STOP_TH_2) 2523 crystal_cap += 3 * sign; 2524 else if (cfo_abs > CFO_TRK_STOP_TH_1) 2525 crystal_cap += 1 * sign; 2526 else 2527 return; 2528 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); 2529 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2530 "X_cap{Curr,Default}={0x%x,0x%x}\n", 2531 cfo->crystal_cap, cfo->def_x_cap); 2532 } 2533 2534 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) 2535 { 2536 const struct rtw89_chip_info *chip = rtwdev->chip; 2537 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2538 s32 cfo_khz_all = 0; 2539 s32 cfo_cnt_all = 0; 2540 s32 cfo_all_avg = 0; 2541 u8 i; 2542 2543 if (rtwdev->total_sta_assoc != 1) 2544 return 0; 2545 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); 2546 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2547 if (cfo->cfo_cnt[i] == 0) 2548 continue; 2549 cfo_khz_all += cfo->cfo_tail[i]; 2550 cfo_cnt_all += cfo->cfo_cnt[i]; 2551 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); 2552 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2553 cfo->dcfo_avg = phy_div(cfo_khz_all << chip->dcfo_comp_sft, 2554 cfo_cnt_all); 2555 } 2556 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2557 "CFO track for macid = %d\n", i); 2558 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2559 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", 2560 cfo_khz_all, cfo_cnt_all, cfo_all_avg); 2561 return cfo_all_avg; 2562 } 2563 2564 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) 2565 { 2566 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2567 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2568 s32 target_cfo = 0; 2569 s32 cfo_khz_all = 0; 2570 s32 cfo_khz_all_tp_wgt = 0; 2571 s32 cfo_avg = 0; 2572 s32 max_cfo_lb = BIT(31); 2573 s32 min_cfo_ub = GENMASK(30, 0); 2574 u16 cfo_cnt_all = 0; 2575 u8 active_entry_cnt = 0; 2576 u8 sta_cnt = 0; 2577 u32 tp_all = 0; 2578 u8 i; 2579 u8 cfo_tol = 0; 2580 2581 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); 2582 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { 2583 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); 2584 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2585 if (cfo->cfo_cnt[i] == 0) 2586 continue; 2587 cfo_khz_all += cfo->cfo_tail[i]; 2588 cfo_cnt_all += cfo->cfo_cnt[i]; 2589 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); 2590 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2591 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", 2592 cfo_khz_all, cfo_cnt_all, cfo_avg); 2593 target_cfo = cfo_avg; 2594 } 2595 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { 2596 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); 2597 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2598 if (cfo->cfo_cnt[i] == 0) 2599 continue; 2600 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2601 (s32)cfo->cfo_cnt[i]); 2602 cfo_khz_all += cfo->cfo_avg[i]; 2603 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2604 "Macid=%d, cfo_avg=%d\n", i, 2605 cfo->cfo_avg[i]); 2606 } 2607 sta_cnt = rtwdev->total_sta_assoc; 2608 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); 2609 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2610 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", 2611 cfo_khz_all, sta_cnt, cfo_avg); 2612 target_cfo = cfo_avg; 2613 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { 2614 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); 2615 cfo_tol = cfo->sta_cfo_tolerance; 2616 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2617 sta_cnt++; 2618 if (cfo->cfo_cnt[i] != 0) { 2619 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2620 (s32)cfo->cfo_cnt[i]); 2621 active_entry_cnt++; 2622 } else { 2623 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; 2624 } 2625 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); 2626 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); 2627 cfo_khz_all += cfo->cfo_avg[i]; 2628 /* need tp for each entry */ 2629 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2630 "[%d] cfo_avg=%d, tp=tbd\n", 2631 i, cfo->cfo_avg[i]); 2632 if (sta_cnt >= rtwdev->total_sta_assoc) 2633 break; 2634 } 2635 tp_all = stats->rx_throughput; /* need tp for each entry */ 2636 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); 2637 2638 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", 2639 sta_cnt); 2640 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", 2641 active_entry_cnt); 2642 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2643 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", 2644 cfo_khz_all_tp_wgt, cfo_avg); 2645 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", 2646 max_cfo_lb, min_cfo_ub); 2647 if (max_cfo_lb <= min_cfo_ub) { 2648 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2649 "cfo win_size=%d\n", 2650 min_cfo_ub - max_cfo_lb); 2651 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); 2652 } else { 2653 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2654 "No intersection of cfo tolerance windows\n"); 2655 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); 2656 } 2657 for (i = 0; i < CFO_TRACK_MAX_USER; i++) 2658 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2659 } 2660 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); 2661 return target_cfo; 2662 } 2663 2664 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) 2665 { 2666 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2667 2668 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); 2669 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); 2670 cfo->packet_count = 0; 2671 cfo->packet_count_pre = 0; 2672 cfo->cfo_avg_pre = 0; 2673 } 2674 2675 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) 2676 { 2677 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2678 s32 new_cfo = 0; 2679 bool x_cap_update = false; 2680 u8 pre_x_cap = cfo->crystal_cap; 2681 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft; 2682 2683 cfo->dcfo_avg = 0; 2684 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", 2685 rtwdev->total_sta_assoc); 2686 if (rtwdev->total_sta_assoc == 0) { 2687 rtw89_phy_cfo_reset(rtwdev); 2688 return; 2689 } 2690 if (cfo->packet_count == 0) { 2691 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); 2692 return; 2693 } 2694 if (cfo->packet_count == cfo->packet_count_pre) { 2695 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); 2696 return; 2697 } 2698 if (rtwdev->total_sta_assoc == 1) 2699 new_cfo = rtw89_phy_average_cfo_calc(rtwdev); 2700 else 2701 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); 2702 if (new_cfo == 0) { 2703 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); 2704 return; 2705 } 2706 if (cfo->divergence_lock_en) { 2707 cfo->lock_cnt++; 2708 if (cfo->lock_cnt > CFO_PERIOD_CNT) { 2709 cfo->divergence_lock_en = false; 2710 cfo->lock_cnt = 0; 2711 } else { 2712 rtw89_phy_cfo_reset(rtwdev); 2713 } 2714 return; 2715 } 2716 if (cfo->crystal_cap >= cfo->x_cap_ub || 2717 cfo->crystal_cap <= cfo->x_cap_lb) { 2718 cfo->divergence_lock_en = true; 2719 rtw89_phy_cfo_reset(rtwdev); 2720 return; 2721 } 2722 2723 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); 2724 cfo->cfo_avg_pre = new_cfo; 2725 cfo->dcfo_avg_pre = cfo->dcfo_avg; 2726 x_cap_update = cfo->crystal_cap != pre_x_cap; 2727 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); 2728 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", 2729 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, 2730 cfo->x_cap_ofst); 2731 if (x_cap_update) { 2732 if (cfo->dcfo_avg > 0) 2733 cfo->dcfo_avg -= CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft; 2734 else 2735 cfo->dcfo_avg += CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft; 2736 } 2737 rtw89_dcfo_comp(rtwdev, cfo->dcfo_avg); 2738 rtw89_phy_cfo_statistics_reset(rtwdev); 2739 } 2740 2741 void rtw89_phy_cfo_track_work(struct work_struct *work) 2742 { 2743 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2744 cfo_track_work.work); 2745 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2746 2747 mutex_lock(&rtwdev->mutex); 2748 if (!cfo->cfo_trig_by_timer_en) 2749 goto out; 2750 rtw89_leave_ps_mode(rtwdev); 2751 rtw89_phy_cfo_dm(rtwdev); 2752 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2753 msecs_to_jiffies(cfo->cfo_timer_ms)); 2754 out: 2755 mutex_unlock(&rtwdev->mutex); 2756 } 2757 2758 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) 2759 { 2760 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2761 2762 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2763 msecs_to_jiffies(cfo->cfo_timer_ms)); 2764 } 2765 2766 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) 2767 { 2768 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2769 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2770 bool is_ul_ofdma = false, ofdma_acc_en = false; 2771 2772 if (stats->rx_tf_periodic > CFO_TF_CNT_TH) 2773 is_ul_ofdma = true; 2774 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE && 2775 is_ul_ofdma) 2776 ofdma_acc_en = true; 2777 2778 switch (cfo->phy_cfo_status) { 2779 case RTW89_PHY_DCFO_STATE_NORMAL: 2780 if (stats->tx_throughput >= CFO_TP_UPPER) { 2781 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; 2782 cfo->cfo_trig_by_timer_en = true; 2783 cfo->cfo_timer_ms = CFO_COMP_PERIOD; 2784 rtw89_phy_cfo_start_work(rtwdev); 2785 } 2786 break; 2787 case RTW89_PHY_DCFO_STATE_ENHANCE: 2788 if (stats->tx_throughput <= CFO_TP_LOWER) 2789 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2790 else if (ofdma_acc_en && 2791 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) 2792 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD; 2793 else 2794 cfo->phy_cfo_trk_cnt++; 2795 2796 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) { 2797 cfo->phy_cfo_trk_cnt = 0; 2798 cfo->cfo_trig_by_timer_en = false; 2799 } 2800 break; 2801 case RTW89_PHY_DCFO_STATE_HOLD: 2802 if (stats->tx_throughput <= CFO_TP_LOWER) { 2803 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2804 cfo->phy_cfo_trk_cnt = 0; 2805 cfo->cfo_trig_by_timer_en = false; 2806 } else { 2807 cfo->phy_cfo_trk_cnt++; 2808 } 2809 break; 2810 default: 2811 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2812 cfo->phy_cfo_trk_cnt = 0; 2813 break; 2814 } 2815 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2816 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", 2817 stats->tx_throughput, cfo->phy_cfo_status, 2818 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, 2819 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); 2820 if (cfo->cfo_trig_by_timer_en) 2821 return; 2822 rtw89_phy_cfo_dm(rtwdev); 2823 } 2824 2825 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 2826 struct rtw89_rx_phy_ppdu *phy_ppdu) 2827 { 2828 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2829 u8 macid = phy_ppdu->mac_id; 2830 2831 if (macid >= CFO_TRACK_MAX_USER) { 2832 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid); 2833 return; 2834 } 2835 2836 cfo->cfo_tail[macid] += cfo_val; 2837 cfo->cfo_cnt[macid]++; 2838 cfo->packet_count++; 2839 } 2840 2841 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2842 { 2843 const struct rtw89_chip_info *chip = rtwdev->chip; 2844 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 2845 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 2846 2847 if (!chip->support_ul_tb_ctrl) 2848 return; 2849 2850 rtwvif->def_tri_idx = 2851 rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG); 2852 2853 if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV) 2854 rtwvif->dyn_tb_bedge_en = false; 2855 else if (chan->band_type >= RTW89_BAND_5G && 2856 chan->band_width >= RTW89_CHANNEL_WIDTH_40) 2857 rtwvif->dyn_tb_bedge_en = true; 2858 else 2859 rtwvif->dyn_tb_bedge_en = false; 2860 2861 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2862 "[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n", 2863 ul_tb_info->def_if_bandedge, rtwvif->def_tri_idx); 2864 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2865 "[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n", 2866 rtwvif->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en); 2867 } 2868 2869 struct rtw89_phy_ul_tb_check_data { 2870 bool valid; 2871 bool high_tf_client; 2872 bool low_tf_client; 2873 bool dyn_tb_bedge_en; 2874 u8 def_tri_idx; 2875 }; 2876 2877 static 2878 void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev, 2879 struct rtw89_vif *rtwvif, 2880 struct rtw89_phy_ul_tb_check_data *ul_tb_data) 2881 { 2882 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2883 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2884 2885 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 2886 return; 2887 2888 if (!vif->cfg.assoc) 2889 return; 2890 2891 if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH) 2892 ul_tb_data->high_tf_client = true; 2893 else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH) 2894 ul_tb_data->low_tf_client = true; 2895 2896 ul_tb_data->valid = true; 2897 ul_tb_data->def_tri_idx = rtwvif->def_tri_idx; 2898 ul_tb_data->dyn_tb_bedge_en = rtwvif->dyn_tb_bedge_en; 2899 } 2900 2901 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev) 2902 { 2903 const struct rtw89_chip_info *chip = rtwdev->chip; 2904 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 2905 struct rtw89_phy_ul_tb_check_data ul_tb_data = {}; 2906 struct rtw89_vif *rtwvif; 2907 2908 if (!chip->support_ul_tb_ctrl) 2909 return; 2910 2911 if (rtwdev->total_sta_assoc != 1) 2912 return; 2913 2914 rtw89_for_each_rtwvif(rtwdev, rtwvif) 2915 rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif, &ul_tb_data); 2916 2917 if (!ul_tb_data.valid) 2918 return; 2919 2920 if (ul_tb_data.dyn_tb_bedge_en) { 2921 if (ul_tb_data.high_tf_client) { 2922 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0); 2923 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2924 "[ULTB] Turn off if_bandedge\n"); 2925 } else if (ul_tb_data.low_tf_client) { 2926 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 2927 ul_tb_info->def_if_bandedge); 2928 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2929 "[ULTB] Set to default if_bandedge = %d\n", 2930 ul_tb_info->def_if_bandedge); 2931 } 2932 } 2933 2934 if (ul_tb_info->dyn_tb_tri_en) { 2935 if (ul_tb_data.high_tf_client) { 2936 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 2937 B_TXSHAPE_TRIANGULAR_CFG, 0); 2938 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2939 "[ULTB] Turn off Tx triangle\n"); 2940 } else if (ul_tb_data.low_tf_client) { 2941 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 2942 B_TXSHAPE_TRIANGULAR_CFG, 2943 ul_tb_data.def_tri_idx); 2944 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2945 "[ULTB] Set to default tx_shap_idx = %d\n", 2946 ul_tb_data.def_tri_idx); 2947 } 2948 } 2949 } 2950 2951 static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev) 2952 { 2953 const struct rtw89_chip_info *chip = rtwdev->chip; 2954 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 2955 2956 if (!chip->support_ul_tb_ctrl) 2957 return; 2958 2959 ul_tb_info->dyn_tb_tri_en = true; 2960 ul_tb_info->def_if_bandedge = 2961 rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN); 2962 } 2963 2964 static 2965 void rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats *antdiv_sts) 2966 { 2967 ewma_rssi_init(&antdiv_sts->cck_rssi_avg); 2968 ewma_rssi_init(&antdiv_sts->ofdm_rssi_avg); 2969 ewma_rssi_init(&antdiv_sts->non_legacy_rssi_avg); 2970 antdiv_sts->pkt_cnt_cck = 0; 2971 antdiv_sts->pkt_cnt_ofdm = 0; 2972 antdiv_sts->pkt_cnt_non_legacy = 0; 2973 antdiv_sts->evm = 0; 2974 } 2975 2976 static void rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev *rtwdev, 2977 struct rtw89_rx_phy_ppdu *phy_ppdu, 2978 struct rtw89_antdiv_stats *stats) 2979 { 2980 if (GET_DATA_RATE_MODE(phy_ppdu->rate) == DATA_RATE_MODE_NON_HT) { 2981 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) { 2982 ewma_rssi_add(&stats->cck_rssi_avg, phy_ppdu->rssi_avg); 2983 stats->pkt_cnt_cck++; 2984 } else { 2985 ewma_rssi_add(&stats->ofdm_rssi_avg, phy_ppdu->rssi_avg); 2986 stats->pkt_cnt_ofdm++; 2987 stats->evm += phy_ppdu->ofdm.evm_min; 2988 } 2989 } else { 2990 ewma_rssi_add(&stats->non_legacy_rssi_avg, phy_ppdu->rssi_avg); 2991 stats->pkt_cnt_non_legacy++; 2992 stats->evm += phy_ppdu->ofdm.evm_min; 2993 } 2994 } 2995 2996 static u8 rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats *stats) 2997 { 2998 if (stats->pkt_cnt_non_legacy >= stats->pkt_cnt_cck && 2999 stats->pkt_cnt_non_legacy >= stats->pkt_cnt_ofdm) 3000 return ewma_rssi_read(&stats->non_legacy_rssi_avg); 3001 else if (stats->pkt_cnt_ofdm >= stats->pkt_cnt_cck && 3002 stats->pkt_cnt_ofdm >= stats->pkt_cnt_non_legacy) 3003 return ewma_rssi_read(&stats->ofdm_rssi_avg); 3004 else 3005 return ewma_rssi_read(&stats->cck_rssi_avg); 3006 } 3007 3008 static u8 rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats *stats) 3009 { 3010 return phy_div(stats->evm, stats->pkt_cnt_non_legacy + stats->pkt_cnt_ofdm); 3011 } 3012 3013 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev, 3014 struct rtw89_rx_phy_ppdu *phy_ppdu) 3015 { 3016 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 3017 struct rtw89_hal *hal = &rtwdev->hal; 3018 3019 if (!hal->ant_diversity || hal->ant_diversity_fixed) 3020 return; 3021 3022 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->target_stats); 3023 3024 if (!antdiv->get_stats) 3025 return; 3026 3027 if (hal->antenna_rx == RF_A) 3028 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->main_stats); 3029 else if (hal->antenna_rx == RF_B) 3030 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->aux_stats); 3031 } 3032 3033 static void rtw89_phy_antdiv_reg_init(struct rtw89_dev *rtwdev) 3034 { 3035 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_ANT_TRAIN_EN, 3036 0x0, RTW89_PHY_0); 3037 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_TX_ANT_SEL, 3038 0x0, RTW89_PHY_0); 3039 3040 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_TRSW_TX_EXTEND, 3041 0x0, RTW89_PHY_0); 3042 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_HW_ANTSW_DIS_BY_GNT_BT, 3043 0x0, RTW89_PHY_0); 3044 3045 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_BT_FORCE_ANTIDX_EN, 3046 0x0, RTW89_PHY_0); 3047 3048 rtw89_phy_write32_idx(rtwdev, R_RFSW_CTRL_ANT0_BASE, B_RFSW_CTRL_ANT_MAPPING, 3049 0x0100, RTW89_PHY_0); 3050 3051 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_BTG_TRX, 3052 0x1, RTW89_PHY_0); 3053 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_HW_CTRL, 3054 0x0, RTW89_PHY_0); 3055 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_2G, 3056 0x0, RTW89_PHY_0); 3057 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_5G, 3058 0x0, RTW89_PHY_0); 3059 } 3060 3061 static void rtw89_phy_antdiv_sts_reset(struct rtw89_dev *rtwdev) 3062 { 3063 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 3064 3065 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats); 3066 rtw89_phy_antdiv_sts_instance_reset(&antdiv->main_stats); 3067 rtw89_phy_antdiv_sts_instance_reset(&antdiv->aux_stats); 3068 } 3069 3070 static void rtw89_phy_antdiv_init(struct rtw89_dev *rtwdev) 3071 { 3072 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 3073 struct rtw89_hal *hal = &rtwdev->hal; 3074 3075 if (!hal->ant_diversity) 3076 return; 3077 3078 antdiv->get_stats = false; 3079 antdiv->rssi_pre = 0; 3080 rtw89_phy_antdiv_sts_reset(rtwdev); 3081 rtw89_phy_antdiv_reg_init(rtwdev); 3082 } 3083 3084 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) 3085 { 3086 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 3087 int i; 3088 u8 th; 3089 3090 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 3091 th = rtw89_chip_get_thermal(rtwdev, i); 3092 if (th) 3093 ewma_thermal_add(&phystat->avg_thermal[i], th); 3094 3095 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 3096 "path(%d) thermal cur=%u avg=%ld", i, th, 3097 ewma_thermal_read(&phystat->avg_thermal[i])); 3098 } 3099 } 3100 3101 struct rtw89_phy_iter_rssi_data { 3102 struct rtw89_dev *rtwdev; 3103 struct rtw89_phy_ch_info *ch_info; 3104 bool rssi_changed; 3105 }; 3106 3107 static void rtw89_phy_stat_rssi_update_iter(void *data, 3108 struct ieee80211_sta *sta) 3109 { 3110 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3111 struct rtw89_phy_iter_rssi_data *rssi_data = 3112 (struct rtw89_phy_iter_rssi_data *)data; 3113 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info; 3114 unsigned long rssi_curr; 3115 3116 rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi); 3117 3118 if (rssi_curr < ch_info->rssi_min) { 3119 ch_info->rssi_min = rssi_curr; 3120 ch_info->rssi_min_macid = rtwsta->mac_id; 3121 } 3122 3123 if (rtwsta->prev_rssi == 0) { 3124 rtwsta->prev_rssi = rssi_curr; 3125 } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) { 3126 rtwsta->prev_rssi = rssi_curr; 3127 rssi_data->rssi_changed = true; 3128 } 3129 } 3130 3131 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) 3132 { 3133 struct rtw89_phy_iter_rssi_data rssi_data = {0}; 3134 3135 rssi_data.rtwdev = rtwdev; 3136 rssi_data.ch_info = &rtwdev->ch_info; 3137 rssi_data.ch_info->rssi_min = U8_MAX; 3138 ieee80211_iterate_stations_atomic(rtwdev->hw, 3139 rtw89_phy_stat_rssi_update_iter, 3140 &rssi_data); 3141 if (rssi_data.rssi_changed) 3142 rtw89_btc_ntfy_wl_sta(rtwdev); 3143 } 3144 3145 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) 3146 { 3147 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 3148 int i; 3149 3150 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 3151 ewma_thermal_init(&phystat->avg_thermal[i]); 3152 3153 rtw89_phy_stat_thermal_update(rtwdev); 3154 3155 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 3156 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); 3157 } 3158 3159 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) 3160 { 3161 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 3162 3163 rtw89_phy_stat_thermal_update(rtwdev); 3164 rtw89_phy_stat_rssi_update(rtwdev); 3165 3166 phystat->last_pkt_stat = phystat->cur_pkt_stat; 3167 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 3168 } 3169 3170 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us) 3171 { 3172 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3173 3174 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 3175 } 3176 3177 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) 3178 { 3179 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3180 3181 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 3182 } 3183 3184 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) 3185 { 3186 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3187 3188 env->ccx_manual_ctrl = false; 3189 env->ccx_ongoing = false; 3190 env->ccx_rac_lv = RTW89_RAC_RELEASE; 3191 env->ccx_rpt_stamp = 0; 3192 env->ccx_period = 0; 3193 env->ccx_unit_idx = RTW89_CCX_32_US; 3194 env->ccx_trigger_time = 0; 3195 env->ccx_edcca_opt_bw_idx = RTW89_CCX_EDCCA_BW20_0; 3196 3197 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1); 3198 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1); 3199 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 3200 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EDCCA_OPT_MSK, 3201 RTW89_CCX_EDCCA_BW20_0); 3202 } 3203 3204 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report, 3205 u16 score) 3206 { 3207 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3208 u32 numer = 0; 3209 u16 ret = 0; 3210 3211 numer = report * score + (env->ccx_period >> 1); 3212 if (env->ccx_period) 3213 ret = numer / env->ccx_period; 3214 3215 return ret >= score ? score - 1 : ret; 3216 } 3217 3218 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, 3219 u16 time_ms, u32 *period, 3220 u32 *unit_idx) 3221 { 3222 u32 idx; 3223 u8 quotient; 3224 3225 if (time_ms >= CCX_MAX_PERIOD) 3226 time_ms = CCX_MAX_PERIOD; 3227 3228 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; 3229 3230 if (quotient < 4) 3231 idx = RTW89_CCX_4_US; 3232 else if (quotient < 8) 3233 idx = RTW89_CCX_8_US; 3234 else if (quotient < 16) 3235 idx = RTW89_CCX_16_US; 3236 else 3237 idx = RTW89_CCX_32_US; 3238 3239 *unit_idx = idx; 3240 *period = (time_ms * MS_TO_4US_RATIO) >> idx; 3241 3242 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3243 "[Trigger Time] period:%d, unit_idx:%d\n", 3244 *period, *unit_idx); 3245 } 3246 3247 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev) 3248 { 3249 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3250 3251 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3252 "lv:(%d)->(0)\n", env->ccx_rac_lv); 3253 3254 env->ccx_ongoing = false; 3255 env->ccx_rac_lv = RTW89_RAC_RELEASE; 3256 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3257 } 3258 3259 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, 3260 struct rtw89_ccx_para_info *para) 3261 { 3262 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3263 bool is_update = env->ifs_clm_app != para->ifs_clm_app; 3264 u8 i = 0; 3265 u16 *ifs_th_l = env->ifs_clm_th_l; 3266 u16 *ifs_th_h = env->ifs_clm_th_h; 3267 u32 ifs_th0_us = 0, ifs_th_times = 0; 3268 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; 3269 3270 if (!is_update) 3271 goto ifs_update_finished; 3272 3273 switch (para->ifs_clm_app) { 3274 case RTW89_IFS_CLM_INIT: 3275 case RTW89_IFS_CLM_BACKGROUND: 3276 case RTW89_IFS_CLM_ACS: 3277 case RTW89_IFS_CLM_DBG: 3278 case RTW89_IFS_CLM_DIG: 3279 case RTW89_IFS_CLM_TDMA_DIG: 3280 ifs_th0_us = IFS_CLM_TH0_UPPER; 3281 ifs_th_times = IFS_CLM_TH_MUL; 3282 break; 3283 case RTW89_IFS_CLM_DBG_MANUAL: 3284 ifs_th0_us = para->ifs_clm_manual_th0; 3285 ifs_th_times = para->ifs_clm_manual_th_times; 3286 break; 3287 default: 3288 break; 3289 } 3290 3291 /* Set sampling threshold for 4 different regions, unit in idx_cnt. 3292 * low[i] = high[i-1] + 1 3293 * high[i] = high[i-1] * ifs_th_times 3294 */ 3295 ifs_th_l[IFS_CLM_TH_START_IDX] = 0; 3296 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; 3297 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, 3298 ifs_th0_us); 3299 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { 3300 ifs_th_l[i] = ifs_th_h[i - 1] + 1; 3301 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; 3302 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]); 3303 } 3304 3305 ifs_update_finished: 3306 if (!is_update) 3307 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3308 "No need to update IFS_TH\n"); 3309 3310 return is_update; 3311 } 3312 3313 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) 3314 { 3315 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3316 u8 i = 0; 3317 3318 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_LOW_MSK, 3319 env->ifs_clm_th_l[0]); 3320 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_LOW_MSK, 3321 env->ifs_clm_th_l[1]); 3322 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_LOW_MSK, 3323 env->ifs_clm_th_l[2]); 3324 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_LOW_MSK, 3325 env->ifs_clm_th_l[3]); 3326 3327 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_HIGH_MSK, 3328 env->ifs_clm_th_h[0]); 3329 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_HIGH_MSK, 3330 env->ifs_clm_th_h[1]); 3331 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_HIGH_MSK, 3332 env->ifs_clm_th_h[2]); 3333 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_HIGH_MSK, 3334 env->ifs_clm_th_h[3]); 3335 3336 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3337 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3338 "Update IFS_T%d_th{low, high} : {%d, %d}\n", 3339 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 3340 } 3341 3342 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) 3343 { 3344 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3345 struct rtw89_ccx_para_info para = {0}; 3346 3347 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3348 env->ifs_clm_mntr_time = 0; 3349 3350 para.ifs_clm_app = RTW89_IFS_CLM_INIT; 3351 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) 3352 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 3353 3354 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COLLECT_EN, 3355 true); 3356 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_EN_MSK, true); 3357 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_EN_MSK, true); 3358 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_EN_MSK, true); 3359 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_EN_MSK, true); 3360 } 3361 3362 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, 3363 enum rtw89_env_racing_lv level) 3364 { 3365 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3366 int ret = 0; 3367 3368 if (level >= RTW89_RAC_MAX_NUM) { 3369 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3370 "[WARNING] Wrong LV=%d\n", level); 3371 return -EINVAL; 3372 } 3373 3374 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3375 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, 3376 env->ccx_rac_lv, level); 3377 3378 if (env->ccx_ongoing) { 3379 if (level <= env->ccx_rac_lv) 3380 ret = -EINVAL; 3381 else 3382 env->ccx_ongoing = false; 3383 } 3384 3385 if (ret == 0) 3386 env->ccx_rac_lv = level; 3387 3388 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", 3389 !ret); 3390 3391 return ret; 3392 } 3393 3394 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) 3395 { 3396 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3397 3398 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 0); 3399 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 0); 3400 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1); 3401 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 3402 3403 env->ccx_rpt_stamp++; 3404 env->ccx_ongoing = true; 3405 } 3406 3407 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) 3408 { 3409 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3410 u8 i = 0; 3411 u32 res = 0; 3412 3413 env->ifs_clm_tx_ratio = 3414 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT); 3415 env->ifs_clm_edcca_excl_cca_ratio = 3416 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca, 3417 PERCENT); 3418 env->ifs_clm_cck_fa_ratio = 3419 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT); 3420 env->ifs_clm_ofdm_fa_ratio = 3421 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT); 3422 env->ifs_clm_cck_cca_excl_fa_ratio = 3423 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa, 3424 PERCENT); 3425 env->ifs_clm_ofdm_cca_excl_fa_ratio = 3426 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa, 3427 PERCENT); 3428 env->ifs_clm_cck_fa_permil = 3429 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL); 3430 env->ifs_clm_ofdm_fa_permil = 3431 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL); 3432 3433 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { 3434 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { 3435 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; 3436 } else { 3437 env->ifs_clm_ifs_avg[i] = 3438 rtw89_phy_ccx_idx_to_us(rtwdev, 3439 env->ifs_clm_avg[i]); 3440 } 3441 3442 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]); 3443 res += env->ifs_clm_his[i] >> 1; 3444 if (env->ifs_clm_his[i]) 3445 res /= env->ifs_clm_his[i]; 3446 else 3447 res = 0; 3448 env->ifs_clm_cca_avg[i] = res; 3449 } 3450 3451 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3452 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", 3453 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); 3454 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3455 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", 3456 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); 3457 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3458 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", 3459 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); 3460 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3461 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", 3462 env->ifs_clm_cck_cca_excl_fa_ratio, 3463 env->ifs_clm_ofdm_cca_excl_fa_ratio); 3464 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3465 "Time:[his, ifs_avg(us), cca_avg(us)]\n"); 3466 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3467 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 3468 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 3469 env->ifs_clm_cca_avg[i]); 3470 } 3471 3472 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) 3473 { 3474 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3475 u8 i = 0; 3476 3477 if (rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_DONE_MSK) == 0) { 3478 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3479 "Get IFS_CLM report Fail\n"); 3480 return false; 3481 } 3482 3483 env->ifs_clm_tx = 3484 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 3485 B_IFS_CLM_TX_CNT_MSK); 3486 env->ifs_clm_edcca_excl_cca = 3487 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 3488 B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK); 3489 env->ifs_clm_cckcca_excl_fa = 3490 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 3491 B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK); 3492 env->ifs_clm_ofdmcca_excl_fa = 3493 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 3494 B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK); 3495 env->ifs_clm_cckfa = 3496 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 3497 B_IFS_CLM_CCK_FA_MSK); 3498 env->ifs_clm_ofdmfa = 3499 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 3500 B_IFS_CLM_OFDM_FA_MSK); 3501 3502 env->ifs_clm_his[0] = 3503 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T1_HIS_MSK); 3504 env->ifs_clm_his[1] = 3505 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T2_HIS_MSK); 3506 env->ifs_clm_his[2] = 3507 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T3_HIS_MSK); 3508 env->ifs_clm_his[3] = 3509 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T4_HIS_MSK); 3510 3511 env->ifs_clm_avg[0] = 3512 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T1_AVG_MSK); 3513 env->ifs_clm_avg[1] = 3514 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T2_AVG_MSK); 3515 env->ifs_clm_avg[2] = 3516 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T3_AVG_MSK); 3517 env->ifs_clm_avg[3] = 3518 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T4_AVG_MSK); 3519 3520 env->ifs_clm_cca[0] = 3521 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T1_CCA_MSK); 3522 env->ifs_clm_cca[1] = 3523 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T2_CCA_MSK); 3524 env->ifs_clm_cca[2] = 3525 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T3_CCA_MSK); 3526 env->ifs_clm_cca[3] = 3527 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T4_CCA_MSK); 3528 3529 env->ifs_clm_total_ifs = 3530 rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_TOTAL_CNT_MSK); 3531 3532 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", 3533 env->ifs_clm_total_ifs); 3534 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3535 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", 3536 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); 3537 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3538 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", 3539 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); 3540 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3541 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", 3542 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); 3543 3544 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); 3545 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3546 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3547 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], 3548 env->ifs_clm_avg[i], env->ifs_clm_cca[i]); 3549 3550 rtw89_phy_ifs_clm_get_utility(rtwdev); 3551 3552 return true; 3553 } 3554 3555 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 3556 struct rtw89_ccx_para_info *para) 3557 { 3558 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3559 u32 period = 0; 3560 u32 unit_idx = 0; 3561 3562 if (para->mntr_time == 0) { 3563 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3564 "[WARN] MNTR_TIME is 0\n"); 3565 return -EINVAL; 3566 } 3567 3568 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv)) 3569 return -EINVAL; 3570 3571 if (para->mntr_time != env->ifs_clm_mntr_time) { 3572 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 3573 &period, &unit_idx); 3574 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 3575 B_IFS_CLM_PERIOD_MSK, period); 3576 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 3577 B_IFS_CLM_COUNTER_UNIT_MSK, unit_idx); 3578 3579 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3580 "Update IFS-CLM time ((%d)) -> ((%d))\n", 3581 env->ifs_clm_mntr_time, para->mntr_time); 3582 3583 env->ifs_clm_mntr_time = para->mntr_time; 3584 env->ccx_period = (u16)period; 3585 env->ccx_unit_idx = (u8)unit_idx; 3586 } 3587 3588 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) { 3589 env->ifs_clm_app = para->ifs_clm_app; 3590 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 3591 } 3592 3593 return 0; 3594 } 3595 3596 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) 3597 { 3598 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3599 struct rtw89_ccx_para_info para = {0}; 3600 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3601 3602 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3603 if (env->ccx_manual_ctrl) { 3604 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3605 "CCX in manual ctrl\n"); 3606 return; 3607 } 3608 3609 /* only ifs_clm for now */ 3610 if (rtw89_phy_ifs_clm_get_result(rtwdev)) 3611 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3612 3613 rtw89_phy_ccx_racing_release(rtwdev); 3614 para.mntr_time = 1900; 3615 para.rac_lv = RTW89_RAC_LV_1; 3616 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3617 3618 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0) 3619 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3620 if (chk_result) 3621 rtw89_phy_ccx_trigger(rtwdev); 3622 3623 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3624 "get_result=0x%x, chk_result:0x%x\n", 3625 env->ccx_watchdog_result, chk_result); 3626 } 3627 3628 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page) 3629 { 3630 if (*ie_page >= RTW89_PHYSTS_BITMAP_NUM || 3631 *ie_page == RTW89_RSVD_9) 3632 return false; 3633 else if (*ie_page > RTW89_RSVD_9) 3634 *ie_page -= 1; 3635 3636 return true; 3637 } 3638 3639 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) 3640 { 3641 static const u8 ie_page_shift = 2; 3642 3643 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); 3644 } 3645 3646 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, 3647 enum rtw89_phy_status_bitmap ie_page) 3648 { 3649 u32 addr; 3650 3651 if (!rtw89_physts_ie_page_valid(&ie_page)) 3652 return 0; 3653 3654 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3655 3656 return rtw89_phy_read32(rtwdev, addr); 3657 } 3658 3659 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, 3660 enum rtw89_phy_status_bitmap ie_page, 3661 u32 val) 3662 { 3663 const struct rtw89_chip_info *chip = rtwdev->chip; 3664 u32 addr; 3665 3666 if (!rtw89_physts_ie_page_valid(&ie_page)) 3667 return; 3668 3669 if (chip->chip_id == RTL8852A) 3670 val &= B_PHY_STS_BITMAP_MSK_52A; 3671 3672 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3673 rtw89_phy_write32(rtwdev, addr, val); 3674 } 3675 3676 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev, 3677 enum rtw89_phy_status_bitmap bitmap, 3678 enum rtw89_phy_status_ie_type ie, 3679 bool enable) 3680 { 3681 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap); 3682 3683 if (enable) 3684 val |= BIT(ie); 3685 else 3686 val &= ~BIT(ie); 3687 3688 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val); 3689 } 3690 3691 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, 3692 bool enable, 3693 enum rtw89_phy_idx phy_idx) 3694 { 3695 if (enable) { 3696 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3697 B_STS_DIS_TRIG_BY_FAIL); 3698 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3699 B_STS_DIS_TRIG_BY_BRK); 3700 } else { 3701 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3702 B_STS_DIS_TRIG_BY_FAIL); 3703 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3704 B_STS_DIS_TRIG_BY_BRK); 3705 } 3706 } 3707 3708 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev) 3709 { 3710 u8 i; 3711 3712 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0); 3713 3714 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { 3715 if (i >= RTW89_CCK_PKT) 3716 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3717 RTW89_PHYSTS_IE09_FTR_0, 3718 true); 3719 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) || 3720 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT)) 3721 continue; 3722 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3723 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A, 3724 true); 3725 } 3726 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT, 3727 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3728 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT, 3729 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3730 3731 /* force IE01 for channel index, only channel field is valid */ 3732 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT, 3733 RTW89_PHYSTS_IE01_CMN_OFDM, true); 3734 } 3735 3736 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) 3737 { 3738 const struct rtw89_chip_info *chip = rtwdev->chip; 3739 struct rtw89_dig_info *dig = &rtwdev->dig; 3740 const struct rtw89_phy_dig_gain_cfg *cfg; 3741 const char *msg; 3742 u8 i; 3743 s8 gain_base; 3744 s8 *gain_arr; 3745 u32 tmp; 3746 3747 switch (type) { 3748 case RTW89_DIG_GAIN_LNA_G: 3749 gain_arr = dig->lna_gain_g; 3750 gain_base = LNA0_GAIN; 3751 cfg = chip->dig_table->cfg_lna_g; 3752 msg = "lna_gain_g"; 3753 break; 3754 case RTW89_DIG_GAIN_TIA_G: 3755 gain_arr = dig->tia_gain_g; 3756 gain_base = TIA0_GAIN_G; 3757 cfg = chip->dig_table->cfg_tia_g; 3758 msg = "tia_gain_g"; 3759 break; 3760 case RTW89_DIG_GAIN_LNA_A: 3761 gain_arr = dig->lna_gain_a; 3762 gain_base = LNA0_GAIN; 3763 cfg = chip->dig_table->cfg_lna_a; 3764 msg = "lna_gain_a"; 3765 break; 3766 case RTW89_DIG_GAIN_TIA_A: 3767 gain_arr = dig->tia_gain_a; 3768 gain_base = TIA0_GAIN_A; 3769 cfg = chip->dig_table->cfg_tia_a; 3770 msg = "tia_gain_a"; 3771 break; 3772 default: 3773 return; 3774 } 3775 3776 for (i = 0; i < cfg->size; i++) { 3777 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr, 3778 cfg->table[i].mask); 3779 tmp >>= DIG_GAIN_SHIFT; 3780 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; 3781 gain_base += DIG_GAIN; 3782 3783 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", 3784 msg, i, gain_arr[i]); 3785 } 3786 } 3787 3788 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev) 3789 { 3790 struct rtw89_dig_info *dig = &rtwdev->dig; 3791 u32 tmp; 3792 u8 i; 3793 3794 if (!rtwdev->hal.support_igi) 3795 return; 3796 3797 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW, 3798 B_PATH0_IB_PKPW_MSK); 3799 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); 3800 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK, 3801 B_PATH0_IB_PBK_MSK); 3802 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", 3803 dig->ib_pkpwr, dig->ib_pbk); 3804 3805 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) 3806 rtw89_phy_dig_read_gain_table(rtwdev, i); 3807 } 3808 3809 static const u8 rssi_nolink = 22; 3810 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; 3811 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; 3812 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; 3813 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; 3814 3815 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev) 3816 { 3817 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 3818 struct rtw89_dig_info *dig = &rtwdev->dig; 3819 bool is_linked = rtwdev->total_sta_assoc > 0; 3820 3821 if (is_linked) { 3822 dig->igi_rssi = ch_info->rssi_min >> 1; 3823 } else { 3824 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); 3825 dig->igi_rssi = rssi_nolink; 3826 } 3827 } 3828 3829 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev) 3830 { 3831 struct rtw89_dig_info *dig = &rtwdev->dig; 3832 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3833 bool is_linked = rtwdev->total_sta_assoc > 0; 3834 const u16 *fa_th_src = NULL; 3835 3836 switch (chan->band_type) { 3837 case RTW89_BAND_2G: 3838 dig->lna_gain = dig->lna_gain_g; 3839 dig->tia_gain = dig->tia_gain_g; 3840 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; 3841 dig->force_gaincode_idx_en = false; 3842 dig->dyn_pd_th_en = true; 3843 break; 3844 case RTW89_BAND_5G: 3845 default: 3846 dig->lna_gain = dig->lna_gain_a; 3847 dig->tia_gain = dig->tia_gain_a; 3848 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; 3849 dig->force_gaincode_idx_en = true; 3850 dig->dyn_pd_th_en = true; 3851 break; 3852 } 3853 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); 3854 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); 3855 } 3856 3857 static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20; 3858 static const u8 igi_max_performance_mode = 0x5a; 3859 static const u8 dynamic_pd_threshold_max; 3860 3861 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev) 3862 { 3863 struct rtw89_dig_info *dig = &rtwdev->dig; 3864 3865 dig->cur_gaincode.lna_idx = LNA_IDX_MAX; 3866 dig->cur_gaincode.tia_idx = TIA_IDX_MAX; 3867 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; 3868 dig->force_gaincode.lna_idx = LNA_IDX_MAX; 3869 dig->force_gaincode.tia_idx = TIA_IDX_MAX; 3870 dig->force_gaincode.rxb_idx = RXB_IDX_MAX; 3871 3872 dig->dyn_igi_max = igi_max_performance_mode; 3873 dig->dyn_igi_min = dynamic_igi_min; 3874 dig->dyn_pd_th_max = dynamic_pd_threshold_max; 3875 dig->pd_low_th_ofst = pd_low_th_offset; 3876 dig->is_linked_pre = false; 3877 } 3878 3879 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) 3880 { 3881 rtw89_phy_dig_update_gain_para(rtwdev); 3882 rtw89_phy_dig_reset(rtwdev); 3883 } 3884 3885 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3886 { 3887 struct rtw89_dig_info *dig = &rtwdev->dig; 3888 u8 lna_idx; 3889 3890 if (rssi < dig->igi_rssi_th[0]) 3891 lna_idx = RTW89_DIG_GAIN_LNA_IDX6; 3892 else if (rssi < dig->igi_rssi_th[1]) 3893 lna_idx = RTW89_DIG_GAIN_LNA_IDX5; 3894 else if (rssi < dig->igi_rssi_th[2]) 3895 lna_idx = RTW89_DIG_GAIN_LNA_IDX4; 3896 else if (rssi < dig->igi_rssi_th[3]) 3897 lna_idx = RTW89_DIG_GAIN_LNA_IDX3; 3898 else if (rssi < dig->igi_rssi_th[4]) 3899 lna_idx = RTW89_DIG_GAIN_LNA_IDX2; 3900 else 3901 lna_idx = RTW89_DIG_GAIN_LNA_IDX1; 3902 3903 return lna_idx; 3904 } 3905 3906 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3907 { 3908 struct rtw89_dig_info *dig = &rtwdev->dig; 3909 u8 tia_idx; 3910 3911 if (rssi < dig->igi_rssi_th[0]) 3912 tia_idx = RTW89_DIG_GAIN_TIA_IDX1; 3913 else 3914 tia_idx = RTW89_DIG_GAIN_TIA_IDX0; 3915 3916 return tia_idx; 3917 } 3918 3919 #define IB_PBK_BASE 110 3920 #define WB_RSSI_BASE 10 3921 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3922 struct rtw89_agc_gaincode_set *set) 3923 { 3924 struct rtw89_dig_info *dig = &rtwdev->dig; 3925 s8 lna_gain = dig->lna_gain[set->lna_idx]; 3926 s8 tia_gain = dig->tia_gain[set->tia_idx]; 3927 s32 wb_rssi = rssi + lna_gain + tia_gain; 3928 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; 3929 u8 rxb_idx; 3930 3931 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; 3932 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); 3933 3934 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", 3935 wb_rssi, rxb_idx_tmp); 3936 3937 return rxb_idx; 3938 } 3939 3940 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3941 struct rtw89_agc_gaincode_set *set) 3942 { 3943 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi); 3944 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi); 3945 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set); 3946 3947 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3948 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", 3949 rssi, set->lna_idx, set->tia_idx, set->rxb_idx); 3950 } 3951 3952 #define IGI_OFFSET_MAX 25 3953 #define IGI_OFFSET_MUL 2 3954 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev) 3955 { 3956 struct rtw89_dig_info *dig = &rtwdev->dig; 3957 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3958 enum rtw89_dig_noisy_level noisy_lv; 3959 u8 igi_offset = dig->fa_rssi_ofst; 3960 u16 fa_ratio = 0; 3961 3962 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; 3963 3964 if (fa_ratio < dig->fa_th[0]) 3965 noisy_lv = RTW89_DIG_NOISY_LEVEL0; 3966 else if (fa_ratio < dig->fa_th[1]) 3967 noisy_lv = RTW89_DIG_NOISY_LEVEL1; 3968 else if (fa_ratio < dig->fa_th[2]) 3969 noisy_lv = RTW89_DIG_NOISY_LEVEL2; 3970 else if (fa_ratio < dig->fa_th[3]) 3971 noisy_lv = RTW89_DIG_NOISY_LEVEL3; 3972 else 3973 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; 3974 3975 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) 3976 igi_offset = 0; 3977 else 3978 igi_offset += noisy_lv * IGI_OFFSET_MUL; 3979 3980 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); 3981 dig->fa_rssi_ofst = igi_offset; 3982 3983 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3984 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", 3985 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); 3986 3987 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3988 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", 3989 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, 3990 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, 3991 noisy_lv, igi_offset); 3992 } 3993 3994 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx) 3995 { 3996 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3997 3998 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_lna_init.addr, 3999 dig_regs->p0_lna_init.mask, lna_idx); 4000 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_lna_init.addr, 4001 dig_regs->p1_lna_init.mask, lna_idx); 4002 } 4003 4004 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx) 4005 { 4006 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4007 4008 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_tia_init.addr, 4009 dig_regs->p0_tia_init.mask, tia_idx); 4010 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_tia_init.addr, 4011 dig_regs->p1_tia_init.mask, tia_idx); 4012 } 4013 4014 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx) 4015 { 4016 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4017 4018 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_rxb_init.addr, 4019 dig_regs->p0_rxb_init.mask, rxb_idx); 4020 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_rxb_init.addr, 4021 dig_regs->p1_rxb_init.mask, rxb_idx); 4022 } 4023 4024 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, 4025 const struct rtw89_agc_gaincode_set set) 4026 { 4027 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx); 4028 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx); 4029 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx); 4030 4031 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", 4032 set.lna_idx, set.tia_idx, set.rxb_idx); 4033 } 4034 4035 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, 4036 bool enable) 4037 { 4038 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4039 4040 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_p20_pagcugc_en.addr, 4041 dig_regs->p0_p20_pagcugc_en.mask, enable); 4042 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_s20_pagcugc_en.addr, 4043 dig_regs->p0_s20_pagcugc_en.mask, enable); 4044 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_p20_pagcugc_en.addr, 4045 dig_regs->p1_p20_pagcugc_en.mask, enable); 4046 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_s20_pagcugc_en.addr, 4047 dig_regs->p1_s20_pagcugc_en.mask, enable); 4048 4049 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); 4050 } 4051 4052 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev) 4053 { 4054 struct rtw89_dig_info *dig = &rtwdev->dig; 4055 4056 if (!rtwdev->hal.support_igi) 4057 return; 4058 4059 if (dig->force_gaincode_idx_en) { 4060 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 4061 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4062 "Force gaincode index enabled.\n"); 4063 } else { 4064 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi, 4065 &dig->cur_gaincode); 4066 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode); 4067 } 4068 } 4069 4070 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, 4071 bool enable) 4072 { 4073 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 4074 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4075 enum rtw89_bandwidth cbw = chan->band_width; 4076 struct rtw89_dig_info *dig = &rtwdev->dig; 4077 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; 4078 u8 ofdm_cca_th; 4079 s8 cck_cca_th; 4080 u32 pd_val = 0; 4081 4082 under_region += PD_TH_SB_FLTR_CMP_VAL; 4083 4084 switch (cbw) { 4085 case RTW89_CHANNEL_WIDTH_40: 4086 under_region += PD_TH_BW40_CMP_VAL; 4087 break; 4088 case RTW89_CHANNEL_WIDTH_80: 4089 under_region += PD_TH_BW80_CMP_VAL; 4090 break; 4091 case RTW89_CHANNEL_WIDTH_160: 4092 under_region += PD_TH_BW160_CMP_VAL; 4093 break; 4094 case RTW89_CHANNEL_WIDTH_20: 4095 fallthrough; 4096 default: 4097 under_region += PD_TH_BW20_CMP_VAL; 4098 break; 4099 } 4100 4101 dig->dyn_pd_th_max = dig->igi_rssi; 4102 4103 final_rssi = min_t(u8, rssi, dig->igi_rssi); 4104 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, 4105 PD_TH_MAX_RSSI + under_region); 4106 4107 if (enable) { 4108 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1; 4109 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4110 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n", 4111 final_rssi, ofdm_cca_th, under_region, pd_val); 4112 } else { 4113 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4114 "Dynamic PD th disabled, Set PD_low_bd=0\n"); 4115 } 4116 4117 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 4118 dig_regs->pd_lower_bound_mask, pd_val); 4119 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 4120 dig_regs->pd_spatial_reuse_en, enable); 4121 4122 if (!rtwdev->hal.support_cckpd) 4123 return; 4124 4125 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI); 4126 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX); 4127 4128 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4129 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n", 4130 final_rssi, cck_cca_th, under_region, pd_val); 4131 4132 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_EN_V1, 4133 B_BMODE_PDTH_LIMIT_EN_MSK_V1, enable); 4134 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_V1, 4135 B_BMODE_PDTH_LOWER_BOUND_MSK_V1, pd_val); 4136 } 4137 4138 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) 4139 { 4140 struct rtw89_dig_info *dig = &rtwdev->dig; 4141 4142 dig->bypass_dig = false; 4143 rtw89_phy_dig_para_reset(rtwdev); 4144 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 4145 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false); 4146 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 4147 rtw89_phy_dig_update_para(rtwdev); 4148 } 4149 4150 #define IGI_RSSI_MIN 10 4151 void rtw89_phy_dig(struct rtw89_dev *rtwdev) 4152 { 4153 struct rtw89_dig_info *dig = &rtwdev->dig; 4154 bool is_linked = rtwdev->total_sta_assoc > 0; 4155 4156 if (unlikely(dig->bypass_dig)) { 4157 dig->bypass_dig = false; 4158 return; 4159 } 4160 4161 if (!dig->is_linked_pre && is_linked) { 4162 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); 4163 rtw89_phy_dig_update_para(rtwdev); 4164 } else if (dig->is_linked_pre && !is_linked) { 4165 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); 4166 rtw89_phy_dig_update_para(rtwdev); 4167 } 4168 dig->is_linked_pre = is_linked; 4169 4170 rtw89_phy_dig_igi_offset_by_env(rtwdev); 4171 rtw89_phy_dig_update_rssi_info(rtwdev); 4172 4173 dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ? 4174 dig->igi_rssi - IGI_RSSI_MIN : 0; 4175 dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX; 4176 dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst; 4177 4178 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, 4179 dig->dyn_igi_max); 4180 4181 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4182 "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n", 4183 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, 4184 dig->igi_fa_rssi); 4185 4186 rtw89_phy_dig_config_igi(rtwdev); 4187 4188 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en); 4189 4190 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) 4191 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true); 4192 else 4193 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 4194 } 4195 4196 static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta) 4197 { 4198 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 4199 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 4200 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 4201 struct rtw89_hal *hal = &rtwdev->hal; 4202 bool *done = data; 4203 u8 rssi_a, rssi_b; 4204 u32 candidate; 4205 4206 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || sta->tdls) 4207 return; 4208 4209 if (*done) 4210 return; 4211 4212 *done = true; 4213 4214 rssi_a = ewma_rssi_read(&rtwsta->rssi[RF_PATH_A]); 4215 rssi_b = ewma_rssi_read(&rtwsta->rssi[RF_PATH_B]); 4216 4217 if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH) 4218 candidate = RF_A; 4219 else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH) 4220 candidate = RF_B; 4221 else 4222 return; 4223 4224 if (hal->antenna_tx == candidate) 4225 return; 4226 4227 hal->antenna_tx = candidate; 4228 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta); 4229 4230 if (hal->antenna_tx == RF_A) { 4231 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12); 4232 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11); 4233 } else if (hal->antenna_tx == RF_B) { 4234 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11); 4235 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12); 4236 } 4237 } 4238 4239 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev) 4240 { 4241 struct rtw89_hal *hal = &rtwdev->hal; 4242 bool done = false; 4243 4244 if (!hal->tx_path_diversity) 4245 return; 4246 4247 ieee80211_iterate_stations_atomic(rtwdev->hw, 4248 rtw89_phy_tx_path_div_sta_iter, 4249 &done); 4250 } 4251 4252 #define ANTDIV_MAIN 0 4253 #define ANTDIV_AUX 1 4254 4255 static void rtw89_phy_antdiv_set_ant(struct rtw89_dev *rtwdev) 4256 { 4257 struct rtw89_hal *hal = &rtwdev->hal; 4258 u8 default_ant, optional_ant; 4259 4260 if (!hal->ant_diversity || hal->antenna_tx == 0) 4261 return; 4262 4263 if (hal->antenna_tx == RF_B) { 4264 default_ant = ANTDIV_AUX; 4265 optional_ant = ANTDIV_MAIN; 4266 } else { 4267 default_ant = ANTDIV_MAIN; 4268 optional_ant = ANTDIV_AUX; 4269 } 4270 4271 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_CGCS_CTRL, 4272 default_ant, RTW89_PHY_0); 4273 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ORI, 4274 default_ant, RTW89_PHY_0); 4275 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ALT, 4276 optional_ant, RTW89_PHY_0); 4277 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_TX_ORI, 4278 default_ant, RTW89_PHY_0); 4279 } 4280 4281 static void rtw89_phy_swap_hal_antenna(struct rtw89_dev *rtwdev) 4282 { 4283 struct rtw89_hal *hal = &rtwdev->hal; 4284 4285 hal->antenna_rx = hal->antenna_rx == RF_A ? RF_B : RF_A; 4286 hal->antenna_tx = hal->antenna_rx; 4287 } 4288 4289 static void rtw89_phy_antdiv_decision_state(struct rtw89_dev *rtwdev) 4290 { 4291 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4292 struct rtw89_hal *hal = &rtwdev->hal; 4293 bool no_change = false; 4294 u8 main_rssi, aux_rssi; 4295 u8 main_evm, aux_evm; 4296 u32 candidate; 4297 4298 antdiv->get_stats = false; 4299 antdiv->training_count = 0; 4300 4301 main_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->main_stats); 4302 main_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->main_stats); 4303 aux_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->aux_stats); 4304 aux_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->aux_stats); 4305 4306 if (main_evm > aux_evm + ANTDIV_EVM_DIFF_TH) 4307 candidate = RF_A; 4308 else if (aux_evm > main_evm + ANTDIV_EVM_DIFF_TH) 4309 candidate = RF_B; 4310 else if (main_rssi > aux_rssi + RTW89_TX_DIV_RSSI_RAW_TH) 4311 candidate = RF_A; 4312 else if (aux_rssi > main_rssi + RTW89_TX_DIV_RSSI_RAW_TH) 4313 candidate = RF_B; 4314 else 4315 no_change = true; 4316 4317 if (no_change) { 4318 /* swap back from training antenna to original */ 4319 rtw89_phy_swap_hal_antenna(rtwdev); 4320 return; 4321 } 4322 4323 hal->antenna_tx = candidate; 4324 hal->antenna_rx = candidate; 4325 } 4326 4327 static void rtw89_phy_antdiv_training_state(struct rtw89_dev *rtwdev) 4328 { 4329 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4330 u64 state_period; 4331 4332 if (antdiv->training_count % 2 == 0) { 4333 if (antdiv->training_count == 0) 4334 rtw89_phy_antdiv_sts_reset(rtwdev); 4335 4336 antdiv->get_stats = true; 4337 state_period = msecs_to_jiffies(ANTDIV_TRAINNING_INTVL); 4338 } else { 4339 antdiv->get_stats = false; 4340 state_period = msecs_to_jiffies(ANTDIV_DELAY); 4341 4342 rtw89_phy_swap_hal_antenna(rtwdev); 4343 rtw89_phy_antdiv_set_ant(rtwdev); 4344 } 4345 4346 antdiv->training_count++; 4347 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 4348 state_period); 4349 } 4350 4351 void rtw89_phy_antdiv_work(struct work_struct *work) 4352 { 4353 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 4354 antdiv_work.work); 4355 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4356 4357 mutex_lock(&rtwdev->mutex); 4358 4359 if (antdiv->training_count <= ANTDIV_TRAINNING_CNT) { 4360 rtw89_phy_antdiv_training_state(rtwdev); 4361 } else { 4362 rtw89_phy_antdiv_decision_state(rtwdev); 4363 rtw89_phy_antdiv_set_ant(rtwdev); 4364 } 4365 4366 mutex_unlock(&rtwdev->mutex); 4367 } 4368 4369 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev) 4370 { 4371 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4372 struct rtw89_hal *hal = &rtwdev->hal; 4373 u8 rssi, rssi_pre; 4374 4375 if (!hal->ant_diversity || hal->ant_diversity_fixed) 4376 return; 4377 4378 rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->target_stats); 4379 rssi_pre = antdiv->rssi_pre; 4380 antdiv->rssi_pre = rssi; 4381 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats); 4382 4383 if (abs((int)rssi - (int)rssi_pre) < ANTDIV_RSSI_DIFF_TH) 4384 return; 4385 4386 antdiv->training_count = 0; 4387 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 0); 4388 } 4389 4390 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) 4391 { 4392 rtw89_phy_ccx_top_setting_init(rtwdev); 4393 rtw89_phy_ifs_clm_setting_init(rtwdev); 4394 } 4395 4396 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 4397 { 4398 const struct rtw89_chip_info *chip = rtwdev->chip; 4399 4400 rtw89_phy_stat_init(rtwdev); 4401 4402 rtw89_chip_bb_sethw(rtwdev); 4403 4404 rtw89_phy_env_monitor_init(rtwdev); 4405 rtw89_physts_parsing_init(rtwdev); 4406 rtw89_phy_dig_init(rtwdev); 4407 rtw89_phy_cfo_init(rtwdev); 4408 rtw89_phy_ul_tb_info_init(rtwdev); 4409 rtw89_phy_antdiv_init(rtwdev); 4410 rtw89_chip_rfe_gpio(rtwdev); 4411 rtw89_phy_antdiv_set_ant(rtwdev); 4412 4413 rtw89_phy_init_rf_nctl(rtwdev); 4414 rtw89_chip_rfk_init(rtwdev); 4415 rtw89_load_txpwr_table(rtwdev, chip->byr_table); 4416 rtw89_chip_set_txpwr_ctrl(rtwdev); 4417 rtw89_chip_power_trim(rtwdev); 4418 rtw89_chip_cfg_txrx_path(rtwdev); 4419 } 4420 4421 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 4422 { 4423 const struct rtw89_chip_info *chip = rtwdev->chip; 4424 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 4425 u8 bss_color; 4426 4427 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 4428 return; 4429 4430 bss_color = vif->bss_conf.he_bss_color.color; 4431 4432 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_VLD0, 0x1, 4433 phy_idx); 4434 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT, 4435 bss_color, phy_idx); 4436 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID, 4437 vif->cfg.aid, phy_idx); 4438 } 4439 4440 static void 4441 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4442 { 4443 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); 4444 } 4445 4446 static void 4447 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4448 { 4449 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 4450 } 4451 4452 static void 4453 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4454 { 4455 rtw89_phy_write32_set(rtwdev, def->addr, def->mask); 4456 } 4457 4458 static void 4459 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4460 { 4461 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); 4462 } 4463 4464 static void 4465 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4466 { 4467 udelay(def->data); 4468 } 4469 4470 static void 4471 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { 4472 [RTW89_RFK_F_WRF] = _rfk_write_rf, 4473 [RTW89_RFK_F_WM] = _rfk_write32_mask, 4474 [RTW89_RFK_F_WS] = _rfk_write32_set, 4475 [RTW89_RFK_F_WC] = _rfk_write32_clr, 4476 [RTW89_RFK_F_DELAY] = _rfk_delay, 4477 }; 4478 4479 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 4480 4481 void 4482 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) 4483 { 4484 const struct rtw89_reg5_def *p = tbl->defs; 4485 const struct rtw89_reg5_def *end = tbl->defs + tbl->size; 4486 4487 for (; p < end; p++) 4488 _rfk_handler[p->flag](rtwdev, p); 4489 } 4490 EXPORT_SYMBOL(rtw89_rfk_parser); 4491 4492 #define RTW89_TSSI_FAST_MODE_NUM 4 4493 4494 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = { 4495 {0xD934, 0xff0000}, 4496 {0xD934, 0xff000000}, 4497 {0xD938, 0xff}, 4498 {0xD934, 0xff00}, 4499 }; 4500 4501 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = { 4502 {0xD930, 0xff0000}, 4503 {0xD930, 0xff000000}, 4504 {0xD934, 0xff}, 4505 {0xD930, 0xff00}, 4506 }; 4507 4508 static 4509 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev, 4510 enum rtw89_mac_idx mac_idx, 4511 enum rtw89_tssi_bandedge_cfg bandedge_cfg, 4512 u32 val) 4513 { 4514 const struct rtw89_reg_def *regs; 4515 u32 reg; 4516 int i; 4517 4518 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 4519 regs = rtw89_tssi_fastmode_regs_flat; 4520 else 4521 regs = rtw89_tssi_fastmode_regs_level; 4522 4523 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) { 4524 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 4525 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); 4526 } 4527 } 4528 4529 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = { 4530 {0xD91C, 0xff000000}, 4531 {0xD920, 0xff}, 4532 {0xD920, 0xff00}, 4533 {0xD920, 0xff0000}, 4534 {0xD920, 0xff000000}, 4535 {0xD924, 0xff}, 4536 {0xD924, 0xff00}, 4537 {0xD914, 0xff000000}, 4538 {0xD918, 0xff}, 4539 {0xD918, 0xff00}, 4540 {0xD918, 0xff0000}, 4541 {0xD918, 0xff000000}, 4542 {0xD91C, 0xff}, 4543 {0xD91C, 0xff00}, 4544 {0xD91C, 0xff0000}, 4545 }; 4546 4547 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = { 4548 {0xD910, 0xff}, 4549 {0xD910, 0xff00}, 4550 {0xD910, 0xff0000}, 4551 {0xD910, 0xff000000}, 4552 {0xD914, 0xff}, 4553 {0xD914, 0xff00}, 4554 {0xD914, 0xff0000}, 4555 {0xD908, 0xff}, 4556 {0xD908, 0xff00}, 4557 {0xD908, 0xff0000}, 4558 {0xD908, 0xff000000}, 4559 {0xD90C, 0xff}, 4560 {0xD90C, 0xff00}, 4561 {0xD90C, 0xff0000}, 4562 {0xD90C, 0xff000000}, 4563 }; 4564 4565 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 4566 enum rtw89_mac_idx mac_idx, 4567 enum rtw89_tssi_bandedge_cfg bandedge_cfg) 4568 { 4569 const struct rtw89_chip_info *chip = rtwdev->chip; 4570 const struct rtw89_reg_def *regs; 4571 const u32 *data; 4572 u32 reg; 4573 int i; 4574 4575 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM) 4576 return; 4577 4578 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 4579 regs = rtw89_tssi_bandedge_regs_flat; 4580 else 4581 regs = rtw89_tssi_bandedge_regs_level; 4582 4583 data = chip->tssi_dbw_table->data[bandedge_cfg]; 4584 4585 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) { 4586 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 4587 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); 4588 } 4589 4590 reg = rtw89_mac_reg_by_idx(R_AX_BANDEDGE_CFG, mac_idx); 4591 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); 4592 4593 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg, 4594 data[RTW89_TSSI_SBW20]); 4595 } 4596 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg); 4597 4598 static 4599 const u8 rtw89_ch_base_table[16] = {1, 0xff, 4600 36, 100, 132, 149, 0xff, 4601 1, 33, 65, 97, 129, 161, 193, 225, 0xff}; 4602 #define RTW89_CH_BASE_IDX_2G 0 4603 #define RTW89_CH_BASE_IDX_5G_FIRST 2 4604 #define RTW89_CH_BASE_IDX_5G_LAST 5 4605 #define RTW89_CH_BASE_IDX_6G_FIRST 7 4606 #define RTW89_CH_BASE_IDX_6G_LAST 14 4607 4608 #define RTW89_CH_BASE_IDX_MASK GENMASK(7, 4) 4609 #define RTW89_CH_OFFSET_MASK GENMASK(3, 0) 4610 4611 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band) 4612 { 4613 u8 chan_idx; 4614 u8 last, first; 4615 u8 idx; 4616 4617 switch (band) { 4618 case RTW89_BAND_2G: 4619 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, RTW89_CH_BASE_IDX_2G) | 4620 FIELD_PREP(RTW89_CH_OFFSET_MASK, central_ch); 4621 return chan_idx; 4622 case RTW89_BAND_5G: 4623 first = RTW89_CH_BASE_IDX_5G_FIRST; 4624 last = RTW89_CH_BASE_IDX_5G_LAST; 4625 break; 4626 case RTW89_BAND_6G: 4627 first = RTW89_CH_BASE_IDX_6G_FIRST; 4628 last = RTW89_CH_BASE_IDX_6G_LAST; 4629 break; 4630 default: 4631 rtw89_warn(rtwdev, "Unsupported band %d\n", band); 4632 return 0; 4633 } 4634 4635 for (idx = last; idx >= first; idx--) 4636 if (central_ch >= rtw89_ch_base_table[idx]) 4637 break; 4638 4639 if (idx < first) { 4640 rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch); 4641 return 0; 4642 } 4643 4644 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, idx) | 4645 FIELD_PREP(RTW89_CH_OFFSET_MASK, 4646 (central_ch - rtw89_ch_base_table[idx]) >> 1); 4647 return chan_idx; 4648 } 4649 EXPORT_SYMBOL(rtw89_encode_chan_idx); 4650 4651 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, 4652 u8 *ch, enum nl80211_band *band) 4653 { 4654 u8 idx, offset; 4655 4656 idx = FIELD_GET(RTW89_CH_BASE_IDX_MASK, chan_idx); 4657 offset = FIELD_GET(RTW89_CH_OFFSET_MASK, chan_idx); 4658 4659 if (idx == RTW89_CH_BASE_IDX_2G) { 4660 *band = NL80211_BAND_2GHZ; 4661 *ch = offset; 4662 return; 4663 } 4664 4665 *band = idx <= RTW89_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ; 4666 *ch = rtw89_ch_base_table[idx] + (offset << 1); 4667 } 4668 EXPORT_SYMBOL(rtw89_decode_chan_idx); 4669 4670 #define EDCCA_DEFAULT 249 4671 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan) 4672 { 4673 u32 reg = rtwdev->chip->edcca_lvl_reg; 4674 struct rtw89_hal *hal = &rtwdev->hal; 4675 u32 val; 4676 4677 if (scan) { 4678 hal->edcca_bak = rtw89_phy_read32(rtwdev, reg); 4679 val = hal->edcca_bak; 4680 u32p_replace_bits(&val, EDCCA_DEFAULT, B_SEG0R_EDCCA_LVL_A_MSK); 4681 u32p_replace_bits(&val, EDCCA_DEFAULT, B_SEG0R_EDCCA_LVL_P_MSK); 4682 u32p_replace_bits(&val, EDCCA_DEFAULT, B_SEG0R_PPDU_LVL_MSK); 4683 rtw89_phy_write32(rtwdev, reg, val); 4684 } else { 4685 rtw89_phy_write32(rtwdev, reg, hal->edcca_bak); 4686 } 4687 } 4688