1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "debug.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "ps.h" 10 #include "reg.h" 11 #include "sar.h" 12 #include "coex.h" 13 14 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, 15 const struct rtw89_ra_report *report) 16 { 17 const struct rate_info *txrate = &report->txrate; 18 u32 bit_rate = report->bit_rate; 19 u8 mcs; 20 21 /* lower than ofdm, do not aggregate */ 22 if (bit_rate < 550) 23 return 1; 24 25 /* prevent hardware rate fallback to G mode rate */ 26 if (txrate->flags & RATE_INFO_FLAGS_MCS) 27 mcs = txrate->mcs & 0x07; 28 else if (txrate->flags & (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_HE_MCS)) 29 mcs = txrate->mcs; 30 else 31 mcs = 0; 32 33 if (mcs <= 2) 34 return 1; 35 36 /* lower than 20M vht 2ss mcs8, make it small */ 37 if (bit_rate < 1800) 38 return 1200; 39 40 /* lower than 40M vht 2ss mcs9, make it medium */ 41 if (bit_rate < 4000) 42 return 2600; 43 44 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ 45 if (bit_rate < 7000) 46 return 3500; 47 48 return rtwdev->chip->max_amsdu_limit; 49 } 50 51 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) 52 { 53 u64 ra_mask = 0; 54 u8 mcs_cap; 55 int i, nss; 56 57 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { 58 mcs_cap = mcs_map & 0x3; 59 switch (mcs_cap) { 60 case 2: 61 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; 62 break; 63 case 1: 64 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; 65 break; 66 case 0: 67 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; 68 break; 69 default: 70 break; 71 } 72 } 73 74 return ra_mask; 75 } 76 77 static u64 get_he_ra_mask(struct ieee80211_sta *sta) 78 { 79 struct ieee80211_sta_he_cap cap = sta->he_cap; 80 u16 mcs_map; 81 82 switch (sta->bandwidth) { 83 case IEEE80211_STA_RX_BW_160: 84 if (cap.he_cap_elem.phy_cap_info[0] & 85 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) 86 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); 87 else 88 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); 89 break; 90 default: 91 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); 92 } 93 94 /* MCS11, MCS9, MCS7 */ 95 return get_mcs_ra_mask(mcs_map, 11, 2); 96 } 97 98 #define RA_FLOOR_TABLE_SIZE 7 99 #define RA_FLOOR_UP_GAP 3 100 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, 101 u8 ratr_state) 102 { 103 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; 104 u8 rssi_lv = 0; 105 u8 i; 106 107 rssi >>= 1; 108 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 109 if (i >= ratr_state) 110 rssi_lv_t[i] += RA_FLOOR_UP_GAP; 111 if (rssi < rssi_lv_t[i]) { 112 rssi_lv = i; 113 break; 114 } 115 } 116 if (rssi_lv == 0) 117 return 0xffffffffffffffffULL; 118 else if (rssi_lv == 1) 119 return 0xfffffffffffffff0ULL; 120 else if (rssi_lv == 2) 121 return 0xffffffffffffefe0ULL; 122 else if (rssi_lv == 3) 123 return 0xffffffffffffcfc0ULL; 124 else if (rssi_lv == 4) 125 return 0xffffffffffff8f80ULL; 126 else if (rssi_lv >= 5) 127 return 0xffffffffffff0f00ULL; 128 129 return 0xffffffffffffffffULL; 130 } 131 132 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak) 133 { 134 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 135 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 136 137 if (ra_mask == 0) 138 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 139 140 return ra_mask; 141 } 142 143 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 144 { 145 struct rtw89_hal *hal = &rtwdev->hal; 146 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 147 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 148 enum nl80211_band band; 149 u64 cfg_mask; 150 151 if (!rtwsta->use_cfg_mask) 152 return -1; 153 154 switch (hal->current_band_type) { 155 case RTW89_BAND_2G: 156 band = NL80211_BAND_2GHZ; 157 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, 158 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); 159 break; 160 case RTW89_BAND_5G: 161 band = NL80211_BAND_5GHZ; 162 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, 163 RA_MASK_OFDM_RATES); 164 break; 165 case RTW89_BAND_6G: 166 band = NL80211_BAND_6GHZ; 167 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy, 168 RA_MASK_OFDM_RATES); 169 break; 170 default: 171 rtw89_warn(rtwdev, "unhandled band type %d\n", hal->current_band_type); 172 return -1; 173 } 174 175 if (sta->he_cap.has_he) { 176 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], 177 RA_MASK_HE_1SS_RATES); 178 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], 179 RA_MASK_HE_2SS_RATES); 180 } else if (sta->vht_cap.vht_supported) { 181 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 182 RA_MASK_VHT_1SS_RATES); 183 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 184 RA_MASK_VHT_2SS_RATES); 185 } else if (sta->ht_cap.ht_supported) { 186 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 187 RA_MASK_HT_1SS_RATES); 188 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 189 RA_MASK_HT_2SS_RATES); 190 } 191 192 return cfg_mask; 193 } 194 195 static const u64 196 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, 197 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; 198 static const u64 199 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 200 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; 201 static const u64 202 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, 203 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; 204 205 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 206 struct ieee80211_sta *sta, bool csi) 207 { 208 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 209 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 210 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 211 struct rtw89_ra_info *ra = &rtwsta->ra; 212 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; 213 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 214 u64 ra_mask = 0; 215 u64 ra_mask_bak; 216 u8 mode = 0; 217 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; 218 u8 bw_mode = 0; 219 u8 stbc_en = 0; 220 u8 ldpc_en = 0; 221 u8 i; 222 bool sgi = false; 223 224 memset(ra, 0, sizeof(*ra)); 225 /* Set the ra mask from sta's capability */ 226 if (sta->he_cap.has_he) { 227 mode |= RTW89_RA_MODE_HE; 228 csi_mode = RTW89_RA_RPT_MODE_HE; 229 ra_mask |= get_he_ra_mask(sta); 230 high_rate_masks = rtw89_ra_mask_he_rates; 231 if (sta->he_cap.he_cap_elem.phy_cap_info[2] & 232 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) 233 stbc_en = 1; 234 if (sta->he_cap.he_cap_elem.phy_cap_info[1] & 235 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) 236 ldpc_en = 1; 237 } else if (sta->vht_cap.vht_supported) { 238 u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map); 239 240 mode |= RTW89_RA_MODE_VHT; 241 csi_mode = RTW89_RA_RPT_MODE_VHT; 242 /* MCS9, MCS8, MCS7 */ 243 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); 244 high_rate_masks = rtw89_ra_mask_vht_rates; 245 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 246 stbc_en = 1; 247 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 248 ldpc_en = 1; 249 } else if (sta->ht_cap.ht_supported) { 250 mode |= RTW89_RA_MODE_HT; 251 csi_mode = RTW89_RA_RPT_MODE_HT; 252 ra_mask |= ((u64)sta->ht_cap.mcs.rx_mask[3] << 48) | 253 ((u64)sta->ht_cap.mcs.rx_mask[2] << 36) | 254 (sta->ht_cap.mcs.rx_mask[1] << 24) | 255 (sta->ht_cap.mcs.rx_mask[0] << 12); 256 high_rate_masks = rtw89_ra_mask_ht_rates; 257 if (sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 258 stbc_en = 1; 259 if (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 260 ldpc_en = 1; 261 } 262 263 switch (rtwdev->hal.current_band_type) { 264 case RTW89_BAND_2G: 265 ra_mask |= sta->supp_rates[NL80211_BAND_2GHZ]; 266 if (sta->supp_rates[NL80211_BAND_2GHZ] <= 0xf) 267 mode |= RTW89_RA_MODE_CCK; 268 else 269 mode |= RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM; 270 break; 271 case RTW89_BAND_5G: 272 ra_mask |= (u64)sta->supp_rates[NL80211_BAND_5GHZ] << 4; 273 mode |= RTW89_RA_MODE_OFDM; 274 break; 275 case RTW89_BAND_6G: 276 ra_mask |= (u64)sta->supp_rates[NL80211_BAND_6GHZ] << 4; 277 mode |= RTW89_RA_MODE_OFDM; 278 break; 279 default: 280 rtw89_err(rtwdev, "Unknown band type\n"); 281 break; 282 } 283 284 ra_mask_bak = ra_mask; 285 286 if (mode >= RTW89_RA_MODE_HT) { 287 u64 mask = 0; 288 for (i = 0; i < rtwdev->hal.tx_nss; i++) 289 mask |= high_rate_masks[i]; 290 if (mode & RTW89_RA_MODE_OFDM) 291 mask |= RA_MASK_SUBOFDM_RATES; 292 if (mode & RTW89_RA_MODE_CCK) 293 mask |= RA_MASK_SUBCCK_RATES; 294 ra_mask &= mask; 295 } else if (mode & RTW89_RA_MODE_OFDM) { 296 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES); 297 } 298 299 if (mode != RTW89_RA_MODE_CCK) 300 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); 301 302 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak); 303 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 304 305 switch (sta->bandwidth) { 306 case IEEE80211_STA_RX_BW_160: 307 bw_mode = RTW89_CHANNEL_WIDTH_160; 308 sgi = sta->vht_cap.vht_supported && 309 (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160); 310 break; 311 case IEEE80211_STA_RX_BW_80: 312 bw_mode = RTW89_CHANNEL_WIDTH_80; 313 sgi = sta->vht_cap.vht_supported && 314 (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 315 break; 316 case IEEE80211_STA_RX_BW_40: 317 bw_mode = RTW89_CHANNEL_WIDTH_40; 318 sgi = sta->ht_cap.ht_supported && 319 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 320 break; 321 default: 322 bw_mode = RTW89_CHANNEL_WIDTH_20; 323 sgi = sta->ht_cap.ht_supported && 324 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 325 break; 326 } 327 328 if (sta->he_cap.he_cap_elem.phy_cap_info[3] & 329 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) 330 ra->dcm_cap = 1; 331 332 if (rate_pattern->enable) { 333 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 334 ra_mask &= rate_pattern->ra_mask; 335 mode = rate_pattern->ra_mode; 336 } 337 338 ra->bw_cap = bw_mode; 339 ra->mode_ctrl = mode; 340 ra->macid = rtwsta->mac_id; 341 ra->stbc_cap = stbc_en; 342 ra->ldpc_cap = ldpc_en; 343 ra->ss_num = min(sta->rx_nss, rtwdev->hal.tx_nss) - 1; 344 ra->en_sgi = sgi; 345 ra->ra_mask = ra_mask; 346 347 if (!csi) 348 return; 349 350 ra->fixed_csi_rate_en = false; 351 ra->ra_csi_rate_en = true; 352 ra->cr_tbl_sel = false; 353 ra->band_num = rtwvif->phy_idx; 354 ra->csi_bw = bw_mode; 355 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; 356 ra->csi_mcs_ss_idx = 5; 357 ra->csi_mode = csi_mode; 358 } 359 360 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) 361 { 362 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 363 struct rtw89_ra_info *ra = &rtwsta->ra; 364 365 rtw89_phy_ra_sta_update(rtwdev, sta, false); 366 ra->upd_mask = 1; 367 rtw89_debug(rtwdev, RTW89_DBG_RA, 368 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", 369 ra->macid, 370 ra->bw_cap, 371 ra->ss_num, 372 ra->en_sgi, 373 ra->giltf); 374 375 rtw89_fw_h2c_ra(rtwdev, ra, false); 376 } 377 378 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, 379 u16 rate_base, u64 ra_mask, u8 ra_mode, 380 u32 rate_ctrl, u32 ctrl_skip, bool force) 381 { 382 u8 n, c; 383 384 if (rate_ctrl == ctrl_skip) 385 return true; 386 387 n = hweight32(rate_ctrl); 388 if (n == 0) 389 return true; 390 391 if (force && n != 1) 392 return false; 393 394 if (next->enable) 395 return false; 396 397 c = __fls(rate_ctrl); 398 next->rate = rate_base + c; 399 next->ra_mode = ra_mode; 400 next->ra_mask = ra_mask; 401 next->enable = true; 402 403 return true; 404 } 405 406 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 407 struct ieee80211_vif *vif, 408 const struct cfg80211_bitrate_mask *mask) 409 { 410 struct ieee80211_supported_band *sband; 411 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 412 struct rtw89_phy_rate_pattern next_pattern = {0}; 413 static const u16 hw_rate_he[] = {RTW89_HW_RATE_HE_NSS1_MCS0, 414 RTW89_HW_RATE_HE_NSS2_MCS0, 415 RTW89_HW_RATE_HE_NSS3_MCS0, 416 RTW89_HW_RATE_HE_NSS4_MCS0}; 417 static const u16 hw_rate_vht[] = {RTW89_HW_RATE_VHT_NSS1_MCS0, 418 RTW89_HW_RATE_VHT_NSS2_MCS0, 419 RTW89_HW_RATE_VHT_NSS3_MCS0, 420 RTW89_HW_RATE_VHT_NSS4_MCS0}; 421 static const u16 hw_rate_ht[] = {RTW89_HW_RATE_MCS0, 422 RTW89_HW_RATE_MCS8, 423 RTW89_HW_RATE_MCS16, 424 RTW89_HW_RATE_MCS24}; 425 u8 band = rtwdev->hal.current_band_type; 426 u8 tx_nss = rtwdev->hal.tx_nss; 427 u8 i; 428 429 for (i = 0; i < tx_nss; i++) 430 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i], 431 RA_MASK_HE_RATES, RTW89_RA_MODE_HE, 432 mask->control[band].he_mcs[i], 433 0, true)) 434 goto out; 435 436 for (i = 0; i < tx_nss; i++) 437 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i], 438 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, 439 mask->control[band].vht_mcs[i], 440 0, true)) 441 goto out; 442 443 for (i = 0; i < tx_nss; i++) 444 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i], 445 RA_MASK_HT_RATES, RTW89_RA_MODE_HT, 446 mask->control[band].ht_mcs[i], 447 0, true)) 448 goto out; 449 450 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and 451 * require at least one basic rate for ieee80211_set_bitrate_mask, 452 * so the decision just depends on if all bitrates are set or not. 453 */ 454 sband = rtwdev->hw->wiphy->bands[band]; 455 if (band == RTW89_BAND_2G) { 456 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, 457 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, 458 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, 459 mask->control[band].legacy, 460 BIT(sband->n_bitrates) - 1, false)) 461 goto out; 462 } else { 463 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, 464 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, 465 mask->control[band].legacy, 466 BIT(sband->n_bitrates) - 1, false)) 467 goto out; 468 } 469 470 if (!next_pattern.enable) 471 goto out; 472 473 rtwvif->rate_pattern = next_pattern; 474 rtw89_debug(rtwdev, RTW89_DBG_RA, 475 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", 476 next_pattern.rate, 477 next_pattern.ra_mask, 478 next_pattern.ra_mode); 479 return; 480 481 out: 482 rtwvif->rate_pattern.enable = false; 483 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); 484 } 485 486 static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta) 487 { 488 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; 489 490 rtw89_phy_ra_updata_sta(rtwdev, sta); 491 } 492 493 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) 494 { 495 ieee80211_iterate_stations_atomic(rtwdev->hw, 496 rtw89_phy_ra_updata_sta_iter, 497 rtwdev); 498 } 499 500 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) 501 { 502 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 503 struct rtw89_ra_info *ra = &rtwsta->ra; 504 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; 505 bool csi = rtw89_sta_has_beamformer_cap(sta); 506 507 rtw89_phy_ra_sta_update(rtwdev, sta, csi); 508 509 if (rssi > 40) 510 ra->init_rate_lv = 1; 511 else if (rssi > 20) 512 ra->init_rate_lv = 2; 513 else if (rssi > 1) 514 ra->init_rate_lv = 3; 515 else 516 ra->init_rate_lv = 0; 517 ra->upd_all = 1; 518 rtw89_debug(rtwdev, RTW89_DBG_RA, 519 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", 520 ra->macid, 521 ra->mode_ctrl, 522 ra->bw_cap, 523 ra->ss_num, 524 ra->init_rate_lv); 525 rtw89_debug(rtwdev, RTW89_DBG_RA, 526 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", 527 ra->dcm_cap, 528 ra->er_cap, 529 ra->ldpc_cap, 530 ra->stbc_cap, 531 ra->en_sgi, 532 ra->giltf); 533 534 rtw89_fw_h2c_ra(rtwdev, ra, csi); 535 } 536 537 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 538 struct rtw89_channel_params *param, 539 enum rtw89_bandwidth dbw) 540 { 541 enum rtw89_bandwidth cbw = param->bandwidth; 542 u8 pri_ch = param->primary_chan; 543 u8 central_ch = param->center_chan; 544 u8 txsc_idx = 0; 545 u8 tmp = 0; 546 547 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 548 return txsc_idx; 549 550 switch (cbw) { 551 case RTW89_CHANNEL_WIDTH_40: 552 txsc_idx = pri_ch > central_ch ? 1 : 2; 553 break; 554 case RTW89_CHANNEL_WIDTH_80: 555 if (dbw == RTW89_CHANNEL_WIDTH_20) { 556 if (pri_ch > central_ch) 557 txsc_idx = (pri_ch - central_ch) >> 1; 558 else 559 txsc_idx = ((central_ch - pri_ch) >> 1) + 1; 560 } else { 561 txsc_idx = pri_ch > central_ch ? 9 : 10; 562 } 563 break; 564 case RTW89_CHANNEL_WIDTH_160: 565 if (pri_ch > central_ch) 566 tmp = (pri_ch - central_ch) >> 1; 567 else 568 tmp = ((central_ch - pri_ch) >> 1) + 1; 569 570 if (dbw == RTW89_CHANNEL_WIDTH_20) { 571 txsc_idx = tmp; 572 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 573 if (tmp == 1 || tmp == 3) 574 txsc_idx = 9; 575 else if (tmp == 5 || tmp == 7) 576 txsc_idx = 11; 577 else if (tmp == 2 || tmp == 4) 578 txsc_idx = 10; 579 else if (tmp == 6 || tmp == 8) 580 txsc_idx = 12; 581 else 582 return 0xff; 583 } else { 584 txsc_idx = pri_ch > central_ch ? 13 : 14; 585 } 586 break; 587 case RTW89_CHANNEL_WIDTH_80_80: 588 if (dbw == RTW89_CHANNEL_WIDTH_20) { 589 if (pri_ch > central_ch) 590 txsc_idx = (10 - (pri_ch - central_ch)) >> 1; 591 else 592 txsc_idx = ((central_ch - pri_ch) >> 1) + 5; 593 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 594 txsc_idx = pri_ch > central_ch ? 10 : 12; 595 } else { 596 txsc_idx = 14; 597 } 598 break; 599 default: 600 break; 601 } 602 603 return txsc_idx; 604 } 605 EXPORT_SYMBOL(rtw89_phy_get_txsc); 606 607 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev) 608 { 609 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) || 610 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1); 611 } 612 613 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 614 u32 addr, u32 mask) 615 { 616 const struct rtw89_chip_info *chip = rtwdev->chip; 617 const u32 *base_addr = chip->rf_base_addr; 618 u32 val, direct_addr; 619 620 if (rf_path >= rtwdev->chip->rf_path_num) { 621 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 622 return INV_RF_DATA; 623 } 624 625 addr &= 0xff; 626 direct_addr = base_addr[rf_path] + (addr << 2); 627 mask &= RFREG_MASK; 628 629 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); 630 631 return val; 632 } 633 EXPORT_SYMBOL(rtw89_phy_read_rf); 634 635 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev, 636 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 637 { 638 bool busy; 639 bool done; 640 u32 val; 641 int ret; 642 643 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 644 1, 30, false, rtwdev); 645 if (ret) { 646 rtw89_err(rtwdev, "read rf busy swsi\n"); 647 return INV_RF_DATA; 648 } 649 650 mask &= RFREG_MASK; 651 652 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) | 653 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr); 654 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val); 655 udelay(2); 656 657 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1, 658 30, false, rtwdev, R_SWSI_V1, 659 B_SWSI_R_DATA_DONE_V1); 660 if (ret) { 661 rtw89_err(rtwdev, "read swsi busy\n"); 662 return INV_RF_DATA; 663 } 664 665 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask); 666 } 667 668 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 669 u32 addr, u32 mask) 670 { 671 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 672 673 if (rf_path >= rtwdev->chip->rf_path_num) { 674 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 675 return INV_RF_DATA; 676 } 677 678 if (ad_sel) 679 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 680 else 681 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask); 682 } 683 EXPORT_SYMBOL(rtw89_phy_read_rf_v1); 684 685 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 686 u32 addr, u32 mask, u32 data) 687 { 688 const struct rtw89_chip_info *chip = rtwdev->chip; 689 const u32 *base_addr = chip->rf_base_addr; 690 u32 direct_addr; 691 692 if (rf_path >= rtwdev->chip->rf_path_num) { 693 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 694 return false; 695 } 696 697 addr &= 0xff; 698 direct_addr = base_addr[rf_path] + (addr << 2); 699 mask &= RFREG_MASK; 700 701 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); 702 703 /* delay to ensure writing properly */ 704 udelay(1); 705 706 return true; 707 } 708 EXPORT_SYMBOL(rtw89_phy_write_rf); 709 710 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev, 711 enum rtw89_rf_path rf_path, u32 addr, u32 mask, 712 u32 data) 713 { 714 u8 bit_shift; 715 u32 val; 716 bool busy, b_msk_en = false; 717 int ret; 718 719 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 720 1, 30, false, rtwdev); 721 if (ret) { 722 rtw89_err(rtwdev, "write rf busy swsi\n"); 723 return false; 724 } 725 726 data &= RFREG_MASK; 727 mask &= RFREG_MASK; 728 729 if (mask != RFREG_MASK) { 730 b_msk_en = true; 731 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK, 732 mask); 733 bit_shift = __ffs(mask); 734 data = (data << bit_shift) & RFREG_MASK; 735 } 736 737 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) | 738 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) | 739 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) | 740 FIELD_PREP(B_SWSI_DATA_VAL_V1, data); 741 742 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val); 743 744 return true; 745 } 746 747 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 748 u32 addr, u32 mask, u32 data) 749 { 750 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 751 752 if (rf_path >= rtwdev->chip->rf_path_num) { 753 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 754 return false; 755 } 756 757 if (ad_sel) 758 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 759 else 760 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data); 761 } 762 EXPORT_SYMBOL(rtw89_phy_write_rf_v1); 763 764 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, 765 enum rtw89_phy_idx phy_idx) 766 { 767 const struct rtw89_chip_info *chip = rtwdev->chip; 768 769 chip->ops->bb_reset(rtwdev, phy_idx); 770 } 771 772 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, 773 const struct rtw89_reg2_def *reg, 774 enum rtw89_rf_path rf_path, 775 void *extra_data) 776 { 777 if (reg->addr == 0xfe) 778 mdelay(50); 779 else if (reg->addr == 0xfd) 780 mdelay(5); 781 else if (reg->addr == 0xfc) 782 mdelay(1); 783 else if (reg->addr == 0xfb) 784 udelay(50); 785 else if (reg->addr == 0xfa) 786 udelay(5); 787 else if (reg->addr == 0xf9) 788 udelay(1); 789 else 790 rtw89_phy_write32(rtwdev, reg->addr, reg->data); 791 } 792 793 static void 794 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, 795 const struct rtw89_reg2_def *reg, 796 enum rtw89_rf_path rf_path, 797 struct rtw89_fw_h2c_rf_reg_info *info) 798 { 799 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; 800 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 801 802 if (page >= RTW89_H2C_RF_PAGE_NUM) { 803 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d", 804 rf_path, info->curr_idx); 805 return; 806 } 807 808 info->rtw89_phy_config_rf_h2c[page][idx] = 809 cpu_to_le32((reg->addr << 20) | reg->data); 810 info->curr_idx++; 811 } 812 813 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, 814 struct rtw89_fw_h2c_rf_reg_info *info) 815 { 816 u16 remain = info->curr_idx; 817 u16 len = 0; 818 u8 i; 819 int ret = 0; 820 821 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) { 822 rtw89_warn(rtwdev, 823 "rf reg h2c total len %d larger than %d\n", 824 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE); 825 ret = -EINVAL; 826 goto out; 827 } 828 829 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) { 830 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain; 831 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i); 832 if (ret) 833 goto out; 834 } 835 out: 836 info->curr_idx = 0; 837 838 return ret; 839 } 840 841 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, 842 const struct rtw89_reg2_def *reg, 843 enum rtw89_rf_path rf_path, 844 void *extra_data) 845 { 846 if (reg->addr == 0xfe) { 847 mdelay(50); 848 } else if (reg->addr == 0xfd) { 849 mdelay(5); 850 } else if (reg->addr == 0xfc) { 851 mdelay(1); 852 } else if (reg->addr == 0xfb) { 853 udelay(50); 854 } else if (reg->addr == 0xfa) { 855 udelay(5); 856 } else if (reg->addr == 0xf9) { 857 udelay(1); 858 } else { 859 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); 860 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 861 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 862 } 863 } 864 865 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 866 const struct rtw89_reg2_def *reg, 867 enum rtw89_rf_path rf_path, 868 void *extra_data) 869 { 870 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data); 871 872 if (reg->addr < 0x100) 873 return; 874 875 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 876 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 877 } 878 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1); 879 880 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, 881 const struct rtw89_phy_table *table, 882 u32 *headline_size, u32 *headline_idx, 883 u8 rfe, u8 cv) 884 { 885 const struct rtw89_reg2_def *reg; 886 u32 headline; 887 u32 compare, target; 888 u8 rfe_para, cv_para; 889 u8 cv_max = 0; 890 bool case_matched = false; 891 u32 i; 892 893 for (i = 0; i < table->n_regs; i++) { 894 reg = &table->regs[i]; 895 headline = get_phy_headline(reg->addr); 896 if (headline != PHY_HEADLINE_VALID) 897 break; 898 } 899 *headline_size = i; 900 if (*headline_size == 0) 901 return 0; 902 903 /* case 1: RFE match, CV match */ 904 compare = get_phy_compare(rfe, cv); 905 for (i = 0; i < *headline_size; i++) { 906 reg = &table->regs[i]; 907 target = get_phy_target(reg->addr); 908 if (target == compare) { 909 *headline_idx = i; 910 return 0; 911 } 912 } 913 914 /* case 2: RFE match, CV don't care */ 915 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); 916 for (i = 0; i < *headline_size; i++) { 917 reg = &table->regs[i]; 918 target = get_phy_target(reg->addr); 919 if (target == compare) { 920 *headline_idx = i; 921 return 0; 922 } 923 } 924 925 /* case 3: RFE match, CV max in table */ 926 for (i = 0; i < *headline_size; i++) { 927 reg = &table->regs[i]; 928 rfe_para = get_phy_cond_rfe(reg->addr); 929 cv_para = get_phy_cond_cv(reg->addr); 930 if (rfe_para == rfe) { 931 if (cv_para >= cv_max) { 932 cv_max = cv_para; 933 *headline_idx = i; 934 case_matched = true; 935 } 936 } 937 } 938 939 if (case_matched) 940 return 0; 941 942 /* case 4: RFE don't care, CV max in table */ 943 for (i = 0; i < *headline_size; i++) { 944 reg = &table->regs[i]; 945 rfe_para = get_phy_cond_rfe(reg->addr); 946 cv_para = get_phy_cond_cv(reg->addr); 947 if (rfe_para == PHY_COND_DONT_CARE) { 948 if (cv_para >= cv_max) { 949 cv_max = cv_para; 950 *headline_idx = i; 951 case_matched = true; 952 } 953 } 954 } 955 956 if (case_matched) 957 return 0; 958 959 return -EINVAL; 960 } 961 962 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, 963 const struct rtw89_phy_table *table, 964 void (*config)(struct rtw89_dev *rtwdev, 965 const struct rtw89_reg2_def *reg, 966 enum rtw89_rf_path rf_path, 967 void *data), 968 void *extra_data) 969 { 970 const struct rtw89_reg2_def *reg; 971 enum rtw89_rf_path rf_path = table->rf_path; 972 u8 rfe = rtwdev->efuse.rfe_type; 973 u8 cv = rtwdev->hal.cv; 974 u32 i; 975 u32 headline_size = 0, headline_idx = 0; 976 u32 target = 0, cfg_target; 977 u8 cond; 978 bool is_matched = true; 979 bool target_found = false; 980 int ret; 981 982 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, 983 &headline_idx, rfe, cv); 984 if (ret) { 985 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); 986 return; 987 } 988 989 cfg_target = get_phy_target(table->regs[headline_idx].addr); 990 for (i = headline_size; i < table->n_regs; i++) { 991 reg = &table->regs[i]; 992 cond = get_phy_cond(reg->addr); 993 switch (cond) { 994 case PHY_COND_BRANCH_IF: 995 case PHY_COND_BRANCH_ELIF: 996 target = get_phy_target(reg->addr); 997 break; 998 case PHY_COND_BRANCH_ELSE: 999 is_matched = false; 1000 if (!target_found) { 1001 rtw89_warn(rtwdev, "failed to load CR %x/%x\n", 1002 reg->addr, reg->data); 1003 return; 1004 } 1005 break; 1006 case PHY_COND_BRANCH_END: 1007 is_matched = true; 1008 target_found = false; 1009 break; 1010 case PHY_COND_CHECK: 1011 if (target_found) { 1012 is_matched = false; 1013 break; 1014 } 1015 1016 if (target == cfg_target) { 1017 is_matched = true; 1018 target_found = true; 1019 } else { 1020 is_matched = false; 1021 target_found = false; 1022 } 1023 break; 1024 default: 1025 if (is_matched) 1026 config(rtwdev, reg, rf_path, extra_data); 1027 break; 1028 } 1029 } 1030 } 1031 1032 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) 1033 { 1034 const struct rtw89_chip_info *chip = rtwdev->chip; 1035 const struct rtw89_phy_table *bb_table = chip->bb_table; 1036 1037 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); 1038 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 1039 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); 1040 } 1041 1042 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 1043 { 1044 rtw89_phy_write32(rtwdev, 0x8080, 0x4); 1045 udelay(1); 1046 return rtw89_phy_read32(rtwdev, 0x8080); 1047 } 1048 1049 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev) 1050 { 1051 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 1052 enum rtw89_rf_path rf_path, void *data); 1053 const struct rtw89_chip_info *chip = rtwdev->chip; 1054 const struct rtw89_phy_table *rf_table; 1055 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; 1056 u8 path; 1057 1058 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); 1059 if (!rf_reg_info) 1060 return; 1061 1062 for (path = RF_PATH_A; path < chip->rf_path_num; path++) { 1063 rf_table = chip->rf_table[path]; 1064 rf_reg_info->rf_path = rf_table->rf_path; 1065 config = rf_table->config ? rf_table->config : rtw89_phy_config_rf_reg; 1066 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info); 1067 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) 1068 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", 1069 rf_reg_info->rf_path); 1070 } 1071 kfree(rf_reg_info); 1072 } 1073 1074 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) 1075 { 1076 const struct rtw89_chip_info *chip = rtwdev->chip; 1077 const struct rtw89_phy_table *nctl_table; 1078 u32 val; 1079 int ret; 1080 1081 /* IQK/DPK clock & reset */ 1082 rtw89_phy_write32_set(rtwdev, 0x0c60, 0x3); 1083 rtw89_phy_write32_set(rtwdev, 0x0c6c, 0x1); 1084 rtw89_phy_write32_set(rtwdev, 0x58ac, 0x8000000); 1085 rtw89_phy_write32_set(rtwdev, 0x78ac, 0x8000000); 1086 1087 /* check 0x8080 */ 1088 rtw89_phy_write32(rtwdev, 0x8000, 0x8); 1089 1090 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, 1091 1000, false, rtwdev); 1092 if (ret) 1093 rtw89_err(rtwdev, "failed to poll nctl block\n"); 1094 1095 nctl_table = chip->nctl_table; 1096 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); 1097 } 1098 1099 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) 1100 { 1101 u32 phy_page = addr >> 8; 1102 u32 ofst = 0; 1103 1104 switch (phy_page) { 1105 case 0x6: 1106 case 0x7: 1107 case 0x8: 1108 case 0x9: 1109 case 0xa: 1110 case 0xb: 1111 case 0xc: 1112 case 0xd: 1113 case 0x19: 1114 case 0x1a: 1115 case 0x1b: 1116 ofst = 0x2000; 1117 break; 1118 default: 1119 /* warning case */ 1120 ofst = 0; 1121 break; 1122 } 1123 1124 if (phy_page >= 0x40 && phy_page <= 0x4f) 1125 ofst = 0x2000; 1126 1127 return ofst; 1128 } 1129 1130 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1131 u32 data, enum rtw89_phy_idx phy_idx) 1132 { 1133 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1134 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1135 rtw89_phy_write32_mask(rtwdev, addr, mask, data); 1136 } 1137 EXPORT_SYMBOL(rtw89_phy_write32_idx); 1138 1139 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1140 u32 val) 1141 { 1142 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 1143 1144 if (!rtwdev->dbcc_en) 1145 return; 1146 1147 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 1148 } 1149 1150 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 1151 const struct rtw89_phy_reg3_tbl *tbl) 1152 { 1153 const struct rtw89_reg3_def *reg3; 1154 int i; 1155 1156 for (i = 0; i < tbl->size; i++) { 1157 reg3 = &tbl->reg3[i]; 1158 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); 1159 } 1160 } 1161 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl); 1162 1163 const u8 rtw89_rs_idx_max[] = { 1164 [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX, 1165 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX, 1166 [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX, 1167 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX, 1168 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX, 1169 }; 1170 EXPORT_SYMBOL(rtw89_rs_idx_max); 1171 1172 const u8 rtw89_rs_nss_max[] = { 1173 [RTW89_RS_CCK] = 1, 1174 [RTW89_RS_OFDM] = 1, 1175 [RTW89_RS_MCS] = RTW89_NSS_MAX, 1176 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX, 1177 [RTW89_RS_OFFSET] = 1, 1178 }; 1179 EXPORT_SYMBOL(rtw89_rs_nss_max); 1180 1181 static const u8 _byr_of_rs[] = { 1182 [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck), 1183 [RTW89_RS_OFDM] = offsetof(struct rtw89_txpwr_byrate, ofdm), 1184 [RTW89_RS_MCS] = offsetof(struct rtw89_txpwr_byrate, mcs), 1185 [RTW89_RS_HEDCM] = offsetof(struct rtw89_txpwr_byrate, hedcm), 1186 [RTW89_RS_OFFSET] = offsetof(struct rtw89_txpwr_byrate, offset), 1187 }; 1188 1189 #define _byr_seek(rs, raw) ((s8 *)(raw) + _byr_of_rs[rs]) 1190 #define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_max[rs] + (idx)) 1191 #define _byr_chk(rs, nss, idx) \ 1192 ((nss) < rtw89_rs_nss_max[rs] && (idx) < rtw89_rs_idx_max[rs]) 1193 1194 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 1195 const struct rtw89_txpwr_table *tbl) 1196 { 1197 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; 1198 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; 1199 s8 *byr; 1200 u32 data; 1201 u8 i, idx; 1202 1203 for (; cfg < end; cfg++) { 1204 byr = _byr_seek(cfg->rs, &rtwdev->byr[cfg->band]); 1205 data = cfg->data; 1206 1207 for (i = 0; i < cfg->len; i++, data >>= 8) { 1208 idx = _byr_idx(cfg->rs, cfg->nss, (cfg->shf + i)); 1209 byr[idx] = (s8)(data & 0xff); 1210 } 1211 } 1212 } 1213 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate); 1214 1215 #define _phy_txpwr_rf_to_mac(rtwdev, txpwr_rf) \ 1216 ({ \ 1217 const struct rtw89_chip_info *__c = (rtwdev)->chip; \ 1218 (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \ 1219 }) 1220 1221 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, 1222 const struct rtw89_rate_desc *rate_desc) 1223 { 1224 enum rtw89_band band = rtwdev->hal.current_band_type; 1225 s8 *byr; 1226 u8 idx; 1227 1228 if (rate_desc->rs == RTW89_RS_CCK) 1229 band = RTW89_BAND_2G; 1230 1231 if (!_byr_chk(rate_desc->rs, rate_desc->nss, rate_desc->idx)) { 1232 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1233 "[TXPWR] unknown byrate desc rs=%d nss=%d idx=%d\n", 1234 rate_desc->rs, rate_desc->nss, rate_desc->idx); 1235 1236 return 0; 1237 } 1238 1239 byr = _byr_seek(rate_desc->rs, &rtwdev->byr[band]); 1240 idx = _byr_idx(rate_desc->rs, rate_desc->nss, rate_desc->idx); 1241 1242 return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]); 1243 } 1244 EXPORT_SYMBOL(rtw89_phy_read_txpwr_byrate); 1245 1246 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g) 1247 { 1248 switch (channel_6g) { 1249 case 1 ... 29: 1250 return (channel_6g - 1) / 2; 1251 case 33 ... 61: 1252 return (channel_6g - 3) / 2; 1253 case 65 ... 93: 1254 return (channel_6g - 5) / 2; 1255 case 97 ... 125: 1256 return (channel_6g - 7) / 2; 1257 case 129 ... 157: 1258 return (channel_6g - 9) / 2; 1259 case 161 ... 189: 1260 return (channel_6g - 11) / 2; 1261 case 193 ... 221: 1262 return (channel_6g - 13) / 2; 1263 case 225 ... 253: 1264 return (channel_6g - 15) / 2; 1265 default: 1266 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g); 1267 return 0; 1268 } 1269 } 1270 1271 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel) 1272 { 1273 if (band == RTW89_BAND_6G) 1274 return rtw89_channel_6g_to_idx(rtwdev, channel); 1275 1276 switch (channel) { 1277 case 1 ... 14: 1278 return channel - 1; 1279 case 36 ... 64: 1280 return (channel - 36) / 2; 1281 case 100 ... 144: 1282 return ((channel - 100) / 2) + 15; 1283 case 149 ... 177: 1284 return ((channel - 149) / 2) + 38; 1285 default: 1286 rtw89_warn(rtwdev, "unknown channel: %d\n", channel); 1287 return 0; 1288 } 1289 } 1290 1291 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, 1292 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) 1293 { 1294 const struct rtw89_chip_info *chip = rtwdev->chip; 1295 u8 band = rtwdev->hal.current_band_type; 1296 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1297 u8 regd = rtw89_regd_get(rtwdev, band); 1298 s8 lmt = 0, sar; 1299 1300 switch (band) { 1301 case RTW89_BAND_2G: 1302 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf][regd][ch_idx]; 1303 if (!lmt) 1304 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf] 1305 [RTW89_WW][ch_idx]; 1306 break; 1307 case RTW89_BAND_5G: 1308 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf][regd][ch_idx]; 1309 if (!lmt) 1310 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf] 1311 [RTW89_WW][ch_idx]; 1312 break; 1313 case RTW89_BAND_6G: 1314 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf][regd][ch_idx]; 1315 if (!lmt) 1316 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf] 1317 [RTW89_WW][ch_idx]; 1318 break; 1319 default: 1320 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1321 return 0; 1322 } 1323 1324 lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt); 1325 sar = rtw89_query_sar(rtwdev); 1326 1327 return min(lmt, sar); 1328 } 1329 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit); 1330 1331 #define __fill_txpwr_limit_nonbf_bf(ptr, bw, ntx, rs, ch) \ 1332 do { \ 1333 u8 __i; \ 1334 for (__i = 0; __i < RTW89_BF_NUM; __i++) \ 1335 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ 1336 bw, ntx, \ 1337 rs, __i, \ 1338 (ch)); \ 1339 } while (0) 1340 1341 static void rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev *rtwdev, 1342 struct rtw89_txpwr_limit *lmt, 1343 u8 ntx, u8 ch) 1344 { 1345 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, RTW89_CHANNEL_WIDTH_20, 1346 ntx, RTW89_RS_CCK, ch); 1347 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, RTW89_CHANNEL_WIDTH_40, 1348 ntx, RTW89_RS_CCK, ch); 1349 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, 1350 ntx, RTW89_RS_OFDM, ch); 1351 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, 1352 ntx, RTW89_RS_MCS, ch); 1353 } 1354 1355 static void rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev *rtwdev, 1356 struct rtw89_txpwr_limit *lmt, 1357 u8 ntx, u8 ch, u8 pri_ch) 1358 { 1359 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, RTW89_CHANNEL_WIDTH_20, 1360 ntx, RTW89_RS_CCK, ch - 2); 1361 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, RTW89_CHANNEL_WIDTH_40, 1362 ntx, RTW89_RS_CCK, ch); 1363 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, 1364 ntx, RTW89_RS_OFDM, pri_ch); 1365 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, 1366 ntx, RTW89_RS_MCS, ch - 2); 1367 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], RTW89_CHANNEL_WIDTH_20, 1368 ntx, RTW89_RS_MCS, ch + 2); 1369 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], RTW89_CHANNEL_WIDTH_40, 1370 ntx, RTW89_RS_MCS, ch); 1371 } 1372 1373 static void rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev *rtwdev, 1374 struct rtw89_txpwr_limit *lmt, 1375 u8 ntx, u8 ch, u8 pri_ch) 1376 { 1377 s8 val_0p5_n[RTW89_BF_NUM]; 1378 s8 val_0p5_p[RTW89_BF_NUM]; 1379 u8 i; 1380 1381 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, 1382 ntx, RTW89_RS_OFDM, pri_ch); 1383 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, 1384 ntx, RTW89_RS_MCS, ch - 6); 1385 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], RTW89_CHANNEL_WIDTH_20, 1386 ntx, RTW89_RS_MCS, ch - 2); 1387 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], RTW89_CHANNEL_WIDTH_20, 1388 ntx, RTW89_RS_MCS, ch + 2); 1389 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], RTW89_CHANNEL_WIDTH_20, 1390 ntx, RTW89_RS_MCS, ch + 6); 1391 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], RTW89_CHANNEL_WIDTH_40, 1392 ntx, RTW89_RS_MCS, ch - 4); 1393 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], RTW89_CHANNEL_WIDTH_40, 1394 ntx, RTW89_RS_MCS, ch + 4); 1395 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], RTW89_CHANNEL_WIDTH_80, 1396 ntx, RTW89_RS_MCS, ch); 1397 1398 __fill_txpwr_limit_nonbf_bf(val_0p5_n, RTW89_CHANNEL_WIDTH_40, 1399 ntx, RTW89_RS_MCS, ch - 4); 1400 __fill_txpwr_limit_nonbf_bf(val_0p5_p, RTW89_CHANNEL_WIDTH_40, 1401 ntx, RTW89_RS_MCS, ch + 4); 1402 1403 for (i = 0; i < RTW89_BF_NUM; i++) 1404 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1405 } 1406 1407 static void rtw89_phy_fill_txpwr_limit_160m(struct rtw89_dev *rtwdev, 1408 struct rtw89_txpwr_limit *lmt, 1409 u8 ntx, u8 ch, u8 pri_ch) 1410 { 1411 s8 val_0p5_n[RTW89_BF_NUM]; 1412 s8 val_0p5_p[RTW89_BF_NUM]; 1413 s8 val_2p5_n[RTW89_BF_NUM]; 1414 s8 val_2p5_p[RTW89_BF_NUM]; 1415 u8 i; 1416 1417 /* fill ofdm section */ 1418 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, 1419 ntx, RTW89_RS_OFDM, pri_ch); 1420 1421 /* fill mcs 20m section */ 1422 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, 1423 ntx, RTW89_RS_MCS, ch - 14); 1424 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], RTW89_CHANNEL_WIDTH_20, 1425 ntx, RTW89_RS_MCS, ch - 10); 1426 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], RTW89_CHANNEL_WIDTH_20, 1427 ntx, RTW89_RS_MCS, ch - 6); 1428 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], RTW89_CHANNEL_WIDTH_20, 1429 ntx, RTW89_RS_MCS, ch - 2); 1430 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], RTW89_CHANNEL_WIDTH_20, 1431 ntx, RTW89_RS_MCS, ch + 2); 1432 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], RTW89_CHANNEL_WIDTH_20, 1433 ntx, RTW89_RS_MCS, ch + 6); 1434 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], RTW89_CHANNEL_WIDTH_20, 1435 ntx, RTW89_RS_MCS, ch + 10); 1436 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], RTW89_CHANNEL_WIDTH_20, 1437 ntx, RTW89_RS_MCS, ch + 14); 1438 1439 /* fill mcs 40m section */ 1440 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], RTW89_CHANNEL_WIDTH_40, 1441 ntx, RTW89_RS_MCS, ch - 12); 1442 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], RTW89_CHANNEL_WIDTH_40, 1443 ntx, RTW89_RS_MCS, ch - 4); 1444 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], RTW89_CHANNEL_WIDTH_40, 1445 ntx, RTW89_RS_MCS, ch + 4); 1446 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], RTW89_CHANNEL_WIDTH_40, 1447 ntx, RTW89_RS_MCS, ch + 12); 1448 1449 /* fill mcs 80m section */ 1450 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], RTW89_CHANNEL_WIDTH_80, 1451 ntx, RTW89_RS_MCS, ch - 8); 1452 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], RTW89_CHANNEL_WIDTH_80, 1453 ntx, RTW89_RS_MCS, ch + 8); 1454 1455 /* fill mcs 160m section */ 1456 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, RTW89_CHANNEL_WIDTH_160, 1457 ntx, RTW89_RS_MCS, ch); 1458 1459 /* fill mcs 40m 0p5 section */ 1460 __fill_txpwr_limit_nonbf_bf(val_0p5_n, RTW89_CHANNEL_WIDTH_40, 1461 ntx, RTW89_RS_MCS, ch - 4); 1462 __fill_txpwr_limit_nonbf_bf(val_0p5_p, RTW89_CHANNEL_WIDTH_40, 1463 ntx, RTW89_RS_MCS, ch + 4); 1464 1465 for (i = 0; i < RTW89_BF_NUM; i++) 1466 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1467 1468 /* fill mcs 40m 2p5 section */ 1469 __fill_txpwr_limit_nonbf_bf(val_2p5_n, RTW89_CHANNEL_WIDTH_40, 1470 ntx, RTW89_RS_MCS, ch - 8); 1471 __fill_txpwr_limit_nonbf_bf(val_2p5_p, RTW89_CHANNEL_WIDTH_40, 1472 ntx, RTW89_RS_MCS, ch + 8); 1473 1474 for (i = 0; i < RTW89_BF_NUM; i++) 1475 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]); 1476 } 1477 1478 void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev, 1479 struct rtw89_txpwr_limit *lmt, 1480 u8 ntx) 1481 { 1482 u8 pri_ch = rtwdev->hal.current_primary_channel; 1483 u8 ch = rtwdev->hal.current_channel; 1484 u8 bw = rtwdev->hal.current_band_width; 1485 1486 memset(lmt, 0, sizeof(*lmt)); 1487 1488 switch (bw) { 1489 case RTW89_CHANNEL_WIDTH_20: 1490 rtw89_phy_fill_txpwr_limit_20m(rtwdev, lmt, ntx, ch); 1491 break; 1492 case RTW89_CHANNEL_WIDTH_40: 1493 rtw89_phy_fill_txpwr_limit_40m(rtwdev, lmt, ntx, ch, pri_ch); 1494 break; 1495 case RTW89_CHANNEL_WIDTH_80: 1496 rtw89_phy_fill_txpwr_limit_80m(rtwdev, lmt, ntx, ch, pri_ch); 1497 break; 1498 case RTW89_CHANNEL_WIDTH_160: 1499 rtw89_phy_fill_txpwr_limit_160m(rtwdev, lmt, ntx, ch, pri_ch); 1500 break; 1501 } 1502 } 1503 EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit); 1504 1505 static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, 1506 u8 ru, u8 ntx, u8 ch) 1507 { 1508 const struct rtw89_chip_info *chip = rtwdev->chip; 1509 u8 band = rtwdev->hal.current_band_type; 1510 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1511 u8 regd = rtw89_regd_get(rtwdev, band); 1512 s8 lmt_ru = 0, sar; 1513 1514 switch (band) { 1515 case RTW89_BAND_2G: 1516 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx][regd][ch_idx]; 1517 if (!lmt_ru) 1518 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx] 1519 [RTW89_WW][ch_idx]; 1520 break; 1521 case RTW89_BAND_5G: 1522 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx][regd][ch_idx]; 1523 if (!lmt_ru) 1524 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx] 1525 [RTW89_WW][ch_idx]; 1526 break; 1527 case RTW89_BAND_6G: 1528 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx][regd][ch_idx]; 1529 if (!lmt_ru) 1530 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx] 1531 [RTW89_WW][ch_idx]; 1532 break; 1533 default: 1534 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1535 return 0; 1536 } 1537 1538 lmt_ru = _phy_txpwr_rf_to_mac(rtwdev, lmt_ru); 1539 sar = rtw89_query_sar(rtwdev); 1540 1541 return min(lmt_ru, sar); 1542 } 1543 1544 static void 1545 rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev, 1546 struct rtw89_txpwr_limit_ru *lmt_ru, 1547 u8 ntx, u8 ch) 1548 { 1549 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1550 ntx, ch); 1551 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1552 ntx, ch); 1553 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1554 ntx, ch); 1555 } 1556 1557 static void 1558 rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev, 1559 struct rtw89_txpwr_limit_ru *lmt_ru, 1560 u8 ntx, u8 ch) 1561 { 1562 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1563 ntx, ch - 2); 1564 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1565 ntx, ch + 2); 1566 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1567 ntx, ch - 2); 1568 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1569 ntx, ch + 2); 1570 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1571 ntx, ch - 2); 1572 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1573 ntx, ch + 2); 1574 } 1575 1576 static void 1577 rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev, 1578 struct rtw89_txpwr_limit_ru *lmt_ru, 1579 u8 ntx, u8 ch) 1580 { 1581 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1582 ntx, ch - 6); 1583 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1584 ntx, ch - 2); 1585 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1586 ntx, ch + 2); 1587 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1588 ntx, ch + 6); 1589 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1590 ntx, ch - 6); 1591 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1592 ntx, ch - 2); 1593 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1594 ntx, ch + 2); 1595 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1596 ntx, ch + 6); 1597 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1598 ntx, ch - 6); 1599 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1600 ntx, ch - 2); 1601 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1602 ntx, ch + 2); 1603 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1604 ntx, ch + 6); 1605 } 1606 1607 static void 1608 rtw89_phy_fill_txpwr_limit_ru_160m(struct rtw89_dev *rtwdev, 1609 struct rtw89_txpwr_limit_ru *lmt_ru, 1610 u8 ntx, u8 ch) 1611 { 1612 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 }; 1613 int i; 1614 1615 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM); 1616 for (i = 0; i < RTW89_RU_SEC_NUM; i++) { 1617 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, 1618 RTW89_RU26, 1619 ntx, 1620 ch + ofst[i]); 1621 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, 1622 RTW89_RU52, 1623 ntx, 1624 ch + ofst[i]); 1625 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, 1626 RTW89_RU106, 1627 ntx, 1628 ch + ofst[i]); 1629 } 1630 } 1631 1632 void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, 1633 struct rtw89_txpwr_limit_ru *lmt_ru, 1634 u8 ntx) 1635 { 1636 u8 ch = rtwdev->hal.current_channel; 1637 u8 bw = rtwdev->hal.current_band_width; 1638 1639 memset(lmt_ru, 0, sizeof(*lmt_ru)); 1640 1641 switch (bw) { 1642 case RTW89_CHANNEL_WIDTH_20: 1643 rtw89_phy_fill_txpwr_limit_ru_20m(rtwdev, lmt_ru, ntx, ch); 1644 break; 1645 case RTW89_CHANNEL_WIDTH_40: 1646 rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, ntx, ch); 1647 break; 1648 case RTW89_CHANNEL_WIDTH_80: 1649 rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, ntx, ch); 1650 break; 1651 case RTW89_CHANNEL_WIDTH_160: 1652 rtw89_phy_fill_txpwr_limit_ru_160m(rtwdev, lmt_ru, ntx, ch); 1653 break; 1654 } 1655 } 1656 EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit_ru); 1657 1658 struct rtw89_phy_iter_ra_data { 1659 struct rtw89_dev *rtwdev; 1660 struct sk_buff *c2h; 1661 }; 1662 1663 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) 1664 { 1665 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; 1666 struct rtw89_dev *rtwdev = ra_data->rtwdev; 1667 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1668 struct rtw89_ra_report *ra_report = &rtwsta->ra_report; 1669 struct sk_buff *c2h = ra_data->c2h; 1670 u8 mode, rate, bw, giltf, mac_id; 1671 1672 mac_id = RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h->data); 1673 if (mac_id != rtwsta->mac_id) 1674 return; 1675 1676 memset(ra_report, 0, sizeof(*ra_report)); 1677 1678 rate = RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h->data); 1679 bw = RTW89_GET_PHY_C2H_RA_RPT_BW(c2h->data); 1680 giltf = RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h->data); 1681 mode = RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h->data); 1682 1683 switch (mode) { 1684 case RTW89_RA_RPT_MODE_LEGACY: 1685 ra_report->txrate.legacy = rtw89_ra_report_to_bitrate(rtwdev, rate); 1686 break; 1687 case RTW89_RA_RPT_MODE_HT: 1688 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; 1689 if (rtwdev->fw.old_ht_ra_format) 1690 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), 1691 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); 1692 else 1693 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); 1694 ra_report->txrate.mcs = rate; 1695 if (giltf) 1696 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1697 break; 1698 case RTW89_RA_RPT_MODE_VHT: 1699 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; 1700 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 1701 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 1702 if (giltf) 1703 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1704 break; 1705 case RTW89_RA_RPT_MODE_HE: 1706 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; 1707 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 1708 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 1709 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 1710 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; 1711 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 1712 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; 1713 else 1714 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; 1715 break; 1716 } 1717 1718 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw); 1719 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); 1720 ra_report->hw_rate = FIELD_PREP(RTW89_HW_RATE_MASK_MOD, mode) | 1721 FIELD_PREP(RTW89_HW_RATE_MASK_VAL, rate); 1722 sta->max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); 1723 rtwsta->max_agg_wait = sta->max_rc_amsdu_len / 1500 - 1; 1724 } 1725 1726 static void 1727 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 1728 { 1729 struct rtw89_phy_iter_ra_data ra_data; 1730 1731 ra_data.rtwdev = rtwdev; 1732 ra_data.c2h = c2h; 1733 ieee80211_iterate_stations_atomic(rtwdev->hw, 1734 rtw89_phy_c2h_ra_rpt_iter, 1735 &ra_data); 1736 } 1737 1738 static 1739 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, 1740 struct sk_buff *c2h, u32 len) = { 1741 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 1742 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 1743 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 1744 }; 1745 1746 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1747 u32 len, u8 class, u8 func) 1748 { 1749 void (*handler)(struct rtw89_dev *rtwdev, 1750 struct sk_buff *c2h, u32 len) = NULL; 1751 1752 switch (class) { 1753 case RTW89_PHY_C2H_CLASS_RA: 1754 if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 1755 handler = rtw89_phy_c2h_ra_handler[func]; 1756 break; 1757 default: 1758 rtw89_info(rtwdev, "c2h class %d not support\n", class); 1759 return; 1760 } 1761 if (!handler) { 1762 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 1763 func); 1764 return; 1765 } 1766 handler(rtwdev, skb, len); 1767 } 1768 1769 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) 1770 { 1771 u32 reg_mask; 1772 1773 if (sc_xo) 1774 reg_mask = B_AX_XTAL_SC_XO_MASK; 1775 else 1776 reg_mask = B_AX_XTAL_SC_XI_MASK; 1777 1778 return (u8)rtw89_read32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask); 1779 } 1780 1781 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, 1782 u8 val) 1783 { 1784 u32 reg_mask; 1785 1786 if (sc_xo) 1787 reg_mask = B_AX_XTAL_SC_XO_MASK; 1788 else 1789 reg_mask = B_AX_XTAL_SC_XI_MASK; 1790 1791 rtw89_write32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask, val); 1792 } 1793 1794 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, 1795 u8 crystal_cap, bool force) 1796 { 1797 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 1798 const struct rtw89_chip_info *chip = rtwdev->chip; 1799 u8 sc_xi_val, sc_xo_val; 1800 1801 if (!force && cfo->crystal_cap == crystal_cap) 1802 return; 1803 crystal_cap = clamp_t(u8, crystal_cap, 0, 127); 1804 if (chip->chip_id == RTL8852A) { 1805 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); 1806 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); 1807 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); 1808 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); 1809 } else { 1810 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, 1811 crystal_cap, XTAL_SC_XO_MASK); 1812 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, 1813 crystal_cap, XTAL_SC_XI_MASK); 1814 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val); 1815 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val); 1816 } 1817 cfo->crystal_cap = sc_xi_val; 1818 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); 1819 1820 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); 1821 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); 1822 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", 1823 cfo->x_cap_ofst); 1824 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); 1825 } 1826 1827 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) 1828 { 1829 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 1830 u8 cap; 1831 1832 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; 1833 cfo->is_adjust = false; 1834 if (cfo->crystal_cap == cfo->def_x_cap) 1835 return; 1836 cap = cfo->crystal_cap; 1837 cap += (cap > cfo->def_x_cap ? -1 : 1); 1838 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); 1839 rtw89_debug(rtwdev, RTW89_DBG_CFO, 1840 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, 1841 cfo->def_x_cap); 1842 } 1843 1844 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) 1845 { 1846 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp; 1847 bool is_linked = rtwdev->total_sta_assoc > 0; 1848 s32 cfo_avg_312; 1849 s32 dcfo_comp_val; 1850 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft; 1851 int sign; 1852 1853 if (!is_linked) { 1854 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", 1855 is_linked); 1856 return; 1857 } 1858 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); 1859 if (curr_cfo == 0) 1860 return; 1861 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); 1862 sign = curr_cfo > 0 ? 1 : -1; 1863 cfo_avg_312 = (curr_cfo << dcfo_comp_sft) / 5 + sign * dcfo_comp_val; 1864 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: avg_cfo=%d\n", cfo_avg_312); 1865 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 1866 cfo_avg_312 = -cfo_avg_312; 1867 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask, 1868 cfo_avg_312); 1869 } 1870 1871 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) 1872 { 1873 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_OPT, B_DCFO_OPT_EN, 1); 1874 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_WEIGHT, B_DCFO_WEIGHT_MSK, 8); 1875 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, B_AX_PWR_UL_CFO_MASK); 1876 } 1877 1878 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) 1879 { 1880 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 1881 struct rtw89_efuse *efuse = &rtwdev->efuse; 1882 1883 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; 1884 cfo->crystal_cap = cfo->crystal_cap_default; 1885 cfo->def_x_cap = cfo->crystal_cap; 1886 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f); 1887 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1); 1888 cfo->is_adjust = false; 1889 cfo->divergence_lock_en = false; 1890 cfo->x_cap_ofst = 0; 1891 cfo->lock_cnt = 0; 1892 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; 1893 cfo->apply_compensation = false; 1894 cfo->residual_cfo_acc = 0; 1895 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", 1896 cfo->crystal_cap_default); 1897 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); 1898 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); 1899 rtw89_dcfo_comp_init(rtwdev); 1900 cfo->cfo_timer_ms = 2000; 1901 cfo->cfo_trig_by_timer_en = false; 1902 cfo->phy_cfo_trk_cnt = 0; 1903 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 1904 } 1905 1906 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, 1907 s32 curr_cfo) 1908 { 1909 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 1910 s8 crystal_cap = cfo->crystal_cap; 1911 s32 cfo_abs = abs(curr_cfo); 1912 int sign; 1913 1914 if (!cfo->is_adjust) { 1915 if (cfo_abs > CFO_TRK_ENABLE_TH) 1916 cfo->is_adjust = true; 1917 } else { 1918 if (cfo_abs < CFO_TRK_STOP_TH) 1919 cfo->is_adjust = false; 1920 } 1921 if (!cfo->is_adjust) { 1922 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); 1923 return; 1924 } 1925 sign = curr_cfo > 0 ? 1 : -1; 1926 if (cfo_abs > CFO_TRK_STOP_TH_4) 1927 crystal_cap += 7 * sign; 1928 else if (cfo_abs > CFO_TRK_STOP_TH_3) 1929 crystal_cap += 5 * sign; 1930 else if (cfo_abs > CFO_TRK_STOP_TH_2) 1931 crystal_cap += 3 * sign; 1932 else if (cfo_abs > CFO_TRK_STOP_TH_1) 1933 crystal_cap += 1 * sign; 1934 else 1935 return; 1936 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); 1937 rtw89_debug(rtwdev, RTW89_DBG_CFO, 1938 "X_cap{Curr,Default}={0x%x,0x%x}\n", 1939 cfo->crystal_cap, cfo->def_x_cap); 1940 } 1941 1942 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) 1943 { 1944 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 1945 s32 cfo_khz_all = 0; 1946 s32 cfo_cnt_all = 0; 1947 s32 cfo_all_avg = 0; 1948 u8 i; 1949 1950 if (rtwdev->total_sta_assoc != 1) 1951 return 0; 1952 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); 1953 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 1954 if (cfo->cfo_cnt[i] == 0) 1955 continue; 1956 cfo_khz_all += cfo->cfo_tail[i]; 1957 cfo_cnt_all += cfo->cfo_cnt[i]; 1958 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); 1959 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 1960 } 1961 rtw89_debug(rtwdev, RTW89_DBG_CFO, 1962 "CFO track for macid = %d\n", i); 1963 rtw89_debug(rtwdev, RTW89_DBG_CFO, 1964 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", 1965 cfo_khz_all, cfo_cnt_all, cfo_all_avg); 1966 return cfo_all_avg; 1967 } 1968 1969 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) 1970 { 1971 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 1972 struct rtw89_traffic_stats *stats = &rtwdev->stats; 1973 s32 target_cfo = 0; 1974 s32 cfo_khz_all = 0; 1975 s32 cfo_khz_all_tp_wgt = 0; 1976 s32 cfo_avg = 0; 1977 s32 max_cfo_lb = BIT(31); 1978 s32 min_cfo_ub = GENMASK(30, 0); 1979 u16 cfo_cnt_all = 0; 1980 u8 active_entry_cnt = 0; 1981 u8 sta_cnt = 0; 1982 u32 tp_all = 0; 1983 u8 i; 1984 u8 cfo_tol = 0; 1985 1986 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); 1987 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { 1988 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); 1989 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 1990 if (cfo->cfo_cnt[i] == 0) 1991 continue; 1992 cfo_khz_all += cfo->cfo_tail[i]; 1993 cfo_cnt_all += cfo->cfo_cnt[i]; 1994 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); 1995 rtw89_debug(rtwdev, RTW89_DBG_CFO, 1996 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", 1997 cfo_khz_all, cfo_cnt_all, cfo_avg); 1998 target_cfo = cfo_avg; 1999 } 2000 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { 2001 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); 2002 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2003 if (cfo->cfo_cnt[i] == 0) 2004 continue; 2005 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2006 (s32)cfo->cfo_cnt[i]); 2007 cfo_khz_all += cfo->cfo_avg[i]; 2008 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2009 "Macid=%d, cfo_avg=%d\n", i, 2010 cfo->cfo_avg[i]); 2011 } 2012 sta_cnt = rtwdev->total_sta_assoc; 2013 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); 2014 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2015 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", 2016 cfo_khz_all, sta_cnt, cfo_avg); 2017 target_cfo = cfo_avg; 2018 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { 2019 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); 2020 cfo_tol = cfo->sta_cfo_tolerance; 2021 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2022 sta_cnt++; 2023 if (cfo->cfo_cnt[i] != 0) { 2024 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2025 (s32)cfo->cfo_cnt[i]); 2026 active_entry_cnt++; 2027 } else { 2028 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; 2029 } 2030 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); 2031 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); 2032 cfo_khz_all += cfo->cfo_avg[i]; 2033 /* need tp for each entry */ 2034 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2035 "[%d] cfo_avg=%d, tp=tbd\n", 2036 i, cfo->cfo_avg[i]); 2037 if (sta_cnt >= rtwdev->total_sta_assoc) 2038 break; 2039 } 2040 tp_all = stats->rx_throughput; /* need tp for each entry */ 2041 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); 2042 2043 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", 2044 sta_cnt); 2045 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", 2046 active_entry_cnt); 2047 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2048 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", 2049 cfo_khz_all_tp_wgt, cfo_avg); 2050 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", 2051 max_cfo_lb, min_cfo_ub); 2052 if (max_cfo_lb <= min_cfo_ub) { 2053 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2054 "cfo win_size=%d\n", 2055 min_cfo_ub - max_cfo_lb); 2056 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); 2057 } else { 2058 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2059 "No intersection of cfo tolerance windows\n"); 2060 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); 2061 } 2062 for (i = 0; i < CFO_TRACK_MAX_USER; i++) 2063 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2064 } 2065 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); 2066 return target_cfo; 2067 } 2068 2069 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) 2070 { 2071 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2072 2073 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); 2074 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); 2075 cfo->packet_count = 0; 2076 cfo->packet_count_pre = 0; 2077 cfo->cfo_avg_pre = 0; 2078 } 2079 2080 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) 2081 { 2082 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2083 s32 new_cfo = 0; 2084 bool x_cap_update = false; 2085 u8 pre_x_cap = cfo->crystal_cap; 2086 2087 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", 2088 rtwdev->total_sta_assoc); 2089 if (rtwdev->total_sta_assoc == 0) { 2090 rtw89_phy_cfo_reset(rtwdev); 2091 return; 2092 } 2093 if (cfo->packet_count == 0) { 2094 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); 2095 return; 2096 } 2097 if (cfo->packet_count == cfo->packet_count_pre) { 2098 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); 2099 return; 2100 } 2101 if (rtwdev->total_sta_assoc == 1) 2102 new_cfo = rtw89_phy_average_cfo_calc(rtwdev); 2103 else 2104 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); 2105 if (new_cfo == 0) { 2106 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); 2107 return; 2108 } 2109 if (cfo->divergence_lock_en) { 2110 cfo->lock_cnt++; 2111 if (cfo->lock_cnt > CFO_PERIOD_CNT) { 2112 cfo->divergence_lock_en = false; 2113 cfo->lock_cnt = 0; 2114 } else { 2115 rtw89_phy_cfo_reset(rtwdev); 2116 } 2117 return; 2118 } 2119 if (cfo->crystal_cap >= cfo->x_cap_ub || 2120 cfo->crystal_cap <= cfo->x_cap_lb) { 2121 cfo->divergence_lock_en = true; 2122 rtw89_phy_cfo_reset(rtwdev); 2123 return; 2124 } 2125 2126 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); 2127 cfo->cfo_avg_pre = new_cfo; 2128 x_cap_update = cfo->crystal_cap != pre_x_cap; 2129 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); 2130 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", 2131 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, 2132 cfo->x_cap_ofst); 2133 if (x_cap_update) { 2134 if (new_cfo > 0) 2135 new_cfo -= CFO_SW_COMP_FINE_TUNE; 2136 else 2137 new_cfo += CFO_SW_COMP_FINE_TUNE; 2138 } 2139 rtw89_dcfo_comp(rtwdev, new_cfo); 2140 rtw89_phy_cfo_statistics_reset(rtwdev); 2141 } 2142 2143 void rtw89_phy_cfo_track_work(struct work_struct *work) 2144 { 2145 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2146 cfo_track_work.work); 2147 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2148 2149 mutex_lock(&rtwdev->mutex); 2150 if (!cfo->cfo_trig_by_timer_en) 2151 goto out; 2152 rtw89_leave_ps_mode(rtwdev); 2153 rtw89_phy_cfo_dm(rtwdev); 2154 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2155 msecs_to_jiffies(cfo->cfo_timer_ms)); 2156 out: 2157 mutex_unlock(&rtwdev->mutex); 2158 } 2159 2160 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) 2161 { 2162 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2163 2164 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2165 msecs_to_jiffies(cfo->cfo_timer_ms)); 2166 } 2167 2168 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) 2169 { 2170 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2171 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2172 2173 switch (cfo->phy_cfo_status) { 2174 case RTW89_PHY_DCFO_STATE_NORMAL: 2175 if (stats->tx_throughput >= CFO_TP_UPPER) { 2176 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; 2177 cfo->cfo_trig_by_timer_en = true; 2178 cfo->cfo_timer_ms = CFO_COMP_PERIOD; 2179 rtw89_phy_cfo_start_work(rtwdev); 2180 } 2181 break; 2182 case RTW89_PHY_DCFO_STATE_ENHANCE: 2183 if (cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) { 2184 cfo->phy_cfo_trk_cnt = 0; 2185 cfo->cfo_trig_by_timer_en = false; 2186 } 2187 if (cfo->cfo_trig_by_timer_en == 1) 2188 cfo->phy_cfo_trk_cnt++; 2189 if (stats->tx_throughput <= CFO_TP_LOWER) { 2190 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2191 cfo->phy_cfo_trk_cnt = 0; 2192 cfo->cfo_trig_by_timer_en = false; 2193 } 2194 break; 2195 default: 2196 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2197 cfo->phy_cfo_trk_cnt = 0; 2198 break; 2199 } 2200 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2201 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", 2202 stats->tx_throughput, cfo->phy_cfo_status, 2203 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, 2204 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); 2205 if (cfo->cfo_trig_by_timer_en) 2206 return; 2207 rtw89_phy_cfo_dm(rtwdev); 2208 } 2209 2210 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 2211 struct rtw89_rx_phy_ppdu *phy_ppdu) 2212 { 2213 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2214 u8 macid = phy_ppdu->mac_id; 2215 2216 cfo->cfo_tail[macid] += cfo_val; 2217 cfo->cfo_cnt[macid]++; 2218 cfo->packet_count++; 2219 } 2220 2221 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) 2222 { 2223 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2224 int i; 2225 u8 th; 2226 2227 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 2228 th = rtw89_chip_get_thermal(rtwdev, i); 2229 if (th) 2230 ewma_thermal_add(&phystat->avg_thermal[i], th); 2231 2232 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 2233 "path(%d) thermal cur=%u avg=%ld", i, th, 2234 ewma_thermal_read(&phystat->avg_thermal[i])); 2235 } 2236 } 2237 2238 struct rtw89_phy_iter_rssi_data { 2239 struct rtw89_dev *rtwdev; 2240 struct rtw89_phy_ch_info *ch_info; 2241 bool rssi_changed; 2242 }; 2243 2244 static void rtw89_phy_stat_rssi_update_iter(void *data, 2245 struct ieee80211_sta *sta) 2246 { 2247 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2248 struct rtw89_phy_iter_rssi_data *rssi_data = 2249 (struct rtw89_phy_iter_rssi_data *)data; 2250 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info; 2251 unsigned long rssi_curr; 2252 2253 rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi); 2254 2255 if (rssi_curr < ch_info->rssi_min) { 2256 ch_info->rssi_min = rssi_curr; 2257 ch_info->rssi_min_macid = rtwsta->mac_id; 2258 } 2259 2260 if (rtwsta->prev_rssi == 0) { 2261 rtwsta->prev_rssi = rssi_curr; 2262 } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) { 2263 rtwsta->prev_rssi = rssi_curr; 2264 rssi_data->rssi_changed = true; 2265 } 2266 } 2267 2268 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) 2269 { 2270 struct rtw89_phy_iter_rssi_data rssi_data = {0}; 2271 2272 rssi_data.rtwdev = rtwdev; 2273 rssi_data.ch_info = &rtwdev->ch_info; 2274 rssi_data.ch_info->rssi_min = U8_MAX; 2275 ieee80211_iterate_stations_atomic(rtwdev->hw, 2276 rtw89_phy_stat_rssi_update_iter, 2277 &rssi_data); 2278 if (rssi_data.rssi_changed) 2279 rtw89_btc_ntfy_wl_sta(rtwdev); 2280 } 2281 2282 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) 2283 { 2284 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2285 int i; 2286 2287 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 2288 ewma_thermal_init(&phystat->avg_thermal[i]); 2289 2290 rtw89_phy_stat_thermal_update(rtwdev); 2291 2292 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 2293 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); 2294 } 2295 2296 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) 2297 { 2298 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2299 2300 rtw89_phy_stat_thermal_update(rtwdev); 2301 rtw89_phy_stat_rssi_update(rtwdev); 2302 2303 phystat->last_pkt_stat = phystat->cur_pkt_stat; 2304 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 2305 } 2306 2307 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us) 2308 { 2309 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2310 2311 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 2312 } 2313 2314 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) 2315 { 2316 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2317 2318 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 2319 } 2320 2321 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) 2322 { 2323 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2324 2325 env->ccx_manual_ctrl = false; 2326 env->ccx_ongoing = false; 2327 env->ccx_rac_lv = RTW89_RAC_RELEASE; 2328 env->ccx_rpt_stamp = 0; 2329 env->ccx_period = 0; 2330 env->ccx_unit_idx = RTW89_CCX_32_US; 2331 env->ccx_trigger_time = 0; 2332 env->ccx_edcca_opt_bw_idx = RTW89_CCX_EDCCA_BW20_0; 2333 2334 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1); 2335 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1); 2336 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 2337 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EDCCA_OPT_MSK, 2338 RTW89_CCX_EDCCA_BW20_0); 2339 } 2340 2341 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report, 2342 u16 score) 2343 { 2344 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2345 u32 numer = 0; 2346 u16 ret = 0; 2347 2348 numer = report * score + (env->ccx_period >> 1); 2349 if (env->ccx_period) 2350 ret = numer / env->ccx_period; 2351 2352 return ret >= score ? score - 1 : ret; 2353 } 2354 2355 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, 2356 u16 time_ms, u32 *period, 2357 u32 *unit_idx) 2358 { 2359 u32 idx; 2360 u8 quotient; 2361 2362 if (time_ms >= CCX_MAX_PERIOD) 2363 time_ms = CCX_MAX_PERIOD; 2364 2365 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; 2366 2367 if (quotient < 4) 2368 idx = RTW89_CCX_4_US; 2369 else if (quotient < 8) 2370 idx = RTW89_CCX_8_US; 2371 else if (quotient < 16) 2372 idx = RTW89_CCX_16_US; 2373 else 2374 idx = RTW89_CCX_32_US; 2375 2376 *unit_idx = idx; 2377 *period = (time_ms * MS_TO_4US_RATIO) >> idx; 2378 2379 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2380 "[Trigger Time] period:%d, unit_idx:%d\n", 2381 *period, *unit_idx); 2382 } 2383 2384 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev) 2385 { 2386 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2387 2388 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2389 "lv:(%d)->(0)\n", env->ccx_rac_lv); 2390 2391 env->ccx_ongoing = false; 2392 env->ccx_rac_lv = RTW89_RAC_RELEASE; 2393 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 2394 } 2395 2396 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, 2397 struct rtw89_ccx_para_info *para) 2398 { 2399 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2400 bool is_update = env->ifs_clm_app != para->ifs_clm_app; 2401 u8 i = 0; 2402 u16 *ifs_th_l = env->ifs_clm_th_l; 2403 u16 *ifs_th_h = env->ifs_clm_th_h; 2404 u32 ifs_th0_us = 0, ifs_th_times = 0; 2405 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; 2406 2407 if (!is_update) 2408 goto ifs_update_finished; 2409 2410 switch (para->ifs_clm_app) { 2411 case RTW89_IFS_CLM_INIT: 2412 case RTW89_IFS_CLM_BACKGROUND: 2413 case RTW89_IFS_CLM_ACS: 2414 case RTW89_IFS_CLM_DBG: 2415 case RTW89_IFS_CLM_DIG: 2416 case RTW89_IFS_CLM_TDMA_DIG: 2417 ifs_th0_us = IFS_CLM_TH0_UPPER; 2418 ifs_th_times = IFS_CLM_TH_MUL; 2419 break; 2420 case RTW89_IFS_CLM_DBG_MANUAL: 2421 ifs_th0_us = para->ifs_clm_manual_th0; 2422 ifs_th_times = para->ifs_clm_manual_th_times; 2423 break; 2424 default: 2425 break; 2426 } 2427 2428 /* Set sampling threshold for 4 different regions, unit in idx_cnt. 2429 * low[i] = high[i-1] + 1 2430 * high[i] = high[i-1] * ifs_th_times 2431 */ 2432 ifs_th_l[IFS_CLM_TH_START_IDX] = 0; 2433 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; 2434 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, 2435 ifs_th0_us); 2436 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { 2437 ifs_th_l[i] = ifs_th_h[i - 1] + 1; 2438 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; 2439 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]); 2440 } 2441 2442 ifs_update_finished: 2443 if (!is_update) 2444 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2445 "No need to update IFS_TH\n"); 2446 2447 return is_update; 2448 } 2449 2450 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) 2451 { 2452 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2453 u8 i = 0; 2454 2455 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_LOW_MSK, 2456 env->ifs_clm_th_l[0]); 2457 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_LOW_MSK, 2458 env->ifs_clm_th_l[1]); 2459 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_LOW_MSK, 2460 env->ifs_clm_th_l[2]); 2461 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_LOW_MSK, 2462 env->ifs_clm_th_l[3]); 2463 2464 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_HIGH_MSK, 2465 env->ifs_clm_th_h[0]); 2466 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_HIGH_MSK, 2467 env->ifs_clm_th_h[1]); 2468 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_HIGH_MSK, 2469 env->ifs_clm_th_h[2]); 2470 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_HIGH_MSK, 2471 env->ifs_clm_th_h[3]); 2472 2473 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 2474 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2475 "Update IFS_T%d_th{low, high} : {%d, %d}\n", 2476 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 2477 } 2478 2479 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) 2480 { 2481 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2482 struct rtw89_ccx_para_info para = {0}; 2483 2484 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 2485 env->ifs_clm_mntr_time = 0; 2486 2487 para.ifs_clm_app = RTW89_IFS_CLM_INIT; 2488 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) 2489 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 2490 2491 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COLLECT_EN, 2492 true); 2493 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_EN_MSK, true); 2494 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_EN_MSK, true); 2495 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_EN_MSK, true); 2496 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_EN_MSK, true); 2497 } 2498 2499 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, 2500 enum rtw89_env_racing_lv level) 2501 { 2502 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2503 int ret = 0; 2504 2505 if (level >= RTW89_RAC_MAX_NUM) { 2506 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2507 "[WARNING] Wrong LV=%d\n", level); 2508 return -EINVAL; 2509 } 2510 2511 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2512 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, 2513 env->ccx_rac_lv, level); 2514 2515 if (env->ccx_ongoing) { 2516 if (level <= env->ccx_rac_lv) 2517 ret = -EINVAL; 2518 else 2519 env->ccx_ongoing = false; 2520 } 2521 2522 if (ret == 0) 2523 env->ccx_rac_lv = level; 2524 2525 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", 2526 !ret); 2527 2528 return ret; 2529 } 2530 2531 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) 2532 { 2533 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2534 2535 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 0); 2536 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 0); 2537 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1); 2538 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 2539 2540 env->ccx_rpt_stamp++; 2541 env->ccx_ongoing = true; 2542 } 2543 2544 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) 2545 { 2546 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2547 u8 i = 0; 2548 u32 res = 0; 2549 2550 env->ifs_clm_tx_ratio = 2551 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT); 2552 env->ifs_clm_edcca_excl_cca_ratio = 2553 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca, 2554 PERCENT); 2555 env->ifs_clm_cck_fa_ratio = 2556 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT); 2557 env->ifs_clm_ofdm_fa_ratio = 2558 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT); 2559 env->ifs_clm_cck_cca_excl_fa_ratio = 2560 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa, 2561 PERCENT); 2562 env->ifs_clm_ofdm_cca_excl_fa_ratio = 2563 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa, 2564 PERCENT); 2565 env->ifs_clm_cck_fa_permil = 2566 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL); 2567 env->ifs_clm_ofdm_fa_permil = 2568 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL); 2569 2570 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { 2571 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { 2572 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; 2573 } else { 2574 env->ifs_clm_ifs_avg[i] = 2575 rtw89_phy_ccx_idx_to_us(rtwdev, 2576 env->ifs_clm_avg[i]); 2577 } 2578 2579 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]); 2580 res += env->ifs_clm_his[i] >> 1; 2581 if (env->ifs_clm_his[i]) 2582 res /= env->ifs_clm_his[i]; 2583 else 2584 res = 0; 2585 env->ifs_clm_cca_avg[i] = res; 2586 } 2587 2588 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2589 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", 2590 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); 2591 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2592 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", 2593 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); 2594 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2595 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", 2596 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); 2597 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2598 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", 2599 env->ifs_clm_cck_cca_excl_fa_ratio, 2600 env->ifs_clm_ofdm_cca_excl_fa_ratio); 2601 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2602 "Time:[his, ifs_avg(us), cca_avg(us)]\n"); 2603 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 2604 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 2605 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 2606 env->ifs_clm_cca_avg[i]); 2607 } 2608 2609 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) 2610 { 2611 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2612 u8 i = 0; 2613 2614 if (rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_DONE_MSK) == 0) { 2615 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2616 "Get IFS_CLM report Fail\n"); 2617 return false; 2618 } 2619 2620 env->ifs_clm_tx = 2621 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 2622 B_IFS_CLM_TX_CNT_MSK); 2623 env->ifs_clm_edcca_excl_cca = 2624 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 2625 B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK); 2626 env->ifs_clm_cckcca_excl_fa = 2627 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 2628 B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK); 2629 env->ifs_clm_ofdmcca_excl_fa = 2630 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 2631 B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK); 2632 env->ifs_clm_cckfa = 2633 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 2634 B_IFS_CLM_CCK_FA_MSK); 2635 env->ifs_clm_ofdmfa = 2636 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 2637 B_IFS_CLM_OFDM_FA_MSK); 2638 2639 env->ifs_clm_his[0] = 2640 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T1_HIS_MSK); 2641 env->ifs_clm_his[1] = 2642 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T2_HIS_MSK); 2643 env->ifs_clm_his[2] = 2644 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T3_HIS_MSK); 2645 env->ifs_clm_his[3] = 2646 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T4_HIS_MSK); 2647 2648 env->ifs_clm_avg[0] = 2649 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T1_AVG_MSK); 2650 env->ifs_clm_avg[1] = 2651 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T2_AVG_MSK); 2652 env->ifs_clm_avg[2] = 2653 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T3_AVG_MSK); 2654 env->ifs_clm_avg[3] = 2655 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T4_AVG_MSK); 2656 2657 env->ifs_clm_cca[0] = 2658 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T1_CCA_MSK); 2659 env->ifs_clm_cca[1] = 2660 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T2_CCA_MSK); 2661 env->ifs_clm_cca[2] = 2662 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T3_CCA_MSK); 2663 env->ifs_clm_cca[3] = 2664 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T4_CCA_MSK); 2665 2666 env->ifs_clm_total_ifs = 2667 rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_TOTAL_CNT_MSK); 2668 2669 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", 2670 env->ifs_clm_total_ifs); 2671 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2672 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", 2673 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); 2674 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2675 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", 2676 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); 2677 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2678 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", 2679 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); 2680 2681 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); 2682 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 2683 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2684 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], 2685 env->ifs_clm_avg[i], env->ifs_clm_cca[i]); 2686 2687 rtw89_phy_ifs_clm_get_utility(rtwdev); 2688 2689 return true; 2690 } 2691 2692 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 2693 struct rtw89_ccx_para_info *para) 2694 { 2695 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2696 u32 period = 0; 2697 u32 unit_idx = 0; 2698 2699 if (para->mntr_time == 0) { 2700 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2701 "[WARN] MNTR_TIME is 0\n"); 2702 return -EINVAL; 2703 } 2704 2705 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv)) 2706 return -EINVAL; 2707 2708 if (para->mntr_time != env->ifs_clm_mntr_time) { 2709 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 2710 &period, &unit_idx); 2711 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 2712 B_IFS_CLM_PERIOD_MSK, period); 2713 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 2714 B_IFS_CLM_COUNTER_UNIT_MSK, unit_idx); 2715 2716 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2717 "Update IFS-CLM time ((%d)) -> ((%d))\n", 2718 env->ifs_clm_mntr_time, para->mntr_time); 2719 2720 env->ifs_clm_mntr_time = para->mntr_time; 2721 env->ccx_period = (u16)period; 2722 env->ccx_unit_idx = (u8)unit_idx; 2723 } 2724 2725 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) { 2726 env->ifs_clm_app = para->ifs_clm_app; 2727 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 2728 } 2729 2730 return 0; 2731 } 2732 2733 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) 2734 { 2735 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2736 struct rtw89_ccx_para_info para = {0}; 2737 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; 2738 2739 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; 2740 if (env->ccx_manual_ctrl) { 2741 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2742 "CCX in manual ctrl\n"); 2743 return; 2744 } 2745 2746 /* only ifs_clm for now */ 2747 if (rtw89_phy_ifs_clm_get_result(rtwdev)) 2748 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; 2749 2750 rtw89_phy_ccx_racing_release(rtwdev); 2751 para.mntr_time = 1900; 2752 para.rac_lv = RTW89_RAC_LV_1; 2753 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 2754 2755 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0) 2756 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 2757 if (chk_result) 2758 rtw89_phy_ccx_trigger(rtwdev); 2759 2760 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2761 "get_result=0x%x, chk_result:0x%x\n", 2762 env->ccx_watchdog_result, chk_result); 2763 } 2764 2765 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page) 2766 { 2767 if (*ie_page > RTW89_PHYSTS_BITMAP_NUM || 2768 *ie_page == RTW89_RSVD_9) 2769 return false; 2770 else if (*ie_page > RTW89_RSVD_9) 2771 *ie_page -= 1; 2772 2773 return true; 2774 } 2775 2776 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) 2777 { 2778 static const u8 ie_page_shift = 2; 2779 2780 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); 2781 } 2782 2783 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, 2784 enum rtw89_phy_status_bitmap ie_page) 2785 { 2786 u32 addr; 2787 2788 if (!rtw89_physts_ie_page_valid(&ie_page)) 2789 return 0; 2790 2791 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 2792 2793 return rtw89_phy_read32(rtwdev, addr); 2794 } 2795 2796 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, 2797 enum rtw89_phy_status_bitmap ie_page, 2798 u32 val) 2799 { 2800 const struct rtw89_chip_info *chip = rtwdev->chip; 2801 u32 addr; 2802 2803 if (!rtw89_physts_ie_page_valid(&ie_page)) 2804 return; 2805 2806 if (chip->chip_id == RTL8852A) 2807 val &= B_PHY_STS_BITMAP_MSK_52A; 2808 2809 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 2810 rtw89_phy_write32(rtwdev, addr, val); 2811 } 2812 2813 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev, 2814 enum rtw89_phy_status_bitmap bitmap, 2815 enum rtw89_phy_status_ie_type ie, 2816 bool enable) 2817 { 2818 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap); 2819 2820 if (enable) 2821 val |= BIT(ie); 2822 else 2823 val &= ~BIT(ie); 2824 2825 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val); 2826 } 2827 2828 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, 2829 bool enable, 2830 enum rtw89_phy_idx phy_idx) 2831 { 2832 if (enable) { 2833 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 2834 B_STS_DIS_TRIG_BY_FAIL); 2835 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 2836 B_STS_DIS_TRIG_BY_BRK); 2837 } else { 2838 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 2839 B_STS_DIS_TRIG_BY_FAIL); 2840 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 2841 B_STS_DIS_TRIG_BY_BRK); 2842 } 2843 } 2844 2845 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev) 2846 { 2847 const struct rtw89_chip_info *chip = rtwdev->chip; 2848 u8 i; 2849 2850 if (chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 2851 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0); 2852 2853 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { 2854 if (i >= RTW89_CCK_PKT) 2855 rtw89_physts_enable_ie_bitmap(rtwdev, i, 2856 RTW89_PHYSTS_IE09_FTR_0, 2857 true); 2858 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) || 2859 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT)) 2860 continue; 2861 rtw89_physts_enable_ie_bitmap(rtwdev, i, 2862 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A, 2863 true); 2864 } 2865 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT, 2866 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 2867 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT, 2868 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 2869 2870 /* force IE01 for channel index, only channel field is valid */ 2871 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT, 2872 RTW89_PHYSTS_IE01_CMN_OFDM, true); 2873 } 2874 2875 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) 2876 { 2877 const struct rtw89_chip_info *chip = rtwdev->chip; 2878 struct rtw89_dig_info *dig = &rtwdev->dig; 2879 const struct rtw89_phy_dig_gain_cfg *cfg; 2880 const char *msg; 2881 u8 i; 2882 s8 gain_base; 2883 s8 *gain_arr; 2884 u32 tmp; 2885 2886 switch (type) { 2887 case RTW89_DIG_GAIN_LNA_G: 2888 gain_arr = dig->lna_gain_g; 2889 gain_base = LNA0_GAIN; 2890 cfg = chip->dig_table->cfg_lna_g; 2891 msg = "lna_gain_g"; 2892 break; 2893 case RTW89_DIG_GAIN_TIA_G: 2894 gain_arr = dig->tia_gain_g; 2895 gain_base = TIA0_GAIN_G; 2896 cfg = chip->dig_table->cfg_tia_g; 2897 msg = "tia_gain_g"; 2898 break; 2899 case RTW89_DIG_GAIN_LNA_A: 2900 gain_arr = dig->lna_gain_a; 2901 gain_base = LNA0_GAIN; 2902 cfg = chip->dig_table->cfg_lna_a; 2903 msg = "lna_gain_a"; 2904 break; 2905 case RTW89_DIG_GAIN_TIA_A: 2906 gain_arr = dig->tia_gain_a; 2907 gain_base = TIA0_GAIN_A; 2908 cfg = chip->dig_table->cfg_tia_a; 2909 msg = "tia_gain_a"; 2910 break; 2911 default: 2912 return; 2913 } 2914 2915 for (i = 0; i < cfg->size; i++) { 2916 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr, 2917 cfg->table[i].mask); 2918 tmp >>= DIG_GAIN_SHIFT; 2919 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; 2920 gain_base += DIG_GAIN; 2921 2922 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", 2923 msg, i, gain_arr[i]); 2924 } 2925 } 2926 2927 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev) 2928 { 2929 struct rtw89_dig_info *dig = &rtwdev->dig; 2930 u32 tmp; 2931 u8 i; 2932 2933 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW, 2934 B_PATH0_IB_PKPW_MSK); 2935 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); 2936 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK, 2937 B_PATH0_IB_PBK_MSK); 2938 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", 2939 dig->ib_pkpwr, dig->ib_pbk); 2940 2941 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) 2942 rtw89_phy_dig_read_gain_table(rtwdev, i); 2943 } 2944 2945 static const u8 rssi_nolink = 22; 2946 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; 2947 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; 2948 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; 2949 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; 2950 2951 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev) 2952 { 2953 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 2954 struct rtw89_dig_info *dig = &rtwdev->dig; 2955 bool is_linked = rtwdev->total_sta_assoc > 0; 2956 2957 if (is_linked) { 2958 dig->igi_rssi = ch_info->rssi_min >> 1; 2959 } else { 2960 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); 2961 dig->igi_rssi = rssi_nolink; 2962 } 2963 } 2964 2965 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev) 2966 { 2967 struct rtw89_dig_info *dig = &rtwdev->dig; 2968 bool is_linked = rtwdev->total_sta_assoc > 0; 2969 const u16 *fa_th_src = NULL; 2970 2971 switch (rtwdev->hal.current_band_type) { 2972 case RTW89_BAND_2G: 2973 dig->lna_gain = dig->lna_gain_g; 2974 dig->tia_gain = dig->tia_gain_g; 2975 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; 2976 dig->force_gaincode_idx_en = false; 2977 dig->dyn_pd_th_en = true; 2978 break; 2979 case RTW89_BAND_5G: 2980 default: 2981 dig->lna_gain = dig->lna_gain_a; 2982 dig->tia_gain = dig->tia_gain_a; 2983 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; 2984 dig->force_gaincode_idx_en = true; 2985 dig->dyn_pd_th_en = true; 2986 break; 2987 } 2988 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); 2989 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); 2990 } 2991 2992 static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20; 2993 static const u8 igi_max_performance_mode = 0x5a; 2994 static const u8 dynamic_pd_threshold_max; 2995 2996 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev) 2997 { 2998 struct rtw89_dig_info *dig = &rtwdev->dig; 2999 3000 dig->cur_gaincode.lna_idx = LNA_IDX_MAX; 3001 dig->cur_gaincode.tia_idx = TIA_IDX_MAX; 3002 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; 3003 dig->force_gaincode.lna_idx = LNA_IDX_MAX; 3004 dig->force_gaincode.tia_idx = TIA_IDX_MAX; 3005 dig->force_gaincode.rxb_idx = RXB_IDX_MAX; 3006 3007 dig->dyn_igi_max = igi_max_performance_mode; 3008 dig->dyn_igi_min = dynamic_igi_min; 3009 dig->dyn_pd_th_max = dynamic_pd_threshold_max; 3010 dig->pd_low_th_ofst = pd_low_th_offset; 3011 dig->is_linked_pre = false; 3012 } 3013 3014 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) 3015 { 3016 rtw89_phy_dig_update_gain_para(rtwdev); 3017 rtw89_phy_dig_reset(rtwdev); 3018 } 3019 3020 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3021 { 3022 struct rtw89_dig_info *dig = &rtwdev->dig; 3023 u8 lna_idx; 3024 3025 if (rssi < dig->igi_rssi_th[0]) 3026 lna_idx = RTW89_DIG_GAIN_LNA_IDX6; 3027 else if (rssi < dig->igi_rssi_th[1]) 3028 lna_idx = RTW89_DIG_GAIN_LNA_IDX5; 3029 else if (rssi < dig->igi_rssi_th[2]) 3030 lna_idx = RTW89_DIG_GAIN_LNA_IDX4; 3031 else if (rssi < dig->igi_rssi_th[3]) 3032 lna_idx = RTW89_DIG_GAIN_LNA_IDX3; 3033 else if (rssi < dig->igi_rssi_th[4]) 3034 lna_idx = RTW89_DIG_GAIN_LNA_IDX2; 3035 else 3036 lna_idx = RTW89_DIG_GAIN_LNA_IDX1; 3037 3038 return lna_idx; 3039 } 3040 3041 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3042 { 3043 struct rtw89_dig_info *dig = &rtwdev->dig; 3044 u8 tia_idx; 3045 3046 if (rssi < dig->igi_rssi_th[0]) 3047 tia_idx = RTW89_DIG_GAIN_TIA_IDX1; 3048 else 3049 tia_idx = RTW89_DIG_GAIN_TIA_IDX0; 3050 3051 return tia_idx; 3052 } 3053 3054 #define IB_PBK_BASE 110 3055 #define WB_RSSI_BASE 10 3056 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3057 struct rtw89_agc_gaincode_set *set) 3058 { 3059 struct rtw89_dig_info *dig = &rtwdev->dig; 3060 s8 lna_gain = dig->lna_gain[set->lna_idx]; 3061 s8 tia_gain = dig->tia_gain[set->tia_idx]; 3062 s32 wb_rssi = rssi + lna_gain + tia_gain; 3063 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; 3064 u8 rxb_idx; 3065 3066 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; 3067 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); 3068 3069 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", 3070 wb_rssi, rxb_idx_tmp); 3071 3072 return rxb_idx; 3073 } 3074 3075 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3076 struct rtw89_agc_gaincode_set *set) 3077 { 3078 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi); 3079 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi); 3080 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set); 3081 3082 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3083 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", 3084 rssi, set->lna_idx, set->tia_idx, set->rxb_idx); 3085 } 3086 3087 #define IGI_OFFSET_MAX 25 3088 #define IGI_OFFSET_MUL 2 3089 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev) 3090 { 3091 struct rtw89_dig_info *dig = &rtwdev->dig; 3092 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3093 enum rtw89_dig_noisy_level noisy_lv; 3094 u8 igi_offset = dig->fa_rssi_ofst; 3095 u16 fa_ratio = 0; 3096 3097 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; 3098 3099 if (fa_ratio < dig->fa_th[0]) 3100 noisy_lv = RTW89_DIG_NOISY_LEVEL0; 3101 else if (fa_ratio < dig->fa_th[1]) 3102 noisy_lv = RTW89_DIG_NOISY_LEVEL1; 3103 else if (fa_ratio < dig->fa_th[2]) 3104 noisy_lv = RTW89_DIG_NOISY_LEVEL2; 3105 else if (fa_ratio < dig->fa_th[3]) 3106 noisy_lv = RTW89_DIG_NOISY_LEVEL3; 3107 else 3108 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; 3109 3110 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) 3111 igi_offset = 0; 3112 else 3113 igi_offset += noisy_lv * IGI_OFFSET_MUL; 3114 3115 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); 3116 dig->fa_rssi_ofst = igi_offset; 3117 3118 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3119 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", 3120 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); 3121 3122 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3123 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", 3124 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, 3125 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, 3126 noisy_lv, igi_offset); 3127 } 3128 3129 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx) 3130 { 3131 rtw89_phy_write32_mask(rtwdev, R_PATH0_LNA_INIT, 3132 B_PATH0_LNA_INIT_IDX_MSK, lna_idx); 3133 rtw89_phy_write32_mask(rtwdev, R_PATH1_LNA_INIT, 3134 B_PATH1_LNA_INIT_IDX_MSK, lna_idx); 3135 } 3136 3137 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx) 3138 { 3139 rtw89_phy_write32_mask(rtwdev, R_PATH0_TIA_INIT, 3140 B_PATH0_TIA_INIT_IDX_MSK, tia_idx); 3141 rtw89_phy_write32_mask(rtwdev, R_PATH1_TIA_INIT, 3142 B_PATH1_TIA_INIT_IDX_MSK, tia_idx); 3143 } 3144 3145 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx) 3146 { 3147 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXB_INIT, 3148 B_PATH0_RXB_INIT_IDX_MSK, rxb_idx); 3149 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXB_INIT, 3150 B_PATH1_RXB_INIT_IDX_MSK, rxb_idx); 3151 } 3152 3153 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, 3154 const struct rtw89_agc_gaincode_set set) 3155 { 3156 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx); 3157 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx); 3158 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx); 3159 3160 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", 3161 set.lna_idx, set.tia_idx, set.rxb_idx); 3162 } 3163 3164 static const struct rtw89_reg_def sdagc_config[4] = { 3165 {R_PATH0_P20_FOLLOW_BY_PAGCUGC, B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 3166 {R_PATH0_S20_FOLLOW_BY_PAGCUGC, B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 3167 {R_PATH1_P20_FOLLOW_BY_PAGCUGC, B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 3168 {R_PATH1_S20_FOLLOW_BY_PAGCUGC, B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 3169 }; 3170 3171 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, 3172 bool enable) 3173 { 3174 u8 i = 0; 3175 3176 for (i = 0; i < ARRAY_SIZE(sdagc_config); i++) 3177 rtw89_phy_write32_mask(rtwdev, sdagc_config[i].addr, 3178 sdagc_config[i].mask, enable); 3179 3180 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); 3181 } 3182 3183 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, 3184 bool enable) 3185 { 3186 enum rtw89_bandwidth cbw = rtwdev->hal.current_band_width; 3187 struct rtw89_dig_info *dig = &rtwdev->dig; 3188 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; 3189 u8 ofdm_cca_th; 3190 s8 cck_cca_th; 3191 u32 pd_val = 0; 3192 3193 under_region += PD_TH_SB_FLTR_CMP_VAL; 3194 3195 switch (cbw) { 3196 case RTW89_CHANNEL_WIDTH_40: 3197 under_region += PD_TH_BW40_CMP_VAL; 3198 break; 3199 case RTW89_CHANNEL_WIDTH_80: 3200 under_region += PD_TH_BW80_CMP_VAL; 3201 break; 3202 case RTW89_CHANNEL_WIDTH_160: 3203 under_region += PD_TH_BW160_CMP_VAL; 3204 break; 3205 case RTW89_CHANNEL_WIDTH_20: 3206 fallthrough; 3207 default: 3208 under_region += PD_TH_BW20_CMP_VAL; 3209 break; 3210 } 3211 3212 dig->dyn_pd_th_max = dig->igi_rssi; 3213 3214 final_rssi = min_t(u8, rssi, dig->igi_rssi); 3215 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, 3216 PD_TH_MAX_RSSI + under_region); 3217 3218 if (enable) { 3219 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1; 3220 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3221 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n", 3222 final_rssi, ofdm_cca_th, under_region, pd_val); 3223 } else { 3224 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3225 "Dynamic PD th disabled, Set PD_low_bd=0\n"); 3226 } 3227 3228 rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, B_SEG0R_PD_LOWER_BOUND_MSK, 3229 pd_val); 3230 rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, 3231 B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, enable); 3232 3233 if (!rtwdev->hal.support_cckpd) 3234 return; 3235 3236 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI); 3237 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX); 3238 3239 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3240 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n", 3241 final_rssi, cck_cca_th, under_region, pd_val); 3242 3243 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_EN_V1, 3244 B_BMODE_PDTH_LIMIT_EN_MSK_V1, enable); 3245 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_V1, 3246 B_BMODE_PDTH_LOWER_BOUND_MSK_V1, pd_val); 3247 } 3248 3249 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) 3250 { 3251 struct rtw89_dig_info *dig = &rtwdev->dig; 3252 3253 dig->bypass_dig = false; 3254 rtw89_phy_dig_para_reset(rtwdev); 3255 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 3256 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false); 3257 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 3258 rtw89_phy_dig_update_para(rtwdev); 3259 } 3260 3261 #define IGI_RSSI_MIN 10 3262 void rtw89_phy_dig(struct rtw89_dev *rtwdev) 3263 { 3264 struct rtw89_dig_info *dig = &rtwdev->dig; 3265 bool is_linked = rtwdev->total_sta_assoc > 0; 3266 3267 if (unlikely(dig->bypass_dig)) { 3268 dig->bypass_dig = false; 3269 return; 3270 } 3271 3272 if (!dig->is_linked_pre && is_linked) { 3273 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); 3274 rtw89_phy_dig_update_para(rtwdev); 3275 } else if (dig->is_linked_pre && !is_linked) { 3276 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); 3277 rtw89_phy_dig_update_para(rtwdev); 3278 } 3279 dig->is_linked_pre = is_linked; 3280 3281 rtw89_phy_dig_igi_offset_by_env(rtwdev); 3282 rtw89_phy_dig_update_rssi_info(rtwdev); 3283 3284 dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ? 3285 dig->igi_rssi - IGI_RSSI_MIN : 0; 3286 dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX; 3287 dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst; 3288 3289 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, 3290 dig->dyn_igi_max); 3291 3292 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3293 "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n", 3294 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, 3295 dig->igi_fa_rssi); 3296 3297 if (dig->force_gaincode_idx_en) { 3298 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 3299 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3300 "Force gaincode index enabled.\n"); 3301 } else { 3302 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi, 3303 &dig->cur_gaincode); 3304 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode); 3305 } 3306 3307 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en); 3308 3309 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) 3310 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true); 3311 else 3312 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 3313 } 3314 3315 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) 3316 { 3317 rtw89_phy_ccx_top_setting_init(rtwdev); 3318 rtw89_phy_ifs_clm_setting_init(rtwdev); 3319 } 3320 3321 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 3322 { 3323 const struct rtw89_chip_info *chip = rtwdev->chip; 3324 3325 rtw89_phy_stat_init(rtwdev); 3326 3327 rtw89_chip_bb_sethw(rtwdev); 3328 3329 rtw89_phy_env_monitor_init(rtwdev); 3330 rtw89_physts_parsing_init(rtwdev); 3331 rtw89_phy_dig_init(rtwdev); 3332 rtw89_phy_cfo_init(rtwdev); 3333 3334 rtw89_phy_init_rf_nctl(rtwdev); 3335 rtw89_chip_rfk_init(rtwdev); 3336 rtw89_load_txpwr_table(rtwdev, chip->byr_table); 3337 rtw89_chip_set_txpwr_ctrl(rtwdev); 3338 rtw89_chip_power_trim(rtwdev); 3339 } 3340 3341 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 3342 { 3343 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 3344 u8 bss_color; 3345 3346 if (!vif->bss_conf.he_support || !vif->bss_conf.assoc) 3347 return; 3348 3349 bss_color = vif->bss_conf.he_bss_color.color; 3350 3351 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0, 0x1, 3352 phy_idx); 3353 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_TGT, bss_color, 3354 phy_idx); 3355 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_STAID, 3356 vif->bss_conf.aid, phy_idx); 3357 } 3358 3359 static void 3360 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3361 { 3362 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); 3363 } 3364 3365 static void 3366 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3367 { 3368 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 3369 } 3370 3371 static void 3372 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3373 { 3374 rtw89_phy_write32_set(rtwdev, def->addr, def->mask); 3375 } 3376 3377 static void 3378 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3379 { 3380 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); 3381 } 3382 3383 static void 3384 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3385 { 3386 udelay(def->data); 3387 } 3388 3389 static void 3390 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { 3391 [RTW89_RFK_F_WRF] = _rfk_write_rf, 3392 [RTW89_RFK_F_WM] = _rfk_write32_mask, 3393 [RTW89_RFK_F_WS] = _rfk_write32_set, 3394 [RTW89_RFK_F_WC] = _rfk_write32_clr, 3395 [RTW89_RFK_F_DELAY] = _rfk_delay, 3396 }; 3397 3398 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 3399 3400 void 3401 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) 3402 { 3403 const struct rtw89_reg5_def *p = tbl->defs; 3404 const struct rtw89_reg5_def *end = tbl->defs + tbl->size; 3405 3406 for (; p < end; p++) 3407 _rfk_handler[p->flag](rtwdev, p); 3408 } 3409 EXPORT_SYMBOL(rtw89_rfk_parser); 3410