1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "debug.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "ps.h" 10 #include "reg.h" 11 #include "sar.h" 12 #include "coex.h" 13 14 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, 15 const struct rtw89_ra_report *report) 16 { 17 u32 bit_rate = report->bit_rate; 18 19 /* lower than ofdm, do not aggregate */ 20 if (bit_rate < 550) 21 return 1; 22 23 /* avoid AMSDU for legacy rate */ 24 if (report->might_fallback_legacy) 25 return 1; 26 27 /* lower than 20M vht 2ss mcs8, make it small */ 28 if (bit_rate < 1800) 29 return 1200; 30 31 /* lower than 40M vht 2ss mcs9, make it medium */ 32 if (bit_rate < 4000) 33 return 2600; 34 35 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ 36 if (bit_rate < 7000) 37 return 3500; 38 39 return rtwdev->chip->max_amsdu_limit; 40 } 41 42 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) 43 { 44 u64 ra_mask = 0; 45 u8 mcs_cap; 46 int i, nss; 47 48 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { 49 mcs_cap = mcs_map & 0x3; 50 switch (mcs_cap) { 51 case 2: 52 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; 53 break; 54 case 1: 55 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; 56 break; 57 case 0: 58 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; 59 break; 60 default: 61 break; 62 } 63 } 64 65 return ra_mask; 66 } 67 68 static u64 get_he_ra_mask(struct ieee80211_sta *sta) 69 { 70 struct ieee80211_sta_he_cap cap = sta->deflink.he_cap; 71 u16 mcs_map; 72 73 switch (sta->deflink.bandwidth) { 74 case IEEE80211_STA_RX_BW_160: 75 if (cap.he_cap_elem.phy_cap_info[0] & 76 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) 77 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); 78 else 79 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); 80 break; 81 default: 82 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); 83 } 84 85 /* MCS11, MCS9, MCS7 */ 86 return get_mcs_ra_mask(mcs_map, 11, 2); 87 } 88 89 #define RA_FLOOR_TABLE_SIZE 7 90 #define RA_FLOOR_UP_GAP 3 91 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, 92 u8 ratr_state) 93 { 94 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; 95 u8 rssi_lv = 0; 96 u8 i; 97 98 rssi >>= 1; 99 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 100 if (i >= ratr_state) 101 rssi_lv_t[i] += RA_FLOOR_UP_GAP; 102 if (rssi < rssi_lv_t[i]) { 103 rssi_lv = i; 104 break; 105 } 106 } 107 if (rssi_lv == 0) 108 return 0xffffffffffffffffULL; 109 else if (rssi_lv == 1) 110 return 0xfffffffffffffff0ULL; 111 else if (rssi_lv == 2) 112 return 0xffffffffffffefe0ULL; 113 else if (rssi_lv == 3) 114 return 0xffffffffffffcfc0ULL; 115 else if (rssi_lv == 4) 116 return 0xffffffffffff8f80ULL; 117 else if (rssi_lv >= 5) 118 return 0xffffffffffff0f00ULL; 119 120 return 0xffffffffffffffffULL; 121 } 122 123 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak) 124 { 125 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 126 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 127 128 if (ra_mask == 0) 129 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 130 131 return ra_mask; 132 } 133 134 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 135 { 136 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 137 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 138 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 139 enum nl80211_band band; 140 u64 cfg_mask; 141 142 if (!rtwsta->use_cfg_mask) 143 return -1; 144 145 switch (chan->band_type) { 146 case RTW89_BAND_2G: 147 band = NL80211_BAND_2GHZ; 148 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, 149 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); 150 break; 151 case RTW89_BAND_5G: 152 band = NL80211_BAND_5GHZ; 153 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, 154 RA_MASK_OFDM_RATES); 155 break; 156 case RTW89_BAND_6G: 157 band = NL80211_BAND_6GHZ; 158 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy, 159 RA_MASK_OFDM_RATES); 160 break; 161 default: 162 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type); 163 return -1; 164 } 165 166 if (sta->deflink.he_cap.has_he) { 167 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], 168 RA_MASK_HE_1SS_RATES); 169 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], 170 RA_MASK_HE_2SS_RATES); 171 } else if (sta->deflink.vht_cap.vht_supported) { 172 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 173 RA_MASK_VHT_1SS_RATES); 174 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 175 RA_MASK_VHT_2SS_RATES); 176 } else if (sta->deflink.ht_cap.ht_supported) { 177 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 178 RA_MASK_HT_1SS_RATES); 179 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 180 RA_MASK_HT_2SS_RATES); 181 } 182 183 return cfg_mask; 184 } 185 186 static const u64 187 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, 188 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; 189 static const u64 190 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 191 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; 192 static const u64 193 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, 194 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; 195 196 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev, 197 struct rtw89_sta *rtwsta, 198 bool *fix_giltf_en, u8 *fix_giltf) 199 { 200 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 201 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 202 u8 band = chan->band_type; 203 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 204 u8 he_gi = mask->control[nl_band].he_gi; 205 u8 he_ltf = mask->control[nl_band].he_ltf; 206 207 if (!rtwsta->use_cfg_mask) 208 return; 209 210 if (he_ltf == 2 && he_gi == 2) { 211 *fix_giltf = RTW89_GILTF_LGI_4XHE32; 212 } else if (he_ltf == 2 && he_gi == 0) { 213 *fix_giltf = RTW89_GILTF_SGI_4XHE08; 214 } else if (he_ltf == 1 && he_gi == 1) { 215 *fix_giltf = RTW89_GILTF_2XHE16; 216 } else if (he_ltf == 1 && he_gi == 0) { 217 *fix_giltf = RTW89_GILTF_2XHE08; 218 } else if (he_ltf == 0 && he_gi == 1) { 219 *fix_giltf = RTW89_GILTF_1XHE16; 220 } else if (he_ltf == 0 && he_gi == 0) { 221 *fix_giltf = RTW89_GILTF_1XHE08; 222 } else { 223 *fix_giltf_en = false; 224 return; 225 } 226 227 *fix_giltf_en = true; 228 } 229 230 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 231 struct ieee80211_sta *sta, bool csi) 232 { 233 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 234 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 235 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 236 struct rtw89_ra_info *ra = &rtwsta->ra; 237 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 238 struct ieee80211_vif *vif = rtwvif_to_vif(rtwsta->rtwvif); 239 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; 240 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 241 u64 ra_mask = 0; 242 u64 ra_mask_bak; 243 u8 mode = 0; 244 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; 245 u8 bw_mode = 0; 246 u8 stbc_en = 0; 247 u8 ldpc_en = 0; 248 u8 fix_giltf = 0; 249 u8 i; 250 bool sgi = false; 251 bool fix_giltf_en = false; 252 253 memset(ra, 0, sizeof(*ra)); 254 /* Set the ra mask from sta's capability */ 255 if (sta->deflink.he_cap.has_he) { 256 mode |= RTW89_RA_MODE_HE; 257 csi_mode = RTW89_RA_RPT_MODE_HE; 258 ra_mask |= get_he_ra_mask(sta); 259 high_rate_masks = rtw89_ra_mask_he_rates; 260 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[2] & 261 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) 262 stbc_en = 1; 263 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[1] & 264 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) 265 ldpc_en = 1; 266 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta, &fix_giltf_en, &fix_giltf); 267 } else if (sta->deflink.vht_cap.vht_supported) { 268 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 269 270 mode |= RTW89_RA_MODE_VHT; 271 csi_mode = RTW89_RA_RPT_MODE_VHT; 272 /* MCS9, MCS8, MCS7 */ 273 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); 274 high_rate_masks = rtw89_ra_mask_vht_rates; 275 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 276 stbc_en = 1; 277 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 278 ldpc_en = 1; 279 } else if (sta->deflink.ht_cap.ht_supported) { 280 mode |= RTW89_RA_MODE_HT; 281 csi_mode = RTW89_RA_RPT_MODE_HT; 282 ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 48) | 283 ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 36) | 284 (sta->deflink.ht_cap.mcs.rx_mask[1] << 24) | 285 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 286 high_rate_masks = rtw89_ra_mask_ht_rates; 287 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 288 stbc_en = 1; 289 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 290 ldpc_en = 1; 291 } 292 293 switch (chan->band_type) { 294 case RTW89_BAND_2G: 295 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 296 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xf) 297 mode |= RTW89_RA_MODE_CCK; 298 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xff0) 299 mode |= RTW89_RA_MODE_OFDM; 300 break; 301 case RTW89_BAND_5G: 302 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 303 mode |= RTW89_RA_MODE_OFDM; 304 break; 305 case RTW89_BAND_6G: 306 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_6GHZ] << 4; 307 mode |= RTW89_RA_MODE_OFDM; 308 break; 309 default: 310 rtw89_err(rtwdev, "Unknown band type\n"); 311 break; 312 } 313 314 ra_mask_bak = ra_mask; 315 316 if (mode >= RTW89_RA_MODE_HT) { 317 u64 mask = 0; 318 for (i = 0; i < rtwdev->hal.tx_nss; i++) 319 mask |= high_rate_masks[i]; 320 if (mode & RTW89_RA_MODE_OFDM) 321 mask |= RA_MASK_SUBOFDM_RATES; 322 if (mode & RTW89_RA_MODE_CCK) 323 mask |= RA_MASK_SUBCCK_RATES; 324 ra_mask &= mask; 325 } else if (mode & RTW89_RA_MODE_OFDM) { 326 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES); 327 } 328 329 if (mode != RTW89_RA_MODE_CCK) 330 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); 331 332 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak); 333 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 334 335 switch (sta->deflink.bandwidth) { 336 case IEEE80211_STA_RX_BW_160: 337 bw_mode = RTW89_CHANNEL_WIDTH_160; 338 sgi = sta->deflink.vht_cap.vht_supported && 339 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160); 340 break; 341 case IEEE80211_STA_RX_BW_80: 342 bw_mode = RTW89_CHANNEL_WIDTH_80; 343 sgi = sta->deflink.vht_cap.vht_supported && 344 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 345 break; 346 case IEEE80211_STA_RX_BW_40: 347 bw_mode = RTW89_CHANNEL_WIDTH_40; 348 sgi = sta->deflink.ht_cap.ht_supported && 349 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 350 break; 351 default: 352 bw_mode = RTW89_CHANNEL_WIDTH_20; 353 sgi = sta->deflink.ht_cap.ht_supported && 354 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 355 break; 356 } 357 358 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 359 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) 360 ra->dcm_cap = 1; 361 362 if (rate_pattern->enable && !vif->p2p) { 363 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 364 ra_mask &= rate_pattern->ra_mask; 365 mode = rate_pattern->ra_mode; 366 } 367 368 ra->bw_cap = bw_mode; 369 ra->mode_ctrl = mode; 370 ra->macid = rtwsta->mac_id; 371 ra->stbc_cap = stbc_en; 372 ra->ldpc_cap = ldpc_en; 373 ra->ss_num = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1; 374 ra->en_sgi = sgi; 375 ra->ra_mask = ra_mask; 376 ra->fix_giltf_en = fix_giltf_en; 377 ra->fix_giltf = fix_giltf; 378 379 if (!csi) 380 return; 381 382 ra->fixed_csi_rate_en = false; 383 ra->ra_csi_rate_en = true; 384 ra->cr_tbl_sel = false; 385 ra->band_num = rtwvif->phy_idx; 386 ra->csi_bw = bw_mode; 387 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; 388 ra->csi_mcs_ss_idx = 5; 389 ra->csi_mode = csi_mode; 390 } 391 392 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 393 u32 changed) 394 { 395 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 396 struct rtw89_ra_info *ra = &rtwsta->ra; 397 398 rtw89_phy_ra_sta_update(rtwdev, sta, false); 399 400 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) 401 ra->upd_mask = 1; 402 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED)) 403 ra->upd_bw_nss_mask = 1; 404 405 rtw89_debug(rtwdev, RTW89_DBG_RA, 406 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", 407 ra->macid, 408 ra->bw_cap, 409 ra->ss_num, 410 ra->en_sgi, 411 ra->giltf); 412 413 rtw89_fw_h2c_ra(rtwdev, ra, false); 414 } 415 416 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, 417 u16 rate_base, u64 ra_mask, u8 ra_mode, 418 u32 rate_ctrl, u32 ctrl_skip, bool force) 419 { 420 u8 n, c; 421 422 if (rate_ctrl == ctrl_skip) 423 return true; 424 425 n = hweight32(rate_ctrl); 426 if (n == 0) 427 return true; 428 429 if (force && n != 1) 430 return false; 431 432 if (next->enable) 433 return false; 434 435 c = __fls(rate_ctrl); 436 next->rate = rate_base + c; 437 next->ra_mode = ra_mode; 438 next->ra_mask = ra_mask; 439 next->enable = true; 440 441 return true; 442 } 443 444 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 445 struct ieee80211_vif *vif, 446 const struct cfg80211_bitrate_mask *mask) 447 { 448 struct ieee80211_supported_band *sband; 449 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 450 struct rtw89_phy_rate_pattern next_pattern = {0}; 451 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 452 static const u16 hw_rate_he[] = {RTW89_HW_RATE_HE_NSS1_MCS0, 453 RTW89_HW_RATE_HE_NSS2_MCS0, 454 RTW89_HW_RATE_HE_NSS3_MCS0, 455 RTW89_HW_RATE_HE_NSS4_MCS0}; 456 static const u16 hw_rate_vht[] = {RTW89_HW_RATE_VHT_NSS1_MCS0, 457 RTW89_HW_RATE_VHT_NSS2_MCS0, 458 RTW89_HW_RATE_VHT_NSS3_MCS0, 459 RTW89_HW_RATE_VHT_NSS4_MCS0}; 460 static const u16 hw_rate_ht[] = {RTW89_HW_RATE_MCS0, 461 RTW89_HW_RATE_MCS8, 462 RTW89_HW_RATE_MCS16, 463 RTW89_HW_RATE_MCS24}; 464 u8 band = chan->band_type; 465 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 466 u8 tx_nss = rtwdev->hal.tx_nss; 467 u8 i; 468 469 for (i = 0; i < tx_nss; i++) 470 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i], 471 RA_MASK_HE_RATES, RTW89_RA_MODE_HE, 472 mask->control[nl_band].he_mcs[i], 473 0, true)) 474 goto out; 475 476 for (i = 0; i < tx_nss; i++) 477 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i], 478 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, 479 mask->control[nl_band].vht_mcs[i], 480 0, true)) 481 goto out; 482 483 for (i = 0; i < tx_nss; i++) 484 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i], 485 RA_MASK_HT_RATES, RTW89_RA_MODE_HT, 486 mask->control[nl_band].ht_mcs[i], 487 0, true)) 488 goto out; 489 490 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and 491 * require at least one basic rate for ieee80211_set_bitrate_mask, 492 * so the decision just depends on if all bitrates are set or not. 493 */ 494 sband = rtwdev->hw->wiphy->bands[nl_band]; 495 if (band == RTW89_BAND_2G) { 496 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, 497 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, 498 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, 499 mask->control[nl_band].legacy, 500 BIT(sband->n_bitrates) - 1, false)) 501 goto out; 502 } else { 503 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, 504 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, 505 mask->control[nl_band].legacy, 506 BIT(sband->n_bitrates) - 1, false)) 507 goto out; 508 } 509 510 if (!next_pattern.enable) 511 goto out; 512 513 rtwvif->rate_pattern = next_pattern; 514 rtw89_debug(rtwdev, RTW89_DBG_RA, 515 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", 516 next_pattern.rate, 517 next_pattern.ra_mask, 518 next_pattern.ra_mode); 519 return; 520 521 out: 522 rtwvif->rate_pattern.enable = false; 523 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); 524 } 525 526 static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta) 527 { 528 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; 529 530 rtw89_phy_ra_updata_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED); 531 } 532 533 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) 534 { 535 ieee80211_iterate_stations_atomic(rtwdev->hw, 536 rtw89_phy_ra_updata_sta_iter, 537 rtwdev); 538 } 539 540 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) 541 { 542 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 543 struct rtw89_ra_info *ra = &rtwsta->ra; 544 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; 545 bool csi = rtw89_sta_has_beamformer_cap(sta); 546 547 rtw89_phy_ra_sta_update(rtwdev, sta, csi); 548 549 if (rssi > 40) 550 ra->init_rate_lv = 1; 551 else if (rssi > 20) 552 ra->init_rate_lv = 2; 553 else if (rssi > 1) 554 ra->init_rate_lv = 3; 555 else 556 ra->init_rate_lv = 0; 557 ra->upd_all = 1; 558 rtw89_debug(rtwdev, RTW89_DBG_RA, 559 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", 560 ra->macid, 561 ra->mode_ctrl, 562 ra->bw_cap, 563 ra->ss_num, 564 ra->init_rate_lv); 565 rtw89_debug(rtwdev, RTW89_DBG_RA, 566 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", 567 ra->dcm_cap, 568 ra->er_cap, 569 ra->ldpc_cap, 570 ra->stbc_cap, 571 ra->en_sgi, 572 ra->giltf); 573 574 rtw89_fw_h2c_ra(rtwdev, ra, csi); 575 } 576 577 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 578 const struct rtw89_chan *chan, 579 enum rtw89_bandwidth dbw) 580 { 581 enum rtw89_bandwidth cbw = chan->band_width; 582 u8 pri_ch = chan->primary_channel; 583 u8 central_ch = chan->channel; 584 u8 txsc_idx = 0; 585 u8 tmp = 0; 586 587 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 588 return txsc_idx; 589 590 switch (cbw) { 591 case RTW89_CHANNEL_WIDTH_40: 592 txsc_idx = pri_ch > central_ch ? 1 : 2; 593 break; 594 case RTW89_CHANNEL_WIDTH_80: 595 if (dbw == RTW89_CHANNEL_WIDTH_20) { 596 if (pri_ch > central_ch) 597 txsc_idx = (pri_ch - central_ch) >> 1; 598 else 599 txsc_idx = ((central_ch - pri_ch) >> 1) + 1; 600 } else { 601 txsc_idx = pri_ch > central_ch ? 9 : 10; 602 } 603 break; 604 case RTW89_CHANNEL_WIDTH_160: 605 if (pri_ch > central_ch) 606 tmp = (pri_ch - central_ch) >> 1; 607 else 608 tmp = ((central_ch - pri_ch) >> 1) + 1; 609 610 if (dbw == RTW89_CHANNEL_WIDTH_20) { 611 txsc_idx = tmp; 612 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 613 if (tmp == 1 || tmp == 3) 614 txsc_idx = 9; 615 else if (tmp == 5 || tmp == 7) 616 txsc_idx = 11; 617 else if (tmp == 2 || tmp == 4) 618 txsc_idx = 10; 619 else if (tmp == 6 || tmp == 8) 620 txsc_idx = 12; 621 else 622 return 0xff; 623 } else { 624 txsc_idx = pri_ch > central_ch ? 13 : 14; 625 } 626 break; 627 case RTW89_CHANNEL_WIDTH_80_80: 628 if (dbw == RTW89_CHANNEL_WIDTH_20) { 629 if (pri_ch > central_ch) 630 txsc_idx = (10 - (pri_ch - central_ch)) >> 1; 631 else 632 txsc_idx = ((central_ch - pri_ch) >> 1) + 5; 633 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 634 txsc_idx = pri_ch > central_ch ? 10 : 12; 635 } else { 636 txsc_idx = 14; 637 } 638 break; 639 default: 640 break; 641 } 642 643 return txsc_idx; 644 } 645 EXPORT_SYMBOL(rtw89_phy_get_txsc); 646 647 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev) 648 { 649 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) || 650 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1); 651 } 652 653 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 654 u32 addr, u32 mask) 655 { 656 const struct rtw89_chip_info *chip = rtwdev->chip; 657 const u32 *base_addr = chip->rf_base_addr; 658 u32 val, direct_addr; 659 660 if (rf_path >= rtwdev->chip->rf_path_num) { 661 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 662 return INV_RF_DATA; 663 } 664 665 addr &= 0xff; 666 direct_addr = base_addr[rf_path] + (addr << 2); 667 mask &= RFREG_MASK; 668 669 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); 670 671 return val; 672 } 673 EXPORT_SYMBOL(rtw89_phy_read_rf); 674 675 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev, 676 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 677 { 678 bool busy; 679 bool done; 680 u32 val; 681 int ret; 682 683 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 684 1, 30, false, rtwdev); 685 if (ret) { 686 rtw89_err(rtwdev, "read rf busy swsi\n"); 687 return INV_RF_DATA; 688 } 689 690 mask &= RFREG_MASK; 691 692 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) | 693 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr); 694 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val); 695 udelay(2); 696 697 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1, 698 30, false, rtwdev, R_SWSI_V1, 699 B_SWSI_R_DATA_DONE_V1); 700 if (ret) { 701 rtw89_err(rtwdev, "read swsi busy\n"); 702 return INV_RF_DATA; 703 } 704 705 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask); 706 } 707 708 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 709 u32 addr, u32 mask) 710 { 711 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 712 713 if (rf_path >= rtwdev->chip->rf_path_num) { 714 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 715 return INV_RF_DATA; 716 } 717 718 if (ad_sel) 719 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 720 else 721 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask); 722 } 723 EXPORT_SYMBOL(rtw89_phy_read_rf_v1); 724 725 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 726 u32 addr, u32 mask, u32 data) 727 { 728 const struct rtw89_chip_info *chip = rtwdev->chip; 729 const u32 *base_addr = chip->rf_base_addr; 730 u32 direct_addr; 731 732 if (rf_path >= rtwdev->chip->rf_path_num) { 733 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 734 return false; 735 } 736 737 addr &= 0xff; 738 direct_addr = base_addr[rf_path] + (addr << 2); 739 mask &= RFREG_MASK; 740 741 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); 742 743 /* delay to ensure writing properly */ 744 udelay(1); 745 746 return true; 747 } 748 EXPORT_SYMBOL(rtw89_phy_write_rf); 749 750 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev, 751 enum rtw89_rf_path rf_path, u32 addr, u32 mask, 752 u32 data) 753 { 754 u8 bit_shift; 755 u32 val; 756 bool busy, b_msk_en = false; 757 int ret; 758 759 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 760 1, 30, false, rtwdev); 761 if (ret) { 762 rtw89_err(rtwdev, "write rf busy swsi\n"); 763 return false; 764 } 765 766 data &= RFREG_MASK; 767 mask &= RFREG_MASK; 768 769 if (mask != RFREG_MASK) { 770 b_msk_en = true; 771 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK, 772 mask); 773 bit_shift = __ffs(mask); 774 data = (data << bit_shift) & RFREG_MASK; 775 } 776 777 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) | 778 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) | 779 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) | 780 FIELD_PREP(B_SWSI_DATA_VAL_V1, data); 781 782 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val); 783 784 return true; 785 } 786 787 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 788 u32 addr, u32 mask, u32 data) 789 { 790 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 791 792 if (rf_path >= rtwdev->chip->rf_path_num) { 793 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 794 return false; 795 } 796 797 if (ad_sel) 798 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 799 else 800 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data); 801 } 802 EXPORT_SYMBOL(rtw89_phy_write_rf_v1); 803 804 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, 805 enum rtw89_phy_idx phy_idx) 806 { 807 const struct rtw89_chip_info *chip = rtwdev->chip; 808 809 chip->ops->bb_reset(rtwdev, phy_idx); 810 } 811 812 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, 813 const struct rtw89_reg2_def *reg, 814 enum rtw89_rf_path rf_path, 815 void *extra_data) 816 { 817 if (reg->addr == 0xfe) 818 mdelay(50); 819 else if (reg->addr == 0xfd) 820 mdelay(5); 821 else if (reg->addr == 0xfc) 822 mdelay(1); 823 else if (reg->addr == 0xfb) 824 udelay(50); 825 else if (reg->addr == 0xfa) 826 udelay(5); 827 else if (reg->addr == 0xf9) 828 udelay(1); 829 else 830 rtw89_phy_write32(rtwdev, reg->addr, reg->data); 831 } 832 833 union rtw89_phy_bb_gain_arg { 834 u32 addr; 835 struct { 836 union { 837 u8 type; 838 struct { 839 u8 rxsc_start:4; 840 u8 bw:4; 841 }; 842 }; 843 u8 path; 844 u8 gain_band; 845 u8 cfg_type; 846 }; 847 } __packed; 848 849 static void 850 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev, 851 union rtw89_phy_bb_gain_arg arg, u32 data) 852 { 853 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 854 u8 type = arg.type; 855 u8 path = arg.path; 856 u8 gband = arg.gain_band; 857 int i; 858 859 switch (type) { 860 case 0: 861 for (i = 0; i < 4; i++, data >>= 8) 862 gain->lna_gain[gband][path][i] = data & 0xff; 863 break; 864 case 1: 865 for (i = 4; i < 7; i++, data >>= 8) 866 gain->lna_gain[gband][path][i] = data & 0xff; 867 break; 868 case 2: 869 for (i = 0; i < 2; i++, data >>= 8) 870 gain->tia_gain[gband][path][i] = data & 0xff; 871 break; 872 default: 873 rtw89_warn(rtwdev, 874 "bb gain error {0x%x:0x%x} with unknown type: %d\n", 875 arg.addr, data, type); 876 break; 877 } 878 } 879 880 enum rtw89_phy_bb_rxsc_start_idx { 881 RTW89_BB_RXSC_START_IDX_FULL = 0, 882 RTW89_BB_RXSC_START_IDX_20 = 1, 883 RTW89_BB_RXSC_START_IDX_20_1 = 5, 884 RTW89_BB_RXSC_START_IDX_40 = 9, 885 RTW89_BB_RXSC_START_IDX_80 = 13, 886 }; 887 888 static void 889 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev, 890 union rtw89_phy_bb_gain_arg arg, u32 data) 891 { 892 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 893 u8 rxsc_start = arg.rxsc_start; 894 u8 bw = arg.bw; 895 u8 path = arg.path; 896 u8 gband = arg.gain_band; 897 u8 rxsc; 898 s8 ofst; 899 int i; 900 901 switch (bw) { 902 case RTW89_CHANNEL_WIDTH_20: 903 gain->rpl_ofst_20[gband][path] = (s8)data; 904 break; 905 case RTW89_CHANNEL_WIDTH_40: 906 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 907 gain->rpl_ofst_40[gband][path][0] = (s8)data; 908 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 909 for (i = 0; i < 2; i++, data >>= 8) { 910 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 911 ofst = (s8)(data & 0xff); 912 gain->rpl_ofst_40[gband][path][rxsc] = ofst; 913 } 914 } 915 break; 916 case RTW89_CHANNEL_WIDTH_80: 917 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 918 gain->rpl_ofst_80[gband][path][0] = (s8)data; 919 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 920 for (i = 0; i < 4; i++, data >>= 8) { 921 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 922 ofst = (s8)(data & 0xff); 923 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 924 } 925 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 926 for (i = 0; i < 2; i++, data >>= 8) { 927 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 928 ofst = (s8)(data & 0xff); 929 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 930 } 931 } 932 break; 933 case RTW89_CHANNEL_WIDTH_160: 934 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 935 gain->rpl_ofst_160[gband][path][0] = (s8)data; 936 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 937 for (i = 0; i < 4; i++, data >>= 8) { 938 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 939 ofst = (s8)(data & 0xff); 940 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 941 } 942 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) { 943 for (i = 0; i < 4; i++, data >>= 8) { 944 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i; 945 ofst = (s8)(data & 0xff); 946 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 947 } 948 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 949 for (i = 0; i < 4; i++, data >>= 8) { 950 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 951 ofst = (s8)(data & 0xff); 952 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 953 } 954 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) { 955 for (i = 0; i < 2; i++, data >>= 8) { 956 rxsc = RTW89_BB_RXSC_START_IDX_80 + i; 957 ofst = (s8)(data & 0xff); 958 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 959 } 960 } 961 break; 962 default: 963 rtw89_warn(rtwdev, 964 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n", 965 arg.addr, data, bw); 966 break; 967 } 968 } 969 970 static void 971 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev, 972 union rtw89_phy_bb_gain_arg arg, u32 data) 973 { 974 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 975 u8 type = arg.type; 976 u8 path = arg.path; 977 u8 gband = arg.gain_band; 978 int i; 979 980 switch (type) { 981 case 0: 982 for (i = 0; i < 4; i++, data >>= 8) 983 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 984 break; 985 case 1: 986 for (i = 4; i < 7; i++, data >>= 8) 987 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 988 break; 989 default: 990 rtw89_warn(rtwdev, 991 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n", 992 arg.addr, data, type); 993 break; 994 } 995 } 996 997 static void 998 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev, 999 union rtw89_phy_bb_gain_arg arg, u32 data) 1000 { 1001 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 1002 u8 type = arg.type; 1003 u8 path = arg.path; 1004 u8 gband = arg.gain_band; 1005 int i; 1006 1007 switch (type) { 1008 case 0: 1009 for (i = 0; i < 4; i++, data >>= 8) 1010 gain->lna_op1db[gband][path][i] = data & 0xff; 1011 break; 1012 case 1: 1013 for (i = 4; i < 7; i++, data >>= 8) 1014 gain->lna_op1db[gband][path][i] = data & 0xff; 1015 break; 1016 case 2: 1017 for (i = 0; i < 4; i++, data >>= 8) 1018 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1019 break; 1020 case 3: 1021 for (i = 4; i < 8; i++, data >>= 8) 1022 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1023 break; 1024 default: 1025 rtw89_warn(rtwdev, 1026 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n", 1027 arg.addr, data, type); 1028 break; 1029 } 1030 } 1031 1032 static void rtw89_phy_config_bb_gain(struct rtw89_dev *rtwdev, 1033 const struct rtw89_reg2_def *reg, 1034 enum rtw89_rf_path rf_path, 1035 void *extra_data) 1036 { 1037 const struct rtw89_chip_info *chip = rtwdev->chip; 1038 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr }; 1039 1040 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR) 1041 return; 1042 1043 if (arg.path >= chip->rf_path_num) 1044 return; 1045 1046 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) { 1047 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n"); 1048 return; 1049 } 1050 1051 switch (arg.cfg_type) { 1052 case 0: 1053 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data); 1054 break; 1055 case 1: 1056 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data); 1057 break; 1058 case 2: 1059 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data); 1060 break; 1061 case 3: 1062 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data); 1063 break; 1064 default: 1065 rtw89_warn(rtwdev, 1066 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n", 1067 arg.addr, reg->data, arg.cfg_type); 1068 break; 1069 } 1070 } 1071 1072 static void 1073 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, 1074 const struct rtw89_reg2_def *reg, 1075 enum rtw89_rf_path rf_path, 1076 struct rtw89_fw_h2c_rf_reg_info *info) 1077 { 1078 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; 1079 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 1080 1081 if (page >= RTW89_H2C_RF_PAGE_NUM) { 1082 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d", 1083 rf_path, info->curr_idx); 1084 return; 1085 } 1086 1087 info->rtw89_phy_config_rf_h2c[page][idx] = 1088 cpu_to_le32((reg->addr << 20) | reg->data); 1089 info->curr_idx++; 1090 } 1091 1092 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, 1093 struct rtw89_fw_h2c_rf_reg_info *info) 1094 { 1095 u16 remain = info->curr_idx; 1096 u16 len = 0; 1097 u8 i; 1098 int ret = 0; 1099 1100 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) { 1101 rtw89_warn(rtwdev, 1102 "rf reg h2c total len %d larger than %d\n", 1103 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE); 1104 ret = -EINVAL; 1105 goto out; 1106 } 1107 1108 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) { 1109 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain; 1110 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i); 1111 if (ret) 1112 goto out; 1113 } 1114 out: 1115 info->curr_idx = 0; 1116 1117 return ret; 1118 } 1119 1120 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, 1121 const struct rtw89_reg2_def *reg, 1122 enum rtw89_rf_path rf_path, 1123 void *extra_data) 1124 { 1125 if (reg->addr == 0xfe) { 1126 mdelay(50); 1127 } else if (reg->addr == 0xfd) { 1128 mdelay(5); 1129 } else if (reg->addr == 0xfc) { 1130 mdelay(1); 1131 } else if (reg->addr == 0xfb) { 1132 udelay(50); 1133 } else if (reg->addr == 0xfa) { 1134 udelay(5); 1135 } else if (reg->addr == 0xf9) { 1136 udelay(1); 1137 } else { 1138 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); 1139 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1140 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1141 } 1142 } 1143 1144 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 1145 const struct rtw89_reg2_def *reg, 1146 enum rtw89_rf_path rf_path, 1147 void *extra_data) 1148 { 1149 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data); 1150 1151 if (reg->addr < 0x100) 1152 return; 1153 1154 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1155 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1156 } 1157 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1); 1158 1159 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, 1160 const struct rtw89_phy_table *table, 1161 u32 *headline_size, u32 *headline_idx, 1162 u8 rfe, u8 cv) 1163 { 1164 const struct rtw89_reg2_def *reg; 1165 u32 headline; 1166 u32 compare, target; 1167 u8 rfe_para, cv_para; 1168 u8 cv_max = 0; 1169 bool case_matched = false; 1170 u32 i; 1171 1172 for (i = 0; i < table->n_regs; i++) { 1173 reg = &table->regs[i]; 1174 headline = get_phy_headline(reg->addr); 1175 if (headline != PHY_HEADLINE_VALID) 1176 break; 1177 } 1178 *headline_size = i; 1179 if (*headline_size == 0) 1180 return 0; 1181 1182 /* case 1: RFE match, CV match */ 1183 compare = get_phy_compare(rfe, cv); 1184 for (i = 0; i < *headline_size; i++) { 1185 reg = &table->regs[i]; 1186 target = get_phy_target(reg->addr); 1187 if (target == compare) { 1188 *headline_idx = i; 1189 return 0; 1190 } 1191 } 1192 1193 /* case 2: RFE match, CV don't care */ 1194 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); 1195 for (i = 0; i < *headline_size; i++) { 1196 reg = &table->regs[i]; 1197 target = get_phy_target(reg->addr); 1198 if (target == compare) { 1199 *headline_idx = i; 1200 return 0; 1201 } 1202 } 1203 1204 /* case 3: RFE match, CV max in table */ 1205 for (i = 0; i < *headline_size; i++) { 1206 reg = &table->regs[i]; 1207 rfe_para = get_phy_cond_rfe(reg->addr); 1208 cv_para = get_phy_cond_cv(reg->addr); 1209 if (rfe_para == rfe) { 1210 if (cv_para >= cv_max) { 1211 cv_max = cv_para; 1212 *headline_idx = i; 1213 case_matched = true; 1214 } 1215 } 1216 } 1217 1218 if (case_matched) 1219 return 0; 1220 1221 /* case 4: RFE don't care, CV max in table */ 1222 for (i = 0; i < *headline_size; i++) { 1223 reg = &table->regs[i]; 1224 rfe_para = get_phy_cond_rfe(reg->addr); 1225 cv_para = get_phy_cond_cv(reg->addr); 1226 if (rfe_para == PHY_COND_DONT_CARE) { 1227 if (cv_para >= cv_max) { 1228 cv_max = cv_para; 1229 *headline_idx = i; 1230 case_matched = true; 1231 } 1232 } 1233 } 1234 1235 if (case_matched) 1236 return 0; 1237 1238 return -EINVAL; 1239 } 1240 1241 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, 1242 const struct rtw89_phy_table *table, 1243 void (*config)(struct rtw89_dev *rtwdev, 1244 const struct rtw89_reg2_def *reg, 1245 enum rtw89_rf_path rf_path, 1246 void *data), 1247 void *extra_data) 1248 { 1249 const struct rtw89_reg2_def *reg; 1250 enum rtw89_rf_path rf_path = table->rf_path; 1251 u8 rfe = rtwdev->efuse.rfe_type; 1252 u8 cv = rtwdev->hal.cv; 1253 u32 i; 1254 u32 headline_size = 0, headline_idx = 0; 1255 u32 target = 0, cfg_target; 1256 u8 cond; 1257 bool is_matched = true; 1258 bool target_found = false; 1259 int ret; 1260 1261 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, 1262 &headline_idx, rfe, cv); 1263 if (ret) { 1264 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); 1265 return; 1266 } 1267 1268 cfg_target = get_phy_target(table->regs[headline_idx].addr); 1269 for (i = headline_size; i < table->n_regs; i++) { 1270 reg = &table->regs[i]; 1271 cond = get_phy_cond(reg->addr); 1272 switch (cond) { 1273 case PHY_COND_BRANCH_IF: 1274 case PHY_COND_BRANCH_ELIF: 1275 target = get_phy_target(reg->addr); 1276 break; 1277 case PHY_COND_BRANCH_ELSE: 1278 is_matched = false; 1279 if (!target_found) { 1280 rtw89_warn(rtwdev, "failed to load CR %x/%x\n", 1281 reg->addr, reg->data); 1282 return; 1283 } 1284 break; 1285 case PHY_COND_BRANCH_END: 1286 is_matched = true; 1287 target_found = false; 1288 break; 1289 case PHY_COND_CHECK: 1290 if (target_found) { 1291 is_matched = false; 1292 break; 1293 } 1294 1295 if (target == cfg_target) { 1296 is_matched = true; 1297 target_found = true; 1298 } else { 1299 is_matched = false; 1300 target_found = false; 1301 } 1302 break; 1303 default: 1304 if (is_matched) 1305 config(rtwdev, reg, rf_path, extra_data); 1306 break; 1307 } 1308 } 1309 } 1310 1311 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) 1312 { 1313 const struct rtw89_chip_info *chip = rtwdev->chip; 1314 const struct rtw89_phy_table *bb_table = chip->bb_table; 1315 const struct rtw89_phy_table *bb_gain_table = chip->bb_gain_table; 1316 1317 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); 1318 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 1319 if (bb_gain_table) 1320 rtw89_phy_init_reg(rtwdev, bb_gain_table, 1321 rtw89_phy_config_bb_gain, NULL); 1322 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); 1323 } 1324 1325 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 1326 { 1327 rtw89_phy_write32(rtwdev, 0x8080, 0x4); 1328 udelay(1); 1329 return rtw89_phy_read32(rtwdev, 0x8080); 1330 } 1331 1332 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev) 1333 { 1334 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 1335 enum rtw89_rf_path rf_path, void *data); 1336 const struct rtw89_chip_info *chip = rtwdev->chip; 1337 const struct rtw89_phy_table *rf_table; 1338 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; 1339 u8 path; 1340 1341 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); 1342 if (!rf_reg_info) 1343 return; 1344 1345 for (path = RF_PATH_A; path < chip->rf_path_num; path++) { 1346 rf_table = chip->rf_table[path]; 1347 rf_reg_info->rf_path = rf_table->rf_path; 1348 config = rf_table->config ? rf_table->config : rtw89_phy_config_rf_reg; 1349 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info); 1350 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) 1351 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", 1352 rf_reg_info->rf_path); 1353 } 1354 kfree(rf_reg_info); 1355 } 1356 1357 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) 1358 { 1359 const struct rtw89_chip_info *chip = rtwdev->chip; 1360 const struct rtw89_phy_table *nctl_table; 1361 u32 val; 1362 int ret; 1363 1364 /* IQK/DPK clock & reset */ 1365 rtw89_phy_write32_set(rtwdev, 0x0c60, 0x3); 1366 rtw89_phy_write32_set(rtwdev, 0x0c6c, 0x1); 1367 rtw89_phy_write32_set(rtwdev, 0x58ac, 0x8000000); 1368 rtw89_phy_write32_set(rtwdev, 0x78ac, 0x8000000); 1369 1370 /* check 0x8080 */ 1371 rtw89_phy_write32(rtwdev, 0x8000, 0x8); 1372 1373 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, 1374 1000, false, rtwdev); 1375 if (ret) 1376 rtw89_err(rtwdev, "failed to poll nctl block\n"); 1377 1378 nctl_table = chip->nctl_table; 1379 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); 1380 } 1381 1382 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) 1383 { 1384 u32 phy_page = addr >> 8; 1385 u32 ofst = 0; 1386 1387 switch (phy_page) { 1388 case 0x6: 1389 case 0x7: 1390 case 0x8: 1391 case 0x9: 1392 case 0xa: 1393 case 0xb: 1394 case 0xc: 1395 case 0xd: 1396 case 0x19: 1397 case 0x1a: 1398 case 0x1b: 1399 ofst = 0x2000; 1400 break; 1401 default: 1402 /* warning case */ 1403 ofst = 0; 1404 break; 1405 } 1406 1407 if (phy_page >= 0x40 && phy_page <= 0x4f) 1408 ofst = 0x2000; 1409 1410 return ofst; 1411 } 1412 1413 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1414 u32 data, enum rtw89_phy_idx phy_idx) 1415 { 1416 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1417 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1418 rtw89_phy_write32_mask(rtwdev, addr, mask, data); 1419 } 1420 EXPORT_SYMBOL(rtw89_phy_write32_idx); 1421 1422 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1423 u32 val) 1424 { 1425 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 1426 1427 if (!rtwdev->dbcc_en) 1428 return; 1429 1430 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 1431 } 1432 1433 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 1434 const struct rtw89_phy_reg3_tbl *tbl) 1435 { 1436 const struct rtw89_reg3_def *reg3; 1437 int i; 1438 1439 for (i = 0; i < tbl->size; i++) { 1440 reg3 = &tbl->reg3[i]; 1441 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); 1442 } 1443 } 1444 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl); 1445 1446 const u8 rtw89_rs_idx_max[] = { 1447 [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX, 1448 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX, 1449 [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX, 1450 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX, 1451 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX, 1452 }; 1453 EXPORT_SYMBOL(rtw89_rs_idx_max); 1454 1455 const u8 rtw89_rs_nss_max[] = { 1456 [RTW89_RS_CCK] = 1, 1457 [RTW89_RS_OFDM] = 1, 1458 [RTW89_RS_MCS] = RTW89_NSS_MAX, 1459 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX, 1460 [RTW89_RS_OFFSET] = 1, 1461 }; 1462 EXPORT_SYMBOL(rtw89_rs_nss_max); 1463 1464 static const u8 _byr_of_rs[] = { 1465 [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck), 1466 [RTW89_RS_OFDM] = offsetof(struct rtw89_txpwr_byrate, ofdm), 1467 [RTW89_RS_MCS] = offsetof(struct rtw89_txpwr_byrate, mcs), 1468 [RTW89_RS_HEDCM] = offsetof(struct rtw89_txpwr_byrate, hedcm), 1469 [RTW89_RS_OFFSET] = offsetof(struct rtw89_txpwr_byrate, offset), 1470 }; 1471 1472 #define _byr_seek(rs, raw) ((s8 *)(raw) + _byr_of_rs[rs]) 1473 #define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_max[rs] + (idx)) 1474 #define _byr_chk(rs, nss, idx) \ 1475 ((nss) < rtw89_rs_nss_max[rs] && (idx) < rtw89_rs_idx_max[rs]) 1476 1477 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 1478 const struct rtw89_txpwr_table *tbl) 1479 { 1480 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; 1481 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; 1482 s8 *byr; 1483 u32 data; 1484 u8 i, idx; 1485 1486 for (; cfg < end; cfg++) { 1487 byr = _byr_seek(cfg->rs, &rtwdev->byr[cfg->band]); 1488 data = cfg->data; 1489 1490 for (i = 0; i < cfg->len; i++, data >>= 8) { 1491 idx = _byr_idx(cfg->rs, cfg->nss, (cfg->shf + i)); 1492 byr[idx] = (s8)(data & 0xff); 1493 } 1494 } 1495 } 1496 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate); 1497 1498 #define _phy_txpwr_rf_to_mac(rtwdev, txpwr_rf) \ 1499 ({ \ 1500 const struct rtw89_chip_info *__c = (rtwdev)->chip; \ 1501 (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \ 1502 }) 1503 1504 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, 1505 const struct rtw89_rate_desc *rate_desc) 1506 { 1507 s8 *byr; 1508 u8 idx; 1509 1510 if (rate_desc->rs == RTW89_RS_CCK) 1511 band = RTW89_BAND_2G; 1512 1513 if (!_byr_chk(rate_desc->rs, rate_desc->nss, rate_desc->idx)) { 1514 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1515 "[TXPWR] unknown byrate desc rs=%d nss=%d idx=%d\n", 1516 rate_desc->rs, rate_desc->nss, rate_desc->idx); 1517 1518 return 0; 1519 } 1520 1521 byr = _byr_seek(rate_desc->rs, &rtwdev->byr[band]); 1522 idx = _byr_idx(rate_desc->rs, rate_desc->nss, rate_desc->idx); 1523 1524 return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]); 1525 } 1526 EXPORT_SYMBOL(rtw89_phy_read_txpwr_byrate); 1527 1528 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g) 1529 { 1530 switch (channel_6g) { 1531 case 1 ... 29: 1532 return (channel_6g - 1) / 2; 1533 case 33 ... 61: 1534 return (channel_6g - 3) / 2; 1535 case 65 ... 93: 1536 return (channel_6g - 5) / 2; 1537 case 97 ... 125: 1538 return (channel_6g - 7) / 2; 1539 case 129 ... 157: 1540 return (channel_6g - 9) / 2; 1541 case 161 ... 189: 1542 return (channel_6g - 11) / 2; 1543 case 193 ... 221: 1544 return (channel_6g - 13) / 2; 1545 case 225 ... 253: 1546 return (channel_6g - 15) / 2; 1547 default: 1548 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g); 1549 return 0; 1550 } 1551 } 1552 1553 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel) 1554 { 1555 if (band == RTW89_BAND_6G) 1556 return rtw89_channel_6g_to_idx(rtwdev, channel); 1557 1558 switch (channel) { 1559 case 1 ... 14: 1560 return channel - 1; 1561 case 36 ... 64: 1562 return (channel - 36) / 2; 1563 case 100 ... 144: 1564 return ((channel - 100) / 2) + 15; 1565 case 149 ... 177: 1566 return ((channel - 149) / 2) + 38; 1567 default: 1568 rtw89_warn(rtwdev, "unknown channel: %d\n", channel); 1569 return 0; 1570 } 1571 } 1572 1573 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 1574 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) 1575 { 1576 const struct rtw89_chip_info *chip = rtwdev->chip; 1577 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1578 u8 regd = rtw89_regd_get(rtwdev, band); 1579 s8 lmt = 0, sar; 1580 1581 switch (band) { 1582 case RTW89_BAND_2G: 1583 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf][regd][ch_idx]; 1584 if (!lmt) 1585 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf] 1586 [RTW89_WW][ch_idx]; 1587 break; 1588 case RTW89_BAND_5G: 1589 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf][regd][ch_idx]; 1590 if (!lmt) 1591 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf] 1592 [RTW89_WW][ch_idx]; 1593 break; 1594 case RTW89_BAND_6G: 1595 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf][regd][ch_idx]; 1596 if (!lmt) 1597 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf] 1598 [RTW89_WW][ch_idx]; 1599 break; 1600 default: 1601 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1602 return 0; 1603 } 1604 1605 lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt); 1606 sar = rtw89_query_sar(rtwdev); 1607 1608 return min(lmt, sar); 1609 } 1610 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit); 1611 1612 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \ 1613 do { \ 1614 u8 __i; \ 1615 for (__i = 0; __i < RTW89_BF_NUM; __i++) \ 1616 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ 1617 band, \ 1618 bw, ntx, \ 1619 rs, __i, \ 1620 (ch)); \ 1621 } while (0) 1622 1623 static void rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev *rtwdev, 1624 struct rtw89_txpwr_limit *lmt, 1625 u8 band, u8 ntx, u8 ch) 1626 { 1627 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1628 ntx, RTW89_RS_CCK, ch); 1629 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1630 ntx, RTW89_RS_CCK, ch); 1631 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1632 ntx, RTW89_RS_OFDM, ch); 1633 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1634 RTW89_CHANNEL_WIDTH_20, 1635 ntx, RTW89_RS_MCS, ch); 1636 } 1637 1638 static void rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev *rtwdev, 1639 struct rtw89_txpwr_limit *lmt, 1640 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1641 { 1642 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1643 ntx, RTW89_RS_CCK, ch - 2); 1644 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1645 ntx, RTW89_RS_CCK, ch); 1646 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1647 ntx, RTW89_RS_OFDM, pri_ch); 1648 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1649 RTW89_CHANNEL_WIDTH_20, 1650 ntx, RTW89_RS_MCS, ch - 2); 1651 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1652 RTW89_CHANNEL_WIDTH_20, 1653 ntx, RTW89_RS_MCS, ch + 2); 1654 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1655 RTW89_CHANNEL_WIDTH_40, 1656 ntx, RTW89_RS_MCS, ch); 1657 } 1658 1659 static void rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev *rtwdev, 1660 struct rtw89_txpwr_limit *lmt, 1661 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1662 { 1663 s8 val_0p5_n[RTW89_BF_NUM]; 1664 s8 val_0p5_p[RTW89_BF_NUM]; 1665 u8 i; 1666 1667 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1668 ntx, RTW89_RS_OFDM, pri_ch); 1669 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1670 RTW89_CHANNEL_WIDTH_20, 1671 ntx, RTW89_RS_MCS, ch - 6); 1672 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1673 RTW89_CHANNEL_WIDTH_20, 1674 ntx, RTW89_RS_MCS, ch - 2); 1675 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1676 RTW89_CHANNEL_WIDTH_20, 1677 ntx, RTW89_RS_MCS, ch + 2); 1678 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1679 RTW89_CHANNEL_WIDTH_20, 1680 ntx, RTW89_RS_MCS, ch + 6); 1681 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1682 RTW89_CHANNEL_WIDTH_40, 1683 ntx, RTW89_RS_MCS, ch - 4); 1684 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1685 RTW89_CHANNEL_WIDTH_40, 1686 ntx, RTW89_RS_MCS, ch + 4); 1687 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1688 RTW89_CHANNEL_WIDTH_80, 1689 ntx, RTW89_RS_MCS, ch); 1690 1691 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1692 ntx, RTW89_RS_MCS, ch - 4); 1693 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1694 ntx, RTW89_RS_MCS, ch + 4); 1695 1696 for (i = 0; i < RTW89_BF_NUM; i++) 1697 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1698 } 1699 1700 static void rtw89_phy_fill_txpwr_limit_160m(struct rtw89_dev *rtwdev, 1701 struct rtw89_txpwr_limit *lmt, 1702 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1703 { 1704 s8 val_0p5_n[RTW89_BF_NUM]; 1705 s8 val_0p5_p[RTW89_BF_NUM]; 1706 s8 val_2p5_n[RTW89_BF_NUM]; 1707 s8 val_2p5_p[RTW89_BF_NUM]; 1708 u8 i; 1709 1710 /* fill ofdm section */ 1711 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1712 ntx, RTW89_RS_OFDM, pri_ch); 1713 1714 /* fill mcs 20m section */ 1715 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1716 RTW89_CHANNEL_WIDTH_20, 1717 ntx, RTW89_RS_MCS, ch - 14); 1718 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1719 RTW89_CHANNEL_WIDTH_20, 1720 ntx, RTW89_RS_MCS, ch - 10); 1721 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1722 RTW89_CHANNEL_WIDTH_20, 1723 ntx, RTW89_RS_MCS, ch - 6); 1724 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1725 RTW89_CHANNEL_WIDTH_20, 1726 ntx, RTW89_RS_MCS, ch - 2); 1727 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band, 1728 RTW89_CHANNEL_WIDTH_20, 1729 ntx, RTW89_RS_MCS, ch + 2); 1730 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band, 1731 RTW89_CHANNEL_WIDTH_20, 1732 ntx, RTW89_RS_MCS, ch + 6); 1733 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band, 1734 RTW89_CHANNEL_WIDTH_20, 1735 ntx, RTW89_RS_MCS, ch + 10); 1736 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band, 1737 RTW89_CHANNEL_WIDTH_20, 1738 ntx, RTW89_RS_MCS, ch + 14); 1739 1740 /* fill mcs 40m section */ 1741 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1742 RTW89_CHANNEL_WIDTH_40, 1743 ntx, RTW89_RS_MCS, ch - 12); 1744 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1745 RTW89_CHANNEL_WIDTH_40, 1746 ntx, RTW89_RS_MCS, ch - 4); 1747 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band, 1748 RTW89_CHANNEL_WIDTH_40, 1749 ntx, RTW89_RS_MCS, ch + 4); 1750 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band, 1751 RTW89_CHANNEL_WIDTH_40, 1752 ntx, RTW89_RS_MCS, ch + 12); 1753 1754 /* fill mcs 80m section */ 1755 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1756 RTW89_CHANNEL_WIDTH_80, 1757 ntx, RTW89_RS_MCS, ch - 8); 1758 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band, 1759 RTW89_CHANNEL_WIDTH_80, 1760 ntx, RTW89_RS_MCS, ch + 8); 1761 1762 /* fill mcs 160m section */ 1763 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band, 1764 RTW89_CHANNEL_WIDTH_160, 1765 ntx, RTW89_RS_MCS, ch); 1766 1767 /* fill mcs 40m 0p5 section */ 1768 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1769 ntx, RTW89_RS_MCS, ch - 4); 1770 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1771 ntx, RTW89_RS_MCS, ch + 4); 1772 1773 for (i = 0; i < RTW89_BF_NUM; i++) 1774 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1775 1776 /* fill mcs 40m 2p5 section */ 1777 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40, 1778 ntx, RTW89_RS_MCS, ch - 8); 1779 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40, 1780 ntx, RTW89_RS_MCS, ch + 8); 1781 1782 for (i = 0; i < RTW89_BF_NUM; i++) 1783 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]); 1784 } 1785 1786 void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev, 1787 const struct rtw89_chan *chan, 1788 struct rtw89_txpwr_limit *lmt, 1789 u8 ntx) 1790 { 1791 u8 band = chan->band_type; 1792 u8 pri_ch = chan->primary_channel; 1793 u8 ch = chan->channel; 1794 u8 bw = chan->band_width; 1795 1796 memset(lmt, 0, sizeof(*lmt)); 1797 1798 switch (bw) { 1799 case RTW89_CHANNEL_WIDTH_20: 1800 rtw89_phy_fill_txpwr_limit_20m(rtwdev, lmt, band, ntx, ch); 1801 break; 1802 case RTW89_CHANNEL_WIDTH_40: 1803 rtw89_phy_fill_txpwr_limit_40m(rtwdev, lmt, band, ntx, ch, 1804 pri_ch); 1805 break; 1806 case RTW89_CHANNEL_WIDTH_80: 1807 rtw89_phy_fill_txpwr_limit_80m(rtwdev, lmt, band, ntx, ch, 1808 pri_ch); 1809 break; 1810 case RTW89_CHANNEL_WIDTH_160: 1811 rtw89_phy_fill_txpwr_limit_160m(rtwdev, lmt, band, ntx, ch, 1812 pri_ch); 1813 break; 1814 } 1815 } 1816 EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit); 1817 1818 static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 1819 u8 ru, u8 ntx, u8 ch) 1820 { 1821 const struct rtw89_chip_info *chip = rtwdev->chip; 1822 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1823 u8 regd = rtw89_regd_get(rtwdev, band); 1824 s8 lmt_ru = 0, sar; 1825 1826 switch (band) { 1827 case RTW89_BAND_2G: 1828 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx][regd][ch_idx]; 1829 if (!lmt_ru) 1830 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx] 1831 [RTW89_WW][ch_idx]; 1832 break; 1833 case RTW89_BAND_5G: 1834 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx][regd][ch_idx]; 1835 if (!lmt_ru) 1836 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx] 1837 [RTW89_WW][ch_idx]; 1838 break; 1839 case RTW89_BAND_6G: 1840 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx][regd][ch_idx]; 1841 if (!lmt_ru) 1842 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx] 1843 [RTW89_WW][ch_idx]; 1844 break; 1845 default: 1846 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1847 return 0; 1848 } 1849 1850 lmt_ru = _phy_txpwr_rf_to_mac(rtwdev, lmt_ru); 1851 sar = rtw89_query_sar(rtwdev); 1852 1853 return min(lmt_ru, sar); 1854 } 1855 1856 static void 1857 rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev, 1858 struct rtw89_txpwr_limit_ru *lmt_ru, 1859 u8 band, u8 ntx, u8 ch) 1860 { 1861 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1862 RTW89_RU26, 1863 ntx, ch); 1864 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1865 RTW89_RU52, 1866 ntx, ch); 1867 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1868 RTW89_RU106, 1869 ntx, ch); 1870 } 1871 1872 static void 1873 rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev, 1874 struct rtw89_txpwr_limit_ru *lmt_ru, 1875 u8 band, u8 ntx, u8 ch) 1876 { 1877 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1878 RTW89_RU26, 1879 ntx, ch - 2); 1880 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1881 RTW89_RU26, 1882 ntx, ch + 2); 1883 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1884 RTW89_RU52, 1885 ntx, ch - 2); 1886 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1887 RTW89_RU52, 1888 ntx, ch + 2); 1889 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1890 RTW89_RU106, 1891 ntx, ch - 2); 1892 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1893 RTW89_RU106, 1894 ntx, ch + 2); 1895 } 1896 1897 static void 1898 rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev, 1899 struct rtw89_txpwr_limit_ru *lmt_ru, 1900 u8 band, u8 ntx, u8 ch) 1901 { 1902 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1903 RTW89_RU26, 1904 ntx, ch - 6); 1905 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1906 RTW89_RU26, 1907 ntx, ch - 2); 1908 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1909 RTW89_RU26, 1910 ntx, ch + 2); 1911 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1912 RTW89_RU26, 1913 ntx, ch + 6); 1914 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1915 RTW89_RU52, 1916 ntx, ch - 6); 1917 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1918 RTW89_RU52, 1919 ntx, ch - 2); 1920 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1921 RTW89_RU52, 1922 ntx, ch + 2); 1923 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1924 RTW89_RU52, 1925 ntx, ch + 6); 1926 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1927 RTW89_RU106, 1928 ntx, ch - 6); 1929 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1930 RTW89_RU106, 1931 ntx, ch - 2); 1932 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1933 RTW89_RU106, 1934 ntx, ch + 2); 1935 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1936 RTW89_RU106, 1937 ntx, ch + 6); 1938 } 1939 1940 static void 1941 rtw89_phy_fill_txpwr_limit_ru_160m(struct rtw89_dev *rtwdev, 1942 struct rtw89_txpwr_limit_ru *lmt_ru, 1943 u8 band, u8 ntx, u8 ch) 1944 { 1945 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 }; 1946 int i; 1947 1948 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM); 1949 for (i = 0; i < RTW89_RU_SEC_NUM; i++) { 1950 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1951 RTW89_RU26, 1952 ntx, 1953 ch + ofst[i]); 1954 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1955 RTW89_RU52, 1956 ntx, 1957 ch + ofst[i]); 1958 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1959 RTW89_RU106, 1960 ntx, 1961 ch + ofst[i]); 1962 } 1963 } 1964 1965 void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, 1966 const struct rtw89_chan *chan, 1967 struct rtw89_txpwr_limit_ru *lmt_ru, 1968 u8 ntx) 1969 { 1970 u8 band = chan->band_type; 1971 u8 ch = chan->channel; 1972 u8 bw = chan->band_width; 1973 1974 memset(lmt_ru, 0, sizeof(*lmt_ru)); 1975 1976 switch (bw) { 1977 case RTW89_CHANNEL_WIDTH_20: 1978 rtw89_phy_fill_txpwr_limit_ru_20m(rtwdev, lmt_ru, band, ntx, 1979 ch); 1980 break; 1981 case RTW89_CHANNEL_WIDTH_40: 1982 rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, band, ntx, 1983 ch); 1984 break; 1985 case RTW89_CHANNEL_WIDTH_80: 1986 rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, band, ntx, 1987 ch); 1988 break; 1989 case RTW89_CHANNEL_WIDTH_160: 1990 rtw89_phy_fill_txpwr_limit_ru_160m(rtwdev, lmt_ru, band, ntx, 1991 ch); 1992 break; 1993 } 1994 } 1995 EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit_ru); 1996 1997 struct rtw89_phy_iter_ra_data { 1998 struct rtw89_dev *rtwdev; 1999 struct sk_buff *c2h; 2000 }; 2001 2002 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) 2003 { 2004 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; 2005 struct rtw89_dev *rtwdev = ra_data->rtwdev; 2006 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2007 struct rtw89_ra_report *ra_report = &rtwsta->ra_report; 2008 struct sk_buff *c2h = ra_data->c2h; 2009 u8 mode, rate, bw, giltf, mac_id; 2010 u16 legacy_bitrate; 2011 bool valid; 2012 u8 mcs = 0; 2013 2014 mac_id = RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h->data); 2015 if (mac_id != rtwsta->mac_id) 2016 return; 2017 2018 rate = RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h->data); 2019 bw = RTW89_GET_PHY_C2H_RA_RPT_BW(c2h->data); 2020 giltf = RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h->data); 2021 mode = RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h->data); 2022 2023 if (mode == RTW89_RA_RPT_MODE_LEGACY) { 2024 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate); 2025 if (!valid) 2026 return; 2027 } 2028 2029 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate)); 2030 2031 switch (mode) { 2032 case RTW89_RA_RPT_MODE_LEGACY: 2033 ra_report->txrate.legacy = legacy_bitrate; 2034 break; 2035 case RTW89_RA_RPT_MODE_HT: 2036 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; 2037 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw)) 2038 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), 2039 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); 2040 else 2041 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); 2042 ra_report->txrate.mcs = rate; 2043 if (giltf) 2044 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2045 mcs = ra_report->txrate.mcs & 0x07; 2046 break; 2047 case RTW89_RA_RPT_MODE_VHT: 2048 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; 2049 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 2050 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 2051 if (giltf) 2052 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2053 mcs = ra_report->txrate.mcs; 2054 break; 2055 case RTW89_RA_RPT_MODE_HE: 2056 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; 2057 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 2058 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 2059 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2060 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; 2061 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2062 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; 2063 else 2064 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; 2065 mcs = ra_report->txrate.mcs; 2066 break; 2067 } 2068 2069 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw); 2070 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); 2071 ra_report->hw_rate = FIELD_PREP(RTW89_HW_RATE_MASK_MOD, mode) | 2072 FIELD_PREP(RTW89_HW_RATE_MASK_VAL, rate); 2073 ra_report->might_fallback_legacy = mcs <= 2; 2074 sta->deflink.agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); 2075 rtwsta->max_agg_wait = sta->deflink.agg.max_rc_amsdu_len / 1500 - 1; 2076 } 2077 2078 static void 2079 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2080 { 2081 struct rtw89_phy_iter_ra_data ra_data; 2082 2083 ra_data.rtwdev = rtwdev; 2084 ra_data.c2h = c2h; 2085 ieee80211_iterate_stations_atomic(rtwdev->hw, 2086 rtw89_phy_c2h_ra_rpt_iter, 2087 &ra_data); 2088 } 2089 2090 static 2091 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, 2092 struct sk_buff *c2h, u32 len) = { 2093 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 2094 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 2095 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 2096 }; 2097 2098 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 2099 u32 len, u8 class, u8 func) 2100 { 2101 void (*handler)(struct rtw89_dev *rtwdev, 2102 struct sk_buff *c2h, u32 len) = NULL; 2103 2104 switch (class) { 2105 case RTW89_PHY_C2H_CLASS_RA: 2106 if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 2107 handler = rtw89_phy_c2h_ra_handler[func]; 2108 break; 2109 default: 2110 rtw89_info(rtwdev, "c2h class %d not support\n", class); 2111 return; 2112 } 2113 if (!handler) { 2114 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 2115 func); 2116 return; 2117 } 2118 handler(rtwdev, skb, len); 2119 } 2120 2121 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) 2122 { 2123 u32 reg_mask; 2124 2125 if (sc_xo) 2126 reg_mask = B_AX_XTAL_SC_XO_MASK; 2127 else 2128 reg_mask = B_AX_XTAL_SC_XI_MASK; 2129 2130 return (u8)rtw89_read32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask); 2131 } 2132 2133 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, 2134 u8 val) 2135 { 2136 u32 reg_mask; 2137 2138 if (sc_xo) 2139 reg_mask = B_AX_XTAL_SC_XO_MASK; 2140 else 2141 reg_mask = B_AX_XTAL_SC_XI_MASK; 2142 2143 rtw89_write32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask, val); 2144 } 2145 2146 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, 2147 u8 crystal_cap, bool force) 2148 { 2149 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2150 const struct rtw89_chip_info *chip = rtwdev->chip; 2151 u8 sc_xi_val, sc_xo_val; 2152 2153 if (!force && cfo->crystal_cap == crystal_cap) 2154 return; 2155 crystal_cap = clamp_t(u8, crystal_cap, 0, 127); 2156 if (chip->chip_id == RTL8852A) { 2157 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); 2158 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); 2159 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); 2160 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); 2161 } else { 2162 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, 2163 crystal_cap, XTAL_SC_XO_MASK); 2164 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, 2165 crystal_cap, XTAL_SC_XI_MASK); 2166 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val); 2167 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val); 2168 } 2169 cfo->crystal_cap = sc_xi_val; 2170 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); 2171 2172 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); 2173 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); 2174 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", 2175 cfo->x_cap_ofst); 2176 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); 2177 } 2178 2179 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) 2180 { 2181 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2182 u8 cap; 2183 2184 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; 2185 cfo->is_adjust = false; 2186 if (cfo->crystal_cap == cfo->def_x_cap) 2187 return; 2188 cap = cfo->crystal_cap; 2189 cap += (cap > cfo->def_x_cap ? -1 : 1); 2190 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); 2191 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2192 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, 2193 cfo->def_x_cap); 2194 } 2195 2196 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) 2197 { 2198 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp; 2199 bool is_linked = rtwdev->total_sta_assoc > 0; 2200 s32 cfo_avg_312; 2201 s32 dcfo_comp_val; 2202 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft; 2203 int sign; 2204 2205 if (!is_linked) { 2206 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", 2207 is_linked); 2208 return; 2209 } 2210 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); 2211 if (curr_cfo == 0) 2212 return; 2213 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); 2214 sign = curr_cfo > 0 ? 1 : -1; 2215 cfo_avg_312 = (curr_cfo << dcfo_comp_sft) / 5 + sign * dcfo_comp_val; 2216 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: avg_cfo=%d\n", cfo_avg_312); 2217 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 2218 cfo_avg_312 = -cfo_avg_312; 2219 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask, 2220 cfo_avg_312); 2221 } 2222 2223 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) 2224 { 2225 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_OPT, B_DCFO_OPT_EN, 1); 2226 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_WEIGHT, B_DCFO_WEIGHT_MSK, 8); 2227 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, B_AX_PWR_UL_CFO_MASK); 2228 } 2229 2230 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) 2231 { 2232 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2233 struct rtw89_efuse *efuse = &rtwdev->efuse; 2234 2235 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; 2236 cfo->crystal_cap = cfo->crystal_cap_default; 2237 cfo->def_x_cap = cfo->crystal_cap; 2238 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f); 2239 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1); 2240 cfo->is_adjust = false; 2241 cfo->divergence_lock_en = false; 2242 cfo->x_cap_ofst = 0; 2243 cfo->lock_cnt = 0; 2244 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; 2245 cfo->apply_compensation = false; 2246 cfo->residual_cfo_acc = 0; 2247 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", 2248 cfo->crystal_cap_default); 2249 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); 2250 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); 2251 rtw89_dcfo_comp_init(rtwdev); 2252 cfo->cfo_timer_ms = 2000; 2253 cfo->cfo_trig_by_timer_en = false; 2254 cfo->phy_cfo_trk_cnt = 0; 2255 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2256 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE; 2257 } 2258 2259 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, 2260 s32 curr_cfo) 2261 { 2262 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2263 s8 crystal_cap = cfo->crystal_cap; 2264 s32 cfo_abs = abs(curr_cfo); 2265 int sign; 2266 2267 if (!cfo->is_adjust) { 2268 if (cfo_abs > CFO_TRK_ENABLE_TH) 2269 cfo->is_adjust = true; 2270 } else { 2271 if (cfo_abs < CFO_TRK_STOP_TH) 2272 cfo->is_adjust = false; 2273 } 2274 if (!cfo->is_adjust) { 2275 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); 2276 return; 2277 } 2278 sign = curr_cfo > 0 ? 1 : -1; 2279 if (cfo_abs > CFO_TRK_STOP_TH_4) 2280 crystal_cap += 7 * sign; 2281 else if (cfo_abs > CFO_TRK_STOP_TH_3) 2282 crystal_cap += 5 * sign; 2283 else if (cfo_abs > CFO_TRK_STOP_TH_2) 2284 crystal_cap += 3 * sign; 2285 else if (cfo_abs > CFO_TRK_STOP_TH_1) 2286 crystal_cap += 1 * sign; 2287 else 2288 return; 2289 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); 2290 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2291 "X_cap{Curr,Default}={0x%x,0x%x}\n", 2292 cfo->crystal_cap, cfo->def_x_cap); 2293 } 2294 2295 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) 2296 { 2297 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2298 s32 cfo_khz_all = 0; 2299 s32 cfo_cnt_all = 0; 2300 s32 cfo_all_avg = 0; 2301 u8 i; 2302 2303 if (rtwdev->total_sta_assoc != 1) 2304 return 0; 2305 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); 2306 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2307 if (cfo->cfo_cnt[i] == 0) 2308 continue; 2309 cfo_khz_all += cfo->cfo_tail[i]; 2310 cfo_cnt_all += cfo->cfo_cnt[i]; 2311 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); 2312 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2313 } 2314 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2315 "CFO track for macid = %d\n", i); 2316 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2317 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", 2318 cfo_khz_all, cfo_cnt_all, cfo_all_avg); 2319 return cfo_all_avg; 2320 } 2321 2322 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) 2323 { 2324 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2325 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2326 s32 target_cfo = 0; 2327 s32 cfo_khz_all = 0; 2328 s32 cfo_khz_all_tp_wgt = 0; 2329 s32 cfo_avg = 0; 2330 s32 max_cfo_lb = BIT(31); 2331 s32 min_cfo_ub = GENMASK(30, 0); 2332 u16 cfo_cnt_all = 0; 2333 u8 active_entry_cnt = 0; 2334 u8 sta_cnt = 0; 2335 u32 tp_all = 0; 2336 u8 i; 2337 u8 cfo_tol = 0; 2338 2339 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); 2340 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { 2341 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); 2342 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2343 if (cfo->cfo_cnt[i] == 0) 2344 continue; 2345 cfo_khz_all += cfo->cfo_tail[i]; 2346 cfo_cnt_all += cfo->cfo_cnt[i]; 2347 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); 2348 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2349 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", 2350 cfo_khz_all, cfo_cnt_all, cfo_avg); 2351 target_cfo = cfo_avg; 2352 } 2353 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { 2354 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); 2355 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2356 if (cfo->cfo_cnt[i] == 0) 2357 continue; 2358 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2359 (s32)cfo->cfo_cnt[i]); 2360 cfo_khz_all += cfo->cfo_avg[i]; 2361 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2362 "Macid=%d, cfo_avg=%d\n", i, 2363 cfo->cfo_avg[i]); 2364 } 2365 sta_cnt = rtwdev->total_sta_assoc; 2366 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); 2367 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2368 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", 2369 cfo_khz_all, sta_cnt, cfo_avg); 2370 target_cfo = cfo_avg; 2371 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { 2372 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); 2373 cfo_tol = cfo->sta_cfo_tolerance; 2374 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2375 sta_cnt++; 2376 if (cfo->cfo_cnt[i] != 0) { 2377 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2378 (s32)cfo->cfo_cnt[i]); 2379 active_entry_cnt++; 2380 } else { 2381 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; 2382 } 2383 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); 2384 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); 2385 cfo_khz_all += cfo->cfo_avg[i]; 2386 /* need tp for each entry */ 2387 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2388 "[%d] cfo_avg=%d, tp=tbd\n", 2389 i, cfo->cfo_avg[i]); 2390 if (sta_cnt >= rtwdev->total_sta_assoc) 2391 break; 2392 } 2393 tp_all = stats->rx_throughput; /* need tp for each entry */ 2394 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); 2395 2396 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", 2397 sta_cnt); 2398 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", 2399 active_entry_cnt); 2400 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2401 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", 2402 cfo_khz_all_tp_wgt, cfo_avg); 2403 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", 2404 max_cfo_lb, min_cfo_ub); 2405 if (max_cfo_lb <= min_cfo_ub) { 2406 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2407 "cfo win_size=%d\n", 2408 min_cfo_ub - max_cfo_lb); 2409 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); 2410 } else { 2411 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2412 "No intersection of cfo tolerance windows\n"); 2413 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); 2414 } 2415 for (i = 0; i < CFO_TRACK_MAX_USER; i++) 2416 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2417 } 2418 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); 2419 return target_cfo; 2420 } 2421 2422 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) 2423 { 2424 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2425 2426 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); 2427 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); 2428 cfo->packet_count = 0; 2429 cfo->packet_count_pre = 0; 2430 cfo->cfo_avg_pre = 0; 2431 } 2432 2433 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) 2434 { 2435 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2436 s32 new_cfo = 0; 2437 bool x_cap_update = false; 2438 u8 pre_x_cap = cfo->crystal_cap; 2439 2440 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", 2441 rtwdev->total_sta_assoc); 2442 if (rtwdev->total_sta_assoc == 0) { 2443 rtw89_phy_cfo_reset(rtwdev); 2444 return; 2445 } 2446 if (cfo->packet_count == 0) { 2447 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); 2448 return; 2449 } 2450 if (cfo->packet_count == cfo->packet_count_pre) { 2451 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); 2452 return; 2453 } 2454 if (rtwdev->total_sta_assoc == 1) 2455 new_cfo = rtw89_phy_average_cfo_calc(rtwdev); 2456 else 2457 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); 2458 if (new_cfo == 0) { 2459 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); 2460 return; 2461 } 2462 if (cfo->divergence_lock_en) { 2463 cfo->lock_cnt++; 2464 if (cfo->lock_cnt > CFO_PERIOD_CNT) { 2465 cfo->divergence_lock_en = false; 2466 cfo->lock_cnt = 0; 2467 } else { 2468 rtw89_phy_cfo_reset(rtwdev); 2469 } 2470 return; 2471 } 2472 if (cfo->crystal_cap >= cfo->x_cap_ub || 2473 cfo->crystal_cap <= cfo->x_cap_lb) { 2474 cfo->divergence_lock_en = true; 2475 rtw89_phy_cfo_reset(rtwdev); 2476 return; 2477 } 2478 2479 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); 2480 cfo->cfo_avg_pre = new_cfo; 2481 x_cap_update = cfo->crystal_cap != pre_x_cap; 2482 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); 2483 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", 2484 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, 2485 cfo->x_cap_ofst); 2486 if (x_cap_update) { 2487 if (new_cfo > 0) 2488 new_cfo -= CFO_SW_COMP_FINE_TUNE; 2489 else 2490 new_cfo += CFO_SW_COMP_FINE_TUNE; 2491 } 2492 rtw89_dcfo_comp(rtwdev, new_cfo); 2493 rtw89_phy_cfo_statistics_reset(rtwdev); 2494 } 2495 2496 void rtw89_phy_cfo_track_work(struct work_struct *work) 2497 { 2498 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2499 cfo_track_work.work); 2500 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2501 2502 mutex_lock(&rtwdev->mutex); 2503 if (!cfo->cfo_trig_by_timer_en) 2504 goto out; 2505 rtw89_leave_ps_mode(rtwdev); 2506 rtw89_phy_cfo_dm(rtwdev); 2507 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2508 msecs_to_jiffies(cfo->cfo_timer_ms)); 2509 out: 2510 mutex_unlock(&rtwdev->mutex); 2511 } 2512 2513 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) 2514 { 2515 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2516 2517 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2518 msecs_to_jiffies(cfo->cfo_timer_ms)); 2519 } 2520 2521 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) 2522 { 2523 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2524 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2525 bool is_ul_ofdma = false, ofdma_acc_en = false; 2526 2527 if (stats->rx_tf_periodic > CFO_TF_CNT_TH) 2528 is_ul_ofdma = true; 2529 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE && 2530 is_ul_ofdma) 2531 ofdma_acc_en = true; 2532 2533 switch (cfo->phy_cfo_status) { 2534 case RTW89_PHY_DCFO_STATE_NORMAL: 2535 if (stats->tx_throughput >= CFO_TP_UPPER) { 2536 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; 2537 cfo->cfo_trig_by_timer_en = true; 2538 cfo->cfo_timer_ms = CFO_COMP_PERIOD; 2539 rtw89_phy_cfo_start_work(rtwdev); 2540 } 2541 break; 2542 case RTW89_PHY_DCFO_STATE_ENHANCE: 2543 if (stats->tx_throughput <= CFO_TP_LOWER) 2544 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2545 else if (ofdma_acc_en && 2546 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) 2547 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD; 2548 else 2549 cfo->phy_cfo_trk_cnt++; 2550 2551 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) { 2552 cfo->phy_cfo_trk_cnt = 0; 2553 cfo->cfo_trig_by_timer_en = false; 2554 } 2555 break; 2556 case RTW89_PHY_DCFO_STATE_HOLD: 2557 if (stats->tx_throughput <= CFO_TP_LOWER) { 2558 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2559 cfo->phy_cfo_trk_cnt = 0; 2560 cfo->cfo_trig_by_timer_en = false; 2561 } else { 2562 cfo->phy_cfo_trk_cnt++; 2563 } 2564 break; 2565 default: 2566 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2567 cfo->phy_cfo_trk_cnt = 0; 2568 break; 2569 } 2570 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2571 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", 2572 stats->tx_throughput, cfo->phy_cfo_status, 2573 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, 2574 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); 2575 if (cfo->cfo_trig_by_timer_en) 2576 return; 2577 rtw89_phy_cfo_dm(rtwdev); 2578 } 2579 2580 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 2581 struct rtw89_rx_phy_ppdu *phy_ppdu) 2582 { 2583 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2584 u8 macid = phy_ppdu->mac_id; 2585 2586 if (macid >= CFO_TRACK_MAX_USER) { 2587 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid); 2588 return; 2589 } 2590 2591 cfo->cfo_tail[macid] += cfo_val; 2592 cfo->cfo_cnt[macid]++; 2593 cfo->packet_count++; 2594 } 2595 2596 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) 2597 { 2598 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2599 int i; 2600 u8 th; 2601 2602 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 2603 th = rtw89_chip_get_thermal(rtwdev, i); 2604 if (th) 2605 ewma_thermal_add(&phystat->avg_thermal[i], th); 2606 2607 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 2608 "path(%d) thermal cur=%u avg=%ld", i, th, 2609 ewma_thermal_read(&phystat->avg_thermal[i])); 2610 } 2611 } 2612 2613 struct rtw89_phy_iter_rssi_data { 2614 struct rtw89_dev *rtwdev; 2615 struct rtw89_phy_ch_info *ch_info; 2616 bool rssi_changed; 2617 }; 2618 2619 static void rtw89_phy_stat_rssi_update_iter(void *data, 2620 struct ieee80211_sta *sta) 2621 { 2622 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2623 struct rtw89_phy_iter_rssi_data *rssi_data = 2624 (struct rtw89_phy_iter_rssi_data *)data; 2625 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info; 2626 unsigned long rssi_curr; 2627 2628 rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi); 2629 2630 if (rssi_curr < ch_info->rssi_min) { 2631 ch_info->rssi_min = rssi_curr; 2632 ch_info->rssi_min_macid = rtwsta->mac_id; 2633 } 2634 2635 if (rtwsta->prev_rssi == 0) { 2636 rtwsta->prev_rssi = rssi_curr; 2637 } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) { 2638 rtwsta->prev_rssi = rssi_curr; 2639 rssi_data->rssi_changed = true; 2640 } 2641 } 2642 2643 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) 2644 { 2645 struct rtw89_phy_iter_rssi_data rssi_data = {0}; 2646 2647 rssi_data.rtwdev = rtwdev; 2648 rssi_data.ch_info = &rtwdev->ch_info; 2649 rssi_data.ch_info->rssi_min = U8_MAX; 2650 ieee80211_iterate_stations_atomic(rtwdev->hw, 2651 rtw89_phy_stat_rssi_update_iter, 2652 &rssi_data); 2653 if (rssi_data.rssi_changed) 2654 rtw89_btc_ntfy_wl_sta(rtwdev); 2655 } 2656 2657 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) 2658 { 2659 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2660 int i; 2661 2662 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 2663 ewma_thermal_init(&phystat->avg_thermal[i]); 2664 2665 rtw89_phy_stat_thermal_update(rtwdev); 2666 2667 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 2668 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); 2669 } 2670 2671 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) 2672 { 2673 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2674 2675 rtw89_phy_stat_thermal_update(rtwdev); 2676 rtw89_phy_stat_rssi_update(rtwdev); 2677 2678 phystat->last_pkt_stat = phystat->cur_pkt_stat; 2679 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 2680 } 2681 2682 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us) 2683 { 2684 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2685 2686 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 2687 } 2688 2689 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) 2690 { 2691 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2692 2693 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 2694 } 2695 2696 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) 2697 { 2698 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2699 2700 env->ccx_manual_ctrl = false; 2701 env->ccx_ongoing = false; 2702 env->ccx_rac_lv = RTW89_RAC_RELEASE; 2703 env->ccx_rpt_stamp = 0; 2704 env->ccx_period = 0; 2705 env->ccx_unit_idx = RTW89_CCX_32_US; 2706 env->ccx_trigger_time = 0; 2707 env->ccx_edcca_opt_bw_idx = RTW89_CCX_EDCCA_BW20_0; 2708 2709 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1); 2710 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1); 2711 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 2712 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EDCCA_OPT_MSK, 2713 RTW89_CCX_EDCCA_BW20_0); 2714 } 2715 2716 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report, 2717 u16 score) 2718 { 2719 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2720 u32 numer = 0; 2721 u16 ret = 0; 2722 2723 numer = report * score + (env->ccx_period >> 1); 2724 if (env->ccx_period) 2725 ret = numer / env->ccx_period; 2726 2727 return ret >= score ? score - 1 : ret; 2728 } 2729 2730 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, 2731 u16 time_ms, u32 *period, 2732 u32 *unit_idx) 2733 { 2734 u32 idx; 2735 u8 quotient; 2736 2737 if (time_ms >= CCX_MAX_PERIOD) 2738 time_ms = CCX_MAX_PERIOD; 2739 2740 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; 2741 2742 if (quotient < 4) 2743 idx = RTW89_CCX_4_US; 2744 else if (quotient < 8) 2745 idx = RTW89_CCX_8_US; 2746 else if (quotient < 16) 2747 idx = RTW89_CCX_16_US; 2748 else 2749 idx = RTW89_CCX_32_US; 2750 2751 *unit_idx = idx; 2752 *period = (time_ms * MS_TO_4US_RATIO) >> idx; 2753 2754 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2755 "[Trigger Time] period:%d, unit_idx:%d\n", 2756 *period, *unit_idx); 2757 } 2758 2759 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev) 2760 { 2761 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2762 2763 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2764 "lv:(%d)->(0)\n", env->ccx_rac_lv); 2765 2766 env->ccx_ongoing = false; 2767 env->ccx_rac_lv = RTW89_RAC_RELEASE; 2768 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 2769 } 2770 2771 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, 2772 struct rtw89_ccx_para_info *para) 2773 { 2774 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2775 bool is_update = env->ifs_clm_app != para->ifs_clm_app; 2776 u8 i = 0; 2777 u16 *ifs_th_l = env->ifs_clm_th_l; 2778 u16 *ifs_th_h = env->ifs_clm_th_h; 2779 u32 ifs_th0_us = 0, ifs_th_times = 0; 2780 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; 2781 2782 if (!is_update) 2783 goto ifs_update_finished; 2784 2785 switch (para->ifs_clm_app) { 2786 case RTW89_IFS_CLM_INIT: 2787 case RTW89_IFS_CLM_BACKGROUND: 2788 case RTW89_IFS_CLM_ACS: 2789 case RTW89_IFS_CLM_DBG: 2790 case RTW89_IFS_CLM_DIG: 2791 case RTW89_IFS_CLM_TDMA_DIG: 2792 ifs_th0_us = IFS_CLM_TH0_UPPER; 2793 ifs_th_times = IFS_CLM_TH_MUL; 2794 break; 2795 case RTW89_IFS_CLM_DBG_MANUAL: 2796 ifs_th0_us = para->ifs_clm_manual_th0; 2797 ifs_th_times = para->ifs_clm_manual_th_times; 2798 break; 2799 default: 2800 break; 2801 } 2802 2803 /* Set sampling threshold for 4 different regions, unit in idx_cnt. 2804 * low[i] = high[i-1] + 1 2805 * high[i] = high[i-1] * ifs_th_times 2806 */ 2807 ifs_th_l[IFS_CLM_TH_START_IDX] = 0; 2808 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; 2809 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, 2810 ifs_th0_us); 2811 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { 2812 ifs_th_l[i] = ifs_th_h[i - 1] + 1; 2813 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; 2814 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]); 2815 } 2816 2817 ifs_update_finished: 2818 if (!is_update) 2819 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2820 "No need to update IFS_TH\n"); 2821 2822 return is_update; 2823 } 2824 2825 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) 2826 { 2827 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2828 u8 i = 0; 2829 2830 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_LOW_MSK, 2831 env->ifs_clm_th_l[0]); 2832 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_LOW_MSK, 2833 env->ifs_clm_th_l[1]); 2834 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_LOW_MSK, 2835 env->ifs_clm_th_l[2]); 2836 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_LOW_MSK, 2837 env->ifs_clm_th_l[3]); 2838 2839 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_HIGH_MSK, 2840 env->ifs_clm_th_h[0]); 2841 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_HIGH_MSK, 2842 env->ifs_clm_th_h[1]); 2843 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_HIGH_MSK, 2844 env->ifs_clm_th_h[2]); 2845 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_HIGH_MSK, 2846 env->ifs_clm_th_h[3]); 2847 2848 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 2849 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2850 "Update IFS_T%d_th{low, high} : {%d, %d}\n", 2851 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 2852 } 2853 2854 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) 2855 { 2856 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2857 struct rtw89_ccx_para_info para = {0}; 2858 2859 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 2860 env->ifs_clm_mntr_time = 0; 2861 2862 para.ifs_clm_app = RTW89_IFS_CLM_INIT; 2863 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) 2864 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 2865 2866 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COLLECT_EN, 2867 true); 2868 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_EN_MSK, true); 2869 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_EN_MSK, true); 2870 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_EN_MSK, true); 2871 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_EN_MSK, true); 2872 } 2873 2874 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, 2875 enum rtw89_env_racing_lv level) 2876 { 2877 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2878 int ret = 0; 2879 2880 if (level >= RTW89_RAC_MAX_NUM) { 2881 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2882 "[WARNING] Wrong LV=%d\n", level); 2883 return -EINVAL; 2884 } 2885 2886 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2887 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, 2888 env->ccx_rac_lv, level); 2889 2890 if (env->ccx_ongoing) { 2891 if (level <= env->ccx_rac_lv) 2892 ret = -EINVAL; 2893 else 2894 env->ccx_ongoing = false; 2895 } 2896 2897 if (ret == 0) 2898 env->ccx_rac_lv = level; 2899 2900 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", 2901 !ret); 2902 2903 return ret; 2904 } 2905 2906 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) 2907 { 2908 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2909 2910 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 0); 2911 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 0); 2912 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1); 2913 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 2914 2915 env->ccx_rpt_stamp++; 2916 env->ccx_ongoing = true; 2917 } 2918 2919 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) 2920 { 2921 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2922 u8 i = 0; 2923 u32 res = 0; 2924 2925 env->ifs_clm_tx_ratio = 2926 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT); 2927 env->ifs_clm_edcca_excl_cca_ratio = 2928 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca, 2929 PERCENT); 2930 env->ifs_clm_cck_fa_ratio = 2931 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT); 2932 env->ifs_clm_ofdm_fa_ratio = 2933 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT); 2934 env->ifs_clm_cck_cca_excl_fa_ratio = 2935 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa, 2936 PERCENT); 2937 env->ifs_clm_ofdm_cca_excl_fa_ratio = 2938 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa, 2939 PERCENT); 2940 env->ifs_clm_cck_fa_permil = 2941 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL); 2942 env->ifs_clm_ofdm_fa_permil = 2943 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL); 2944 2945 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { 2946 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { 2947 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; 2948 } else { 2949 env->ifs_clm_ifs_avg[i] = 2950 rtw89_phy_ccx_idx_to_us(rtwdev, 2951 env->ifs_clm_avg[i]); 2952 } 2953 2954 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]); 2955 res += env->ifs_clm_his[i] >> 1; 2956 if (env->ifs_clm_his[i]) 2957 res /= env->ifs_clm_his[i]; 2958 else 2959 res = 0; 2960 env->ifs_clm_cca_avg[i] = res; 2961 } 2962 2963 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2964 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", 2965 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); 2966 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2967 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", 2968 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); 2969 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2970 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", 2971 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); 2972 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2973 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", 2974 env->ifs_clm_cck_cca_excl_fa_ratio, 2975 env->ifs_clm_ofdm_cca_excl_fa_ratio); 2976 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2977 "Time:[his, ifs_avg(us), cca_avg(us)]\n"); 2978 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 2979 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 2980 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 2981 env->ifs_clm_cca_avg[i]); 2982 } 2983 2984 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) 2985 { 2986 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2987 u8 i = 0; 2988 2989 if (rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_DONE_MSK) == 0) { 2990 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2991 "Get IFS_CLM report Fail\n"); 2992 return false; 2993 } 2994 2995 env->ifs_clm_tx = 2996 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 2997 B_IFS_CLM_TX_CNT_MSK); 2998 env->ifs_clm_edcca_excl_cca = 2999 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 3000 B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK); 3001 env->ifs_clm_cckcca_excl_fa = 3002 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 3003 B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK); 3004 env->ifs_clm_ofdmcca_excl_fa = 3005 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 3006 B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK); 3007 env->ifs_clm_cckfa = 3008 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 3009 B_IFS_CLM_CCK_FA_MSK); 3010 env->ifs_clm_ofdmfa = 3011 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 3012 B_IFS_CLM_OFDM_FA_MSK); 3013 3014 env->ifs_clm_his[0] = 3015 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T1_HIS_MSK); 3016 env->ifs_clm_his[1] = 3017 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T2_HIS_MSK); 3018 env->ifs_clm_his[2] = 3019 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T3_HIS_MSK); 3020 env->ifs_clm_his[3] = 3021 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T4_HIS_MSK); 3022 3023 env->ifs_clm_avg[0] = 3024 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T1_AVG_MSK); 3025 env->ifs_clm_avg[1] = 3026 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T2_AVG_MSK); 3027 env->ifs_clm_avg[2] = 3028 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T3_AVG_MSK); 3029 env->ifs_clm_avg[3] = 3030 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T4_AVG_MSK); 3031 3032 env->ifs_clm_cca[0] = 3033 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T1_CCA_MSK); 3034 env->ifs_clm_cca[1] = 3035 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T2_CCA_MSK); 3036 env->ifs_clm_cca[2] = 3037 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T3_CCA_MSK); 3038 env->ifs_clm_cca[3] = 3039 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T4_CCA_MSK); 3040 3041 env->ifs_clm_total_ifs = 3042 rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_TOTAL_CNT_MSK); 3043 3044 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", 3045 env->ifs_clm_total_ifs); 3046 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3047 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", 3048 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); 3049 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3050 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", 3051 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); 3052 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3053 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", 3054 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); 3055 3056 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); 3057 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3058 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3059 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], 3060 env->ifs_clm_avg[i], env->ifs_clm_cca[i]); 3061 3062 rtw89_phy_ifs_clm_get_utility(rtwdev); 3063 3064 return true; 3065 } 3066 3067 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 3068 struct rtw89_ccx_para_info *para) 3069 { 3070 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3071 u32 period = 0; 3072 u32 unit_idx = 0; 3073 3074 if (para->mntr_time == 0) { 3075 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3076 "[WARN] MNTR_TIME is 0\n"); 3077 return -EINVAL; 3078 } 3079 3080 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv)) 3081 return -EINVAL; 3082 3083 if (para->mntr_time != env->ifs_clm_mntr_time) { 3084 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 3085 &period, &unit_idx); 3086 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 3087 B_IFS_CLM_PERIOD_MSK, period); 3088 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 3089 B_IFS_CLM_COUNTER_UNIT_MSK, unit_idx); 3090 3091 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3092 "Update IFS-CLM time ((%d)) -> ((%d))\n", 3093 env->ifs_clm_mntr_time, para->mntr_time); 3094 3095 env->ifs_clm_mntr_time = para->mntr_time; 3096 env->ccx_period = (u16)period; 3097 env->ccx_unit_idx = (u8)unit_idx; 3098 } 3099 3100 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) { 3101 env->ifs_clm_app = para->ifs_clm_app; 3102 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 3103 } 3104 3105 return 0; 3106 } 3107 3108 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) 3109 { 3110 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3111 struct rtw89_ccx_para_info para = {0}; 3112 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3113 3114 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3115 if (env->ccx_manual_ctrl) { 3116 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3117 "CCX in manual ctrl\n"); 3118 return; 3119 } 3120 3121 /* only ifs_clm for now */ 3122 if (rtw89_phy_ifs_clm_get_result(rtwdev)) 3123 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3124 3125 rtw89_phy_ccx_racing_release(rtwdev); 3126 para.mntr_time = 1900; 3127 para.rac_lv = RTW89_RAC_LV_1; 3128 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3129 3130 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0) 3131 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3132 if (chk_result) 3133 rtw89_phy_ccx_trigger(rtwdev); 3134 3135 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3136 "get_result=0x%x, chk_result:0x%x\n", 3137 env->ccx_watchdog_result, chk_result); 3138 } 3139 3140 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page) 3141 { 3142 if (*ie_page > RTW89_PHYSTS_BITMAP_NUM || 3143 *ie_page == RTW89_RSVD_9) 3144 return false; 3145 else if (*ie_page > RTW89_RSVD_9) 3146 *ie_page -= 1; 3147 3148 return true; 3149 } 3150 3151 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) 3152 { 3153 static const u8 ie_page_shift = 2; 3154 3155 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); 3156 } 3157 3158 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, 3159 enum rtw89_phy_status_bitmap ie_page) 3160 { 3161 u32 addr; 3162 3163 if (!rtw89_physts_ie_page_valid(&ie_page)) 3164 return 0; 3165 3166 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3167 3168 return rtw89_phy_read32(rtwdev, addr); 3169 } 3170 3171 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, 3172 enum rtw89_phy_status_bitmap ie_page, 3173 u32 val) 3174 { 3175 const struct rtw89_chip_info *chip = rtwdev->chip; 3176 u32 addr; 3177 3178 if (!rtw89_physts_ie_page_valid(&ie_page)) 3179 return; 3180 3181 if (chip->chip_id == RTL8852A) 3182 val &= B_PHY_STS_BITMAP_MSK_52A; 3183 3184 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3185 rtw89_phy_write32(rtwdev, addr, val); 3186 } 3187 3188 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev, 3189 enum rtw89_phy_status_bitmap bitmap, 3190 enum rtw89_phy_status_ie_type ie, 3191 bool enable) 3192 { 3193 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap); 3194 3195 if (enable) 3196 val |= BIT(ie); 3197 else 3198 val &= ~BIT(ie); 3199 3200 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val); 3201 } 3202 3203 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, 3204 bool enable, 3205 enum rtw89_phy_idx phy_idx) 3206 { 3207 if (enable) { 3208 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3209 B_STS_DIS_TRIG_BY_FAIL); 3210 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3211 B_STS_DIS_TRIG_BY_BRK); 3212 } else { 3213 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3214 B_STS_DIS_TRIG_BY_FAIL); 3215 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3216 B_STS_DIS_TRIG_BY_BRK); 3217 } 3218 } 3219 3220 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev) 3221 { 3222 u8 i; 3223 3224 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0); 3225 3226 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { 3227 if (i >= RTW89_CCK_PKT) 3228 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3229 RTW89_PHYSTS_IE09_FTR_0, 3230 true); 3231 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) || 3232 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT)) 3233 continue; 3234 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3235 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A, 3236 true); 3237 } 3238 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT, 3239 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3240 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT, 3241 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3242 3243 /* force IE01 for channel index, only channel field is valid */ 3244 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT, 3245 RTW89_PHYSTS_IE01_CMN_OFDM, true); 3246 } 3247 3248 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) 3249 { 3250 const struct rtw89_chip_info *chip = rtwdev->chip; 3251 struct rtw89_dig_info *dig = &rtwdev->dig; 3252 const struct rtw89_phy_dig_gain_cfg *cfg; 3253 const char *msg; 3254 u8 i; 3255 s8 gain_base; 3256 s8 *gain_arr; 3257 u32 tmp; 3258 3259 switch (type) { 3260 case RTW89_DIG_GAIN_LNA_G: 3261 gain_arr = dig->lna_gain_g; 3262 gain_base = LNA0_GAIN; 3263 cfg = chip->dig_table->cfg_lna_g; 3264 msg = "lna_gain_g"; 3265 break; 3266 case RTW89_DIG_GAIN_TIA_G: 3267 gain_arr = dig->tia_gain_g; 3268 gain_base = TIA0_GAIN_G; 3269 cfg = chip->dig_table->cfg_tia_g; 3270 msg = "tia_gain_g"; 3271 break; 3272 case RTW89_DIG_GAIN_LNA_A: 3273 gain_arr = dig->lna_gain_a; 3274 gain_base = LNA0_GAIN; 3275 cfg = chip->dig_table->cfg_lna_a; 3276 msg = "lna_gain_a"; 3277 break; 3278 case RTW89_DIG_GAIN_TIA_A: 3279 gain_arr = dig->tia_gain_a; 3280 gain_base = TIA0_GAIN_A; 3281 cfg = chip->dig_table->cfg_tia_a; 3282 msg = "tia_gain_a"; 3283 break; 3284 default: 3285 return; 3286 } 3287 3288 for (i = 0; i < cfg->size; i++) { 3289 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr, 3290 cfg->table[i].mask); 3291 tmp >>= DIG_GAIN_SHIFT; 3292 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; 3293 gain_base += DIG_GAIN; 3294 3295 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", 3296 msg, i, gain_arr[i]); 3297 } 3298 } 3299 3300 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev) 3301 { 3302 struct rtw89_dig_info *dig = &rtwdev->dig; 3303 u32 tmp; 3304 u8 i; 3305 3306 if (!rtwdev->hal.support_igi) 3307 return; 3308 3309 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW, 3310 B_PATH0_IB_PKPW_MSK); 3311 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); 3312 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK, 3313 B_PATH0_IB_PBK_MSK); 3314 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", 3315 dig->ib_pkpwr, dig->ib_pbk); 3316 3317 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) 3318 rtw89_phy_dig_read_gain_table(rtwdev, i); 3319 } 3320 3321 static const u8 rssi_nolink = 22; 3322 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; 3323 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; 3324 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; 3325 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; 3326 3327 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev) 3328 { 3329 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 3330 struct rtw89_dig_info *dig = &rtwdev->dig; 3331 bool is_linked = rtwdev->total_sta_assoc > 0; 3332 3333 if (is_linked) { 3334 dig->igi_rssi = ch_info->rssi_min >> 1; 3335 } else { 3336 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); 3337 dig->igi_rssi = rssi_nolink; 3338 } 3339 } 3340 3341 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev) 3342 { 3343 struct rtw89_dig_info *dig = &rtwdev->dig; 3344 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3345 bool is_linked = rtwdev->total_sta_assoc > 0; 3346 const u16 *fa_th_src = NULL; 3347 3348 switch (chan->band_type) { 3349 case RTW89_BAND_2G: 3350 dig->lna_gain = dig->lna_gain_g; 3351 dig->tia_gain = dig->tia_gain_g; 3352 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; 3353 dig->force_gaincode_idx_en = false; 3354 dig->dyn_pd_th_en = true; 3355 break; 3356 case RTW89_BAND_5G: 3357 default: 3358 dig->lna_gain = dig->lna_gain_a; 3359 dig->tia_gain = dig->tia_gain_a; 3360 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; 3361 dig->force_gaincode_idx_en = true; 3362 dig->dyn_pd_th_en = true; 3363 break; 3364 } 3365 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); 3366 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); 3367 } 3368 3369 static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20; 3370 static const u8 igi_max_performance_mode = 0x5a; 3371 static const u8 dynamic_pd_threshold_max; 3372 3373 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev) 3374 { 3375 struct rtw89_dig_info *dig = &rtwdev->dig; 3376 3377 dig->cur_gaincode.lna_idx = LNA_IDX_MAX; 3378 dig->cur_gaincode.tia_idx = TIA_IDX_MAX; 3379 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; 3380 dig->force_gaincode.lna_idx = LNA_IDX_MAX; 3381 dig->force_gaincode.tia_idx = TIA_IDX_MAX; 3382 dig->force_gaincode.rxb_idx = RXB_IDX_MAX; 3383 3384 dig->dyn_igi_max = igi_max_performance_mode; 3385 dig->dyn_igi_min = dynamic_igi_min; 3386 dig->dyn_pd_th_max = dynamic_pd_threshold_max; 3387 dig->pd_low_th_ofst = pd_low_th_offset; 3388 dig->is_linked_pre = false; 3389 } 3390 3391 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) 3392 { 3393 rtw89_phy_dig_update_gain_para(rtwdev); 3394 rtw89_phy_dig_reset(rtwdev); 3395 } 3396 3397 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3398 { 3399 struct rtw89_dig_info *dig = &rtwdev->dig; 3400 u8 lna_idx; 3401 3402 if (rssi < dig->igi_rssi_th[0]) 3403 lna_idx = RTW89_DIG_GAIN_LNA_IDX6; 3404 else if (rssi < dig->igi_rssi_th[1]) 3405 lna_idx = RTW89_DIG_GAIN_LNA_IDX5; 3406 else if (rssi < dig->igi_rssi_th[2]) 3407 lna_idx = RTW89_DIG_GAIN_LNA_IDX4; 3408 else if (rssi < dig->igi_rssi_th[3]) 3409 lna_idx = RTW89_DIG_GAIN_LNA_IDX3; 3410 else if (rssi < dig->igi_rssi_th[4]) 3411 lna_idx = RTW89_DIG_GAIN_LNA_IDX2; 3412 else 3413 lna_idx = RTW89_DIG_GAIN_LNA_IDX1; 3414 3415 return lna_idx; 3416 } 3417 3418 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3419 { 3420 struct rtw89_dig_info *dig = &rtwdev->dig; 3421 u8 tia_idx; 3422 3423 if (rssi < dig->igi_rssi_th[0]) 3424 tia_idx = RTW89_DIG_GAIN_TIA_IDX1; 3425 else 3426 tia_idx = RTW89_DIG_GAIN_TIA_IDX0; 3427 3428 return tia_idx; 3429 } 3430 3431 #define IB_PBK_BASE 110 3432 #define WB_RSSI_BASE 10 3433 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3434 struct rtw89_agc_gaincode_set *set) 3435 { 3436 struct rtw89_dig_info *dig = &rtwdev->dig; 3437 s8 lna_gain = dig->lna_gain[set->lna_idx]; 3438 s8 tia_gain = dig->tia_gain[set->tia_idx]; 3439 s32 wb_rssi = rssi + lna_gain + tia_gain; 3440 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; 3441 u8 rxb_idx; 3442 3443 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; 3444 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); 3445 3446 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", 3447 wb_rssi, rxb_idx_tmp); 3448 3449 return rxb_idx; 3450 } 3451 3452 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3453 struct rtw89_agc_gaincode_set *set) 3454 { 3455 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi); 3456 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi); 3457 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set); 3458 3459 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3460 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", 3461 rssi, set->lna_idx, set->tia_idx, set->rxb_idx); 3462 } 3463 3464 #define IGI_OFFSET_MAX 25 3465 #define IGI_OFFSET_MUL 2 3466 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev) 3467 { 3468 struct rtw89_dig_info *dig = &rtwdev->dig; 3469 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3470 enum rtw89_dig_noisy_level noisy_lv; 3471 u8 igi_offset = dig->fa_rssi_ofst; 3472 u16 fa_ratio = 0; 3473 3474 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; 3475 3476 if (fa_ratio < dig->fa_th[0]) 3477 noisy_lv = RTW89_DIG_NOISY_LEVEL0; 3478 else if (fa_ratio < dig->fa_th[1]) 3479 noisy_lv = RTW89_DIG_NOISY_LEVEL1; 3480 else if (fa_ratio < dig->fa_th[2]) 3481 noisy_lv = RTW89_DIG_NOISY_LEVEL2; 3482 else if (fa_ratio < dig->fa_th[3]) 3483 noisy_lv = RTW89_DIG_NOISY_LEVEL3; 3484 else 3485 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; 3486 3487 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) 3488 igi_offset = 0; 3489 else 3490 igi_offset += noisy_lv * IGI_OFFSET_MUL; 3491 3492 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); 3493 dig->fa_rssi_ofst = igi_offset; 3494 3495 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3496 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", 3497 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); 3498 3499 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3500 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", 3501 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, 3502 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, 3503 noisy_lv, igi_offset); 3504 } 3505 3506 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx) 3507 { 3508 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3509 3510 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_lna_init.addr, 3511 dig_regs->p0_lna_init.mask, lna_idx); 3512 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_lna_init.addr, 3513 dig_regs->p1_lna_init.mask, lna_idx); 3514 } 3515 3516 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx) 3517 { 3518 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3519 3520 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_tia_init.addr, 3521 dig_regs->p0_tia_init.mask, tia_idx); 3522 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_tia_init.addr, 3523 dig_regs->p1_tia_init.mask, tia_idx); 3524 } 3525 3526 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx) 3527 { 3528 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3529 3530 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_rxb_init.addr, 3531 dig_regs->p0_rxb_init.mask, rxb_idx); 3532 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_rxb_init.addr, 3533 dig_regs->p1_rxb_init.mask, rxb_idx); 3534 } 3535 3536 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, 3537 const struct rtw89_agc_gaincode_set set) 3538 { 3539 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx); 3540 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx); 3541 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx); 3542 3543 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", 3544 set.lna_idx, set.tia_idx, set.rxb_idx); 3545 } 3546 3547 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, 3548 bool enable) 3549 { 3550 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3551 3552 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_p20_pagcugc_en.addr, 3553 dig_regs->p0_p20_pagcugc_en.mask, enable); 3554 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_s20_pagcugc_en.addr, 3555 dig_regs->p0_s20_pagcugc_en.mask, enable); 3556 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_p20_pagcugc_en.addr, 3557 dig_regs->p1_p20_pagcugc_en.mask, enable); 3558 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_s20_pagcugc_en.addr, 3559 dig_regs->p1_s20_pagcugc_en.mask, enable); 3560 3561 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); 3562 } 3563 3564 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev) 3565 { 3566 struct rtw89_dig_info *dig = &rtwdev->dig; 3567 3568 if (!rtwdev->hal.support_igi) 3569 return; 3570 3571 if (dig->force_gaincode_idx_en) { 3572 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 3573 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3574 "Force gaincode index enabled.\n"); 3575 } else { 3576 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi, 3577 &dig->cur_gaincode); 3578 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode); 3579 } 3580 } 3581 3582 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, 3583 bool enable) 3584 { 3585 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3586 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3587 enum rtw89_bandwidth cbw = chan->band_width; 3588 struct rtw89_dig_info *dig = &rtwdev->dig; 3589 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; 3590 u8 ofdm_cca_th; 3591 s8 cck_cca_th; 3592 u32 pd_val = 0; 3593 3594 under_region += PD_TH_SB_FLTR_CMP_VAL; 3595 3596 switch (cbw) { 3597 case RTW89_CHANNEL_WIDTH_40: 3598 under_region += PD_TH_BW40_CMP_VAL; 3599 break; 3600 case RTW89_CHANNEL_WIDTH_80: 3601 under_region += PD_TH_BW80_CMP_VAL; 3602 break; 3603 case RTW89_CHANNEL_WIDTH_160: 3604 under_region += PD_TH_BW160_CMP_VAL; 3605 break; 3606 case RTW89_CHANNEL_WIDTH_20: 3607 fallthrough; 3608 default: 3609 under_region += PD_TH_BW20_CMP_VAL; 3610 break; 3611 } 3612 3613 dig->dyn_pd_th_max = dig->igi_rssi; 3614 3615 final_rssi = min_t(u8, rssi, dig->igi_rssi); 3616 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, 3617 PD_TH_MAX_RSSI + under_region); 3618 3619 if (enable) { 3620 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1; 3621 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3622 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n", 3623 final_rssi, ofdm_cca_th, under_region, pd_val); 3624 } else { 3625 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3626 "Dynamic PD th disabled, Set PD_low_bd=0\n"); 3627 } 3628 3629 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 3630 dig_regs->pd_lower_bound_mask, pd_val); 3631 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 3632 dig_regs->pd_spatial_reuse_en, enable); 3633 3634 if (!rtwdev->hal.support_cckpd) 3635 return; 3636 3637 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI); 3638 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX); 3639 3640 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3641 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n", 3642 final_rssi, cck_cca_th, under_region, pd_val); 3643 3644 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_EN_V1, 3645 B_BMODE_PDTH_LIMIT_EN_MSK_V1, enable); 3646 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_V1, 3647 B_BMODE_PDTH_LOWER_BOUND_MSK_V1, pd_val); 3648 } 3649 3650 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) 3651 { 3652 struct rtw89_dig_info *dig = &rtwdev->dig; 3653 3654 dig->bypass_dig = false; 3655 rtw89_phy_dig_para_reset(rtwdev); 3656 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 3657 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false); 3658 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 3659 rtw89_phy_dig_update_para(rtwdev); 3660 } 3661 3662 #define IGI_RSSI_MIN 10 3663 void rtw89_phy_dig(struct rtw89_dev *rtwdev) 3664 { 3665 struct rtw89_dig_info *dig = &rtwdev->dig; 3666 bool is_linked = rtwdev->total_sta_assoc > 0; 3667 3668 if (unlikely(dig->bypass_dig)) { 3669 dig->bypass_dig = false; 3670 return; 3671 } 3672 3673 if (!dig->is_linked_pre && is_linked) { 3674 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); 3675 rtw89_phy_dig_update_para(rtwdev); 3676 } else if (dig->is_linked_pre && !is_linked) { 3677 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); 3678 rtw89_phy_dig_update_para(rtwdev); 3679 } 3680 dig->is_linked_pre = is_linked; 3681 3682 rtw89_phy_dig_igi_offset_by_env(rtwdev); 3683 rtw89_phy_dig_update_rssi_info(rtwdev); 3684 3685 dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ? 3686 dig->igi_rssi - IGI_RSSI_MIN : 0; 3687 dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX; 3688 dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst; 3689 3690 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, 3691 dig->dyn_igi_max); 3692 3693 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3694 "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n", 3695 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, 3696 dig->igi_fa_rssi); 3697 3698 rtw89_phy_dig_config_igi(rtwdev); 3699 3700 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en); 3701 3702 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) 3703 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true); 3704 else 3705 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 3706 } 3707 3708 static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta) 3709 { 3710 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3711 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3712 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 3713 struct rtw89_hal *hal = &rtwdev->hal; 3714 bool *done = data; 3715 u8 rssi_a, rssi_b; 3716 u32 candidate; 3717 3718 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || sta->tdls) 3719 return; 3720 3721 if (*done) 3722 return; 3723 3724 *done = true; 3725 3726 rssi_a = ewma_rssi_read(&rtwsta->rssi[RF_PATH_A]); 3727 rssi_b = ewma_rssi_read(&rtwsta->rssi[RF_PATH_B]); 3728 3729 if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH) 3730 candidate = RF_A; 3731 else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH) 3732 candidate = RF_B; 3733 else 3734 return; 3735 3736 if (hal->antenna_tx == candidate) 3737 return; 3738 3739 hal->antenna_tx = candidate; 3740 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta); 3741 3742 if (hal->antenna_tx == RF_A) { 3743 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12); 3744 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11); 3745 } else if (hal->antenna_tx == RF_B) { 3746 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11); 3747 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12); 3748 } 3749 } 3750 3751 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev) 3752 { 3753 struct rtw89_hal *hal = &rtwdev->hal; 3754 bool done = false; 3755 3756 if (!hal->tx_path_diversity) 3757 return; 3758 3759 ieee80211_iterate_stations_atomic(rtwdev->hw, 3760 rtw89_phy_tx_path_div_sta_iter, 3761 &done); 3762 } 3763 3764 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) 3765 { 3766 rtw89_phy_ccx_top_setting_init(rtwdev); 3767 rtw89_phy_ifs_clm_setting_init(rtwdev); 3768 } 3769 3770 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 3771 { 3772 const struct rtw89_chip_info *chip = rtwdev->chip; 3773 3774 rtw89_phy_stat_init(rtwdev); 3775 3776 rtw89_chip_bb_sethw(rtwdev); 3777 3778 rtw89_phy_env_monitor_init(rtwdev); 3779 rtw89_physts_parsing_init(rtwdev); 3780 rtw89_phy_dig_init(rtwdev); 3781 rtw89_phy_cfo_init(rtwdev); 3782 3783 rtw89_phy_init_rf_nctl(rtwdev); 3784 rtw89_chip_rfk_init(rtwdev); 3785 rtw89_load_txpwr_table(rtwdev, chip->byr_table); 3786 rtw89_chip_set_txpwr_ctrl(rtwdev); 3787 rtw89_chip_power_trim(rtwdev); 3788 rtw89_chip_cfg_txrx_path(rtwdev); 3789 } 3790 3791 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 3792 { 3793 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 3794 u8 bss_color; 3795 3796 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 3797 return; 3798 3799 bss_color = vif->bss_conf.he_bss_color.color; 3800 3801 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0, 0x1, 3802 phy_idx); 3803 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_TGT, bss_color, 3804 phy_idx); 3805 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_STAID, 3806 vif->cfg.aid, phy_idx); 3807 } 3808 3809 static void 3810 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3811 { 3812 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); 3813 } 3814 3815 static void 3816 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3817 { 3818 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 3819 } 3820 3821 static void 3822 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3823 { 3824 rtw89_phy_write32_set(rtwdev, def->addr, def->mask); 3825 } 3826 3827 static void 3828 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3829 { 3830 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); 3831 } 3832 3833 static void 3834 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3835 { 3836 udelay(def->data); 3837 } 3838 3839 static void 3840 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { 3841 [RTW89_RFK_F_WRF] = _rfk_write_rf, 3842 [RTW89_RFK_F_WM] = _rfk_write32_mask, 3843 [RTW89_RFK_F_WS] = _rfk_write32_set, 3844 [RTW89_RFK_F_WC] = _rfk_write32_clr, 3845 [RTW89_RFK_F_DELAY] = _rfk_delay, 3846 }; 3847 3848 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 3849 3850 void 3851 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) 3852 { 3853 const struct rtw89_reg5_def *p = tbl->defs; 3854 const struct rtw89_reg5_def *end = tbl->defs + tbl->size; 3855 3856 for (; p < end; p++) 3857 _rfk_handler[p->flag](rtwdev, p); 3858 } 3859 EXPORT_SYMBOL(rtw89_rfk_parser); 3860 3861 #define RTW89_TSSI_FAST_MODE_NUM 4 3862 3863 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = { 3864 {0xD934, 0xff0000}, 3865 {0xD934, 0xff000000}, 3866 {0xD938, 0xff}, 3867 {0xD934, 0xff00}, 3868 }; 3869 3870 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = { 3871 {0xD930, 0xff0000}, 3872 {0xD930, 0xff000000}, 3873 {0xD934, 0xff}, 3874 {0xD930, 0xff00}, 3875 }; 3876 3877 static 3878 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev, 3879 enum rtw89_mac_idx mac_idx, 3880 enum rtw89_tssi_bandedge_cfg bandedge_cfg, 3881 u32 val) 3882 { 3883 const struct rtw89_reg_def *regs; 3884 u32 reg; 3885 int i; 3886 3887 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 3888 regs = rtw89_tssi_fastmode_regs_flat; 3889 else 3890 regs = rtw89_tssi_fastmode_regs_level; 3891 3892 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) { 3893 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 3894 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); 3895 } 3896 } 3897 3898 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = { 3899 {0xD91C, 0xff000000}, 3900 {0xD920, 0xff}, 3901 {0xD920, 0xff00}, 3902 {0xD920, 0xff0000}, 3903 {0xD920, 0xff000000}, 3904 {0xD924, 0xff}, 3905 {0xD924, 0xff00}, 3906 {0xD914, 0xff000000}, 3907 {0xD918, 0xff}, 3908 {0xD918, 0xff00}, 3909 {0xD918, 0xff0000}, 3910 {0xD918, 0xff000000}, 3911 {0xD91C, 0xff}, 3912 {0xD91C, 0xff00}, 3913 {0xD91C, 0xff0000}, 3914 }; 3915 3916 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = { 3917 {0xD910, 0xff}, 3918 {0xD910, 0xff00}, 3919 {0xD910, 0xff0000}, 3920 {0xD910, 0xff000000}, 3921 {0xD914, 0xff}, 3922 {0xD914, 0xff00}, 3923 {0xD914, 0xff0000}, 3924 {0xD908, 0xff}, 3925 {0xD908, 0xff00}, 3926 {0xD908, 0xff0000}, 3927 {0xD908, 0xff000000}, 3928 {0xD90C, 0xff}, 3929 {0xD90C, 0xff00}, 3930 {0xD90C, 0xff0000}, 3931 {0xD90C, 0xff000000}, 3932 }; 3933 3934 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 3935 enum rtw89_mac_idx mac_idx, 3936 enum rtw89_tssi_bandedge_cfg bandedge_cfg) 3937 { 3938 const struct rtw89_chip_info *chip = rtwdev->chip; 3939 const struct rtw89_reg_def *regs; 3940 const u32 *data; 3941 u32 reg; 3942 int i; 3943 3944 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM) 3945 return; 3946 3947 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 3948 regs = rtw89_tssi_bandedge_regs_flat; 3949 else 3950 regs = rtw89_tssi_bandedge_regs_level; 3951 3952 data = chip->tssi_dbw_table->data[bandedge_cfg]; 3953 3954 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) { 3955 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 3956 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); 3957 } 3958 3959 reg = rtw89_mac_reg_by_idx(R_AX_BANDEDGE_CFG, mac_idx); 3960 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); 3961 3962 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg, 3963 data[RTW89_TSSI_SBW20]); 3964 } 3965 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg); 3966