1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "debug.h" 6 #include "fw.h" 7 #include "phy.h" 8 #include "ps.h" 9 #include "reg.h" 10 #include "sar.h" 11 #include "coex.h" 12 13 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, 14 const struct rtw89_ra_report *report) 15 { 16 const struct rate_info *txrate = &report->txrate; 17 u32 bit_rate = report->bit_rate; 18 u8 mcs; 19 20 /* lower than ofdm, do not aggregate */ 21 if (bit_rate < 550) 22 return 1; 23 24 /* prevent hardware rate fallback to G mode rate */ 25 if (txrate->flags & RATE_INFO_FLAGS_MCS) 26 mcs = txrate->mcs & 0x07; 27 else if (txrate->flags & (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_HE_MCS)) 28 mcs = txrate->mcs; 29 else 30 mcs = 0; 31 32 if (mcs <= 2) 33 return 1; 34 35 /* lower than 20M vht 2ss mcs8, make it small */ 36 if (bit_rate < 1800) 37 return 1200; 38 39 /* lower than 40M vht 2ss mcs9, make it medium */ 40 if (bit_rate < 4000) 41 return 2600; 42 43 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ 44 if (bit_rate < 7000) 45 return 3500; 46 47 return rtwdev->chip->max_amsdu_limit; 48 } 49 50 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) 51 { 52 u64 ra_mask = 0; 53 u8 mcs_cap; 54 int i, nss; 55 56 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { 57 mcs_cap = mcs_map & 0x3; 58 switch (mcs_cap) { 59 case 2: 60 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; 61 break; 62 case 1: 63 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; 64 break; 65 case 0: 66 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; 67 break; 68 default: 69 break; 70 } 71 } 72 73 return ra_mask; 74 } 75 76 static u64 get_he_ra_mask(struct ieee80211_sta *sta) 77 { 78 struct ieee80211_sta_he_cap cap = sta->he_cap; 79 u16 mcs_map; 80 81 switch (sta->bandwidth) { 82 case IEEE80211_STA_RX_BW_160: 83 if (cap.he_cap_elem.phy_cap_info[0] & 84 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) 85 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); 86 else 87 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); 88 break; 89 default: 90 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); 91 } 92 93 /* MCS11, MCS9, MCS7 */ 94 return get_mcs_ra_mask(mcs_map, 11, 2); 95 } 96 97 #define RA_FLOOR_TABLE_SIZE 7 98 #define RA_FLOOR_UP_GAP 3 99 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, 100 u8 ratr_state) 101 { 102 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; 103 u8 rssi_lv = 0; 104 u8 i; 105 106 rssi >>= 1; 107 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 108 if (i >= ratr_state) 109 rssi_lv_t[i] += RA_FLOOR_UP_GAP; 110 if (rssi < rssi_lv_t[i]) { 111 rssi_lv = i; 112 break; 113 } 114 } 115 if (rssi_lv == 0) 116 return 0xffffffffffffffffULL; 117 else if (rssi_lv == 1) 118 return 0xfffffffffffffff0ULL; 119 else if (rssi_lv == 2) 120 return 0xffffffffffffffe0ULL; 121 else if (rssi_lv == 3) 122 return 0xffffffffffffffc0ULL; 123 else if (rssi_lv == 4) 124 return 0xffffffffffffff80ULL; 125 else if (rssi_lv >= 5) 126 return 0xffffffffffffff00ULL; 127 128 return 0xffffffffffffffffULL; 129 } 130 131 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 132 { 133 struct rtw89_hal *hal = &rtwdev->hal; 134 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 135 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 136 enum nl80211_band band; 137 u64 cfg_mask; 138 139 if (!rtwsta->use_cfg_mask) 140 return -1; 141 142 switch (hal->current_band_type) { 143 case RTW89_BAND_2G: 144 band = NL80211_BAND_2GHZ; 145 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, 146 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); 147 break; 148 case RTW89_BAND_5G: 149 band = NL80211_BAND_5GHZ; 150 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, 151 RA_MASK_OFDM_RATES); 152 break; 153 default: 154 rtw89_warn(rtwdev, "unhandled band type %d\n", hal->current_band_type); 155 return -1; 156 } 157 158 if (sta->he_cap.has_he) { 159 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], 160 RA_MASK_HE_1SS_RATES); 161 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], 162 RA_MASK_HE_2SS_RATES); 163 } else if (sta->vht_cap.vht_supported) { 164 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 165 RA_MASK_VHT_1SS_RATES); 166 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 167 RA_MASK_VHT_2SS_RATES); 168 } else if (sta->ht_cap.ht_supported) { 169 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 170 RA_MASK_HT_1SS_RATES); 171 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 172 RA_MASK_HT_2SS_RATES); 173 } 174 175 return cfg_mask; 176 } 177 178 static const u64 179 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, 180 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; 181 static const u64 182 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 183 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; 184 static const u64 185 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, 186 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; 187 188 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 189 struct ieee80211_sta *sta, bool csi) 190 { 191 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 192 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 193 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 194 struct rtw89_ra_info *ra = &rtwsta->ra; 195 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; 196 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 197 u64 high_rate_mask = 0; 198 u64 ra_mask = 0; 199 u8 mode = 0; 200 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; 201 u8 bw_mode = 0; 202 u8 stbc_en = 0; 203 u8 ldpc_en = 0; 204 u8 i; 205 bool sgi = false; 206 207 memset(ra, 0, sizeof(*ra)); 208 /* Set the ra mask from sta's capability */ 209 if (sta->he_cap.has_he) { 210 mode |= RTW89_RA_MODE_HE; 211 csi_mode = RTW89_RA_RPT_MODE_HE; 212 ra_mask |= get_he_ra_mask(sta); 213 high_rate_masks = rtw89_ra_mask_he_rates; 214 if (sta->he_cap.he_cap_elem.phy_cap_info[2] & 215 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) 216 stbc_en = 1; 217 if (sta->he_cap.he_cap_elem.phy_cap_info[1] & 218 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) 219 ldpc_en = 1; 220 } else if (sta->vht_cap.vht_supported) { 221 u16 mcs_map = le16_to_cpu(sta->vht_cap.vht_mcs.rx_mcs_map); 222 223 mode |= RTW89_RA_MODE_VHT; 224 csi_mode = RTW89_RA_RPT_MODE_VHT; 225 /* MCS9, MCS8, MCS7 */ 226 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); 227 high_rate_masks = rtw89_ra_mask_vht_rates; 228 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 229 stbc_en = 1; 230 if (sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 231 ldpc_en = 1; 232 } else if (sta->ht_cap.ht_supported) { 233 mode |= RTW89_RA_MODE_HT; 234 csi_mode = RTW89_RA_RPT_MODE_HT; 235 ra_mask |= ((u64)sta->ht_cap.mcs.rx_mask[3] << 48) | 236 ((u64)sta->ht_cap.mcs.rx_mask[2] << 36) | 237 (sta->ht_cap.mcs.rx_mask[1] << 24) | 238 (sta->ht_cap.mcs.rx_mask[0] << 12); 239 high_rate_masks = rtw89_ra_mask_ht_rates; 240 if (sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 241 stbc_en = 1; 242 if (sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 243 ldpc_en = 1; 244 } 245 246 if (rtwdev->hal.current_band_type == RTW89_BAND_2G) { 247 if (sta->supp_rates[NL80211_BAND_2GHZ] <= 0xf) 248 mode |= RTW89_RA_MODE_CCK; 249 else 250 mode |= RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM; 251 } else { 252 mode |= RTW89_RA_MODE_OFDM; 253 } 254 255 if (mode >= RTW89_RA_MODE_HT) { 256 for (i = 0; i < rtwdev->hal.tx_nss; i++) 257 high_rate_mask |= high_rate_masks[i]; 258 ra_mask &= high_rate_mask; 259 if (mode & RTW89_RA_MODE_OFDM) 260 ra_mask |= RA_MASK_SUBOFDM_RATES; 261 if (mode & RTW89_RA_MODE_CCK) 262 ra_mask |= RA_MASK_SUBCCK_RATES; 263 } else if (mode & RTW89_RA_MODE_OFDM) { 264 if (mode & RTW89_RA_MODE_CCK) 265 ra_mask |= RA_MASK_SUBCCK_RATES; 266 ra_mask |= RA_MASK_OFDM_RATES; 267 } else { 268 ra_mask = RA_MASK_CCK_RATES; 269 } 270 271 if (mode != RTW89_RA_MODE_CCK) { 272 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); 273 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 274 } 275 276 switch (sta->bandwidth) { 277 case IEEE80211_STA_RX_BW_80: 278 bw_mode = RTW89_CHANNEL_WIDTH_80; 279 sgi = sta->vht_cap.vht_supported && 280 (sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 281 break; 282 case IEEE80211_STA_RX_BW_40: 283 bw_mode = RTW89_CHANNEL_WIDTH_40; 284 sgi = sta->ht_cap.ht_supported && 285 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 286 break; 287 default: 288 bw_mode = RTW89_CHANNEL_WIDTH_20; 289 sgi = sta->ht_cap.ht_supported && 290 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 291 break; 292 } 293 294 if (sta->he_cap.he_cap_elem.phy_cap_info[3] & 295 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) 296 ra->dcm_cap = 1; 297 298 if (rate_pattern->enable) { 299 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 300 ra_mask &= rate_pattern->ra_mask; 301 mode = rate_pattern->ra_mode; 302 } 303 304 ra->bw_cap = bw_mode; 305 ra->mode_ctrl = mode; 306 ra->macid = rtwsta->mac_id; 307 ra->stbc_cap = stbc_en; 308 ra->ldpc_cap = ldpc_en; 309 ra->ss_num = min(sta->rx_nss, rtwdev->hal.tx_nss) - 1; 310 ra->en_sgi = sgi; 311 ra->ra_mask = ra_mask; 312 313 if (!csi) 314 return; 315 316 ra->fixed_csi_rate_en = false; 317 ra->ra_csi_rate_en = true; 318 ra->cr_tbl_sel = false; 319 ra->band_num = rtwvif->phy_idx; 320 ra->csi_bw = bw_mode; 321 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; 322 ra->csi_mcs_ss_idx = 5; 323 ra->csi_mode = csi_mode; 324 } 325 326 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) 327 { 328 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 329 struct rtw89_ra_info *ra = &rtwsta->ra; 330 331 rtw89_phy_ra_sta_update(rtwdev, sta, false); 332 ra->upd_mask = 1; 333 rtw89_debug(rtwdev, RTW89_DBG_RA, 334 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", 335 ra->macid, 336 ra->bw_cap, 337 ra->ss_num, 338 ra->en_sgi, 339 ra->giltf); 340 341 rtw89_fw_h2c_ra(rtwdev, ra, false); 342 } 343 344 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, 345 u16 rate_base, u64 ra_mask, u8 ra_mode, 346 u32 rate_ctrl, u32 ctrl_skip, bool force) 347 { 348 u8 n, c; 349 350 if (rate_ctrl == ctrl_skip) 351 return true; 352 353 n = hweight32(rate_ctrl); 354 if (n == 0) 355 return true; 356 357 if (force && n != 1) 358 return false; 359 360 if (next->enable) 361 return false; 362 363 c = __fls(rate_ctrl); 364 next->rate = rate_base + c; 365 next->ra_mode = ra_mode; 366 next->ra_mask = ra_mask; 367 next->enable = true; 368 369 return true; 370 } 371 372 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 373 struct ieee80211_vif *vif, 374 const struct cfg80211_bitrate_mask *mask) 375 { 376 struct ieee80211_supported_band *sband; 377 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 378 struct rtw89_phy_rate_pattern next_pattern = {0}; 379 static const u16 hw_rate_he[] = {RTW89_HW_RATE_HE_NSS1_MCS0, 380 RTW89_HW_RATE_HE_NSS2_MCS0, 381 RTW89_HW_RATE_HE_NSS3_MCS0, 382 RTW89_HW_RATE_HE_NSS4_MCS0}; 383 static const u16 hw_rate_vht[] = {RTW89_HW_RATE_VHT_NSS1_MCS0, 384 RTW89_HW_RATE_VHT_NSS2_MCS0, 385 RTW89_HW_RATE_VHT_NSS3_MCS0, 386 RTW89_HW_RATE_VHT_NSS4_MCS0}; 387 static const u16 hw_rate_ht[] = {RTW89_HW_RATE_MCS0, 388 RTW89_HW_RATE_MCS8, 389 RTW89_HW_RATE_MCS16, 390 RTW89_HW_RATE_MCS24}; 391 u8 band = rtwdev->hal.current_band_type; 392 u8 tx_nss = rtwdev->hal.tx_nss; 393 u8 i; 394 395 for (i = 0; i < tx_nss; i++) 396 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i], 397 RA_MASK_HE_RATES, RTW89_RA_MODE_HE, 398 mask->control[band].he_mcs[i], 399 0, true)) 400 goto out; 401 402 for (i = 0; i < tx_nss; i++) 403 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i], 404 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, 405 mask->control[band].vht_mcs[i], 406 0, true)) 407 goto out; 408 409 for (i = 0; i < tx_nss; i++) 410 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i], 411 RA_MASK_HT_RATES, RTW89_RA_MODE_HT, 412 mask->control[band].ht_mcs[i], 413 0, true)) 414 goto out; 415 416 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and 417 * require at least one basic rate for ieee80211_set_bitrate_mask, 418 * so the decision just depends on if all bitrates are set or not. 419 */ 420 sband = rtwdev->hw->wiphy->bands[band]; 421 if (band == RTW89_BAND_2G) { 422 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, 423 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, 424 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, 425 mask->control[band].legacy, 426 BIT(sband->n_bitrates) - 1, false)) 427 goto out; 428 } else { 429 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, 430 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, 431 mask->control[band].legacy, 432 BIT(sband->n_bitrates) - 1, false)) 433 goto out; 434 } 435 436 if (!next_pattern.enable) 437 goto out; 438 439 rtwvif->rate_pattern = next_pattern; 440 rtw89_debug(rtwdev, RTW89_DBG_RA, 441 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", 442 next_pattern.rate, 443 next_pattern.ra_mask, 444 next_pattern.ra_mode); 445 return; 446 447 out: 448 rtwvif->rate_pattern.enable = false; 449 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); 450 } 451 452 static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta) 453 { 454 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; 455 456 rtw89_phy_ra_updata_sta(rtwdev, sta); 457 } 458 459 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) 460 { 461 ieee80211_iterate_stations_atomic(rtwdev->hw, 462 rtw89_phy_ra_updata_sta_iter, 463 rtwdev); 464 } 465 466 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) 467 { 468 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 469 struct rtw89_ra_info *ra = &rtwsta->ra; 470 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; 471 bool csi = rtw89_sta_has_beamformer_cap(sta); 472 473 rtw89_phy_ra_sta_update(rtwdev, sta, csi); 474 475 if (rssi > 40) 476 ra->init_rate_lv = 1; 477 else if (rssi > 20) 478 ra->init_rate_lv = 2; 479 else if (rssi > 1) 480 ra->init_rate_lv = 3; 481 else 482 ra->init_rate_lv = 0; 483 ra->upd_all = 1; 484 rtw89_debug(rtwdev, RTW89_DBG_RA, 485 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", 486 ra->macid, 487 ra->mode_ctrl, 488 ra->bw_cap, 489 ra->ss_num, 490 ra->init_rate_lv); 491 rtw89_debug(rtwdev, RTW89_DBG_RA, 492 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", 493 ra->dcm_cap, 494 ra->er_cap, 495 ra->ldpc_cap, 496 ra->stbc_cap, 497 ra->en_sgi, 498 ra->giltf); 499 500 rtw89_fw_h2c_ra(rtwdev, ra, csi); 501 } 502 503 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 504 struct rtw89_channel_params *param, 505 enum rtw89_bandwidth dbw) 506 { 507 enum rtw89_bandwidth cbw = param->bandwidth; 508 u8 pri_ch = param->primary_chan; 509 u8 central_ch = param->center_chan; 510 u8 txsc_idx = 0; 511 u8 tmp = 0; 512 513 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 514 return txsc_idx; 515 516 switch (cbw) { 517 case RTW89_CHANNEL_WIDTH_40: 518 txsc_idx = pri_ch > central_ch ? 1 : 2; 519 break; 520 case RTW89_CHANNEL_WIDTH_80: 521 if (dbw == RTW89_CHANNEL_WIDTH_20) { 522 if (pri_ch > central_ch) 523 txsc_idx = (pri_ch - central_ch) >> 1; 524 else 525 txsc_idx = ((central_ch - pri_ch) >> 1) + 1; 526 } else { 527 txsc_idx = pri_ch > central_ch ? 9 : 10; 528 } 529 break; 530 case RTW89_CHANNEL_WIDTH_160: 531 if (pri_ch > central_ch) 532 tmp = (pri_ch - central_ch) >> 1; 533 else 534 tmp = ((central_ch - pri_ch) >> 1) + 1; 535 536 if (dbw == RTW89_CHANNEL_WIDTH_20) { 537 txsc_idx = tmp; 538 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 539 if (tmp == 1 || tmp == 3) 540 txsc_idx = 9; 541 else if (tmp == 5 || tmp == 7) 542 txsc_idx = 11; 543 else if (tmp == 2 || tmp == 4) 544 txsc_idx = 10; 545 else if (tmp == 6 || tmp == 8) 546 txsc_idx = 12; 547 else 548 return 0xff; 549 } else { 550 txsc_idx = pri_ch > central_ch ? 13 : 14; 551 } 552 break; 553 case RTW89_CHANNEL_WIDTH_80_80: 554 if (dbw == RTW89_CHANNEL_WIDTH_20) { 555 if (pri_ch > central_ch) 556 txsc_idx = (10 - (pri_ch - central_ch)) >> 1; 557 else 558 txsc_idx = ((central_ch - pri_ch) >> 1) + 5; 559 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 560 txsc_idx = pri_ch > central_ch ? 10 : 12; 561 } else { 562 txsc_idx = 14; 563 } 564 break; 565 default: 566 break; 567 } 568 569 return txsc_idx; 570 } 571 572 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 573 u32 addr, u32 mask) 574 { 575 const struct rtw89_chip_info *chip = rtwdev->chip; 576 const u32 *base_addr = chip->rf_base_addr; 577 u32 val, direct_addr; 578 579 if (rf_path >= rtwdev->chip->rf_path_num) { 580 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 581 return INV_RF_DATA; 582 } 583 584 addr &= 0xff; 585 direct_addr = base_addr[rf_path] + (addr << 2); 586 mask &= RFREG_MASK; 587 588 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); 589 590 return val; 591 } 592 EXPORT_SYMBOL(rtw89_phy_read_rf); 593 594 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 595 u32 addr, u32 mask, u32 data) 596 { 597 const struct rtw89_chip_info *chip = rtwdev->chip; 598 const u32 *base_addr = chip->rf_base_addr; 599 u32 direct_addr; 600 601 if (rf_path >= rtwdev->chip->rf_path_num) { 602 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 603 return false; 604 } 605 606 addr &= 0xff; 607 direct_addr = base_addr[rf_path] + (addr << 2); 608 mask &= RFREG_MASK; 609 610 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); 611 612 /* delay to ensure writing properly */ 613 udelay(1); 614 615 return true; 616 } 617 EXPORT_SYMBOL(rtw89_phy_write_rf); 618 619 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, 620 enum rtw89_phy_idx phy_idx) 621 { 622 const struct rtw89_chip_info *chip = rtwdev->chip; 623 624 chip->ops->bb_reset(rtwdev, phy_idx); 625 } 626 627 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, 628 const struct rtw89_reg2_def *reg, 629 enum rtw89_rf_path rf_path, 630 void *extra_data) 631 { 632 if (reg->addr == 0xfe) 633 mdelay(50); 634 else if (reg->addr == 0xfd) 635 mdelay(5); 636 else if (reg->addr == 0xfc) 637 mdelay(1); 638 else if (reg->addr == 0xfb) 639 udelay(50); 640 else if (reg->addr == 0xfa) 641 udelay(5); 642 else if (reg->addr == 0xf9) 643 udelay(1); 644 else 645 rtw89_phy_write32(rtwdev, reg->addr, reg->data); 646 } 647 648 static void 649 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, 650 const struct rtw89_reg2_def *reg, 651 enum rtw89_rf_path rf_path, 652 struct rtw89_fw_h2c_rf_reg_info *info) 653 { 654 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; 655 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 656 657 info->rtw89_phy_config_rf_h2c[page][idx] = 658 cpu_to_le32((reg->addr << 20) | reg->data); 659 info->curr_idx++; 660 } 661 662 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, 663 struct rtw89_fw_h2c_rf_reg_info *info) 664 { 665 u16 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 666 u16 len = (info->curr_idx % RTW89_H2C_RF_PAGE_SIZE) * 4; 667 u8 i; 668 int ret = 0; 669 670 if (page > RTW89_H2C_RF_PAGE_NUM) { 671 rtw89_warn(rtwdev, 672 "rf reg h2c total page num %d larger than %d (RTW89_H2C_RF_PAGE_NUM)\n", 673 page, RTW89_H2C_RF_PAGE_NUM); 674 return -EINVAL; 675 } 676 677 for (i = 0; i < page; i++) { 678 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, 679 RTW89_H2C_RF_PAGE_SIZE * 4, i); 680 if (ret) 681 return ret; 682 } 683 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len, i); 684 if (ret) 685 return ret; 686 info->curr_idx = 0; 687 688 return 0; 689 } 690 691 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, 692 const struct rtw89_reg2_def *reg, 693 enum rtw89_rf_path rf_path, 694 void *extra_data) 695 { 696 if (reg->addr == 0xfe) { 697 mdelay(50); 698 } else if (reg->addr == 0xfd) { 699 mdelay(5); 700 } else if (reg->addr == 0xfc) { 701 mdelay(1); 702 } else if (reg->addr == 0xfb) { 703 udelay(50); 704 } else if (reg->addr == 0xfa) { 705 udelay(5); 706 } else if (reg->addr == 0xf9) { 707 udelay(1); 708 } else { 709 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); 710 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 711 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 712 } 713 } 714 715 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, 716 const struct rtw89_phy_table *table, 717 u32 *headline_size, u32 *headline_idx, 718 u8 rfe, u8 cv) 719 { 720 const struct rtw89_reg2_def *reg; 721 u32 headline; 722 u32 compare, target; 723 u8 rfe_para, cv_para; 724 u8 cv_max = 0; 725 bool case_matched = false; 726 u32 i; 727 728 for (i = 0; i < table->n_regs; i++) { 729 reg = &table->regs[i]; 730 headline = get_phy_headline(reg->addr); 731 if (headline != PHY_HEADLINE_VALID) 732 break; 733 } 734 *headline_size = i; 735 if (*headline_size == 0) 736 return 0; 737 738 /* case 1: RFE match, CV match */ 739 compare = get_phy_compare(rfe, cv); 740 for (i = 0; i < *headline_size; i++) { 741 reg = &table->regs[i]; 742 target = get_phy_target(reg->addr); 743 if (target == compare) { 744 *headline_idx = i; 745 return 0; 746 } 747 } 748 749 /* case 2: RFE match, CV don't care */ 750 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); 751 for (i = 0; i < *headline_size; i++) { 752 reg = &table->regs[i]; 753 target = get_phy_target(reg->addr); 754 if (target == compare) { 755 *headline_idx = i; 756 return 0; 757 } 758 } 759 760 /* case 3: RFE match, CV max in table */ 761 for (i = 0; i < *headline_size; i++) { 762 reg = &table->regs[i]; 763 rfe_para = get_phy_cond_rfe(reg->addr); 764 cv_para = get_phy_cond_cv(reg->addr); 765 if (rfe_para == rfe) { 766 if (cv_para >= cv_max) { 767 cv_max = cv_para; 768 *headline_idx = i; 769 case_matched = true; 770 } 771 } 772 } 773 774 if (case_matched) 775 return 0; 776 777 /* case 4: RFE don't care, CV max in table */ 778 for (i = 0; i < *headline_size; i++) { 779 reg = &table->regs[i]; 780 rfe_para = get_phy_cond_rfe(reg->addr); 781 cv_para = get_phy_cond_cv(reg->addr); 782 if (rfe_para == PHY_COND_DONT_CARE) { 783 if (cv_para >= cv_max) { 784 cv_max = cv_para; 785 *headline_idx = i; 786 case_matched = true; 787 } 788 } 789 } 790 791 if (case_matched) 792 return 0; 793 794 return -EINVAL; 795 } 796 797 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, 798 const struct rtw89_phy_table *table, 799 void (*config)(struct rtw89_dev *rtwdev, 800 const struct rtw89_reg2_def *reg, 801 enum rtw89_rf_path rf_path, 802 void *data), 803 void *extra_data) 804 { 805 const struct rtw89_reg2_def *reg; 806 enum rtw89_rf_path rf_path = table->rf_path; 807 u8 rfe = rtwdev->efuse.rfe_type; 808 u8 cv = rtwdev->hal.cv; 809 u32 i; 810 u32 headline_size = 0, headline_idx = 0; 811 u32 target = 0, cfg_target; 812 u8 cond; 813 bool is_matched = true; 814 bool target_found = false; 815 int ret; 816 817 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, 818 &headline_idx, rfe, cv); 819 if (ret) { 820 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); 821 return; 822 } 823 824 cfg_target = get_phy_target(table->regs[headline_idx].addr); 825 for (i = headline_size; i < table->n_regs; i++) { 826 reg = &table->regs[i]; 827 cond = get_phy_cond(reg->addr); 828 switch (cond) { 829 case PHY_COND_BRANCH_IF: 830 case PHY_COND_BRANCH_ELIF: 831 target = get_phy_target(reg->addr); 832 break; 833 case PHY_COND_BRANCH_ELSE: 834 is_matched = false; 835 if (!target_found) { 836 rtw89_warn(rtwdev, "failed to load CR %x/%x\n", 837 reg->addr, reg->data); 838 return; 839 } 840 break; 841 case PHY_COND_BRANCH_END: 842 is_matched = true; 843 target_found = false; 844 break; 845 case PHY_COND_CHECK: 846 if (target_found) { 847 is_matched = false; 848 break; 849 } 850 851 if (target == cfg_target) { 852 is_matched = true; 853 target_found = true; 854 } else { 855 is_matched = false; 856 target_found = false; 857 } 858 break; 859 default: 860 if (is_matched) 861 config(rtwdev, reg, rf_path, extra_data); 862 break; 863 } 864 } 865 } 866 867 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) 868 { 869 const struct rtw89_chip_info *chip = rtwdev->chip; 870 const struct rtw89_phy_table *bb_table = chip->bb_table; 871 872 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); 873 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 874 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); 875 } 876 877 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 878 { 879 rtw89_phy_write32(rtwdev, 0x8080, 0x4); 880 udelay(1); 881 return rtw89_phy_read32(rtwdev, 0x8080); 882 } 883 884 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev) 885 { 886 const struct rtw89_chip_info *chip = rtwdev->chip; 887 const struct rtw89_phy_table *rf_table; 888 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; 889 u8 path; 890 891 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); 892 if (!rf_reg_info) 893 return; 894 895 for (path = RF_PATH_A; path < chip->rf_path_num; path++) { 896 rf_reg_info->rf_path = path; 897 rf_table = chip->rf_table[path]; 898 rtw89_phy_init_reg(rtwdev, rf_table, rtw89_phy_config_rf_reg, 899 (void *)rf_reg_info); 900 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) 901 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", 902 path); 903 } 904 kfree(rf_reg_info); 905 } 906 907 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) 908 { 909 const struct rtw89_chip_info *chip = rtwdev->chip; 910 const struct rtw89_phy_table *nctl_table; 911 u32 val; 912 int ret; 913 914 /* IQK/DPK clock & reset */ 915 rtw89_phy_write32_set(rtwdev, 0x0c60, 0x3); 916 rtw89_phy_write32_set(rtwdev, 0x0c6c, 0x1); 917 rtw89_phy_write32_set(rtwdev, 0x58ac, 0x8000000); 918 rtw89_phy_write32_set(rtwdev, 0x78ac, 0x8000000); 919 920 /* check 0x8080 */ 921 rtw89_phy_write32(rtwdev, 0x8000, 0x8); 922 923 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, 924 1000, false, rtwdev); 925 if (ret) 926 rtw89_err(rtwdev, "failed to poll nctl block\n"); 927 928 nctl_table = chip->nctl_table; 929 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); 930 } 931 932 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) 933 { 934 u32 phy_page = addr >> 8; 935 u32 ofst = 0; 936 937 switch (phy_page) { 938 case 0x6: 939 case 0x7: 940 case 0x8: 941 case 0x9: 942 case 0xa: 943 case 0xb: 944 case 0xc: 945 case 0xd: 946 case 0x19: 947 case 0x1a: 948 case 0x1b: 949 ofst = 0x2000; 950 break; 951 default: 952 /* warning case */ 953 ofst = 0; 954 break; 955 } 956 957 if (phy_page >= 0x40 && phy_page <= 0x4f) 958 ofst = 0x2000; 959 960 return ofst; 961 } 962 963 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 964 u32 data, enum rtw89_phy_idx phy_idx) 965 { 966 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 967 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 968 rtw89_phy_write32_mask(rtwdev, addr, mask, data); 969 } 970 971 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 972 u32 val) 973 { 974 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 975 976 if (!rtwdev->dbcc_en) 977 return; 978 979 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 980 } 981 982 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 983 const struct rtw89_phy_reg3_tbl *tbl) 984 { 985 const struct rtw89_reg3_def *reg3; 986 int i; 987 988 for (i = 0; i < tbl->size; i++) { 989 reg3 = &tbl->reg3[i]; 990 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); 991 } 992 } 993 994 const u8 rtw89_rs_idx_max[] = { 995 [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX, 996 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX, 997 [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX, 998 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX, 999 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX, 1000 }; 1001 1002 const u8 rtw89_rs_nss_max[] = { 1003 [RTW89_RS_CCK] = 1, 1004 [RTW89_RS_OFDM] = 1, 1005 [RTW89_RS_MCS] = RTW89_NSS_MAX, 1006 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX, 1007 [RTW89_RS_OFFSET] = 1, 1008 }; 1009 1010 static const u8 _byr_of_rs[] = { 1011 [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck), 1012 [RTW89_RS_OFDM] = offsetof(struct rtw89_txpwr_byrate, ofdm), 1013 [RTW89_RS_MCS] = offsetof(struct rtw89_txpwr_byrate, mcs), 1014 [RTW89_RS_HEDCM] = offsetof(struct rtw89_txpwr_byrate, hedcm), 1015 [RTW89_RS_OFFSET] = offsetof(struct rtw89_txpwr_byrate, offset), 1016 }; 1017 1018 #define _byr_seek(rs, raw) ((s8 *)(raw) + _byr_of_rs[rs]) 1019 #define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_max[rs] + (idx)) 1020 #define _byr_chk(rs, nss, idx) \ 1021 ((nss) < rtw89_rs_nss_max[rs] && (idx) < rtw89_rs_idx_max[rs]) 1022 1023 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 1024 const struct rtw89_txpwr_table *tbl) 1025 { 1026 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; 1027 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; 1028 s8 *byr; 1029 u32 data; 1030 u8 i, idx; 1031 1032 for (; cfg < end; cfg++) { 1033 byr = _byr_seek(cfg->rs, &rtwdev->byr[cfg->band]); 1034 data = cfg->data; 1035 1036 for (i = 0; i < cfg->len; i++, data >>= 8) { 1037 idx = _byr_idx(cfg->rs, cfg->nss, (cfg->shf + i)); 1038 byr[idx] = (s8)(data & 0xff); 1039 } 1040 } 1041 } 1042 1043 #define _phy_txpwr_rf_to_mac(rtwdev, txpwr_rf) \ 1044 ({ \ 1045 const struct rtw89_chip_info *__c = (rtwdev)->chip; \ 1046 (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \ 1047 }) 1048 1049 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, 1050 const struct rtw89_rate_desc *rate_desc) 1051 { 1052 enum rtw89_band band = rtwdev->hal.current_band_type; 1053 s8 *byr; 1054 u8 idx; 1055 1056 if (rate_desc->rs == RTW89_RS_CCK) 1057 band = RTW89_BAND_2G; 1058 1059 if (!_byr_chk(rate_desc->rs, rate_desc->nss, rate_desc->idx)) { 1060 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1061 "[TXPWR] unknown byrate desc rs=%d nss=%d idx=%d\n", 1062 rate_desc->rs, rate_desc->nss, rate_desc->idx); 1063 1064 return 0; 1065 } 1066 1067 byr = _byr_seek(rate_desc->rs, &rtwdev->byr[band]); 1068 idx = _byr_idx(rate_desc->rs, rate_desc->nss, rate_desc->idx); 1069 1070 return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]); 1071 } 1072 1073 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 channel) 1074 { 1075 switch (channel) { 1076 case 1 ... 14: 1077 return channel - 1; 1078 case 36 ... 64: 1079 return (channel - 36) / 2; 1080 case 100 ... 144: 1081 return ((channel - 100) / 2) + 15; 1082 case 149 ... 177: 1083 return ((channel - 149) / 2) + 38; 1084 default: 1085 rtw89_warn(rtwdev, "unknown channel: %d\n", channel); 1086 return 0; 1087 } 1088 } 1089 1090 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, 1091 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) 1092 { 1093 const struct rtw89_chip_info *chip = rtwdev->chip; 1094 u8 ch_idx = rtw89_channel_to_idx(rtwdev, ch); 1095 u8 band = rtwdev->hal.current_band_type; 1096 u8 regd = rtw89_regd_get(rtwdev, band); 1097 s8 lmt = 0, sar; 1098 1099 switch (band) { 1100 case RTW89_BAND_2G: 1101 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf][regd][ch_idx]; 1102 break; 1103 case RTW89_BAND_5G: 1104 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf][regd][ch_idx]; 1105 break; 1106 default: 1107 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1108 return 0; 1109 } 1110 1111 lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt); 1112 sar = rtw89_query_sar(rtwdev); 1113 1114 return min(lmt, sar); 1115 } 1116 1117 #define __fill_txpwr_limit_nonbf_bf(ptr, bw, ntx, rs, ch) \ 1118 do { \ 1119 u8 __i; \ 1120 for (__i = 0; __i < RTW89_BF_NUM; __i++) \ 1121 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ 1122 bw, ntx, \ 1123 rs, __i, \ 1124 (ch)); \ 1125 } while (0) 1126 1127 static void rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev *rtwdev, 1128 struct rtw89_txpwr_limit *lmt, 1129 u8 ntx, u8 ch) 1130 { 1131 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, RTW89_CHANNEL_WIDTH_20, 1132 ntx, RTW89_RS_CCK, ch); 1133 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, RTW89_CHANNEL_WIDTH_40, 1134 ntx, RTW89_RS_CCK, ch); 1135 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, 1136 ntx, RTW89_RS_OFDM, ch); 1137 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, 1138 ntx, RTW89_RS_MCS, ch); 1139 } 1140 1141 static void rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev *rtwdev, 1142 struct rtw89_txpwr_limit *lmt, 1143 u8 ntx, u8 ch) 1144 { 1145 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, RTW89_CHANNEL_WIDTH_20, 1146 ntx, RTW89_RS_CCK, ch - 2); 1147 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, RTW89_CHANNEL_WIDTH_40, 1148 ntx, RTW89_RS_CCK, ch); 1149 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, 1150 ntx, RTW89_RS_OFDM, ch - 2); 1151 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, 1152 ntx, RTW89_RS_MCS, ch - 2); 1153 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], RTW89_CHANNEL_WIDTH_20, 1154 ntx, RTW89_RS_MCS, ch + 2); 1155 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], RTW89_CHANNEL_WIDTH_40, 1156 ntx, RTW89_RS_MCS, ch); 1157 } 1158 1159 static void rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev *rtwdev, 1160 struct rtw89_txpwr_limit *lmt, 1161 u8 ntx, u8 ch) 1162 { 1163 s8 val_0p5_n[RTW89_BF_NUM]; 1164 s8 val_0p5_p[RTW89_BF_NUM]; 1165 u8 i; 1166 1167 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, 1168 ntx, RTW89_RS_OFDM, ch - 6); 1169 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, 1170 ntx, RTW89_RS_MCS, ch - 6); 1171 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], RTW89_CHANNEL_WIDTH_20, 1172 ntx, RTW89_RS_MCS, ch - 2); 1173 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], RTW89_CHANNEL_WIDTH_20, 1174 ntx, RTW89_RS_MCS, ch + 2); 1175 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], RTW89_CHANNEL_WIDTH_20, 1176 ntx, RTW89_RS_MCS, ch + 6); 1177 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], RTW89_CHANNEL_WIDTH_40, 1178 ntx, RTW89_RS_MCS, ch - 4); 1179 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], RTW89_CHANNEL_WIDTH_40, 1180 ntx, RTW89_RS_MCS, ch + 4); 1181 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], RTW89_CHANNEL_WIDTH_80, 1182 ntx, RTW89_RS_MCS, ch); 1183 1184 __fill_txpwr_limit_nonbf_bf(val_0p5_n, RTW89_CHANNEL_WIDTH_40, 1185 ntx, RTW89_RS_MCS, ch - 4); 1186 __fill_txpwr_limit_nonbf_bf(val_0p5_p, RTW89_CHANNEL_WIDTH_40, 1187 ntx, RTW89_RS_MCS, ch + 4); 1188 1189 for (i = 0; i < RTW89_BF_NUM; i++) 1190 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1191 } 1192 1193 void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev, 1194 struct rtw89_txpwr_limit *lmt, 1195 u8 ntx) 1196 { 1197 u8 ch = rtwdev->hal.current_channel; 1198 u8 bw = rtwdev->hal.current_band_width; 1199 1200 memset(lmt, 0, sizeof(*lmt)); 1201 1202 switch (bw) { 1203 case RTW89_CHANNEL_WIDTH_20: 1204 rtw89_phy_fill_txpwr_limit_20m(rtwdev, lmt, ntx, ch); 1205 break; 1206 case RTW89_CHANNEL_WIDTH_40: 1207 rtw89_phy_fill_txpwr_limit_40m(rtwdev, lmt, ntx, ch); 1208 break; 1209 case RTW89_CHANNEL_WIDTH_80: 1210 rtw89_phy_fill_txpwr_limit_80m(rtwdev, lmt, ntx, ch); 1211 break; 1212 } 1213 } 1214 1215 static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, 1216 u8 ru, u8 ntx, u8 ch) 1217 { 1218 const struct rtw89_chip_info *chip = rtwdev->chip; 1219 u8 ch_idx = rtw89_channel_to_idx(rtwdev, ch); 1220 u8 band = rtwdev->hal.current_band_type; 1221 u8 regd = rtw89_regd_get(rtwdev, band); 1222 s8 lmt_ru = 0, sar; 1223 1224 switch (band) { 1225 case RTW89_BAND_2G: 1226 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx][regd][ch_idx]; 1227 break; 1228 case RTW89_BAND_5G: 1229 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx][regd][ch_idx]; 1230 break; 1231 default: 1232 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1233 return 0; 1234 } 1235 1236 lmt_ru = _phy_txpwr_rf_to_mac(rtwdev, lmt_ru); 1237 sar = rtw89_query_sar(rtwdev); 1238 1239 return min(lmt_ru, sar); 1240 } 1241 1242 static void 1243 rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev, 1244 struct rtw89_txpwr_limit_ru *lmt_ru, 1245 u8 ntx, u8 ch) 1246 { 1247 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1248 ntx, ch); 1249 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1250 ntx, ch); 1251 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1252 ntx, ch); 1253 } 1254 1255 static void 1256 rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev, 1257 struct rtw89_txpwr_limit_ru *lmt_ru, 1258 u8 ntx, u8 ch) 1259 { 1260 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1261 ntx, ch - 2); 1262 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1263 ntx, ch + 2); 1264 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1265 ntx, ch - 2); 1266 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1267 ntx, ch + 2); 1268 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1269 ntx, ch - 2); 1270 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1271 ntx, ch + 2); 1272 } 1273 1274 static void 1275 rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev, 1276 struct rtw89_txpwr_limit_ru *lmt_ru, 1277 u8 ntx, u8 ch) 1278 { 1279 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1280 ntx, ch - 6); 1281 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1282 ntx, ch - 2); 1283 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1284 ntx, ch + 2); 1285 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1286 ntx, ch + 6); 1287 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1288 ntx, ch - 6); 1289 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1290 ntx, ch - 2); 1291 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1292 ntx, ch + 2); 1293 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1294 ntx, ch + 6); 1295 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1296 ntx, ch - 6); 1297 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1298 ntx, ch - 2); 1299 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1300 ntx, ch + 2); 1301 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1302 ntx, ch + 6); 1303 } 1304 1305 void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, 1306 struct rtw89_txpwr_limit_ru *lmt_ru, 1307 u8 ntx) 1308 { 1309 u8 ch = rtwdev->hal.current_channel; 1310 u8 bw = rtwdev->hal.current_band_width; 1311 1312 memset(lmt_ru, 0, sizeof(*lmt_ru)); 1313 1314 switch (bw) { 1315 case RTW89_CHANNEL_WIDTH_20: 1316 rtw89_phy_fill_txpwr_limit_ru_20m(rtwdev, lmt_ru, ntx, ch); 1317 break; 1318 case RTW89_CHANNEL_WIDTH_40: 1319 rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, ntx, ch); 1320 break; 1321 case RTW89_CHANNEL_WIDTH_80: 1322 rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, ntx, ch); 1323 break; 1324 } 1325 } 1326 1327 struct rtw89_phy_iter_ra_data { 1328 struct rtw89_dev *rtwdev; 1329 struct sk_buff *c2h; 1330 }; 1331 1332 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) 1333 { 1334 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; 1335 struct rtw89_dev *rtwdev = ra_data->rtwdev; 1336 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1337 struct rtw89_ra_report *ra_report = &rtwsta->ra_report; 1338 struct sk_buff *c2h = ra_data->c2h; 1339 u8 mode, rate, bw, giltf, mac_id; 1340 1341 mac_id = RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h->data); 1342 if (mac_id != rtwsta->mac_id) 1343 return; 1344 1345 memset(ra_report, 0, sizeof(*ra_report)); 1346 1347 rate = RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h->data); 1348 bw = RTW89_GET_PHY_C2H_RA_RPT_BW(c2h->data); 1349 giltf = RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h->data); 1350 mode = RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h->data); 1351 1352 switch (mode) { 1353 case RTW89_RA_RPT_MODE_LEGACY: 1354 ra_report->txrate.legacy = rtw89_ra_report_to_bitrate(rtwdev, rate); 1355 break; 1356 case RTW89_RA_RPT_MODE_HT: 1357 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; 1358 if (rtwdev->fw.old_ht_ra_format) 1359 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), 1360 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); 1361 else 1362 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); 1363 ra_report->txrate.mcs = rate; 1364 if (giltf) 1365 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1366 break; 1367 case RTW89_RA_RPT_MODE_VHT: 1368 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; 1369 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 1370 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 1371 if (giltf) 1372 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1373 break; 1374 case RTW89_RA_RPT_MODE_HE: 1375 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; 1376 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 1377 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 1378 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 1379 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; 1380 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 1381 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; 1382 else 1383 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; 1384 break; 1385 } 1386 1387 if (bw == RTW89_CHANNEL_WIDTH_80) 1388 ra_report->txrate.bw = RATE_INFO_BW_80; 1389 else if (bw == RTW89_CHANNEL_WIDTH_40) 1390 ra_report->txrate.bw = RATE_INFO_BW_40; 1391 else 1392 ra_report->txrate.bw = RATE_INFO_BW_20; 1393 1394 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); 1395 ra_report->hw_rate = FIELD_PREP(RTW89_HW_RATE_MASK_MOD, mode) | 1396 FIELD_PREP(RTW89_HW_RATE_MASK_VAL, rate); 1397 sta->max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); 1398 rtwsta->max_agg_wait = sta->max_rc_amsdu_len / 1500 - 1; 1399 } 1400 1401 static void 1402 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 1403 { 1404 struct rtw89_phy_iter_ra_data ra_data; 1405 1406 ra_data.rtwdev = rtwdev; 1407 ra_data.c2h = c2h; 1408 ieee80211_iterate_stations_atomic(rtwdev->hw, 1409 rtw89_phy_c2h_ra_rpt_iter, 1410 &ra_data); 1411 } 1412 1413 static 1414 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, 1415 struct sk_buff *c2h, u32 len) = { 1416 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 1417 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 1418 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 1419 }; 1420 1421 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1422 u32 len, u8 class, u8 func) 1423 { 1424 void (*handler)(struct rtw89_dev *rtwdev, 1425 struct sk_buff *c2h, u32 len) = NULL; 1426 1427 switch (class) { 1428 case RTW89_PHY_C2H_CLASS_RA: 1429 if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 1430 handler = rtw89_phy_c2h_ra_handler[func]; 1431 break; 1432 default: 1433 rtw89_info(rtwdev, "c2h class %d not support\n", class); 1434 return; 1435 } 1436 if (!handler) { 1437 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 1438 func); 1439 return; 1440 } 1441 handler(rtwdev, skb, len); 1442 } 1443 1444 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) 1445 { 1446 u32 reg_mask; 1447 1448 if (sc_xo) 1449 reg_mask = B_AX_XTAL_SC_XO_MASK; 1450 else 1451 reg_mask = B_AX_XTAL_SC_XI_MASK; 1452 1453 return (u8)rtw89_read32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask); 1454 } 1455 1456 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, 1457 u8 val) 1458 { 1459 u32 reg_mask; 1460 1461 if (sc_xo) 1462 reg_mask = B_AX_XTAL_SC_XO_MASK; 1463 else 1464 reg_mask = B_AX_XTAL_SC_XI_MASK; 1465 1466 rtw89_write32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask, val); 1467 } 1468 1469 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, 1470 u8 crystal_cap, bool force) 1471 { 1472 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 1473 u8 sc_xi_val, sc_xo_val; 1474 1475 if (!force && cfo->crystal_cap == crystal_cap) 1476 return; 1477 crystal_cap = clamp_t(u8, crystal_cap, 0, 127); 1478 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); 1479 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); 1480 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); 1481 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); 1482 cfo->crystal_cap = sc_xi_val; 1483 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); 1484 1485 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); 1486 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); 1487 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", 1488 cfo->x_cap_ofst); 1489 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); 1490 } 1491 1492 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) 1493 { 1494 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 1495 u8 cap; 1496 1497 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; 1498 cfo->is_adjust = false; 1499 if (cfo->crystal_cap == cfo->def_x_cap) 1500 return; 1501 cap = cfo->crystal_cap; 1502 cap += (cap > cfo->def_x_cap ? -1 : 1); 1503 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); 1504 rtw89_debug(rtwdev, RTW89_DBG_CFO, 1505 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, 1506 cfo->def_x_cap); 1507 } 1508 1509 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) 1510 { 1511 bool is_linked = rtwdev->total_sta_assoc > 0; 1512 s32 cfo_avg_312; 1513 s32 dcfo_comp; 1514 int sign; 1515 1516 if (!is_linked) { 1517 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", 1518 is_linked); 1519 return; 1520 } 1521 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); 1522 if (curr_cfo == 0) 1523 return; 1524 dcfo_comp = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); 1525 sign = curr_cfo > 0 ? 1 : -1; 1526 cfo_avg_312 = (curr_cfo << 3) / 5 + sign * dcfo_comp; 1527 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: avg_cfo=%d\n", cfo_avg_312); 1528 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 1529 cfo_avg_312 = -cfo_avg_312; 1530 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK, 1531 cfo_avg_312); 1532 } 1533 1534 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) 1535 { 1536 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_OPT, B_DCFO_OPT_EN, 1); 1537 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_WEIGHT, B_DCFO_WEIGHT_MSK, 8); 1538 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, B_AX_PWR_UL_CFO_MASK); 1539 } 1540 1541 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) 1542 { 1543 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 1544 struct rtw89_efuse *efuse = &rtwdev->efuse; 1545 1546 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; 1547 cfo->crystal_cap = cfo->crystal_cap_default; 1548 cfo->def_x_cap = cfo->crystal_cap; 1549 cfo->is_adjust = false; 1550 cfo->x_cap_ofst = 0; 1551 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; 1552 cfo->apply_compensation = false; 1553 cfo->residual_cfo_acc = 0; 1554 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", 1555 cfo->crystal_cap_default); 1556 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); 1557 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); 1558 rtw89_dcfo_comp_init(rtwdev); 1559 cfo->cfo_timer_ms = 2000; 1560 cfo->cfo_trig_by_timer_en = false; 1561 cfo->phy_cfo_trk_cnt = 0; 1562 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 1563 } 1564 1565 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, 1566 s32 curr_cfo) 1567 { 1568 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 1569 s8 crystal_cap = cfo->crystal_cap; 1570 s32 cfo_abs = abs(curr_cfo); 1571 int sign; 1572 1573 if (!cfo->is_adjust) { 1574 if (cfo_abs > CFO_TRK_ENABLE_TH) 1575 cfo->is_adjust = true; 1576 } else { 1577 if (cfo_abs < CFO_TRK_STOP_TH) 1578 cfo->is_adjust = false; 1579 } 1580 if (!cfo->is_adjust) { 1581 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); 1582 return; 1583 } 1584 sign = curr_cfo > 0 ? 1 : -1; 1585 if (cfo_abs > CFO_TRK_STOP_TH_4) 1586 crystal_cap += 7 * sign; 1587 else if (cfo_abs > CFO_TRK_STOP_TH_3) 1588 crystal_cap += 5 * sign; 1589 else if (cfo_abs > CFO_TRK_STOP_TH_2) 1590 crystal_cap += 3 * sign; 1591 else if (cfo_abs > CFO_TRK_STOP_TH_1) 1592 crystal_cap += 1 * sign; 1593 else 1594 return; 1595 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); 1596 rtw89_debug(rtwdev, RTW89_DBG_CFO, 1597 "X_cap{Curr,Default}={0x%x,0x%x}\n", 1598 cfo->crystal_cap, cfo->def_x_cap); 1599 } 1600 1601 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) 1602 { 1603 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 1604 s32 cfo_khz_all = 0; 1605 s32 cfo_cnt_all = 0; 1606 s32 cfo_all_avg = 0; 1607 u8 i; 1608 1609 if (rtwdev->total_sta_assoc != 1) 1610 return 0; 1611 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); 1612 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 1613 if (cfo->cfo_cnt[i] == 0) 1614 continue; 1615 cfo_khz_all += cfo->cfo_tail[i]; 1616 cfo_cnt_all += cfo->cfo_cnt[i]; 1617 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); 1618 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 1619 } 1620 rtw89_debug(rtwdev, RTW89_DBG_CFO, 1621 "CFO track for macid = %d\n", i); 1622 rtw89_debug(rtwdev, RTW89_DBG_CFO, 1623 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", 1624 cfo_khz_all, cfo_cnt_all, cfo_all_avg); 1625 return cfo_all_avg; 1626 } 1627 1628 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) 1629 { 1630 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 1631 struct rtw89_traffic_stats *stats = &rtwdev->stats; 1632 s32 target_cfo = 0; 1633 s32 cfo_khz_all = 0; 1634 s32 cfo_khz_all_tp_wgt = 0; 1635 s32 cfo_avg = 0; 1636 s32 max_cfo_lb = BIT(31); 1637 s32 min_cfo_ub = GENMASK(30, 0); 1638 u16 cfo_cnt_all = 0; 1639 u8 active_entry_cnt = 0; 1640 u8 sta_cnt = 0; 1641 u32 tp_all = 0; 1642 u8 i; 1643 u8 cfo_tol = 0; 1644 1645 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); 1646 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { 1647 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); 1648 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 1649 if (cfo->cfo_cnt[i] == 0) 1650 continue; 1651 cfo_khz_all += cfo->cfo_tail[i]; 1652 cfo_cnt_all += cfo->cfo_cnt[i]; 1653 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); 1654 rtw89_debug(rtwdev, RTW89_DBG_CFO, 1655 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", 1656 cfo_khz_all, cfo_cnt_all, cfo_avg); 1657 target_cfo = cfo_avg; 1658 } 1659 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { 1660 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); 1661 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 1662 if (cfo->cfo_cnt[i] == 0) 1663 continue; 1664 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 1665 (s32)cfo->cfo_cnt[i]); 1666 cfo_khz_all += cfo->cfo_avg[i]; 1667 rtw89_debug(rtwdev, RTW89_DBG_CFO, 1668 "Macid=%d, cfo_avg=%d\n", i, 1669 cfo->cfo_avg[i]); 1670 } 1671 sta_cnt = rtwdev->total_sta_assoc; 1672 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); 1673 rtw89_debug(rtwdev, RTW89_DBG_CFO, 1674 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", 1675 cfo_khz_all, sta_cnt, cfo_avg); 1676 target_cfo = cfo_avg; 1677 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { 1678 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); 1679 cfo_tol = cfo->sta_cfo_tolerance; 1680 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 1681 sta_cnt++; 1682 if (cfo->cfo_cnt[i] != 0) { 1683 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 1684 (s32)cfo->cfo_cnt[i]); 1685 active_entry_cnt++; 1686 } else { 1687 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; 1688 } 1689 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); 1690 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); 1691 cfo_khz_all += cfo->cfo_avg[i]; 1692 /* need tp for each entry */ 1693 rtw89_debug(rtwdev, RTW89_DBG_CFO, 1694 "[%d] cfo_avg=%d, tp=tbd\n", 1695 i, cfo->cfo_avg[i]); 1696 if (sta_cnt >= rtwdev->total_sta_assoc) 1697 break; 1698 } 1699 tp_all = stats->rx_throughput; /* need tp for each entry */ 1700 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); 1701 1702 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", 1703 sta_cnt); 1704 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", 1705 active_entry_cnt); 1706 rtw89_debug(rtwdev, RTW89_DBG_CFO, 1707 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", 1708 cfo_khz_all_tp_wgt, cfo_avg); 1709 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", 1710 max_cfo_lb, min_cfo_ub); 1711 if (max_cfo_lb <= min_cfo_ub) { 1712 rtw89_debug(rtwdev, RTW89_DBG_CFO, 1713 "cfo win_size=%d\n", 1714 min_cfo_ub - max_cfo_lb); 1715 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); 1716 } else { 1717 rtw89_debug(rtwdev, RTW89_DBG_CFO, 1718 "No intersection of cfo tolerance windows\n"); 1719 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); 1720 } 1721 for (i = 0; i < CFO_TRACK_MAX_USER; i++) 1722 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 1723 } 1724 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); 1725 return target_cfo; 1726 } 1727 1728 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) 1729 { 1730 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 1731 1732 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); 1733 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); 1734 cfo->packet_count = 0; 1735 cfo->packet_count_pre = 0; 1736 cfo->cfo_avg_pre = 0; 1737 } 1738 1739 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) 1740 { 1741 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 1742 s32 new_cfo = 0; 1743 bool x_cap_update = false; 1744 u8 pre_x_cap = cfo->crystal_cap; 1745 1746 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", 1747 rtwdev->total_sta_assoc); 1748 if (rtwdev->total_sta_assoc == 0) { 1749 rtw89_phy_cfo_reset(rtwdev); 1750 return; 1751 } 1752 if (cfo->packet_count == 0) { 1753 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); 1754 return; 1755 } 1756 if (cfo->packet_count == cfo->packet_count_pre) { 1757 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); 1758 return; 1759 } 1760 if (rtwdev->total_sta_assoc == 1) 1761 new_cfo = rtw89_phy_average_cfo_calc(rtwdev); 1762 else 1763 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); 1764 if (new_cfo == 0) { 1765 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); 1766 return; 1767 } 1768 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); 1769 cfo->cfo_avg_pre = new_cfo; 1770 x_cap_update = cfo->crystal_cap == pre_x_cap ? false : true; 1771 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); 1772 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", 1773 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, 1774 cfo->x_cap_ofst); 1775 if (x_cap_update) { 1776 if (new_cfo > 0) 1777 new_cfo -= CFO_SW_COMP_FINE_TUNE; 1778 else 1779 new_cfo += CFO_SW_COMP_FINE_TUNE; 1780 } 1781 rtw89_dcfo_comp(rtwdev, new_cfo); 1782 rtw89_phy_cfo_statistics_reset(rtwdev); 1783 } 1784 1785 void rtw89_phy_cfo_track_work(struct work_struct *work) 1786 { 1787 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 1788 cfo_track_work.work); 1789 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 1790 1791 mutex_lock(&rtwdev->mutex); 1792 if (!cfo->cfo_trig_by_timer_en) 1793 goto out; 1794 rtw89_leave_ps_mode(rtwdev); 1795 rtw89_phy_cfo_dm(rtwdev); 1796 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 1797 msecs_to_jiffies(cfo->cfo_timer_ms)); 1798 out: 1799 mutex_unlock(&rtwdev->mutex); 1800 } 1801 1802 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) 1803 { 1804 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 1805 1806 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 1807 msecs_to_jiffies(cfo->cfo_timer_ms)); 1808 } 1809 1810 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) 1811 { 1812 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 1813 struct rtw89_traffic_stats *stats = &rtwdev->stats; 1814 1815 switch (cfo->phy_cfo_status) { 1816 case RTW89_PHY_DCFO_STATE_NORMAL: 1817 if (stats->tx_throughput >= CFO_TP_UPPER) { 1818 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; 1819 cfo->cfo_trig_by_timer_en = true; 1820 cfo->cfo_timer_ms = CFO_COMP_PERIOD; 1821 rtw89_phy_cfo_start_work(rtwdev); 1822 } 1823 break; 1824 case RTW89_PHY_DCFO_STATE_ENHANCE: 1825 if (cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) { 1826 cfo->phy_cfo_trk_cnt = 0; 1827 cfo->cfo_trig_by_timer_en = false; 1828 } 1829 if (cfo->cfo_trig_by_timer_en == 1) 1830 cfo->phy_cfo_trk_cnt++; 1831 if (stats->tx_throughput <= CFO_TP_LOWER) { 1832 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 1833 cfo->phy_cfo_trk_cnt = 0; 1834 cfo->cfo_trig_by_timer_en = false; 1835 } 1836 break; 1837 default: 1838 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 1839 cfo->phy_cfo_trk_cnt = 0; 1840 break; 1841 } 1842 rtw89_debug(rtwdev, RTW89_DBG_CFO, 1843 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", 1844 stats->tx_throughput, cfo->phy_cfo_status, 1845 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, 1846 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); 1847 if (cfo->cfo_trig_by_timer_en) 1848 return; 1849 rtw89_phy_cfo_dm(rtwdev); 1850 } 1851 1852 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 1853 struct rtw89_rx_phy_ppdu *phy_ppdu) 1854 { 1855 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 1856 u8 macid = phy_ppdu->mac_id; 1857 1858 cfo->cfo_tail[macid] += cfo_val; 1859 cfo->cfo_cnt[macid]++; 1860 cfo->packet_count++; 1861 } 1862 1863 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) 1864 { 1865 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 1866 int i; 1867 u8 th; 1868 1869 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 1870 th = rtw89_chip_get_thermal(rtwdev, i); 1871 if (th) 1872 ewma_thermal_add(&phystat->avg_thermal[i], th); 1873 1874 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 1875 "path(%d) thermal cur=%u avg=%ld", i, th, 1876 ewma_thermal_read(&phystat->avg_thermal[i])); 1877 } 1878 } 1879 1880 struct rtw89_phy_iter_rssi_data { 1881 struct rtw89_dev *rtwdev; 1882 struct rtw89_phy_ch_info *ch_info; 1883 bool rssi_changed; 1884 }; 1885 1886 static void rtw89_phy_stat_rssi_update_iter(void *data, 1887 struct ieee80211_sta *sta) 1888 { 1889 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1890 struct rtw89_phy_iter_rssi_data *rssi_data = 1891 (struct rtw89_phy_iter_rssi_data *)data; 1892 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info; 1893 unsigned long rssi_curr; 1894 1895 rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi); 1896 1897 if (rssi_curr < ch_info->rssi_min) { 1898 ch_info->rssi_min = rssi_curr; 1899 ch_info->rssi_min_macid = rtwsta->mac_id; 1900 } 1901 1902 if (rtwsta->prev_rssi == 0) { 1903 rtwsta->prev_rssi = rssi_curr; 1904 } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) { 1905 rtwsta->prev_rssi = rssi_curr; 1906 rssi_data->rssi_changed = true; 1907 } 1908 } 1909 1910 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) 1911 { 1912 struct rtw89_phy_iter_rssi_data rssi_data = {0}; 1913 1914 rssi_data.rtwdev = rtwdev; 1915 rssi_data.ch_info = &rtwdev->ch_info; 1916 rssi_data.ch_info->rssi_min = U8_MAX; 1917 ieee80211_iterate_stations_atomic(rtwdev->hw, 1918 rtw89_phy_stat_rssi_update_iter, 1919 &rssi_data); 1920 if (rssi_data.rssi_changed) 1921 rtw89_btc_ntfy_wl_sta(rtwdev); 1922 } 1923 1924 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) 1925 { 1926 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 1927 int i; 1928 1929 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 1930 ewma_thermal_init(&phystat->avg_thermal[i]); 1931 1932 rtw89_phy_stat_thermal_update(rtwdev); 1933 1934 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 1935 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); 1936 } 1937 1938 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) 1939 { 1940 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 1941 1942 rtw89_phy_stat_thermal_update(rtwdev); 1943 rtw89_phy_stat_rssi_update(rtwdev); 1944 1945 phystat->last_pkt_stat = phystat->cur_pkt_stat; 1946 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 1947 } 1948 1949 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us) 1950 { 1951 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 1952 1953 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 1954 } 1955 1956 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) 1957 { 1958 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 1959 1960 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 1961 } 1962 1963 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) 1964 { 1965 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 1966 1967 env->ccx_manual_ctrl = false; 1968 env->ccx_ongoing = false; 1969 env->ccx_rac_lv = RTW89_RAC_RELEASE; 1970 env->ccx_rpt_stamp = 0; 1971 env->ccx_period = 0; 1972 env->ccx_unit_idx = RTW89_CCX_32_US; 1973 env->ccx_trigger_time = 0; 1974 env->ccx_edcca_opt_bw_idx = RTW89_CCX_EDCCA_BW20_0; 1975 1976 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1); 1977 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1); 1978 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 1979 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EDCCA_OPT_MSK, 1980 RTW89_CCX_EDCCA_BW20_0); 1981 } 1982 1983 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report, 1984 u16 score) 1985 { 1986 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 1987 u32 numer = 0; 1988 u16 ret = 0; 1989 1990 numer = report * score + (env->ccx_period >> 1); 1991 if (env->ccx_period) 1992 ret = numer / env->ccx_period; 1993 1994 return ret >= score ? score - 1 : ret; 1995 } 1996 1997 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, 1998 u16 time_ms, u32 *period, 1999 u32 *unit_idx) 2000 { 2001 u32 idx; 2002 u8 quotient; 2003 2004 if (time_ms >= CCX_MAX_PERIOD) 2005 time_ms = CCX_MAX_PERIOD; 2006 2007 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; 2008 2009 if (quotient < 4) 2010 idx = RTW89_CCX_4_US; 2011 else if (quotient < 8) 2012 idx = RTW89_CCX_8_US; 2013 else if (quotient < 16) 2014 idx = RTW89_CCX_16_US; 2015 else 2016 idx = RTW89_CCX_32_US; 2017 2018 *unit_idx = idx; 2019 *period = (time_ms * MS_TO_4US_RATIO) >> idx; 2020 2021 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2022 "[Trigger Time] period:%d, unit_idx:%d\n", 2023 *period, *unit_idx); 2024 } 2025 2026 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev) 2027 { 2028 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2029 2030 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2031 "lv:(%d)->(0)\n", env->ccx_rac_lv); 2032 2033 env->ccx_ongoing = false; 2034 env->ccx_rac_lv = RTW89_RAC_RELEASE; 2035 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 2036 } 2037 2038 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, 2039 struct rtw89_ccx_para_info *para) 2040 { 2041 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2042 bool is_update = env->ifs_clm_app != para->ifs_clm_app; 2043 u8 i = 0; 2044 u16 *ifs_th_l = env->ifs_clm_th_l; 2045 u16 *ifs_th_h = env->ifs_clm_th_h; 2046 u32 ifs_th0_us = 0, ifs_th_times = 0; 2047 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; 2048 2049 if (!is_update) 2050 goto ifs_update_finished; 2051 2052 switch (para->ifs_clm_app) { 2053 case RTW89_IFS_CLM_INIT: 2054 case RTW89_IFS_CLM_BACKGROUND: 2055 case RTW89_IFS_CLM_ACS: 2056 case RTW89_IFS_CLM_DBG: 2057 case RTW89_IFS_CLM_DIG: 2058 case RTW89_IFS_CLM_TDMA_DIG: 2059 ifs_th0_us = IFS_CLM_TH0_UPPER; 2060 ifs_th_times = IFS_CLM_TH_MUL; 2061 break; 2062 case RTW89_IFS_CLM_DBG_MANUAL: 2063 ifs_th0_us = para->ifs_clm_manual_th0; 2064 ifs_th_times = para->ifs_clm_manual_th_times; 2065 break; 2066 default: 2067 break; 2068 } 2069 2070 /* Set sampling threshold for 4 different regions, unit in idx_cnt. 2071 * low[i] = high[i-1] + 1 2072 * high[i] = high[i-1] * ifs_th_times 2073 */ 2074 ifs_th_l[IFS_CLM_TH_START_IDX] = 0; 2075 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; 2076 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, 2077 ifs_th0_us); 2078 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { 2079 ifs_th_l[i] = ifs_th_h[i - 1] + 1; 2080 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; 2081 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]); 2082 } 2083 2084 ifs_update_finished: 2085 if (!is_update) 2086 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2087 "No need to update IFS_TH\n"); 2088 2089 return is_update; 2090 } 2091 2092 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) 2093 { 2094 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2095 u8 i = 0; 2096 2097 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_LOW_MSK, 2098 env->ifs_clm_th_l[0]); 2099 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_LOW_MSK, 2100 env->ifs_clm_th_l[1]); 2101 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_LOW_MSK, 2102 env->ifs_clm_th_l[2]); 2103 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_LOW_MSK, 2104 env->ifs_clm_th_l[3]); 2105 2106 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_HIGH_MSK, 2107 env->ifs_clm_th_h[0]); 2108 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_HIGH_MSK, 2109 env->ifs_clm_th_h[1]); 2110 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_HIGH_MSK, 2111 env->ifs_clm_th_h[2]); 2112 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_HIGH_MSK, 2113 env->ifs_clm_th_h[3]); 2114 2115 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 2116 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2117 "Update IFS_T%d_th{low, high} : {%d, %d}\n", 2118 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 2119 } 2120 2121 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) 2122 { 2123 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2124 struct rtw89_ccx_para_info para = {0}; 2125 2126 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 2127 env->ifs_clm_mntr_time = 0; 2128 2129 para.ifs_clm_app = RTW89_IFS_CLM_INIT; 2130 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) 2131 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 2132 2133 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COLLECT_EN, 2134 true); 2135 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_EN_MSK, true); 2136 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_EN_MSK, true); 2137 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_EN_MSK, true); 2138 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_EN_MSK, true); 2139 } 2140 2141 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, 2142 enum rtw89_env_racing_lv level) 2143 { 2144 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2145 int ret = 0; 2146 2147 if (level >= RTW89_RAC_MAX_NUM) { 2148 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2149 "[WARNING] Wrong LV=%d\n", level); 2150 return -EINVAL; 2151 } 2152 2153 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2154 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, 2155 env->ccx_rac_lv, level); 2156 2157 if (env->ccx_ongoing) { 2158 if (level <= env->ccx_rac_lv) 2159 ret = -EINVAL; 2160 else 2161 env->ccx_ongoing = false; 2162 } 2163 2164 if (ret == 0) 2165 env->ccx_rac_lv = level; 2166 2167 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", 2168 !ret); 2169 2170 return ret; 2171 } 2172 2173 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) 2174 { 2175 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2176 2177 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 0); 2178 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 0); 2179 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1); 2180 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 2181 2182 env->ccx_rpt_stamp++; 2183 env->ccx_ongoing = true; 2184 } 2185 2186 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) 2187 { 2188 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2189 u8 i = 0; 2190 u32 res = 0; 2191 2192 env->ifs_clm_tx_ratio = 2193 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT); 2194 env->ifs_clm_edcca_excl_cca_ratio = 2195 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca, 2196 PERCENT); 2197 env->ifs_clm_cck_fa_ratio = 2198 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT); 2199 env->ifs_clm_ofdm_fa_ratio = 2200 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT); 2201 env->ifs_clm_cck_cca_excl_fa_ratio = 2202 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa, 2203 PERCENT); 2204 env->ifs_clm_ofdm_cca_excl_fa_ratio = 2205 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa, 2206 PERCENT); 2207 env->ifs_clm_cck_fa_permil = 2208 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL); 2209 env->ifs_clm_ofdm_fa_permil = 2210 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL); 2211 2212 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { 2213 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { 2214 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; 2215 } else { 2216 env->ifs_clm_ifs_avg[i] = 2217 rtw89_phy_ccx_idx_to_us(rtwdev, 2218 env->ifs_clm_avg[i]); 2219 } 2220 2221 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]); 2222 res += env->ifs_clm_his[i] >> 1; 2223 if (env->ifs_clm_his[i]) 2224 res /= env->ifs_clm_his[i]; 2225 else 2226 res = 0; 2227 env->ifs_clm_cca_avg[i] = res; 2228 } 2229 2230 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2231 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", 2232 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); 2233 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2234 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", 2235 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); 2236 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2237 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", 2238 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); 2239 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2240 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", 2241 env->ifs_clm_cck_cca_excl_fa_ratio, 2242 env->ifs_clm_ofdm_cca_excl_fa_ratio); 2243 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2244 "Time:[his, ifs_avg(us), cca_avg(us)]\n"); 2245 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 2246 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 2247 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 2248 env->ifs_clm_cca_avg[i]); 2249 } 2250 2251 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) 2252 { 2253 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2254 u8 i = 0; 2255 2256 if (rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_DONE_MSK) == 0) { 2257 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2258 "Get IFS_CLM report Fail\n"); 2259 return false; 2260 } 2261 2262 env->ifs_clm_tx = 2263 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 2264 B_IFS_CLM_TX_CNT_MSK); 2265 env->ifs_clm_edcca_excl_cca = 2266 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 2267 B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK); 2268 env->ifs_clm_cckcca_excl_fa = 2269 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 2270 B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK); 2271 env->ifs_clm_ofdmcca_excl_fa = 2272 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 2273 B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK); 2274 env->ifs_clm_cckfa = 2275 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 2276 B_IFS_CLM_CCK_FA_MSK); 2277 env->ifs_clm_ofdmfa = 2278 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 2279 B_IFS_CLM_OFDM_FA_MSK); 2280 2281 env->ifs_clm_his[0] = 2282 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T1_HIS_MSK); 2283 env->ifs_clm_his[1] = 2284 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T2_HIS_MSK); 2285 env->ifs_clm_his[2] = 2286 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T3_HIS_MSK); 2287 env->ifs_clm_his[3] = 2288 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T4_HIS_MSK); 2289 2290 env->ifs_clm_avg[0] = 2291 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T1_AVG_MSK); 2292 env->ifs_clm_avg[1] = 2293 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T2_AVG_MSK); 2294 env->ifs_clm_avg[2] = 2295 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T3_AVG_MSK); 2296 env->ifs_clm_avg[3] = 2297 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T4_AVG_MSK); 2298 2299 env->ifs_clm_cca[0] = 2300 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T1_CCA_MSK); 2301 env->ifs_clm_cca[1] = 2302 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T2_CCA_MSK); 2303 env->ifs_clm_cca[2] = 2304 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T3_CCA_MSK); 2305 env->ifs_clm_cca[3] = 2306 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T4_CCA_MSK); 2307 2308 env->ifs_clm_total_ifs = 2309 rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_TOTAL_CNT_MSK); 2310 2311 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", 2312 env->ifs_clm_total_ifs); 2313 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2314 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", 2315 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); 2316 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2317 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", 2318 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); 2319 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2320 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", 2321 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); 2322 2323 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); 2324 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 2325 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2326 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], 2327 env->ifs_clm_avg[i], env->ifs_clm_cca[i]); 2328 2329 rtw89_phy_ifs_clm_get_utility(rtwdev); 2330 2331 return true; 2332 } 2333 2334 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 2335 struct rtw89_ccx_para_info *para) 2336 { 2337 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2338 u32 period = 0; 2339 u32 unit_idx = 0; 2340 2341 if (para->mntr_time == 0) { 2342 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2343 "[WARN] MNTR_TIME is 0\n"); 2344 return -EINVAL; 2345 } 2346 2347 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv)) 2348 return -EINVAL; 2349 2350 if (para->mntr_time != env->ifs_clm_mntr_time) { 2351 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 2352 &period, &unit_idx); 2353 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 2354 B_IFS_CLM_PERIOD_MSK, period); 2355 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 2356 B_IFS_CLM_COUNTER_UNIT_MSK, unit_idx); 2357 2358 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2359 "Update IFS-CLM time ((%d)) -> ((%d))\n", 2360 env->ifs_clm_mntr_time, para->mntr_time); 2361 2362 env->ifs_clm_mntr_time = para->mntr_time; 2363 env->ccx_period = (u16)period; 2364 env->ccx_unit_idx = (u8)unit_idx; 2365 } 2366 2367 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) { 2368 env->ifs_clm_app = para->ifs_clm_app; 2369 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 2370 } 2371 2372 return 0; 2373 } 2374 2375 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) 2376 { 2377 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2378 struct rtw89_ccx_para_info para = {0}; 2379 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; 2380 2381 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; 2382 if (env->ccx_manual_ctrl) { 2383 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2384 "CCX in manual ctrl\n"); 2385 return; 2386 } 2387 2388 /* only ifs_clm for now */ 2389 if (rtw89_phy_ifs_clm_get_result(rtwdev)) 2390 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; 2391 2392 rtw89_phy_ccx_racing_release(rtwdev); 2393 para.mntr_time = 1900; 2394 para.rac_lv = RTW89_RAC_LV_1; 2395 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 2396 2397 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0) 2398 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 2399 if (chk_result) 2400 rtw89_phy_ccx_trigger(rtwdev); 2401 2402 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2403 "get_result=0x%x, chk_result:0x%x\n", 2404 env->ccx_watchdog_result, chk_result); 2405 } 2406 2407 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) 2408 { 2409 const struct rtw89_chip_info *chip = rtwdev->chip; 2410 struct rtw89_dig_info *dig = &rtwdev->dig; 2411 const struct rtw89_phy_dig_gain_cfg *cfg; 2412 const char *msg; 2413 u8 i; 2414 s8 gain_base; 2415 s8 *gain_arr; 2416 u32 tmp; 2417 2418 switch (type) { 2419 case RTW89_DIG_GAIN_LNA_G: 2420 gain_arr = dig->lna_gain_g; 2421 gain_base = LNA0_GAIN; 2422 cfg = chip->dig_table->cfg_lna_g; 2423 msg = "lna_gain_g"; 2424 break; 2425 case RTW89_DIG_GAIN_TIA_G: 2426 gain_arr = dig->tia_gain_g; 2427 gain_base = TIA0_GAIN_G; 2428 cfg = chip->dig_table->cfg_tia_g; 2429 msg = "tia_gain_g"; 2430 break; 2431 case RTW89_DIG_GAIN_LNA_A: 2432 gain_arr = dig->lna_gain_a; 2433 gain_base = LNA0_GAIN; 2434 cfg = chip->dig_table->cfg_lna_a; 2435 msg = "lna_gain_a"; 2436 break; 2437 case RTW89_DIG_GAIN_TIA_A: 2438 gain_arr = dig->tia_gain_a; 2439 gain_base = TIA0_GAIN_A; 2440 cfg = chip->dig_table->cfg_tia_a; 2441 msg = "tia_gain_a"; 2442 break; 2443 default: 2444 return; 2445 } 2446 2447 for (i = 0; i < cfg->size; i++) { 2448 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr, 2449 cfg->table[i].mask); 2450 tmp >>= DIG_GAIN_SHIFT; 2451 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; 2452 gain_base += DIG_GAIN; 2453 2454 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", 2455 msg, i, gain_arr[i]); 2456 } 2457 } 2458 2459 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev) 2460 { 2461 struct rtw89_dig_info *dig = &rtwdev->dig; 2462 u32 tmp; 2463 u8 i; 2464 2465 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW, 2466 B_PATH0_IB_PKPW_MSK); 2467 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); 2468 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK, 2469 B_PATH0_IB_PBK_MSK); 2470 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", 2471 dig->ib_pkpwr, dig->ib_pbk); 2472 2473 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) 2474 rtw89_phy_dig_read_gain_table(rtwdev, i); 2475 } 2476 2477 static const u8 rssi_nolink = 22; 2478 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; 2479 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; 2480 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; 2481 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; 2482 2483 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev) 2484 { 2485 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 2486 struct rtw89_dig_info *dig = &rtwdev->dig; 2487 bool is_linked = rtwdev->total_sta_assoc > 0; 2488 2489 if (is_linked) { 2490 dig->igi_rssi = ch_info->rssi_min >> 1; 2491 } else { 2492 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); 2493 dig->igi_rssi = rssi_nolink; 2494 } 2495 } 2496 2497 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev) 2498 { 2499 struct rtw89_dig_info *dig = &rtwdev->dig; 2500 bool is_linked = rtwdev->total_sta_assoc > 0; 2501 const u16 *fa_th_src = NULL; 2502 2503 switch (rtwdev->hal.current_band_type) { 2504 case RTW89_BAND_2G: 2505 dig->lna_gain = dig->lna_gain_g; 2506 dig->tia_gain = dig->tia_gain_g; 2507 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; 2508 dig->force_gaincode_idx_en = false; 2509 dig->dyn_pd_th_en = true; 2510 break; 2511 case RTW89_BAND_5G: 2512 default: 2513 dig->lna_gain = dig->lna_gain_a; 2514 dig->tia_gain = dig->tia_gain_a; 2515 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; 2516 dig->force_gaincode_idx_en = true; 2517 dig->dyn_pd_th_en = true; 2518 break; 2519 } 2520 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); 2521 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); 2522 } 2523 2524 static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20; 2525 static const u8 igi_max_performance_mode = 0x5a; 2526 static const u8 dynamic_pd_threshold_max; 2527 2528 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev) 2529 { 2530 struct rtw89_dig_info *dig = &rtwdev->dig; 2531 2532 dig->cur_gaincode.lna_idx = LNA_IDX_MAX; 2533 dig->cur_gaincode.tia_idx = TIA_IDX_MAX; 2534 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; 2535 dig->force_gaincode.lna_idx = LNA_IDX_MAX; 2536 dig->force_gaincode.tia_idx = TIA_IDX_MAX; 2537 dig->force_gaincode.rxb_idx = RXB_IDX_MAX; 2538 2539 dig->dyn_igi_max = igi_max_performance_mode; 2540 dig->dyn_igi_min = dynamic_igi_min; 2541 dig->dyn_pd_th_max = dynamic_pd_threshold_max; 2542 dig->pd_low_th_ofst = pd_low_th_offset; 2543 dig->is_linked_pre = false; 2544 } 2545 2546 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) 2547 { 2548 rtw89_phy_dig_update_gain_para(rtwdev); 2549 rtw89_phy_dig_reset(rtwdev); 2550 } 2551 2552 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 2553 { 2554 struct rtw89_dig_info *dig = &rtwdev->dig; 2555 u8 lna_idx; 2556 2557 if (rssi < dig->igi_rssi_th[0]) 2558 lna_idx = RTW89_DIG_GAIN_LNA_IDX6; 2559 else if (rssi < dig->igi_rssi_th[1]) 2560 lna_idx = RTW89_DIG_GAIN_LNA_IDX5; 2561 else if (rssi < dig->igi_rssi_th[2]) 2562 lna_idx = RTW89_DIG_GAIN_LNA_IDX4; 2563 else if (rssi < dig->igi_rssi_th[3]) 2564 lna_idx = RTW89_DIG_GAIN_LNA_IDX3; 2565 else if (rssi < dig->igi_rssi_th[4]) 2566 lna_idx = RTW89_DIG_GAIN_LNA_IDX2; 2567 else 2568 lna_idx = RTW89_DIG_GAIN_LNA_IDX1; 2569 2570 return lna_idx; 2571 } 2572 2573 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 2574 { 2575 struct rtw89_dig_info *dig = &rtwdev->dig; 2576 u8 tia_idx; 2577 2578 if (rssi < dig->igi_rssi_th[0]) 2579 tia_idx = RTW89_DIG_GAIN_TIA_IDX1; 2580 else 2581 tia_idx = RTW89_DIG_GAIN_TIA_IDX0; 2582 2583 return tia_idx; 2584 } 2585 2586 #define IB_PBK_BASE 110 2587 #define WB_RSSI_BASE 10 2588 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 2589 struct rtw89_agc_gaincode_set *set) 2590 { 2591 struct rtw89_dig_info *dig = &rtwdev->dig; 2592 s8 lna_gain = dig->lna_gain[set->lna_idx]; 2593 s8 tia_gain = dig->tia_gain[set->tia_idx]; 2594 s32 wb_rssi = rssi + lna_gain + tia_gain; 2595 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; 2596 u8 rxb_idx; 2597 2598 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; 2599 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); 2600 2601 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", 2602 wb_rssi, rxb_idx_tmp); 2603 2604 return rxb_idx; 2605 } 2606 2607 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 2608 struct rtw89_agc_gaincode_set *set) 2609 { 2610 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi); 2611 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi); 2612 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set); 2613 2614 rtw89_debug(rtwdev, RTW89_DBG_DIG, 2615 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", 2616 rssi, set->lna_idx, set->tia_idx, set->rxb_idx); 2617 } 2618 2619 #define IGI_OFFSET_MAX 25 2620 #define IGI_OFFSET_MUL 2 2621 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev) 2622 { 2623 struct rtw89_dig_info *dig = &rtwdev->dig; 2624 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2625 enum rtw89_dig_noisy_level noisy_lv; 2626 u8 igi_offset = dig->fa_rssi_ofst; 2627 u16 fa_ratio = 0; 2628 2629 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; 2630 2631 if (fa_ratio < dig->fa_th[0]) 2632 noisy_lv = RTW89_DIG_NOISY_LEVEL0; 2633 else if (fa_ratio < dig->fa_th[1]) 2634 noisy_lv = RTW89_DIG_NOISY_LEVEL1; 2635 else if (fa_ratio < dig->fa_th[2]) 2636 noisy_lv = RTW89_DIG_NOISY_LEVEL2; 2637 else if (fa_ratio < dig->fa_th[3]) 2638 noisy_lv = RTW89_DIG_NOISY_LEVEL3; 2639 else 2640 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; 2641 2642 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) 2643 igi_offset = 0; 2644 else 2645 igi_offset += noisy_lv * IGI_OFFSET_MUL; 2646 2647 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); 2648 dig->fa_rssi_ofst = igi_offset; 2649 2650 rtw89_debug(rtwdev, RTW89_DBG_DIG, 2651 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", 2652 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); 2653 2654 rtw89_debug(rtwdev, RTW89_DBG_DIG, 2655 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", 2656 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, 2657 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, 2658 noisy_lv, igi_offset); 2659 } 2660 2661 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx) 2662 { 2663 rtw89_phy_write32_mask(rtwdev, R_PATH0_LNA_INIT, 2664 B_PATH0_LNA_INIT_IDX_MSK, lna_idx); 2665 rtw89_phy_write32_mask(rtwdev, R_PATH1_LNA_INIT, 2666 B_PATH1_LNA_INIT_IDX_MSK, lna_idx); 2667 } 2668 2669 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx) 2670 { 2671 rtw89_phy_write32_mask(rtwdev, R_PATH0_TIA_INIT, 2672 B_PATH0_TIA_INIT_IDX_MSK, tia_idx); 2673 rtw89_phy_write32_mask(rtwdev, R_PATH1_TIA_INIT, 2674 B_PATH1_TIA_INIT_IDX_MSK, tia_idx); 2675 } 2676 2677 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx) 2678 { 2679 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXB_INIT, 2680 B_PATH0_RXB_INIT_IDX_MSK, rxb_idx); 2681 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXB_INIT, 2682 B_PATH1_RXB_INIT_IDX_MSK, rxb_idx); 2683 } 2684 2685 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, 2686 const struct rtw89_agc_gaincode_set set) 2687 { 2688 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx); 2689 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx); 2690 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx); 2691 2692 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", 2693 set.lna_idx, set.tia_idx, set.rxb_idx); 2694 } 2695 2696 static const struct rtw89_reg_def sdagc_config[4] = { 2697 {R_PATH0_P20_FOLLOW_BY_PAGCUGC, B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 2698 {R_PATH0_S20_FOLLOW_BY_PAGCUGC, B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 2699 {R_PATH1_P20_FOLLOW_BY_PAGCUGC, B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 2700 {R_PATH1_S20_FOLLOW_BY_PAGCUGC, B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 2701 }; 2702 2703 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, 2704 bool enable) 2705 { 2706 u8 i = 0; 2707 2708 for (i = 0; i < ARRAY_SIZE(sdagc_config); i++) 2709 rtw89_phy_write32_mask(rtwdev, sdagc_config[i].addr, 2710 sdagc_config[i].mask, enable); 2711 2712 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); 2713 } 2714 2715 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, 2716 bool enable) 2717 { 2718 enum rtw89_bandwidth cbw = rtwdev->hal.current_band_width; 2719 struct rtw89_dig_info *dig = &rtwdev->dig; 2720 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; 2721 u32 val = 0; 2722 2723 under_region += PD_TH_SB_FLTR_CMP_VAL; 2724 2725 switch (cbw) { 2726 case RTW89_CHANNEL_WIDTH_40: 2727 under_region += PD_TH_BW40_CMP_VAL; 2728 break; 2729 case RTW89_CHANNEL_WIDTH_80: 2730 under_region += PD_TH_BW80_CMP_VAL; 2731 break; 2732 case RTW89_CHANNEL_WIDTH_20: 2733 fallthrough; 2734 default: 2735 under_region += PD_TH_BW20_CMP_VAL; 2736 break; 2737 } 2738 2739 dig->dyn_pd_th_max = dig->igi_rssi; 2740 2741 final_rssi = min_t(u8, rssi, dig->igi_rssi); 2742 final_rssi = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, 2743 PD_TH_MAX_RSSI + under_region); 2744 2745 if (enable) { 2746 val = (final_rssi - under_region - PD_TH_MIN_RSSI) >> 1; 2747 rtw89_debug(rtwdev, RTW89_DBG_DIG, 2748 "dyn_max=%d, final_rssi=%d, total=%d, PD_low=%d\n", 2749 dig->igi_rssi, final_rssi, under_region, val); 2750 } else { 2751 rtw89_debug(rtwdev, RTW89_DBG_DIG, 2752 "Dynamic PD th disabled, Set PD_low_bd=0\n"); 2753 } 2754 2755 rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, B_SEG0R_PD_LOWER_BOUND_MSK, 2756 val); 2757 rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, 2758 B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, enable); 2759 } 2760 2761 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) 2762 { 2763 struct rtw89_dig_info *dig = &rtwdev->dig; 2764 2765 dig->bypass_dig = false; 2766 rtw89_phy_dig_para_reset(rtwdev); 2767 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 2768 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false); 2769 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 2770 rtw89_phy_dig_update_para(rtwdev); 2771 } 2772 2773 #define IGI_RSSI_MIN 10 2774 void rtw89_phy_dig(struct rtw89_dev *rtwdev) 2775 { 2776 struct rtw89_dig_info *dig = &rtwdev->dig; 2777 bool is_linked = rtwdev->total_sta_assoc > 0; 2778 2779 if (unlikely(dig->bypass_dig)) { 2780 dig->bypass_dig = false; 2781 return; 2782 } 2783 2784 if (!dig->is_linked_pre && is_linked) { 2785 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); 2786 rtw89_phy_dig_update_para(rtwdev); 2787 } else if (dig->is_linked_pre && !is_linked) { 2788 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); 2789 rtw89_phy_dig_update_para(rtwdev); 2790 } 2791 dig->is_linked_pre = is_linked; 2792 2793 rtw89_phy_dig_igi_offset_by_env(rtwdev); 2794 rtw89_phy_dig_update_rssi_info(rtwdev); 2795 2796 dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ? 2797 dig->igi_rssi - IGI_RSSI_MIN : 0; 2798 dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX; 2799 dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst; 2800 2801 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, 2802 dig->dyn_igi_max); 2803 2804 rtw89_debug(rtwdev, RTW89_DBG_DIG, 2805 "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n", 2806 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, 2807 dig->igi_fa_rssi); 2808 2809 if (dig->force_gaincode_idx_en) { 2810 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 2811 rtw89_debug(rtwdev, RTW89_DBG_DIG, 2812 "Force gaincode index enabled.\n"); 2813 } else { 2814 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi, 2815 &dig->cur_gaincode); 2816 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode); 2817 } 2818 2819 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en); 2820 2821 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) 2822 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true); 2823 else 2824 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 2825 } 2826 2827 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) 2828 { 2829 rtw89_phy_ccx_top_setting_init(rtwdev); 2830 rtw89_phy_ifs_clm_setting_init(rtwdev); 2831 } 2832 2833 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 2834 { 2835 const struct rtw89_chip_info *chip = rtwdev->chip; 2836 2837 rtw89_phy_stat_init(rtwdev); 2838 2839 rtw89_chip_bb_sethw(rtwdev); 2840 2841 rtw89_phy_env_monitor_init(rtwdev); 2842 rtw89_phy_dig_init(rtwdev); 2843 rtw89_phy_cfo_init(rtwdev); 2844 2845 rtw89_phy_init_rf_nctl(rtwdev); 2846 rtw89_chip_rfk_init(rtwdev); 2847 rtw89_load_txpwr_table(rtwdev, chip->byr_table); 2848 rtw89_chip_set_txpwr_ctrl(rtwdev); 2849 rtw89_chip_power_trim(rtwdev); 2850 } 2851 2852 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 2853 { 2854 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 2855 u8 bss_color; 2856 2857 if (!vif->bss_conf.he_support || !vif->bss_conf.assoc) 2858 return; 2859 2860 bss_color = vif->bss_conf.he_bss_color.color; 2861 2862 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0, 0x1, 2863 phy_idx); 2864 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_TGT, bss_color, 2865 phy_idx); 2866 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_STAID, 2867 vif->bss_conf.aid, phy_idx); 2868 } 2869