1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "debug.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "ps.h" 10 #include "reg.h" 11 #include "sar.h" 12 #include "coex.h" 13 14 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, 15 const struct rtw89_ra_report *report) 16 { 17 const struct rate_info *txrate = &report->txrate; 18 u32 bit_rate = report->bit_rate; 19 u8 mcs; 20 21 /* lower than ofdm, do not aggregate */ 22 if (bit_rate < 550) 23 return 1; 24 25 /* prevent hardware rate fallback to G mode rate */ 26 if (txrate->flags & RATE_INFO_FLAGS_MCS) 27 mcs = txrate->mcs & 0x07; 28 else if (txrate->flags & (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_HE_MCS)) 29 mcs = txrate->mcs; 30 else 31 mcs = 0; 32 33 if (mcs <= 2) 34 return 1; 35 36 /* lower than 20M vht 2ss mcs8, make it small */ 37 if (bit_rate < 1800) 38 return 1200; 39 40 /* lower than 40M vht 2ss mcs9, make it medium */ 41 if (bit_rate < 4000) 42 return 2600; 43 44 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ 45 if (bit_rate < 7000) 46 return 3500; 47 48 return rtwdev->chip->max_amsdu_limit; 49 } 50 51 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) 52 { 53 u64 ra_mask = 0; 54 u8 mcs_cap; 55 int i, nss; 56 57 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { 58 mcs_cap = mcs_map & 0x3; 59 switch (mcs_cap) { 60 case 2: 61 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; 62 break; 63 case 1: 64 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; 65 break; 66 case 0: 67 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; 68 break; 69 default: 70 break; 71 } 72 } 73 74 return ra_mask; 75 } 76 77 static u64 get_he_ra_mask(struct ieee80211_sta *sta) 78 { 79 struct ieee80211_sta_he_cap cap = sta->deflink.he_cap; 80 u16 mcs_map; 81 82 switch (sta->deflink.bandwidth) { 83 case IEEE80211_STA_RX_BW_160: 84 if (cap.he_cap_elem.phy_cap_info[0] & 85 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) 86 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); 87 else 88 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); 89 break; 90 default: 91 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); 92 } 93 94 /* MCS11, MCS9, MCS7 */ 95 return get_mcs_ra_mask(mcs_map, 11, 2); 96 } 97 98 #define RA_FLOOR_TABLE_SIZE 7 99 #define RA_FLOOR_UP_GAP 3 100 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, 101 u8 ratr_state) 102 { 103 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; 104 u8 rssi_lv = 0; 105 u8 i; 106 107 rssi >>= 1; 108 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 109 if (i >= ratr_state) 110 rssi_lv_t[i] += RA_FLOOR_UP_GAP; 111 if (rssi < rssi_lv_t[i]) { 112 rssi_lv = i; 113 break; 114 } 115 } 116 if (rssi_lv == 0) 117 return 0xffffffffffffffffULL; 118 else if (rssi_lv == 1) 119 return 0xfffffffffffffff0ULL; 120 else if (rssi_lv == 2) 121 return 0xffffffffffffefe0ULL; 122 else if (rssi_lv == 3) 123 return 0xffffffffffffcfc0ULL; 124 else if (rssi_lv == 4) 125 return 0xffffffffffff8f80ULL; 126 else if (rssi_lv >= 5) 127 return 0xffffffffffff0f00ULL; 128 129 return 0xffffffffffffffffULL; 130 } 131 132 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak) 133 { 134 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 135 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 136 137 if (ra_mask == 0) 138 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 139 140 return ra_mask; 141 } 142 143 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 144 { 145 struct rtw89_hal *hal = &rtwdev->hal; 146 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 147 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 148 enum nl80211_band band; 149 u64 cfg_mask; 150 151 if (!rtwsta->use_cfg_mask) 152 return -1; 153 154 switch (hal->current_band_type) { 155 case RTW89_BAND_2G: 156 band = NL80211_BAND_2GHZ; 157 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, 158 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); 159 break; 160 case RTW89_BAND_5G: 161 band = NL80211_BAND_5GHZ; 162 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, 163 RA_MASK_OFDM_RATES); 164 break; 165 case RTW89_BAND_6G: 166 band = NL80211_BAND_6GHZ; 167 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy, 168 RA_MASK_OFDM_RATES); 169 break; 170 default: 171 rtw89_warn(rtwdev, "unhandled band type %d\n", hal->current_band_type); 172 return -1; 173 } 174 175 if (sta->deflink.he_cap.has_he) { 176 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], 177 RA_MASK_HE_1SS_RATES); 178 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], 179 RA_MASK_HE_2SS_RATES); 180 } else if (sta->deflink.vht_cap.vht_supported) { 181 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 182 RA_MASK_VHT_1SS_RATES); 183 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 184 RA_MASK_VHT_2SS_RATES); 185 } else if (sta->deflink.ht_cap.ht_supported) { 186 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 187 RA_MASK_HT_1SS_RATES); 188 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 189 RA_MASK_HT_2SS_RATES); 190 } 191 192 return cfg_mask; 193 } 194 195 static const u64 196 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, 197 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; 198 static const u64 199 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 200 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; 201 static const u64 202 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, 203 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; 204 205 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 206 struct ieee80211_sta *sta, bool csi) 207 { 208 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 209 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 210 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 211 struct rtw89_ra_info *ra = &rtwsta->ra; 212 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; 213 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 214 u64 ra_mask = 0; 215 u64 ra_mask_bak; 216 u8 mode = 0; 217 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; 218 u8 bw_mode = 0; 219 u8 stbc_en = 0; 220 u8 ldpc_en = 0; 221 u8 i; 222 bool sgi = false; 223 224 memset(ra, 0, sizeof(*ra)); 225 /* Set the ra mask from sta's capability */ 226 if (sta->deflink.he_cap.has_he) { 227 mode |= RTW89_RA_MODE_HE; 228 csi_mode = RTW89_RA_RPT_MODE_HE; 229 ra_mask |= get_he_ra_mask(sta); 230 high_rate_masks = rtw89_ra_mask_he_rates; 231 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[2] & 232 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) 233 stbc_en = 1; 234 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[1] & 235 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) 236 ldpc_en = 1; 237 } else if (sta->deflink.vht_cap.vht_supported) { 238 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 239 240 mode |= RTW89_RA_MODE_VHT; 241 csi_mode = RTW89_RA_RPT_MODE_VHT; 242 /* MCS9, MCS8, MCS7 */ 243 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); 244 high_rate_masks = rtw89_ra_mask_vht_rates; 245 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 246 stbc_en = 1; 247 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 248 ldpc_en = 1; 249 } else if (sta->deflink.ht_cap.ht_supported) { 250 mode |= RTW89_RA_MODE_HT; 251 csi_mode = RTW89_RA_RPT_MODE_HT; 252 ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 48) | 253 ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 36) | 254 (sta->deflink.ht_cap.mcs.rx_mask[1] << 24) | 255 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 256 high_rate_masks = rtw89_ra_mask_ht_rates; 257 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 258 stbc_en = 1; 259 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 260 ldpc_en = 1; 261 } 262 263 switch (rtwdev->hal.current_band_type) { 264 case RTW89_BAND_2G: 265 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 266 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] <= 0xf) 267 mode |= RTW89_RA_MODE_CCK; 268 else 269 mode |= RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM; 270 break; 271 case RTW89_BAND_5G: 272 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 273 mode |= RTW89_RA_MODE_OFDM; 274 break; 275 case RTW89_BAND_6G: 276 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_6GHZ] << 4; 277 mode |= RTW89_RA_MODE_OFDM; 278 break; 279 default: 280 rtw89_err(rtwdev, "Unknown band type\n"); 281 break; 282 } 283 284 ra_mask_bak = ra_mask; 285 286 if (mode >= RTW89_RA_MODE_HT) { 287 u64 mask = 0; 288 for (i = 0; i < rtwdev->hal.tx_nss; i++) 289 mask |= high_rate_masks[i]; 290 if (mode & RTW89_RA_MODE_OFDM) 291 mask |= RA_MASK_SUBOFDM_RATES; 292 if (mode & RTW89_RA_MODE_CCK) 293 mask |= RA_MASK_SUBCCK_RATES; 294 ra_mask &= mask; 295 } else if (mode & RTW89_RA_MODE_OFDM) { 296 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES); 297 } 298 299 if (mode != RTW89_RA_MODE_CCK) 300 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); 301 302 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak); 303 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 304 305 switch (sta->deflink.bandwidth) { 306 case IEEE80211_STA_RX_BW_160: 307 bw_mode = RTW89_CHANNEL_WIDTH_160; 308 sgi = sta->deflink.vht_cap.vht_supported && 309 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160); 310 break; 311 case IEEE80211_STA_RX_BW_80: 312 bw_mode = RTW89_CHANNEL_WIDTH_80; 313 sgi = sta->deflink.vht_cap.vht_supported && 314 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 315 break; 316 case IEEE80211_STA_RX_BW_40: 317 bw_mode = RTW89_CHANNEL_WIDTH_40; 318 sgi = sta->deflink.ht_cap.ht_supported && 319 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 320 break; 321 default: 322 bw_mode = RTW89_CHANNEL_WIDTH_20; 323 sgi = sta->deflink.ht_cap.ht_supported && 324 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 325 break; 326 } 327 328 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 329 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) 330 ra->dcm_cap = 1; 331 332 if (rate_pattern->enable) { 333 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 334 ra_mask &= rate_pattern->ra_mask; 335 mode = rate_pattern->ra_mode; 336 } 337 338 ra->bw_cap = bw_mode; 339 ra->mode_ctrl = mode; 340 ra->macid = rtwsta->mac_id; 341 ra->stbc_cap = stbc_en; 342 ra->ldpc_cap = ldpc_en; 343 ra->ss_num = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1; 344 ra->en_sgi = sgi; 345 ra->ra_mask = ra_mask; 346 347 if (!csi) 348 return; 349 350 ra->fixed_csi_rate_en = false; 351 ra->ra_csi_rate_en = true; 352 ra->cr_tbl_sel = false; 353 ra->band_num = rtwvif->phy_idx; 354 ra->csi_bw = bw_mode; 355 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; 356 ra->csi_mcs_ss_idx = 5; 357 ra->csi_mode = csi_mode; 358 } 359 360 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 361 u32 changed) 362 { 363 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 364 struct rtw89_ra_info *ra = &rtwsta->ra; 365 366 rtw89_phy_ra_sta_update(rtwdev, sta, false); 367 368 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) 369 ra->upd_mask = 1; 370 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED)) 371 ra->upd_bw_nss_mask = 1; 372 373 rtw89_debug(rtwdev, RTW89_DBG_RA, 374 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", 375 ra->macid, 376 ra->bw_cap, 377 ra->ss_num, 378 ra->en_sgi, 379 ra->giltf); 380 381 rtw89_fw_h2c_ra(rtwdev, ra, false); 382 } 383 384 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, 385 u16 rate_base, u64 ra_mask, u8 ra_mode, 386 u32 rate_ctrl, u32 ctrl_skip, bool force) 387 { 388 u8 n, c; 389 390 if (rate_ctrl == ctrl_skip) 391 return true; 392 393 n = hweight32(rate_ctrl); 394 if (n == 0) 395 return true; 396 397 if (force && n != 1) 398 return false; 399 400 if (next->enable) 401 return false; 402 403 c = __fls(rate_ctrl); 404 next->rate = rate_base + c; 405 next->ra_mode = ra_mode; 406 next->ra_mask = ra_mask; 407 next->enable = true; 408 409 return true; 410 } 411 412 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 413 struct ieee80211_vif *vif, 414 const struct cfg80211_bitrate_mask *mask) 415 { 416 struct ieee80211_supported_band *sband; 417 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 418 struct rtw89_phy_rate_pattern next_pattern = {0}; 419 static const u16 hw_rate_he[] = {RTW89_HW_RATE_HE_NSS1_MCS0, 420 RTW89_HW_RATE_HE_NSS2_MCS0, 421 RTW89_HW_RATE_HE_NSS3_MCS0, 422 RTW89_HW_RATE_HE_NSS4_MCS0}; 423 static const u16 hw_rate_vht[] = {RTW89_HW_RATE_VHT_NSS1_MCS0, 424 RTW89_HW_RATE_VHT_NSS2_MCS0, 425 RTW89_HW_RATE_VHT_NSS3_MCS0, 426 RTW89_HW_RATE_VHT_NSS4_MCS0}; 427 static const u16 hw_rate_ht[] = {RTW89_HW_RATE_MCS0, 428 RTW89_HW_RATE_MCS8, 429 RTW89_HW_RATE_MCS16, 430 RTW89_HW_RATE_MCS24}; 431 u8 band = rtwdev->hal.current_band_type; 432 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 433 u8 tx_nss = rtwdev->hal.tx_nss; 434 u8 i; 435 436 for (i = 0; i < tx_nss; i++) 437 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i], 438 RA_MASK_HE_RATES, RTW89_RA_MODE_HE, 439 mask->control[nl_band].he_mcs[i], 440 0, true)) 441 goto out; 442 443 for (i = 0; i < tx_nss; i++) 444 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i], 445 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, 446 mask->control[nl_band].vht_mcs[i], 447 0, true)) 448 goto out; 449 450 for (i = 0; i < tx_nss; i++) 451 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i], 452 RA_MASK_HT_RATES, RTW89_RA_MODE_HT, 453 mask->control[nl_band].ht_mcs[i], 454 0, true)) 455 goto out; 456 457 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and 458 * require at least one basic rate for ieee80211_set_bitrate_mask, 459 * so the decision just depends on if all bitrates are set or not. 460 */ 461 sband = rtwdev->hw->wiphy->bands[nl_band]; 462 if (band == RTW89_BAND_2G) { 463 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, 464 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, 465 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, 466 mask->control[nl_band].legacy, 467 BIT(sband->n_bitrates) - 1, false)) 468 goto out; 469 } else { 470 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, 471 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, 472 mask->control[nl_band].legacy, 473 BIT(sband->n_bitrates) - 1, false)) 474 goto out; 475 } 476 477 if (!next_pattern.enable) 478 goto out; 479 480 rtwvif->rate_pattern = next_pattern; 481 rtw89_debug(rtwdev, RTW89_DBG_RA, 482 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", 483 next_pattern.rate, 484 next_pattern.ra_mask, 485 next_pattern.ra_mode); 486 return; 487 488 out: 489 rtwvif->rate_pattern.enable = false; 490 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); 491 } 492 493 static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta) 494 { 495 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; 496 497 rtw89_phy_ra_updata_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED); 498 } 499 500 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) 501 { 502 ieee80211_iterate_stations_atomic(rtwdev->hw, 503 rtw89_phy_ra_updata_sta_iter, 504 rtwdev); 505 } 506 507 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) 508 { 509 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 510 struct rtw89_ra_info *ra = &rtwsta->ra; 511 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; 512 bool csi = rtw89_sta_has_beamformer_cap(sta); 513 514 rtw89_phy_ra_sta_update(rtwdev, sta, csi); 515 516 if (rssi > 40) 517 ra->init_rate_lv = 1; 518 else if (rssi > 20) 519 ra->init_rate_lv = 2; 520 else if (rssi > 1) 521 ra->init_rate_lv = 3; 522 else 523 ra->init_rate_lv = 0; 524 ra->upd_all = 1; 525 rtw89_debug(rtwdev, RTW89_DBG_RA, 526 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", 527 ra->macid, 528 ra->mode_ctrl, 529 ra->bw_cap, 530 ra->ss_num, 531 ra->init_rate_lv); 532 rtw89_debug(rtwdev, RTW89_DBG_RA, 533 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", 534 ra->dcm_cap, 535 ra->er_cap, 536 ra->ldpc_cap, 537 ra->stbc_cap, 538 ra->en_sgi, 539 ra->giltf); 540 541 rtw89_fw_h2c_ra(rtwdev, ra, csi); 542 } 543 544 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 545 struct rtw89_channel_params *param, 546 enum rtw89_bandwidth dbw) 547 { 548 enum rtw89_bandwidth cbw = param->bandwidth; 549 u8 pri_ch = param->primary_chan; 550 u8 central_ch = param->center_chan; 551 u8 txsc_idx = 0; 552 u8 tmp = 0; 553 554 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 555 return txsc_idx; 556 557 switch (cbw) { 558 case RTW89_CHANNEL_WIDTH_40: 559 txsc_idx = pri_ch > central_ch ? 1 : 2; 560 break; 561 case RTW89_CHANNEL_WIDTH_80: 562 if (dbw == RTW89_CHANNEL_WIDTH_20) { 563 if (pri_ch > central_ch) 564 txsc_idx = (pri_ch - central_ch) >> 1; 565 else 566 txsc_idx = ((central_ch - pri_ch) >> 1) + 1; 567 } else { 568 txsc_idx = pri_ch > central_ch ? 9 : 10; 569 } 570 break; 571 case RTW89_CHANNEL_WIDTH_160: 572 if (pri_ch > central_ch) 573 tmp = (pri_ch - central_ch) >> 1; 574 else 575 tmp = ((central_ch - pri_ch) >> 1) + 1; 576 577 if (dbw == RTW89_CHANNEL_WIDTH_20) { 578 txsc_idx = tmp; 579 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 580 if (tmp == 1 || tmp == 3) 581 txsc_idx = 9; 582 else if (tmp == 5 || tmp == 7) 583 txsc_idx = 11; 584 else if (tmp == 2 || tmp == 4) 585 txsc_idx = 10; 586 else if (tmp == 6 || tmp == 8) 587 txsc_idx = 12; 588 else 589 return 0xff; 590 } else { 591 txsc_idx = pri_ch > central_ch ? 13 : 14; 592 } 593 break; 594 case RTW89_CHANNEL_WIDTH_80_80: 595 if (dbw == RTW89_CHANNEL_WIDTH_20) { 596 if (pri_ch > central_ch) 597 txsc_idx = (10 - (pri_ch - central_ch)) >> 1; 598 else 599 txsc_idx = ((central_ch - pri_ch) >> 1) + 5; 600 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 601 txsc_idx = pri_ch > central_ch ? 10 : 12; 602 } else { 603 txsc_idx = 14; 604 } 605 break; 606 default: 607 break; 608 } 609 610 return txsc_idx; 611 } 612 EXPORT_SYMBOL(rtw89_phy_get_txsc); 613 614 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev) 615 { 616 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) || 617 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1); 618 } 619 620 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 621 u32 addr, u32 mask) 622 { 623 const struct rtw89_chip_info *chip = rtwdev->chip; 624 const u32 *base_addr = chip->rf_base_addr; 625 u32 val, direct_addr; 626 627 if (rf_path >= rtwdev->chip->rf_path_num) { 628 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 629 return INV_RF_DATA; 630 } 631 632 addr &= 0xff; 633 direct_addr = base_addr[rf_path] + (addr << 2); 634 mask &= RFREG_MASK; 635 636 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); 637 638 return val; 639 } 640 EXPORT_SYMBOL(rtw89_phy_read_rf); 641 642 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev, 643 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 644 { 645 bool busy; 646 bool done; 647 u32 val; 648 int ret; 649 650 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 651 1, 30, false, rtwdev); 652 if (ret) { 653 rtw89_err(rtwdev, "read rf busy swsi\n"); 654 return INV_RF_DATA; 655 } 656 657 mask &= RFREG_MASK; 658 659 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) | 660 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr); 661 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val); 662 udelay(2); 663 664 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1, 665 30, false, rtwdev, R_SWSI_V1, 666 B_SWSI_R_DATA_DONE_V1); 667 if (ret) { 668 rtw89_err(rtwdev, "read swsi busy\n"); 669 return INV_RF_DATA; 670 } 671 672 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask); 673 } 674 675 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 676 u32 addr, u32 mask) 677 { 678 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 679 680 if (rf_path >= rtwdev->chip->rf_path_num) { 681 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 682 return INV_RF_DATA; 683 } 684 685 if (ad_sel) 686 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 687 else 688 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask); 689 } 690 EXPORT_SYMBOL(rtw89_phy_read_rf_v1); 691 692 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 693 u32 addr, u32 mask, u32 data) 694 { 695 const struct rtw89_chip_info *chip = rtwdev->chip; 696 const u32 *base_addr = chip->rf_base_addr; 697 u32 direct_addr; 698 699 if (rf_path >= rtwdev->chip->rf_path_num) { 700 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 701 return false; 702 } 703 704 addr &= 0xff; 705 direct_addr = base_addr[rf_path] + (addr << 2); 706 mask &= RFREG_MASK; 707 708 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); 709 710 /* delay to ensure writing properly */ 711 udelay(1); 712 713 return true; 714 } 715 EXPORT_SYMBOL(rtw89_phy_write_rf); 716 717 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev, 718 enum rtw89_rf_path rf_path, u32 addr, u32 mask, 719 u32 data) 720 { 721 u8 bit_shift; 722 u32 val; 723 bool busy, b_msk_en = false; 724 int ret; 725 726 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 727 1, 30, false, rtwdev); 728 if (ret) { 729 rtw89_err(rtwdev, "write rf busy swsi\n"); 730 return false; 731 } 732 733 data &= RFREG_MASK; 734 mask &= RFREG_MASK; 735 736 if (mask != RFREG_MASK) { 737 b_msk_en = true; 738 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK, 739 mask); 740 bit_shift = __ffs(mask); 741 data = (data << bit_shift) & RFREG_MASK; 742 } 743 744 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) | 745 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) | 746 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) | 747 FIELD_PREP(B_SWSI_DATA_VAL_V1, data); 748 749 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val); 750 751 return true; 752 } 753 754 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 755 u32 addr, u32 mask, u32 data) 756 { 757 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 758 759 if (rf_path >= rtwdev->chip->rf_path_num) { 760 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 761 return false; 762 } 763 764 if (ad_sel) 765 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 766 else 767 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data); 768 } 769 EXPORT_SYMBOL(rtw89_phy_write_rf_v1); 770 771 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, 772 enum rtw89_phy_idx phy_idx) 773 { 774 const struct rtw89_chip_info *chip = rtwdev->chip; 775 776 chip->ops->bb_reset(rtwdev, phy_idx); 777 } 778 779 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, 780 const struct rtw89_reg2_def *reg, 781 enum rtw89_rf_path rf_path, 782 void *extra_data) 783 { 784 if (reg->addr == 0xfe) 785 mdelay(50); 786 else if (reg->addr == 0xfd) 787 mdelay(5); 788 else if (reg->addr == 0xfc) 789 mdelay(1); 790 else if (reg->addr == 0xfb) 791 udelay(50); 792 else if (reg->addr == 0xfa) 793 udelay(5); 794 else if (reg->addr == 0xf9) 795 udelay(1); 796 else 797 rtw89_phy_write32(rtwdev, reg->addr, reg->data); 798 } 799 800 union rtw89_phy_bb_gain_arg { 801 u32 addr; 802 struct { 803 union { 804 u8 type; 805 struct { 806 u8 rxsc_start:4; 807 u8 bw:4; 808 }; 809 }; 810 u8 path; 811 u8 gain_band; 812 u8 cfg_type; 813 }; 814 } __packed; 815 816 static void 817 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev, 818 union rtw89_phy_bb_gain_arg arg, u32 data) 819 { 820 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 821 u8 type = arg.type; 822 u8 path = arg.path; 823 u8 gband = arg.gain_band; 824 int i; 825 826 switch (type) { 827 case 0: 828 for (i = 0; i < 4; i++, data >>= 8) 829 gain->lna_gain[gband][path][i] = data & 0xff; 830 break; 831 case 1: 832 for (i = 4; i < 7; i++, data >>= 8) 833 gain->lna_gain[gband][path][i] = data & 0xff; 834 break; 835 case 2: 836 for (i = 0; i < 2; i++, data >>= 8) 837 gain->tia_gain[gband][path][i] = data & 0xff; 838 break; 839 default: 840 rtw89_warn(rtwdev, 841 "bb gain error {0x%x:0x%x} with unknown type: %d\n", 842 arg.addr, data, type); 843 break; 844 } 845 } 846 847 enum rtw89_phy_bb_rxsc_start_idx { 848 RTW89_BB_RXSC_START_IDX_FULL = 0, 849 RTW89_BB_RXSC_START_IDX_20 = 1, 850 RTW89_BB_RXSC_START_IDX_20_1 = 5, 851 RTW89_BB_RXSC_START_IDX_40 = 9, 852 RTW89_BB_RXSC_START_IDX_80 = 13, 853 }; 854 855 static void 856 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev, 857 union rtw89_phy_bb_gain_arg arg, u32 data) 858 { 859 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 860 u8 rxsc_start = arg.rxsc_start; 861 u8 bw = arg.bw; 862 u8 path = arg.path; 863 u8 gband = arg.gain_band; 864 u8 rxsc; 865 s8 ofst; 866 int i; 867 868 switch (bw) { 869 case RTW89_CHANNEL_WIDTH_20: 870 gain->rpl_ofst_20[gband][path] = (s8)data; 871 break; 872 case RTW89_CHANNEL_WIDTH_40: 873 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 874 gain->rpl_ofst_40[gband][path][0] = (s8)data; 875 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 876 for (i = 0; i < 2; i++, data >>= 8) { 877 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 878 ofst = (s8)(data & 0xff); 879 gain->rpl_ofst_40[gband][path][rxsc] = ofst; 880 } 881 } 882 break; 883 case RTW89_CHANNEL_WIDTH_80: 884 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 885 gain->rpl_ofst_80[gband][path][0] = (s8)data; 886 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 887 for (i = 0; i < 4; i++, data >>= 8) { 888 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 889 ofst = (s8)(data & 0xff); 890 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 891 } 892 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 893 for (i = 0; i < 2; i++, data >>= 8) { 894 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 895 ofst = (s8)(data & 0xff); 896 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 897 } 898 } 899 break; 900 case RTW89_CHANNEL_WIDTH_160: 901 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 902 gain->rpl_ofst_160[gband][path][0] = (s8)data; 903 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 904 for (i = 0; i < 4; i++, data >>= 8) { 905 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 906 ofst = (s8)(data & 0xff); 907 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 908 } 909 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) { 910 for (i = 0; i < 4; i++, data >>= 8) { 911 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i; 912 ofst = (s8)(data & 0xff); 913 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 914 } 915 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 916 for (i = 0; i < 4; i++, data >>= 8) { 917 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 918 ofst = (s8)(data & 0xff); 919 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 920 } 921 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) { 922 for (i = 0; i < 2; i++, data >>= 8) { 923 rxsc = RTW89_BB_RXSC_START_IDX_80 + i; 924 ofst = (s8)(data & 0xff); 925 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 926 } 927 } 928 break; 929 default: 930 rtw89_warn(rtwdev, 931 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n", 932 arg.addr, data, bw); 933 break; 934 } 935 } 936 937 static void 938 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev, 939 union rtw89_phy_bb_gain_arg arg, u32 data) 940 { 941 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 942 u8 type = arg.type; 943 u8 path = arg.path; 944 u8 gband = arg.gain_band; 945 int i; 946 947 switch (type) { 948 case 0: 949 for (i = 0; i < 4; i++, data >>= 8) 950 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 951 break; 952 case 1: 953 for (i = 4; i < 7; i++, data >>= 8) 954 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 955 break; 956 default: 957 rtw89_warn(rtwdev, 958 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n", 959 arg.addr, data, type); 960 break; 961 } 962 } 963 964 static void 965 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev, 966 union rtw89_phy_bb_gain_arg arg, u32 data) 967 { 968 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 969 u8 type = arg.type; 970 u8 path = arg.path; 971 u8 gband = arg.gain_band; 972 int i; 973 974 switch (type) { 975 case 0: 976 for (i = 0; i < 4; i++, data >>= 8) 977 gain->lna_op1db[gband][path][i] = data & 0xff; 978 break; 979 case 1: 980 for (i = 4; i < 7; i++, data >>= 8) 981 gain->lna_op1db[gband][path][i] = data & 0xff; 982 break; 983 case 2: 984 for (i = 0; i < 4; i++, data >>= 8) 985 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 986 break; 987 case 3: 988 for (i = 4; i < 8; i++, data >>= 8) 989 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 990 break; 991 default: 992 rtw89_warn(rtwdev, 993 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n", 994 arg.addr, data, type); 995 break; 996 } 997 } 998 999 static void rtw89_phy_config_bb_gain(struct rtw89_dev *rtwdev, 1000 const struct rtw89_reg2_def *reg, 1001 enum rtw89_rf_path rf_path, 1002 void *extra_data) 1003 { 1004 const struct rtw89_chip_info *chip = rtwdev->chip; 1005 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr }; 1006 1007 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR) 1008 return; 1009 1010 if (arg.path >= chip->rf_path_num) 1011 return; 1012 1013 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) { 1014 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n"); 1015 return; 1016 } 1017 1018 switch (arg.cfg_type) { 1019 case 0: 1020 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data); 1021 break; 1022 case 1: 1023 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data); 1024 break; 1025 case 2: 1026 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data); 1027 break; 1028 case 3: 1029 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data); 1030 break; 1031 default: 1032 rtw89_warn(rtwdev, 1033 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n", 1034 arg.addr, reg->data, arg.cfg_type); 1035 break; 1036 } 1037 } 1038 1039 static void 1040 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, 1041 const struct rtw89_reg2_def *reg, 1042 enum rtw89_rf_path rf_path, 1043 struct rtw89_fw_h2c_rf_reg_info *info) 1044 { 1045 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; 1046 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 1047 1048 if (page >= RTW89_H2C_RF_PAGE_NUM) { 1049 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d", 1050 rf_path, info->curr_idx); 1051 return; 1052 } 1053 1054 info->rtw89_phy_config_rf_h2c[page][idx] = 1055 cpu_to_le32((reg->addr << 20) | reg->data); 1056 info->curr_idx++; 1057 } 1058 1059 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, 1060 struct rtw89_fw_h2c_rf_reg_info *info) 1061 { 1062 u16 remain = info->curr_idx; 1063 u16 len = 0; 1064 u8 i; 1065 int ret = 0; 1066 1067 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) { 1068 rtw89_warn(rtwdev, 1069 "rf reg h2c total len %d larger than %d\n", 1070 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE); 1071 ret = -EINVAL; 1072 goto out; 1073 } 1074 1075 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) { 1076 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain; 1077 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i); 1078 if (ret) 1079 goto out; 1080 } 1081 out: 1082 info->curr_idx = 0; 1083 1084 return ret; 1085 } 1086 1087 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, 1088 const struct rtw89_reg2_def *reg, 1089 enum rtw89_rf_path rf_path, 1090 void *extra_data) 1091 { 1092 if (reg->addr == 0xfe) { 1093 mdelay(50); 1094 } else if (reg->addr == 0xfd) { 1095 mdelay(5); 1096 } else if (reg->addr == 0xfc) { 1097 mdelay(1); 1098 } else if (reg->addr == 0xfb) { 1099 udelay(50); 1100 } else if (reg->addr == 0xfa) { 1101 udelay(5); 1102 } else if (reg->addr == 0xf9) { 1103 udelay(1); 1104 } else { 1105 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); 1106 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1107 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1108 } 1109 } 1110 1111 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 1112 const struct rtw89_reg2_def *reg, 1113 enum rtw89_rf_path rf_path, 1114 void *extra_data) 1115 { 1116 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data); 1117 1118 if (reg->addr < 0x100) 1119 return; 1120 1121 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1122 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1123 } 1124 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1); 1125 1126 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, 1127 const struct rtw89_phy_table *table, 1128 u32 *headline_size, u32 *headline_idx, 1129 u8 rfe, u8 cv) 1130 { 1131 const struct rtw89_reg2_def *reg; 1132 u32 headline; 1133 u32 compare, target; 1134 u8 rfe_para, cv_para; 1135 u8 cv_max = 0; 1136 bool case_matched = false; 1137 u32 i; 1138 1139 for (i = 0; i < table->n_regs; i++) { 1140 reg = &table->regs[i]; 1141 headline = get_phy_headline(reg->addr); 1142 if (headline != PHY_HEADLINE_VALID) 1143 break; 1144 } 1145 *headline_size = i; 1146 if (*headline_size == 0) 1147 return 0; 1148 1149 /* case 1: RFE match, CV match */ 1150 compare = get_phy_compare(rfe, cv); 1151 for (i = 0; i < *headline_size; i++) { 1152 reg = &table->regs[i]; 1153 target = get_phy_target(reg->addr); 1154 if (target == compare) { 1155 *headline_idx = i; 1156 return 0; 1157 } 1158 } 1159 1160 /* case 2: RFE match, CV don't care */ 1161 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); 1162 for (i = 0; i < *headline_size; i++) { 1163 reg = &table->regs[i]; 1164 target = get_phy_target(reg->addr); 1165 if (target == compare) { 1166 *headline_idx = i; 1167 return 0; 1168 } 1169 } 1170 1171 /* case 3: RFE match, CV max in table */ 1172 for (i = 0; i < *headline_size; i++) { 1173 reg = &table->regs[i]; 1174 rfe_para = get_phy_cond_rfe(reg->addr); 1175 cv_para = get_phy_cond_cv(reg->addr); 1176 if (rfe_para == rfe) { 1177 if (cv_para >= cv_max) { 1178 cv_max = cv_para; 1179 *headline_idx = i; 1180 case_matched = true; 1181 } 1182 } 1183 } 1184 1185 if (case_matched) 1186 return 0; 1187 1188 /* case 4: RFE don't care, CV max in table */ 1189 for (i = 0; i < *headline_size; i++) { 1190 reg = &table->regs[i]; 1191 rfe_para = get_phy_cond_rfe(reg->addr); 1192 cv_para = get_phy_cond_cv(reg->addr); 1193 if (rfe_para == PHY_COND_DONT_CARE) { 1194 if (cv_para >= cv_max) { 1195 cv_max = cv_para; 1196 *headline_idx = i; 1197 case_matched = true; 1198 } 1199 } 1200 } 1201 1202 if (case_matched) 1203 return 0; 1204 1205 return -EINVAL; 1206 } 1207 1208 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, 1209 const struct rtw89_phy_table *table, 1210 void (*config)(struct rtw89_dev *rtwdev, 1211 const struct rtw89_reg2_def *reg, 1212 enum rtw89_rf_path rf_path, 1213 void *data), 1214 void *extra_data) 1215 { 1216 const struct rtw89_reg2_def *reg; 1217 enum rtw89_rf_path rf_path = table->rf_path; 1218 u8 rfe = rtwdev->efuse.rfe_type; 1219 u8 cv = rtwdev->hal.cv; 1220 u32 i; 1221 u32 headline_size = 0, headline_idx = 0; 1222 u32 target = 0, cfg_target; 1223 u8 cond; 1224 bool is_matched = true; 1225 bool target_found = false; 1226 int ret; 1227 1228 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, 1229 &headline_idx, rfe, cv); 1230 if (ret) { 1231 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); 1232 return; 1233 } 1234 1235 cfg_target = get_phy_target(table->regs[headline_idx].addr); 1236 for (i = headline_size; i < table->n_regs; i++) { 1237 reg = &table->regs[i]; 1238 cond = get_phy_cond(reg->addr); 1239 switch (cond) { 1240 case PHY_COND_BRANCH_IF: 1241 case PHY_COND_BRANCH_ELIF: 1242 target = get_phy_target(reg->addr); 1243 break; 1244 case PHY_COND_BRANCH_ELSE: 1245 is_matched = false; 1246 if (!target_found) { 1247 rtw89_warn(rtwdev, "failed to load CR %x/%x\n", 1248 reg->addr, reg->data); 1249 return; 1250 } 1251 break; 1252 case PHY_COND_BRANCH_END: 1253 is_matched = true; 1254 target_found = false; 1255 break; 1256 case PHY_COND_CHECK: 1257 if (target_found) { 1258 is_matched = false; 1259 break; 1260 } 1261 1262 if (target == cfg_target) { 1263 is_matched = true; 1264 target_found = true; 1265 } else { 1266 is_matched = false; 1267 target_found = false; 1268 } 1269 break; 1270 default: 1271 if (is_matched) 1272 config(rtwdev, reg, rf_path, extra_data); 1273 break; 1274 } 1275 } 1276 } 1277 1278 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) 1279 { 1280 const struct rtw89_chip_info *chip = rtwdev->chip; 1281 const struct rtw89_phy_table *bb_table = chip->bb_table; 1282 const struct rtw89_phy_table *bb_gain_table = chip->bb_gain_table; 1283 1284 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); 1285 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 1286 if (bb_gain_table) 1287 rtw89_phy_init_reg(rtwdev, bb_gain_table, 1288 rtw89_phy_config_bb_gain, NULL); 1289 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); 1290 } 1291 1292 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 1293 { 1294 rtw89_phy_write32(rtwdev, 0x8080, 0x4); 1295 udelay(1); 1296 return rtw89_phy_read32(rtwdev, 0x8080); 1297 } 1298 1299 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev) 1300 { 1301 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 1302 enum rtw89_rf_path rf_path, void *data); 1303 const struct rtw89_chip_info *chip = rtwdev->chip; 1304 const struct rtw89_phy_table *rf_table; 1305 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; 1306 u8 path; 1307 1308 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); 1309 if (!rf_reg_info) 1310 return; 1311 1312 for (path = RF_PATH_A; path < chip->rf_path_num; path++) { 1313 rf_table = chip->rf_table[path]; 1314 rf_reg_info->rf_path = rf_table->rf_path; 1315 config = rf_table->config ? rf_table->config : rtw89_phy_config_rf_reg; 1316 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info); 1317 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) 1318 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", 1319 rf_reg_info->rf_path); 1320 } 1321 kfree(rf_reg_info); 1322 } 1323 1324 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) 1325 { 1326 const struct rtw89_chip_info *chip = rtwdev->chip; 1327 const struct rtw89_phy_table *nctl_table; 1328 u32 val; 1329 int ret; 1330 1331 /* IQK/DPK clock & reset */ 1332 rtw89_phy_write32_set(rtwdev, 0x0c60, 0x3); 1333 rtw89_phy_write32_set(rtwdev, 0x0c6c, 0x1); 1334 rtw89_phy_write32_set(rtwdev, 0x58ac, 0x8000000); 1335 rtw89_phy_write32_set(rtwdev, 0x78ac, 0x8000000); 1336 1337 /* check 0x8080 */ 1338 rtw89_phy_write32(rtwdev, 0x8000, 0x8); 1339 1340 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, 1341 1000, false, rtwdev); 1342 if (ret) 1343 rtw89_err(rtwdev, "failed to poll nctl block\n"); 1344 1345 nctl_table = chip->nctl_table; 1346 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); 1347 } 1348 1349 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) 1350 { 1351 u32 phy_page = addr >> 8; 1352 u32 ofst = 0; 1353 1354 switch (phy_page) { 1355 case 0x6: 1356 case 0x7: 1357 case 0x8: 1358 case 0x9: 1359 case 0xa: 1360 case 0xb: 1361 case 0xc: 1362 case 0xd: 1363 case 0x19: 1364 case 0x1a: 1365 case 0x1b: 1366 ofst = 0x2000; 1367 break; 1368 default: 1369 /* warning case */ 1370 ofst = 0; 1371 break; 1372 } 1373 1374 if (phy_page >= 0x40 && phy_page <= 0x4f) 1375 ofst = 0x2000; 1376 1377 return ofst; 1378 } 1379 1380 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1381 u32 data, enum rtw89_phy_idx phy_idx) 1382 { 1383 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1384 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1385 rtw89_phy_write32_mask(rtwdev, addr, mask, data); 1386 } 1387 EXPORT_SYMBOL(rtw89_phy_write32_idx); 1388 1389 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1390 u32 val) 1391 { 1392 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 1393 1394 if (!rtwdev->dbcc_en) 1395 return; 1396 1397 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 1398 } 1399 1400 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 1401 const struct rtw89_phy_reg3_tbl *tbl) 1402 { 1403 const struct rtw89_reg3_def *reg3; 1404 int i; 1405 1406 for (i = 0; i < tbl->size; i++) { 1407 reg3 = &tbl->reg3[i]; 1408 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); 1409 } 1410 } 1411 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl); 1412 1413 const u8 rtw89_rs_idx_max[] = { 1414 [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX, 1415 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX, 1416 [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX, 1417 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX, 1418 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX, 1419 }; 1420 EXPORT_SYMBOL(rtw89_rs_idx_max); 1421 1422 const u8 rtw89_rs_nss_max[] = { 1423 [RTW89_RS_CCK] = 1, 1424 [RTW89_RS_OFDM] = 1, 1425 [RTW89_RS_MCS] = RTW89_NSS_MAX, 1426 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX, 1427 [RTW89_RS_OFFSET] = 1, 1428 }; 1429 EXPORT_SYMBOL(rtw89_rs_nss_max); 1430 1431 static const u8 _byr_of_rs[] = { 1432 [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck), 1433 [RTW89_RS_OFDM] = offsetof(struct rtw89_txpwr_byrate, ofdm), 1434 [RTW89_RS_MCS] = offsetof(struct rtw89_txpwr_byrate, mcs), 1435 [RTW89_RS_HEDCM] = offsetof(struct rtw89_txpwr_byrate, hedcm), 1436 [RTW89_RS_OFFSET] = offsetof(struct rtw89_txpwr_byrate, offset), 1437 }; 1438 1439 #define _byr_seek(rs, raw) ((s8 *)(raw) + _byr_of_rs[rs]) 1440 #define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_max[rs] + (idx)) 1441 #define _byr_chk(rs, nss, idx) \ 1442 ((nss) < rtw89_rs_nss_max[rs] && (idx) < rtw89_rs_idx_max[rs]) 1443 1444 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 1445 const struct rtw89_txpwr_table *tbl) 1446 { 1447 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; 1448 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; 1449 s8 *byr; 1450 u32 data; 1451 u8 i, idx; 1452 1453 for (; cfg < end; cfg++) { 1454 byr = _byr_seek(cfg->rs, &rtwdev->byr[cfg->band]); 1455 data = cfg->data; 1456 1457 for (i = 0; i < cfg->len; i++, data >>= 8) { 1458 idx = _byr_idx(cfg->rs, cfg->nss, (cfg->shf + i)); 1459 byr[idx] = (s8)(data & 0xff); 1460 } 1461 } 1462 } 1463 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate); 1464 1465 #define _phy_txpwr_rf_to_mac(rtwdev, txpwr_rf) \ 1466 ({ \ 1467 const struct rtw89_chip_info *__c = (rtwdev)->chip; \ 1468 (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \ 1469 }) 1470 1471 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, 1472 const struct rtw89_rate_desc *rate_desc) 1473 { 1474 enum rtw89_band band = rtwdev->hal.current_band_type; 1475 s8 *byr; 1476 u8 idx; 1477 1478 if (rate_desc->rs == RTW89_RS_CCK) 1479 band = RTW89_BAND_2G; 1480 1481 if (!_byr_chk(rate_desc->rs, rate_desc->nss, rate_desc->idx)) { 1482 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1483 "[TXPWR] unknown byrate desc rs=%d nss=%d idx=%d\n", 1484 rate_desc->rs, rate_desc->nss, rate_desc->idx); 1485 1486 return 0; 1487 } 1488 1489 byr = _byr_seek(rate_desc->rs, &rtwdev->byr[band]); 1490 idx = _byr_idx(rate_desc->rs, rate_desc->nss, rate_desc->idx); 1491 1492 return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]); 1493 } 1494 EXPORT_SYMBOL(rtw89_phy_read_txpwr_byrate); 1495 1496 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g) 1497 { 1498 switch (channel_6g) { 1499 case 1 ... 29: 1500 return (channel_6g - 1) / 2; 1501 case 33 ... 61: 1502 return (channel_6g - 3) / 2; 1503 case 65 ... 93: 1504 return (channel_6g - 5) / 2; 1505 case 97 ... 125: 1506 return (channel_6g - 7) / 2; 1507 case 129 ... 157: 1508 return (channel_6g - 9) / 2; 1509 case 161 ... 189: 1510 return (channel_6g - 11) / 2; 1511 case 193 ... 221: 1512 return (channel_6g - 13) / 2; 1513 case 225 ... 253: 1514 return (channel_6g - 15) / 2; 1515 default: 1516 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g); 1517 return 0; 1518 } 1519 } 1520 1521 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel) 1522 { 1523 if (band == RTW89_BAND_6G) 1524 return rtw89_channel_6g_to_idx(rtwdev, channel); 1525 1526 switch (channel) { 1527 case 1 ... 14: 1528 return channel - 1; 1529 case 36 ... 64: 1530 return (channel - 36) / 2; 1531 case 100 ... 144: 1532 return ((channel - 100) / 2) + 15; 1533 case 149 ... 177: 1534 return ((channel - 149) / 2) + 38; 1535 default: 1536 rtw89_warn(rtwdev, "unknown channel: %d\n", channel); 1537 return 0; 1538 } 1539 } 1540 1541 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, 1542 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) 1543 { 1544 const struct rtw89_chip_info *chip = rtwdev->chip; 1545 u8 band = rtwdev->hal.current_band_type; 1546 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1547 u8 regd = rtw89_regd_get(rtwdev, band); 1548 s8 lmt = 0, sar; 1549 1550 switch (band) { 1551 case RTW89_BAND_2G: 1552 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf][regd][ch_idx]; 1553 if (!lmt) 1554 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf] 1555 [RTW89_WW][ch_idx]; 1556 break; 1557 case RTW89_BAND_5G: 1558 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf][regd][ch_idx]; 1559 if (!lmt) 1560 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf] 1561 [RTW89_WW][ch_idx]; 1562 break; 1563 case RTW89_BAND_6G: 1564 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf][regd][ch_idx]; 1565 if (!lmt) 1566 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf] 1567 [RTW89_WW][ch_idx]; 1568 break; 1569 default: 1570 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1571 return 0; 1572 } 1573 1574 lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt); 1575 sar = rtw89_query_sar(rtwdev); 1576 1577 return min(lmt, sar); 1578 } 1579 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit); 1580 1581 #define __fill_txpwr_limit_nonbf_bf(ptr, bw, ntx, rs, ch) \ 1582 do { \ 1583 u8 __i; \ 1584 for (__i = 0; __i < RTW89_BF_NUM; __i++) \ 1585 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ 1586 bw, ntx, \ 1587 rs, __i, \ 1588 (ch)); \ 1589 } while (0) 1590 1591 static void rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev *rtwdev, 1592 struct rtw89_txpwr_limit *lmt, 1593 u8 ntx, u8 ch) 1594 { 1595 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, RTW89_CHANNEL_WIDTH_20, 1596 ntx, RTW89_RS_CCK, ch); 1597 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, RTW89_CHANNEL_WIDTH_40, 1598 ntx, RTW89_RS_CCK, ch); 1599 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, 1600 ntx, RTW89_RS_OFDM, ch); 1601 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, 1602 ntx, RTW89_RS_MCS, ch); 1603 } 1604 1605 static void rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev *rtwdev, 1606 struct rtw89_txpwr_limit *lmt, 1607 u8 ntx, u8 ch, u8 pri_ch) 1608 { 1609 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, RTW89_CHANNEL_WIDTH_20, 1610 ntx, RTW89_RS_CCK, ch - 2); 1611 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, RTW89_CHANNEL_WIDTH_40, 1612 ntx, RTW89_RS_CCK, ch); 1613 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, 1614 ntx, RTW89_RS_OFDM, pri_ch); 1615 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, 1616 ntx, RTW89_RS_MCS, ch - 2); 1617 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], RTW89_CHANNEL_WIDTH_20, 1618 ntx, RTW89_RS_MCS, ch + 2); 1619 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], RTW89_CHANNEL_WIDTH_40, 1620 ntx, RTW89_RS_MCS, ch); 1621 } 1622 1623 static void rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev *rtwdev, 1624 struct rtw89_txpwr_limit *lmt, 1625 u8 ntx, u8 ch, u8 pri_ch) 1626 { 1627 s8 val_0p5_n[RTW89_BF_NUM]; 1628 s8 val_0p5_p[RTW89_BF_NUM]; 1629 u8 i; 1630 1631 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, 1632 ntx, RTW89_RS_OFDM, pri_ch); 1633 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, 1634 ntx, RTW89_RS_MCS, ch - 6); 1635 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], RTW89_CHANNEL_WIDTH_20, 1636 ntx, RTW89_RS_MCS, ch - 2); 1637 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], RTW89_CHANNEL_WIDTH_20, 1638 ntx, RTW89_RS_MCS, ch + 2); 1639 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], RTW89_CHANNEL_WIDTH_20, 1640 ntx, RTW89_RS_MCS, ch + 6); 1641 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], RTW89_CHANNEL_WIDTH_40, 1642 ntx, RTW89_RS_MCS, ch - 4); 1643 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], RTW89_CHANNEL_WIDTH_40, 1644 ntx, RTW89_RS_MCS, ch + 4); 1645 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], RTW89_CHANNEL_WIDTH_80, 1646 ntx, RTW89_RS_MCS, ch); 1647 1648 __fill_txpwr_limit_nonbf_bf(val_0p5_n, RTW89_CHANNEL_WIDTH_40, 1649 ntx, RTW89_RS_MCS, ch - 4); 1650 __fill_txpwr_limit_nonbf_bf(val_0p5_p, RTW89_CHANNEL_WIDTH_40, 1651 ntx, RTW89_RS_MCS, ch + 4); 1652 1653 for (i = 0; i < RTW89_BF_NUM; i++) 1654 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1655 } 1656 1657 static void rtw89_phy_fill_txpwr_limit_160m(struct rtw89_dev *rtwdev, 1658 struct rtw89_txpwr_limit *lmt, 1659 u8 ntx, u8 ch, u8 pri_ch) 1660 { 1661 s8 val_0p5_n[RTW89_BF_NUM]; 1662 s8 val_0p5_p[RTW89_BF_NUM]; 1663 s8 val_2p5_n[RTW89_BF_NUM]; 1664 s8 val_2p5_p[RTW89_BF_NUM]; 1665 u8 i; 1666 1667 /* fill ofdm section */ 1668 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, 1669 ntx, RTW89_RS_OFDM, pri_ch); 1670 1671 /* fill mcs 20m section */ 1672 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, 1673 ntx, RTW89_RS_MCS, ch - 14); 1674 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], RTW89_CHANNEL_WIDTH_20, 1675 ntx, RTW89_RS_MCS, ch - 10); 1676 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], RTW89_CHANNEL_WIDTH_20, 1677 ntx, RTW89_RS_MCS, ch - 6); 1678 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], RTW89_CHANNEL_WIDTH_20, 1679 ntx, RTW89_RS_MCS, ch - 2); 1680 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], RTW89_CHANNEL_WIDTH_20, 1681 ntx, RTW89_RS_MCS, ch + 2); 1682 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], RTW89_CHANNEL_WIDTH_20, 1683 ntx, RTW89_RS_MCS, ch + 6); 1684 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], RTW89_CHANNEL_WIDTH_20, 1685 ntx, RTW89_RS_MCS, ch + 10); 1686 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], RTW89_CHANNEL_WIDTH_20, 1687 ntx, RTW89_RS_MCS, ch + 14); 1688 1689 /* fill mcs 40m section */ 1690 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], RTW89_CHANNEL_WIDTH_40, 1691 ntx, RTW89_RS_MCS, ch - 12); 1692 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], RTW89_CHANNEL_WIDTH_40, 1693 ntx, RTW89_RS_MCS, ch - 4); 1694 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], RTW89_CHANNEL_WIDTH_40, 1695 ntx, RTW89_RS_MCS, ch + 4); 1696 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], RTW89_CHANNEL_WIDTH_40, 1697 ntx, RTW89_RS_MCS, ch + 12); 1698 1699 /* fill mcs 80m section */ 1700 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], RTW89_CHANNEL_WIDTH_80, 1701 ntx, RTW89_RS_MCS, ch - 8); 1702 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], RTW89_CHANNEL_WIDTH_80, 1703 ntx, RTW89_RS_MCS, ch + 8); 1704 1705 /* fill mcs 160m section */ 1706 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, RTW89_CHANNEL_WIDTH_160, 1707 ntx, RTW89_RS_MCS, ch); 1708 1709 /* fill mcs 40m 0p5 section */ 1710 __fill_txpwr_limit_nonbf_bf(val_0p5_n, RTW89_CHANNEL_WIDTH_40, 1711 ntx, RTW89_RS_MCS, ch - 4); 1712 __fill_txpwr_limit_nonbf_bf(val_0p5_p, RTW89_CHANNEL_WIDTH_40, 1713 ntx, RTW89_RS_MCS, ch + 4); 1714 1715 for (i = 0; i < RTW89_BF_NUM; i++) 1716 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1717 1718 /* fill mcs 40m 2p5 section */ 1719 __fill_txpwr_limit_nonbf_bf(val_2p5_n, RTW89_CHANNEL_WIDTH_40, 1720 ntx, RTW89_RS_MCS, ch - 8); 1721 __fill_txpwr_limit_nonbf_bf(val_2p5_p, RTW89_CHANNEL_WIDTH_40, 1722 ntx, RTW89_RS_MCS, ch + 8); 1723 1724 for (i = 0; i < RTW89_BF_NUM; i++) 1725 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]); 1726 } 1727 1728 void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev, 1729 struct rtw89_txpwr_limit *lmt, 1730 u8 ntx) 1731 { 1732 u8 pri_ch = rtwdev->hal.current_primary_channel; 1733 u8 ch = rtwdev->hal.current_channel; 1734 u8 bw = rtwdev->hal.current_band_width; 1735 1736 memset(lmt, 0, sizeof(*lmt)); 1737 1738 switch (bw) { 1739 case RTW89_CHANNEL_WIDTH_20: 1740 rtw89_phy_fill_txpwr_limit_20m(rtwdev, lmt, ntx, ch); 1741 break; 1742 case RTW89_CHANNEL_WIDTH_40: 1743 rtw89_phy_fill_txpwr_limit_40m(rtwdev, lmt, ntx, ch, pri_ch); 1744 break; 1745 case RTW89_CHANNEL_WIDTH_80: 1746 rtw89_phy_fill_txpwr_limit_80m(rtwdev, lmt, ntx, ch, pri_ch); 1747 break; 1748 case RTW89_CHANNEL_WIDTH_160: 1749 rtw89_phy_fill_txpwr_limit_160m(rtwdev, lmt, ntx, ch, pri_ch); 1750 break; 1751 } 1752 } 1753 EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit); 1754 1755 static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, 1756 u8 ru, u8 ntx, u8 ch) 1757 { 1758 const struct rtw89_chip_info *chip = rtwdev->chip; 1759 u8 band = rtwdev->hal.current_band_type; 1760 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1761 u8 regd = rtw89_regd_get(rtwdev, band); 1762 s8 lmt_ru = 0, sar; 1763 1764 switch (band) { 1765 case RTW89_BAND_2G: 1766 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx][regd][ch_idx]; 1767 if (!lmt_ru) 1768 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx] 1769 [RTW89_WW][ch_idx]; 1770 break; 1771 case RTW89_BAND_5G: 1772 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx][regd][ch_idx]; 1773 if (!lmt_ru) 1774 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx] 1775 [RTW89_WW][ch_idx]; 1776 break; 1777 case RTW89_BAND_6G: 1778 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx][regd][ch_idx]; 1779 if (!lmt_ru) 1780 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx] 1781 [RTW89_WW][ch_idx]; 1782 break; 1783 default: 1784 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1785 return 0; 1786 } 1787 1788 lmt_ru = _phy_txpwr_rf_to_mac(rtwdev, lmt_ru); 1789 sar = rtw89_query_sar(rtwdev); 1790 1791 return min(lmt_ru, sar); 1792 } 1793 1794 static void 1795 rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev, 1796 struct rtw89_txpwr_limit_ru *lmt_ru, 1797 u8 ntx, u8 ch) 1798 { 1799 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1800 ntx, ch); 1801 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1802 ntx, ch); 1803 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1804 ntx, ch); 1805 } 1806 1807 static void 1808 rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev, 1809 struct rtw89_txpwr_limit_ru *lmt_ru, 1810 u8 ntx, u8 ch) 1811 { 1812 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1813 ntx, ch - 2); 1814 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1815 ntx, ch + 2); 1816 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1817 ntx, ch - 2); 1818 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1819 ntx, ch + 2); 1820 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1821 ntx, ch - 2); 1822 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1823 ntx, ch + 2); 1824 } 1825 1826 static void 1827 rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev, 1828 struct rtw89_txpwr_limit_ru *lmt_ru, 1829 u8 ntx, u8 ch) 1830 { 1831 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1832 ntx, ch - 6); 1833 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1834 ntx, ch - 2); 1835 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1836 ntx, ch + 2); 1837 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1838 ntx, ch + 6); 1839 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1840 ntx, ch - 6); 1841 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1842 ntx, ch - 2); 1843 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1844 ntx, ch + 2); 1845 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1846 ntx, ch + 6); 1847 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1848 ntx, ch - 6); 1849 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1850 ntx, ch - 2); 1851 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1852 ntx, ch + 2); 1853 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1854 ntx, ch + 6); 1855 } 1856 1857 static void 1858 rtw89_phy_fill_txpwr_limit_ru_160m(struct rtw89_dev *rtwdev, 1859 struct rtw89_txpwr_limit_ru *lmt_ru, 1860 u8 ntx, u8 ch) 1861 { 1862 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 }; 1863 int i; 1864 1865 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM); 1866 for (i = 0; i < RTW89_RU_SEC_NUM; i++) { 1867 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, 1868 RTW89_RU26, 1869 ntx, 1870 ch + ofst[i]); 1871 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, 1872 RTW89_RU52, 1873 ntx, 1874 ch + ofst[i]); 1875 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, 1876 RTW89_RU106, 1877 ntx, 1878 ch + ofst[i]); 1879 } 1880 } 1881 1882 void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, 1883 struct rtw89_txpwr_limit_ru *lmt_ru, 1884 u8 ntx) 1885 { 1886 u8 ch = rtwdev->hal.current_channel; 1887 u8 bw = rtwdev->hal.current_band_width; 1888 1889 memset(lmt_ru, 0, sizeof(*lmt_ru)); 1890 1891 switch (bw) { 1892 case RTW89_CHANNEL_WIDTH_20: 1893 rtw89_phy_fill_txpwr_limit_ru_20m(rtwdev, lmt_ru, ntx, ch); 1894 break; 1895 case RTW89_CHANNEL_WIDTH_40: 1896 rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, ntx, ch); 1897 break; 1898 case RTW89_CHANNEL_WIDTH_80: 1899 rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, ntx, ch); 1900 break; 1901 case RTW89_CHANNEL_WIDTH_160: 1902 rtw89_phy_fill_txpwr_limit_ru_160m(rtwdev, lmt_ru, ntx, ch); 1903 break; 1904 } 1905 } 1906 EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit_ru); 1907 1908 struct rtw89_phy_iter_ra_data { 1909 struct rtw89_dev *rtwdev; 1910 struct sk_buff *c2h; 1911 }; 1912 1913 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) 1914 { 1915 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; 1916 struct rtw89_dev *rtwdev = ra_data->rtwdev; 1917 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1918 struct rtw89_ra_report *ra_report = &rtwsta->ra_report; 1919 struct sk_buff *c2h = ra_data->c2h; 1920 u8 mode, rate, bw, giltf, mac_id; 1921 u16 legacy_bitrate; 1922 bool valid; 1923 1924 mac_id = RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h->data); 1925 if (mac_id != rtwsta->mac_id) 1926 return; 1927 1928 rate = RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h->data); 1929 bw = RTW89_GET_PHY_C2H_RA_RPT_BW(c2h->data); 1930 giltf = RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h->data); 1931 mode = RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h->data); 1932 1933 if (mode == RTW89_RA_RPT_MODE_LEGACY) { 1934 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate); 1935 if (!valid) 1936 return; 1937 } 1938 1939 memset(ra_report, 0, sizeof(*ra_report)); 1940 1941 switch (mode) { 1942 case RTW89_RA_RPT_MODE_LEGACY: 1943 ra_report->txrate.legacy = legacy_bitrate; 1944 break; 1945 case RTW89_RA_RPT_MODE_HT: 1946 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; 1947 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw)) 1948 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), 1949 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); 1950 else 1951 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); 1952 ra_report->txrate.mcs = rate; 1953 if (giltf) 1954 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1955 break; 1956 case RTW89_RA_RPT_MODE_VHT: 1957 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; 1958 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 1959 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 1960 if (giltf) 1961 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1962 break; 1963 case RTW89_RA_RPT_MODE_HE: 1964 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; 1965 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 1966 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 1967 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 1968 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; 1969 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 1970 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; 1971 else 1972 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; 1973 break; 1974 } 1975 1976 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw); 1977 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); 1978 ra_report->hw_rate = FIELD_PREP(RTW89_HW_RATE_MASK_MOD, mode) | 1979 FIELD_PREP(RTW89_HW_RATE_MASK_VAL, rate); 1980 sta->max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); 1981 rtwsta->max_agg_wait = sta->max_rc_amsdu_len / 1500 - 1; 1982 } 1983 1984 static void 1985 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 1986 { 1987 struct rtw89_phy_iter_ra_data ra_data; 1988 1989 ra_data.rtwdev = rtwdev; 1990 ra_data.c2h = c2h; 1991 ieee80211_iterate_stations_atomic(rtwdev->hw, 1992 rtw89_phy_c2h_ra_rpt_iter, 1993 &ra_data); 1994 } 1995 1996 static 1997 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, 1998 struct sk_buff *c2h, u32 len) = { 1999 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 2000 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 2001 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 2002 }; 2003 2004 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 2005 u32 len, u8 class, u8 func) 2006 { 2007 void (*handler)(struct rtw89_dev *rtwdev, 2008 struct sk_buff *c2h, u32 len) = NULL; 2009 2010 switch (class) { 2011 case RTW89_PHY_C2H_CLASS_RA: 2012 if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 2013 handler = rtw89_phy_c2h_ra_handler[func]; 2014 break; 2015 default: 2016 rtw89_info(rtwdev, "c2h class %d not support\n", class); 2017 return; 2018 } 2019 if (!handler) { 2020 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 2021 func); 2022 return; 2023 } 2024 handler(rtwdev, skb, len); 2025 } 2026 2027 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) 2028 { 2029 u32 reg_mask; 2030 2031 if (sc_xo) 2032 reg_mask = B_AX_XTAL_SC_XO_MASK; 2033 else 2034 reg_mask = B_AX_XTAL_SC_XI_MASK; 2035 2036 return (u8)rtw89_read32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask); 2037 } 2038 2039 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, 2040 u8 val) 2041 { 2042 u32 reg_mask; 2043 2044 if (sc_xo) 2045 reg_mask = B_AX_XTAL_SC_XO_MASK; 2046 else 2047 reg_mask = B_AX_XTAL_SC_XI_MASK; 2048 2049 rtw89_write32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask, val); 2050 } 2051 2052 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, 2053 u8 crystal_cap, bool force) 2054 { 2055 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2056 const struct rtw89_chip_info *chip = rtwdev->chip; 2057 u8 sc_xi_val, sc_xo_val; 2058 2059 if (!force && cfo->crystal_cap == crystal_cap) 2060 return; 2061 crystal_cap = clamp_t(u8, crystal_cap, 0, 127); 2062 if (chip->chip_id == RTL8852A) { 2063 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); 2064 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); 2065 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); 2066 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); 2067 } else { 2068 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, 2069 crystal_cap, XTAL_SC_XO_MASK); 2070 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, 2071 crystal_cap, XTAL_SC_XI_MASK); 2072 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val); 2073 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val); 2074 } 2075 cfo->crystal_cap = sc_xi_val; 2076 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); 2077 2078 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); 2079 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); 2080 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", 2081 cfo->x_cap_ofst); 2082 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); 2083 } 2084 2085 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) 2086 { 2087 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2088 u8 cap; 2089 2090 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; 2091 cfo->is_adjust = false; 2092 if (cfo->crystal_cap == cfo->def_x_cap) 2093 return; 2094 cap = cfo->crystal_cap; 2095 cap += (cap > cfo->def_x_cap ? -1 : 1); 2096 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); 2097 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2098 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, 2099 cfo->def_x_cap); 2100 } 2101 2102 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) 2103 { 2104 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp; 2105 bool is_linked = rtwdev->total_sta_assoc > 0; 2106 s32 cfo_avg_312; 2107 s32 dcfo_comp_val; 2108 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft; 2109 int sign; 2110 2111 if (!is_linked) { 2112 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", 2113 is_linked); 2114 return; 2115 } 2116 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); 2117 if (curr_cfo == 0) 2118 return; 2119 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); 2120 sign = curr_cfo > 0 ? 1 : -1; 2121 cfo_avg_312 = (curr_cfo << dcfo_comp_sft) / 5 + sign * dcfo_comp_val; 2122 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: avg_cfo=%d\n", cfo_avg_312); 2123 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 2124 cfo_avg_312 = -cfo_avg_312; 2125 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask, 2126 cfo_avg_312); 2127 } 2128 2129 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) 2130 { 2131 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_OPT, B_DCFO_OPT_EN, 1); 2132 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_WEIGHT, B_DCFO_WEIGHT_MSK, 8); 2133 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, B_AX_PWR_UL_CFO_MASK); 2134 } 2135 2136 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) 2137 { 2138 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2139 struct rtw89_efuse *efuse = &rtwdev->efuse; 2140 2141 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; 2142 cfo->crystal_cap = cfo->crystal_cap_default; 2143 cfo->def_x_cap = cfo->crystal_cap; 2144 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f); 2145 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1); 2146 cfo->is_adjust = false; 2147 cfo->divergence_lock_en = false; 2148 cfo->x_cap_ofst = 0; 2149 cfo->lock_cnt = 0; 2150 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; 2151 cfo->apply_compensation = false; 2152 cfo->residual_cfo_acc = 0; 2153 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", 2154 cfo->crystal_cap_default); 2155 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); 2156 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); 2157 rtw89_dcfo_comp_init(rtwdev); 2158 cfo->cfo_timer_ms = 2000; 2159 cfo->cfo_trig_by_timer_en = false; 2160 cfo->phy_cfo_trk_cnt = 0; 2161 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2162 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE; 2163 } 2164 2165 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, 2166 s32 curr_cfo) 2167 { 2168 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2169 s8 crystal_cap = cfo->crystal_cap; 2170 s32 cfo_abs = abs(curr_cfo); 2171 int sign; 2172 2173 if (!cfo->is_adjust) { 2174 if (cfo_abs > CFO_TRK_ENABLE_TH) 2175 cfo->is_adjust = true; 2176 } else { 2177 if (cfo_abs < CFO_TRK_STOP_TH) 2178 cfo->is_adjust = false; 2179 } 2180 if (!cfo->is_adjust) { 2181 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); 2182 return; 2183 } 2184 sign = curr_cfo > 0 ? 1 : -1; 2185 if (cfo_abs > CFO_TRK_STOP_TH_4) 2186 crystal_cap += 7 * sign; 2187 else if (cfo_abs > CFO_TRK_STOP_TH_3) 2188 crystal_cap += 5 * sign; 2189 else if (cfo_abs > CFO_TRK_STOP_TH_2) 2190 crystal_cap += 3 * sign; 2191 else if (cfo_abs > CFO_TRK_STOP_TH_1) 2192 crystal_cap += 1 * sign; 2193 else 2194 return; 2195 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); 2196 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2197 "X_cap{Curr,Default}={0x%x,0x%x}\n", 2198 cfo->crystal_cap, cfo->def_x_cap); 2199 } 2200 2201 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) 2202 { 2203 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2204 s32 cfo_khz_all = 0; 2205 s32 cfo_cnt_all = 0; 2206 s32 cfo_all_avg = 0; 2207 u8 i; 2208 2209 if (rtwdev->total_sta_assoc != 1) 2210 return 0; 2211 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); 2212 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2213 if (cfo->cfo_cnt[i] == 0) 2214 continue; 2215 cfo_khz_all += cfo->cfo_tail[i]; 2216 cfo_cnt_all += cfo->cfo_cnt[i]; 2217 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); 2218 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2219 } 2220 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2221 "CFO track for macid = %d\n", i); 2222 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2223 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", 2224 cfo_khz_all, cfo_cnt_all, cfo_all_avg); 2225 return cfo_all_avg; 2226 } 2227 2228 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) 2229 { 2230 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2231 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2232 s32 target_cfo = 0; 2233 s32 cfo_khz_all = 0; 2234 s32 cfo_khz_all_tp_wgt = 0; 2235 s32 cfo_avg = 0; 2236 s32 max_cfo_lb = BIT(31); 2237 s32 min_cfo_ub = GENMASK(30, 0); 2238 u16 cfo_cnt_all = 0; 2239 u8 active_entry_cnt = 0; 2240 u8 sta_cnt = 0; 2241 u32 tp_all = 0; 2242 u8 i; 2243 u8 cfo_tol = 0; 2244 2245 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); 2246 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { 2247 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); 2248 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2249 if (cfo->cfo_cnt[i] == 0) 2250 continue; 2251 cfo_khz_all += cfo->cfo_tail[i]; 2252 cfo_cnt_all += cfo->cfo_cnt[i]; 2253 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); 2254 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2255 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", 2256 cfo_khz_all, cfo_cnt_all, cfo_avg); 2257 target_cfo = cfo_avg; 2258 } 2259 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { 2260 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); 2261 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2262 if (cfo->cfo_cnt[i] == 0) 2263 continue; 2264 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2265 (s32)cfo->cfo_cnt[i]); 2266 cfo_khz_all += cfo->cfo_avg[i]; 2267 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2268 "Macid=%d, cfo_avg=%d\n", i, 2269 cfo->cfo_avg[i]); 2270 } 2271 sta_cnt = rtwdev->total_sta_assoc; 2272 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); 2273 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2274 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", 2275 cfo_khz_all, sta_cnt, cfo_avg); 2276 target_cfo = cfo_avg; 2277 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { 2278 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); 2279 cfo_tol = cfo->sta_cfo_tolerance; 2280 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2281 sta_cnt++; 2282 if (cfo->cfo_cnt[i] != 0) { 2283 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2284 (s32)cfo->cfo_cnt[i]); 2285 active_entry_cnt++; 2286 } else { 2287 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; 2288 } 2289 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); 2290 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); 2291 cfo_khz_all += cfo->cfo_avg[i]; 2292 /* need tp for each entry */ 2293 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2294 "[%d] cfo_avg=%d, tp=tbd\n", 2295 i, cfo->cfo_avg[i]); 2296 if (sta_cnt >= rtwdev->total_sta_assoc) 2297 break; 2298 } 2299 tp_all = stats->rx_throughput; /* need tp for each entry */ 2300 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); 2301 2302 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", 2303 sta_cnt); 2304 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", 2305 active_entry_cnt); 2306 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2307 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", 2308 cfo_khz_all_tp_wgt, cfo_avg); 2309 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", 2310 max_cfo_lb, min_cfo_ub); 2311 if (max_cfo_lb <= min_cfo_ub) { 2312 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2313 "cfo win_size=%d\n", 2314 min_cfo_ub - max_cfo_lb); 2315 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); 2316 } else { 2317 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2318 "No intersection of cfo tolerance windows\n"); 2319 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); 2320 } 2321 for (i = 0; i < CFO_TRACK_MAX_USER; i++) 2322 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2323 } 2324 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); 2325 return target_cfo; 2326 } 2327 2328 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) 2329 { 2330 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2331 2332 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); 2333 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); 2334 cfo->packet_count = 0; 2335 cfo->packet_count_pre = 0; 2336 cfo->cfo_avg_pre = 0; 2337 } 2338 2339 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) 2340 { 2341 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2342 s32 new_cfo = 0; 2343 bool x_cap_update = false; 2344 u8 pre_x_cap = cfo->crystal_cap; 2345 2346 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", 2347 rtwdev->total_sta_assoc); 2348 if (rtwdev->total_sta_assoc == 0) { 2349 rtw89_phy_cfo_reset(rtwdev); 2350 return; 2351 } 2352 if (cfo->packet_count == 0) { 2353 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); 2354 return; 2355 } 2356 if (cfo->packet_count == cfo->packet_count_pre) { 2357 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); 2358 return; 2359 } 2360 if (rtwdev->total_sta_assoc == 1) 2361 new_cfo = rtw89_phy_average_cfo_calc(rtwdev); 2362 else 2363 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); 2364 if (new_cfo == 0) { 2365 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); 2366 return; 2367 } 2368 if (cfo->divergence_lock_en) { 2369 cfo->lock_cnt++; 2370 if (cfo->lock_cnt > CFO_PERIOD_CNT) { 2371 cfo->divergence_lock_en = false; 2372 cfo->lock_cnt = 0; 2373 } else { 2374 rtw89_phy_cfo_reset(rtwdev); 2375 } 2376 return; 2377 } 2378 if (cfo->crystal_cap >= cfo->x_cap_ub || 2379 cfo->crystal_cap <= cfo->x_cap_lb) { 2380 cfo->divergence_lock_en = true; 2381 rtw89_phy_cfo_reset(rtwdev); 2382 return; 2383 } 2384 2385 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); 2386 cfo->cfo_avg_pre = new_cfo; 2387 x_cap_update = cfo->crystal_cap != pre_x_cap; 2388 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); 2389 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", 2390 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, 2391 cfo->x_cap_ofst); 2392 if (x_cap_update) { 2393 if (new_cfo > 0) 2394 new_cfo -= CFO_SW_COMP_FINE_TUNE; 2395 else 2396 new_cfo += CFO_SW_COMP_FINE_TUNE; 2397 } 2398 rtw89_dcfo_comp(rtwdev, new_cfo); 2399 rtw89_phy_cfo_statistics_reset(rtwdev); 2400 } 2401 2402 void rtw89_phy_cfo_track_work(struct work_struct *work) 2403 { 2404 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2405 cfo_track_work.work); 2406 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2407 2408 mutex_lock(&rtwdev->mutex); 2409 if (!cfo->cfo_trig_by_timer_en) 2410 goto out; 2411 rtw89_leave_ps_mode(rtwdev); 2412 rtw89_phy_cfo_dm(rtwdev); 2413 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2414 msecs_to_jiffies(cfo->cfo_timer_ms)); 2415 out: 2416 mutex_unlock(&rtwdev->mutex); 2417 } 2418 2419 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) 2420 { 2421 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2422 2423 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2424 msecs_to_jiffies(cfo->cfo_timer_ms)); 2425 } 2426 2427 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) 2428 { 2429 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2430 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2431 bool is_ul_ofdma = false, ofdma_acc_en = false; 2432 2433 if (stats->rx_tf_periodic > CFO_TF_CNT_TH) 2434 is_ul_ofdma = true; 2435 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE && 2436 is_ul_ofdma) 2437 ofdma_acc_en = true; 2438 2439 switch (cfo->phy_cfo_status) { 2440 case RTW89_PHY_DCFO_STATE_NORMAL: 2441 if (stats->tx_throughput >= CFO_TP_UPPER) { 2442 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; 2443 cfo->cfo_trig_by_timer_en = true; 2444 cfo->cfo_timer_ms = CFO_COMP_PERIOD; 2445 rtw89_phy_cfo_start_work(rtwdev); 2446 } 2447 break; 2448 case RTW89_PHY_DCFO_STATE_ENHANCE: 2449 if (stats->tx_throughput <= CFO_TP_LOWER) 2450 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2451 else if (ofdma_acc_en && 2452 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) 2453 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD; 2454 else 2455 cfo->phy_cfo_trk_cnt++; 2456 2457 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) { 2458 cfo->phy_cfo_trk_cnt = 0; 2459 cfo->cfo_trig_by_timer_en = false; 2460 } 2461 break; 2462 case RTW89_PHY_DCFO_STATE_HOLD: 2463 if (stats->tx_throughput <= CFO_TP_LOWER) { 2464 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2465 cfo->phy_cfo_trk_cnt = 0; 2466 cfo->cfo_trig_by_timer_en = false; 2467 } else { 2468 cfo->phy_cfo_trk_cnt++; 2469 } 2470 break; 2471 default: 2472 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2473 cfo->phy_cfo_trk_cnt = 0; 2474 break; 2475 } 2476 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2477 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", 2478 stats->tx_throughput, cfo->phy_cfo_status, 2479 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, 2480 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); 2481 if (cfo->cfo_trig_by_timer_en) 2482 return; 2483 rtw89_phy_cfo_dm(rtwdev); 2484 } 2485 2486 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 2487 struct rtw89_rx_phy_ppdu *phy_ppdu) 2488 { 2489 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2490 u8 macid = phy_ppdu->mac_id; 2491 2492 if (macid >= CFO_TRACK_MAX_USER) { 2493 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid); 2494 return; 2495 } 2496 2497 cfo->cfo_tail[macid] += cfo_val; 2498 cfo->cfo_cnt[macid]++; 2499 cfo->packet_count++; 2500 } 2501 2502 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) 2503 { 2504 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2505 int i; 2506 u8 th; 2507 2508 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 2509 th = rtw89_chip_get_thermal(rtwdev, i); 2510 if (th) 2511 ewma_thermal_add(&phystat->avg_thermal[i], th); 2512 2513 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 2514 "path(%d) thermal cur=%u avg=%ld", i, th, 2515 ewma_thermal_read(&phystat->avg_thermal[i])); 2516 } 2517 } 2518 2519 struct rtw89_phy_iter_rssi_data { 2520 struct rtw89_dev *rtwdev; 2521 struct rtw89_phy_ch_info *ch_info; 2522 bool rssi_changed; 2523 }; 2524 2525 static void rtw89_phy_stat_rssi_update_iter(void *data, 2526 struct ieee80211_sta *sta) 2527 { 2528 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2529 struct rtw89_phy_iter_rssi_data *rssi_data = 2530 (struct rtw89_phy_iter_rssi_data *)data; 2531 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info; 2532 unsigned long rssi_curr; 2533 2534 rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi); 2535 2536 if (rssi_curr < ch_info->rssi_min) { 2537 ch_info->rssi_min = rssi_curr; 2538 ch_info->rssi_min_macid = rtwsta->mac_id; 2539 } 2540 2541 if (rtwsta->prev_rssi == 0) { 2542 rtwsta->prev_rssi = rssi_curr; 2543 } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) { 2544 rtwsta->prev_rssi = rssi_curr; 2545 rssi_data->rssi_changed = true; 2546 } 2547 } 2548 2549 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) 2550 { 2551 struct rtw89_phy_iter_rssi_data rssi_data = {0}; 2552 2553 rssi_data.rtwdev = rtwdev; 2554 rssi_data.ch_info = &rtwdev->ch_info; 2555 rssi_data.ch_info->rssi_min = U8_MAX; 2556 ieee80211_iterate_stations_atomic(rtwdev->hw, 2557 rtw89_phy_stat_rssi_update_iter, 2558 &rssi_data); 2559 if (rssi_data.rssi_changed) 2560 rtw89_btc_ntfy_wl_sta(rtwdev); 2561 } 2562 2563 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) 2564 { 2565 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2566 int i; 2567 2568 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 2569 ewma_thermal_init(&phystat->avg_thermal[i]); 2570 2571 rtw89_phy_stat_thermal_update(rtwdev); 2572 2573 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 2574 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); 2575 } 2576 2577 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) 2578 { 2579 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2580 2581 rtw89_phy_stat_thermal_update(rtwdev); 2582 rtw89_phy_stat_rssi_update(rtwdev); 2583 2584 phystat->last_pkt_stat = phystat->cur_pkt_stat; 2585 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 2586 } 2587 2588 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us) 2589 { 2590 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2591 2592 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 2593 } 2594 2595 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) 2596 { 2597 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2598 2599 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 2600 } 2601 2602 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) 2603 { 2604 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2605 2606 env->ccx_manual_ctrl = false; 2607 env->ccx_ongoing = false; 2608 env->ccx_rac_lv = RTW89_RAC_RELEASE; 2609 env->ccx_rpt_stamp = 0; 2610 env->ccx_period = 0; 2611 env->ccx_unit_idx = RTW89_CCX_32_US; 2612 env->ccx_trigger_time = 0; 2613 env->ccx_edcca_opt_bw_idx = RTW89_CCX_EDCCA_BW20_0; 2614 2615 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1); 2616 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1); 2617 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 2618 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EDCCA_OPT_MSK, 2619 RTW89_CCX_EDCCA_BW20_0); 2620 } 2621 2622 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report, 2623 u16 score) 2624 { 2625 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2626 u32 numer = 0; 2627 u16 ret = 0; 2628 2629 numer = report * score + (env->ccx_period >> 1); 2630 if (env->ccx_period) 2631 ret = numer / env->ccx_period; 2632 2633 return ret >= score ? score - 1 : ret; 2634 } 2635 2636 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, 2637 u16 time_ms, u32 *period, 2638 u32 *unit_idx) 2639 { 2640 u32 idx; 2641 u8 quotient; 2642 2643 if (time_ms >= CCX_MAX_PERIOD) 2644 time_ms = CCX_MAX_PERIOD; 2645 2646 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; 2647 2648 if (quotient < 4) 2649 idx = RTW89_CCX_4_US; 2650 else if (quotient < 8) 2651 idx = RTW89_CCX_8_US; 2652 else if (quotient < 16) 2653 idx = RTW89_CCX_16_US; 2654 else 2655 idx = RTW89_CCX_32_US; 2656 2657 *unit_idx = idx; 2658 *period = (time_ms * MS_TO_4US_RATIO) >> idx; 2659 2660 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2661 "[Trigger Time] period:%d, unit_idx:%d\n", 2662 *period, *unit_idx); 2663 } 2664 2665 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev) 2666 { 2667 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2668 2669 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2670 "lv:(%d)->(0)\n", env->ccx_rac_lv); 2671 2672 env->ccx_ongoing = false; 2673 env->ccx_rac_lv = RTW89_RAC_RELEASE; 2674 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 2675 } 2676 2677 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, 2678 struct rtw89_ccx_para_info *para) 2679 { 2680 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2681 bool is_update = env->ifs_clm_app != para->ifs_clm_app; 2682 u8 i = 0; 2683 u16 *ifs_th_l = env->ifs_clm_th_l; 2684 u16 *ifs_th_h = env->ifs_clm_th_h; 2685 u32 ifs_th0_us = 0, ifs_th_times = 0; 2686 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; 2687 2688 if (!is_update) 2689 goto ifs_update_finished; 2690 2691 switch (para->ifs_clm_app) { 2692 case RTW89_IFS_CLM_INIT: 2693 case RTW89_IFS_CLM_BACKGROUND: 2694 case RTW89_IFS_CLM_ACS: 2695 case RTW89_IFS_CLM_DBG: 2696 case RTW89_IFS_CLM_DIG: 2697 case RTW89_IFS_CLM_TDMA_DIG: 2698 ifs_th0_us = IFS_CLM_TH0_UPPER; 2699 ifs_th_times = IFS_CLM_TH_MUL; 2700 break; 2701 case RTW89_IFS_CLM_DBG_MANUAL: 2702 ifs_th0_us = para->ifs_clm_manual_th0; 2703 ifs_th_times = para->ifs_clm_manual_th_times; 2704 break; 2705 default: 2706 break; 2707 } 2708 2709 /* Set sampling threshold for 4 different regions, unit in idx_cnt. 2710 * low[i] = high[i-1] + 1 2711 * high[i] = high[i-1] * ifs_th_times 2712 */ 2713 ifs_th_l[IFS_CLM_TH_START_IDX] = 0; 2714 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; 2715 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, 2716 ifs_th0_us); 2717 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { 2718 ifs_th_l[i] = ifs_th_h[i - 1] + 1; 2719 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; 2720 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]); 2721 } 2722 2723 ifs_update_finished: 2724 if (!is_update) 2725 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2726 "No need to update IFS_TH\n"); 2727 2728 return is_update; 2729 } 2730 2731 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) 2732 { 2733 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2734 u8 i = 0; 2735 2736 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_LOW_MSK, 2737 env->ifs_clm_th_l[0]); 2738 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_LOW_MSK, 2739 env->ifs_clm_th_l[1]); 2740 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_LOW_MSK, 2741 env->ifs_clm_th_l[2]); 2742 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_LOW_MSK, 2743 env->ifs_clm_th_l[3]); 2744 2745 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_HIGH_MSK, 2746 env->ifs_clm_th_h[0]); 2747 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_HIGH_MSK, 2748 env->ifs_clm_th_h[1]); 2749 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_HIGH_MSK, 2750 env->ifs_clm_th_h[2]); 2751 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_HIGH_MSK, 2752 env->ifs_clm_th_h[3]); 2753 2754 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 2755 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2756 "Update IFS_T%d_th{low, high} : {%d, %d}\n", 2757 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 2758 } 2759 2760 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) 2761 { 2762 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2763 struct rtw89_ccx_para_info para = {0}; 2764 2765 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 2766 env->ifs_clm_mntr_time = 0; 2767 2768 para.ifs_clm_app = RTW89_IFS_CLM_INIT; 2769 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) 2770 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 2771 2772 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COLLECT_EN, 2773 true); 2774 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_EN_MSK, true); 2775 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_EN_MSK, true); 2776 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_EN_MSK, true); 2777 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_EN_MSK, true); 2778 } 2779 2780 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, 2781 enum rtw89_env_racing_lv level) 2782 { 2783 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2784 int ret = 0; 2785 2786 if (level >= RTW89_RAC_MAX_NUM) { 2787 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2788 "[WARNING] Wrong LV=%d\n", level); 2789 return -EINVAL; 2790 } 2791 2792 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2793 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, 2794 env->ccx_rac_lv, level); 2795 2796 if (env->ccx_ongoing) { 2797 if (level <= env->ccx_rac_lv) 2798 ret = -EINVAL; 2799 else 2800 env->ccx_ongoing = false; 2801 } 2802 2803 if (ret == 0) 2804 env->ccx_rac_lv = level; 2805 2806 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", 2807 !ret); 2808 2809 return ret; 2810 } 2811 2812 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) 2813 { 2814 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2815 2816 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 0); 2817 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 0); 2818 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1); 2819 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 2820 2821 env->ccx_rpt_stamp++; 2822 env->ccx_ongoing = true; 2823 } 2824 2825 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) 2826 { 2827 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2828 u8 i = 0; 2829 u32 res = 0; 2830 2831 env->ifs_clm_tx_ratio = 2832 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT); 2833 env->ifs_clm_edcca_excl_cca_ratio = 2834 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca, 2835 PERCENT); 2836 env->ifs_clm_cck_fa_ratio = 2837 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT); 2838 env->ifs_clm_ofdm_fa_ratio = 2839 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT); 2840 env->ifs_clm_cck_cca_excl_fa_ratio = 2841 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa, 2842 PERCENT); 2843 env->ifs_clm_ofdm_cca_excl_fa_ratio = 2844 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa, 2845 PERCENT); 2846 env->ifs_clm_cck_fa_permil = 2847 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL); 2848 env->ifs_clm_ofdm_fa_permil = 2849 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL); 2850 2851 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { 2852 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { 2853 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; 2854 } else { 2855 env->ifs_clm_ifs_avg[i] = 2856 rtw89_phy_ccx_idx_to_us(rtwdev, 2857 env->ifs_clm_avg[i]); 2858 } 2859 2860 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]); 2861 res += env->ifs_clm_his[i] >> 1; 2862 if (env->ifs_clm_his[i]) 2863 res /= env->ifs_clm_his[i]; 2864 else 2865 res = 0; 2866 env->ifs_clm_cca_avg[i] = res; 2867 } 2868 2869 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2870 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", 2871 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); 2872 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2873 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", 2874 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); 2875 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2876 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", 2877 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); 2878 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2879 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", 2880 env->ifs_clm_cck_cca_excl_fa_ratio, 2881 env->ifs_clm_ofdm_cca_excl_fa_ratio); 2882 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2883 "Time:[his, ifs_avg(us), cca_avg(us)]\n"); 2884 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 2885 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 2886 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 2887 env->ifs_clm_cca_avg[i]); 2888 } 2889 2890 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) 2891 { 2892 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2893 u8 i = 0; 2894 2895 if (rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_DONE_MSK) == 0) { 2896 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2897 "Get IFS_CLM report Fail\n"); 2898 return false; 2899 } 2900 2901 env->ifs_clm_tx = 2902 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 2903 B_IFS_CLM_TX_CNT_MSK); 2904 env->ifs_clm_edcca_excl_cca = 2905 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 2906 B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK); 2907 env->ifs_clm_cckcca_excl_fa = 2908 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 2909 B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK); 2910 env->ifs_clm_ofdmcca_excl_fa = 2911 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 2912 B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK); 2913 env->ifs_clm_cckfa = 2914 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 2915 B_IFS_CLM_CCK_FA_MSK); 2916 env->ifs_clm_ofdmfa = 2917 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 2918 B_IFS_CLM_OFDM_FA_MSK); 2919 2920 env->ifs_clm_his[0] = 2921 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T1_HIS_MSK); 2922 env->ifs_clm_his[1] = 2923 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T2_HIS_MSK); 2924 env->ifs_clm_his[2] = 2925 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T3_HIS_MSK); 2926 env->ifs_clm_his[3] = 2927 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T4_HIS_MSK); 2928 2929 env->ifs_clm_avg[0] = 2930 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T1_AVG_MSK); 2931 env->ifs_clm_avg[1] = 2932 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T2_AVG_MSK); 2933 env->ifs_clm_avg[2] = 2934 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T3_AVG_MSK); 2935 env->ifs_clm_avg[3] = 2936 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T4_AVG_MSK); 2937 2938 env->ifs_clm_cca[0] = 2939 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T1_CCA_MSK); 2940 env->ifs_clm_cca[1] = 2941 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T2_CCA_MSK); 2942 env->ifs_clm_cca[2] = 2943 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T3_CCA_MSK); 2944 env->ifs_clm_cca[3] = 2945 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T4_CCA_MSK); 2946 2947 env->ifs_clm_total_ifs = 2948 rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_TOTAL_CNT_MSK); 2949 2950 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", 2951 env->ifs_clm_total_ifs); 2952 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2953 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", 2954 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); 2955 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2956 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", 2957 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); 2958 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2959 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", 2960 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); 2961 2962 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); 2963 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 2964 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2965 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], 2966 env->ifs_clm_avg[i], env->ifs_clm_cca[i]); 2967 2968 rtw89_phy_ifs_clm_get_utility(rtwdev); 2969 2970 return true; 2971 } 2972 2973 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 2974 struct rtw89_ccx_para_info *para) 2975 { 2976 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2977 u32 period = 0; 2978 u32 unit_idx = 0; 2979 2980 if (para->mntr_time == 0) { 2981 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2982 "[WARN] MNTR_TIME is 0\n"); 2983 return -EINVAL; 2984 } 2985 2986 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv)) 2987 return -EINVAL; 2988 2989 if (para->mntr_time != env->ifs_clm_mntr_time) { 2990 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 2991 &period, &unit_idx); 2992 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 2993 B_IFS_CLM_PERIOD_MSK, period); 2994 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 2995 B_IFS_CLM_COUNTER_UNIT_MSK, unit_idx); 2996 2997 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2998 "Update IFS-CLM time ((%d)) -> ((%d))\n", 2999 env->ifs_clm_mntr_time, para->mntr_time); 3000 3001 env->ifs_clm_mntr_time = para->mntr_time; 3002 env->ccx_period = (u16)period; 3003 env->ccx_unit_idx = (u8)unit_idx; 3004 } 3005 3006 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) { 3007 env->ifs_clm_app = para->ifs_clm_app; 3008 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 3009 } 3010 3011 return 0; 3012 } 3013 3014 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) 3015 { 3016 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3017 struct rtw89_ccx_para_info para = {0}; 3018 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3019 3020 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3021 if (env->ccx_manual_ctrl) { 3022 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3023 "CCX in manual ctrl\n"); 3024 return; 3025 } 3026 3027 /* only ifs_clm for now */ 3028 if (rtw89_phy_ifs_clm_get_result(rtwdev)) 3029 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3030 3031 rtw89_phy_ccx_racing_release(rtwdev); 3032 para.mntr_time = 1900; 3033 para.rac_lv = RTW89_RAC_LV_1; 3034 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3035 3036 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0) 3037 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3038 if (chk_result) 3039 rtw89_phy_ccx_trigger(rtwdev); 3040 3041 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3042 "get_result=0x%x, chk_result:0x%x\n", 3043 env->ccx_watchdog_result, chk_result); 3044 } 3045 3046 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page) 3047 { 3048 if (*ie_page > RTW89_PHYSTS_BITMAP_NUM || 3049 *ie_page == RTW89_RSVD_9) 3050 return false; 3051 else if (*ie_page > RTW89_RSVD_9) 3052 *ie_page -= 1; 3053 3054 return true; 3055 } 3056 3057 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) 3058 { 3059 static const u8 ie_page_shift = 2; 3060 3061 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); 3062 } 3063 3064 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, 3065 enum rtw89_phy_status_bitmap ie_page) 3066 { 3067 u32 addr; 3068 3069 if (!rtw89_physts_ie_page_valid(&ie_page)) 3070 return 0; 3071 3072 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3073 3074 return rtw89_phy_read32(rtwdev, addr); 3075 } 3076 3077 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, 3078 enum rtw89_phy_status_bitmap ie_page, 3079 u32 val) 3080 { 3081 const struct rtw89_chip_info *chip = rtwdev->chip; 3082 u32 addr; 3083 3084 if (!rtw89_physts_ie_page_valid(&ie_page)) 3085 return; 3086 3087 if (chip->chip_id == RTL8852A) 3088 val &= B_PHY_STS_BITMAP_MSK_52A; 3089 3090 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3091 rtw89_phy_write32(rtwdev, addr, val); 3092 } 3093 3094 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev, 3095 enum rtw89_phy_status_bitmap bitmap, 3096 enum rtw89_phy_status_ie_type ie, 3097 bool enable) 3098 { 3099 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap); 3100 3101 if (enable) 3102 val |= BIT(ie); 3103 else 3104 val &= ~BIT(ie); 3105 3106 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val); 3107 } 3108 3109 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, 3110 bool enable, 3111 enum rtw89_phy_idx phy_idx) 3112 { 3113 if (enable) { 3114 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3115 B_STS_DIS_TRIG_BY_FAIL); 3116 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3117 B_STS_DIS_TRIG_BY_BRK); 3118 } else { 3119 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3120 B_STS_DIS_TRIG_BY_FAIL); 3121 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3122 B_STS_DIS_TRIG_BY_BRK); 3123 } 3124 } 3125 3126 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev) 3127 { 3128 u8 i; 3129 3130 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0); 3131 3132 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { 3133 if (i >= RTW89_CCK_PKT) 3134 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3135 RTW89_PHYSTS_IE09_FTR_0, 3136 true); 3137 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) || 3138 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT)) 3139 continue; 3140 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3141 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A, 3142 true); 3143 } 3144 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT, 3145 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3146 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT, 3147 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3148 3149 /* force IE01 for channel index, only channel field is valid */ 3150 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT, 3151 RTW89_PHYSTS_IE01_CMN_OFDM, true); 3152 } 3153 3154 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) 3155 { 3156 const struct rtw89_chip_info *chip = rtwdev->chip; 3157 struct rtw89_dig_info *dig = &rtwdev->dig; 3158 const struct rtw89_phy_dig_gain_cfg *cfg; 3159 const char *msg; 3160 u8 i; 3161 s8 gain_base; 3162 s8 *gain_arr; 3163 u32 tmp; 3164 3165 switch (type) { 3166 case RTW89_DIG_GAIN_LNA_G: 3167 gain_arr = dig->lna_gain_g; 3168 gain_base = LNA0_GAIN; 3169 cfg = chip->dig_table->cfg_lna_g; 3170 msg = "lna_gain_g"; 3171 break; 3172 case RTW89_DIG_GAIN_TIA_G: 3173 gain_arr = dig->tia_gain_g; 3174 gain_base = TIA0_GAIN_G; 3175 cfg = chip->dig_table->cfg_tia_g; 3176 msg = "tia_gain_g"; 3177 break; 3178 case RTW89_DIG_GAIN_LNA_A: 3179 gain_arr = dig->lna_gain_a; 3180 gain_base = LNA0_GAIN; 3181 cfg = chip->dig_table->cfg_lna_a; 3182 msg = "lna_gain_a"; 3183 break; 3184 case RTW89_DIG_GAIN_TIA_A: 3185 gain_arr = dig->tia_gain_a; 3186 gain_base = TIA0_GAIN_A; 3187 cfg = chip->dig_table->cfg_tia_a; 3188 msg = "tia_gain_a"; 3189 break; 3190 default: 3191 return; 3192 } 3193 3194 for (i = 0; i < cfg->size; i++) { 3195 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr, 3196 cfg->table[i].mask); 3197 tmp >>= DIG_GAIN_SHIFT; 3198 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; 3199 gain_base += DIG_GAIN; 3200 3201 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", 3202 msg, i, gain_arr[i]); 3203 } 3204 } 3205 3206 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev) 3207 { 3208 struct rtw89_dig_info *dig = &rtwdev->dig; 3209 u32 tmp; 3210 u8 i; 3211 3212 if (!rtwdev->hal.support_igi) 3213 return; 3214 3215 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW, 3216 B_PATH0_IB_PKPW_MSK); 3217 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); 3218 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK, 3219 B_PATH0_IB_PBK_MSK); 3220 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", 3221 dig->ib_pkpwr, dig->ib_pbk); 3222 3223 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) 3224 rtw89_phy_dig_read_gain_table(rtwdev, i); 3225 } 3226 3227 static const u8 rssi_nolink = 22; 3228 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; 3229 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; 3230 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; 3231 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; 3232 3233 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev) 3234 { 3235 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 3236 struct rtw89_dig_info *dig = &rtwdev->dig; 3237 bool is_linked = rtwdev->total_sta_assoc > 0; 3238 3239 if (is_linked) { 3240 dig->igi_rssi = ch_info->rssi_min >> 1; 3241 } else { 3242 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); 3243 dig->igi_rssi = rssi_nolink; 3244 } 3245 } 3246 3247 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev) 3248 { 3249 struct rtw89_dig_info *dig = &rtwdev->dig; 3250 bool is_linked = rtwdev->total_sta_assoc > 0; 3251 const u16 *fa_th_src = NULL; 3252 3253 switch (rtwdev->hal.current_band_type) { 3254 case RTW89_BAND_2G: 3255 dig->lna_gain = dig->lna_gain_g; 3256 dig->tia_gain = dig->tia_gain_g; 3257 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; 3258 dig->force_gaincode_idx_en = false; 3259 dig->dyn_pd_th_en = true; 3260 break; 3261 case RTW89_BAND_5G: 3262 default: 3263 dig->lna_gain = dig->lna_gain_a; 3264 dig->tia_gain = dig->tia_gain_a; 3265 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; 3266 dig->force_gaincode_idx_en = true; 3267 dig->dyn_pd_th_en = true; 3268 break; 3269 } 3270 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); 3271 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); 3272 } 3273 3274 static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20; 3275 static const u8 igi_max_performance_mode = 0x5a; 3276 static const u8 dynamic_pd_threshold_max; 3277 3278 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev) 3279 { 3280 struct rtw89_dig_info *dig = &rtwdev->dig; 3281 3282 dig->cur_gaincode.lna_idx = LNA_IDX_MAX; 3283 dig->cur_gaincode.tia_idx = TIA_IDX_MAX; 3284 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; 3285 dig->force_gaincode.lna_idx = LNA_IDX_MAX; 3286 dig->force_gaincode.tia_idx = TIA_IDX_MAX; 3287 dig->force_gaincode.rxb_idx = RXB_IDX_MAX; 3288 3289 dig->dyn_igi_max = igi_max_performance_mode; 3290 dig->dyn_igi_min = dynamic_igi_min; 3291 dig->dyn_pd_th_max = dynamic_pd_threshold_max; 3292 dig->pd_low_th_ofst = pd_low_th_offset; 3293 dig->is_linked_pre = false; 3294 } 3295 3296 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) 3297 { 3298 rtw89_phy_dig_update_gain_para(rtwdev); 3299 rtw89_phy_dig_reset(rtwdev); 3300 } 3301 3302 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3303 { 3304 struct rtw89_dig_info *dig = &rtwdev->dig; 3305 u8 lna_idx; 3306 3307 if (rssi < dig->igi_rssi_th[0]) 3308 lna_idx = RTW89_DIG_GAIN_LNA_IDX6; 3309 else if (rssi < dig->igi_rssi_th[1]) 3310 lna_idx = RTW89_DIG_GAIN_LNA_IDX5; 3311 else if (rssi < dig->igi_rssi_th[2]) 3312 lna_idx = RTW89_DIG_GAIN_LNA_IDX4; 3313 else if (rssi < dig->igi_rssi_th[3]) 3314 lna_idx = RTW89_DIG_GAIN_LNA_IDX3; 3315 else if (rssi < dig->igi_rssi_th[4]) 3316 lna_idx = RTW89_DIG_GAIN_LNA_IDX2; 3317 else 3318 lna_idx = RTW89_DIG_GAIN_LNA_IDX1; 3319 3320 return lna_idx; 3321 } 3322 3323 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3324 { 3325 struct rtw89_dig_info *dig = &rtwdev->dig; 3326 u8 tia_idx; 3327 3328 if (rssi < dig->igi_rssi_th[0]) 3329 tia_idx = RTW89_DIG_GAIN_TIA_IDX1; 3330 else 3331 tia_idx = RTW89_DIG_GAIN_TIA_IDX0; 3332 3333 return tia_idx; 3334 } 3335 3336 #define IB_PBK_BASE 110 3337 #define WB_RSSI_BASE 10 3338 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3339 struct rtw89_agc_gaincode_set *set) 3340 { 3341 struct rtw89_dig_info *dig = &rtwdev->dig; 3342 s8 lna_gain = dig->lna_gain[set->lna_idx]; 3343 s8 tia_gain = dig->tia_gain[set->tia_idx]; 3344 s32 wb_rssi = rssi + lna_gain + tia_gain; 3345 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; 3346 u8 rxb_idx; 3347 3348 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; 3349 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); 3350 3351 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", 3352 wb_rssi, rxb_idx_tmp); 3353 3354 return rxb_idx; 3355 } 3356 3357 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3358 struct rtw89_agc_gaincode_set *set) 3359 { 3360 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi); 3361 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi); 3362 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set); 3363 3364 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3365 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", 3366 rssi, set->lna_idx, set->tia_idx, set->rxb_idx); 3367 } 3368 3369 #define IGI_OFFSET_MAX 25 3370 #define IGI_OFFSET_MUL 2 3371 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev) 3372 { 3373 struct rtw89_dig_info *dig = &rtwdev->dig; 3374 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3375 enum rtw89_dig_noisy_level noisy_lv; 3376 u8 igi_offset = dig->fa_rssi_ofst; 3377 u16 fa_ratio = 0; 3378 3379 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; 3380 3381 if (fa_ratio < dig->fa_th[0]) 3382 noisy_lv = RTW89_DIG_NOISY_LEVEL0; 3383 else if (fa_ratio < dig->fa_th[1]) 3384 noisy_lv = RTW89_DIG_NOISY_LEVEL1; 3385 else if (fa_ratio < dig->fa_th[2]) 3386 noisy_lv = RTW89_DIG_NOISY_LEVEL2; 3387 else if (fa_ratio < dig->fa_th[3]) 3388 noisy_lv = RTW89_DIG_NOISY_LEVEL3; 3389 else 3390 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; 3391 3392 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) 3393 igi_offset = 0; 3394 else 3395 igi_offset += noisy_lv * IGI_OFFSET_MUL; 3396 3397 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); 3398 dig->fa_rssi_ofst = igi_offset; 3399 3400 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3401 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", 3402 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); 3403 3404 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3405 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", 3406 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, 3407 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, 3408 noisy_lv, igi_offset); 3409 } 3410 3411 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx) 3412 { 3413 rtw89_phy_write32_mask(rtwdev, R_PATH0_LNA_INIT, 3414 B_PATH0_LNA_INIT_IDX_MSK, lna_idx); 3415 rtw89_phy_write32_mask(rtwdev, R_PATH1_LNA_INIT, 3416 B_PATH1_LNA_INIT_IDX_MSK, lna_idx); 3417 } 3418 3419 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx) 3420 { 3421 rtw89_phy_write32_mask(rtwdev, R_PATH0_TIA_INIT, 3422 B_PATH0_TIA_INIT_IDX_MSK, tia_idx); 3423 rtw89_phy_write32_mask(rtwdev, R_PATH1_TIA_INIT, 3424 B_PATH1_TIA_INIT_IDX_MSK, tia_idx); 3425 } 3426 3427 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx) 3428 { 3429 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXB_INIT, 3430 B_PATH0_RXB_INIT_IDX_MSK, rxb_idx); 3431 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXB_INIT, 3432 B_PATH1_RXB_INIT_IDX_MSK, rxb_idx); 3433 } 3434 3435 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, 3436 const struct rtw89_agc_gaincode_set set) 3437 { 3438 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx); 3439 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx); 3440 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx); 3441 3442 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", 3443 set.lna_idx, set.tia_idx, set.rxb_idx); 3444 } 3445 3446 static const struct rtw89_reg_def sdagc_config[4] = { 3447 {R_PATH0_P20_FOLLOW_BY_PAGCUGC, B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 3448 {R_PATH0_S20_FOLLOW_BY_PAGCUGC, B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 3449 {R_PATH1_P20_FOLLOW_BY_PAGCUGC, B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 3450 {R_PATH1_S20_FOLLOW_BY_PAGCUGC, B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 3451 }; 3452 3453 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, 3454 bool enable) 3455 { 3456 u8 i = 0; 3457 3458 for (i = 0; i < ARRAY_SIZE(sdagc_config); i++) 3459 rtw89_phy_write32_mask(rtwdev, sdagc_config[i].addr, 3460 sdagc_config[i].mask, enable); 3461 3462 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); 3463 } 3464 3465 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev) 3466 { 3467 struct rtw89_dig_info *dig = &rtwdev->dig; 3468 3469 if (!rtwdev->hal.support_igi) 3470 return; 3471 3472 if (dig->force_gaincode_idx_en) { 3473 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 3474 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3475 "Force gaincode index enabled.\n"); 3476 } else { 3477 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi, 3478 &dig->cur_gaincode); 3479 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode); 3480 } 3481 } 3482 3483 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, 3484 bool enable) 3485 { 3486 enum rtw89_bandwidth cbw = rtwdev->hal.current_band_width; 3487 struct rtw89_dig_info *dig = &rtwdev->dig; 3488 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; 3489 u8 ofdm_cca_th; 3490 s8 cck_cca_th; 3491 u32 pd_val = 0; 3492 3493 under_region += PD_TH_SB_FLTR_CMP_VAL; 3494 3495 switch (cbw) { 3496 case RTW89_CHANNEL_WIDTH_40: 3497 under_region += PD_TH_BW40_CMP_VAL; 3498 break; 3499 case RTW89_CHANNEL_WIDTH_80: 3500 under_region += PD_TH_BW80_CMP_VAL; 3501 break; 3502 case RTW89_CHANNEL_WIDTH_160: 3503 under_region += PD_TH_BW160_CMP_VAL; 3504 break; 3505 case RTW89_CHANNEL_WIDTH_20: 3506 fallthrough; 3507 default: 3508 under_region += PD_TH_BW20_CMP_VAL; 3509 break; 3510 } 3511 3512 dig->dyn_pd_th_max = dig->igi_rssi; 3513 3514 final_rssi = min_t(u8, rssi, dig->igi_rssi); 3515 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, 3516 PD_TH_MAX_RSSI + under_region); 3517 3518 if (enable) { 3519 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1; 3520 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3521 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n", 3522 final_rssi, ofdm_cca_th, under_region, pd_val); 3523 } else { 3524 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3525 "Dynamic PD th disabled, Set PD_low_bd=0\n"); 3526 } 3527 3528 rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, B_SEG0R_PD_LOWER_BOUND_MSK, 3529 pd_val); 3530 rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, 3531 B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, enable); 3532 3533 if (!rtwdev->hal.support_cckpd) 3534 return; 3535 3536 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI); 3537 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX); 3538 3539 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3540 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n", 3541 final_rssi, cck_cca_th, under_region, pd_val); 3542 3543 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_EN_V1, 3544 B_BMODE_PDTH_LIMIT_EN_MSK_V1, enable); 3545 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_V1, 3546 B_BMODE_PDTH_LOWER_BOUND_MSK_V1, pd_val); 3547 } 3548 3549 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) 3550 { 3551 struct rtw89_dig_info *dig = &rtwdev->dig; 3552 3553 dig->bypass_dig = false; 3554 rtw89_phy_dig_para_reset(rtwdev); 3555 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 3556 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false); 3557 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 3558 rtw89_phy_dig_update_para(rtwdev); 3559 } 3560 3561 #define IGI_RSSI_MIN 10 3562 void rtw89_phy_dig(struct rtw89_dev *rtwdev) 3563 { 3564 struct rtw89_dig_info *dig = &rtwdev->dig; 3565 bool is_linked = rtwdev->total_sta_assoc > 0; 3566 3567 if (unlikely(dig->bypass_dig)) { 3568 dig->bypass_dig = false; 3569 return; 3570 } 3571 3572 if (!dig->is_linked_pre && is_linked) { 3573 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); 3574 rtw89_phy_dig_update_para(rtwdev); 3575 } else if (dig->is_linked_pre && !is_linked) { 3576 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); 3577 rtw89_phy_dig_update_para(rtwdev); 3578 } 3579 dig->is_linked_pre = is_linked; 3580 3581 rtw89_phy_dig_igi_offset_by_env(rtwdev); 3582 rtw89_phy_dig_update_rssi_info(rtwdev); 3583 3584 dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ? 3585 dig->igi_rssi - IGI_RSSI_MIN : 0; 3586 dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX; 3587 dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst; 3588 3589 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, 3590 dig->dyn_igi_max); 3591 3592 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3593 "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n", 3594 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, 3595 dig->igi_fa_rssi); 3596 3597 rtw89_phy_dig_config_igi(rtwdev); 3598 3599 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en); 3600 3601 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) 3602 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true); 3603 else 3604 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 3605 } 3606 3607 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) 3608 { 3609 rtw89_phy_ccx_top_setting_init(rtwdev); 3610 rtw89_phy_ifs_clm_setting_init(rtwdev); 3611 } 3612 3613 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 3614 { 3615 const struct rtw89_chip_info *chip = rtwdev->chip; 3616 3617 rtw89_phy_stat_init(rtwdev); 3618 3619 rtw89_chip_bb_sethw(rtwdev); 3620 3621 rtw89_phy_env_monitor_init(rtwdev); 3622 rtw89_physts_parsing_init(rtwdev); 3623 rtw89_phy_dig_init(rtwdev); 3624 rtw89_phy_cfo_init(rtwdev); 3625 3626 rtw89_phy_init_rf_nctl(rtwdev); 3627 rtw89_chip_rfk_init(rtwdev); 3628 rtw89_load_txpwr_table(rtwdev, chip->byr_table); 3629 rtw89_chip_set_txpwr_ctrl(rtwdev); 3630 rtw89_chip_power_trim(rtwdev); 3631 rtw89_chip_cfg_txrx_path(rtwdev); 3632 } 3633 3634 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 3635 { 3636 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 3637 u8 bss_color; 3638 3639 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 3640 return; 3641 3642 bss_color = vif->bss_conf.he_bss_color.color; 3643 3644 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0, 0x1, 3645 phy_idx); 3646 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_TGT, bss_color, 3647 phy_idx); 3648 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_STAID, 3649 vif->cfg.aid, phy_idx); 3650 } 3651 3652 static void 3653 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3654 { 3655 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); 3656 } 3657 3658 static void 3659 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3660 { 3661 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 3662 } 3663 3664 static void 3665 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3666 { 3667 rtw89_phy_write32_set(rtwdev, def->addr, def->mask); 3668 } 3669 3670 static void 3671 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3672 { 3673 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); 3674 } 3675 3676 static void 3677 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3678 { 3679 udelay(def->data); 3680 } 3681 3682 static void 3683 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { 3684 [RTW89_RFK_F_WRF] = _rfk_write_rf, 3685 [RTW89_RFK_F_WM] = _rfk_write32_mask, 3686 [RTW89_RFK_F_WS] = _rfk_write32_set, 3687 [RTW89_RFK_F_WC] = _rfk_write32_clr, 3688 [RTW89_RFK_F_DELAY] = _rfk_delay, 3689 }; 3690 3691 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 3692 3693 void 3694 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) 3695 { 3696 const struct rtw89_reg5_def *p = tbl->defs; 3697 const struct rtw89_reg5_def *end = tbl->defs + tbl->size; 3698 3699 for (; p < end; p++) 3700 _rfk_handler[p->flag](rtwdev, p); 3701 } 3702 EXPORT_SYMBOL(rtw89_rfk_parser); 3703 3704 #define RTW89_TSSI_FAST_MODE_NUM 4 3705 3706 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = { 3707 {0xD934, 0xff0000}, 3708 {0xD934, 0xff000000}, 3709 {0xD938, 0xff}, 3710 {0xD934, 0xff00}, 3711 }; 3712 3713 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = { 3714 {0xD930, 0xff0000}, 3715 {0xD930, 0xff000000}, 3716 {0xD934, 0xff}, 3717 {0xD930, 0xff00}, 3718 }; 3719 3720 static 3721 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev, 3722 enum rtw89_mac_idx mac_idx, 3723 enum rtw89_tssi_bandedge_cfg bandedge_cfg, 3724 u32 val) 3725 { 3726 const struct rtw89_reg_def *regs; 3727 u32 reg; 3728 int i; 3729 3730 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 3731 regs = rtw89_tssi_fastmode_regs_flat; 3732 else 3733 regs = rtw89_tssi_fastmode_regs_level; 3734 3735 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) { 3736 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 3737 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); 3738 } 3739 } 3740 3741 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = { 3742 {0xD91C, 0xff000000}, 3743 {0xD920, 0xff}, 3744 {0xD920, 0xff00}, 3745 {0xD920, 0xff0000}, 3746 {0xD920, 0xff000000}, 3747 {0xD924, 0xff}, 3748 {0xD924, 0xff00}, 3749 {0xD914, 0xff000000}, 3750 {0xD918, 0xff}, 3751 {0xD918, 0xff00}, 3752 {0xD918, 0xff0000}, 3753 {0xD918, 0xff000000}, 3754 {0xD91C, 0xff}, 3755 {0xD91C, 0xff00}, 3756 {0xD91C, 0xff0000}, 3757 }; 3758 3759 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = { 3760 {0xD910, 0xff}, 3761 {0xD910, 0xff00}, 3762 {0xD910, 0xff0000}, 3763 {0xD910, 0xff000000}, 3764 {0xD914, 0xff}, 3765 {0xD914, 0xff00}, 3766 {0xD914, 0xff0000}, 3767 {0xD908, 0xff}, 3768 {0xD908, 0xff00}, 3769 {0xD908, 0xff0000}, 3770 {0xD908, 0xff000000}, 3771 {0xD90C, 0xff}, 3772 {0xD90C, 0xff00}, 3773 {0xD90C, 0xff0000}, 3774 {0xD90C, 0xff000000}, 3775 }; 3776 3777 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 3778 enum rtw89_mac_idx mac_idx, 3779 enum rtw89_tssi_bandedge_cfg bandedge_cfg) 3780 { 3781 const struct rtw89_chip_info *chip = rtwdev->chip; 3782 const struct rtw89_reg_def *regs; 3783 const u32 *data; 3784 u32 reg; 3785 int i; 3786 3787 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM) 3788 return; 3789 3790 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 3791 regs = rtw89_tssi_bandedge_regs_flat; 3792 else 3793 regs = rtw89_tssi_bandedge_regs_level; 3794 3795 data = chip->tssi_dbw_table->data[bandedge_cfg]; 3796 3797 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) { 3798 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 3799 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); 3800 } 3801 3802 reg = rtw89_mac_reg_by_idx(R_AX_BANDEDGE_CFG, mac_idx); 3803 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); 3804 3805 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg, 3806 data[RTW89_TSSI_SBW20]); 3807 } 3808 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg); 3809