1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "debug.h" 7 #include "fw.h" 8 #include "mac.h" 9 #include "phy.h" 10 #include "ps.h" 11 #include "reg.h" 12 #include "sar.h" 13 #include "util.h" 14 15 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, 16 const struct rtw89_ra_report *report) 17 { 18 u32 bit_rate = report->bit_rate; 19 20 /* lower than ofdm, do not aggregate */ 21 if (bit_rate < 550) 22 return 1; 23 24 /* avoid AMSDU for legacy rate */ 25 if (report->might_fallback_legacy) 26 return 1; 27 28 /* lower than 20M vht 2ss mcs8, make it small */ 29 if (bit_rate < 1800) 30 return 1200; 31 32 /* lower than 40M vht 2ss mcs9, make it medium */ 33 if (bit_rate < 4000) 34 return 2600; 35 36 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ 37 if (bit_rate < 7000) 38 return 3500; 39 40 return rtwdev->chip->max_amsdu_limit; 41 } 42 43 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) 44 { 45 u64 ra_mask = 0; 46 u8 mcs_cap; 47 int i, nss; 48 49 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { 50 mcs_cap = mcs_map & 0x3; 51 switch (mcs_cap) { 52 case 2: 53 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; 54 break; 55 case 1: 56 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; 57 break; 58 case 0: 59 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; 60 break; 61 default: 62 break; 63 } 64 } 65 66 return ra_mask; 67 } 68 69 static u64 get_he_ra_mask(struct ieee80211_sta *sta) 70 { 71 struct ieee80211_sta_he_cap cap = sta->deflink.he_cap; 72 u16 mcs_map; 73 74 switch (sta->deflink.bandwidth) { 75 case IEEE80211_STA_RX_BW_160: 76 if (cap.he_cap_elem.phy_cap_info[0] & 77 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) 78 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); 79 else 80 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); 81 break; 82 default: 83 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); 84 } 85 86 /* MCS11, MCS9, MCS7 */ 87 return get_mcs_ra_mask(mcs_map, 11, 2); 88 } 89 90 #define RA_FLOOR_TABLE_SIZE 7 91 #define RA_FLOOR_UP_GAP 3 92 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, 93 u8 ratr_state) 94 { 95 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; 96 u8 rssi_lv = 0; 97 u8 i; 98 99 rssi >>= 1; 100 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 101 if (i >= ratr_state) 102 rssi_lv_t[i] += RA_FLOOR_UP_GAP; 103 if (rssi < rssi_lv_t[i]) { 104 rssi_lv = i; 105 break; 106 } 107 } 108 if (rssi_lv == 0) 109 return 0xffffffffffffffffULL; 110 else if (rssi_lv == 1) 111 return 0xfffffffffffffff0ULL; 112 else if (rssi_lv == 2) 113 return 0xffffffffffffefe0ULL; 114 else if (rssi_lv == 3) 115 return 0xffffffffffffcfc0ULL; 116 else if (rssi_lv == 4) 117 return 0xffffffffffff8f80ULL; 118 else if (rssi_lv >= 5) 119 return 0xffffffffffff0f00ULL; 120 121 return 0xffffffffffffffffULL; 122 } 123 124 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak) 125 { 126 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 127 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 128 129 if (ra_mask == 0) 130 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 131 132 return ra_mask; 133 } 134 135 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 136 { 137 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 138 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 139 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 140 enum nl80211_band band; 141 u64 cfg_mask; 142 143 if (!rtwsta->use_cfg_mask) 144 return -1; 145 146 switch (chan->band_type) { 147 case RTW89_BAND_2G: 148 band = NL80211_BAND_2GHZ; 149 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, 150 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); 151 break; 152 case RTW89_BAND_5G: 153 band = NL80211_BAND_5GHZ; 154 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, 155 RA_MASK_OFDM_RATES); 156 break; 157 case RTW89_BAND_6G: 158 band = NL80211_BAND_6GHZ; 159 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy, 160 RA_MASK_OFDM_RATES); 161 break; 162 default: 163 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type); 164 return -1; 165 } 166 167 if (sta->deflink.he_cap.has_he) { 168 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], 169 RA_MASK_HE_1SS_RATES); 170 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], 171 RA_MASK_HE_2SS_RATES); 172 } else if (sta->deflink.vht_cap.vht_supported) { 173 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 174 RA_MASK_VHT_1SS_RATES); 175 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 176 RA_MASK_VHT_2SS_RATES); 177 } else if (sta->deflink.ht_cap.ht_supported) { 178 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 179 RA_MASK_HT_1SS_RATES); 180 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 181 RA_MASK_HT_2SS_RATES); 182 } 183 184 return cfg_mask; 185 } 186 187 static const u64 188 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, 189 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; 190 static const u64 191 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 192 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; 193 static const u64 194 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, 195 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; 196 197 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev, 198 struct rtw89_sta *rtwsta, 199 bool *fix_giltf_en, u8 *fix_giltf) 200 { 201 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 202 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 203 u8 band = chan->band_type; 204 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 205 u8 he_gi = mask->control[nl_band].he_gi; 206 u8 he_ltf = mask->control[nl_band].he_ltf; 207 208 if (!rtwsta->use_cfg_mask) 209 return; 210 211 if (he_ltf == 2 && he_gi == 2) { 212 *fix_giltf = RTW89_GILTF_LGI_4XHE32; 213 } else if (he_ltf == 2 && he_gi == 0) { 214 *fix_giltf = RTW89_GILTF_SGI_4XHE08; 215 } else if (he_ltf == 1 && he_gi == 1) { 216 *fix_giltf = RTW89_GILTF_2XHE16; 217 } else if (he_ltf == 1 && he_gi == 0) { 218 *fix_giltf = RTW89_GILTF_2XHE08; 219 } else if (he_ltf == 0 && he_gi == 1) { 220 *fix_giltf = RTW89_GILTF_1XHE16; 221 } else if (he_ltf == 0 && he_gi == 0) { 222 *fix_giltf = RTW89_GILTF_1XHE08; 223 } else { 224 *fix_giltf_en = false; 225 return; 226 } 227 228 *fix_giltf_en = true; 229 } 230 231 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 232 struct ieee80211_sta *sta, bool csi) 233 { 234 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 235 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 236 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 237 struct rtw89_ra_info *ra = &rtwsta->ra; 238 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 239 struct ieee80211_vif *vif = rtwvif_to_vif(rtwsta->rtwvif); 240 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; 241 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 242 u64 ra_mask = 0; 243 u64 ra_mask_bak; 244 u8 mode = 0; 245 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; 246 u8 bw_mode = 0; 247 u8 stbc_en = 0; 248 u8 ldpc_en = 0; 249 u8 fix_giltf = 0; 250 u8 i; 251 bool sgi = false; 252 bool fix_giltf_en = false; 253 254 memset(ra, 0, sizeof(*ra)); 255 /* Set the ra mask from sta's capability */ 256 if (sta->deflink.he_cap.has_he) { 257 mode |= RTW89_RA_MODE_HE; 258 csi_mode = RTW89_RA_RPT_MODE_HE; 259 ra_mask |= get_he_ra_mask(sta); 260 high_rate_masks = rtw89_ra_mask_he_rates; 261 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[2] & 262 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) 263 stbc_en = 1; 264 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[1] & 265 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) 266 ldpc_en = 1; 267 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta, &fix_giltf_en, &fix_giltf); 268 } else if (sta->deflink.vht_cap.vht_supported) { 269 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 270 271 mode |= RTW89_RA_MODE_VHT; 272 csi_mode = RTW89_RA_RPT_MODE_VHT; 273 /* MCS9, MCS8, MCS7 */ 274 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); 275 high_rate_masks = rtw89_ra_mask_vht_rates; 276 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 277 stbc_en = 1; 278 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 279 ldpc_en = 1; 280 } else if (sta->deflink.ht_cap.ht_supported) { 281 mode |= RTW89_RA_MODE_HT; 282 csi_mode = RTW89_RA_RPT_MODE_HT; 283 ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 48) | 284 ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 36) | 285 (sta->deflink.ht_cap.mcs.rx_mask[1] << 24) | 286 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 287 high_rate_masks = rtw89_ra_mask_ht_rates; 288 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 289 stbc_en = 1; 290 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 291 ldpc_en = 1; 292 } 293 294 switch (chan->band_type) { 295 case RTW89_BAND_2G: 296 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 297 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xf) 298 mode |= RTW89_RA_MODE_CCK; 299 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xff0) 300 mode |= RTW89_RA_MODE_OFDM; 301 break; 302 case RTW89_BAND_5G: 303 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 304 mode |= RTW89_RA_MODE_OFDM; 305 break; 306 case RTW89_BAND_6G: 307 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_6GHZ] << 4; 308 mode |= RTW89_RA_MODE_OFDM; 309 break; 310 default: 311 rtw89_err(rtwdev, "Unknown band type\n"); 312 break; 313 } 314 315 ra_mask_bak = ra_mask; 316 317 if (mode >= RTW89_RA_MODE_HT) { 318 u64 mask = 0; 319 for (i = 0; i < rtwdev->hal.tx_nss; i++) 320 mask |= high_rate_masks[i]; 321 if (mode & RTW89_RA_MODE_OFDM) 322 mask |= RA_MASK_SUBOFDM_RATES; 323 if (mode & RTW89_RA_MODE_CCK) 324 mask |= RA_MASK_SUBCCK_RATES; 325 ra_mask &= mask; 326 } else if (mode & RTW89_RA_MODE_OFDM) { 327 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES); 328 } 329 330 if (mode != RTW89_RA_MODE_CCK) 331 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); 332 333 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak); 334 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 335 336 switch (sta->deflink.bandwidth) { 337 case IEEE80211_STA_RX_BW_160: 338 bw_mode = RTW89_CHANNEL_WIDTH_160; 339 sgi = sta->deflink.vht_cap.vht_supported && 340 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160); 341 break; 342 case IEEE80211_STA_RX_BW_80: 343 bw_mode = RTW89_CHANNEL_WIDTH_80; 344 sgi = sta->deflink.vht_cap.vht_supported && 345 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 346 break; 347 case IEEE80211_STA_RX_BW_40: 348 bw_mode = RTW89_CHANNEL_WIDTH_40; 349 sgi = sta->deflink.ht_cap.ht_supported && 350 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 351 break; 352 default: 353 bw_mode = RTW89_CHANNEL_WIDTH_20; 354 sgi = sta->deflink.ht_cap.ht_supported && 355 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 356 break; 357 } 358 359 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 360 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) 361 ra->dcm_cap = 1; 362 363 if (rate_pattern->enable && !vif->p2p) { 364 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 365 ra_mask &= rate_pattern->ra_mask; 366 mode = rate_pattern->ra_mode; 367 } 368 369 ra->bw_cap = bw_mode; 370 ra->er_cap = rtwsta->er_cap; 371 ra->mode_ctrl = mode; 372 ra->macid = rtwsta->mac_id; 373 ra->stbc_cap = stbc_en; 374 ra->ldpc_cap = ldpc_en; 375 ra->ss_num = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1; 376 ra->en_sgi = sgi; 377 ra->ra_mask = ra_mask; 378 ra->fix_giltf_en = fix_giltf_en; 379 ra->fix_giltf = fix_giltf; 380 381 if (!csi) 382 return; 383 384 ra->fixed_csi_rate_en = false; 385 ra->ra_csi_rate_en = true; 386 ra->cr_tbl_sel = false; 387 ra->band_num = rtwvif->phy_idx; 388 ra->csi_bw = bw_mode; 389 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; 390 ra->csi_mcs_ss_idx = 5; 391 ra->csi_mode = csi_mode; 392 } 393 394 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 395 u32 changed) 396 { 397 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 398 struct rtw89_ra_info *ra = &rtwsta->ra; 399 400 rtw89_phy_ra_sta_update(rtwdev, sta, false); 401 402 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) 403 ra->upd_mask = 1; 404 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED)) 405 ra->upd_bw_nss_mask = 1; 406 407 rtw89_debug(rtwdev, RTW89_DBG_RA, 408 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", 409 ra->macid, 410 ra->bw_cap, 411 ra->ss_num, 412 ra->en_sgi, 413 ra->giltf); 414 415 rtw89_fw_h2c_ra(rtwdev, ra, false); 416 } 417 418 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, 419 u16 rate_base, u64 ra_mask, u8 ra_mode, 420 u32 rate_ctrl, u32 ctrl_skip, bool force) 421 { 422 u8 n, c; 423 424 if (rate_ctrl == ctrl_skip) 425 return true; 426 427 n = hweight32(rate_ctrl); 428 if (n == 0) 429 return true; 430 431 if (force && n != 1) 432 return false; 433 434 if (next->enable) 435 return false; 436 437 c = __fls(rate_ctrl); 438 next->rate = rate_base + c; 439 next->ra_mode = ra_mode; 440 next->ra_mask = ra_mask; 441 next->enable = true; 442 443 return true; 444 } 445 446 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 447 struct ieee80211_vif *vif, 448 const struct cfg80211_bitrate_mask *mask) 449 { 450 struct ieee80211_supported_band *sband; 451 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 452 struct rtw89_phy_rate_pattern next_pattern = {0}; 453 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 454 static const u16 hw_rate_he[] = {RTW89_HW_RATE_HE_NSS1_MCS0, 455 RTW89_HW_RATE_HE_NSS2_MCS0, 456 RTW89_HW_RATE_HE_NSS3_MCS0, 457 RTW89_HW_RATE_HE_NSS4_MCS0}; 458 static const u16 hw_rate_vht[] = {RTW89_HW_RATE_VHT_NSS1_MCS0, 459 RTW89_HW_RATE_VHT_NSS2_MCS0, 460 RTW89_HW_RATE_VHT_NSS3_MCS0, 461 RTW89_HW_RATE_VHT_NSS4_MCS0}; 462 static const u16 hw_rate_ht[] = {RTW89_HW_RATE_MCS0, 463 RTW89_HW_RATE_MCS8, 464 RTW89_HW_RATE_MCS16, 465 RTW89_HW_RATE_MCS24}; 466 u8 band = chan->band_type; 467 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 468 u8 tx_nss = rtwdev->hal.tx_nss; 469 u8 i; 470 471 for (i = 0; i < tx_nss; i++) 472 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i], 473 RA_MASK_HE_RATES, RTW89_RA_MODE_HE, 474 mask->control[nl_band].he_mcs[i], 475 0, true)) 476 goto out; 477 478 for (i = 0; i < tx_nss; i++) 479 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i], 480 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, 481 mask->control[nl_band].vht_mcs[i], 482 0, true)) 483 goto out; 484 485 for (i = 0; i < tx_nss; i++) 486 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i], 487 RA_MASK_HT_RATES, RTW89_RA_MODE_HT, 488 mask->control[nl_band].ht_mcs[i], 489 0, true)) 490 goto out; 491 492 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and 493 * require at least one basic rate for ieee80211_set_bitrate_mask, 494 * so the decision just depends on if all bitrates are set or not. 495 */ 496 sband = rtwdev->hw->wiphy->bands[nl_band]; 497 if (band == RTW89_BAND_2G) { 498 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, 499 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, 500 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, 501 mask->control[nl_band].legacy, 502 BIT(sband->n_bitrates) - 1, false)) 503 goto out; 504 } else { 505 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, 506 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, 507 mask->control[nl_band].legacy, 508 BIT(sband->n_bitrates) - 1, false)) 509 goto out; 510 } 511 512 if (!next_pattern.enable) 513 goto out; 514 515 rtwvif->rate_pattern = next_pattern; 516 rtw89_debug(rtwdev, RTW89_DBG_RA, 517 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", 518 next_pattern.rate, 519 next_pattern.ra_mask, 520 next_pattern.ra_mode); 521 return; 522 523 out: 524 rtwvif->rate_pattern.enable = false; 525 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); 526 } 527 528 static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta) 529 { 530 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; 531 532 rtw89_phy_ra_updata_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED); 533 } 534 535 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) 536 { 537 ieee80211_iterate_stations_atomic(rtwdev->hw, 538 rtw89_phy_ra_updata_sta_iter, 539 rtwdev); 540 } 541 542 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) 543 { 544 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 545 struct rtw89_ra_info *ra = &rtwsta->ra; 546 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; 547 bool csi = rtw89_sta_has_beamformer_cap(sta); 548 549 rtw89_phy_ra_sta_update(rtwdev, sta, csi); 550 551 if (rssi > 40) 552 ra->init_rate_lv = 1; 553 else if (rssi > 20) 554 ra->init_rate_lv = 2; 555 else if (rssi > 1) 556 ra->init_rate_lv = 3; 557 else 558 ra->init_rate_lv = 0; 559 ra->upd_all = 1; 560 rtw89_debug(rtwdev, RTW89_DBG_RA, 561 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", 562 ra->macid, 563 ra->mode_ctrl, 564 ra->bw_cap, 565 ra->ss_num, 566 ra->init_rate_lv); 567 rtw89_debug(rtwdev, RTW89_DBG_RA, 568 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", 569 ra->dcm_cap, 570 ra->er_cap, 571 ra->ldpc_cap, 572 ra->stbc_cap, 573 ra->en_sgi, 574 ra->giltf); 575 576 rtw89_fw_h2c_ra(rtwdev, ra, csi); 577 } 578 579 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 580 const struct rtw89_chan *chan, 581 enum rtw89_bandwidth dbw) 582 { 583 enum rtw89_bandwidth cbw = chan->band_width; 584 u8 pri_ch = chan->primary_channel; 585 u8 central_ch = chan->channel; 586 u8 txsc_idx = 0; 587 u8 tmp = 0; 588 589 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 590 return txsc_idx; 591 592 switch (cbw) { 593 case RTW89_CHANNEL_WIDTH_40: 594 txsc_idx = pri_ch > central_ch ? 1 : 2; 595 break; 596 case RTW89_CHANNEL_WIDTH_80: 597 if (dbw == RTW89_CHANNEL_WIDTH_20) { 598 if (pri_ch > central_ch) 599 txsc_idx = (pri_ch - central_ch) >> 1; 600 else 601 txsc_idx = ((central_ch - pri_ch) >> 1) + 1; 602 } else { 603 txsc_idx = pri_ch > central_ch ? 9 : 10; 604 } 605 break; 606 case RTW89_CHANNEL_WIDTH_160: 607 if (pri_ch > central_ch) 608 tmp = (pri_ch - central_ch) >> 1; 609 else 610 tmp = ((central_ch - pri_ch) >> 1) + 1; 611 612 if (dbw == RTW89_CHANNEL_WIDTH_20) { 613 txsc_idx = tmp; 614 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 615 if (tmp == 1 || tmp == 3) 616 txsc_idx = 9; 617 else if (tmp == 5 || tmp == 7) 618 txsc_idx = 11; 619 else if (tmp == 2 || tmp == 4) 620 txsc_idx = 10; 621 else if (tmp == 6 || tmp == 8) 622 txsc_idx = 12; 623 else 624 return 0xff; 625 } else { 626 txsc_idx = pri_ch > central_ch ? 13 : 14; 627 } 628 break; 629 case RTW89_CHANNEL_WIDTH_80_80: 630 if (dbw == RTW89_CHANNEL_WIDTH_20) { 631 if (pri_ch > central_ch) 632 txsc_idx = (10 - (pri_ch - central_ch)) >> 1; 633 else 634 txsc_idx = ((central_ch - pri_ch) >> 1) + 5; 635 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 636 txsc_idx = pri_ch > central_ch ? 10 : 12; 637 } else { 638 txsc_idx = 14; 639 } 640 break; 641 default: 642 break; 643 } 644 645 return txsc_idx; 646 } 647 EXPORT_SYMBOL(rtw89_phy_get_txsc); 648 649 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev) 650 { 651 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) || 652 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1); 653 } 654 655 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 656 u32 addr, u32 mask) 657 { 658 const struct rtw89_chip_info *chip = rtwdev->chip; 659 const u32 *base_addr = chip->rf_base_addr; 660 u32 val, direct_addr; 661 662 if (rf_path >= rtwdev->chip->rf_path_num) { 663 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 664 return INV_RF_DATA; 665 } 666 667 addr &= 0xff; 668 direct_addr = base_addr[rf_path] + (addr << 2); 669 mask &= RFREG_MASK; 670 671 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); 672 673 return val; 674 } 675 EXPORT_SYMBOL(rtw89_phy_read_rf); 676 677 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev, 678 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 679 { 680 bool busy; 681 bool done; 682 u32 val; 683 int ret; 684 685 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 686 1, 30, false, rtwdev); 687 if (ret) { 688 rtw89_err(rtwdev, "read rf busy swsi\n"); 689 return INV_RF_DATA; 690 } 691 692 mask &= RFREG_MASK; 693 694 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) | 695 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr); 696 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val); 697 udelay(2); 698 699 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1, 700 30, false, rtwdev, R_SWSI_V1, 701 B_SWSI_R_DATA_DONE_V1); 702 if (ret) { 703 rtw89_err(rtwdev, "read swsi busy\n"); 704 return INV_RF_DATA; 705 } 706 707 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask); 708 } 709 710 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 711 u32 addr, u32 mask) 712 { 713 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 714 715 if (rf_path >= rtwdev->chip->rf_path_num) { 716 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 717 return INV_RF_DATA; 718 } 719 720 if (ad_sel) 721 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 722 else 723 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask); 724 } 725 EXPORT_SYMBOL(rtw89_phy_read_rf_v1); 726 727 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 728 u32 addr, u32 mask, u32 data) 729 { 730 const struct rtw89_chip_info *chip = rtwdev->chip; 731 const u32 *base_addr = chip->rf_base_addr; 732 u32 direct_addr; 733 734 if (rf_path >= rtwdev->chip->rf_path_num) { 735 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 736 return false; 737 } 738 739 addr &= 0xff; 740 direct_addr = base_addr[rf_path] + (addr << 2); 741 mask &= RFREG_MASK; 742 743 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); 744 745 /* delay to ensure writing properly */ 746 udelay(1); 747 748 return true; 749 } 750 EXPORT_SYMBOL(rtw89_phy_write_rf); 751 752 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev, 753 enum rtw89_rf_path rf_path, u32 addr, u32 mask, 754 u32 data) 755 { 756 u8 bit_shift; 757 u32 val; 758 bool busy, b_msk_en = false; 759 int ret; 760 761 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 762 1, 30, false, rtwdev); 763 if (ret) { 764 rtw89_err(rtwdev, "write rf busy swsi\n"); 765 return false; 766 } 767 768 data &= RFREG_MASK; 769 mask &= RFREG_MASK; 770 771 if (mask != RFREG_MASK) { 772 b_msk_en = true; 773 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK, 774 mask); 775 bit_shift = __ffs(mask); 776 data = (data << bit_shift) & RFREG_MASK; 777 } 778 779 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) | 780 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) | 781 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) | 782 FIELD_PREP(B_SWSI_DATA_VAL_V1, data); 783 784 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val); 785 786 return true; 787 } 788 789 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 790 u32 addr, u32 mask, u32 data) 791 { 792 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 793 794 if (rf_path >= rtwdev->chip->rf_path_num) { 795 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 796 return false; 797 } 798 799 if (ad_sel) 800 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 801 else 802 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data); 803 } 804 EXPORT_SYMBOL(rtw89_phy_write_rf_v1); 805 806 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev) 807 { 808 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1; 809 } 810 811 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, 812 enum rtw89_phy_idx phy_idx) 813 { 814 const struct rtw89_chip_info *chip = rtwdev->chip; 815 816 chip->ops->bb_reset(rtwdev, phy_idx); 817 } 818 819 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, 820 const struct rtw89_reg2_def *reg, 821 enum rtw89_rf_path rf_path, 822 void *extra_data) 823 { 824 if (reg->addr == 0xfe) 825 mdelay(50); 826 else if (reg->addr == 0xfd) 827 mdelay(5); 828 else if (reg->addr == 0xfc) 829 mdelay(1); 830 else if (reg->addr == 0xfb) 831 udelay(50); 832 else if (reg->addr == 0xfa) 833 udelay(5); 834 else if (reg->addr == 0xf9) 835 udelay(1); 836 else 837 rtw89_phy_write32(rtwdev, reg->addr, reg->data); 838 } 839 840 union rtw89_phy_bb_gain_arg { 841 u32 addr; 842 struct { 843 union { 844 u8 type; 845 struct { 846 u8 rxsc_start:4; 847 u8 bw:4; 848 }; 849 }; 850 u8 path; 851 u8 gain_band; 852 u8 cfg_type; 853 }; 854 } __packed; 855 856 static void 857 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev, 858 union rtw89_phy_bb_gain_arg arg, u32 data) 859 { 860 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 861 u8 type = arg.type; 862 u8 path = arg.path; 863 u8 gband = arg.gain_band; 864 int i; 865 866 switch (type) { 867 case 0: 868 for (i = 0; i < 4; i++, data >>= 8) 869 gain->lna_gain[gband][path][i] = data & 0xff; 870 break; 871 case 1: 872 for (i = 4; i < 7; i++, data >>= 8) 873 gain->lna_gain[gband][path][i] = data & 0xff; 874 break; 875 case 2: 876 for (i = 0; i < 2; i++, data >>= 8) 877 gain->tia_gain[gband][path][i] = data & 0xff; 878 break; 879 default: 880 rtw89_warn(rtwdev, 881 "bb gain error {0x%x:0x%x} with unknown type: %d\n", 882 arg.addr, data, type); 883 break; 884 } 885 } 886 887 enum rtw89_phy_bb_rxsc_start_idx { 888 RTW89_BB_RXSC_START_IDX_FULL = 0, 889 RTW89_BB_RXSC_START_IDX_20 = 1, 890 RTW89_BB_RXSC_START_IDX_20_1 = 5, 891 RTW89_BB_RXSC_START_IDX_40 = 9, 892 RTW89_BB_RXSC_START_IDX_80 = 13, 893 }; 894 895 static void 896 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev, 897 union rtw89_phy_bb_gain_arg arg, u32 data) 898 { 899 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 900 u8 rxsc_start = arg.rxsc_start; 901 u8 bw = arg.bw; 902 u8 path = arg.path; 903 u8 gband = arg.gain_band; 904 u8 rxsc; 905 s8 ofst; 906 int i; 907 908 switch (bw) { 909 case RTW89_CHANNEL_WIDTH_20: 910 gain->rpl_ofst_20[gband][path] = (s8)data; 911 break; 912 case RTW89_CHANNEL_WIDTH_40: 913 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 914 gain->rpl_ofst_40[gband][path][0] = (s8)data; 915 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 916 for (i = 0; i < 2; i++, data >>= 8) { 917 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 918 ofst = (s8)(data & 0xff); 919 gain->rpl_ofst_40[gband][path][rxsc] = ofst; 920 } 921 } 922 break; 923 case RTW89_CHANNEL_WIDTH_80: 924 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 925 gain->rpl_ofst_80[gband][path][0] = (s8)data; 926 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 927 for (i = 0; i < 4; i++, data >>= 8) { 928 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 929 ofst = (s8)(data & 0xff); 930 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 931 } 932 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 933 for (i = 0; i < 2; i++, data >>= 8) { 934 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 935 ofst = (s8)(data & 0xff); 936 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 937 } 938 } 939 break; 940 case RTW89_CHANNEL_WIDTH_160: 941 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 942 gain->rpl_ofst_160[gband][path][0] = (s8)data; 943 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 944 for (i = 0; i < 4; i++, data >>= 8) { 945 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 946 ofst = (s8)(data & 0xff); 947 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 948 } 949 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) { 950 for (i = 0; i < 4; i++, data >>= 8) { 951 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i; 952 ofst = (s8)(data & 0xff); 953 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 954 } 955 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 956 for (i = 0; i < 4; i++, data >>= 8) { 957 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 958 ofst = (s8)(data & 0xff); 959 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 960 } 961 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) { 962 for (i = 0; i < 2; i++, data >>= 8) { 963 rxsc = RTW89_BB_RXSC_START_IDX_80 + i; 964 ofst = (s8)(data & 0xff); 965 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 966 } 967 } 968 break; 969 default: 970 rtw89_warn(rtwdev, 971 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n", 972 arg.addr, data, bw); 973 break; 974 } 975 } 976 977 static void 978 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev, 979 union rtw89_phy_bb_gain_arg arg, u32 data) 980 { 981 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 982 u8 type = arg.type; 983 u8 path = arg.path; 984 u8 gband = arg.gain_band; 985 int i; 986 987 switch (type) { 988 case 0: 989 for (i = 0; i < 4; i++, data >>= 8) 990 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 991 break; 992 case 1: 993 for (i = 4; i < 7; i++, data >>= 8) 994 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 995 break; 996 default: 997 rtw89_warn(rtwdev, 998 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n", 999 arg.addr, data, type); 1000 break; 1001 } 1002 } 1003 1004 static void 1005 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev, 1006 union rtw89_phy_bb_gain_arg arg, u32 data) 1007 { 1008 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 1009 u8 type = arg.type; 1010 u8 path = arg.path; 1011 u8 gband = arg.gain_band; 1012 int i; 1013 1014 switch (type) { 1015 case 0: 1016 for (i = 0; i < 4; i++, data >>= 8) 1017 gain->lna_op1db[gband][path][i] = data & 0xff; 1018 break; 1019 case 1: 1020 for (i = 4; i < 7; i++, data >>= 8) 1021 gain->lna_op1db[gband][path][i] = data & 0xff; 1022 break; 1023 case 2: 1024 for (i = 0; i < 4; i++, data >>= 8) 1025 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1026 break; 1027 case 3: 1028 for (i = 4; i < 8; i++, data >>= 8) 1029 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1030 break; 1031 default: 1032 rtw89_warn(rtwdev, 1033 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n", 1034 arg.addr, data, type); 1035 break; 1036 } 1037 } 1038 1039 static void rtw89_phy_config_bb_gain(struct rtw89_dev *rtwdev, 1040 const struct rtw89_reg2_def *reg, 1041 enum rtw89_rf_path rf_path, 1042 void *extra_data) 1043 { 1044 const struct rtw89_chip_info *chip = rtwdev->chip; 1045 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr }; 1046 struct rtw89_efuse *efuse = &rtwdev->efuse; 1047 1048 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR) 1049 return; 1050 1051 if (arg.path >= chip->rf_path_num) 1052 return; 1053 1054 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) { 1055 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n"); 1056 return; 1057 } 1058 1059 switch (arg.cfg_type) { 1060 case 0: 1061 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data); 1062 break; 1063 case 1: 1064 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data); 1065 break; 1066 case 2: 1067 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data); 1068 break; 1069 case 3: 1070 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data); 1071 break; 1072 case 4: 1073 /* This cfg_type is only used by rfe_type >= 50 with eFEM */ 1074 if (efuse->rfe_type < 50) 1075 break; 1076 fallthrough; 1077 default: 1078 rtw89_warn(rtwdev, 1079 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n", 1080 arg.addr, reg->data, arg.cfg_type); 1081 break; 1082 } 1083 } 1084 1085 static void 1086 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, 1087 const struct rtw89_reg2_def *reg, 1088 enum rtw89_rf_path rf_path, 1089 struct rtw89_fw_h2c_rf_reg_info *info) 1090 { 1091 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; 1092 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 1093 1094 if (page >= RTW89_H2C_RF_PAGE_NUM) { 1095 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d", 1096 rf_path, info->curr_idx); 1097 return; 1098 } 1099 1100 info->rtw89_phy_config_rf_h2c[page][idx] = 1101 cpu_to_le32((reg->addr << 20) | reg->data); 1102 info->curr_idx++; 1103 } 1104 1105 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, 1106 struct rtw89_fw_h2c_rf_reg_info *info) 1107 { 1108 u16 remain = info->curr_idx; 1109 u16 len = 0; 1110 u8 i; 1111 int ret = 0; 1112 1113 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) { 1114 rtw89_warn(rtwdev, 1115 "rf reg h2c total len %d larger than %d\n", 1116 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE); 1117 ret = -EINVAL; 1118 goto out; 1119 } 1120 1121 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) { 1122 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain; 1123 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i); 1124 if (ret) 1125 goto out; 1126 } 1127 out: 1128 info->curr_idx = 0; 1129 1130 return ret; 1131 } 1132 1133 static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev, 1134 const struct rtw89_reg2_def *reg, 1135 enum rtw89_rf_path rf_path, 1136 void *extra_data) 1137 { 1138 u32 addr = reg->addr; 1139 1140 if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb || 1141 addr == 0xfa || addr == 0xf9) 1142 return; 1143 1144 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100) 1145 return; 1146 1147 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1148 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1149 } 1150 1151 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, 1152 const struct rtw89_reg2_def *reg, 1153 enum rtw89_rf_path rf_path, 1154 void *extra_data) 1155 { 1156 if (reg->addr == 0xfe) { 1157 mdelay(50); 1158 } else if (reg->addr == 0xfd) { 1159 mdelay(5); 1160 } else if (reg->addr == 0xfc) { 1161 mdelay(1); 1162 } else if (reg->addr == 0xfb) { 1163 udelay(50); 1164 } else if (reg->addr == 0xfa) { 1165 udelay(5); 1166 } else if (reg->addr == 0xf9) { 1167 udelay(1); 1168 } else { 1169 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); 1170 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1171 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1172 } 1173 } 1174 1175 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 1176 const struct rtw89_reg2_def *reg, 1177 enum rtw89_rf_path rf_path, 1178 void *extra_data) 1179 { 1180 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data); 1181 1182 if (reg->addr < 0x100) 1183 return; 1184 1185 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1186 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1187 } 1188 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1); 1189 1190 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, 1191 const struct rtw89_phy_table *table, 1192 u32 *headline_size, u32 *headline_idx, 1193 u8 rfe, u8 cv) 1194 { 1195 const struct rtw89_reg2_def *reg; 1196 u32 headline; 1197 u32 compare, target; 1198 u8 rfe_para, cv_para; 1199 u8 cv_max = 0; 1200 bool case_matched = false; 1201 u32 i; 1202 1203 for (i = 0; i < table->n_regs; i++) { 1204 reg = &table->regs[i]; 1205 headline = get_phy_headline(reg->addr); 1206 if (headline != PHY_HEADLINE_VALID) 1207 break; 1208 } 1209 *headline_size = i; 1210 if (*headline_size == 0) 1211 return 0; 1212 1213 /* case 1: RFE match, CV match */ 1214 compare = get_phy_compare(rfe, cv); 1215 for (i = 0; i < *headline_size; i++) { 1216 reg = &table->regs[i]; 1217 target = get_phy_target(reg->addr); 1218 if (target == compare) { 1219 *headline_idx = i; 1220 return 0; 1221 } 1222 } 1223 1224 /* case 2: RFE match, CV don't care */ 1225 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); 1226 for (i = 0; i < *headline_size; i++) { 1227 reg = &table->regs[i]; 1228 target = get_phy_target(reg->addr); 1229 if (target == compare) { 1230 *headline_idx = i; 1231 return 0; 1232 } 1233 } 1234 1235 /* case 3: RFE match, CV max in table */ 1236 for (i = 0; i < *headline_size; i++) { 1237 reg = &table->regs[i]; 1238 rfe_para = get_phy_cond_rfe(reg->addr); 1239 cv_para = get_phy_cond_cv(reg->addr); 1240 if (rfe_para == rfe) { 1241 if (cv_para >= cv_max) { 1242 cv_max = cv_para; 1243 *headline_idx = i; 1244 case_matched = true; 1245 } 1246 } 1247 } 1248 1249 if (case_matched) 1250 return 0; 1251 1252 /* case 4: RFE don't care, CV max in table */ 1253 for (i = 0; i < *headline_size; i++) { 1254 reg = &table->regs[i]; 1255 rfe_para = get_phy_cond_rfe(reg->addr); 1256 cv_para = get_phy_cond_cv(reg->addr); 1257 if (rfe_para == PHY_COND_DONT_CARE) { 1258 if (cv_para >= cv_max) { 1259 cv_max = cv_para; 1260 *headline_idx = i; 1261 case_matched = true; 1262 } 1263 } 1264 } 1265 1266 if (case_matched) 1267 return 0; 1268 1269 return -EINVAL; 1270 } 1271 1272 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, 1273 const struct rtw89_phy_table *table, 1274 void (*config)(struct rtw89_dev *rtwdev, 1275 const struct rtw89_reg2_def *reg, 1276 enum rtw89_rf_path rf_path, 1277 void *data), 1278 void *extra_data) 1279 { 1280 const struct rtw89_reg2_def *reg; 1281 enum rtw89_rf_path rf_path = table->rf_path; 1282 u8 rfe = rtwdev->efuse.rfe_type; 1283 u8 cv = rtwdev->hal.cv; 1284 u32 i; 1285 u32 headline_size = 0, headline_idx = 0; 1286 u32 target = 0, cfg_target; 1287 u8 cond; 1288 bool is_matched = true; 1289 bool target_found = false; 1290 int ret; 1291 1292 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, 1293 &headline_idx, rfe, cv); 1294 if (ret) { 1295 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); 1296 return; 1297 } 1298 1299 cfg_target = get_phy_target(table->regs[headline_idx].addr); 1300 for (i = headline_size; i < table->n_regs; i++) { 1301 reg = &table->regs[i]; 1302 cond = get_phy_cond(reg->addr); 1303 switch (cond) { 1304 case PHY_COND_BRANCH_IF: 1305 case PHY_COND_BRANCH_ELIF: 1306 target = get_phy_target(reg->addr); 1307 break; 1308 case PHY_COND_BRANCH_ELSE: 1309 is_matched = false; 1310 if (!target_found) { 1311 rtw89_warn(rtwdev, "failed to load CR %x/%x\n", 1312 reg->addr, reg->data); 1313 return; 1314 } 1315 break; 1316 case PHY_COND_BRANCH_END: 1317 is_matched = true; 1318 target_found = false; 1319 break; 1320 case PHY_COND_CHECK: 1321 if (target_found) { 1322 is_matched = false; 1323 break; 1324 } 1325 1326 if (target == cfg_target) { 1327 is_matched = true; 1328 target_found = true; 1329 } else { 1330 is_matched = false; 1331 target_found = false; 1332 } 1333 break; 1334 default: 1335 if (is_matched) 1336 config(rtwdev, reg, rf_path, extra_data); 1337 break; 1338 } 1339 } 1340 } 1341 1342 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) 1343 { 1344 const struct rtw89_chip_info *chip = rtwdev->chip; 1345 const struct rtw89_phy_table *bb_table = chip->bb_table; 1346 const struct rtw89_phy_table *bb_gain_table = chip->bb_gain_table; 1347 1348 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); 1349 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 1350 if (bb_gain_table) 1351 rtw89_phy_init_reg(rtwdev, bb_gain_table, 1352 rtw89_phy_config_bb_gain, NULL); 1353 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); 1354 } 1355 1356 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 1357 { 1358 rtw89_phy_write32(rtwdev, 0x8080, 0x4); 1359 udelay(1); 1360 return rtw89_phy_read32(rtwdev, 0x8080); 1361 } 1362 1363 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio) 1364 { 1365 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 1366 enum rtw89_rf_path rf_path, void *data); 1367 const struct rtw89_chip_info *chip = rtwdev->chip; 1368 const struct rtw89_phy_table *rf_table; 1369 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; 1370 u8 path; 1371 1372 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); 1373 if (!rf_reg_info) 1374 return; 1375 1376 for (path = RF_PATH_A; path < chip->rf_path_num; path++) { 1377 rf_table = chip->rf_table[path]; 1378 rf_reg_info->rf_path = rf_table->rf_path; 1379 if (noio) 1380 config = rtw89_phy_config_rf_reg_noio; 1381 else 1382 config = rf_table->config ? rf_table->config : 1383 rtw89_phy_config_rf_reg; 1384 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info); 1385 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) 1386 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", 1387 rf_reg_info->rf_path); 1388 } 1389 kfree(rf_reg_info); 1390 } 1391 1392 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) 1393 { 1394 const struct rtw89_chip_info *chip = rtwdev->chip; 1395 const struct rtw89_phy_table *nctl_table; 1396 u32 val; 1397 int ret; 1398 1399 /* IQK/DPK clock & reset */ 1400 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3); 1401 rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1); 1402 rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000); 1403 rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000); 1404 if (chip->chip_id == RTL8852B) 1405 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2); 1406 1407 /* check 0x8080 */ 1408 rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8); 1409 1410 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, 1411 1000, false, rtwdev); 1412 if (ret) 1413 rtw89_err(rtwdev, "failed to poll nctl block\n"); 1414 1415 nctl_table = chip->nctl_table; 1416 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); 1417 } 1418 1419 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) 1420 { 1421 u32 phy_page = addr >> 8; 1422 u32 ofst = 0; 1423 1424 switch (phy_page) { 1425 case 0x6: 1426 case 0x7: 1427 case 0x8: 1428 case 0x9: 1429 case 0xa: 1430 case 0xb: 1431 case 0xc: 1432 case 0xd: 1433 case 0x19: 1434 case 0x1a: 1435 case 0x1b: 1436 ofst = 0x2000; 1437 break; 1438 default: 1439 /* warning case */ 1440 ofst = 0; 1441 break; 1442 } 1443 1444 if (phy_page >= 0x40 && phy_page <= 0x4f) 1445 ofst = 0x2000; 1446 1447 return ofst; 1448 } 1449 1450 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1451 u32 data, enum rtw89_phy_idx phy_idx) 1452 { 1453 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1454 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1455 rtw89_phy_write32_mask(rtwdev, addr, mask, data); 1456 } 1457 EXPORT_SYMBOL(rtw89_phy_write32_idx); 1458 1459 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1460 enum rtw89_phy_idx phy_idx) 1461 { 1462 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1463 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1464 return rtw89_phy_read32_mask(rtwdev, addr, mask); 1465 } 1466 EXPORT_SYMBOL(rtw89_phy_read32_idx); 1467 1468 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1469 u32 val) 1470 { 1471 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 1472 1473 if (!rtwdev->dbcc_en) 1474 return; 1475 1476 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 1477 } 1478 1479 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 1480 const struct rtw89_phy_reg3_tbl *tbl) 1481 { 1482 const struct rtw89_reg3_def *reg3; 1483 int i; 1484 1485 for (i = 0; i < tbl->size; i++) { 1486 reg3 = &tbl->reg3[i]; 1487 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); 1488 } 1489 } 1490 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl); 1491 1492 static const u8 rtw89_rs_idx_max[] = { 1493 [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX, 1494 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX, 1495 [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX, 1496 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX, 1497 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX, 1498 }; 1499 1500 static const u8 rtw89_rs_nss_max[] = { 1501 [RTW89_RS_CCK] = 1, 1502 [RTW89_RS_OFDM] = 1, 1503 [RTW89_RS_MCS] = RTW89_NSS_MAX, 1504 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX, 1505 [RTW89_RS_OFFSET] = 1, 1506 }; 1507 1508 static const u8 _byr_of_rs[] = { 1509 [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck), 1510 [RTW89_RS_OFDM] = offsetof(struct rtw89_txpwr_byrate, ofdm), 1511 [RTW89_RS_MCS] = offsetof(struct rtw89_txpwr_byrate, mcs), 1512 [RTW89_RS_HEDCM] = offsetof(struct rtw89_txpwr_byrate, hedcm), 1513 [RTW89_RS_OFFSET] = offsetof(struct rtw89_txpwr_byrate, offset), 1514 }; 1515 1516 #define _byr_seek(rs, raw) ((s8 *)(raw) + _byr_of_rs[rs]) 1517 #define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_max[rs] + (idx)) 1518 #define _byr_chk(rs, nss, idx) \ 1519 ((nss) < rtw89_rs_nss_max[rs] && (idx) < rtw89_rs_idx_max[rs]) 1520 1521 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 1522 const struct rtw89_txpwr_table *tbl) 1523 { 1524 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; 1525 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; 1526 s8 *byr; 1527 u32 data; 1528 u8 i, idx; 1529 1530 for (; cfg < end; cfg++) { 1531 byr = _byr_seek(cfg->rs, &rtwdev->byr[cfg->band]); 1532 data = cfg->data; 1533 1534 for (i = 0; i < cfg->len; i++, data >>= 8) { 1535 idx = _byr_idx(cfg->rs, cfg->nss, (cfg->shf + i)); 1536 byr[idx] = (s8)(data & 0xff); 1537 } 1538 } 1539 } 1540 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate); 1541 1542 #define _phy_txpwr_rf_to_mac(rtwdev, txpwr_rf) \ 1543 ({ \ 1544 const struct rtw89_chip_info *__c = (rtwdev)->chip; \ 1545 (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \ 1546 }) 1547 1548 static 1549 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, 1550 const struct rtw89_rate_desc *rate_desc) 1551 { 1552 s8 *byr; 1553 u8 idx; 1554 1555 if (rate_desc->rs == RTW89_RS_CCK) 1556 band = RTW89_BAND_2G; 1557 1558 if (!_byr_chk(rate_desc->rs, rate_desc->nss, rate_desc->idx)) { 1559 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1560 "[TXPWR] unknown byrate desc rs=%d nss=%d idx=%d\n", 1561 rate_desc->rs, rate_desc->nss, rate_desc->idx); 1562 1563 return 0; 1564 } 1565 1566 byr = _byr_seek(rate_desc->rs, &rtwdev->byr[band]); 1567 idx = _byr_idx(rate_desc->rs, rate_desc->nss, rate_desc->idx); 1568 1569 return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]); 1570 } 1571 1572 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g) 1573 { 1574 switch (channel_6g) { 1575 case 1 ... 29: 1576 return (channel_6g - 1) / 2; 1577 case 33 ... 61: 1578 return (channel_6g - 3) / 2; 1579 case 65 ... 93: 1580 return (channel_6g - 5) / 2; 1581 case 97 ... 125: 1582 return (channel_6g - 7) / 2; 1583 case 129 ... 157: 1584 return (channel_6g - 9) / 2; 1585 case 161 ... 189: 1586 return (channel_6g - 11) / 2; 1587 case 193 ... 221: 1588 return (channel_6g - 13) / 2; 1589 case 225 ... 253: 1590 return (channel_6g - 15) / 2; 1591 default: 1592 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g); 1593 return 0; 1594 } 1595 } 1596 1597 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel) 1598 { 1599 if (band == RTW89_BAND_6G) 1600 return rtw89_channel_6g_to_idx(rtwdev, channel); 1601 1602 switch (channel) { 1603 case 1 ... 14: 1604 return channel - 1; 1605 case 36 ... 64: 1606 return (channel - 36) / 2; 1607 case 100 ... 144: 1608 return ((channel - 100) / 2) + 15; 1609 case 149 ... 177: 1610 return ((channel - 149) / 2) + 38; 1611 default: 1612 rtw89_warn(rtwdev, "unknown channel: %d\n", channel); 1613 return 0; 1614 } 1615 } 1616 1617 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 1618 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) 1619 { 1620 const struct rtw89_chip_info *chip = rtwdev->chip; 1621 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1622 u8 regd = rtw89_regd_get(rtwdev, band); 1623 s8 lmt = 0, sar; 1624 1625 switch (band) { 1626 case RTW89_BAND_2G: 1627 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf][regd][ch_idx]; 1628 if (!lmt) 1629 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf] 1630 [RTW89_WW][ch_idx]; 1631 break; 1632 case RTW89_BAND_5G: 1633 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf][regd][ch_idx]; 1634 if (!lmt) 1635 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf] 1636 [RTW89_WW][ch_idx]; 1637 break; 1638 case RTW89_BAND_6G: 1639 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf][regd][ch_idx]; 1640 if (!lmt) 1641 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf] 1642 [RTW89_WW][ch_idx]; 1643 break; 1644 default: 1645 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1646 return 0; 1647 } 1648 1649 lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt); 1650 sar = rtw89_query_sar(rtwdev); 1651 1652 return min(lmt, sar); 1653 } 1654 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit); 1655 1656 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \ 1657 do { \ 1658 u8 __i; \ 1659 for (__i = 0; __i < RTW89_BF_NUM; __i++) \ 1660 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ 1661 band, \ 1662 bw, ntx, \ 1663 rs, __i, \ 1664 (ch)); \ 1665 } while (0) 1666 1667 static void rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev *rtwdev, 1668 struct rtw89_txpwr_limit *lmt, 1669 u8 band, u8 ntx, u8 ch) 1670 { 1671 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1672 ntx, RTW89_RS_CCK, ch); 1673 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1674 ntx, RTW89_RS_CCK, ch); 1675 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1676 ntx, RTW89_RS_OFDM, ch); 1677 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1678 RTW89_CHANNEL_WIDTH_20, 1679 ntx, RTW89_RS_MCS, ch); 1680 } 1681 1682 static void rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev *rtwdev, 1683 struct rtw89_txpwr_limit *lmt, 1684 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1685 { 1686 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1687 ntx, RTW89_RS_CCK, ch - 2); 1688 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1689 ntx, RTW89_RS_CCK, ch); 1690 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1691 ntx, RTW89_RS_OFDM, pri_ch); 1692 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1693 RTW89_CHANNEL_WIDTH_20, 1694 ntx, RTW89_RS_MCS, ch - 2); 1695 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1696 RTW89_CHANNEL_WIDTH_20, 1697 ntx, RTW89_RS_MCS, ch + 2); 1698 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1699 RTW89_CHANNEL_WIDTH_40, 1700 ntx, RTW89_RS_MCS, ch); 1701 } 1702 1703 static void rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev *rtwdev, 1704 struct rtw89_txpwr_limit *lmt, 1705 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1706 { 1707 s8 val_0p5_n[RTW89_BF_NUM]; 1708 s8 val_0p5_p[RTW89_BF_NUM]; 1709 u8 i; 1710 1711 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1712 ntx, RTW89_RS_OFDM, pri_ch); 1713 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1714 RTW89_CHANNEL_WIDTH_20, 1715 ntx, RTW89_RS_MCS, ch - 6); 1716 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1717 RTW89_CHANNEL_WIDTH_20, 1718 ntx, RTW89_RS_MCS, ch - 2); 1719 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1720 RTW89_CHANNEL_WIDTH_20, 1721 ntx, RTW89_RS_MCS, ch + 2); 1722 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1723 RTW89_CHANNEL_WIDTH_20, 1724 ntx, RTW89_RS_MCS, ch + 6); 1725 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1726 RTW89_CHANNEL_WIDTH_40, 1727 ntx, RTW89_RS_MCS, ch - 4); 1728 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1729 RTW89_CHANNEL_WIDTH_40, 1730 ntx, RTW89_RS_MCS, ch + 4); 1731 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1732 RTW89_CHANNEL_WIDTH_80, 1733 ntx, RTW89_RS_MCS, ch); 1734 1735 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1736 ntx, RTW89_RS_MCS, ch - 4); 1737 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1738 ntx, RTW89_RS_MCS, ch + 4); 1739 1740 for (i = 0; i < RTW89_BF_NUM; i++) 1741 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1742 } 1743 1744 static void rtw89_phy_fill_txpwr_limit_160m(struct rtw89_dev *rtwdev, 1745 struct rtw89_txpwr_limit *lmt, 1746 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1747 { 1748 s8 val_0p5_n[RTW89_BF_NUM]; 1749 s8 val_0p5_p[RTW89_BF_NUM]; 1750 s8 val_2p5_n[RTW89_BF_NUM]; 1751 s8 val_2p5_p[RTW89_BF_NUM]; 1752 u8 i; 1753 1754 /* fill ofdm section */ 1755 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1756 ntx, RTW89_RS_OFDM, pri_ch); 1757 1758 /* fill mcs 20m section */ 1759 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1760 RTW89_CHANNEL_WIDTH_20, 1761 ntx, RTW89_RS_MCS, ch - 14); 1762 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1763 RTW89_CHANNEL_WIDTH_20, 1764 ntx, RTW89_RS_MCS, ch - 10); 1765 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1766 RTW89_CHANNEL_WIDTH_20, 1767 ntx, RTW89_RS_MCS, ch - 6); 1768 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1769 RTW89_CHANNEL_WIDTH_20, 1770 ntx, RTW89_RS_MCS, ch - 2); 1771 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band, 1772 RTW89_CHANNEL_WIDTH_20, 1773 ntx, RTW89_RS_MCS, ch + 2); 1774 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band, 1775 RTW89_CHANNEL_WIDTH_20, 1776 ntx, RTW89_RS_MCS, ch + 6); 1777 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band, 1778 RTW89_CHANNEL_WIDTH_20, 1779 ntx, RTW89_RS_MCS, ch + 10); 1780 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band, 1781 RTW89_CHANNEL_WIDTH_20, 1782 ntx, RTW89_RS_MCS, ch + 14); 1783 1784 /* fill mcs 40m section */ 1785 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1786 RTW89_CHANNEL_WIDTH_40, 1787 ntx, RTW89_RS_MCS, ch - 12); 1788 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1789 RTW89_CHANNEL_WIDTH_40, 1790 ntx, RTW89_RS_MCS, ch - 4); 1791 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band, 1792 RTW89_CHANNEL_WIDTH_40, 1793 ntx, RTW89_RS_MCS, ch + 4); 1794 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band, 1795 RTW89_CHANNEL_WIDTH_40, 1796 ntx, RTW89_RS_MCS, ch + 12); 1797 1798 /* fill mcs 80m section */ 1799 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1800 RTW89_CHANNEL_WIDTH_80, 1801 ntx, RTW89_RS_MCS, ch - 8); 1802 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band, 1803 RTW89_CHANNEL_WIDTH_80, 1804 ntx, RTW89_RS_MCS, ch + 8); 1805 1806 /* fill mcs 160m section */ 1807 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band, 1808 RTW89_CHANNEL_WIDTH_160, 1809 ntx, RTW89_RS_MCS, ch); 1810 1811 /* fill mcs 40m 0p5 section */ 1812 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1813 ntx, RTW89_RS_MCS, ch - 4); 1814 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1815 ntx, RTW89_RS_MCS, ch + 4); 1816 1817 for (i = 0; i < RTW89_BF_NUM; i++) 1818 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1819 1820 /* fill mcs 40m 2p5 section */ 1821 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40, 1822 ntx, RTW89_RS_MCS, ch - 8); 1823 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40, 1824 ntx, RTW89_RS_MCS, ch + 8); 1825 1826 for (i = 0; i < RTW89_BF_NUM; i++) 1827 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]); 1828 } 1829 1830 static 1831 void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev, 1832 const struct rtw89_chan *chan, 1833 struct rtw89_txpwr_limit *lmt, 1834 u8 ntx) 1835 { 1836 u8 band = chan->band_type; 1837 u8 pri_ch = chan->primary_channel; 1838 u8 ch = chan->channel; 1839 u8 bw = chan->band_width; 1840 1841 memset(lmt, 0, sizeof(*lmt)); 1842 1843 switch (bw) { 1844 case RTW89_CHANNEL_WIDTH_20: 1845 rtw89_phy_fill_txpwr_limit_20m(rtwdev, lmt, band, ntx, ch); 1846 break; 1847 case RTW89_CHANNEL_WIDTH_40: 1848 rtw89_phy_fill_txpwr_limit_40m(rtwdev, lmt, band, ntx, ch, 1849 pri_ch); 1850 break; 1851 case RTW89_CHANNEL_WIDTH_80: 1852 rtw89_phy_fill_txpwr_limit_80m(rtwdev, lmt, band, ntx, ch, 1853 pri_ch); 1854 break; 1855 case RTW89_CHANNEL_WIDTH_160: 1856 rtw89_phy_fill_txpwr_limit_160m(rtwdev, lmt, band, ntx, ch, 1857 pri_ch); 1858 break; 1859 } 1860 } 1861 1862 static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 1863 u8 ru, u8 ntx, u8 ch) 1864 { 1865 const struct rtw89_chip_info *chip = rtwdev->chip; 1866 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1867 u8 regd = rtw89_regd_get(rtwdev, band); 1868 s8 lmt_ru = 0, sar; 1869 1870 switch (band) { 1871 case RTW89_BAND_2G: 1872 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx][regd][ch_idx]; 1873 if (!lmt_ru) 1874 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx] 1875 [RTW89_WW][ch_idx]; 1876 break; 1877 case RTW89_BAND_5G: 1878 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx][regd][ch_idx]; 1879 if (!lmt_ru) 1880 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx] 1881 [RTW89_WW][ch_idx]; 1882 break; 1883 case RTW89_BAND_6G: 1884 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx][regd][ch_idx]; 1885 if (!lmt_ru) 1886 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx] 1887 [RTW89_WW][ch_idx]; 1888 break; 1889 default: 1890 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1891 return 0; 1892 } 1893 1894 lmt_ru = _phy_txpwr_rf_to_mac(rtwdev, lmt_ru); 1895 sar = rtw89_query_sar(rtwdev); 1896 1897 return min(lmt_ru, sar); 1898 } 1899 1900 static void 1901 rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev, 1902 struct rtw89_txpwr_limit_ru *lmt_ru, 1903 u8 band, u8 ntx, u8 ch) 1904 { 1905 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1906 RTW89_RU26, 1907 ntx, ch); 1908 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1909 RTW89_RU52, 1910 ntx, ch); 1911 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1912 RTW89_RU106, 1913 ntx, ch); 1914 } 1915 1916 static void 1917 rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev, 1918 struct rtw89_txpwr_limit_ru *lmt_ru, 1919 u8 band, u8 ntx, u8 ch) 1920 { 1921 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1922 RTW89_RU26, 1923 ntx, ch - 2); 1924 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1925 RTW89_RU26, 1926 ntx, ch + 2); 1927 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1928 RTW89_RU52, 1929 ntx, ch - 2); 1930 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1931 RTW89_RU52, 1932 ntx, ch + 2); 1933 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1934 RTW89_RU106, 1935 ntx, ch - 2); 1936 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1937 RTW89_RU106, 1938 ntx, ch + 2); 1939 } 1940 1941 static void 1942 rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev, 1943 struct rtw89_txpwr_limit_ru *lmt_ru, 1944 u8 band, u8 ntx, u8 ch) 1945 { 1946 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1947 RTW89_RU26, 1948 ntx, ch - 6); 1949 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1950 RTW89_RU26, 1951 ntx, ch - 2); 1952 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1953 RTW89_RU26, 1954 ntx, ch + 2); 1955 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1956 RTW89_RU26, 1957 ntx, ch + 6); 1958 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1959 RTW89_RU52, 1960 ntx, ch - 6); 1961 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1962 RTW89_RU52, 1963 ntx, ch - 2); 1964 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1965 RTW89_RU52, 1966 ntx, ch + 2); 1967 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1968 RTW89_RU52, 1969 ntx, ch + 6); 1970 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1971 RTW89_RU106, 1972 ntx, ch - 6); 1973 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1974 RTW89_RU106, 1975 ntx, ch - 2); 1976 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1977 RTW89_RU106, 1978 ntx, ch + 2); 1979 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1980 RTW89_RU106, 1981 ntx, ch + 6); 1982 } 1983 1984 static void 1985 rtw89_phy_fill_txpwr_limit_ru_160m(struct rtw89_dev *rtwdev, 1986 struct rtw89_txpwr_limit_ru *lmt_ru, 1987 u8 band, u8 ntx, u8 ch) 1988 { 1989 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 }; 1990 int i; 1991 1992 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM); 1993 for (i = 0; i < RTW89_RU_SEC_NUM; i++) { 1994 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1995 RTW89_RU26, 1996 ntx, 1997 ch + ofst[i]); 1998 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1999 RTW89_RU52, 2000 ntx, 2001 ch + ofst[i]); 2002 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2003 RTW89_RU106, 2004 ntx, 2005 ch + ofst[i]); 2006 } 2007 } 2008 2009 static 2010 void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, 2011 const struct rtw89_chan *chan, 2012 struct rtw89_txpwr_limit_ru *lmt_ru, 2013 u8 ntx) 2014 { 2015 u8 band = chan->band_type; 2016 u8 ch = chan->channel; 2017 u8 bw = chan->band_width; 2018 2019 memset(lmt_ru, 0, sizeof(*lmt_ru)); 2020 2021 switch (bw) { 2022 case RTW89_CHANNEL_WIDTH_20: 2023 rtw89_phy_fill_txpwr_limit_ru_20m(rtwdev, lmt_ru, band, ntx, 2024 ch); 2025 break; 2026 case RTW89_CHANNEL_WIDTH_40: 2027 rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, band, ntx, 2028 ch); 2029 break; 2030 case RTW89_CHANNEL_WIDTH_80: 2031 rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, band, ntx, 2032 ch); 2033 break; 2034 case RTW89_CHANNEL_WIDTH_160: 2035 rtw89_phy_fill_txpwr_limit_ru_160m(rtwdev, lmt_ru, band, ntx, 2036 ch); 2037 break; 2038 } 2039 } 2040 2041 void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev, 2042 const struct rtw89_chan *chan, 2043 enum rtw89_phy_idx phy_idx) 2044 { 2045 static const u8 rs[] = { 2046 RTW89_RS_CCK, 2047 RTW89_RS_OFDM, 2048 RTW89_RS_MCS, 2049 RTW89_RS_HEDCM, 2050 }; 2051 struct rtw89_rate_desc cur; 2052 u8 band = chan->band_type; 2053 u8 ch = chan->channel; 2054 u32 addr, val; 2055 s8 v[4] = {}; 2056 u8 i; 2057 2058 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2059 "[TXPWR] set txpwr byrate with ch=%d\n", ch); 2060 2061 BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_CCK] % 4); 2062 BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_OFDM] % 4); 2063 BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_MCS] % 4); 2064 BUILD_BUG_ON(rtw89_rs_idx_max[RTW89_RS_HEDCM] % 4); 2065 2066 addr = R_AX_PWR_BY_RATE; 2067 for (cur.nss = 0; cur.nss <= RTW89_NSS_2; cur.nss++) { 2068 for (i = 0; i < ARRAY_SIZE(rs); i++) { 2069 if (cur.nss >= rtw89_rs_nss_max[rs[i]]) 2070 continue; 2071 2072 cur.rs = rs[i]; 2073 for (cur.idx = 0; cur.idx < rtw89_rs_idx_max[rs[i]]; 2074 cur.idx++) { 2075 v[cur.idx % 4] = 2076 rtw89_phy_read_txpwr_byrate(rtwdev, 2077 band, 2078 &cur); 2079 2080 if ((cur.idx + 1) % 4) 2081 continue; 2082 2083 val = FIELD_PREP(GENMASK(7, 0), v[0]) | 2084 FIELD_PREP(GENMASK(15, 8), v[1]) | 2085 FIELD_PREP(GENMASK(23, 16), v[2]) | 2086 FIELD_PREP(GENMASK(31, 24), v[3]); 2087 2088 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 2089 val); 2090 addr += 4; 2091 } 2092 } 2093 } 2094 } 2095 EXPORT_SYMBOL(rtw89_phy_set_txpwr_byrate); 2096 2097 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev, 2098 const struct rtw89_chan *chan, 2099 enum rtw89_phy_idx phy_idx) 2100 { 2101 struct rtw89_rate_desc desc = { 2102 .nss = RTW89_NSS_1, 2103 .rs = RTW89_RS_OFFSET, 2104 }; 2105 u8 band = chan->band_type; 2106 s8 v[RTW89_RATE_OFFSET_MAX] = {}; 2107 u32 val; 2108 2109 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n"); 2110 2111 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_MAX; desc.idx++) 2112 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, &desc); 2113 2114 BUILD_BUG_ON(RTW89_RATE_OFFSET_MAX != 5); 2115 val = FIELD_PREP(GENMASK(3, 0), v[0]) | 2116 FIELD_PREP(GENMASK(7, 4), v[1]) | 2117 FIELD_PREP(GENMASK(11, 8), v[2]) | 2118 FIELD_PREP(GENMASK(15, 12), v[3]) | 2119 FIELD_PREP(GENMASK(19, 16), v[4]); 2120 2121 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL, 2122 GENMASK(19, 0), val); 2123 } 2124 EXPORT_SYMBOL(rtw89_phy_set_txpwr_offset); 2125 2126 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev, 2127 const struct rtw89_chan *chan, 2128 enum rtw89_phy_idx phy_idx) 2129 { 2130 struct rtw89_txpwr_limit lmt; 2131 u8 ch = chan->channel; 2132 u8 bw = chan->band_width; 2133 const s8 *ptr; 2134 u32 addr, val; 2135 u8 i, j; 2136 2137 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2138 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw); 2139 2140 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit) != 2141 RTW89_TXPWR_LMT_PAGE_SIZE); 2142 2143 addr = R_AX_PWR_LMT; 2144 for (i = 0; i < RTW89_NTX_NUM; i++) { 2145 rtw89_phy_fill_txpwr_limit(rtwdev, chan, &lmt, i); 2146 2147 ptr = (s8 *)&lmt; 2148 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE; 2149 j += 4, addr += 4, ptr += 4) { 2150 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2151 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2152 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2153 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2154 2155 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2156 } 2157 } 2158 } 2159 EXPORT_SYMBOL(rtw89_phy_set_txpwr_limit); 2160 2161 void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, 2162 const struct rtw89_chan *chan, 2163 enum rtw89_phy_idx phy_idx) 2164 { 2165 struct rtw89_txpwr_limit_ru lmt_ru; 2166 u8 ch = chan->channel; 2167 u8 bw = chan->band_width; 2168 const s8 *ptr; 2169 u32 addr, val; 2170 u8 i, j; 2171 2172 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2173 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); 2174 2175 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru) != 2176 RTW89_TXPWR_LMT_RU_PAGE_SIZE); 2177 2178 addr = R_AX_PWR_RU_LMT; 2179 for (i = 0; i < RTW89_NTX_NUM; i++) { 2180 rtw89_phy_fill_txpwr_limit_ru(rtwdev, chan, &lmt_ru, i); 2181 2182 ptr = (s8 *)&lmt_ru; 2183 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE; 2184 j += 4, addr += 4, ptr += 4) { 2185 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2186 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2187 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2188 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2189 2190 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2191 } 2192 } 2193 } 2194 EXPORT_SYMBOL(rtw89_phy_set_txpwr_limit_ru); 2195 2196 struct rtw89_phy_iter_ra_data { 2197 struct rtw89_dev *rtwdev; 2198 struct sk_buff *c2h; 2199 }; 2200 2201 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) 2202 { 2203 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; 2204 struct rtw89_dev *rtwdev = ra_data->rtwdev; 2205 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2206 struct rtw89_ra_report *ra_report = &rtwsta->ra_report; 2207 struct sk_buff *c2h = ra_data->c2h; 2208 u8 mode, rate, bw, giltf, mac_id; 2209 u16 legacy_bitrate; 2210 bool valid; 2211 u8 mcs = 0; 2212 2213 mac_id = RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h->data); 2214 if (mac_id != rtwsta->mac_id) 2215 return; 2216 2217 rate = RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h->data); 2218 bw = RTW89_GET_PHY_C2H_RA_RPT_BW(c2h->data); 2219 giltf = RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h->data); 2220 mode = RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h->data); 2221 2222 if (mode == RTW89_RA_RPT_MODE_LEGACY) { 2223 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate); 2224 if (!valid) 2225 return; 2226 } 2227 2228 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate)); 2229 2230 switch (mode) { 2231 case RTW89_RA_RPT_MODE_LEGACY: 2232 ra_report->txrate.legacy = legacy_bitrate; 2233 break; 2234 case RTW89_RA_RPT_MODE_HT: 2235 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; 2236 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw)) 2237 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), 2238 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); 2239 else 2240 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); 2241 ra_report->txrate.mcs = rate; 2242 if (giltf) 2243 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2244 mcs = ra_report->txrate.mcs & 0x07; 2245 break; 2246 case RTW89_RA_RPT_MODE_VHT: 2247 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; 2248 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 2249 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 2250 if (giltf) 2251 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2252 mcs = ra_report->txrate.mcs; 2253 break; 2254 case RTW89_RA_RPT_MODE_HE: 2255 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; 2256 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 2257 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 2258 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2259 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; 2260 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2261 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; 2262 else 2263 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; 2264 mcs = ra_report->txrate.mcs; 2265 break; 2266 } 2267 2268 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw); 2269 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); 2270 ra_report->hw_rate = FIELD_PREP(RTW89_HW_RATE_MASK_MOD, mode) | 2271 FIELD_PREP(RTW89_HW_RATE_MASK_VAL, rate); 2272 ra_report->might_fallback_legacy = mcs <= 2; 2273 sta->deflink.agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); 2274 rtwsta->max_agg_wait = sta->deflink.agg.max_rc_amsdu_len / 1500 - 1; 2275 } 2276 2277 static void 2278 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2279 { 2280 struct rtw89_phy_iter_ra_data ra_data; 2281 2282 ra_data.rtwdev = rtwdev; 2283 ra_data.c2h = c2h; 2284 ieee80211_iterate_stations_atomic(rtwdev->hw, 2285 rtw89_phy_c2h_ra_rpt_iter, 2286 &ra_data); 2287 } 2288 2289 static 2290 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, 2291 struct sk_buff *c2h, u32 len) = { 2292 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 2293 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 2294 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 2295 }; 2296 2297 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 2298 u32 len, u8 class, u8 func) 2299 { 2300 void (*handler)(struct rtw89_dev *rtwdev, 2301 struct sk_buff *c2h, u32 len) = NULL; 2302 2303 switch (class) { 2304 case RTW89_PHY_C2H_CLASS_RA: 2305 if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 2306 handler = rtw89_phy_c2h_ra_handler[func]; 2307 break; 2308 case RTW89_PHY_C2H_CLASS_DM: 2309 if (func == RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY) 2310 return; 2311 fallthrough; 2312 default: 2313 rtw89_info(rtwdev, "c2h class %d not support\n", class); 2314 return; 2315 } 2316 if (!handler) { 2317 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 2318 func); 2319 return; 2320 } 2321 handler(rtwdev, skb, len); 2322 } 2323 2324 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) 2325 { 2326 u32 reg_mask; 2327 2328 if (sc_xo) 2329 reg_mask = B_AX_XTAL_SC_XO_MASK; 2330 else 2331 reg_mask = B_AX_XTAL_SC_XI_MASK; 2332 2333 return (u8)rtw89_read32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask); 2334 } 2335 2336 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, 2337 u8 val) 2338 { 2339 u32 reg_mask; 2340 2341 if (sc_xo) 2342 reg_mask = B_AX_XTAL_SC_XO_MASK; 2343 else 2344 reg_mask = B_AX_XTAL_SC_XI_MASK; 2345 2346 rtw89_write32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask, val); 2347 } 2348 2349 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, 2350 u8 crystal_cap, bool force) 2351 { 2352 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2353 const struct rtw89_chip_info *chip = rtwdev->chip; 2354 u8 sc_xi_val, sc_xo_val; 2355 2356 if (!force && cfo->crystal_cap == crystal_cap) 2357 return; 2358 crystal_cap = clamp_t(u8, crystal_cap, 0, 127); 2359 if (chip->chip_id == RTL8852A) { 2360 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); 2361 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); 2362 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); 2363 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); 2364 } else { 2365 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, 2366 crystal_cap, XTAL_SC_XO_MASK); 2367 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, 2368 crystal_cap, XTAL_SC_XI_MASK); 2369 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val); 2370 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val); 2371 } 2372 cfo->crystal_cap = sc_xi_val; 2373 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); 2374 2375 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); 2376 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); 2377 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", 2378 cfo->x_cap_ofst); 2379 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); 2380 } 2381 2382 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) 2383 { 2384 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2385 u8 cap; 2386 2387 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; 2388 cfo->is_adjust = false; 2389 if (cfo->crystal_cap == cfo->def_x_cap) 2390 return; 2391 cap = cfo->crystal_cap; 2392 cap += (cap > cfo->def_x_cap ? -1 : 1); 2393 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); 2394 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2395 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, 2396 cfo->def_x_cap); 2397 } 2398 2399 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) 2400 { 2401 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp; 2402 bool is_linked = rtwdev->total_sta_assoc > 0; 2403 s32 cfo_avg_312; 2404 s32 dcfo_comp_val; 2405 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft; 2406 int sign; 2407 2408 if (!is_linked) { 2409 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", 2410 is_linked); 2411 return; 2412 } 2413 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); 2414 if (curr_cfo == 0) 2415 return; 2416 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); 2417 sign = curr_cfo > 0 ? 1 : -1; 2418 cfo_avg_312 = (curr_cfo << dcfo_comp_sft) / 5 + sign * dcfo_comp_val; 2419 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: avg_cfo=%d\n", cfo_avg_312); 2420 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 2421 cfo_avg_312 = -cfo_avg_312; 2422 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask, 2423 cfo_avg_312); 2424 } 2425 2426 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) 2427 { 2428 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_OPT, B_DCFO_OPT_EN, 1); 2429 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_WEIGHT, B_DCFO_WEIGHT_MSK, 8); 2430 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, B_AX_PWR_UL_CFO_MASK); 2431 } 2432 2433 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) 2434 { 2435 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2436 struct rtw89_efuse *efuse = &rtwdev->efuse; 2437 2438 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; 2439 cfo->crystal_cap = cfo->crystal_cap_default; 2440 cfo->def_x_cap = cfo->crystal_cap; 2441 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f); 2442 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1); 2443 cfo->is_adjust = false; 2444 cfo->divergence_lock_en = false; 2445 cfo->x_cap_ofst = 0; 2446 cfo->lock_cnt = 0; 2447 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; 2448 cfo->apply_compensation = false; 2449 cfo->residual_cfo_acc = 0; 2450 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", 2451 cfo->crystal_cap_default); 2452 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); 2453 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); 2454 rtw89_dcfo_comp_init(rtwdev); 2455 cfo->cfo_timer_ms = 2000; 2456 cfo->cfo_trig_by_timer_en = false; 2457 cfo->phy_cfo_trk_cnt = 0; 2458 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2459 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE; 2460 } 2461 2462 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, 2463 s32 curr_cfo) 2464 { 2465 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2466 s8 crystal_cap = cfo->crystal_cap; 2467 s32 cfo_abs = abs(curr_cfo); 2468 int sign; 2469 2470 if (!cfo->is_adjust) { 2471 if (cfo_abs > CFO_TRK_ENABLE_TH) 2472 cfo->is_adjust = true; 2473 } else { 2474 if (cfo_abs < CFO_TRK_STOP_TH) 2475 cfo->is_adjust = false; 2476 } 2477 if (!cfo->is_adjust) { 2478 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); 2479 return; 2480 } 2481 sign = curr_cfo > 0 ? 1 : -1; 2482 if (cfo_abs > CFO_TRK_STOP_TH_4) 2483 crystal_cap += 7 * sign; 2484 else if (cfo_abs > CFO_TRK_STOP_TH_3) 2485 crystal_cap += 5 * sign; 2486 else if (cfo_abs > CFO_TRK_STOP_TH_2) 2487 crystal_cap += 3 * sign; 2488 else if (cfo_abs > CFO_TRK_STOP_TH_1) 2489 crystal_cap += 1 * sign; 2490 else 2491 return; 2492 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); 2493 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2494 "X_cap{Curr,Default}={0x%x,0x%x}\n", 2495 cfo->crystal_cap, cfo->def_x_cap); 2496 } 2497 2498 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) 2499 { 2500 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2501 s32 cfo_khz_all = 0; 2502 s32 cfo_cnt_all = 0; 2503 s32 cfo_all_avg = 0; 2504 u8 i; 2505 2506 if (rtwdev->total_sta_assoc != 1) 2507 return 0; 2508 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); 2509 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2510 if (cfo->cfo_cnt[i] == 0) 2511 continue; 2512 cfo_khz_all += cfo->cfo_tail[i]; 2513 cfo_cnt_all += cfo->cfo_cnt[i]; 2514 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); 2515 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2516 } 2517 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2518 "CFO track for macid = %d\n", i); 2519 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2520 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", 2521 cfo_khz_all, cfo_cnt_all, cfo_all_avg); 2522 return cfo_all_avg; 2523 } 2524 2525 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) 2526 { 2527 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2528 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2529 s32 target_cfo = 0; 2530 s32 cfo_khz_all = 0; 2531 s32 cfo_khz_all_tp_wgt = 0; 2532 s32 cfo_avg = 0; 2533 s32 max_cfo_lb = BIT(31); 2534 s32 min_cfo_ub = GENMASK(30, 0); 2535 u16 cfo_cnt_all = 0; 2536 u8 active_entry_cnt = 0; 2537 u8 sta_cnt = 0; 2538 u32 tp_all = 0; 2539 u8 i; 2540 u8 cfo_tol = 0; 2541 2542 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); 2543 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { 2544 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); 2545 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2546 if (cfo->cfo_cnt[i] == 0) 2547 continue; 2548 cfo_khz_all += cfo->cfo_tail[i]; 2549 cfo_cnt_all += cfo->cfo_cnt[i]; 2550 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); 2551 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2552 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", 2553 cfo_khz_all, cfo_cnt_all, cfo_avg); 2554 target_cfo = cfo_avg; 2555 } 2556 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { 2557 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); 2558 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2559 if (cfo->cfo_cnt[i] == 0) 2560 continue; 2561 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2562 (s32)cfo->cfo_cnt[i]); 2563 cfo_khz_all += cfo->cfo_avg[i]; 2564 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2565 "Macid=%d, cfo_avg=%d\n", i, 2566 cfo->cfo_avg[i]); 2567 } 2568 sta_cnt = rtwdev->total_sta_assoc; 2569 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); 2570 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2571 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", 2572 cfo_khz_all, sta_cnt, cfo_avg); 2573 target_cfo = cfo_avg; 2574 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { 2575 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); 2576 cfo_tol = cfo->sta_cfo_tolerance; 2577 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2578 sta_cnt++; 2579 if (cfo->cfo_cnt[i] != 0) { 2580 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2581 (s32)cfo->cfo_cnt[i]); 2582 active_entry_cnt++; 2583 } else { 2584 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; 2585 } 2586 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); 2587 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); 2588 cfo_khz_all += cfo->cfo_avg[i]; 2589 /* need tp for each entry */ 2590 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2591 "[%d] cfo_avg=%d, tp=tbd\n", 2592 i, cfo->cfo_avg[i]); 2593 if (sta_cnt >= rtwdev->total_sta_assoc) 2594 break; 2595 } 2596 tp_all = stats->rx_throughput; /* need tp for each entry */ 2597 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); 2598 2599 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", 2600 sta_cnt); 2601 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", 2602 active_entry_cnt); 2603 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2604 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", 2605 cfo_khz_all_tp_wgt, cfo_avg); 2606 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", 2607 max_cfo_lb, min_cfo_ub); 2608 if (max_cfo_lb <= min_cfo_ub) { 2609 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2610 "cfo win_size=%d\n", 2611 min_cfo_ub - max_cfo_lb); 2612 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); 2613 } else { 2614 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2615 "No intersection of cfo tolerance windows\n"); 2616 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); 2617 } 2618 for (i = 0; i < CFO_TRACK_MAX_USER; i++) 2619 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2620 } 2621 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); 2622 return target_cfo; 2623 } 2624 2625 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) 2626 { 2627 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2628 2629 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); 2630 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); 2631 cfo->packet_count = 0; 2632 cfo->packet_count_pre = 0; 2633 cfo->cfo_avg_pre = 0; 2634 } 2635 2636 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) 2637 { 2638 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2639 s32 new_cfo = 0; 2640 bool x_cap_update = false; 2641 u8 pre_x_cap = cfo->crystal_cap; 2642 2643 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", 2644 rtwdev->total_sta_assoc); 2645 if (rtwdev->total_sta_assoc == 0) { 2646 rtw89_phy_cfo_reset(rtwdev); 2647 return; 2648 } 2649 if (cfo->packet_count == 0) { 2650 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); 2651 return; 2652 } 2653 if (cfo->packet_count == cfo->packet_count_pre) { 2654 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); 2655 return; 2656 } 2657 if (rtwdev->total_sta_assoc == 1) 2658 new_cfo = rtw89_phy_average_cfo_calc(rtwdev); 2659 else 2660 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); 2661 if (new_cfo == 0) { 2662 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); 2663 return; 2664 } 2665 if (cfo->divergence_lock_en) { 2666 cfo->lock_cnt++; 2667 if (cfo->lock_cnt > CFO_PERIOD_CNT) { 2668 cfo->divergence_lock_en = false; 2669 cfo->lock_cnt = 0; 2670 } else { 2671 rtw89_phy_cfo_reset(rtwdev); 2672 } 2673 return; 2674 } 2675 if (cfo->crystal_cap >= cfo->x_cap_ub || 2676 cfo->crystal_cap <= cfo->x_cap_lb) { 2677 cfo->divergence_lock_en = true; 2678 rtw89_phy_cfo_reset(rtwdev); 2679 return; 2680 } 2681 2682 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); 2683 cfo->cfo_avg_pre = new_cfo; 2684 x_cap_update = cfo->crystal_cap != pre_x_cap; 2685 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); 2686 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", 2687 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, 2688 cfo->x_cap_ofst); 2689 if (x_cap_update) { 2690 if (new_cfo > 0) 2691 new_cfo -= CFO_SW_COMP_FINE_TUNE; 2692 else 2693 new_cfo += CFO_SW_COMP_FINE_TUNE; 2694 } 2695 rtw89_dcfo_comp(rtwdev, new_cfo); 2696 rtw89_phy_cfo_statistics_reset(rtwdev); 2697 } 2698 2699 void rtw89_phy_cfo_track_work(struct work_struct *work) 2700 { 2701 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2702 cfo_track_work.work); 2703 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2704 2705 mutex_lock(&rtwdev->mutex); 2706 if (!cfo->cfo_trig_by_timer_en) 2707 goto out; 2708 rtw89_leave_ps_mode(rtwdev); 2709 rtw89_phy_cfo_dm(rtwdev); 2710 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2711 msecs_to_jiffies(cfo->cfo_timer_ms)); 2712 out: 2713 mutex_unlock(&rtwdev->mutex); 2714 } 2715 2716 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) 2717 { 2718 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2719 2720 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2721 msecs_to_jiffies(cfo->cfo_timer_ms)); 2722 } 2723 2724 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) 2725 { 2726 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2727 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2728 bool is_ul_ofdma = false, ofdma_acc_en = false; 2729 2730 if (stats->rx_tf_periodic > CFO_TF_CNT_TH) 2731 is_ul_ofdma = true; 2732 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE && 2733 is_ul_ofdma) 2734 ofdma_acc_en = true; 2735 2736 switch (cfo->phy_cfo_status) { 2737 case RTW89_PHY_DCFO_STATE_NORMAL: 2738 if (stats->tx_throughput >= CFO_TP_UPPER) { 2739 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; 2740 cfo->cfo_trig_by_timer_en = true; 2741 cfo->cfo_timer_ms = CFO_COMP_PERIOD; 2742 rtw89_phy_cfo_start_work(rtwdev); 2743 } 2744 break; 2745 case RTW89_PHY_DCFO_STATE_ENHANCE: 2746 if (stats->tx_throughput <= CFO_TP_LOWER) 2747 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2748 else if (ofdma_acc_en && 2749 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) 2750 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD; 2751 else 2752 cfo->phy_cfo_trk_cnt++; 2753 2754 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) { 2755 cfo->phy_cfo_trk_cnt = 0; 2756 cfo->cfo_trig_by_timer_en = false; 2757 } 2758 break; 2759 case RTW89_PHY_DCFO_STATE_HOLD: 2760 if (stats->tx_throughput <= CFO_TP_LOWER) { 2761 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2762 cfo->phy_cfo_trk_cnt = 0; 2763 cfo->cfo_trig_by_timer_en = false; 2764 } else { 2765 cfo->phy_cfo_trk_cnt++; 2766 } 2767 break; 2768 default: 2769 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2770 cfo->phy_cfo_trk_cnt = 0; 2771 break; 2772 } 2773 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2774 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", 2775 stats->tx_throughput, cfo->phy_cfo_status, 2776 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, 2777 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); 2778 if (cfo->cfo_trig_by_timer_en) 2779 return; 2780 rtw89_phy_cfo_dm(rtwdev); 2781 } 2782 2783 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 2784 struct rtw89_rx_phy_ppdu *phy_ppdu) 2785 { 2786 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2787 u8 macid = phy_ppdu->mac_id; 2788 2789 if (macid >= CFO_TRACK_MAX_USER) { 2790 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid); 2791 return; 2792 } 2793 2794 cfo->cfo_tail[macid] += cfo_val; 2795 cfo->cfo_cnt[macid]++; 2796 cfo->packet_count++; 2797 } 2798 2799 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2800 { 2801 const struct rtw89_chip_info *chip = rtwdev->chip; 2802 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 2803 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 2804 2805 if (!chip->support_ul_tb_ctrl) 2806 return; 2807 2808 rtwvif->def_tri_idx = 2809 rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG); 2810 2811 if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV) 2812 rtwvif->dyn_tb_bedge_en = false; 2813 else if (chan->band_type >= RTW89_BAND_5G && 2814 chan->band_width >= RTW89_CHANNEL_WIDTH_40) 2815 rtwvif->dyn_tb_bedge_en = true; 2816 else 2817 rtwvif->dyn_tb_bedge_en = false; 2818 2819 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2820 "[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n", 2821 ul_tb_info->def_if_bandedge, rtwvif->def_tri_idx); 2822 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2823 "[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n", 2824 rtwvif->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en); 2825 } 2826 2827 struct rtw89_phy_ul_tb_check_data { 2828 bool valid; 2829 bool high_tf_client; 2830 bool low_tf_client; 2831 bool dyn_tb_bedge_en; 2832 u8 def_tri_idx; 2833 }; 2834 2835 static 2836 void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev, 2837 struct rtw89_vif *rtwvif, 2838 struct rtw89_phy_ul_tb_check_data *ul_tb_data) 2839 { 2840 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2841 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2842 2843 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 2844 return; 2845 2846 if (!vif->cfg.assoc) 2847 return; 2848 2849 if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH) 2850 ul_tb_data->high_tf_client = true; 2851 else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH) 2852 ul_tb_data->low_tf_client = true; 2853 2854 ul_tb_data->valid = true; 2855 ul_tb_data->def_tri_idx = rtwvif->def_tri_idx; 2856 ul_tb_data->dyn_tb_bedge_en = rtwvif->dyn_tb_bedge_en; 2857 } 2858 2859 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev) 2860 { 2861 const struct rtw89_chip_info *chip = rtwdev->chip; 2862 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 2863 struct rtw89_phy_ul_tb_check_data ul_tb_data = {}; 2864 struct rtw89_vif *rtwvif; 2865 2866 if (!chip->support_ul_tb_ctrl) 2867 return; 2868 2869 if (rtwdev->total_sta_assoc != 1) 2870 return; 2871 2872 rtw89_for_each_rtwvif(rtwdev, rtwvif) 2873 rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif, &ul_tb_data); 2874 2875 if (!ul_tb_data.valid) 2876 return; 2877 2878 if (ul_tb_data.dyn_tb_bedge_en) { 2879 if (ul_tb_data.high_tf_client) { 2880 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0); 2881 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2882 "[ULTB] Turn off if_bandedge\n"); 2883 } else if (ul_tb_data.low_tf_client) { 2884 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 2885 ul_tb_info->def_if_bandedge); 2886 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2887 "[ULTB] Set to default if_bandedge = %d\n", 2888 ul_tb_info->def_if_bandedge); 2889 } 2890 } 2891 2892 if (ul_tb_info->dyn_tb_tri_en) { 2893 if (ul_tb_data.high_tf_client) { 2894 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 2895 B_TXSHAPE_TRIANGULAR_CFG, 0); 2896 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2897 "[ULTB] Turn off Tx triangle\n"); 2898 } else if (ul_tb_data.low_tf_client) { 2899 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 2900 B_TXSHAPE_TRIANGULAR_CFG, 2901 ul_tb_data.def_tri_idx); 2902 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2903 "[ULTB] Set to default tx_shap_idx = %d\n", 2904 ul_tb_data.def_tri_idx); 2905 } 2906 } 2907 } 2908 2909 static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev) 2910 { 2911 const struct rtw89_chip_info *chip = rtwdev->chip; 2912 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 2913 2914 if (!chip->support_ul_tb_ctrl) 2915 return; 2916 2917 ul_tb_info->dyn_tb_tri_en = true; 2918 ul_tb_info->def_if_bandedge = 2919 rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN); 2920 } 2921 2922 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) 2923 { 2924 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2925 int i; 2926 u8 th; 2927 2928 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 2929 th = rtw89_chip_get_thermal(rtwdev, i); 2930 if (th) 2931 ewma_thermal_add(&phystat->avg_thermal[i], th); 2932 2933 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 2934 "path(%d) thermal cur=%u avg=%ld", i, th, 2935 ewma_thermal_read(&phystat->avg_thermal[i])); 2936 } 2937 } 2938 2939 struct rtw89_phy_iter_rssi_data { 2940 struct rtw89_dev *rtwdev; 2941 struct rtw89_phy_ch_info *ch_info; 2942 bool rssi_changed; 2943 }; 2944 2945 static void rtw89_phy_stat_rssi_update_iter(void *data, 2946 struct ieee80211_sta *sta) 2947 { 2948 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2949 struct rtw89_phy_iter_rssi_data *rssi_data = 2950 (struct rtw89_phy_iter_rssi_data *)data; 2951 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info; 2952 unsigned long rssi_curr; 2953 2954 rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi); 2955 2956 if (rssi_curr < ch_info->rssi_min) { 2957 ch_info->rssi_min = rssi_curr; 2958 ch_info->rssi_min_macid = rtwsta->mac_id; 2959 } 2960 2961 if (rtwsta->prev_rssi == 0) { 2962 rtwsta->prev_rssi = rssi_curr; 2963 } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) { 2964 rtwsta->prev_rssi = rssi_curr; 2965 rssi_data->rssi_changed = true; 2966 } 2967 } 2968 2969 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) 2970 { 2971 struct rtw89_phy_iter_rssi_data rssi_data = {0}; 2972 2973 rssi_data.rtwdev = rtwdev; 2974 rssi_data.ch_info = &rtwdev->ch_info; 2975 rssi_data.ch_info->rssi_min = U8_MAX; 2976 ieee80211_iterate_stations_atomic(rtwdev->hw, 2977 rtw89_phy_stat_rssi_update_iter, 2978 &rssi_data); 2979 if (rssi_data.rssi_changed) 2980 rtw89_btc_ntfy_wl_sta(rtwdev); 2981 } 2982 2983 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) 2984 { 2985 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2986 int i; 2987 2988 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 2989 ewma_thermal_init(&phystat->avg_thermal[i]); 2990 2991 rtw89_phy_stat_thermal_update(rtwdev); 2992 2993 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 2994 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); 2995 } 2996 2997 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) 2998 { 2999 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 3000 3001 rtw89_phy_stat_thermal_update(rtwdev); 3002 rtw89_phy_stat_rssi_update(rtwdev); 3003 3004 phystat->last_pkt_stat = phystat->cur_pkt_stat; 3005 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 3006 } 3007 3008 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us) 3009 { 3010 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3011 3012 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 3013 } 3014 3015 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) 3016 { 3017 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3018 3019 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 3020 } 3021 3022 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) 3023 { 3024 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3025 3026 env->ccx_manual_ctrl = false; 3027 env->ccx_ongoing = false; 3028 env->ccx_rac_lv = RTW89_RAC_RELEASE; 3029 env->ccx_rpt_stamp = 0; 3030 env->ccx_period = 0; 3031 env->ccx_unit_idx = RTW89_CCX_32_US; 3032 env->ccx_trigger_time = 0; 3033 env->ccx_edcca_opt_bw_idx = RTW89_CCX_EDCCA_BW20_0; 3034 3035 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1); 3036 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1); 3037 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 3038 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EDCCA_OPT_MSK, 3039 RTW89_CCX_EDCCA_BW20_0); 3040 } 3041 3042 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report, 3043 u16 score) 3044 { 3045 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3046 u32 numer = 0; 3047 u16 ret = 0; 3048 3049 numer = report * score + (env->ccx_period >> 1); 3050 if (env->ccx_period) 3051 ret = numer / env->ccx_period; 3052 3053 return ret >= score ? score - 1 : ret; 3054 } 3055 3056 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, 3057 u16 time_ms, u32 *period, 3058 u32 *unit_idx) 3059 { 3060 u32 idx; 3061 u8 quotient; 3062 3063 if (time_ms >= CCX_MAX_PERIOD) 3064 time_ms = CCX_MAX_PERIOD; 3065 3066 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; 3067 3068 if (quotient < 4) 3069 idx = RTW89_CCX_4_US; 3070 else if (quotient < 8) 3071 idx = RTW89_CCX_8_US; 3072 else if (quotient < 16) 3073 idx = RTW89_CCX_16_US; 3074 else 3075 idx = RTW89_CCX_32_US; 3076 3077 *unit_idx = idx; 3078 *period = (time_ms * MS_TO_4US_RATIO) >> idx; 3079 3080 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3081 "[Trigger Time] period:%d, unit_idx:%d\n", 3082 *period, *unit_idx); 3083 } 3084 3085 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev) 3086 { 3087 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3088 3089 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3090 "lv:(%d)->(0)\n", env->ccx_rac_lv); 3091 3092 env->ccx_ongoing = false; 3093 env->ccx_rac_lv = RTW89_RAC_RELEASE; 3094 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3095 } 3096 3097 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, 3098 struct rtw89_ccx_para_info *para) 3099 { 3100 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3101 bool is_update = env->ifs_clm_app != para->ifs_clm_app; 3102 u8 i = 0; 3103 u16 *ifs_th_l = env->ifs_clm_th_l; 3104 u16 *ifs_th_h = env->ifs_clm_th_h; 3105 u32 ifs_th0_us = 0, ifs_th_times = 0; 3106 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; 3107 3108 if (!is_update) 3109 goto ifs_update_finished; 3110 3111 switch (para->ifs_clm_app) { 3112 case RTW89_IFS_CLM_INIT: 3113 case RTW89_IFS_CLM_BACKGROUND: 3114 case RTW89_IFS_CLM_ACS: 3115 case RTW89_IFS_CLM_DBG: 3116 case RTW89_IFS_CLM_DIG: 3117 case RTW89_IFS_CLM_TDMA_DIG: 3118 ifs_th0_us = IFS_CLM_TH0_UPPER; 3119 ifs_th_times = IFS_CLM_TH_MUL; 3120 break; 3121 case RTW89_IFS_CLM_DBG_MANUAL: 3122 ifs_th0_us = para->ifs_clm_manual_th0; 3123 ifs_th_times = para->ifs_clm_manual_th_times; 3124 break; 3125 default: 3126 break; 3127 } 3128 3129 /* Set sampling threshold for 4 different regions, unit in idx_cnt. 3130 * low[i] = high[i-1] + 1 3131 * high[i] = high[i-1] * ifs_th_times 3132 */ 3133 ifs_th_l[IFS_CLM_TH_START_IDX] = 0; 3134 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; 3135 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, 3136 ifs_th0_us); 3137 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { 3138 ifs_th_l[i] = ifs_th_h[i - 1] + 1; 3139 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; 3140 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]); 3141 } 3142 3143 ifs_update_finished: 3144 if (!is_update) 3145 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3146 "No need to update IFS_TH\n"); 3147 3148 return is_update; 3149 } 3150 3151 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) 3152 { 3153 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3154 u8 i = 0; 3155 3156 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_LOW_MSK, 3157 env->ifs_clm_th_l[0]); 3158 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_LOW_MSK, 3159 env->ifs_clm_th_l[1]); 3160 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_LOW_MSK, 3161 env->ifs_clm_th_l[2]); 3162 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_LOW_MSK, 3163 env->ifs_clm_th_l[3]); 3164 3165 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_HIGH_MSK, 3166 env->ifs_clm_th_h[0]); 3167 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_HIGH_MSK, 3168 env->ifs_clm_th_h[1]); 3169 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_HIGH_MSK, 3170 env->ifs_clm_th_h[2]); 3171 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_HIGH_MSK, 3172 env->ifs_clm_th_h[3]); 3173 3174 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3175 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3176 "Update IFS_T%d_th{low, high} : {%d, %d}\n", 3177 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 3178 } 3179 3180 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) 3181 { 3182 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3183 struct rtw89_ccx_para_info para = {0}; 3184 3185 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3186 env->ifs_clm_mntr_time = 0; 3187 3188 para.ifs_clm_app = RTW89_IFS_CLM_INIT; 3189 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) 3190 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 3191 3192 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COLLECT_EN, 3193 true); 3194 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_EN_MSK, true); 3195 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_EN_MSK, true); 3196 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_EN_MSK, true); 3197 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_EN_MSK, true); 3198 } 3199 3200 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, 3201 enum rtw89_env_racing_lv level) 3202 { 3203 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3204 int ret = 0; 3205 3206 if (level >= RTW89_RAC_MAX_NUM) { 3207 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3208 "[WARNING] Wrong LV=%d\n", level); 3209 return -EINVAL; 3210 } 3211 3212 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3213 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, 3214 env->ccx_rac_lv, level); 3215 3216 if (env->ccx_ongoing) { 3217 if (level <= env->ccx_rac_lv) 3218 ret = -EINVAL; 3219 else 3220 env->ccx_ongoing = false; 3221 } 3222 3223 if (ret == 0) 3224 env->ccx_rac_lv = level; 3225 3226 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", 3227 !ret); 3228 3229 return ret; 3230 } 3231 3232 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) 3233 { 3234 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3235 3236 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 0); 3237 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 0); 3238 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1); 3239 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 3240 3241 env->ccx_rpt_stamp++; 3242 env->ccx_ongoing = true; 3243 } 3244 3245 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) 3246 { 3247 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3248 u8 i = 0; 3249 u32 res = 0; 3250 3251 env->ifs_clm_tx_ratio = 3252 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT); 3253 env->ifs_clm_edcca_excl_cca_ratio = 3254 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca, 3255 PERCENT); 3256 env->ifs_clm_cck_fa_ratio = 3257 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT); 3258 env->ifs_clm_ofdm_fa_ratio = 3259 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT); 3260 env->ifs_clm_cck_cca_excl_fa_ratio = 3261 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa, 3262 PERCENT); 3263 env->ifs_clm_ofdm_cca_excl_fa_ratio = 3264 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa, 3265 PERCENT); 3266 env->ifs_clm_cck_fa_permil = 3267 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL); 3268 env->ifs_clm_ofdm_fa_permil = 3269 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL); 3270 3271 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { 3272 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { 3273 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; 3274 } else { 3275 env->ifs_clm_ifs_avg[i] = 3276 rtw89_phy_ccx_idx_to_us(rtwdev, 3277 env->ifs_clm_avg[i]); 3278 } 3279 3280 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]); 3281 res += env->ifs_clm_his[i] >> 1; 3282 if (env->ifs_clm_his[i]) 3283 res /= env->ifs_clm_his[i]; 3284 else 3285 res = 0; 3286 env->ifs_clm_cca_avg[i] = res; 3287 } 3288 3289 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3290 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", 3291 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); 3292 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3293 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", 3294 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); 3295 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3296 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", 3297 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); 3298 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3299 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", 3300 env->ifs_clm_cck_cca_excl_fa_ratio, 3301 env->ifs_clm_ofdm_cca_excl_fa_ratio); 3302 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3303 "Time:[his, ifs_avg(us), cca_avg(us)]\n"); 3304 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3305 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 3306 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 3307 env->ifs_clm_cca_avg[i]); 3308 } 3309 3310 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) 3311 { 3312 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3313 u8 i = 0; 3314 3315 if (rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_DONE_MSK) == 0) { 3316 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3317 "Get IFS_CLM report Fail\n"); 3318 return false; 3319 } 3320 3321 env->ifs_clm_tx = 3322 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 3323 B_IFS_CLM_TX_CNT_MSK); 3324 env->ifs_clm_edcca_excl_cca = 3325 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 3326 B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK); 3327 env->ifs_clm_cckcca_excl_fa = 3328 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 3329 B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK); 3330 env->ifs_clm_ofdmcca_excl_fa = 3331 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 3332 B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK); 3333 env->ifs_clm_cckfa = 3334 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 3335 B_IFS_CLM_CCK_FA_MSK); 3336 env->ifs_clm_ofdmfa = 3337 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 3338 B_IFS_CLM_OFDM_FA_MSK); 3339 3340 env->ifs_clm_his[0] = 3341 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T1_HIS_MSK); 3342 env->ifs_clm_his[1] = 3343 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T2_HIS_MSK); 3344 env->ifs_clm_his[2] = 3345 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T3_HIS_MSK); 3346 env->ifs_clm_his[3] = 3347 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T4_HIS_MSK); 3348 3349 env->ifs_clm_avg[0] = 3350 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T1_AVG_MSK); 3351 env->ifs_clm_avg[1] = 3352 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T2_AVG_MSK); 3353 env->ifs_clm_avg[2] = 3354 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T3_AVG_MSK); 3355 env->ifs_clm_avg[3] = 3356 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T4_AVG_MSK); 3357 3358 env->ifs_clm_cca[0] = 3359 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T1_CCA_MSK); 3360 env->ifs_clm_cca[1] = 3361 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T2_CCA_MSK); 3362 env->ifs_clm_cca[2] = 3363 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T3_CCA_MSK); 3364 env->ifs_clm_cca[3] = 3365 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T4_CCA_MSK); 3366 3367 env->ifs_clm_total_ifs = 3368 rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_TOTAL_CNT_MSK); 3369 3370 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", 3371 env->ifs_clm_total_ifs); 3372 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3373 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", 3374 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); 3375 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3376 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", 3377 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); 3378 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3379 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", 3380 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); 3381 3382 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); 3383 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3384 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3385 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], 3386 env->ifs_clm_avg[i], env->ifs_clm_cca[i]); 3387 3388 rtw89_phy_ifs_clm_get_utility(rtwdev); 3389 3390 return true; 3391 } 3392 3393 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 3394 struct rtw89_ccx_para_info *para) 3395 { 3396 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3397 u32 period = 0; 3398 u32 unit_idx = 0; 3399 3400 if (para->mntr_time == 0) { 3401 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3402 "[WARN] MNTR_TIME is 0\n"); 3403 return -EINVAL; 3404 } 3405 3406 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv)) 3407 return -EINVAL; 3408 3409 if (para->mntr_time != env->ifs_clm_mntr_time) { 3410 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 3411 &period, &unit_idx); 3412 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 3413 B_IFS_CLM_PERIOD_MSK, period); 3414 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 3415 B_IFS_CLM_COUNTER_UNIT_MSK, unit_idx); 3416 3417 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3418 "Update IFS-CLM time ((%d)) -> ((%d))\n", 3419 env->ifs_clm_mntr_time, para->mntr_time); 3420 3421 env->ifs_clm_mntr_time = para->mntr_time; 3422 env->ccx_period = (u16)period; 3423 env->ccx_unit_idx = (u8)unit_idx; 3424 } 3425 3426 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) { 3427 env->ifs_clm_app = para->ifs_clm_app; 3428 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 3429 } 3430 3431 return 0; 3432 } 3433 3434 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) 3435 { 3436 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3437 struct rtw89_ccx_para_info para = {0}; 3438 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3439 3440 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3441 if (env->ccx_manual_ctrl) { 3442 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3443 "CCX in manual ctrl\n"); 3444 return; 3445 } 3446 3447 /* only ifs_clm for now */ 3448 if (rtw89_phy_ifs_clm_get_result(rtwdev)) 3449 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3450 3451 rtw89_phy_ccx_racing_release(rtwdev); 3452 para.mntr_time = 1900; 3453 para.rac_lv = RTW89_RAC_LV_1; 3454 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3455 3456 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0) 3457 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3458 if (chk_result) 3459 rtw89_phy_ccx_trigger(rtwdev); 3460 3461 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3462 "get_result=0x%x, chk_result:0x%x\n", 3463 env->ccx_watchdog_result, chk_result); 3464 } 3465 3466 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page) 3467 { 3468 if (*ie_page >= RTW89_PHYSTS_BITMAP_NUM || 3469 *ie_page == RTW89_RSVD_9) 3470 return false; 3471 else if (*ie_page > RTW89_RSVD_9) 3472 *ie_page -= 1; 3473 3474 return true; 3475 } 3476 3477 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) 3478 { 3479 static const u8 ie_page_shift = 2; 3480 3481 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); 3482 } 3483 3484 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, 3485 enum rtw89_phy_status_bitmap ie_page) 3486 { 3487 u32 addr; 3488 3489 if (!rtw89_physts_ie_page_valid(&ie_page)) 3490 return 0; 3491 3492 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3493 3494 return rtw89_phy_read32(rtwdev, addr); 3495 } 3496 3497 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, 3498 enum rtw89_phy_status_bitmap ie_page, 3499 u32 val) 3500 { 3501 const struct rtw89_chip_info *chip = rtwdev->chip; 3502 u32 addr; 3503 3504 if (!rtw89_physts_ie_page_valid(&ie_page)) 3505 return; 3506 3507 if (chip->chip_id == RTL8852A) 3508 val &= B_PHY_STS_BITMAP_MSK_52A; 3509 3510 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3511 rtw89_phy_write32(rtwdev, addr, val); 3512 } 3513 3514 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev, 3515 enum rtw89_phy_status_bitmap bitmap, 3516 enum rtw89_phy_status_ie_type ie, 3517 bool enable) 3518 { 3519 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap); 3520 3521 if (enable) 3522 val |= BIT(ie); 3523 else 3524 val &= ~BIT(ie); 3525 3526 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val); 3527 } 3528 3529 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, 3530 bool enable, 3531 enum rtw89_phy_idx phy_idx) 3532 { 3533 if (enable) { 3534 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3535 B_STS_DIS_TRIG_BY_FAIL); 3536 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3537 B_STS_DIS_TRIG_BY_BRK); 3538 } else { 3539 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3540 B_STS_DIS_TRIG_BY_FAIL); 3541 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3542 B_STS_DIS_TRIG_BY_BRK); 3543 } 3544 } 3545 3546 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev) 3547 { 3548 u8 i; 3549 3550 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0); 3551 3552 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { 3553 if (i >= RTW89_CCK_PKT) 3554 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3555 RTW89_PHYSTS_IE09_FTR_0, 3556 true); 3557 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) || 3558 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT)) 3559 continue; 3560 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3561 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A, 3562 true); 3563 } 3564 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT, 3565 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3566 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT, 3567 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3568 3569 /* force IE01 for channel index, only channel field is valid */ 3570 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT, 3571 RTW89_PHYSTS_IE01_CMN_OFDM, true); 3572 } 3573 3574 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) 3575 { 3576 const struct rtw89_chip_info *chip = rtwdev->chip; 3577 struct rtw89_dig_info *dig = &rtwdev->dig; 3578 const struct rtw89_phy_dig_gain_cfg *cfg; 3579 const char *msg; 3580 u8 i; 3581 s8 gain_base; 3582 s8 *gain_arr; 3583 u32 tmp; 3584 3585 switch (type) { 3586 case RTW89_DIG_GAIN_LNA_G: 3587 gain_arr = dig->lna_gain_g; 3588 gain_base = LNA0_GAIN; 3589 cfg = chip->dig_table->cfg_lna_g; 3590 msg = "lna_gain_g"; 3591 break; 3592 case RTW89_DIG_GAIN_TIA_G: 3593 gain_arr = dig->tia_gain_g; 3594 gain_base = TIA0_GAIN_G; 3595 cfg = chip->dig_table->cfg_tia_g; 3596 msg = "tia_gain_g"; 3597 break; 3598 case RTW89_DIG_GAIN_LNA_A: 3599 gain_arr = dig->lna_gain_a; 3600 gain_base = LNA0_GAIN; 3601 cfg = chip->dig_table->cfg_lna_a; 3602 msg = "lna_gain_a"; 3603 break; 3604 case RTW89_DIG_GAIN_TIA_A: 3605 gain_arr = dig->tia_gain_a; 3606 gain_base = TIA0_GAIN_A; 3607 cfg = chip->dig_table->cfg_tia_a; 3608 msg = "tia_gain_a"; 3609 break; 3610 default: 3611 return; 3612 } 3613 3614 for (i = 0; i < cfg->size; i++) { 3615 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr, 3616 cfg->table[i].mask); 3617 tmp >>= DIG_GAIN_SHIFT; 3618 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; 3619 gain_base += DIG_GAIN; 3620 3621 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", 3622 msg, i, gain_arr[i]); 3623 } 3624 } 3625 3626 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev) 3627 { 3628 struct rtw89_dig_info *dig = &rtwdev->dig; 3629 u32 tmp; 3630 u8 i; 3631 3632 if (!rtwdev->hal.support_igi) 3633 return; 3634 3635 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW, 3636 B_PATH0_IB_PKPW_MSK); 3637 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); 3638 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK, 3639 B_PATH0_IB_PBK_MSK); 3640 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", 3641 dig->ib_pkpwr, dig->ib_pbk); 3642 3643 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) 3644 rtw89_phy_dig_read_gain_table(rtwdev, i); 3645 } 3646 3647 static const u8 rssi_nolink = 22; 3648 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; 3649 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; 3650 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; 3651 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; 3652 3653 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev) 3654 { 3655 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 3656 struct rtw89_dig_info *dig = &rtwdev->dig; 3657 bool is_linked = rtwdev->total_sta_assoc > 0; 3658 3659 if (is_linked) { 3660 dig->igi_rssi = ch_info->rssi_min >> 1; 3661 } else { 3662 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); 3663 dig->igi_rssi = rssi_nolink; 3664 } 3665 } 3666 3667 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev) 3668 { 3669 struct rtw89_dig_info *dig = &rtwdev->dig; 3670 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3671 bool is_linked = rtwdev->total_sta_assoc > 0; 3672 const u16 *fa_th_src = NULL; 3673 3674 switch (chan->band_type) { 3675 case RTW89_BAND_2G: 3676 dig->lna_gain = dig->lna_gain_g; 3677 dig->tia_gain = dig->tia_gain_g; 3678 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; 3679 dig->force_gaincode_idx_en = false; 3680 dig->dyn_pd_th_en = true; 3681 break; 3682 case RTW89_BAND_5G: 3683 default: 3684 dig->lna_gain = dig->lna_gain_a; 3685 dig->tia_gain = dig->tia_gain_a; 3686 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; 3687 dig->force_gaincode_idx_en = true; 3688 dig->dyn_pd_th_en = true; 3689 break; 3690 } 3691 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); 3692 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); 3693 } 3694 3695 static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20; 3696 static const u8 igi_max_performance_mode = 0x5a; 3697 static const u8 dynamic_pd_threshold_max; 3698 3699 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev) 3700 { 3701 struct rtw89_dig_info *dig = &rtwdev->dig; 3702 3703 dig->cur_gaincode.lna_idx = LNA_IDX_MAX; 3704 dig->cur_gaincode.tia_idx = TIA_IDX_MAX; 3705 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; 3706 dig->force_gaincode.lna_idx = LNA_IDX_MAX; 3707 dig->force_gaincode.tia_idx = TIA_IDX_MAX; 3708 dig->force_gaincode.rxb_idx = RXB_IDX_MAX; 3709 3710 dig->dyn_igi_max = igi_max_performance_mode; 3711 dig->dyn_igi_min = dynamic_igi_min; 3712 dig->dyn_pd_th_max = dynamic_pd_threshold_max; 3713 dig->pd_low_th_ofst = pd_low_th_offset; 3714 dig->is_linked_pre = false; 3715 } 3716 3717 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) 3718 { 3719 rtw89_phy_dig_update_gain_para(rtwdev); 3720 rtw89_phy_dig_reset(rtwdev); 3721 } 3722 3723 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3724 { 3725 struct rtw89_dig_info *dig = &rtwdev->dig; 3726 u8 lna_idx; 3727 3728 if (rssi < dig->igi_rssi_th[0]) 3729 lna_idx = RTW89_DIG_GAIN_LNA_IDX6; 3730 else if (rssi < dig->igi_rssi_th[1]) 3731 lna_idx = RTW89_DIG_GAIN_LNA_IDX5; 3732 else if (rssi < dig->igi_rssi_th[2]) 3733 lna_idx = RTW89_DIG_GAIN_LNA_IDX4; 3734 else if (rssi < dig->igi_rssi_th[3]) 3735 lna_idx = RTW89_DIG_GAIN_LNA_IDX3; 3736 else if (rssi < dig->igi_rssi_th[4]) 3737 lna_idx = RTW89_DIG_GAIN_LNA_IDX2; 3738 else 3739 lna_idx = RTW89_DIG_GAIN_LNA_IDX1; 3740 3741 return lna_idx; 3742 } 3743 3744 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3745 { 3746 struct rtw89_dig_info *dig = &rtwdev->dig; 3747 u8 tia_idx; 3748 3749 if (rssi < dig->igi_rssi_th[0]) 3750 tia_idx = RTW89_DIG_GAIN_TIA_IDX1; 3751 else 3752 tia_idx = RTW89_DIG_GAIN_TIA_IDX0; 3753 3754 return tia_idx; 3755 } 3756 3757 #define IB_PBK_BASE 110 3758 #define WB_RSSI_BASE 10 3759 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3760 struct rtw89_agc_gaincode_set *set) 3761 { 3762 struct rtw89_dig_info *dig = &rtwdev->dig; 3763 s8 lna_gain = dig->lna_gain[set->lna_idx]; 3764 s8 tia_gain = dig->tia_gain[set->tia_idx]; 3765 s32 wb_rssi = rssi + lna_gain + tia_gain; 3766 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; 3767 u8 rxb_idx; 3768 3769 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; 3770 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); 3771 3772 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", 3773 wb_rssi, rxb_idx_tmp); 3774 3775 return rxb_idx; 3776 } 3777 3778 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3779 struct rtw89_agc_gaincode_set *set) 3780 { 3781 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi); 3782 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi); 3783 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set); 3784 3785 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3786 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", 3787 rssi, set->lna_idx, set->tia_idx, set->rxb_idx); 3788 } 3789 3790 #define IGI_OFFSET_MAX 25 3791 #define IGI_OFFSET_MUL 2 3792 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev) 3793 { 3794 struct rtw89_dig_info *dig = &rtwdev->dig; 3795 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3796 enum rtw89_dig_noisy_level noisy_lv; 3797 u8 igi_offset = dig->fa_rssi_ofst; 3798 u16 fa_ratio = 0; 3799 3800 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; 3801 3802 if (fa_ratio < dig->fa_th[0]) 3803 noisy_lv = RTW89_DIG_NOISY_LEVEL0; 3804 else if (fa_ratio < dig->fa_th[1]) 3805 noisy_lv = RTW89_DIG_NOISY_LEVEL1; 3806 else if (fa_ratio < dig->fa_th[2]) 3807 noisy_lv = RTW89_DIG_NOISY_LEVEL2; 3808 else if (fa_ratio < dig->fa_th[3]) 3809 noisy_lv = RTW89_DIG_NOISY_LEVEL3; 3810 else 3811 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; 3812 3813 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) 3814 igi_offset = 0; 3815 else 3816 igi_offset += noisy_lv * IGI_OFFSET_MUL; 3817 3818 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); 3819 dig->fa_rssi_ofst = igi_offset; 3820 3821 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3822 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", 3823 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); 3824 3825 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3826 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", 3827 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, 3828 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, 3829 noisy_lv, igi_offset); 3830 } 3831 3832 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx) 3833 { 3834 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3835 3836 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_lna_init.addr, 3837 dig_regs->p0_lna_init.mask, lna_idx); 3838 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_lna_init.addr, 3839 dig_regs->p1_lna_init.mask, lna_idx); 3840 } 3841 3842 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx) 3843 { 3844 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3845 3846 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_tia_init.addr, 3847 dig_regs->p0_tia_init.mask, tia_idx); 3848 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_tia_init.addr, 3849 dig_regs->p1_tia_init.mask, tia_idx); 3850 } 3851 3852 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx) 3853 { 3854 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3855 3856 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_rxb_init.addr, 3857 dig_regs->p0_rxb_init.mask, rxb_idx); 3858 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_rxb_init.addr, 3859 dig_regs->p1_rxb_init.mask, rxb_idx); 3860 } 3861 3862 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, 3863 const struct rtw89_agc_gaincode_set set) 3864 { 3865 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx); 3866 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx); 3867 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx); 3868 3869 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", 3870 set.lna_idx, set.tia_idx, set.rxb_idx); 3871 } 3872 3873 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, 3874 bool enable) 3875 { 3876 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3877 3878 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_p20_pagcugc_en.addr, 3879 dig_regs->p0_p20_pagcugc_en.mask, enable); 3880 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_s20_pagcugc_en.addr, 3881 dig_regs->p0_s20_pagcugc_en.mask, enable); 3882 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_p20_pagcugc_en.addr, 3883 dig_regs->p1_p20_pagcugc_en.mask, enable); 3884 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_s20_pagcugc_en.addr, 3885 dig_regs->p1_s20_pagcugc_en.mask, enable); 3886 3887 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); 3888 } 3889 3890 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev) 3891 { 3892 struct rtw89_dig_info *dig = &rtwdev->dig; 3893 3894 if (!rtwdev->hal.support_igi) 3895 return; 3896 3897 if (dig->force_gaincode_idx_en) { 3898 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 3899 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3900 "Force gaincode index enabled.\n"); 3901 } else { 3902 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi, 3903 &dig->cur_gaincode); 3904 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode); 3905 } 3906 } 3907 3908 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, 3909 bool enable) 3910 { 3911 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3912 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 3913 enum rtw89_bandwidth cbw = chan->band_width; 3914 struct rtw89_dig_info *dig = &rtwdev->dig; 3915 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; 3916 u8 ofdm_cca_th; 3917 s8 cck_cca_th; 3918 u32 pd_val = 0; 3919 3920 under_region += PD_TH_SB_FLTR_CMP_VAL; 3921 3922 switch (cbw) { 3923 case RTW89_CHANNEL_WIDTH_40: 3924 under_region += PD_TH_BW40_CMP_VAL; 3925 break; 3926 case RTW89_CHANNEL_WIDTH_80: 3927 under_region += PD_TH_BW80_CMP_VAL; 3928 break; 3929 case RTW89_CHANNEL_WIDTH_160: 3930 under_region += PD_TH_BW160_CMP_VAL; 3931 break; 3932 case RTW89_CHANNEL_WIDTH_20: 3933 fallthrough; 3934 default: 3935 under_region += PD_TH_BW20_CMP_VAL; 3936 break; 3937 } 3938 3939 dig->dyn_pd_th_max = dig->igi_rssi; 3940 3941 final_rssi = min_t(u8, rssi, dig->igi_rssi); 3942 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, 3943 PD_TH_MAX_RSSI + under_region); 3944 3945 if (enable) { 3946 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1; 3947 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3948 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n", 3949 final_rssi, ofdm_cca_th, under_region, pd_val); 3950 } else { 3951 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3952 "Dynamic PD th disabled, Set PD_low_bd=0\n"); 3953 } 3954 3955 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 3956 dig_regs->pd_lower_bound_mask, pd_val); 3957 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 3958 dig_regs->pd_spatial_reuse_en, enable); 3959 3960 if (!rtwdev->hal.support_cckpd) 3961 return; 3962 3963 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI); 3964 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX); 3965 3966 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3967 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n", 3968 final_rssi, cck_cca_th, under_region, pd_val); 3969 3970 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_EN_V1, 3971 B_BMODE_PDTH_LIMIT_EN_MSK_V1, enable); 3972 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_V1, 3973 B_BMODE_PDTH_LOWER_BOUND_MSK_V1, pd_val); 3974 } 3975 3976 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) 3977 { 3978 struct rtw89_dig_info *dig = &rtwdev->dig; 3979 3980 dig->bypass_dig = false; 3981 rtw89_phy_dig_para_reset(rtwdev); 3982 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 3983 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false); 3984 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 3985 rtw89_phy_dig_update_para(rtwdev); 3986 } 3987 3988 #define IGI_RSSI_MIN 10 3989 void rtw89_phy_dig(struct rtw89_dev *rtwdev) 3990 { 3991 struct rtw89_dig_info *dig = &rtwdev->dig; 3992 bool is_linked = rtwdev->total_sta_assoc > 0; 3993 3994 if (unlikely(dig->bypass_dig)) { 3995 dig->bypass_dig = false; 3996 return; 3997 } 3998 3999 if (!dig->is_linked_pre && is_linked) { 4000 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); 4001 rtw89_phy_dig_update_para(rtwdev); 4002 } else if (dig->is_linked_pre && !is_linked) { 4003 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); 4004 rtw89_phy_dig_update_para(rtwdev); 4005 } 4006 dig->is_linked_pre = is_linked; 4007 4008 rtw89_phy_dig_igi_offset_by_env(rtwdev); 4009 rtw89_phy_dig_update_rssi_info(rtwdev); 4010 4011 dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ? 4012 dig->igi_rssi - IGI_RSSI_MIN : 0; 4013 dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX; 4014 dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst; 4015 4016 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, 4017 dig->dyn_igi_max); 4018 4019 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4020 "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n", 4021 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, 4022 dig->igi_fa_rssi); 4023 4024 rtw89_phy_dig_config_igi(rtwdev); 4025 4026 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en); 4027 4028 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) 4029 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true); 4030 else 4031 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 4032 } 4033 4034 static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta) 4035 { 4036 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 4037 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 4038 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 4039 struct rtw89_hal *hal = &rtwdev->hal; 4040 bool *done = data; 4041 u8 rssi_a, rssi_b; 4042 u32 candidate; 4043 4044 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || sta->tdls) 4045 return; 4046 4047 if (*done) 4048 return; 4049 4050 *done = true; 4051 4052 rssi_a = ewma_rssi_read(&rtwsta->rssi[RF_PATH_A]); 4053 rssi_b = ewma_rssi_read(&rtwsta->rssi[RF_PATH_B]); 4054 4055 if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH) 4056 candidate = RF_A; 4057 else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH) 4058 candidate = RF_B; 4059 else 4060 return; 4061 4062 if (hal->antenna_tx == candidate) 4063 return; 4064 4065 hal->antenna_tx = candidate; 4066 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta); 4067 4068 if (hal->antenna_tx == RF_A) { 4069 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12); 4070 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11); 4071 } else if (hal->antenna_tx == RF_B) { 4072 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11); 4073 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12); 4074 } 4075 } 4076 4077 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev) 4078 { 4079 struct rtw89_hal *hal = &rtwdev->hal; 4080 bool done = false; 4081 4082 if (!hal->tx_path_diversity) 4083 return; 4084 4085 ieee80211_iterate_stations_atomic(rtwdev->hw, 4086 rtw89_phy_tx_path_div_sta_iter, 4087 &done); 4088 } 4089 4090 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) 4091 { 4092 rtw89_phy_ccx_top_setting_init(rtwdev); 4093 rtw89_phy_ifs_clm_setting_init(rtwdev); 4094 } 4095 4096 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 4097 { 4098 const struct rtw89_chip_info *chip = rtwdev->chip; 4099 4100 rtw89_phy_stat_init(rtwdev); 4101 4102 rtw89_chip_bb_sethw(rtwdev); 4103 4104 rtw89_phy_env_monitor_init(rtwdev); 4105 rtw89_physts_parsing_init(rtwdev); 4106 rtw89_phy_dig_init(rtwdev); 4107 rtw89_phy_cfo_init(rtwdev); 4108 rtw89_phy_ul_tb_info_init(rtwdev); 4109 4110 rtw89_phy_init_rf_nctl(rtwdev); 4111 rtw89_chip_rfk_init(rtwdev); 4112 rtw89_load_txpwr_table(rtwdev, chip->byr_table); 4113 rtw89_chip_set_txpwr_ctrl(rtwdev); 4114 rtw89_chip_power_trim(rtwdev); 4115 rtw89_chip_cfg_txrx_path(rtwdev); 4116 } 4117 4118 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 4119 { 4120 const struct rtw89_chip_info *chip = rtwdev->chip; 4121 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 4122 u8 bss_color; 4123 4124 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 4125 return; 4126 4127 bss_color = vif->bss_conf.he_bss_color.color; 4128 4129 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_VLD0, 0x1, 4130 phy_idx); 4131 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT, 4132 bss_color, phy_idx); 4133 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID, 4134 vif->cfg.aid, phy_idx); 4135 } 4136 4137 static void 4138 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4139 { 4140 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); 4141 } 4142 4143 static void 4144 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4145 { 4146 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 4147 } 4148 4149 static void 4150 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4151 { 4152 rtw89_phy_write32_set(rtwdev, def->addr, def->mask); 4153 } 4154 4155 static void 4156 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4157 { 4158 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); 4159 } 4160 4161 static void 4162 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4163 { 4164 udelay(def->data); 4165 } 4166 4167 static void 4168 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { 4169 [RTW89_RFK_F_WRF] = _rfk_write_rf, 4170 [RTW89_RFK_F_WM] = _rfk_write32_mask, 4171 [RTW89_RFK_F_WS] = _rfk_write32_set, 4172 [RTW89_RFK_F_WC] = _rfk_write32_clr, 4173 [RTW89_RFK_F_DELAY] = _rfk_delay, 4174 }; 4175 4176 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 4177 4178 void 4179 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) 4180 { 4181 const struct rtw89_reg5_def *p = tbl->defs; 4182 const struct rtw89_reg5_def *end = tbl->defs + tbl->size; 4183 4184 for (; p < end; p++) 4185 _rfk_handler[p->flag](rtwdev, p); 4186 } 4187 EXPORT_SYMBOL(rtw89_rfk_parser); 4188 4189 #define RTW89_TSSI_FAST_MODE_NUM 4 4190 4191 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = { 4192 {0xD934, 0xff0000}, 4193 {0xD934, 0xff000000}, 4194 {0xD938, 0xff}, 4195 {0xD934, 0xff00}, 4196 }; 4197 4198 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = { 4199 {0xD930, 0xff0000}, 4200 {0xD930, 0xff000000}, 4201 {0xD934, 0xff}, 4202 {0xD930, 0xff00}, 4203 }; 4204 4205 static 4206 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev, 4207 enum rtw89_mac_idx mac_idx, 4208 enum rtw89_tssi_bandedge_cfg bandedge_cfg, 4209 u32 val) 4210 { 4211 const struct rtw89_reg_def *regs; 4212 u32 reg; 4213 int i; 4214 4215 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 4216 regs = rtw89_tssi_fastmode_regs_flat; 4217 else 4218 regs = rtw89_tssi_fastmode_regs_level; 4219 4220 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) { 4221 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 4222 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); 4223 } 4224 } 4225 4226 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = { 4227 {0xD91C, 0xff000000}, 4228 {0xD920, 0xff}, 4229 {0xD920, 0xff00}, 4230 {0xD920, 0xff0000}, 4231 {0xD920, 0xff000000}, 4232 {0xD924, 0xff}, 4233 {0xD924, 0xff00}, 4234 {0xD914, 0xff000000}, 4235 {0xD918, 0xff}, 4236 {0xD918, 0xff00}, 4237 {0xD918, 0xff0000}, 4238 {0xD918, 0xff000000}, 4239 {0xD91C, 0xff}, 4240 {0xD91C, 0xff00}, 4241 {0xD91C, 0xff0000}, 4242 }; 4243 4244 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = { 4245 {0xD910, 0xff}, 4246 {0xD910, 0xff00}, 4247 {0xD910, 0xff0000}, 4248 {0xD910, 0xff000000}, 4249 {0xD914, 0xff}, 4250 {0xD914, 0xff00}, 4251 {0xD914, 0xff0000}, 4252 {0xD908, 0xff}, 4253 {0xD908, 0xff00}, 4254 {0xD908, 0xff0000}, 4255 {0xD908, 0xff000000}, 4256 {0xD90C, 0xff}, 4257 {0xD90C, 0xff00}, 4258 {0xD90C, 0xff0000}, 4259 {0xD90C, 0xff000000}, 4260 }; 4261 4262 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 4263 enum rtw89_mac_idx mac_idx, 4264 enum rtw89_tssi_bandedge_cfg bandedge_cfg) 4265 { 4266 const struct rtw89_chip_info *chip = rtwdev->chip; 4267 const struct rtw89_reg_def *regs; 4268 const u32 *data; 4269 u32 reg; 4270 int i; 4271 4272 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM) 4273 return; 4274 4275 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 4276 regs = rtw89_tssi_bandedge_regs_flat; 4277 else 4278 regs = rtw89_tssi_bandedge_regs_level; 4279 4280 data = chip->tssi_dbw_table->data[bandedge_cfg]; 4281 4282 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) { 4283 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 4284 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); 4285 } 4286 4287 reg = rtw89_mac_reg_by_idx(R_AX_BANDEDGE_CFG, mac_idx); 4288 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); 4289 4290 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg, 4291 data[RTW89_TSSI_SBW20]); 4292 } 4293 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg); 4294