1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "debug.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "ps.h" 10 #include "reg.h" 11 #include "sar.h" 12 #include "coex.h" 13 14 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, 15 const struct rtw89_ra_report *report) 16 { 17 u32 bit_rate = report->bit_rate; 18 19 /* lower than ofdm, do not aggregate */ 20 if (bit_rate < 550) 21 return 1; 22 23 /* avoid AMSDU for legacy rate */ 24 if (report->might_fallback_legacy) 25 return 1; 26 27 /* lower than 20M vht 2ss mcs8, make it small */ 28 if (bit_rate < 1800) 29 return 1200; 30 31 /* lower than 40M vht 2ss mcs9, make it medium */ 32 if (bit_rate < 4000) 33 return 2600; 34 35 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ 36 if (bit_rate < 7000) 37 return 3500; 38 39 return rtwdev->chip->max_amsdu_limit; 40 } 41 42 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) 43 { 44 u64 ra_mask = 0; 45 u8 mcs_cap; 46 int i, nss; 47 48 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { 49 mcs_cap = mcs_map & 0x3; 50 switch (mcs_cap) { 51 case 2: 52 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; 53 break; 54 case 1: 55 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; 56 break; 57 case 0: 58 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; 59 break; 60 default: 61 break; 62 } 63 } 64 65 return ra_mask; 66 } 67 68 static u64 get_he_ra_mask(struct ieee80211_sta *sta) 69 { 70 struct ieee80211_sta_he_cap cap = sta->deflink.he_cap; 71 u16 mcs_map; 72 73 switch (sta->deflink.bandwidth) { 74 case IEEE80211_STA_RX_BW_160: 75 if (cap.he_cap_elem.phy_cap_info[0] & 76 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) 77 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); 78 else 79 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); 80 break; 81 default: 82 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); 83 } 84 85 /* MCS11, MCS9, MCS7 */ 86 return get_mcs_ra_mask(mcs_map, 11, 2); 87 } 88 89 #define RA_FLOOR_TABLE_SIZE 7 90 #define RA_FLOOR_UP_GAP 3 91 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, 92 u8 ratr_state) 93 { 94 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; 95 u8 rssi_lv = 0; 96 u8 i; 97 98 rssi >>= 1; 99 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 100 if (i >= ratr_state) 101 rssi_lv_t[i] += RA_FLOOR_UP_GAP; 102 if (rssi < rssi_lv_t[i]) { 103 rssi_lv = i; 104 break; 105 } 106 } 107 if (rssi_lv == 0) 108 return 0xffffffffffffffffULL; 109 else if (rssi_lv == 1) 110 return 0xfffffffffffffff0ULL; 111 else if (rssi_lv == 2) 112 return 0xffffffffffffefe0ULL; 113 else if (rssi_lv == 3) 114 return 0xffffffffffffcfc0ULL; 115 else if (rssi_lv == 4) 116 return 0xffffffffffff8f80ULL; 117 else if (rssi_lv >= 5) 118 return 0xffffffffffff0f00ULL; 119 120 return 0xffffffffffffffffULL; 121 } 122 123 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak) 124 { 125 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 126 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 127 128 if (ra_mask == 0) 129 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 130 131 return ra_mask; 132 } 133 134 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 135 { 136 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 137 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 138 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 139 enum nl80211_band band; 140 u64 cfg_mask; 141 142 if (!rtwsta->use_cfg_mask) 143 return -1; 144 145 switch (chan->band_type) { 146 case RTW89_BAND_2G: 147 band = NL80211_BAND_2GHZ; 148 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, 149 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); 150 break; 151 case RTW89_BAND_5G: 152 band = NL80211_BAND_5GHZ; 153 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, 154 RA_MASK_OFDM_RATES); 155 break; 156 case RTW89_BAND_6G: 157 band = NL80211_BAND_6GHZ; 158 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy, 159 RA_MASK_OFDM_RATES); 160 break; 161 default: 162 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type); 163 return -1; 164 } 165 166 if (sta->deflink.he_cap.has_he) { 167 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], 168 RA_MASK_HE_1SS_RATES); 169 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], 170 RA_MASK_HE_2SS_RATES); 171 } else if (sta->deflink.vht_cap.vht_supported) { 172 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 173 RA_MASK_VHT_1SS_RATES); 174 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 175 RA_MASK_VHT_2SS_RATES); 176 } else if (sta->deflink.ht_cap.ht_supported) { 177 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 178 RA_MASK_HT_1SS_RATES); 179 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 180 RA_MASK_HT_2SS_RATES); 181 } 182 183 return cfg_mask; 184 } 185 186 static const u64 187 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, 188 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; 189 static const u64 190 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 191 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; 192 static const u64 193 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, 194 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; 195 196 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 197 struct ieee80211_sta *sta, bool csi) 198 { 199 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 200 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 201 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 202 struct rtw89_ra_info *ra = &rtwsta->ra; 203 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 204 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; 205 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 206 u64 ra_mask = 0; 207 u64 ra_mask_bak; 208 u8 mode = 0; 209 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; 210 u8 bw_mode = 0; 211 u8 stbc_en = 0; 212 u8 ldpc_en = 0; 213 u8 i; 214 bool sgi = false; 215 216 memset(ra, 0, sizeof(*ra)); 217 /* Set the ra mask from sta's capability */ 218 if (sta->deflink.he_cap.has_he) { 219 mode |= RTW89_RA_MODE_HE; 220 csi_mode = RTW89_RA_RPT_MODE_HE; 221 ra_mask |= get_he_ra_mask(sta); 222 high_rate_masks = rtw89_ra_mask_he_rates; 223 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[2] & 224 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) 225 stbc_en = 1; 226 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[1] & 227 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) 228 ldpc_en = 1; 229 } else if (sta->deflink.vht_cap.vht_supported) { 230 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 231 232 mode |= RTW89_RA_MODE_VHT; 233 csi_mode = RTW89_RA_RPT_MODE_VHT; 234 /* MCS9, MCS8, MCS7 */ 235 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); 236 high_rate_masks = rtw89_ra_mask_vht_rates; 237 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 238 stbc_en = 1; 239 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 240 ldpc_en = 1; 241 } else if (sta->deflink.ht_cap.ht_supported) { 242 mode |= RTW89_RA_MODE_HT; 243 csi_mode = RTW89_RA_RPT_MODE_HT; 244 ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 48) | 245 ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 36) | 246 (sta->deflink.ht_cap.mcs.rx_mask[1] << 24) | 247 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 248 high_rate_masks = rtw89_ra_mask_ht_rates; 249 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 250 stbc_en = 1; 251 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 252 ldpc_en = 1; 253 } 254 255 switch (chan->band_type) { 256 case RTW89_BAND_2G: 257 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 258 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] <= 0xf) 259 mode |= RTW89_RA_MODE_CCK; 260 else 261 mode |= RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM; 262 break; 263 case RTW89_BAND_5G: 264 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 265 mode |= RTW89_RA_MODE_OFDM; 266 break; 267 case RTW89_BAND_6G: 268 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_6GHZ] << 4; 269 mode |= RTW89_RA_MODE_OFDM; 270 break; 271 default: 272 rtw89_err(rtwdev, "Unknown band type\n"); 273 break; 274 } 275 276 ra_mask_bak = ra_mask; 277 278 if (mode >= RTW89_RA_MODE_HT) { 279 u64 mask = 0; 280 for (i = 0; i < rtwdev->hal.tx_nss; i++) 281 mask |= high_rate_masks[i]; 282 if (mode & RTW89_RA_MODE_OFDM) 283 mask |= RA_MASK_SUBOFDM_RATES; 284 if (mode & RTW89_RA_MODE_CCK) 285 mask |= RA_MASK_SUBCCK_RATES; 286 ra_mask &= mask; 287 } else if (mode & RTW89_RA_MODE_OFDM) { 288 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES); 289 } 290 291 if (mode != RTW89_RA_MODE_CCK) 292 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); 293 294 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak); 295 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 296 297 switch (sta->deflink.bandwidth) { 298 case IEEE80211_STA_RX_BW_160: 299 bw_mode = RTW89_CHANNEL_WIDTH_160; 300 sgi = sta->deflink.vht_cap.vht_supported && 301 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160); 302 break; 303 case IEEE80211_STA_RX_BW_80: 304 bw_mode = RTW89_CHANNEL_WIDTH_80; 305 sgi = sta->deflink.vht_cap.vht_supported && 306 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 307 break; 308 case IEEE80211_STA_RX_BW_40: 309 bw_mode = RTW89_CHANNEL_WIDTH_40; 310 sgi = sta->deflink.ht_cap.ht_supported && 311 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 312 break; 313 default: 314 bw_mode = RTW89_CHANNEL_WIDTH_20; 315 sgi = sta->deflink.ht_cap.ht_supported && 316 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 317 break; 318 } 319 320 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 321 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) 322 ra->dcm_cap = 1; 323 324 if (rate_pattern->enable) { 325 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 326 ra_mask &= rate_pattern->ra_mask; 327 mode = rate_pattern->ra_mode; 328 } 329 330 ra->bw_cap = bw_mode; 331 ra->mode_ctrl = mode; 332 ra->macid = rtwsta->mac_id; 333 ra->stbc_cap = stbc_en; 334 ra->ldpc_cap = ldpc_en; 335 ra->ss_num = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1; 336 ra->en_sgi = sgi; 337 ra->ra_mask = ra_mask; 338 339 if (!csi) 340 return; 341 342 ra->fixed_csi_rate_en = false; 343 ra->ra_csi_rate_en = true; 344 ra->cr_tbl_sel = false; 345 ra->band_num = rtwvif->phy_idx; 346 ra->csi_bw = bw_mode; 347 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; 348 ra->csi_mcs_ss_idx = 5; 349 ra->csi_mode = csi_mode; 350 } 351 352 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 353 u32 changed) 354 { 355 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 356 struct rtw89_ra_info *ra = &rtwsta->ra; 357 358 rtw89_phy_ra_sta_update(rtwdev, sta, false); 359 360 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) 361 ra->upd_mask = 1; 362 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED)) 363 ra->upd_bw_nss_mask = 1; 364 365 rtw89_debug(rtwdev, RTW89_DBG_RA, 366 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", 367 ra->macid, 368 ra->bw_cap, 369 ra->ss_num, 370 ra->en_sgi, 371 ra->giltf); 372 373 rtw89_fw_h2c_ra(rtwdev, ra, false); 374 } 375 376 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, 377 u16 rate_base, u64 ra_mask, u8 ra_mode, 378 u32 rate_ctrl, u32 ctrl_skip, bool force) 379 { 380 u8 n, c; 381 382 if (rate_ctrl == ctrl_skip) 383 return true; 384 385 n = hweight32(rate_ctrl); 386 if (n == 0) 387 return true; 388 389 if (force && n != 1) 390 return false; 391 392 if (next->enable) 393 return false; 394 395 c = __fls(rate_ctrl); 396 next->rate = rate_base + c; 397 next->ra_mode = ra_mode; 398 next->ra_mask = ra_mask; 399 next->enable = true; 400 401 return true; 402 } 403 404 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 405 struct ieee80211_vif *vif, 406 const struct cfg80211_bitrate_mask *mask) 407 { 408 struct ieee80211_supported_band *sband; 409 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 410 struct rtw89_phy_rate_pattern next_pattern = {0}; 411 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 412 static const u16 hw_rate_he[] = {RTW89_HW_RATE_HE_NSS1_MCS0, 413 RTW89_HW_RATE_HE_NSS2_MCS0, 414 RTW89_HW_RATE_HE_NSS3_MCS0, 415 RTW89_HW_RATE_HE_NSS4_MCS0}; 416 static const u16 hw_rate_vht[] = {RTW89_HW_RATE_VHT_NSS1_MCS0, 417 RTW89_HW_RATE_VHT_NSS2_MCS0, 418 RTW89_HW_RATE_VHT_NSS3_MCS0, 419 RTW89_HW_RATE_VHT_NSS4_MCS0}; 420 static const u16 hw_rate_ht[] = {RTW89_HW_RATE_MCS0, 421 RTW89_HW_RATE_MCS8, 422 RTW89_HW_RATE_MCS16, 423 RTW89_HW_RATE_MCS24}; 424 u8 band = chan->band_type; 425 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 426 u8 tx_nss = rtwdev->hal.tx_nss; 427 u8 i; 428 429 for (i = 0; i < tx_nss; i++) 430 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i], 431 RA_MASK_HE_RATES, RTW89_RA_MODE_HE, 432 mask->control[nl_band].he_mcs[i], 433 0, true)) 434 goto out; 435 436 for (i = 0; i < tx_nss; i++) 437 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i], 438 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, 439 mask->control[nl_band].vht_mcs[i], 440 0, true)) 441 goto out; 442 443 for (i = 0; i < tx_nss; i++) 444 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i], 445 RA_MASK_HT_RATES, RTW89_RA_MODE_HT, 446 mask->control[nl_band].ht_mcs[i], 447 0, true)) 448 goto out; 449 450 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and 451 * require at least one basic rate for ieee80211_set_bitrate_mask, 452 * so the decision just depends on if all bitrates are set or not. 453 */ 454 sband = rtwdev->hw->wiphy->bands[nl_band]; 455 if (band == RTW89_BAND_2G) { 456 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, 457 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, 458 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, 459 mask->control[nl_band].legacy, 460 BIT(sband->n_bitrates) - 1, false)) 461 goto out; 462 } else { 463 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, 464 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, 465 mask->control[nl_band].legacy, 466 BIT(sband->n_bitrates) - 1, false)) 467 goto out; 468 } 469 470 if (!next_pattern.enable) 471 goto out; 472 473 rtwvif->rate_pattern = next_pattern; 474 rtw89_debug(rtwdev, RTW89_DBG_RA, 475 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", 476 next_pattern.rate, 477 next_pattern.ra_mask, 478 next_pattern.ra_mode); 479 return; 480 481 out: 482 rtwvif->rate_pattern.enable = false; 483 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); 484 } 485 486 static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta) 487 { 488 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; 489 490 rtw89_phy_ra_updata_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED); 491 } 492 493 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) 494 { 495 ieee80211_iterate_stations_atomic(rtwdev->hw, 496 rtw89_phy_ra_updata_sta_iter, 497 rtwdev); 498 } 499 500 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) 501 { 502 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 503 struct rtw89_ra_info *ra = &rtwsta->ra; 504 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; 505 bool csi = rtw89_sta_has_beamformer_cap(sta); 506 507 rtw89_phy_ra_sta_update(rtwdev, sta, csi); 508 509 if (rssi > 40) 510 ra->init_rate_lv = 1; 511 else if (rssi > 20) 512 ra->init_rate_lv = 2; 513 else if (rssi > 1) 514 ra->init_rate_lv = 3; 515 else 516 ra->init_rate_lv = 0; 517 ra->upd_all = 1; 518 rtw89_debug(rtwdev, RTW89_DBG_RA, 519 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", 520 ra->macid, 521 ra->mode_ctrl, 522 ra->bw_cap, 523 ra->ss_num, 524 ra->init_rate_lv); 525 rtw89_debug(rtwdev, RTW89_DBG_RA, 526 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", 527 ra->dcm_cap, 528 ra->er_cap, 529 ra->ldpc_cap, 530 ra->stbc_cap, 531 ra->en_sgi, 532 ra->giltf); 533 534 rtw89_fw_h2c_ra(rtwdev, ra, csi); 535 } 536 537 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 538 const struct rtw89_chan *chan, 539 enum rtw89_bandwidth dbw) 540 { 541 enum rtw89_bandwidth cbw = chan->band_width; 542 u8 pri_ch = chan->primary_channel; 543 u8 central_ch = chan->channel; 544 u8 txsc_idx = 0; 545 u8 tmp = 0; 546 547 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 548 return txsc_idx; 549 550 switch (cbw) { 551 case RTW89_CHANNEL_WIDTH_40: 552 txsc_idx = pri_ch > central_ch ? 1 : 2; 553 break; 554 case RTW89_CHANNEL_WIDTH_80: 555 if (dbw == RTW89_CHANNEL_WIDTH_20) { 556 if (pri_ch > central_ch) 557 txsc_idx = (pri_ch - central_ch) >> 1; 558 else 559 txsc_idx = ((central_ch - pri_ch) >> 1) + 1; 560 } else { 561 txsc_idx = pri_ch > central_ch ? 9 : 10; 562 } 563 break; 564 case RTW89_CHANNEL_WIDTH_160: 565 if (pri_ch > central_ch) 566 tmp = (pri_ch - central_ch) >> 1; 567 else 568 tmp = ((central_ch - pri_ch) >> 1) + 1; 569 570 if (dbw == RTW89_CHANNEL_WIDTH_20) { 571 txsc_idx = tmp; 572 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 573 if (tmp == 1 || tmp == 3) 574 txsc_idx = 9; 575 else if (tmp == 5 || tmp == 7) 576 txsc_idx = 11; 577 else if (tmp == 2 || tmp == 4) 578 txsc_idx = 10; 579 else if (tmp == 6 || tmp == 8) 580 txsc_idx = 12; 581 else 582 return 0xff; 583 } else { 584 txsc_idx = pri_ch > central_ch ? 13 : 14; 585 } 586 break; 587 case RTW89_CHANNEL_WIDTH_80_80: 588 if (dbw == RTW89_CHANNEL_WIDTH_20) { 589 if (pri_ch > central_ch) 590 txsc_idx = (10 - (pri_ch - central_ch)) >> 1; 591 else 592 txsc_idx = ((central_ch - pri_ch) >> 1) + 5; 593 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 594 txsc_idx = pri_ch > central_ch ? 10 : 12; 595 } else { 596 txsc_idx = 14; 597 } 598 break; 599 default: 600 break; 601 } 602 603 return txsc_idx; 604 } 605 EXPORT_SYMBOL(rtw89_phy_get_txsc); 606 607 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev) 608 { 609 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) || 610 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1); 611 } 612 613 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 614 u32 addr, u32 mask) 615 { 616 const struct rtw89_chip_info *chip = rtwdev->chip; 617 const u32 *base_addr = chip->rf_base_addr; 618 u32 val, direct_addr; 619 620 if (rf_path >= rtwdev->chip->rf_path_num) { 621 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 622 return INV_RF_DATA; 623 } 624 625 addr &= 0xff; 626 direct_addr = base_addr[rf_path] + (addr << 2); 627 mask &= RFREG_MASK; 628 629 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); 630 631 return val; 632 } 633 EXPORT_SYMBOL(rtw89_phy_read_rf); 634 635 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev, 636 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 637 { 638 bool busy; 639 bool done; 640 u32 val; 641 int ret; 642 643 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 644 1, 30, false, rtwdev); 645 if (ret) { 646 rtw89_err(rtwdev, "read rf busy swsi\n"); 647 return INV_RF_DATA; 648 } 649 650 mask &= RFREG_MASK; 651 652 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) | 653 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr); 654 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val); 655 udelay(2); 656 657 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1, 658 30, false, rtwdev, R_SWSI_V1, 659 B_SWSI_R_DATA_DONE_V1); 660 if (ret) { 661 rtw89_err(rtwdev, "read swsi busy\n"); 662 return INV_RF_DATA; 663 } 664 665 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask); 666 } 667 668 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 669 u32 addr, u32 mask) 670 { 671 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 672 673 if (rf_path >= rtwdev->chip->rf_path_num) { 674 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 675 return INV_RF_DATA; 676 } 677 678 if (ad_sel) 679 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 680 else 681 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask); 682 } 683 EXPORT_SYMBOL(rtw89_phy_read_rf_v1); 684 685 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 686 u32 addr, u32 mask, u32 data) 687 { 688 const struct rtw89_chip_info *chip = rtwdev->chip; 689 const u32 *base_addr = chip->rf_base_addr; 690 u32 direct_addr; 691 692 if (rf_path >= rtwdev->chip->rf_path_num) { 693 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 694 return false; 695 } 696 697 addr &= 0xff; 698 direct_addr = base_addr[rf_path] + (addr << 2); 699 mask &= RFREG_MASK; 700 701 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); 702 703 /* delay to ensure writing properly */ 704 udelay(1); 705 706 return true; 707 } 708 EXPORT_SYMBOL(rtw89_phy_write_rf); 709 710 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev, 711 enum rtw89_rf_path rf_path, u32 addr, u32 mask, 712 u32 data) 713 { 714 u8 bit_shift; 715 u32 val; 716 bool busy, b_msk_en = false; 717 int ret; 718 719 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 720 1, 30, false, rtwdev); 721 if (ret) { 722 rtw89_err(rtwdev, "write rf busy swsi\n"); 723 return false; 724 } 725 726 data &= RFREG_MASK; 727 mask &= RFREG_MASK; 728 729 if (mask != RFREG_MASK) { 730 b_msk_en = true; 731 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK, 732 mask); 733 bit_shift = __ffs(mask); 734 data = (data << bit_shift) & RFREG_MASK; 735 } 736 737 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) | 738 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) | 739 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) | 740 FIELD_PREP(B_SWSI_DATA_VAL_V1, data); 741 742 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val); 743 744 return true; 745 } 746 747 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 748 u32 addr, u32 mask, u32 data) 749 { 750 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 751 752 if (rf_path >= rtwdev->chip->rf_path_num) { 753 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 754 return false; 755 } 756 757 if (ad_sel) 758 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 759 else 760 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data); 761 } 762 EXPORT_SYMBOL(rtw89_phy_write_rf_v1); 763 764 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, 765 enum rtw89_phy_idx phy_idx) 766 { 767 const struct rtw89_chip_info *chip = rtwdev->chip; 768 769 chip->ops->bb_reset(rtwdev, phy_idx); 770 } 771 772 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, 773 const struct rtw89_reg2_def *reg, 774 enum rtw89_rf_path rf_path, 775 void *extra_data) 776 { 777 if (reg->addr == 0xfe) 778 mdelay(50); 779 else if (reg->addr == 0xfd) 780 mdelay(5); 781 else if (reg->addr == 0xfc) 782 mdelay(1); 783 else if (reg->addr == 0xfb) 784 udelay(50); 785 else if (reg->addr == 0xfa) 786 udelay(5); 787 else if (reg->addr == 0xf9) 788 udelay(1); 789 else 790 rtw89_phy_write32(rtwdev, reg->addr, reg->data); 791 } 792 793 union rtw89_phy_bb_gain_arg { 794 u32 addr; 795 struct { 796 union { 797 u8 type; 798 struct { 799 u8 rxsc_start:4; 800 u8 bw:4; 801 }; 802 }; 803 u8 path; 804 u8 gain_band; 805 u8 cfg_type; 806 }; 807 } __packed; 808 809 static void 810 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev, 811 union rtw89_phy_bb_gain_arg arg, u32 data) 812 { 813 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 814 u8 type = arg.type; 815 u8 path = arg.path; 816 u8 gband = arg.gain_band; 817 int i; 818 819 switch (type) { 820 case 0: 821 for (i = 0; i < 4; i++, data >>= 8) 822 gain->lna_gain[gband][path][i] = data & 0xff; 823 break; 824 case 1: 825 for (i = 4; i < 7; i++, data >>= 8) 826 gain->lna_gain[gband][path][i] = data & 0xff; 827 break; 828 case 2: 829 for (i = 0; i < 2; i++, data >>= 8) 830 gain->tia_gain[gband][path][i] = data & 0xff; 831 break; 832 default: 833 rtw89_warn(rtwdev, 834 "bb gain error {0x%x:0x%x} with unknown type: %d\n", 835 arg.addr, data, type); 836 break; 837 } 838 } 839 840 enum rtw89_phy_bb_rxsc_start_idx { 841 RTW89_BB_RXSC_START_IDX_FULL = 0, 842 RTW89_BB_RXSC_START_IDX_20 = 1, 843 RTW89_BB_RXSC_START_IDX_20_1 = 5, 844 RTW89_BB_RXSC_START_IDX_40 = 9, 845 RTW89_BB_RXSC_START_IDX_80 = 13, 846 }; 847 848 static void 849 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev, 850 union rtw89_phy_bb_gain_arg arg, u32 data) 851 { 852 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 853 u8 rxsc_start = arg.rxsc_start; 854 u8 bw = arg.bw; 855 u8 path = arg.path; 856 u8 gband = arg.gain_band; 857 u8 rxsc; 858 s8 ofst; 859 int i; 860 861 switch (bw) { 862 case RTW89_CHANNEL_WIDTH_20: 863 gain->rpl_ofst_20[gband][path] = (s8)data; 864 break; 865 case RTW89_CHANNEL_WIDTH_40: 866 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 867 gain->rpl_ofst_40[gband][path][0] = (s8)data; 868 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 869 for (i = 0; i < 2; i++, data >>= 8) { 870 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 871 ofst = (s8)(data & 0xff); 872 gain->rpl_ofst_40[gband][path][rxsc] = ofst; 873 } 874 } 875 break; 876 case RTW89_CHANNEL_WIDTH_80: 877 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 878 gain->rpl_ofst_80[gband][path][0] = (s8)data; 879 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 880 for (i = 0; i < 4; i++, data >>= 8) { 881 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 882 ofst = (s8)(data & 0xff); 883 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 884 } 885 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 886 for (i = 0; i < 2; i++, data >>= 8) { 887 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 888 ofst = (s8)(data & 0xff); 889 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 890 } 891 } 892 break; 893 case RTW89_CHANNEL_WIDTH_160: 894 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 895 gain->rpl_ofst_160[gband][path][0] = (s8)data; 896 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 897 for (i = 0; i < 4; i++, data >>= 8) { 898 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 899 ofst = (s8)(data & 0xff); 900 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 901 } 902 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) { 903 for (i = 0; i < 4; i++, data >>= 8) { 904 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i; 905 ofst = (s8)(data & 0xff); 906 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 907 } 908 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 909 for (i = 0; i < 4; i++, data >>= 8) { 910 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 911 ofst = (s8)(data & 0xff); 912 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 913 } 914 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) { 915 for (i = 0; i < 2; i++, data >>= 8) { 916 rxsc = RTW89_BB_RXSC_START_IDX_80 + i; 917 ofst = (s8)(data & 0xff); 918 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 919 } 920 } 921 break; 922 default: 923 rtw89_warn(rtwdev, 924 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n", 925 arg.addr, data, bw); 926 break; 927 } 928 } 929 930 static void 931 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev, 932 union rtw89_phy_bb_gain_arg arg, u32 data) 933 { 934 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 935 u8 type = arg.type; 936 u8 path = arg.path; 937 u8 gband = arg.gain_band; 938 int i; 939 940 switch (type) { 941 case 0: 942 for (i = 0; i < 4; i++, data >>= 8) 943 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 944 break; 945 case 1: 946 for (i = 4; i < 7; i++, data >>= 8) 947 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 948 break; 949 default: 950 rtw89_warn(rtwdev, 951 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n", 952 arg.addr, data, type); 953 break; 954 } 955 } 956 957 static void 958 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev, 959 union rtw89_phy_bb_gain_arg arg, u32 data) 960 { 961 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 962 u8 type = arg.type; 963 u8 path = arg.path; 964 u8 gband = arg.gain_band; 965 int i; 966 967 switch (type) { 968 case 0: 969 for (i = 0; i < 4; i++, data >>= 8) 970 gain->lna_op1db[gband][path][i] = data & 0xff; 971 break; 972 case 1: 973 for (i = 4; i < 7; i++, data >>= 8) 974 gain->lna_op1db[gband][path][i] = data & 0xff; 975 break; 976 case 2: 977 for (i = 0; i < 4; i++, data >>= 8) 978 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 979 break; 980 case 3: 981 for (i = 4; i < 8; i++, data >>= 8) 982 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 983 break; 984 default: 985 rtw89_warn(rtwdev, 986 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n", 987 arg.addr, data, type); 988 break; 989 } 990 } 991 992 static void rtw89_phy_config_bb_gain(struct rtw89_dev *rtwdev, 993 const struct rtw89_reg2_def *reg, 994 enum rtw89_rf_path rf_path, 995 void *extra_data) 996 { 997 const struct rtw89_chip_info *chip = rtwdev->chip; 998 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr }; 999 1000 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR) 1001 return; 1002 1003 if (arg.path >= chip->rf_path_num) 1004 return; 1005 1006 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) { 1007 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n"); 1008 return; 1009 } 1010 1011 switch (arg.cfg_type) { 1012 case 0: 1013 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data); 1014 break; 1015 case 1: 1016 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data); 1017 break; 1018 case 2: 1019 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data); 1020 break; 1021 case 3: 1022 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data); 1023 break; 1024 default: 1025 rtw89_warn(rtwdev, 1026 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n", 1027 arg.addr, reg->data, arg.cfg_type); 1028 break; 1029 } 1030 } 1031 1032 static void 1033 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, 1034 const struct rtw89_reg2_def *reg, 1035 enum rtw89_rf_path rf_path, 1036 struct rtw89_fw_h2c_rf_reg_info *info) 1037 { 1038 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; 1039 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 1040 1041 if (page >= RTW89_H2C_RF_PAGE_NUM) { 1042 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d", 1043 rf_path, info->curr_idx); 1044 return; 1045 } 1046 1047 info->rtw89_phy_config_rf_h2c[page][idx] = 1048 cpu_to_le32((reg->addr << 20) | reg->data); 1049 info->curr_idx++; 1050 } 1051 1052 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, 1053 struct rtw89_fw_h2c_rf_reg_info *info) 1054 { 1055 u16 remain = info->curr_idx; 1056 u16 len = 0; 1057 u8 i; 1058 int ret = 0; 1059 1060 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) { 1061 rtw89_warn(rtwdev, 1062 "rf reg h2c total len %d larger than %d\n", 1063 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE); 1064 ret = -EINVAL; 1065 goto out; 1066 } 1067 1068 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) { 1069 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain; 1070 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i); 1071 if (ret) 1072 goto out; 1073 } 1074 out: 1075 info->curr_idx = 0; 1076 1077 return ret; 1078 } 1079 1080 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, 1081 const struct rtw89_reg2_def *reg, 1082 enum rtw89_rf_path rf_path, 1083 void *extra_data) 1084 { 1085 if (reg->addr == 0xfe) { 1086 mdelay(50); 1087 } else if (reg->addr == 0xfd) { 1088 mdelay(5); 1089 } else if (reg->addr == 0xfc) { 1090 mdelay(1); 1091 } else if (reg->addr == 0xfb) { 1092 udelay(50); 1093 } else if (reg->addr == 0xfa) { 1094 udelay(5); 1095 } else if (reg->addr == 0xf9) { 1096 udelay(1); 1097 } else { 1098 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); 1099 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1100 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1101 } 1102 } 1103 1104 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 1105 const struct rtw89_reg2_def *reg, 1106 enum rtw89_rf_path rf_path, 1107 void *extra_data) 1108 { 1109 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data); 1110 1111 if (reg->addr < 0x100) 1112 return; 1113 1114 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1115 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1116 } 1117 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1); 1118 1119 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, 1120 const struct rtw89_phy_table *table, 1121 u32 *headline_size, u32 *headline_idx, 1122 u8 rfe, u8 cv) 1123 { 1124 const struct rtw89_reg2_def *reg; 1125 u32 headline; 1126 u32 compare, target; 1127 u8 rfe_para, cv_para; 1128 u8 cv_max = 0; 1129 bool case_matched = false; 1130 u32 i; 1131 1132 for (i = 0; i < table->n_regs; i++) { 1133 reg = &table->regs[i]; 1134 headline = get_phy_headline(reg->addr); 1135 if (headline != PHY_HEADLINE_VALID) 1136 break; 1137 } 1138 *headline_size = i; 1139 if (*headline_size == 0) 1140 return 0; 1141 1142 /* case 1: RFE match, CV match */ 1143 compare = get_phy_compare(rfe, cv); 1144 for (i = 0; i < *headline_size; i++) { 1145 reg = &table->regs[i]; 1146 target = get_phy_target(reg->addr); 1147 if (target == compare) { 1148 *headline_idx = i; 1149 return 0; 1150 } 1151 } 1152 1153 /* case 2: RFE match, CV don't care */ 1154 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); 1155 for (i = 0; i < *headline_size; i++) { 1156 reg = &table->regs[i]; 1157 target = get_phy_target(reg->addr); 1158 if (target == compare) { 1159 *headline_idx = i; 1160 return 0; 1161 } 1162 } 1163 1164 /* case 3: RFE match, CV max in table */ 1165 for (i = 0; i < *headline_size; i++) { 1166 reg = &table->regs[i]; 1167 rfe_para = get_phy_cond_rfe(reg->addr); 1168 cv_para = get_phy_cond_cv(reg->addr); 1169 if (rfe_para == rfe) { 1170 if (cv_para >= cv_max) { 1171 cv_max = cv_para; 1172 *headline_idx = i; 1173 case_matched = true; 1174 } 1175 } 1176 } 1177 1178 if (case_matched) 1179 return 0; 1180 1181 /* case 4: RFE don't care, CV max in table */ 1182 for (i = 0; i < *headline_size; i++) { 1183 reg = &table->regs[i]; 1184 rfe_para = get_phy_cond_rfe(reg->addr); 1185 cv_para = get_phy_cond_cv(reg->addr); 1186 if (rfe_para == PHY_COND_DONT_CARE) { 1187 if (cv_para >= cv_max) { 1188 cv_max = cv_para; 1189 *headline_idx = i; 1190 case_matched = true; 1191 } 1192 } 1193 } 1194 1195 if (case_matched) 1196 return 0; 1197 1198 return -EINVAL; 1199 } 1200 1201 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, 1202 const struct rtw89_phy_table *table, 1203 void (*config)(struct rtw89_dev *rtwdev, 1204 const struct rtw89_reg2_def *reg, 1205 enum rtw89_rf_path rf_path, 1206 void *data), 1207 void *extra_data) 1208 { 1209 const struct rtw89_reg2_def *reg; 1210 enum rtw89_rf_path rf_path = table->rf_path; 1211 u8 rfe = rtwdev->efuse.rfe_type; 1212 u8 cv = rtwdev->hal.cv; 1213 u32 i; 1214 u32 headline_size = 0, headline_idx = 0; 1215 u32 target = 0, cfg_target; 1216 u8 cond; 1217 bool is_matched = true; 1218 bool target_found = false; 1219 int ret; 1220 1221 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, 1222 &headline_idx, rfe, cv); 1223 if (ret) { 1224 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); 1225 return; 1226 } 1227 1228 cfg_target = get_phy_target(table->regs[headline_idx].addr); 1229 for (i = headline_size; i < table->n_regs; i++) { 1230 reg = &table->regs[i]; 1231 cond = get_phy_cond(reg->addr); 1232 switch (cond) { 1233 case PHY_COND_BRANCH_IF: 1234 case PHY_COND_BRANCH_ELIF: 1235 target = get_phy_target(reg->addr); 1236 break; 1237 case PHY_COND_BRANCH_ELSE: 1238 is_matched = false; 1239 if (!target_found) { 1240 rtw89_warn(rtwdev, "failed to load CR %x/%x\n", 1241 reg->addr, reg->data); 1242 return; 1243 } 1244 break; 1245 case PHY_COND_BRANCH_END: 1246 is_matched = true; 1247 target_found = false; 1248 break; 1249 case PHY_COND_CHECK: 1250 if (target_found) { 1251 is_matched = false; 1252 break; 1253 } 1254 1255 if (target == cfg_target) { 1256 is_matched = true; 1257 target_found = true; 1258 } else { 1259 is_matched = false; 1260 target_found = false; 1261 } 1262 break; 1263 default: 1264 if (is_matched) 1265 config(rtwdev, reg, rf_path, extra_data); 1266 break; 1267 } 1268 } 1269 } 1270 1271 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) 1272 { 1273 const struct rtw89_chip_info *chip = rtwdev->chip; 1274 const struct rtw89_phy_table *bb_table = chip->bb_table; 1275 const struct rtw89_phy_table *bb_gain_table = chip->bb_gain_table; 1276 1277 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); 1278 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 1279 if (bb_gain_table) 1280 rtw89_phy_init_reg(rtwdev, bb_gain_table, 1281 rtw89_phy_config_bb_gain, NULL); 1282 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); 1283 } 1284 1285 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 1286 { 1287 rtw89_phy_write32(rtwdev, 0x8080, 0x4); 1288 udelay(1); 1289 return rtw89_phy_read32(rtwdev, 0x8080); 1290 } 1291 1292 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev) 1293 { 1294 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 1295 enum rtw89_rf_path rf_path, void *data); 1296 const struct rtw89_chip_info *chip = rtwdev->chip; 1297 const struct rtw89_phy_table *rf_table; 1298 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; 1299 u8 path; 1300 1301 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); 1302 if (!rf_reg_info) 1303 return; 1304 1305 for (path = RF_PATH_A; path < chip->rf_path_num; path++) { 1306 rf_table = chip->rf_table[path]; 1307 rf_reg_info->rf_path = rf_table->rf_path; 1308 config = rf_table->config ? rf_table->config : rtw89_phy_config_rf_reg; 1309 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info); 1310 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) 1311 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", 1312 rf_reg_info->rf_path); 1313 } 1314 kfree(rf_reg_info); 1315 } 1316 1317 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) 1318 { 1319 const struct rtw89_chip_info *chip = rtwdev->chip; 1320 const struct rtw89_phy_table *nctl_table; 1321 u32 val; 1322 int ret; 1323 1324 /* IQK/DPK clock & reset */ 1325 rtw89_phy_write32_set(rtwdev, 0x0c60, 0x3); 1326 rtw89_phy_write32_set(rtwdev, 0x0c6c, 0x1); 1327 rtw89_phy_write32_set(rtwdev, 0x58ac, 0x8000000); 1328 rtw89_phy_write32_set(rtwdev, 0x78ac, 0x8000000); 1329 1330 /* check 0x8080 */ 1331 rtw89_phy_write32(rtwdev, 0x8000, 0x8); 1332 1333 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, 1334 1000, false, rtwdev); 1335 if (ret) 1336 rtw89_err(rtwdev, "failed to poll nctl block\n"); 1337 1338 nctl_table = chip->nctl_table; 1339 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); 1340 } 1341 1342 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) 1343 { 1344 u32 phy_page = addr >> 8; 1345 u32 ofst = 0; 1346 1347 switch (phy_page) { 1348 case 0x6: 1349 case 0x7: 1350 case 0x8: 1351 case 0x9: 1352 case 0xa: 1353 case 0xb: 1354 case 0xc: 1355 case 0xd: 1356 case 0x19: 1357 case 0x1a: 1358 case 0x1b: 1359 ofst = 0x2000; 1360 break; 1361 default: 1362 /* warning case */ 1363 ofst = 0; 1364 break; 1365 } 1366 1367 if (phy_page >= 0x40 && phy_page <= 0x4f) 1368 ofst = 0x2000; 1369 1370 return ofst; 1371 } 1372 1373 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1374 u32 data, enum rtw89_phy_idx phy_idx) 1375 { 1376 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1377 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1378 rtw89_phy_write32_mask(rtwdev, addr, mask, data); 1379 } 1380 EXPORT_SYMBOL(rtw89_phy_write32_idx); 1381 1382 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1383 u32 val) 1384 { 1385 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 1386 1387 if (!rtwdev->dbcc_en) 1388 return; 1389 1390 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 1391 } 1392 1393 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 1394 const struct rtw89_phy_reg3_tbl *tbl) 1395 { 1396 const struct rtw89_reg3_def *reg3; 1397 int i; 1398 1399 for (i = 0; i < tbl->size; i++) { 1400 reg3 = &tbl->reg3[i]; 1401 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); 1402 } 1403 } 1404 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl); 1405 1406 const u8 rtw89_rs_idx_max[] = { 1407 [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX, 1408 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX, 1409 [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX, 1410 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX, 1411 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX, 1412 }; 1413 EXPORT_SYMBOL(rtw89_rs_idx_max); 1414 1415 const u8 rtw89_rs_nss_max[] = { 1416 [RTW89_RS_CCK] = 1, 1417 [RTW89_RS_OFDM] = 1, 1418 [RTW89_RS_MCS] = RTW89_NSS_MAX, 1419 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX, 1420 [RTW89_RS_OFFSET] = 1, 1421 }; 1422 EXPORT_SYMBOL(rtw89_rs_nss_max); 1423 1424 static const u8 _byr_of_rs[] = { 1425 [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck), 1426 [RTW89_RS_OFDM] = offsetof(struct rtw89_txpwr_byrate, ofdm), 1427 [RTW89_RS_MCS] = offsetof(struct rtw89_txpwr_byrate, mcs), 1428 [RTW89_RS_HEDCM] = offsetof(struct rtw89_txpwr_byrate, hedcm), 1429 [RTW89_RS_OFFSET] = offsetof(struct rtw89_txpwr_byrate, offset), 1430 }; 1431 1432 #define _byr_seek(rs, raw) ((s8 *)(raw) + _byr_of_rs[rs]) 1433 #define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_max[rs] + (idx)) 1434 #define _byr_chk(rs, nss, idx) \ 1435 ((nss) < rtw89_rs_nss_max[rs] && (idx) < rtw89_rs_idx_max[rs]) 1436 1437 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 1438 const struct rtw89_txpwr_table *tbl) 1439 { 1440 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; 1441 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; 1442 s8 *byr; 1443 u32 data; 1444 u8 i, idx; 1445 1446 for (; cfg < end; cfg++) { 1447 byr = _byr_seek(cfg->rs, &rtwdev->byr[cfg->band]); 1448 data = cfg->data; 1449 1450 for (i = 0; i < cfg->len; i++, data >>= 8) { 1451 idx = _byr_idx(cfg->rs, cfg->nss, (cfg->shf + i)); 1452 byr[idx] = (s8)(data & 0xff); 1453 } 1454 } 1455 } 1456 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate); 1457 1458 #define _phy_txpwr_rf_to_mac(rtwdev, txpwr_rf) \ 1459 ({ \ 1460 const struct rtw89_chip_info *__c = (rtwdev)->chip; \ 1461 (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \ 1462 }) 1463 1464 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, 1465 const struct rtw89_rate_desc *rate_desc) 1466 { 1467 s8 *byr; 1468 u8 idx; 1469 1470 if (rate_desc->rs == RTW89_RS_CCK) 1471 band = RTW89_BAND_2G; 1472 1473 if (!_byr_chk(rate_desc->rs, rate_desc->nss, rate_desc->idx)) { 1474 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1475 "[TXPWR] unknown byrate desc rs=%d nss=%d idx=%d\n", 1476 rate_desc->rs, rate_desc->nss, rate_desc->idx); 1477 1478 return 0; 1479 } 1480 1481 byr = _byr_seek(rate_desc->rs, &rtwdev->byr[band]); 1482 idx = _byr_idx(rate_desc->rs, rate_desc->nss, rate_desc->idx); 1483 1484 return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]); 1485 } 1486 EXPORT_SYMBOL(rtw89_phy_read_txpwr_byrate); 1487 1488 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g) 1489 { 1490 switch (channel_6g) { 1491 case 1 ... 29: 1492 return (channel_6g - 1) / 2; 1493 case 33 ... 61: 1494 return (channel_6g - 3) / 2; 1495 case 65 ... 93: 1496 return (channel_6g - 5) / 2; 1497 case 97 ... 125: 1498 return (channel_6g - 7) / 2; 1499 case 129 ... 157: 1500 return (channel_6g - 9) / 2; 1501 case 161 ... 189: 1502 return (channel_6g - 11) / 2; 1503 case 193 ... 221: 1504 return (channel_6g - 13) / 2; 1505 case 225 ... 253: 1506 return (channel_6g - 15) / 2; 1507 default: 1508 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g); 1509 return 0; 1510 } 1511 } 1512 1513 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel) 1514 { 1515 if (band == RTW89_BAND_6G) 1516 return rtw89_channel_6g_to_idx(rtwdev, channel); 1517 1518 switch (channel) { 1519 case 1 ... 14: 1520 return channel - 1; 1521 case 36 ... 64: 1522 return (channel - 36) / 2; 1523 case 100 ... 144: 1524 return ((channel - 100) / 2) + 15; 1525 case 149 ... 177: 1526 return ((channel - 149) / 2) + 38; 1527 default: 1528 rtw89_warn(rtwdev, "unknown channel: %d\n", channel); 1529 return 0; 1530 } 1531 } 1532 1533 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 1534 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) 1535 { 1536 const struct rtw89_chip_info *chip = rtwdev->chip; 1537 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1538 u8 regd = rtw89_regd_get(rtwdev, band); 1539 s8 lmt = 0, sar; 1540 1541 switch (band) { 1542 case RTW89_BAND_2G: 1543 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf][regd][ch_idx]; 1544 if (!lmt) 1545 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf] 1546 [RTW89_WW][ch_idx]; 1547 break; 1548 case RTW89_BAND_5G: 1549 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf][regd][ch_idx]; 1550 if (!lmt) 1551 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf] 1552 [RTW89_WW][ch_idx]; 1553 break; 1554 case RTW89_BAND_6G: 1555 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf][regd][ch_idx]; 1556 if (!lmt) 1557 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf] 1558 [RTW89_WW][ch_idx]; 1559 break; 1560 default: 1561 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1562 return 0; 1563 } 1564 1565 lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt); 1566 sar = rtw89_query_sar(rtwdev); 1567 1568 return min(lmt, sar); 1569 } 1570 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit); 1571 1572 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \ 1573 do { \ 1574 u8 __i; \ 1575 for (__i = 0; __i < RTW89_BF_NUM; __i++) \ 1576 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ 1577 band, \ 1578 bw, ntx, \ 1579 rs, __i, \ 1580 (ch)); \ 1581 } while (0) 1582 1583 static void rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev *rtwdev, 1584 struct rtw89_txpwr_limit *lmt, 1585 u8 band, u8 ntx, u8 ch) 1586 { 1587 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1588 ntx, RTW89_RS_CCK, ch); 1589 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1590 ntx, RTW89_RS_CCK, ch); 1591 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1592 ntx, RTW89_RS_OFDM, ch); 1593 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1594 RTW89_CHANNEL_WIDTH_20, 1595 ntx, RTW89_RS_MCS, ch); 1596 } 1597 1598 static void rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev *rtwdev, 1599 struct rtw89_txpwr_limit *lmt, 1600 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1601 { 1602 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1603 ntx, RTW89_RS_CCK, ch - 2); 1604 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1605 ntx, RTW89_RS_CCK, ch); 1606 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1607 ntx, RTW89_RS_OFDM, pri_ch); 1608 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1609 RTW89_CHANNEL_WIDTH_20, 1610 ntx, RTW89_RS_MCS, ch - 2); 1611 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1612 RTW89_CHANNEL_WIDTH_20, 1613 ntx, RTW89_RS_MCS, ch + 2); 1614 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1615 RTW89_CHANNEL_WIDTH_40, 1616 ntx, RTW89_RS_MCS, ch); 1617 } 1618 1619 static void rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev *rtwdev, 1620 struct rtw89_txpwr_limit *lmt, 1621 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1622 { 1623 s8 val_0p5_n[RTW89_BF_NUM]; 1624 s8 val_0p5_p[RTW89_BF_NUM]; 1625 u8 i; 1626 1627 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1628 ntx, RTW89_RS_OFDM, pri_ch); 1629 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1630 RTW89_CHANNEL_WIDTH_20, 1631 ntx, RTW89_RS_MCS, ch - 6); 1632 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1633 RTW89_CHANNEL_WIDTH_20, 1634 ntx, RTW89_RS_MCS, ch - 2); 1635 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1636 RTW89_CHANNEL_WIDTH_20, 1637 ntx, RTW89_RS_MCS, ch + 2); 1638 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1639 RTW89_CHANNEL_WIDTH_20, 1640 ntx, RTW89_RS_MCS, ch + 6); 1641 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1642 RTW89_CHANNEL_WIDTH_40, 1643 ntx, RTW89_RS_MCS, ch - 4); 1644 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1645 RTW89_CHANNEL_WIDTH_40, 1646 ntx, RTW89_RS_MCS, ch + 4); 1647 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1648 RTW89_CHANNEL_WIDTH_80, 1649 ntx, RTW89_RS_MCS, ch); 1650 1651 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1652 ntx, RTW89_RS_MCS, ch - 4); 1653 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1654 ntx, RTW89_RS_MCS, ch + 4); 1655 1656 for (i = 0; i < RTW89_BF_NUM; i++) 1657 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1658 } 1659 1660 static void rtw89_phy_fill_txpwr_limit_160m(struct rtw89_dev *rtwdev, 1661 struct rtw89_txpwr_limit *lmt, 1662 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1663 { 1664 s8 val_0p5_n[RTW89_BF_NUM]; 1665 s8 val_0p5_p[RTW89_BF_NUM]; 1666 s8 val_2p5_n[RTW89_BF_NUM]; 1667 s8 val_2p5_p[RTW89_BF_NUM]; 1668 u8 i; 1669 1670 /* fill ofdm section */ 1671 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1672 ntx, RTW89_RS_OFDM, pri_ch); 1673 1674 /* fill mcs 20m section */ 1675 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1676 RTW89_CHANNEL_WIDTH_20, 1677 ntx, RTW89_RS_MCS, ch - 14); 1678 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1679 RTW89_CHANNEL_WIDTH_20, 1680 ntx, RTW89_RS_MCS, ch - 10); 1681 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1682 RTW89_CHANNEL_WIDTH_20, 1683 ntx, RTW89_RS_MCS, ch - 6); 1684 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1685 RTW89_CHANNEL_WIDTH_20, 1686 ntx, RTW89_RS_MCS, ch - 2); 1687 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band, 1688 RTW89_CHANNEL_WIDTH_20, 1689 ntx, RTW89_RS_MCS, ch + 2); 1690 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band, 1691 RTW89_CHANNEL_WIDTH_20, 1692 ntx, RTW89_RS_MCS, ch + 6); 1693 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band, 1694 RTW89_CHANNEL_WIDTH_20, 1695 ntx, RTW89_RS_MCS, ch + 10); 1696 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band, 1697 RTW89_CHANNEL_WIDTH_20, 1698 ntx, RTW89_RS_MCS, ch + 14); 1699 1700 /* fill mcs 40m section */ 1701 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1702 RTW89_CHANNEL_WIDTH_40, 1703 ntx, RTW89_RS_MCS, ch - 12); 1704 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1705 RTW89_CHANNEL_WIDTH_40, 1706 ntx, RTW89_RS_MCS, ch - 4); 1707 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band, 1708 RTW89_CHANNEL_WIDTH_40, 1709 ntx, RTW89_RS_MCS, ch + 4); 1710 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band, 1711 RTW89_CHANNEL_WIDTH_40, 1712 ntx, RTW89_RS_MCS, ch + 12); 1713 1714 /* fill mcs 80m section */ 1715 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1716 RTW89_CHANNEL_WIDTH_80, 1717 ntx, RTW89_RS_MCS, ch - 8); 1718 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band, 1719 RTW89_CHANNEL_WIDTH_80, 1720 ntx, RTW89_RS_MCS, ch + 8); 1721 1722 /* fill mcs 160m section */ 1723 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band, 1724 RTW89_CHANNEL_WIDTH_160, 1725 ntx, RTW89_RS_MCS, ch); 1726 1727 /* fill mcs 40m 0p5 section */ 1728 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1729 ntx, RTW89_RS_MCS, ch - 4); 1730 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1731 ntx, RTW89_RS_MCS, ch + 4); 1732 1733 for (i = 0; i < RTW89_BF_NUM; i++) 1734 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1735 1736 /* fill mcs 40m 2p5 section */ 1737 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40, 1738 ntx, RTW89_RS_MCS, ch - 8); 1739 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40, 1740 ntx, RTW89_RS_MCS, ch + 8); 1741 1742 for (i = 0; i < RTW89_BF_NUM; i++) 1743 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]); 1744 } 1745 1746 void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev, 1747 const struct rtw89_chan *chan, 1748 struct rtw89_txpwr_limit *lmt, 1749 u8 ntx) 1750 { 1751 u8 band = chan->band_type; 1752 u8 pri_ch = chan->primary_channel; 1753 u8 ch = chan->channel; 1754 u8 bw = chan->band_width; 1755 1756 memset(lmt, 0, sizeof(*lmt)); 1757 1758 switch (bw) { 1759 case RTW89_CHANNEL_WIDTH_20: 1760 rtw89_phy_fill_txpwr_limit_20m(rtwdev, lmt, band, ntx, ch); 1761 break; 1762 case RTW89_CHANNEL_WIDTH_40: 1763 rtw89_phy_fill_txpwr_limit_40m(rtwdev, lmt, band, ntx, ch, 1764 pri_ch); 1765 break; 1766 case RTW89_CHANNEL_WIDTH_80: 1767 rtw89_phy_fill_txpwr_limit_80m(rtwdev, lmt, band, ntx, ch, 1768 pri_ch); 1769 break; 1770 case RTW89_CHANNEL_WIDTH_160: 1771 rtw89_phy_fill_txpwr_limit_160m(rtwdev, lmt, band, ntx, ch, 1772 pri_ch); 1773 break; 1774 } 1775 } 1776 EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit); 1777 1778 static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 1779 u8 ru, u8 ntx, u8 ch) 1780 { 1781 const struct rtw89_chip_info *chip = rtwdev->chip; 1782 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1783 u8 regd = rtw89_regd_get(rtwdev, band); 1784 s8 lmt_ru = 0, sar; 1785 1786 switch (band) { 1787 case RTW89_BAND_2G: 1788 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx][regd][ch_idx]; 1789 if (!lmt_ru) 1790 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx] 1791 [RTW89_WW][ch_idx]; 1792 break; 1793 case RTW89_BAND_5G: 1794 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx][regd][ch_idx]; 1795 if (!lmt_ru) 1796 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx] 1797 [RTW89_WW][ch_idx]; 1798 break; 1799 case RTW89_BAND_6G: 1800 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx][regd][ch_idx]; 1801 if (!lmt_ru) 1802 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx] 1803 [RTW89_WW][ch_idx]; 1804 break; 1805 default: 1806 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1807 return 0; 1808 } 1809 1810 lmt_ru = _phy_txpwr_rf_to_mac(rtwdev, lmt_ru); 1811 sar = rtw89_query_sar(rtwdev); 1812 1813 return min(lmt_ru, sar); 1814 } 1815 1816 static void 1817 rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev, 1818 struct rtw89_txpwr_limit_ru *lmt_ru, 1819 u8 band, u8 ntx, u8 ch) 1820 { 1821 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1822 RTW89_RU26, 1823 ntx, ch); 1824 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1825 RTW89_RU52, 1826 ntx, ch); 1827 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1828 RTW89_RU106, 1829 ntx, ch); 1830 } 1831 1832 static void 1833 rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev, 1834 struct rtw89_txpwr_limit_ru *lmt_ru, 1835 u8 band, u8 ntx, u8 ch) 1836 { 1837 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1838 RTW89_RU26, 1839 ntx, ch - 2); 1840 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1841 RTW89_RU26, 1842 ntx, ch + 2); 1843 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1844 RTW89_RU52, 1845 ntx, ch - 2); 1846 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1847 RTW89_RU52, 1848 ntx, ch + 2); 1849 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1850 RTW89_RU106, 1851 ntx, ch - 2); 1852 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1853 RTW89_RU106, 1854 ntx, ch + 2); 1855 } 1856 1857 static void 1858 rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev, 1859 struct rtw89_txpwr_limit_ru *lmt_ru, 1860 u8 band, u8 ntx, u8 ch) 1861 { 1862 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1863 RTW89_RU26, 1864 ntx, ch - 6); 1865 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1866 RTW89_RU26, 1867 ntx, ch - 2); 1868 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1869 RTW89_RU26, 1870 ntx, ch + 2); 1871 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1872 RTW89_RU26, 1873 ntx, ch + 6); 1874 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1875 RTW89_RU52, 1876 ntx, ch - 6); 1877 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1878 RTW89_RU52, 1879 ntx, ch - 2); 1880 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1881 RTW89_RU52, 1882 ntx, ch + 2); 1883 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1884 RTW89_RU52, 1885 ntx, ch + 6); 1886 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1887 RTW89_RU106, 1888 ntx, ch - 6); 1889 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1890 RTW89_RU106, 1891 ntx, ch - 2); 1892 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1893 RTW89_RU106, 1894 ntx, ch + 2); 1895 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1896 RTW89_RU106, 1897 ntx, ch + 6); 1898 } 1899 1900 static void 1901 rtw89_phy_fill_txpwr_limit_ru_160m(struct rtw89_dev *rtwdev, 1902 struct rtw89_txpwr_limit_ru *lmt_ru, 1903 u8 band, u8 ntx, u8 ch) 1904 { 1905 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 }; 1906 int i; 1907 1908 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM); 1909 for (i = 0; i < RTW89_RU_SEC_NUM; i++) { 1910 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1911 RTW89_RU26, 1912 ntx, 1913 ch + ofst[i]); 1914 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1915 RTW89_RU52, 1916 ntx, 1917 ch + ofst[i]); 1918 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1919 RTW89_RU106, 1920 ntx, 1921 ch + ofst[i]); 1922 } 1923 } 1924 1925 void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, 1926 const struct rtw89_chan *chan, 1927 struct rtw89_txpwr_limit_ru *lmt_ru, 1928 u8 ntx) 1929 { 1930 u8 band = chan->band_type; 1931 u8 ch = chan->channel; 1932 u8 bw = chan->band_width; 1933 1934 memset(lmt_ru, 0, sizeof(*lmt_ru)); 1935 1936 switch (bw) { 1937 case RTW89_CHANNEL_WIDTH_20: 1938 rtw89_phy_fill_txpwr_limit_ru_20m(rtwdev, lmt_ru, band, ntx, 1939 ch); 1940 break; 1941 case RTW89_CHANNEL_WIDTH_40: 1942 rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, band, ntx, 1943 ch); 1944 break; 1945 case RTW89_CHANNEL_WIDTH_80: 1946 rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, band, ntx, 1947 ch); 1948 break; 1949 case RTW89_CHANNEL_WIDTH_160: 1950 rtw89_phy_fill_txpwr_limit_ru_160m(rtwdev, lmt_ru, band, ntx, 1951 ch); 1952 break; 1953 } 1954 } 1955 EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit_ru); 1956 1957 struct rtw89_phy_iter_ra_data { 1958 struct rtw89_dev *rtwdev; 1959 struct sk_buff *c2h; 1960 }; 1961 1962 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) 1963 { 1964 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; 1965 struct rtw89_dev *rtwdev = ra_data->rtwdev; 1966 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1967 struct rtw89_ra_report *ra_report = &rtwsta->ra_report; 1968 struct sk_buff *c2h = ra_data->c2h; 1969 u8 mode, rate, bw, giltf, mac_id; 1970 u16 legacy_bitrate; 1971 bool valid; 1972 u8 mcs = 0; 1973 1974 mac_id = RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h->data); 1975 if (mac_id != rtwsta->mac_id) 1976 return; 1977 1978 rate = RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h->data); 1979 bw = RTW89_GET_PHY_C2H_RA_RPT_BW(c2h->data); 1980 giltf = RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h->data); 1981 mode = RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h->data); 1982 1983 if (mode == RTW89_RA_RPT_MODE_LEGACY) { 1984 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate); 1985 if (!valid) 1986 return; 1987 } 1988 1989 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate)); 1990 1991 switch (mode) { 1992 case RTW89_RA_RPT_MODE_LEGACY: 1993 ra_report->txrate.legacy = legacy_bitrate; 1994 break; 1995 case RTW89_RA_RPT_MODE_HT: 1996 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; 1997 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw)) 1998 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), 1999 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); 2000 else 2001 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); 2002 ra_report->txrate.mcs = rate; 2003 if (giltf) 2004 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2005 mcs = ra_report->txrate.mcs & 0x07; 2006 break; 2007 case RTW89_RA_RPT_MODE_VHT: 2008 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; 2009 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 2010 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 2011 if (giltf) 2012 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2013 mcs = ra_report->txrate.mcs; 2014 break; 2015 case RTW89_RA_RPT_MODE_HE: 2016 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; 2017 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 2018 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 2019 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2020 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; 2021 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2022 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; 2023 else 2024 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; 2025 mcs = ra_report->txrate.mcs; 2026 break; 2027 } 2028 2029 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw); 2030 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); 2031 ra_report->hw_rate = FIELD_PREP(RTW89_HW_RATE_MASK_MOD, mode) | 2032 FIELD_PREP(RTW89_HW_RATE_MASK_VAL, rate); 2033 ra_report->might_fallback_legacy = mcs <= 2; 2034 sta->max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); 2035 rtwsta->max_agg_wait = sta->max_rc_amsdu_len / 1500 - 1; 2036 } 2037 2038 static void 2039 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2040 { 2041 struct rtw89_phy_iter_ra_data ra_data; 2042 2043 ra_data.rtwdev = rtwdev; 2044 ra_data.c2h = c2h; 2045 ieee80211_iterate_stations_atomic(rtwdev->hw, 2046 rtw89_phy_c2h_ra_rpt_iter, 2047 &ra_data); 2048 } 2049 2050 static 2051 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, 2052 struct sk_buff *c2h, u32 len) = { 2053 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 2054 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 2055 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 2056 }; 2057 2058 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 2059 u32 len, u8 class, u8 func) 2060 { 2061 void (*handler)(struct rtw89_dev *rtwdev, 2062 struct sk_buff *c2h, u32 len) = NULL; 2063 2064 switch (class) { 2065 case RTW89_PHY_C2H_CLASS_RA: 2066 if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 2067 handler = rtw89_phy_c2h_ra_handler[func]; 2068 break; 2069 default: 2070 rtw89_info(rtwdev, "c2h class %d not support\n", class); 2071 return; 2072 } 2073 if (!handler) { 2074 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 2075 func); 2076 return; 2077 } 2078 handler(rtwdev, skb, len); 2079 } 2080 2081 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) 2082 { 2083 u32 reg_mask; 2084 2085 if (sc_xo) 2086 reg_mask = B_AX_XTAL_SC_XO_MASK; 2087 else 2088 reg_mask = B_AX_XTAL_SC_XI_MASK; 2089 2090 return (u8)rtw89_read32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask); 2091 } 2092 2093 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, 2094 u8 val) 2095 { 2096 u32 reg_mask; 2097 2098 if (sc_xo) 2099 reg_mask = B_AX_XTAL_SC_XO_MASK; 2100 else 2101 reg_mask = B_AX_XTAL_SC_XI_MASK; 2102 2103 rtw89_write32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask, val); 2104 } 2105 2106 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, 2107 u8 crystal_cap, bool force) 2108 { 2109 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2110 const struct rtw89_chip_info *chip = rtwdev->chip; 2111 u8 sc_xi_val, sc_xo_val; 2112 2113 if (!force && cfo->crystal_cap == crystal_cap) 2114 return; 2115 crystal_cap = clamp_t(u8, crystal_cap, 0, 127); 2116 if (chip->chip_id == RTL8852A) { 2117 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); 2118 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); 2119 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); 2120 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); 2121 } else { 2122 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, 2123 crystal_cap, XTAL_SC_XO_MASK); 2124 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, 2125 crystal_cap, XTAL_SC_XI_MASK); 2126 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val); 2127 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val); 2128 } 2129 cfo->crystal_cap = sc_xi_val; 2130 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); 2131 2132 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); 2133 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); 2134 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", 2135 cfo->x_cap_ofst); 2136 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); 2137 } 2138 2139 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) 2140 { 2141 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2142 u8 cap; 2143 2144 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; 2145 cfo->is_adjust = false; 2146 if (cfo->crystal_cap == cfo->def_x_cap) 2147 return; 2148 cap = cfo->crystal_cap; 2149 cap += (cap > cfo->def_x_cap ? -1 : 1); 2150 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); 2151 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2152 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, 2153 cfo->def_x_cap); 2154 } 2155 2156 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) 2157 { 2158 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp; 2159 bool is_linked = rtwdev->total_sta_assoc > 0; 2160 s32 cfo_avg_312; 2161 s32 dcfo_comp_val; 2162 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft; 2163 int sign; 2164 2165 if (!is_linked) { 2166 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", 2167 is_linked); 2168 return; 2169 } 2170 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); 2171 if (curr_cfo == 0) 2172 return; 2173 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); 2174 sign = curr_cfo > 0 ? 1 : -1; 2175 cfo_avg_312 = (curr_cfo << dcfo_comp_sft) / 5 + sign * dcfo_comp_val; 2176 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: avg_cfo=%d\n", cfo_avg_312); 2177 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 2178 cfo_avg_312 = -cfo_avg_312; 2179 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask, 2180 cfo_avg_312); 2181 } 2182 2183 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) 2184 { 2185 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_OPT, B_DCFO_OPT_EN, 1); 2186 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_WEIGHT, B_DCFO_WEIGHT_MSK, 8); 2187 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, B_AX_PWR_UL_CFO_MASK); 2188 } 2189 2190 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) 2191 { 2192 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2193 struct rtw89_efuse *efuse = &rtwdev->efuse; 2194 2195 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; 2196 cfo->crystal_cap = cfo->crystal_cap_default; 2197 cfo->def_x_cap = cfo->crystal_cap; 2198 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f); 2199 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1); 2200 cfo->is_adjust = false; 2201 cfo->divergence_lock_en = false; 2202 cfo->x_cap_ofst = 0; 2203 cfo->lock_cnt = 0; 2204 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; 2205 cfo->apply_compensation = false; 2206 cfo->residual_cfo_acc = 0; 2207 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", 2208 cfo->crystal_cap_default); 2209 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); 2210 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); 2211 rtw89_dcfo_comp_init(rtwdev); 2212 cfo->cfo_timer_ms = 2000; 2213 cfo->cfo_trig_by_timer_en = false; 2214 cfo->phy_cfo_trk_cnt = 0; 2215 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2216 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE; 2217 } 2218 2219 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, 2220 s32 curr_cfo) 2221 { 2222 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2223 s8 crystal_cap = cfo->crystal_cap; 2224 s32 cfo_abs = abs(curr_cfo); 2225 int sign; 2226 2227 if (!cfo->is_adjust) { 2228 if (cfo_abs > CFO_TRK_ENABLE_TH) 2229 cfo->is_adjust = true; 2230 } else { 2231 if (cfo_abs < CFO_TRK_STOP_TH) 2232 cfo->is_adjust = false; 2233 } 2234 if (!cfo->is_adjust) { 2235 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); 2236 return; 2237 } 2238 sign = curr_cfo > 0 ? 1 : -1; 2239 if (cfo_abs > CFO_TRK_STOP_TH_4) 2240 crystal_cap += 7 * sign; 2241 else if (cfo_abs > CFO_TRK_STOP_TH_3) 2242 crystal_cap += 5 * sign; 2243 else if (cfo_abs > CFO_TRK_STOP_TH_2) 2244 crystal_cap += 3 * sign; 2245 else if (cfo_abs > CFO_TRK_STOP_TH_1) 2246 crystal_cap += 1 * sign; 2247 else 2248 return; 2249 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); 2250 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2251 "X_cap{Curr,Default}={0x%x,0x%x}\n", 2252 cfo->crystal_cap, cfo->def_x_cap); 2253 } 2254 2255 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) 2256 { 2257 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2258 s32 cfo_khz_all = 0; 2259 s32 cfo_cnt_all = 0; 2260 s32 cfo_all_avg = 0; 2261 u8 i; 2262 2263 if (rtwdev->total_sta_assoc != 1) 2264 return 0; 2265 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); 2266 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2267 if (cfo->cfo_cnt[i] == 0) 2268 continue; 2269 cfo_khz_all += cfo->cfo_tail[i]; 2270 cfo_cnt_all += cfo->cfo_cnt[i]; 2271 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); 2272 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2273 } 2274 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2275 "CFO track for macid = %d\n", i); 2276 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2277 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", 2278 cfo_khz_all, cfo_cnt_all, cfo_all_avg); 2279 return cfo_all_avg; 2280 } 2281 2282 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) 2283 { 2284 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2285 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2286 s32 target_cfo = 0; 2287 s32 cfo_khz_all = 0; 2288 s32 cfo_khz_all_tp_wgt = 0; 2289 s32 cfo_avg = 0; 2290 s32 max_cfo_lb = BIT(31); 2291 s32 min_cfo_ub = GENMASK(30, 0); 2292 u16 cfo_cnt_all = 0; 2293 u8 active_entry_cnt = 0; 2294 u8 sta_cnt = 0; 2295 u32 tp_all = 0; 2296 u8 i; 2297 u8 cfo_tol = 0; 2298 2299 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); 2300 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { 2301 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); 2302 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2303 if (cfo->cfo_cnt[i] == 0) 2304 continue; 2305 cfo_khz_all += cfo->cfo_tail[i]; 2306 cfo_cnt_all += cfo->cfo_cnt[i]; 2307 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); 2308 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2309 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", 2310 cfo_khz_all, cfo_cnt_all, cfo_avg); 2311 target_cfo = cfo_avg; 2312 } 2313 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { 2314 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); 2315 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2316 if (cfo->cfo_cnt[i] == 0) 2317 continue; 2318 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2319 (s32)cfo->cfo_cnt[i]); 2320 cfo_khz_all += cfo->cfo_avg[i]; 2321 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2322 "Macid=%d, cfo_avg=%d\n", i, 2323 cfo->cfo_avg[i]); 2324 } 2325 sta_cnt = rtwdev->total_sta_assoc; 2326 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); 2327 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2328 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", 2329 cfo_khz_all, sta_cnt, cfo_avg); 2330 target_cfo = cfo_avg; 2331 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { 2332 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); 2333 cfo_tol = cfo->sta_cfo_tolerance; 2334 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2335 sta_cnt++; 2336 if (cfo->cfo_cnt[i] != 0) { 2337 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2338 (s32)cfo->cfo_cnt[i]); 2339 active_entry_cnt++; 2340 } else { 2341 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; 2342 } 2343 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); 2344 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); 2345 cfo_khz_all += cfo->cfo_avg[i]; 2346 /* need tp for each entry */ 2347 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2348 "[%d] cfo_avg=%d, tp=tbd\n", 2349 i, cfo->cfo_avg[i]); 2350 if (sta_cnt >= rtwdev->total_sta_assoc) 2351 break; 2352 } 2353 tp_all = stats->rx_throughput; /* need tp for each entry */ 2354 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); 2355 2356 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", 2357 sta_cnt); 2358 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", 2359 active_entry_cnt); 2360 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2361 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", 2362 cfo_khz_all_tp_wgt, cfo_avg); 2363 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", 2364 max_cfo_lb, min_cfo_ub); 2365 if (max_cfo_lb <= min_cfo_ub) { 2366 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2367 "cfo win_size=%d\n", 2368 min_cfo_ub - max_cfo_lb); 2369 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); 2370 } else { 2371 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2372 "No intersection of cfo tolerance windows\n"); 2373 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); 2374 } 2375 for (i = 0; i < CFO_TRACK_MAX_USER; i++) 2376 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2377 } 2378 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); 2379 return target_cfo; 2380 } 2381 2382 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) 2383 { 2384 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2385 2386 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); 2387 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); 2388 cfo->packet_count = 0; 2389 cfo->packet_count_pre = 0; 2390 cfo->cfo_avg_pre = 0; 2391 } 2392 2393 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) 2394 { 2395 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2396 s32 new_cfo = 0; 2397 bool x_cap_update = false; 2398 u8 pre_x_cap = cfo->crystal_cap; 2399 2400 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", 2401 rtwdev->total_sta_assoc); 2402 if (rtwdev->total_sta_assoc == 0) { 2403 rtw89_phy_cfo_reset(rtwdev); 2404 return; 2405 } 2406 if (cfo->packet_count == 0) { 2407 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); 2408 return; 2409 } 2410 if (cfo->packet_count == cfo->packet_count_pre) { 2411 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); 2412 return; 2413 } 2414 if (rtwdev->total_sta_assoc == 1) 2415 new_cfo = rtw89_phy_average_cfo_calc(rtwdev); 2416 else 2417 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); 2418 if (new_cfo == 0) { 2419 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); 2420 return; 2421 } 2422 if (cfo->divergence_lock_en) { 2423 cfo->lock_cnt++; 2424 if (cfo->lock_cnt > CFO_PERIOD_CNT) { 2425 cfo->divergence_lock_en = false; 2426 cfo->lock_cnt = 0; 2427 } else { 2428 rtw89_phy_cfo_reset(rtwdev); 2429 } 2430 return; 2431 } 2432 if (cfo->crystal_cap >= cfo->x_cap_ub || 2433 cfo->crystal_cap <= cfo->x_cap_lb) { 2434 cfo->divergence_lock_en = true; 2435 rtw89_phy_cfo_reset(rtwdev); 2436 return; 2437 } 2438 2439 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); 2440 cfo->cfo_avg_pre = new_cfo; 2441 x_cap_update = cfo->crystal_cap != pre_x_cap; 2442 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); 2443 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", 2444 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, 2445 cfo->x_cap_ofst); 2446 if (x_cap_update) { 2447 if (new_cfo > 0) 2448 new_cfo -= CFO_SW_COMP_FINE_TUNE; 2449 else 2450 new_cfo += CFO_SW_COMP_FINE_TUNE; 2451 } 2452 rtw89_dcfo_comp(rtwdev, new_cfo); 2453 rtw89_phy_cfo_statistics_reset(rtwdev); 2454 } 2455 2456 void rtw89_phy_cfo_track_work(struct work_struct *work) 2457 { 2458 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2459 cfo_track_work.work); 2460 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2461 2462 mutex_lock(&rtwdev->mutex); 2463 if (!cfo->cfo_trig_by_timer_en) 2464 goto out; 2465 rtw89_leave_ps_mode(rtwdev); 2466 rtw89_phy_cfo_dm(rtwdev); 2467 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2468 msecs_to_jiffies(cfo->cfo_timer_ms)); 2469 out: 2470 mutex_unlock(&rtwdev->mutex); 2471 } 2472 2473 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) 2474 { 2475 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2476 2477 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2478 msecs_to_jiffies(cfo->cfo_timer_ms)); 2479 } 2480 2481 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) 2482 { 2483 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2484 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2485 bool is_ul_ofdma = false, ofdma_acc_en = false; 2486 2487 if (stats->rx_tf_periodic > CFO_TF_CNT_TH) 2488 is_ul_ofdma = true; 2489 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE && 2490 is_ul_ofdma) 2491 ofdma_acc_en = true; 2492 2493 switch (cfo->phy_cfo_status) { 2494 case RTW89_PHY_DCFO_STATE_NORMAL: 2495 if (stats->tx_throughput >= CFO_TP_UPPER) { 2496 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; 2497 cfo->cfo_trig_by_timer_en = true; 2498 cfo->cfo_timer_ms = CFO_COMP_PERIOD; 2499 rtw89_phy_cfo_start_work(rtwdev); 2500 } 2501 break; 2502 case RTW89_PHY_DCFO_STATE_ENHANCE: 2503 if (stats->tx_throughput <= CFO_TP_LOWER) 2504 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2505 else if (ofdma_acc_en && 2506 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) 2507 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD; 2508 else 2509 cfo->phy_cfo_trk_cnt++; 2510 2511 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) { 2512 cfo->phy_cfo_trk_cnt = 0; 2513 cfo->cfo_trig_by_timer_en = false; 2514 } 2515 break; 2516 case RTW89_PHY_DCFO_STATE_HOLD: 2517 if (stats->tx_throughput <= CFO_TP_LOWER) { 2518 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2519 cfo->phy_cfo_trk_cnt = 0; 2520 cfo->cfo_trig_by_timer_en = false; 2521 } else { 2522 cfo->phy_cfo_trk_cnt++; 2523 } 2524 break; 2525 default: 2526 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2527 cfo->phy_cfo_trk_cnt = 0; 2528 break; 2529 } 2530 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2531 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", 2532 stats->tx_throughput, cfo->phy_cfo_status, 2533 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, 2534 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); 2535 if (cfo->cfo_trig_by_timer_en) 2536 return; 2537 rtw89_phy_cfo_dm(rtwdev); 2538 } 2539 2540 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 2541 struct rtw89_rx_phy_ppdu *phy_ppdu) 2542 { 2543 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2544 u8 macid = phy_ppdu->mac_id; 2545 2546 if (macid >= CFO_TRACK_MAX_USER) { 2547 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid); 2548 return; 2549 } 2550 2551 cfo->cfo_tail[macid] += cfo_val; 2552 cfo->cfo_cnt[macid]++; 2553 cfo->packet_count++; 2554 } 2555 2556 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) 2557 { 2558 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2559 int i; 2560 u8 th; 2561 2562 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 2563 th = rtw89_chip_get_thermal(rtwdev, i); 2564 if (th) 2565 ewma_thermal_add(&phystat->avg_thermal[i], th); 2566 2567 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 2568 "path(%d) thermal cur=%u avg=%ld", i, th, 2569 ewma_thermal_read(&phystat->avg_thermal[i])); 2570 } 2571 } 2572 2573 struct rtw89_phy_iter_rssi_data { 2574 struct rtw89_dev *rtwdev; 2575 struct rtw89_phy_ch_info *ch_info; 2576 bool rssi_changed; 2577 }; 2578 2579 static void rtw89_phy_stat_rssi_update_iter(void *data, 2580 struct ieee80211_sta *sta) 2581 { 2582 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2583 struct rtw89_phy_iter_rssi_data *rssi_data = 2584 (struct rtw89_phy_iter_rssi_data *)data; 2585 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info; 2586 unsigned long rssi_curr; 2587 2588 rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi); 2589 2590 if (rssi_curr < ch_info->rssi_min) { 2591 ch_info->rssi_min = rssi_curr; 2592 ch_info->rssi_min_macid = rtwsta->mac_id; 2593 } 2594 2595 if (rtwsta->prev_rssi == 0) { 2596 rtwsta->prev_rssi = rssi_curr; 2597 } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) { 2598 rtwsta->prev_rssi = rssi_curr; 2599 rssi_data->rssi_changed = true; 2600 } 2601 } 2602 2603 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) 2604 { 2605 struct rtw89_phy_iter_rssi_data rssi_data = {0}; 2606 2607 rssi_data.rtwdev = rtwdev; 2608 rssi_data.ch_info = &rtwdev->ch_info; 2609 rssi_data.ch_info->rssi_min = U8_MAX; 2610 ieee80211_iterate_stations_atomic(rtwdev->hw, 2611 rtw89_phy_stat_rssi_update_iter, 2612 &rssi_data); 2613 if (rssi_data.rssi_changed) 2614 rtw89_btc_ntfy_wl_sta(rtwdev); 2615 } 2616 2617 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) 2618 { 2619 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2620 int i; 2621 2622 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 2623 ewma_thermal_init(&phystat->avg_thermal[i]); 2624 2625 rtw89_phy_stat_thermal_update(rtwdev); 2626 2627 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 2628 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); 2629 } 2630 2631 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) 2632 { 2633 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2634 2635 rtw89_phy_stat_thermal_update(rtwdev); 2636 rtw89_phy_stat_rssi_update(rtwdev); 2637 2638 phystat->last_pkt_stat = phystat->cur_pkt_stat; 2639 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 2640 } 2641 2642 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us) 2643 { 2644 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2645 2646 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 2647 } 2648 2649 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) 2650 { 2651 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2652 2653 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 2654 } 2655 2656 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) 2657 { 2658 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2659 2660 env->ccx_manual_ctrl = false; 2661 env->ccx_ongoing = false; 2662 env->ccx_rac_lv = RTW89_RAC_RELEASE; 2663 env->ccx_rpt_stamp = 0; 2664 env->ccx_period = 0; 2665 env->ccx_unit_idx = RTW89_CCX_32_US; 2666 env->ccx_trigger_time = 0; 2667 env->ccx_edcca_opt_bw_idx = RTW89_CCX_EDCCA_BW20_0; 2668 2669 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1); 2670 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1); 2671 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 2672 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EDCCA_OPT_MSK, 2673 RTW89_CCX_EDCCA_BW20_0); 2674 } 2675 2676 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report, 2677 u16 score) 2678 { 2679 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2680 u32 numer = 0; 2681 u16 ret = 0; 2682 2683 numer = report * score + (env->ccx_period >> 1); 2684 if (env->ccx_period) 2685 ret = numer / env->ccx_period; 2686 2687 return ret >= score ? score - 1 : ret; 2688 } 2689 2690 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, 2691 u16 time_ms, u32 *period, 2692 u32 *unit_idx) 2693 { 2694 u32 idx; 2695 u8 quotient; 2696 2697 if (time_ms >= CCX_MAX_PERIOD) 2698 time_ms = CCX_MAX_PERIOD; 2699 2700 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; 2701 2702 if (quotient < 4) 2703 idx = RTW89_CCX_4_US; 2704 else if (quotient < 8) 2705 idx = RTW89_CCX_8_US; 2706 else if (quotient < 16) 2707 idx = RTW89_CCX_16_US; 2708 else 2709 idx = RTW89_CCX_32_US; 2710 2711 *unit_idx = idx; 2712 *period = (time_ms * MS_TO_4US_RATIO) >> idx; 2713 2714 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2715 "[Trigger Time] period:%d, unit_idx:%d\n", 2716 *period, *unit_idx); 2717 } 2718 2719 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev) 2720 { 2721 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2722 2723 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2724 "lv:(%d)->(0)\n", env->ccx_rac_lv); 2725 2726 env->ccx_ongoing = false; 2727 env->ccx_rac_lv = RTW89_RAC_RELEASE; 2728 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 2729 } 2730 2731 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, 2732 struct rtw89_ccx_para_info *para) 2733 { 2734 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2735 bool is_update = env->ifs_clm_app != para->ifs_clm_app; 2736 u8 i = 0; 2737 u16 *ifs_th_l = env->ifs_clm_th_l; 2738 u16 *ifs_th_h = env->ifs_clm_th_h; 2739 u32 ifs_th0_us = 0, ifs_th_times = 0; 2740 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; 2741 2742 if (!is_update) 2743 goto ifs_update_finished; 2744 2745 switch (para->ifs_clm_app) { 2746 case RTW89_IFS_CLM_INIT: 2747 case RTW89_IFS_CLM_BACKGROUND: 2748 case RTW89_IFS_CLM_ACS: 2749 case RTW89_IFS_CLM_DBG: 2750 case RTW89_IFS_CLM_DIG: 2751 case RTW89_IFS_CLM_TDMA_DIG: 2752 ifs_th0_us = IFS_CLM_TH0_UPPER; 2753 ifs_th_times = IFS_CLM_TH_MUL; 2754 break; 2755 case RTW89_IFS_CLM_DBG_MANUAL: 2756 ifs_th0_us = para->ifs_clm_manual_th0; 2757 ifs_th_times = para->ifs_clm_manual_th_times; 2758 break; 2759 default: 2760 break; 2761 } 2762 2763 /* Set sampling threshold for 4 different regions, unit in idx_cnt. 2764 * low[i] = high[i-1] + 1 2765 * high[i] = high[i-1] * ifs_th_times 2766 */ 2767 ifs_th_l[IFS_CLM_TH_START_IDX] = 0; 2768 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; 2769 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, 2770 ifs_th0_us); 2771 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { 2772 ifs_th_l[i] = ifs_th_h[i - 1] + 1; 2773 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; 2774 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]); 2775 } 2776 2777 ifs_update_finished: 2778 if (!is_update) 2779 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2780 "No need to update IFS_TH\n"); 2781 2782 return is_update; 2783 } 2784 2785 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) 2786 { 2787 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2788 u8 i = 0; 2789 2790 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_LOW_MSK, 2791 env->ifs_clm_th_l[0]); 2792 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_LOW_MSK, 2793 env->ifs_clm_th_l[1]); 2794 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_LOW_MSK, 2795 env->ifs_clm_th_l[2]); 2796 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_LOW_MSK, 2797 env->ifs_clm_th_l[3]); 2798 2799 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_HIGH_MSK, 2800 env->ifs_clm_th_h[0]); 2801 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_HIGH_MSK, 2802 env->ifs_clm_th_h[1]); 2803 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_HIGH_MSK, 2804 env->ifs_clm_th_h[2]); 2805 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_HIGH_MSK, 2806 env->ifs_clm_th_h[3]); 2807 2808 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 2809 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2810 "Update IFS_T%d_th{low, high} : {%d, %d}\n", 2811 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 2812 } 2813 2814 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) 2815 { 2816 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2817 struct rtw89_ccx_para_info para = {0}; 2818 2819 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 2820 env->ifs_clm_mntr_time = 0; 2821 2822 para.ifs_clm_app = RTW89_IFS_CLM_INIT; 2823 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) 2824 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 2825 2826 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COLLECT_EN, 2827 true); 2828 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_EN_MSK, true); 2829 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_EN_MSK, true); 2830 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_EN_MSK, true); 2831 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_EN_MSK, true); 2832 } 2833 2834 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, 2835 enum rtw89_env_racing_lv level) 2836 { 2837 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2838 int ret = 0; 2839 2840 if (level >= RTW89_RAC_MAX_NUM) { 2841 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2842 "[WARNING] Wrong LV=%d\n", level); 2843 return -EINVAL; 2844 } 2845 2846 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2847 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, 2848 env->ccx_rac_lv, level); 2849 2850 if (env->ccx_ongoing) { 2851 if (level <= env->ccx_rac_lv) 2852 ret = -EINVAL; 2853 else 2854 env->ccx_ongoing = false; 2855 } 2856 2857 if (ret == 0) 2858 env->ccx_rac_lv = level; 2859 2860 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", 2861 !ret); 2862 2863 return ret; 2864 } 2865 2866 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) 2867 { 2868 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2869 2870 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 0); 2871 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 0); 2872 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1); 2873 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 2874 2875 env->ccx_rpt_stamp++; 2876 env->ccx_ongoing = true; 2877 } 2878 2879 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) 2880 { 2881 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2882 u8 i = 0; 2883 u32 res = 0; 2884 2885 env->ifs_clm_tx_ratio = 2886 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT); 2887 env->ifs_clm_edcca_excl_cca_ratio = 2888 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca, 2889 PERCENT); 2890 env->ifs_clm_cck_fa_ratio = 2891 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT); 2892 env->ifs_clm_ofdm_fa_ratio = 2893 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT); 2894 env->ifs_clm_cck_cca_excl_fa_ratio = 2895 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa, 2896 PERCENT); 2897 env->ifs_clm_ofdm_cca_excl_fa_ratio = 2898 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa, 2899 PERCENT); 2900 env->ifs_clm_cck_fa_permil = 2901 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL); 2902 env->ifs_clm_ofdm_fa_permil = 2903 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL); 2904 2905 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { 2906 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { 2907 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; 2908 } else { 2909 env->ifs_clm_ifs_avg[i] = 2910 rtw89_phy_ccx_idx_to_us(rtwdev, 2911 env->ifs_clm_avg[i]); 2912 } 2913 2914 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]); 2915 res += env->ifs_clm_his[i] >> 1; 2916 if (env->ifs_clm_his[i]) 2917 res /= env->ifs_clm_his[i]; 2918 else 2919 res = 0; 2920 env->ifs_clm_cca_avg[i] = res; 2921 } 2922 2923 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2924 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", 2925 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); 2926 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2927 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", 2928 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); 2929 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2930 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", 2931 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); 2932 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2933 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", 2934 env->ifs_clm_cck_cca_excl_fa_ratio, 2935 env->ifs_clm_ofdm_cca_excl_fa_ratio); 2936 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2937 "Time:[his, ifs_avg(us), cca_avg(us)]\n"); 2938 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 2939 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 2940 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 2941 env->ifs_clm_cca_avg[i]); 2942 } 2943 2944 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) 2945 { 2946 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2947 u8 i = 0; 2948 2949 if (rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_DONE_MSK) == 0) { 2950 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2951 "Get IFS_CLM report Fail\n"); 2952 return false; 2953 } 2954 2955 env->ifs_clm_tx = 2956 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 2957 B_IFS_CLM_TX_CNT_MSK); 2958 env->ifs_clm_edcca_excl_cca = 2959 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 2960 B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK); 2961 env->ifs_clm_cckcca_excl_fa = 2962 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 2963 B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK); 2964 env->ifs_clm_ofdmcca_excl_fa = 2965 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 2966 B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK); 2967 env->ifs_clm_cckfa = 2968 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 2969 B_IFS_CLM_CCK_FA_MSK); 2970 env->ifs_clm_ofdmfa = 2971 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 2972 B_IFS_CLM_OFDM_FA_MSK); 2973 2974 env->ifs_clm_his[0] = 2975 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T1_HIS_MSK); 2976 env->ifs_clm_his[1] = 2977 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T2_HIS_MSK); 2978 env->ifs_clm_his[2] = 2979 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T3_HIS_MSK); 2980 env->ifs_clm_his[3] = 2981 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T4_HIS_MSK); 2982 2983 env->ifs_clm_avg[0] = 2984 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T1_AVG_MSK); 2985 env->ifs_clm_avg[1] = 2986 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T2_AVG_MSK); 2987 env->ifs_clm_avg[2] = 2988 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T3_AVG_MSK); 2989 env->ifs_clm_avg[3] = 2990 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T4_AVG_MSK); 2991 2992 env->ifs_clm_cca[0] = 2993 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T1_CCA_MSK); 2994 env->ifs_clm_cca[1] = 2995 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T2_CCA_MSK); 2996 env->ifs_clm_cca[2] = 2997 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T3_CCA_MSK); 2998 env->ifs_clm_cca[3] = 2999 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T4_CCA_MSK); 3000 3001 env->ifs_clm_total_ifs = 3002 rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_TOTAL_CNT_MSK); 3003 3004 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", 3005 env->ifs_clm_total_ifs); 3006 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3007 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", 3008 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); 3009 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3010 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", 3011 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); 3012 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3013 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", 3014 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); 3015 3016 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); 3017 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3018 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3019 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], 3020 env->ifs_clm_avg[i], env->ifs_clm_cca[i]); 3021 3022 rtw89_phy_ifs_clm_get_utility(rtwdev); 3023 3024 return true; 3025 } 3026 3027 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 3028 struct rtw89_ccx_para_info *para) 3029 { 3030 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3031 u32 period = 0; 3032 u32 unit_idx = 0; 3033 3034 if (para->mntr_time == 0) { 3035 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3036 "[WARN] MNTR_TIME is 0\n"); 3037 return -EINVAL; 3038 } 3039 3040 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv)) 3041 return -EINVAL; 3042 3043 if (para->mntr_time != env->ifs_clm_mntr_time) { 3044 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 3045 &period, &unit_idx); 3046 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 3047 B_IFS_CLM_PERIOD_MSK, period); 3048 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 3049 B_IFS_CLM_COUNTER_UNIT_MSK, unit_idx); 3050 3051 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3052 "Update IFS-CLM time ((%d)) -> ((%d))\n", 3053 env->ifs_clm_mntr_time, para->mntr_time); 3054 3055 env->ifs_clm_mntr_time = para->mntr_time; 3056 env->ccx_period = (u16)period; 3057 env->ccx_unit_idx = (u8)unit_idx; 3058 } 3059 3060 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) { 3061 env->ifs_clm_app = para->ifs_clm_app; 3062 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 3063 } 3064 3065 return 0; 3066 } 3067 3068 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) 3069 { 3070 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3071 struct rtw89_ccx_para_info para = {0}; 3072 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3073 3074 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3075 if (env->ccx_manual_ctrl) { 3076 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3077 "CCX in manual ctrl\n"); 3078 return; 3079 } 3080 3081 /* only ifs_clm for now */ 3082 if (rtw89_phy_ifs_clm_get_result(rtwdev)) 3083 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3084 3085 rtw89_phy_ccx_racing_release(rtwdev); 3086 para.mntr_time = 1900; 3087 para.rac_lv = RTW89_RAC_LV_1; 3088 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3089 3090 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0) 3091 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3092 if (chk_result) 3093 rtw89_phy_ccx_trigger(rtwdev); 3094 3095 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3096 "get_result=0x%x, chk_result:0x%x\n", 3097 env->ccx_watchdog_result, chk_result); 3098 } 3099 3100 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page) 3101 { 3102 if (*ie_page > RTW89_PHYSTS_BITMAP_NUM || 3103 *ie_page == RTW89_RSVD_9) 3104 return false; 3105 else if (*ie_page > RTW89_RSVD_9) 3106 *ie_page -= 1; 3107 3108 return true; 3109 } 3110 3111 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) 3112 { 3113 static const u8 ie_page_shift = 2; 3114 3115 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); 3116 } 3117 3118 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, 3119 enum rtw89_phy_status_bitmap ie_page) 3120 { 3121 u32 addr; 3122 3123 if (!rtw89_physts_ie_page_valid(&ie_page)) 3124 return 0; 3125 3126 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3127 3128 return rtw89_phy_read32(rtwdev, addr); 3129 } 3130 3131 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, 3132 enum rtw89_phy_status_bitmap ie_page, 3133 u32 val) 3134 { 3135 const struct rtw89_chip_info *chip = rtwdev->chip; 3136 u32 addr; 3137 3138 if (!rtw89_physts_ie_page_valid(&ie_page)) 3139 return; 3140 3141 if (chip->chip_id == RTL8852A) 3142 val &= B_PHY_STS_BITMAP_MSK_52A; 3143 3144 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3145 rtw89_phy_write32(rtwdev, addr, val); 3146 } 3147 3148 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev, 3149 enum rtw89_phy_status_bitmap bitmap, 3150 enum rtw89_phy_status_ie_type ie, 3151 bool enable) 3152 { 3153 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap); 3154 3155 if (enable) 3156 val |= BIT(ie); 3157 else 3158 val &= ~BIT(ie); 3159 3160 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val); 3161 } 3162 3163 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, 3164 bool enable, 3165 enum rtw89_phy_idx phy_idx) 3166 { 3167 if (enable) { 3168 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3169 B_STS_DIS_TRIG_BY_FAIL); 3170 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3171 B_STS_DIS_TRIG_BY_BRK); 3172 } else { 3173 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3174 B_STS_DIS_TRIG_BY_FAIL); 3175 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3176 B_STS_DIS_TRIG_BY_BRK); 3177 } 3178 } 3179 3180 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev) 3181 { 3182 u8 i; 3183 3184 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0); 3185 3186 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { 3187 if (i >= RTW89_CCK_PKT) 3188 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3189 RTW89_PHYSTS_IE09_FTR_0, 3190 true); 3191 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) || 3192 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT)) 3193 continue; 3194 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3195 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A, 3196 true); 3197 } 3198 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT, 3199 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3200 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT, 3201 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3202 3203 /* force IE01 for channel index, only channel field is valid */ 3204 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT, 3205 RTW89_PHYSTS_IE01_CMN_OFDM, true); 3206 } 3207 3208 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) 3209 { 3210 const struct rtw89_chip_info *chip = rtwdev->chip; 3211 struct rtw89_dig_info *dig = &rtwdev->dig; 3212 const struct rtw89_phy_dig_gain_cfg *cfg; 3213 const char *msg; 3214 u8 i; 3215 s8 gain_base; 3216 s8 *gain_arr; 3217 u32 tmp; 3218 3219 switch (type) { 3220 case RTW89_DIG_GAIN_LNA_G: 3221 gain_arr = dig->lna_gain_g; 3222 gain_base = LNA0_GAIN; 3223 cfg = chip->dig_table->cfg_lna_g; 3224 msg = "lna_gain_g"; 3225 break; 3226 case RTW89_DIG_GAIN_TIA_G: 3227 gain_arr = dig->tia_gain_g; 3228 gain_base = TIA0_GAIN_G; 3229 cfg = chip->dig_table->cfg_tia_g; 3230 msg = "tia_gain_g"; 3231 break; 3232 case RTW89_DIG_GAIN_LNA_A: 3233 gain_arr = dig->lna_gain_a; 3234 gain_base = LNA0_GAIN; 3235 cfg = chip->dig_table->cfg_lna_a; 3236 msg = "lna_gain_a"; 3237 break; 3238 case RTW89_DIG_GAIN_TIA_A: 3239 gain_arr = dig->tia_gain_a; 3240 gain_base = TIA0_GAIN_A; 3241 cfg = chip->dig_table->cfg_tia_a; 3242 msg = "tia_gain_a"; 3243 break; 3244 default: 3245 return; 3246 } 3247 3248 for (i = 0; i < cfg->size; i++) { 3249 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr, 3250 cfg->table[i].mask); 3251 tmp >>= DIG_GAIN_SHIFT; 3252 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; 3253 gain_base += DIG_GAIN; 3254 3255 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", 3256 msg, i, gain_arr[i]); 3257 } 3258 } 3259 3260 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev) 3261 { 3262 struct rtw89_dig_info *dig = &rtwdev->dig; 3263 u32 tmp; 3264 u8 i; 3265 3266 if (!rtwdev->hal.support_igi) 3267 return; 3268 3269 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW, 3270 B_PATH0_IB_PKPW_MSK); 3271 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); 3272 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK, 3273 B_PATH0_IB_PBK_MSK); 3274 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", 3275 dig->ib_pkpwr, dig->ib_pbk); 3276 3277 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) 3278 rtw89_phy_dig_read_gain_table(rtwdev, i); 3279 } 3280 3281 static const u8 rssi_nolink = 22; 3282 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; 3283 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; 3284 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; 3285 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; 3286 3287 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev) 3288 { 3289 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 3290 struct rtw89_dig_info *dig = &rtwdev->dig; 3291 bool is_linked = rtwdev->total_sta_assoc > 0; 3292 3293 if (is_linked) { 3294 dig->igi_rssi = ch_info->rssi_min >> 1; 3295 } else { 3296 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); 3297 dig->igi_rssi = rssi_nolink; 3298 } 3299 } 3300 3301 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev) 3302 { 3303 struct rtw89_dig_info *dig = &rtwdev->dig; 3304 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3305 bool is_linked = rtwdev->total_sta_assoc > 0; 3306 const u16 *fa_th_src = NULL; 3307 3308 switch (chan->band_type) { 3309 case RTW89_BAND_2G: 3310 dig->lna_gain = dig->lna_gain_g; 3311 dig->tia_gain = dig->tia_gain_g; 3312 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; 3313 dig->force_gaincode_idx_en = false; 3314 dig->dyn_pd_th_en = true; 3315 break; 3316 case RTW89_BAND_5G: 3317 default: 3318 dig->lna_gain = dig->lna_gain_a; 3319 dig->tia_gain = dig->tia_gain_a; 3320 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; 3321 dig->force_gaincode_idx_en = true; 3322 dig->dyn_pd_th_en = true; 3323 break; 3324 } 3325 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); 3326 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); 3327 } 3328 3329 static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20; 3330 static const u8 igi_max_performance_mode = 0x5a; 3331 static const u8 dynamic_pd_threshold_max; 3332 3333 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev) 3334 { 3335 struct rtw89_dig_info *dig = &rtwdev->dig; 3336 3337 dig->cur_gaincode.lna_idx = LNA_IDX_MAX; 3338 dig->cur_gaincode.tia_idx = TIA_IDX_MAX; 3339 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; 3340 dig->force_gaincode.lna_idx = LNA_IDX_MAX; 3341 dig->force_gaincode.tia_idx = TIA_IDX_MAX; 3342 dig->force_gaincode.rxb_idx = RXB_IDX_MAX; 3343 3344 dig->dyn_igi_max = igi_max_performance_mode; 3345 dig->dyn_igi_min = dynamic_igi_min; 3346 dig->dyn_pd_th_max = dynamic_pd_threshold_max; 3347 dig->pd_low_th_ofst = pd_low_th_offset; 3348 dig->is_linked_pre = false; 3349 } 3350 3351 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) 3352 { 3353 rtw89_phy_dig_update_gain_para(rtwdev); 3354 rtw89_phy_dig_reset(rtwdev); 3355 } 3356 3357 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3358 { 3359 struct rtw89_dig_info *dig = &rtwdev->dig; 3360 u8 lna_idx; 3361 3362 if (rssi < dig->igi_rssi_th[0]) 3363 lna_idx = RTW89_DIG_GAIN_LNA_IDX6; 3364 else if (rssi < dig->igi_rssi_th[1]) 3365 lna_idx = RTW89_DIG_GAIN_LNA_IDX5; 3366 else if (rssi < dig->igi_rssi_th[2]) 3367 lna_idx = RTW89_DIG_GAIN_LNA_IDX4; 3368 else if (rssi < dig->igi_rssi_th[3]) 3369 lna_idx = RTW89_DIG_GAIN_LNA_IDX3; 3370 else if (rssi < dig->igi_rssi_th[4]) 3371 lna_idx = RTW89_DIG_GAIN_LNA_IDX2; 3372 else 3373 lna_idx = RTW89_DIG_GAIN_LNA_IDX1; 3374 3375 return lna_idx; 3376 } 3377 3378 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3379 { 3380 struct rtw89_dig_info *dig = &rtwdev->dig; 3381 u8 tia_idx; 3382 3383 if (rssi < dig->igi_rssi_th[0]) 3384 tia_idx = RTW89_DIG_GAIN_TIA_IDX1; 3385 else 3386 tia_idx = RTW89_DIG_GAIN_TIA_IDX0; 3387 3388 return tia_idx; 3389 } 3390 3391 #define IB_PBK_BASE 110 3392 #define WB_RSSI_BASE 10 3393 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3394 struct rtw89_agc_gaincode_set *set) 3395 { 3396 struct rtw89_dig_info *dig = &rtwdev->dig; 3397 s8 lna_gain = dig->lna_gain[set->lna_idx]; 3398 s8 tia_gain = dig->tia_gain[set->tia_idx]; 3399 s32 wb_rssi = rssi + lna_gain + tia_gain; 3400 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; 3401 u8 rxb_idx; 3402 3403 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; 3404 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); 3405 3406 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", 3407 wb_rssi, rxb_idx_tmp); 3408 3409 return rxb_idx; 3410 } 3411 3412 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3413 struct rtw89_agc_gaincode_set *set) 3414 { 3415 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi); 3416 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi); 3417 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set); 3418 3419 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3420 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", 3421 rssi, set->lna_idx, set->tia_idx, set->rxb_idx); 3422 } 3423 3424 #define IGI_OFFSET_MAX 25 3425 #define IGI_OFFSET_MUL 2 3426 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev) 3427 { 3428 struct rtw89_dig_info *dig = &rtwdev->dig; 3429 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3430 enum rtw89_dig_noisy_level noisy_lv; 3431 u8 igi_offset = dig->fa_rssi_ofst; 3432 u16 fa_ratio = 0; 3433 3434 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; 3435 3436 if (fa_ratio < dig->fa_th[0]) 3437 noisy_lv = RTW89_DIG_NOISY_LEVEL0; 3438 else if (fa_ratio < dig->fa_th[1]) 3439 noisy_lv = RTW89_DIG_NOISY_LEVEL1; 3440 else if (fa_ratio < dig->fa_th[2]) 3441 noisy_lv = RTW89_DIG_NOISY_LEVEL2; 3442 else if (fa_ratio < dig->fa_th[3]) 3443 noisy_lv = RTW89_DIG_NOISY_LEVEL3; 3444 else 3445 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; 3446 3447 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) 3448 igi_offset = 0; 3449 else 3450 igi_offset += noisy_lv * IGI_OFFSET_MUL; 3451 3452 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); 3453 dig->fa_rssi_ofst = igi_offset; 3454 3455 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3456 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", 3457 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); 3458 3459 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3460 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", 3461 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, 3462 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, 3463 noisy_lv, igi_offset); 3464 } 3465 3466 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx) 3467 { 3468 rtw89_phy_write32_mask(rtwdev, R_PATH0_LNA_INIT, 3469 B_PATH0_LNA_INIT_IDX_MSK, lna_idx); 3470 rtw89_phy_write32_mask(rtwdev, R_PATH1_LNA_INIT, 3471 B_PATH1_LNA_INIT_IDX_MSK, lna_idx); 3472 } 3473 3474 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx) 3475 { 3476 rtw89_phy_write32_mask(rtwdev, R_PATH0_TIA_INIT, 3477 B_PATH0_TIA_INIT_IDX_MSK, tia_idx); 3478 rtw89_phy_write32_mask(rtwdev, R_PATH1_TIA_INIT, 3479 B_PATH1_TIA_INIT_IDX_MSK, tia_idx); 3480 } 3481 3482 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx) 3483 { 3484 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXB_INIT, 3485 B_PATH0_RXB_INIT_IDX_MSK, rxb_idx); 3486 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXB_INIT, 3487 B_PATH1_RXB_INIT_IDX_MSK, rxb_idx); 3488 } 3489 3490 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, 3491 const struct rtw89_agc_gaincode_set set) 3492 { 3493 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx); 3494 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx); 3495 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx); 3496 3497 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", 3498 set.lna_idx, set.tia_idx, set.rxb_idx); 3499 } 3500 3501 static const struct rtw89_reg_def sdagc_config[4] = { 3502 {R_PATH0_P20_FOLLOW_BY_PAGCUGC, B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 3503 {R_PATH0_S20_FOLLOW_BY_PAGCUGC, B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 3504 {R_PATH1_P20_FOLLOW_BY_PAGCUGC, B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 3505 {R_PATH1_S20_FOLLOW_BY_PAGCUGC, B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 3506 }; 3507 3508 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, 3509 bool enable) 3510 { 3511 u8 i = 0; 3512 3513 for (i = 0; i < ARRAY_SIZE(sdagc_config); i++) 3514 rtw89_phy_write32_mask(rtwdev, sdagc_config[i].addr, 3515 sdagc_config[i].mask, enable); 3516 3517 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); 3518 } 3519 3520 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev) 3521 { 3522 struct rtw89_dig_info *dig = &rtwdev->dig; 3523 3524 if (!rtwdev->hal.support_igi) 3525 return; 3526 3527 if (dig->force_gaincode_idx_en) { 3528 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 3529 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3530 "Force gaincode index enabled.\n"); 3531 } else { 3532 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi, 3533 &dig->cur_gaincode); 3534 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode); 3535 } 3536 } 3537 3538 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, 3539 bool enable) 3540 { 3541 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3542 enum rtw89_bandwidth cbw = chan->band_width; 3543 struct rtw89_dig_info *dig = &rtwdev->dig; 3544 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; 3545 u8 ofdm_cca_th; 3546 s8 cck_cca_th; 3547 u32 pd_val = 0; 3548 3549 under_region += PD_TH_SB_FLTR_CMP_VAL; 3550 3551 switch (cbw) { 3552 case RTW89_CHANNEL_WIDTH_40: 3553 under_region += PD_TH_BW40_CMP_VAL; 3554 break; 3555 case RTW89_CHANNEL_WIDTH_80: 3556 under_region += PD_TH_BW80_CMP_VAL; 3557 break; 3558 case RTW89_CHANNEL_WIDTH_160: 3559 under_region += PD_TH_BW160_CMP_VAL; 3560 break; 3561 case RTW89_CHANNEL_WIDTH_20: 3562 fallthrough; 3563 default: 3564 under_region += PD_TH_BW20_CMP_VAL; 3565 break; 3566 } 3567 3568 dig->dyn_pd_th_max = dig->igi_rssi; 3569 3570 final_rssi = min_t(u8, rssi, dig->igi_rssi); 3571 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, 3572 PD_TH_MAX_RSSI + under_region); 3573 3574 if (enable) { 3575 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1; 3576 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3577 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n", 3578 final_rssi, ofdm_cca_th, under_region, pd_val); 3579 } else { 3580 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3581 "Dynamic PD th disabled, Set PD_low_bd=0\n"); 3582 } 3583 3584 rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, B_SEG0R_PD_LOWER_BOUND_MSK, 3585 pd_val); 3586 rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, 3587 B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, enable); 3588 3589 if (!rtwdev->hal.support_cckpd) 3590 return; 3591 3592 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI); 3593 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX); 3594 3595 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3596 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n", 3597 final_rssi, cck_cca_th, under_region, pd_val); 3598 3599 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_EN_V1, 3600 B_BMODE_PDTH_LIMIT_EN_MSK_V1, enable); 3601 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_V1, 3602 B_BMODE_PDTH_LOWER_BOUND_MSK_V1, pd_val); 3603 } 3604 3605 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) 3606 { 3607 struct rtw89_dig_info *dig = &rtwdev->dig; 3608 3609 dig->bypass_dig = false; 3610 rtw89_phy_dig_para_reset(rtwdev); 3611 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 3612 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false); 3613 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 3614 rtw89_phy_dig_update_para(rtwdev); 3615 } 3616 3617 #define IGI_RSSI_MIN 10 3618 void rtw89_phy_dig(struct rtw89_dev *rtwdev) 3619 { 3620 struct rtw89_dig_info *dig = &rtwdev->dig; 3621 bool is_linked = rtwdev->total_sta_assoc > 0; 3622 3623 if (unlikely(dig->bypass_dig)) { 3624 dig->bypass_dig = false; 3625 return; 3626 } 3627 3628 if (!dig->is_linked_pre && is_linked) { 3629 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); 3630 rtw89_phy_dig_update_para(rtwdev); 3631 } else if (dig->is_linked_pre && !is_linked) { 3632 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); 3633 rtw89_phy_dig_update_para(rtwdev); 3634 } 3635 dig->is_linked_pre = is_linked; 3636 3637 rtw89_phy_dig_igi_offset_by_env(rtwdev); 3638 rtw89_phy_dig_update_rssi_info(rtwdev); 3639 3640 dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ? 3641 dig->igi_rssi - IGI_RSSI_MIN : 0; 3642 dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX; 3643 dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst; 3644 3645 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, 3646 dig->dyn_igi_max); 3647 3648 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3649 "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n", 3650 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, 3651 dig->igi_fa_rssi); 3652 3653 rtw89_phy_dig_config_igi(rtwdev); 3654 3655 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en); 3656 3657 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) 3658 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true); 3659 else 3660 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 3661 } 3662 3663 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) 3664 { 3665 rtw89_phy_ccx_top_setting_init(rtwdev); 3666 rtw89_phy_ifs_clm_setting_init(rtwdev); 3667 } 3668 3669 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 3670 { 3671 const struct rtw89_chip_info *chip = rtwdev->chip; 3672 3673 rtw89_phy_stat_init(rtwdev); 3674 3675 rtw89_chip_bb_sethw(rtwdev); 3676 3677 rtw89_phy_env_monitor_init(rtwdev); 3678 rtw89_physts_parsing_init(rtwdev); 3679 rtw89_phy_dig_init(rtwdev); 3680 rtw89_phy_cfo_init(rtwdev); 3681 3682 rtw89_phy_init_rf_nctl(rtwdev); 3683 rtw89_chip_rfk_init(rtwdev); 3684 rtw89_load_txpwr_table(rtwdev, chip->byr_table); 3685 rtw89_chip_set_txpwr_ctrl(rtwdev); 3686 rtw89_chip_power_trim(rtwdev); 3687 rtw89_chip_cfg_txrx_path(rtwdev); 3688 } 3689 3690 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 3691 { 3692 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 3693 u8 bss_color; 3694 3695 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 3696 return; 3697 3698 bss_color = vif->bss_conf.he_bss_color.color; 3699 3700 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0, 0x1, 3701 phy_idx); 3702 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_TGT, bss_color, 3703 phy_idx); 3704 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_STAID, 3705 vif->cfg.aid, phy_idx); 3706 } 3707 3708 static void 3709 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3710 { 3711 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); 3712 } 3713 3714 static void 3715 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3716 { 3717 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 3718 } 3719 3720 static void 3721 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3722 { 3723 rtw89_phy_write32_set(rtwdev, def->addr, def->mask); 3724 } 3725 3726 static void 3727 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3728 { 3729 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); 3730 } 3731 3732 static void 3733 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3734 { 3735 udelay(def->data); 3736 } 3737 3738 static void 3739 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { 3740 [RTW89_RFK_F_WRF] = _rfk_write_rf, 3741 [RTW89_RFK_F_WM] = _rfk_write32_mask, 3742 [RTW89_RFK_F_WS] = _rfk_write32_set, 3743 [RTW89_RFK_F_WC] = _rfk_write32_clr, 3744 [RTW89_RFK_F_DELAY] = _rfk_delay, 3745 }; 3746 3747 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 3748 3749 void 3750 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) 3751 { 3752 const struct rtw89_reg5_def *p = tbl->defs; 3753 const struct rtw89_reg5_def *end = tbl->defs + tbl->size; 3754 3755 for (; p < end; p++) 3756 _rfk_handler[p->flag](rtwdev, p); 3757 } 3758 EXPORT_SYMBOL(rtw89_rfk_parser); 3759 3760 #define RTW89_TSSI_FAST_MODE_NUM 4 3761 3762 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = { 3763 {0xD934, 0xff0000}, 3764 {0xD934, 0xff000000}, 3765 {0xD938, 0xff}, 3766 {0xD934, 0xff00}, 3767 }; 3768 3769 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = { 3770 {0xD930, 0xff0000}, 3771 {0xD930, 0xff000000}, 3772 {0xD934, 0xff}, 3773 {0xD930, 0xff00}, 3774 }; 3775 3776 static 3777 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev, 3778 enum rtw89_mac_idx mac_idx, 3779 enum rtw89_tssi_bandedge_cfg bandedge_cfg, 3780 u32 val) 3781 { 3782 const struct rtw89_reg_def *regs; 3783 u32 reg; 3784 int i; 3785 3786 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 3787 regs = rtw89_tssi_fastmode_regs_flat; 3788 else 3789 regs = rtw89_tssi_fastmode_regs_level; 3790 3791 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) { 3792 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 3793 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); 3794 } 3795 } 3796 3797 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = { 3798 {0xD91C, 0xff000000}, 3799 {0xD920, 0xff}, 3800 {0xD920, 0xff00}, 3801 {0xD920, 0xff0000}, 3802 {0xD920, 0xff000000}, 3803 {0xD924, 0xff}, 3804 {0xD924, 0xff00}, 3805 {0xD914, 0xff000000}, 3806 {0xD918, 0xff}, 3807 {0xD918, 0xff00}, 3808 {0xD918, 0xff0000}, 3809 {0xD918, 0xff000000}, 3810 {0xD91C, 0xff}, 3811 {0xD91C, 0xff00}, 3812 {0xD91C, 0xff0000}, 3813 }; 3814 3815 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = { 3816 {0xD910, 0xff}, 3817 {0xD910, 0xff00}, 3818 {0xD910, 0xff0000}, 3819 {0xD910, 0xff000000}, 3820 {0xD914, 0xff}, 3821 {0xD914, 0xff00}, 3822 {0xD914, 0xff0000}, 3823 {0xD908, 0xff}, 3824 {0xD908, 0xff00}, 3825 {0xD908, 0xff0000}, 3826 {0xD908, 0xff000000}, 3827 {0xD90C, 0xff}, 3828 {0xD90C, 0xff00}, 3829 {0xD90C, 0xff0000}, 3830 {0xD90C, 0xff000000}, 3831 }; 3832 3833 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 3834 enum rtw89_mac_idx mac_idx, 3835 enum rtw89_tssi_bandedge_cfg bandedge_cfg) 3836 { 3837 const struct rtw89_chip_info *chip = rtwdev->chip; 3838 const struct rtw89_reg_def *regs; 3839 const u32 *data; 3840 u32 reg; 3841 int i; 3842 3843 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM) 3844 return; 3845 3846 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 3847 regs = rtw89_tssi_bandedge_regs_flat; 3848 else 3849 regs = rtw89_tssi_bandedge_regs_level; 3850 3851 data = chip->tssi_dbw_table->data[bandedge_cfg]; 3852 3853 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) { 3854 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 3855 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); 3856 } 3857 3858 reg = rtw89_mac_reg_by_idx(R_AX_BANDEDGE_CFG, mac_idx); 3859 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); 3860 3861 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg, 3862 data[RTW89_TSSI_SBW20]); 3863 } 3864 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg); 3865