1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2020  Realtek Corporation
3  */
4 
5 #ifndef __RTW89_PCI_H__
6 #define __RTW89_PCI_H__
7 
8 #include "txrx.h"
9 
10 #define MDIO_PG0_G1 0
11 #define MDIO_PG1_G1 1
12 #define MDIO_PG0_G2 2
13 #define MDIO_PG1_G2 3
14 #define RAC_CTRL_PPR			0x00
15 #define RAC_ANA0A			0x0A
16 #define B_BAC_EQ_SEL			BIT(5)
17 #define RAC_ANA0C			0x0C
18 #define B_PCIE_BIT_PSAVE		BIT(15)
19 #define RAC_ANA10			0x10
20 #define B_PCIE_BIT_PINOUT_DIS		BIT(3)
21 #define RAC_REG_REV2			0x1B
22 #define BAC_CMU_EN_DLY_MASK		GENMASK(15, 12)
23 #define PCIE_DPHY_DLY_25US		0x1
24 #define RAC_ANA19			0x19
25 #define B_PCIE_BIT_RD_SEL		BIT(2)
26 #define RAC_REG_FLD_0			0x1D
27 #define BAC_AUTOK_N_MASK		GENMASK(3, 2)
28 #define PCIE_AUTOK_4			0x3
29 #define RAC_ANA1F			0x1F
30 #define RAC_ANA24			0x24
31 #define B_AX_DEGLITCH			GENMASK(11, 8)
32 #define RAC_ANA26			0x26
33 #define B_AX_RXEN			GENMASK(15, 14)
34 #define RAC_CTRL_PPR_V1			0x30
35 #define B_AX_CLK_CALIB_EN		BIT(12)
36 #define B_AX_CALIB_EN			BIT(13)
37 #define B_AX_DIV			GENMASK(15, 14)
38 #define RAC_SET_PPR_V1			0x31
39 
40 #define R_AX_DBI_FLAG			0x1090
41 #define B_AX_DBI_RFLAG			BIT(17)
42 #define B_AX_DBI_WFLAG			BIT(16)
43 #define B_AX_DBI_WREN_MSK		GENMASK(15, 12)
44 #define B_AX_DBI_ADDR_MSK		GENMASK(11, 2)
45 #define R_AX_DBI_WDATA			0x1094
46 #define R_AX_DBI_RDATA			0x1098
47 
48 #define R_AX_MDIO_WDATA			0x10A4
49 #define R_AX_MDIO_RDATA			0x10A6
50 
51 #define R_AX_PCIE_PS_CTRL_V1		0x3008
52 #define B_AX_CMAC_EXIT_L1_EN		BIT(7)
53 #define B_AX_DMAC0_EXIT_L1_EN		BIT(6)
54 #define B_AX_SEL_XFER_PENDING		BIT(3)
55 #define B_AX_SEL_REQ_ENTR_L1		BIT(2)
56 #define B_AX_SEL_REQ_EXIT_L1		BIT(0)
57 
58 #define R_AX_PCIE_MIX_CFG_V1		0x300C
59 #define B_AX_ASPM_CTRL_L1		BIT(17)
60 #define B_AX_ASPM_CTRL_L0		BIT(16)
61 #define B_AX_ASPM_CTRL_MASK		GENMASK(17, 16)
62 #define B_AX_XFER_PENDING_FW		BIT(11)
63 #define B_AX_XFER_PENDING		BIT(10)
64 #define B_AX_REQ_EXIT_L1		BIT(9)
65 #define B_AX_REQ_ENTR_L1		BIT(8)
66 #define B_AX_L1SUB_DISABLE		BIT(0)
67 
68 #define R_AX_L1_CLK_CTRL		0x3010
69 #define B_AX_CLK_REQ_N			BIT(1)
70 
71 #define R_AX_PCIE_BG_CLR		0x303C
72 #define B_AX_BG_CLR_ASYNC_M3		BIT(4)
73 
74 #define R_AX_PCIE_LAT_CTRL		0x3044
75 #define B_AX_CLK_REQ_SEL_OPT		BIT(1)
76 #define B_AX_CLK_REQ_SEL		BIT(0)
77 
78 #define R_AX_PCIE_IO_RCY_M1 0x3100
79 #define B_AX_PCIE_IO_RCY_P_M1 BIT(5)
80 #define B_AX_PCIE_IO_RCY_WDT_P_M1 BIT(4)
81 #define B_AX_PCIE_IO_RCY_WDT_MODE_M1 BIT(3)
82 #define B_AX_PCIE_IO_RCY_TRIG_M1 BIT(0)
83 
84 #define R_AX_PCIE_WDT_TIMER_M1 0x3104
85 #define B_AX_PCIE_WDT_TIMER_M1_MASK GENMASK(31, 0)
86 
87 #define R_AX_PCIE_IO_RCY_M2 0x310C
88 #define B_AX_PCIE_IO_RCY_P_M2 BIT(5)
89 #define B_AX_PCIE_IO_RCY_WDT_P_M2 BIT(4)
90 #define B_AX_PCIE_IO_RCY_WDT_MODE_M2 BIT(3)
91 #define B_AX_PCIE_IO_RCY_TRIG_M2 BIT(0)
92 
93 #define R_AX_PCIE_WDT_TIMER_M2 0x3110
94 #define B_AX_PCIE_WDT_TIMER_M2_MASK GENMASK(31, 0)
95 
96 #define R_AX_PCIE_IO_RCY_E0 0x3118
97 #define B_AX_PCIE_IO_RCY_P_E0 BIT(5)
98 #define B_AX_PCIE_IO_RCY_WDT_P_E0 BIT(4)
99 #define B_AX_PCIE_IO_RCY_WDT_MODE_E0 BIT(3)
100 #define B_AX_PCIE_IO_RCY_TRIG_E0 BIT(0)
101 
102 #define R_AX_PCIE_WDT_TIMER_E0 0x311C
103 #define B_AX_PCIE_WDT_TIMER_E0_MASK GENMASK(31, 0)
104 
105 #define R_AX_PCIE_IO_RCY_S1 0x3124
106 #define B_AX_PCIE_IO_RCY_RP_S1 BIT(7)
107 #define B_AX_PCIE_IO_RCY_WP_S1 BIT(6)
108 #define B_AX_PCIE_IO_RCY_WDT_RP_S1 BIT(5)
109 #define B_AX_PCIE_IO_RCY_WDT_WP_S1 BIT(4)
110 #define B_AX_PCIE_IO_RCY_WDT_MODE_S1 BIT(3)
111 #define B_AX_PCIE_IO_RCY_RTRIG_S1 BIT(1)
112 #define B_AX_PCIE_IO_RCY_WTRIG_S1 BIT(0)
113 
114 #define R_AX_PCIE_WDT_TIMER_S1 0x3128
115 #define B_AX_PCIE_WDT_TIMER_S1_MASK GENMASK(31, 0)
116 
117 #define R_RAC_DIRECT_OFFSET_G1 0x3800
118 #define FILTER_OUT_EQ_MASK GENMASK(14, 10)
119 #define R_RAC_DIRECT_OFFSET_G2 0x3880
120 #define REG_FILTER_OUT_MASK GENMASK(6, 2)
121 #define RAC_MULT 2
122 
123 #define RTW89_PCI_WR_RETRY_CNT		20
124 
125 /* Interrupts */
126 #define R_AX_HIMR0 0x01A0
127 #define B_AX_WDT_TIMEOUT_INT_EN BIT(22)
128 #define B_AX_HALT_C2H_INT_EN BIT(21)
129 #define R_AX_HISR0 0x01A4
130 
131 #define R_AX_HIMR1 0x01A8
132 #define B_AX_GPIO18_INT_EN BIT(2)
133 #define B_AX_GPIO17_INT_EN BIT(1)
134 #define B_AX_GPIO16_INT_EN BIT(0)
135 
136 #define R_AX_HISR1 0x01AC
137 #define B_AX_GPIO18_INT BIT(2)
138 #define B_AX_GPIO17_INT BIT(1)
139 #define B_AX_GPIO16_INT BIT(0)
140 
141 #define R_AX_MDIO_CFG			0x10A0
142 #define B_AX_MDIO_PHY_ADDR_MASK		GENMASK(13, 12)
143 #define B_AX_MDIO_RFLAG			BIT(9)
144 #define B_AX_MDIO_WFLAG			BIT(8)
145 #define B_AX_MDIO_ADDR_MASK		GENMASK(4, 0)
146 
147 #define R_AX_PCIE_HIMR00	0x10B0
148 #define R_AX_HAXI_HIMR00 0x10B0
149 #define B_AX_HC00ISR_IND_INT_EN		BIT(27)
150 #define B_AX_HD1ISR_IND_INT_EN		BIT(26)
151 #define B_AX_HD0ISR_IND_INT_EN		BIT(25)
152 #define B_AX_HS0ISR_IND_INT_EN		BIT(24)
153 #define B_AX_HS0ISR_IND_INT_EN_WKARND	BIT(23)
154 #define B_AX_RETRAIN_INT_EN		BIT(21)
155 #define B_AX_RPQBD_FULL_INT_EN		BIT(20)
156 #define B_AX_RDU_INT_EN			BIT(19)
157 #define B_AX_RXDMA_STUCK_INT_EN		BIT(18)
158 #define B_AX_TXDMA_STUCK_INT_EN		BIT(17)
159 #define B_AX_PCIE_HOTRST_INT_EN		BIT(16)
160 #define B_AX_PCIE_FLR_INT_EN		BIT(15)
161 #define B_AX_PCIE_PERST_INT_EN		BIT(14)
162 #define B_AX_TXDMA_CH12_INT_EN		BIT(13)
163 #define B_AX_TXDMA_CH9_INT_EN		BIT(12)
164 #define B_AX_TXDMA_CH8_INT_EN		BIT(11)
165 #define B_AX_TXDMA_ACH7_INT_EN		BIT(10)
166 #define B_AX_TXDMA_ACH6_INT_EN		BIT(9)
167 #define B_AX_TXDMA_ACH5_INT_EN		BIT(8)
168 #define B_AX_TXDMA_ACH4_INT_EN		BIT(7)
169 #define B_AX_TXDMA_ACH3_INT_EN		BIT(6)
170 #define B_AX_TXDMA_ACH2_INT_EN		BIT(5)
171 #define B_AX_TXDMA_ACH1_INT_EN		BIT(4)
172 #define B_AX_TXDMA_ACH0_INT_EN		BIT(3)
173 #define B_AX_RPQDMA_INT_EN		BIT(2)
174 #define B_AX_RXP1DMA_INT_EN		BIT(1)
175 #define B_AX_RXDMA_INT_EN		BIT(0)
176 
177 #define R_AX_PCIE_HISR00	0x10B4
178 #define R_AX_HAXI_HISR00 0x10B4
179 #define B_AX_HC00ISR_IND_INT		BIT(27)
180 #define B_AX_HD1ISR_IND_INT		BIT(26)
181 #define B_AX_HD0ISR_IND_INT		BIT(25)
182 #define B_AX_HS0ISR_IND_INT		BIT(24)
183 #define B_AX_RETRAIN_INT		BIT(21)
184 #define B_AX_RPQBD_FULL_INT		BIT(20)
185 #define B_AX_RDU_INT			BIT(19)
186 #define B_AX_RXDMA_STUCK_INT		BIT(18)
187 #define B_AX_TXDMA_STUCK_INT		BIT(17)
188 #define B_AX_PCIE_HOTRST_INT		BIT(16)
189 #define B_AX_PCIE_FLR_INT		BIT(15)
190 #define B_AX_PCIE_PERST_INT		BIT(14)
191 #define B_AX_TXDMA_CH12_INT		BIT(13)
192 #define B_AX_TXDMA_CH9_INT		BIT(12)
193 #define B_AX_TXDMA_CH8_INT		BIT(11)
194 #define B_AX_TXDMA_ACH7_INT		BIT(10)
195 #define B_AX_TXDMA_ACH6_INT		BIT(9)
196 #define B_AX_TXDMA_ACH5_INT		BIT(8)
197 #define B_AX_TXDMA_ACH4_INT		BIT(7)
198 #define B_AX_TXDMA_ACH3_INT		BIT(6)
199 #define B_AX_TXDMA_ACH2_INT		BIT(5)
200 #define B_AX_TXDMA_ACH1_INT		BIT(4)
201 #define B_AX_TXDMA_ACH0_INT		BIT(3)
202 #define B_AX_RPQDMA_INT			BIT(2)
203 #define B_AX_RXP1DMA_INT		BIT(1)
204 #define B_AX_RXDMA_INT			BIT(0)
205 
206 #define R_AX_HAXI_IDCT_MSK 0x10B8
207 #define B_AX_TXBD_LEN0_ERR_IDCT_MSK BIT(3)
208 #define B_AX_TXBD_4KBOUND_ERR_IDCT_MSK BIT(2)
209 #define B_AX_RXMDA_STUCK_IDCT_MSK BIT(1)
210 #define B_AX_TXMDA_STUCK_IDCT_MSK BIT(0)
211 
212 #define R_AX_HAXI_IDCT 0x10BC
213 #define B_AX_TXBD_LEN0_ERR_IDCT BIT(3)
214 #define B_AX_TXBD_4KBOUND_ERR_IDCT BIT(2)
215 #define B_AX_RXMDA_STUCK_IDCT BIT(1)
216 #define B_AX_TXMDA_STUCK_IDCT BIT(0)
217 
218 #define R_AX_HAXI_HIMR10 0x11E0
219 #define B_AX_TXDMA_CH11_INT_EN_V1 BIT(1)
220 #define B_AX_TXDMA_CH10_INT_EN_V1 BIT(0)
221 
222 #define R_AX_PCIE_HIMR10	0x13B0
223 #define B_AX_HC10ISR_IND_INT_EN		BIT(28)
224 #define B_AX_TXDMA_CH11_INT_EN		BIT(12)
225 #define B_AX_TXDMA_CH10_INT_EN		BIT(11)
226 
227 #define R_AX_PCIE_HISR10	0x13B4
228 #define B_AX_HC10ISR_IND_INT		BIT(28)
229 #define B_AX_TXDMA_CH11_INT		BIT(12)
230 #define B_AX_TXDMA_CH10_INT		BIT(11)
231 
232 #define R_AX_PCIE_HIMR00_V1 0x30B0
233 #define B_AX_HCI_AXIDMA_INT_EN BIT(29)
234 #define B_AX_HC00ISR_IND_INT_EN_V1 BIT(28)
235 #define B_AX_HD1ISR_IND_INT_EN_V1 BIT(27)
236 #define B_AX_HD0ISR_IND_INT_EN_V1 BIT(26)
237 #define B_AX_HS1ISR_IND_INT_EN BIT(25)
238 #define B_AX_PCIE_DBG_STE_INT_EN BIT(13)
239 
240 #define R_AX_PCIE_HISR00_V1 0x30B4
241 #define B_AX_HCI_AXIDMA_INT BIT(29)
242 #define B_AX_HC00ISR_IND_INT_V1 BIT(28)
243 #define B_AX_HD1ISR_IND_INT_V1 BIT(27)
244 #define B_AX_HD0ISR_IND_INT_V1 BIT(26)
245 #define B_AX_HS1ISR_IND_INT BIT(25)
246 #define B_AX_PCIE_DBG_STE_INT BIT(13)
247 
248 /* TX/RX */
249 #define R_AX_DRV_FW_HSK_0	0x01B0
250 #define R_AX_DRV_FW_HSK_1	0x01B4
251 #define R_AX_DRV_FW_HSK_2	0x01B8
252 #define R_AX_DRV_FW_HSK_3	0x01BC
253 #define R_AX_DRV_FW_HSK_4	0x01C0
254 #define R_AX_DRV_FW_HSK_5	0x01C4
255 #define R_AX_DRV_FW_HSK_6	0x01C8
256 #define R_AX_DRV_FW_HSK_7	0x01CC
257 
258 #define R_AX_RXQ_RXBD_IDX	0x1050
259 #define R_AX_RPQ_RXBD_IDX	0x1054
260 #define R_AX_ACH0_TXBD_IDX	0x1058
261 #define R_AX_ACH1_TXBD_IDX	0x105C
262 #define R_AX_ACH2_TXBD_IDX	0x1060
263 #define R_AX_ACH3_TXBD_IDX	0x1064
264 #define R_AX_ACH4_TXBD_IDX	0x1068
265 #define R_AX_ACH5_TXBD_IDX	0x106C
266 #define R_AX_ACH6_TXBD_IDX	0x1070
267 #define R_AX_ACH7_TXBD_IDX	0x1074
268 #define R_AX_CH8_TXBD_IDX	0x1078 /* Management Queue band 0 */
269 #define R_AX_CH9_TXBD_IDX	0x107C /* HI Queue band 0 */
270 #define R_AX_CH10_TXBD_IDX	0x137C /* Management Queue band 1 */
271 #define R_AX_CH11_TXBD_IDX	0x1380 /* HI Queue band 1 */
272 #define R_AX_CH12_TXBD_IDX	0x1080 /* FWCMD Queue */
273 #define R_AX_CH10_TXBD_IDX_V1	0x11D0
274 #define R_AX_CH11_TXBD_IDX_V1	0x11D4
275 #define R_AX_RXQ_RXBD_IDX_V1	0x1218
276 #define R_AX_RPQ_RXBD_IDX_V1	0x121C
277 #define TXBD_HW_IDX_MASK	GENMASK(27, 16)
278 #define TXBD_HOST_IDX_MASK	GENMASK(11, 0)
279 
280 #define R_AX_ACH0_TXBD_DESA_L	0x1110
281 #define R_AX_ACH0_TXBD_DESA_H	0x1114
282 #define R_AX_ACH1_TXBD_DESA_L	0x1118
283 #define R_AX_ACH1_TXBD_DESA_H	0x111C
284 #define R_AX_ACH2_TXBD_DESA_L	0x1120
285 #define R_AX_ACH2_TXBD_DESA_H	0x1124
286 #define R_AX_ACH3_TXBD_DESA_L	0x1128
287 #define R_AX_ACH3_TXBD_DESA_H	0x112C
288 #define R_AX_ACH4_TXBD_DESA_L	0x1130
289 #define R_AX_ACH4_TXBD_DESA_H	0x1134
290 #define R_AX_ACH5_TXBD_DESA_L	0x1138
291 #define R_AX_ACH5_TXBD_DESA_H	0x113C
292 #define R_AX_ACH6_TXBD_DESA_L	0x1140
293 #define R_AX_ACH6_TXBD_DESA_H	0x1144
294 #define R_AX_ACH7_TXBD_DESA_L	0x1148
295 #define R_AX_ACH7_TXBD_DESA_H	0x114C
296 #define R_AX_CH8_TXBD_DESA_L	0x1150
297 #define R_AX_CH8_TXBD_DESA_H	0x1154
298 #define R_AX_CH9_TXBD_DESA_L	0x1158
299 #define R_AX_CH9_TXBD_DESA_H	0x115C
300 #define R_AX_CH10_TXBD_DESA_L	0x1358
301 #define R_AX_CH10_TXBD_DESA_H	0x135C
302 #define R_AX_CH11_TXBD_DESA_L	0x1360
303 #define R_AX_CH11_TXBD_DESA_H	0x1364
304 #define R_AX_CH12_TXBD_DESA_L	0x1160
305 #define R_AX_CH12_TXBD_DESA_H	0x1164
306 #define R_AX_RXQ_RXBD_DESA_L	0x1100
307 #define R_AX_RXQ_RXBD_DESA_H	0x1104
308 #define R_AX_RPQ_RXBD_DESA_L	0x1108
309 #define R_AX_RPQ_RXBD_DESA_H	0x110C
310 #define R_AX_RXQ_RXBD_DESA_L_V1 0x1220
311 #define R_AX_RXQ_RXBD_DESA_H_V1 0x1224
312 #define R_AX_RPQ_RXBD_DESA_L_V1 0x1228
313 #define R_AX_RPQ_RXBD_DESA_H_V1 0x122C
314 #define R_AX_ACH0_TXBD_DESA_L_V1 0x1230
315 #define R_AX_ACH0_TXBD_DESA_H_V1 0x1234
316 #define R_AX_ACH1_TXBD_DESA_L_V1 0x1238
317 #define R_AX_ACH1_TXBD_DESA_H_V1 0x123C
318 #define R_AX_ACH2_TXBD_DESA_L_V1 0x1240
319 #define R_AX_ACH2_TXBD_DESA_H_V1 0x1244
320 #define R_AX_ACH3_TXBD_DESA_L_V1 0x1248
321 #define R_AX_ACH3_TXBD_DESA_H_V1 0x124C
322 #define R_AX_ACH4_TXBD_DESA_L_V1 0x1250
323 #define R_AX_ACH4_TXBD_DESA_H_V1 0x1254
324 #define R_AX_ACH5_TXBD_DESA_L_V1 0x1258
325 #define R_AX_ACH5_TXBD_DESA_H_V1 0x125C
326 #define R_AX_ACH6_TXBD_DESA_L_V1 0x1260
327 #define R_AX_ACH6_TXBD_DESA_H_V1 0x1264
328 #define R_AX_ACH7_TXBD_DESA_L_V1 0x1268
329 #define R_AX_ACH7_TXBD_DESA_H_V1 0x126C
330 #define R_AX_CH8_TXBD_DESA_L_V1 0x1270
331 #define R_AX_CH8_TXBD_DESA_H_V1 0x1274
332 #define R_AX_CH9_TXBD_DESA_L_V1 0x1278
333 #define R_AX_CH9_TXBD_DESA_H_V1 0x127C
334 #define R_AX_CH12_TXBD_DESA_L_V1 0x1280
335 #define R_AX_CH12_TXBD_DESA_H_V1 0x1284
336 #define R_AX_CH10_TXBD_DESA_L_V1 0x1458
337 #define R_AX_CH10_TXBD_DESA_H_V1 0x145C
338 #define R_AX_CH11_TXBD_DESA_L_V1 0x1460
339 #define R_AX_CH11_TXBD_DESA_H_V1 0x1464
340 #define B_AX_DESC_NUM_MSK		GENMASK(11, 0)
341 
342 #define R_AX_RXQ_RXBD_NUM	0x1020
343 #define R_AX_RPQ_RXBD_NUM	0x1022
344 #define R_AX_ACH0_TXBD_NUM	0x1024
345 #define R_AX_ACH1_TXBD_NUM	0x1026
346 #define R_AX_ACH2_TXBD_NUM	0x1028
347 #define R_AX_ACH3_TXBD_NUM	0x102A
348 #define R_AX_ACH4_TXBD_NUM	0x102C
349 #define R_AX_ACH5_TXBD_NUM	0x102E
350 #define R_AX_ACH6_TXBD_NUM	0x1030
351 #define R_AX_ACH7_TXBD_NUM	0x1032
352 #define R_AX_CH8_TXBD_NUM	0x1034
353 #define R_AX_CH9_TXBD_NUM	0x1036
354 #define R_AX_CH10_TXBD_NUM	0x1338
355 #define R_AX_CH11_TXBD_NUM	0x133A
356 #define R_AX_CH12_TXBD_NUM	0x1038
357 #define R_AX_RXQ_RXBD_NUM_V1	0x1210
358 #define R_AX_RPQ_RXBD_NUM_V1	0x1212
359 #define R_AX_CH10_TXBD_NUM_V1	0x1438
360 #define R_AX_CH11_TXBD_NUM_V1	0x143A
361 
362 #define R_AX_ACH0_BDRAM_CTRL	0x1200
363 #define R_AX_ACH1_BDRAM_CTRL	0x1204
364 #define R_AX_ACH2_BDRAM_CTRL	0x1208
365 #define R_AX_ACH3_BDRAM_CTRL	0x120C
366 #define R_AX_ACH4_BDRAM_CTRL	0x1210
367 #define R_AX_ACH5_BDRAM_CTRL	0x1214
368 #define R_AX_ACH6_BDRAM_CTRL	0x1218
369 #define R_AX_ACH7_BDRAM_CTRL	0x121C
370 #define R_AX_CH8_BDRAM_CTRL	0x1220
371 #define R_AX_CH9_BDRAM_CTRL	0x1224
372 #define R_AX_CH10_BDRAM_CTRL	0x1320
373 #define R_AX_CH11_BDRAM_CTRL	0x1324
374 #define R_AX_CH12_BDRAM_CTRL	0x1228
375 #define R_AX_ACH0_BDRAM_CTRL_V1 0x1300
376 #define R_AX_ACH1_BDRAM_CTRL_V1 0x1304
377 #define R_AX_ACH2_BDRAM_CTRL_V1 0x1308
378 #define R_AX_ACH3_BDRAM_CTRL_V1 0x130C
379 #define R_AX_ACH4_BDRAM_CTRL_V1 0x1310
380 #define R_AX_ACH5_BDRAM_CTRL_V1 0x1314
381 #define R_AX_ACH6_BDRAM_CTRL_V1 0x1318
382 #define R_AX_ACH7_BDRAM_CTRL_V1 0x131C
383 #define R_AX_CH8_BDRAM_CTRL_V1 0x1320
384 #define R_AX_CH9_BDRAM_CTRL_V1 0x1324
385 #define R_AX_CH12_BDRAM_CTRL_V1 0x1328
386 #define R_AX_CH10_BDRAM_CTRL_V1 0x1420
387 #define R_AX_CH11_BDRAM_CTRL_V1 0x1424
388 #define BDRAM_SIDX_MASK		GENMASK(7, 0)
389 #define BDRAM_MAX_MASK		GENMASK(15, 8)
390 #define BDRAM_MIN_MASK		GENMASK(23, 16)
391 
392 #define R_AX_PCIE_INIT_CFG1	0x1000
393 #define B_AX_PCIE_RXRST_KEEP_REG	BIT(23)
394 #define B_AX_PCIE_TXRST_KEEP_REG	BIT(22)
395 #define B_AX_PCIE_PERST_KEEP_REG	BIT(21)
396 #define B_AX_PCIE_FLR_KEEP_REG		BIT(20)
397 #define B_AX_PCIE_TRAIN_KEEP_REG	BIT(19)
398 #define B_AX_RXBD_MODE			BIT(18)
399 #define B_AX_PCIE_MAX_RXDMA_MASK	GENMASK(16, 14)
400 #define B_AX_RXHCI_EN			BIT(13)
401 #define B_AX_LATENCY_CONTROL		BIT(12)
402 #define B_AX_TXHCI_EN			BIT(11)
403 #define B_AX_PCIE_MAX_TXDMA_MASK	GENMASK(10, 8)
404 #define B_AX_TX_TRUNC_MODE		BIT(5)
405 #define B_AX_RX_TRUNC_MODE		BIT(4)
406 #define B_AX_RST_BDRAM			BIT(3)
407 #define B_AX_DIS_RXDMA_PRE		BIT(2)
408 
409 #define R_AX_TXDMA_ADDR_H	0x10F0
410 #define R_AX_RXDMA_ADDR_H	0x10F4
411 
412 #define R_AX_PCIE_DMA_STOP1	0x1010
413 #define B_AX_STOP_PCIEIO		BIT(20)
414 #define B_AX_STOP_WPDMA			BIT(19)
415 #define B_AX_STOP_CH12			BIT(18)
416 #define B_AX_STOP_CH9			BIT(17)
417 #define B_AX_STOP_CH8			BIT(16)
418 #define B_AX_STOP_ACH7			BIT(15)
419 #define B_AX_STOP_ACH6			BIT(14)
420 #define B_AX_STOP_ACH5			BIT(13)
421 #define B_AX_STOP_ACH4			BIT(12)
422 #define B_AX_STOP_ACH3			BIT(11)
423 #define B_AX_STOP_ACH2			BIT(10)
424 #define B_AX_STOP_ACH1			BIT(9)
425 #define B_AX_STOP_ACH0			BIT(8)
426 #define B_AX_STOP_RPQ			BIT(1)
427 #define B_AX_STOP_RXQ			BIT(0)
428 #define B_AX_TX_STOP1_ALL		GENMASK(18, 8)
429 #define B_AX_TX_STOP1_MASK		(B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | \
430 					 B_AX_STOP_ACH2 | B_AX_STOP_ACH3 | \
431 					 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | \
432 					 B_AX_STOP_ACH6 | B_AX_STOP_ACH7 | \
433 					 B_AX_STOP_CH8 | B_AX_STOP_CH9 | \
434 					 B_AX_STOP_CH12)
435 #define B_AX_TX_STOP1_MASK_V1		(B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | \
436 					 B_AX_STOP_ACH2 | B_AX_STOP_ACH3 | \
437 					 B_AX_STOP_CH8 | B_AX_STOP_CH9 | \
438 					 B_AX_STOP_CH12)
439 
440 #define R_AX_PCIE_DMA_STOP2	0x1310
441 #define B_AX_STOP_CH11			BIT(1)
442 #define B_AX_STOP_CH10			BIT(0)
443 #define B_AX_TX_STOP2_ALL		GENMASK(1, 0)
444 
445 #define R_AX_TXBD_RWPTR_CLR1	0x1014
446 #define B_AX_CLR_CH12_IDX		BIT(10)
447 #define B_AX_CLR_CH9_IDX		BIT(9)
448 #define B_AX_CLR_CH8_IDX		BIT(8)
449 #define B_AX_CLR_ACH7_IDX		BIT(7)
450 #define B_AX_CLR_ACH6_IDX		BIT(6)
451 #define B_AX_CLR_ACH5_IDX		BIT(5)
452 #define B_AX_CLR_ACH4_IDX		BIT(4)
453 #define B_AX_CLR_ACH3_IDX		BIT(3)
454 #define B_AX_CLR_ACH2_IDX		BIT(2)
455 #define B_AX_CLR_ACH1_IDX		BIT(1)
456 #define B_AX_CLR_ACH0_IDX		BIT(0)
457 #define B_AX_TXBD_CLR1_ALL		GENMASK(10, 0)
458 
459 #define R_AX_RXBD_RWPTR_CLR	0x1018
460 #define B_AX_CLR_RPQ_IDX		BIT(1)
461 #define B_AX_CLR_RXQ_IDX		BIT(0)
462 #define B_AX_RXBD_CLR_ALL		GENMASK(1, 0)
463 
464 #define R_AX_TXBD_RWPTR_CLR2	0x1314
465 #define B_AX_CLR_CH11_IDX		BIT(1)
466 #define B_AX_CLR_CH10_IDX		BIT(0)
467 #define B_AX_TXBD_CLR2_ALL		GENMASK(1, 0)
468 
469 #define R_AX_PCIE_DMA_BUSY1	0x101C
470 #define B_AX_PCIEIO_RX_BUSY		BIT(22)
471 #define B_AX_PCIEIO_TX_BUSY		BIT(21)
472 #define B_AX_PCIEIO_BUSY		BIT(20)
473 #define B_AX_WPDMA_BUSY			BIT(19)
474 #define B_AX_CH12_BUSY			BIT(18)
475 #define B_AX_CH9_BUSY			BIT(17)
476 #define B_AX_CH8_BUSY			BIT(16)
477 #define B_AX_ACH7_BUSY			BIT(15)
478 #define B_AX_ACH6_BUSY			BIT(14)
479 #define B_AX_ACH5_BUSY			BIT(13)
480 #define B_AX_ACH4_BUSY			BIT(12)
481 #define B_AX_ACH3_BUSY			BIT(11)
482 #define B_AX_ACH2_BUSY			BIT(10)
483 #define B_AX_ACH1_BUSY			BIT(9)
484 #define B_AX_ACH0_BUSY			BIT(8)
485 #define B_AX_RPQ_BUSY			BIT(1)
486 #define B_AX_RXQ_BUSY			BIT(0)
487 #define DMA_BUSY1_CHECK		(B_AX_ACH0_BUSY | B_AX_ACH1_BUSY | B_AX_ACH2_BUSY | \
488 				 B_AX_ACH3_BUSY | B_AX_ACH4_BUSY | B_AX_ACH5_BUSY | \
489 				 B_AX_ACH6_BUSY | B_AX_ACH7_BUSY | B_AX_CH8_BUSY | \
490 				 B_AX_CH9_BUSY | B_AX_CH12_BUSY)
491 #define DMA_BUSY1_CHECK_V1	(B_AX_ACH0_BUSY | B_AX_ACH1_BUSY | B_AX_ACH2_BUSY | \
492 				 B_AX_ACH3_BUSY | B_AX_CH8_BUSY | B_AX_CH9_BUSY | \
493 				 B_AX_CH12_BUSY)
494 
495 #define R_AX_PCIE_DMA_BUSY2	0x131C
496 #define B_AX_CH11_BUSY			BIT(1)
497 #define B_AX_CH10_BUSY			BIT(0)
498 
499 /* Configure */
500 #define R_AX_PCIE_INIT_CFG2		0x1004
501 #define B_AX_WD_ITVL_IDLE		GENMASK(27, 24)
502 #define B_AX_WD_ITVL_ACT		GENMASK(19, 16)
503 #define B_AX_PCIE_RX_APPLEN_MASK	GENMASK(13, 0)
504 
505 #define R_AX_PCIE_PS_CTRL		0x1008
506 #define B_AX_L1OFF_PWR_OFF_EN		BIT(5)
507 
508 #define R_AX_INT_MIT_RX			0x10D4
509 #define B_AX_RXMIT_RXP2_SEL		BIT(19)
510 #define B_AX_RXMIT_RXP1_SEL		BIT(18)
511 #define B_AX_RXTIMER_UNIT_MASK		GENMASK(17, 16)
512 #define AX_RXTIMER_UNIT_64US		0
513 #define AX_RXTIMER_UNIT_128US		1
514 #define AX_RXTIMER_UNIT_256US		2
515 #define AX_RXTIMER_UNIT_512US		3
516 #define B_AX_RXCOUNTER_MATCH_MASK	GENMASK(15, 8)
517 #define B_AX_RXTIMER_MATCH_MASK		GENMASK(7, 0)
518 
519 #define R_AX_DBG_ERR_FLAG		0x11C4
520 #define B_AX_PCIE_RPQ_FULL		BIT(29)
521 #define B_AX_PCIE_RXQ_FULL		BIT(28)
522 #define B_AX_CPL_STATUS_MASK		GENMASK(27, 25)
523 #define B_AX_RX_STUCK			BIT(22)
524 #define B_AX_TX_STUCK			BIT(21)
525 #define B_AX_PCIEDBG_TXERR0		BIT(16)
526 #define B_AX_PCIE_RXP1_ERR0		BIT(4)
527 #define B_AX_PCIE_TXBD_LEN0		BIT(1)
528 #define B_AX_PCIE_TXBD_4KBOUD_LENERR	BIT(0)
529 
530 #define R_AX_TXBD_RWPTR_CLR2_V1		0x11C4
531 #define B_AX_CLR_CH11_IDX		BIT(1)
532 #define B_AX_CLR_CH10_IDX		BIT(0)
533 
534 #define R_AX_LBC_WATCHDOG		0x11D8
535 #define B_AX_LBC_TIMER			GENMASK(7, 4)
536 #define B_AX_LBC_FLAG			BIT(1)
537 #define B_AX_LBC_EN			BIT(0)
538 
539 #define R_AX_RXBD_RWPTR_CLR_V1		0x1200
540 #define B_AX_CLR_RPQ_IDX		BIT(1)
541 #define B_AX_CLR_RXQ_IDX		BIT(0)
542 
543 #define R_AX_HAXI_EXP_CTRL		0x1204
544 #define B_AX_MAX_TAG_NUM_V1_MASK	GENMASK(2, 0)
545 
546 #define R_AX_PCIE_EXP_CTRL		0x13F0
547 #define B_AX_EN_CHKDSC_NO_RX_STUCK	BIT(20)
548 #define B_AX_MAX_TAG_NUM		GENMASK(18, 16)
549 #define B_AX_SIC_EN_FORCE_CLKREQ	BIT(4)
550 
551 #define R_AX_PCIE_RX_PREF_ADV		0x13F4
552 #define B_AX_RXDMA_PREF_ADV_EN		BIT(0)
553 
554 #define R_AX_PCIE_HRPWM_V1		0x30C0
555 #define R_AX_PCIE_CRPWM			0x30C4
556 
557 #define RTW89_PCI_TXBD_NUM_MAX		256
558 #define RTW89_PCI_RXBD_NUM_MAX		256
559 #define RTW89_PCI_TXWD_NUM_MAX		512
560 #define RTW89_PCI_TXWD_PAGE_SIZE	128
561 #define RTW89_PCI_ADDRINFO_MAX		4
562 #define RTW89_PCI_RX_BUF_SIZE		11460
563 
564 #define RTW89_PCI_POLL_BDRAM_RST_CNT	100
565 #define RTW89_PCI_MULTITAG		8
566 
567 /* PCIE CFG register */
568 #define RTW89_PCIE_L1_STS_V1		0x80
569 #define RTW89_BCFG_LINK_SPEED_MASK	GENMASK(19, 16)
570 #define RTW89_PCIE_GEN1_SPEED		0x01
571 #define RTW89_PCIE_GEN2_SPEED		0x02
572 #define RTW89_PCIE_PHY_RATE		0x82
573 #define RTW89_PCIE_PHY_RATE_MASK	GENMASK(1, 0)
574 #define RTW89_PCIE_L1SS_STS_V1		0x0168
575 #define RTW89_PCIE_BIT_ASPM_L11		BIT(3)
576 #define RTW89_PCIE_BIT_ASPM_L12		BIT(2)
577 #define RTW89_PCIE_BIT_PCI_L11		BIT(1)
578 #define RTW89_PCIE_BIT_PCI_L12		BIT(0)
579 #define RTW89_PCIE_ASPM_CTRL		0x070F
580 #define RTW89_L1DLY_MASK		GENMASK(5, 3)
581 #define RTW89_L0DLY_MASK		GENMASK(2, 0)
582 #define RTW89_PCIE_TIMER_CTRL		0x0718
583 #define RTW89_PCIE_BIT_L1SUB		BIT(5)
584 #define RTW89_PCIE_L1_CTRL		0x0719
585 #define RTW89_PCIE_BIT_CLK		BIT(4)
586 #define RTW89_PCIE_BIT_L1		BIT(3)
587 #define RTW89_PCIE_CLK_CTRL		0x0725
588 #define RTW89_PCIE_RST_MSTATE		0x0B48
589 #define RTW89_PCIE_BIT_CFG_RST_MSTATE	BIT(0)
590 
591 #define INTF_INTGRA_MINREF_V1	90
592 #define INTF_INTGRA_HOSTREF_V1	100
593 
594 enum rtw89_pcie_phy {
595 	PCIE_PHY_GEN1,
596 	PCIE_PHY_GEN2,
597 	PCIE_PHY_GEN1_UNDEFINE = 0x7F,
598 };
599 
600 enum rtw89_pcie_l0sdly {
601 	PCIE_L0SDLY_1US = 0,
602 	PCIE_L0SDLY_2US = 1,
603 	PCIE_L0SDLY_3US = 2,
604 	PCIE_L0SDLY_4US = 3,
605 	PCIE_L0SDLY_5US = 4,
606 	PCIE_L0SDLY_6US = 5,
607 	PCIE_L0SDLY_7US = 6,
608 };
609 
610 enum rtw89_pcie_l1dly {
611 	PCIE_L1DLY_16US = 4,
612 	PCIE_L1DLY_32US = 5,
613 	PCIE_L1DLY_64US = 6,
614 	PCIE_L1DLY_HW_INFI = 7,
615 };
616 
617 enum rtw89_pcie_clkdly_hw {
618 	PCIE_CLKDLY_HW_0 = 0,
619 	PCIE_CLKDLY_HW_30US = 0x1,
620 	PCIE_CLKDLY_HW_50US = 0x2,
621 	PCIE_CLKDLY_HW_100US = 0x3,
622 	PCIE_CLKDLY_HW_150US = 0x4,
623 	PCIE_CLKDLY_HW_200US = 0x5,
624 };
625 
626 enum mac_ax_bd_trunc_mode {
627 	MAC_AX_BD_NORM,
628 	MAC_AX_BD_TRUNC,
629 	MAC_AX_BD_DEF = 0xFE
630 };
631 
632 enum mac_ax_rxbd_mode {
633 	MAC_AX_RXBD_PKT,
634 	MAC_AX_RXBD_SEP,
635 	MAC_AX_RXBD_DEF = 0xFE
636 };
637 
638 enum mac_ax_tag_mode {
639 	MAC_AX_TAG_SGL,
640 	MAC_AX_TAG_MULTI,
641 	MAC_AX_TAG_DEF = 0xFE
642 };
643 
644 enum mac_ax_tx_burst {
645 	MAC_AX_TX_BURST_16B = 0,
646 	MAC_AX_TX_BURST_32B = 1,
647 	MAC_AX_TX_BURST_64B = 2,
648 	MAC_AX_TX_BURST_V1_64B = 0,
649 	MAC_AX_TX_BURST_128B = 3,
650 	MAC_AX_TX_BURST_V1_128B = 1,
651 	MAC_AX_TX_BURST_256B = 4,
652 	MAC_AX_TX_BURST_V1_256B = 2,
653 	MAC_AX_TX_BURST_512B = 5,
654 	MAC_AX_TX_BURST_1024B = 6,
655 	MAC_AX_TX_BURST_2048B = 7,
656 	MAC_AX_TX_BURST_DEF = 0xFE
657 };
658 
659 enum mac_ax_rx_burst {
660 	MAC_AX_RX_BURST_16B = 0,
661 	MAC_AX_RX_BURST_32B = 1,
662 	MAC_AX_RX_BURST_64B = 2,
663 	MAC_AX_RX_BURST_V1_64B = 0,
664 	MAC_AX_RX_BURST_128B = 3,
665 	MAC_AX_RX_BURST_V1_128B = 1,
666 	MAC_AX_RX_BURST_V1_256B = 0,
667 	MAC_AX_RX_BURST_DEF = 0xFE
668 };
669 
670 enum mac_ax_wd_dma_intvl {
671 	MAC_AX_WD_DMA_INTVL_0S,
672 	MAC_AX_WD_DMA_INTVL_256NS,
673 	MAC_AX_WD_DMA_INTVL_512NS,
674 	MAC_AX_WD_DMA_INTVL_768NS,
675 	MAC_AX_WD_DMA_INTVL_1US,
676 	MAC_AX_WD_DMA_INTVL_1_5US,
677 	MAC_AX_WD_DMA_INTVL_2US,
678 	MAC_AX_WD_DMA_INTVL_4US,
679 	MAC_AX_WD_DMA_INTVL_8US,
680 	MAC_AX_WD_DMA_INTVL_16US,
681 	MAC_AX_WD_DMA_INTVL_DEF = 0xFE
682 };
683 
684 enum mac_ax_multi_tag_num {
685 	MAC_AX_TAG_NUM_1,
686 	MAC_AX_TAG_NUM_2,
687 	MAC_AX_TAG_NUM_3,
688 	MAC_AX_TAG_NUM_4,
689 	MAC_AX_TAG_NUM_5,
690 	MAC_AX_TAG_NUM_6,
691 	MAC_AX_TAG_NUM_7,
692 	MAC_AX_TAG_NUM_8,
693 	MAC_AX_TAG_NUM_DEF = 0xFE
694 };
695 
696 enum mac_ax_lbc_tmr {
697 	MAC_AX_LBC_TMR_8US = 0,
698 	MAC_AX_LBC_TMR_16US,
699 	MAC_AX_LBC_TMR_32US,
700 	MAC_AX_LBC_TMR_64US,
701 	MAC_AX_LBC_TMR_128US,
702 	MAC_AX_LBC_TMR_256US,
703 	MAC_AX_LBC_TMR_512US,
704 	MAC_AX_LBC_TMR_1MS,
705 	MAC_AX_LBC_TMR_2MS,
706 	MAC_AX_LBC_TMR_4MS,
707 	MAC_AX_LBC_TMR_8MS,
708 	MAC_AX_LBC_TMR_DEF = 0xFE
709 };
710 
711 enum mac_ax_pcie_func_ctrl {
712 	MAC_AX_PCIE_DISABLE = 0,
713 	MAC_AX_PCIE_ENABLE = 1,
714 	MAC_AX_PCIE_DEFAULT = 0xFE,
715 	MAC_AX_PCIE_IGNORE = 0xFF
716 };
717 
718 enum mac_ax_io_rcy_tmr {
719 	MAC_AX_IO_RCY_ANA_TMR_2MS = 24000,
720 	MAC_AX_IO_RCY_ANA_TMR_4MS = 48000,
721 	MAC_AX_IO_RCY_ANA_TMR_6MS = 72000,
722 	MAC_AX_IO_RCY_ANA_TMR_DEF = 0xFE
723 };
724 
725 enum rtw89_pci_intr_mask_cfg {
726 	RTW89_PCI_INTR_MASK_RESET,
727 	RTW89_PCI_INTR_MASK_NORMAL,
728 	RTW89_PCI_INTR_MASK_LOW_POWER,
729 	RTW89_PCI_INTR_MASK_RECOVERY_START,
730 	RTW89_PCI_INTR_MASK_RECOVERY_COMPLETE,
731 };
732 
733 struct rtw89_pci_isrs;
734 struct rtw89_pci;
735 
736 struct rtw89_pci_bd_idx_addr {
737 	u32 tx_bd_addrs[RTW89_TXCH_NUM];
738 	u32 rx_bd_addrs[RTW89_RXCH_NUM];
739 };
740 
741 struct rtw89_pci_ch_dma_addr {
742 	u32 num;
743 	u32 idx;
744 	u32 bdram;
745 	u32 desa_l;
746 	u32 desa_h;
747 };
748 
749 struct rtw89_pci_ch_dma_addr_set {
750 	struct rtw89_pci_ch_dma_addr tx[RTW89_TXCH_NUM];
751 	struct rtw89_pci_ch_dma_addr rx[RTW89_RXCH_NUM];
752 };
753 
754 struct rtw89_pci_bd_ram {
755 	u8 start_idx;
756 	u8 max_num;
757 	u8 min_num;
758 };
759 
760 struct rtw89_pci_info {
761 	enum mac_ax_bd_trunc_mode txbd_trunc_mode;
762 	enum mac_ax_bd_trunc_mode rxbd_trunc_mode;
763 	enum mac_ax_rxbd_mode rxbd_mode;
764 	enum mac_ax_tag_mode tag_mode;
765 	enum mac_ax_tx_burst tx_burst;
766 	enum mac_ax_rx_burst rx_burst;
767 	enum mac_ax_wd_dma_intvl wd_dma_idle_intvl;
768 	enum mac_ax_wd_dma_intvl wd_dma_act_intvl;
769 	enum mac_ax_multi_tag_num multi_tag_num;
770 	enum mac_ax_pcie_func_ctrl lbc_en;
771 	enum mac_ax_lbc_tmr lbc_tmr;
772 	enum mac_ax_pcie_func_ctrl autok_en;
773 	enum mac_ax_pcie_func_ctrl io_rcy_en;
774 	enum mac_ax_io_rcy_tmr io_rcy_tmr;
775 
776 	u32 init_cfg_reg;
777 	u32 txhci_en_bit;
778 	u32 rxhci_en_bit;
779 	u32 rxbd_mode_bit;
780 	u32 exp_ctrl_reg;
781 	u32 max_tag_num_mask;
782 	u32 rxbd_rwptr_clr_reg;
783 	u32 txbd_rwptr_clr2_reg;
784 	struct rtw89_reg_def dma_stop1;
785 	struct rtw89_reg_def dma_stop2;
786 	struct rtw89_reg_def dma_busy1;
787 	u32 dma_busy2_reg;
788 	u32 dma_busy3_reg;
789 
790 	u32 rpwm_addr;
791 	u32 cpwm_addr;
792 	u32 tx_dma_ch_mask;
793 	const struct rtw89_pci_bd_idx_addr *bd_idx_addr_low_power;
794 	const struct rtw89_pci_ch_dma_addr_set *dma_addr_set;
795 	const struct rtw89_pci_bd_ram (*bd_ram_table)[RTW89_TXCH_NUM];
796 
797 	int (*ltr_set)(struct rtw89_dev *rtwdev, bool en);
798 	u32 (*fill_txaddr_info)(struct rtw89_dev *rtwdev,
799 				void *txaddr_info_addr, u32 total_len,
800 				dma_addr_t dma, u8 *add_info_nr);
801 	void (*config_intr_mask)(struct rtw89_dev *rtwdev);
802 	void (*enable_intr)(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
803 	void (*disable_intr)(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
804 	void (*recognize_intrs)(struct rtw89_dev *rtwdev,
805 				struct rtw89_pci *rtwpci,
806 				struct rtw89_pci_isrs *isrs);
807 };
808 
809 struct rtw89_pci_tx_data {
810 	dma_addr_t dma;
811 };
812 
813 struct rtw89_pci_rx_info {
814 	dma_addr_t dma;
815 	u32 fs:1, ls:1, tag:11, len:14;
816 };
817 
818 #define RTW89_PCI_TXBD_OPTION_LS	BIT(14)
819 
820 struct rtw89_pci_tx_bd_32 {
821 	__le16 length;
822 	__le16 option;
823 	__le32 dma;
824 } __packed;
825 
826 #define RTW89_PCI_TXWP_VALID		BIT(15)
827 
828 struct rtw89_pci_tx_wp_info {
829 	__le16 seq0;
830 	__le16 seq1;
831 	__le16 seq2;
832 	__le16 seq3;
833 } __packed;
834 
835 #define RTW89_PCI_ADDR_MSDU_LS		BIT(15)
836 #define RTW89_PCI_ADDR_LS		BIT(14)
837 #define RTW89_PCI_ADDR_HIGH(a)		(((a) << 6) & GENMASK(13, 6))
838 #define RTW89_PCI_ADDR_NUM(x)		((x) & GENMASK(5, 0))
839 
840 struct rtw89_pci_tx_addr_info_32 {
841 	__le16 length;
842 	__le16 option;
843 	__le32 dma;
844 } __packed;
845 
846 #define RTW89_TXADDR_INFO_NR_V1		10
847 
848 struct rtw89_pci_tx_addr_info_32_v1 {
849 	__le16 length_opt;
850 #define B_PCIADDR_LEN_V1_MASK		GENMASK(10, 0)
851 #define B_PCIADDR_HIGH_SEL_V1_MASK	GENMASK(14, 11)
852 #define B_PCIADDR_LS_V1_MASK		BIT(15)
853 #define TXADDR_INFO_LENTHG_V1_MAX	ALIGN_DOWN(BIT(11) - 1, 4)
854 	__le16 dma_low_lsb;
855 	__le16 dma_low_msb;
856 } __packed;
857 
858 #define RTW89_PCI_RPP_POLLUTED		BIT(31)
859 #define RTW89_PCI_RPP_SEQ		GENMASK(30, 16)
860 #define RTW89_PCI_RPP_TX_STATUS		GENMASK(15, 13)
861 #define RTW89_TX_DONE			0x0
862 #define RTW89_TX_RETRY_LIMIT		0x1
863 #define RTW89_TX_LIFE_TIME		0x2
864 #define RTW89_TX_MACID_DROP		0x3
865 #define RTW89_PCI_RPP_QSEL		GENMASK(12, 8)
866 #define RTW89_PCI_RPP_MACID		GENMASK(7, 0)
867 
868 struct rtw89_pci_rpp_fmt {
869 	__le32 dword;
870 } __packed;
871 
872 struct rtw89_pci_rx_bd_32 {
873 	__le16 buf_size;
874 	__le16 rsvd;
875 	__le32 dma;
876 } __packed;
877 
878 #define RTW89_PCI_RXBD_FS		BIT(15)
879 #define RTW89_PCI_RXBD_LS		BIT(14)
880 #define RTW89_PCI_RXBD_WRITE_SIZE	GENMASK(13, 0)
881 #define RTW89_PCI_RXBD_TAG		GENMASK(28, 16)
882 
883 struct rtw89_pci_rxbd_info {
884 	__le32 dword;
885 };
886 
887 struct rtw89_pci_tx_wd {
888 	struct list_head list;
889 	struct sk_buff_head queue;
890 
891 	void *vaddr;
892 	dma_addr_t paddr;
893 	u32 len;
894 	u32 seq;
895 };
896 
897 struct rtw89_pci_dma_ring {
898 	void *head;
899 	u8 desc_size;
900 	dma_addr_t dma;
901 
902 	struct rtw89_pci_ch_dma_addr addr;
903 
904 	u32 len;
905 	u32 wp; /* host idx */
906 	u32 rp; /* hw idx */
907 };
908 
909 struct rtw89_pci_tx_wd_ring {
910 	void *head;
911 	dma_addr_t dma;
912 
913 	struct rtw89_pci_tx_wd pages[RTW89_PCI_TXWD_NUM_MAX];
914 	struct list_head free_pages;
915 
916 	u32 page_size;
917 	u32 page_num;
918 	u32 curr_num;
919 };
920 
921 #define RTW89_RX_TAG_MAX		0x1fff
922 
923 struct rtw89_pci_tx_ring {
924 	struct rtw89_pci_tx_wd_ring wd_ring;
925 	struct rtw89_pci_dma_ring bd_ring;
926 	struct list_head busy_pages;
927 	u8 txch;
928 	bool dma_enabled;
929 	u16 tag; /* range from 0x0001 ~ 0x1fff */
930 
931 	u64 tx_cnt;
932 	u64 tx_acked;
933 	u64 tx_retry_lmt;
934 	u64 tx_life_time;
935 	u64 tx_mac_id_drop;
936 };
937 
938 struct rtw89_pci_rx_ring {
939 	struct rtw89_pci_dma_ring bd_ring;
940 	struct sk_buff *buf[RTW89_PCI_RXBD_NUM_MAX];
941 	u32 buf_sz;
942 	struct sk_buff *diliver_skb;
943 	struct rtw89_rx_desc_info diliver_desc;
944 };
945 
946 struct rtw89_pci_isrs {
947 	u32 ind_isrs;
948 	u32 halt_c2h_isrs;
949 	u32 isrs[2];
950 };
951 
952 struct rtw89_pci {
953 	struct pci_dev *pdev;
954 
955 	/* protect HW irq related registers */
956 	spinlock_t irq_lock;
957 	/* protect TRX resources (exclude RXQ) */
958 	spinlock_t trx_lock;
959 	bool running;
960 	bool low_power;
961 	bool under_recovery;
962 	struct rtw89_pci_tx_ring tx_rings[RTW89_TXCH_NUM];
963 	struct rtw89_pci_rx_ring rx_rings[RTW89_RXCH_NUM];
964 	struct sk_buff_head h2c_queue;
965 	struct sk_buff_head h2c_release_queue;
966 	DECLARE_BITMAP(kick_map, RTW89_TXCH_NUM);
967 
968 	u32 ind_intrs;
969 	u32 halt_c2h_intrs;
970 	u32 intrs[2];
971 	void __iomem *mmap;
972 };
973 
974 static inline struct rtw89_pci_rx_info *RTW89_PCI_RX_SKB_CB(struct sk_buff *skb)
975 {
976 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
977 
978 	BUILD_BUG_ON(sizeof(struct rtw89_pci_tx_data) >
979 		     sizeof(info->status.status_driver_data));
980 
981 	return (struct rtw89_pci_rx_info *)skb->cb;
982 }
983 
984 static inline struct rtw89_pci_rx_bd_32 *
985 RTW89_PCI_RX_BD(struct rtw89_pci_rx_ring *rx_ring, u32 idx)
986 {
987 	struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
988 	u8 *head = bd_ring->head;
989 	u32 desc_size = bd_ring->desc_size;
990 	u32 offset = idx * desc_size;
991 
992 	return (struct rtw89_pci_rx_bd_32 *)(head + offset);
993 }
994 
995 static inline void
996 rtw89_pci_rxbd_increase(struct rtw89_pci_rx_ring *rx_ring, u32 cnt)
997 {
998 	struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
999 
1000 	bd_ring->wp += cnt;
1001 
1002 	if (bd_ring->wp >= bd_ring->len)
1003 		bd_ring->wp -= bd_ring->len;
1004 }
1005 
1006 static inline struct rtw89_pci_tx_data *RTW89_PCI_TX_SKB_CB(struct sk_buff *skb)
1007 {
1008 	struct rtw89_tx_skb_data *data = RTW89_TX_SKB_CB(skb);
1009 
1010 	return (struct rtw89_pci_tx_data *)data->hci_priv;
1011 }
1012 
1013 static inline struct rtw89_pci_tx_bd_32 *
1014 rtw89_pci_get_next_txbd(struct rtw89_pci_tx_ring *tx_ring)
1015 {
1016 	struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring;
1017 	struct rtw89_pci_tx_bd_32 *tx_bd, *head;
1018 
1019 	head = bd_ring->head;
1020 	tx_bd = head + bd_ring->wp;
1021 
1022 	return tx_bd;
1023 }
1024 
1025 static inline struct rtw89_pci_tx_wd *
1026 rtw89_pci_dequeue_txwd(struct rtw89_pci_tx_ring *tx_ring)
1027 {
1028 	struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
1029 	struct rtw89_pci_tx_wd *txwd;
1030 
1031 	txwd = list_first_entry_or_null(&wd_ring->free_pages,
1032 					struct rtw89_pci_tx_wd, list);
1033 	if (!txwd)
1034 		return NULL;
1035 
1036 	list_del_init(&txwd->list);
1037 	txwd->len = 0;
1038 	wd_ring->curr_num--;
1039 
1040 	return txwd;
1041 }
1042 
1043 static inline void
1044 rtw89_pci_enqueue_txwd(struct rtw89_pci_tx_ring *tx_ring,
1045 		       struct rtw89_pci_tx_wd *txwd)
1046 {
1047 	struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
1048 
1049 	memset(txwd->vaddr, 0, wd_ring->page_size);
1050 	list_add_tail(&txwd->list, &wd_ring->free_pages);
1051 	wd_ring->curr_num++;
1052 }
1053 
1054 static inline bool rtw89_pci_ltr_is_err_reg_val(u32 val)
1055 {
1056 	return val == 0xffffffff || val == 0xeaeaeaea;
1057 }
1058 
1059 extern const struct dev_pm_ops rtw89_pm_ops;
1060 extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set;
1061 extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_v1;
1062 extern const struct rtw89_pci_bd_ram rtw89_bd_ram_table_dual[RTW89_TXCH_NUM];
1063 extern const struct rtw89_pci_bd_ram rtw89_bd_ram_table_single[RTW89_TXCH_NUM];
1064 
1065 struct pci_device_id;
1066 
1067 int rtw89_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
1068 void rtw89_pci_remove(struct pci_dev *pdev);
1069 int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev, bool en);
1070 int rtw89_pci_ltr_set_v1(struct rtw89_dev *rtwdev, bool en);
1071 u32 rtw89_pci_fill_txaddr_info(struct rtw89_dev *rtwdev,
1072 			       void *txaddr_info_addr, u32 total_len,
1073 			       dma_addr_t dma, u8 *add_info_nr);
1074 u32 rtw89_pci_fill_txaddr_info_v1(struct rtw89_dev *rtwdev,
1075 				  void *txaddr_info_addr, u32 total_len,
1076 				  dma_addr_t dma, u8 *add_info_nr);
1077 void rtw89_pci_config_intr_mask(struct rtw89_dev *rtwdev);
1078 void rtw89_pci_config_intr_mask_v1(struct rtw89_dev *rtwdev);
1079 void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1080 void rtw89_pci_disable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1081 void rtw89_pci_enable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1082 void rtw89_pci_disable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1083 void rtw89_pci_recognize_intrs(struct rtw89_dev *rtwdev,
1084 			       struct rtw89_pci *rtwpci,
1085 			       struct rtw89_pci_isrs *isrs);
1086 void rtw89_pci_recognize_intrs_v1(struct rtw89_dev *rtwdev,
1087 				  struct rtw89_pci *rtwpci,
1088 				  struct rtw89_pci_isrs *isrs);
1089 
1090 static inline
1091 u32 rtw89_chip_fill_txaddr_info(struct rtw89_dev *rtwdev,
1092 				void *txaddr_info_addr, u32 total_len,
1093 				dma_addr_t dma, u8 *add_info_nr)
1094 {
1095 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1096 
1097 	return info->fill_txaddr_info(rtwdev, txaddr_info_addr, total_len,
1098 				      dma, add_info_nr);
1099 }
1100 
1101 static inline void rtw89_chip_config_intr_mask(struct rtw89_dev *rtwdev,
1102 					       enum rtw89_pci_intr_mask_cfg cfg)
1103 {
1104 	struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1105 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1106 
1107 	switch (cfg) {
1108 	default:
1109 	case RTW89_PCI_INTR_MASK_RESET:
1110 		rtwpci->low_power = false;
1111 		rtwpci->under_recovery = false;
1112 		break;
1113 	case RTW89_PCI_INTR_MASK_NORMAL:
1114 		rtwpci->low_power = false;
1115 		break;
1116 	case RTW89_PCI_INTR_MASK_LOW_POWER:
1117 		rtwpci->low_power = true;
1118 		break;
1119 	case RTW89_PCI_INTR_MASK_RECOVERY_START:
1120 		rtwpci->under_recovery = true;
1121 		break;
1122 	case RTW89_PCI_INTR_MASK_RECOVERY_COMPLETE:
1123 		rtwpci->under_recovery = false;
1124 		break;
1125 	}
1126 
1127 	rtw89_debug(rtwdev, RTW89_DBG_HCI,
1128 		    "Configure PCI interrupt mask mode low_power=%d under_recovery=%d\n",
1129 		    rtwpci->low_power, rtwpci->under_recovery);
1130 
1131 	info->config_intr_mask(rtwdev);
1132 }
1133 
1134 static inline
1135 void rtw89_chip_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
1136 {
1137 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1138 
1139 	info->enable_intr(rtwdev, rtwpci);
1140 }
1141 
1142 static inline
1143 void rtw89_chip_disable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
1144 {
1145 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1146 
1147 	info->disable_intr(rtwdev, rtwpci);
1148 }
1149 
1150 static inline
1151 void rtw89_chip_recognize_intrs(struct rtw89_dev *rtwdev,
1152 				struct rtw89_pci *rtwpci,
1153 				struct rtw89_pci_isrs *isrs)
1154 {
1155 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1156 
1157 	info->recognize_intrs(rtwdev, rtwpci, isrs);
1158 }
1159 
1160 #endif
1161