1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_PCI_H__ 6 #define __RTW89_PCI_H__ 7 8 #include "txrx.h" 9 10 #define MDIO_PG0_G1 0 11 #define MDIO_PG1_G1 1 12 #define MDIO_PG0_G2 2 13 #define MDIO_PG1_G2 3 14 #define RAC_ANA10 0x10 15 #define RAC_REG_REV2 0x1B 16 #define BAC_CMU_EN_DLY_MASK GENMASK(15, 12) 17 #define PCIE_DPHY_DLY_25US 0x1 18 #define RAC_ANA19 0x19 19 #define RAC_ANA1F 0x1F 20 #define RAC_ANA24 0x24 21 #define B_AX_DEGLITCH GENMASK(11, 8) 22 #define RAC_ANA26 0x26 23 #define B_AX_RXEN GENMASK(15, 14) 24 #define RAC_CTRL_PPR_V1 0x30 25 #define B_AX_CLK_CALIB_EN BIT(12) 26 #define B_AX_CALIB_EN BIT(13) 27 #define B_AX_DIV GENMASK(15, 14) 28 #define RAC_SET_PPR_V1 0x31 29 30 #define R_AX_DBI_FLAG 0x1090 31 #define B_AX_DBI_RFLAG BIT(17) 32 #define B_AX_DBI_WFLAG BIT(16) 33 #define B_AX_DBI_WREN_MSK GENMASK(15, 12) 34 #define B_AX_DBI_ADDR_MSK GENMASK(11, 2) 35 #define R_AX_DBI_WDATA 0x1094 36 #define R_AX_DBI_RDATA 0x1098 37 38 #define R_AX_MDIO_WDATA 0x10A4 39 #define R_AX_MDIO_RDATA 0x10A6 40 41 #define R_AX_PCIE_PS_CTRL_V1 0x3008 42 #define B_AX_CMAC_EXIT_L1_EN BIT(7) 43 #define B_AX_DMAC0_EXIT_L1_EN BIT(6) 44 #define B_AX_SEL_XFER_PENDING BIT(3) 45 #define B_AX_SEL_REQ_ENTR_L1 BIT(2) 46 #define B_AX_SEL_REQ_EXIT_L1 BIT(0) 47 48 #define R_AX_PCIE_BG_CLR 0x303C 49 #define B_AX_BG_CLR_ASYNC_M3 BIT(4) 50 51 #define R_AX_PCIE_IO_RCY_M1 0x3100 52 #define B_AX_PCIE_IO_RCY_P_M1 BIT(5) 53 #define B_AX_PCIE_IO_RCY_WDT_P_M1 BIT(4) 54 #define B_AX_PCIE_IO_RCY_WDT_MODE_M1 BIT(3) 55 #define B_AX_PCIE_IO_RCY_TRIG_M1 BIT(0) 56 57 #define R_AX_PCIE_WDT_TIMER_M1 0x3104 58 #define B_AX_PCIE_WDT_TIMER_M1_MASK GENMASK(31, 0) 59 60 #define R_AX_PCIE_IO_RCY_M2 0x310C 61 #define B_AX_PCIE_IO_RCY_P_M2 BIT(5) 62 #define B_AX_PCIE_IO_RCY_WDT_P_M2 BIT(4) 63 #define B_AX_PCIE_IO_RCY_WDT_MODE_M2 BIT(3) 64 #define B_AX_PCIE_IO_RCY_TRIG_M2 BIT(0) 65 66 #define R_AX_PCIE_WDT_TIMER_M2 0x3110 67 #define B_AX_PCIE_WDT_TIMER_M2_MASK GENMASK(31, 0) 68 69 #define R_AX_PCIE_IO_RCY_E0 0x3118 70 #define B_AX_PCIE_IO_RCY_P_E0 BIT(5) 71 #define B_AX_PCIE_IO_RCY_WDT_P_E0 BIT(4) 72 #define B_AX_PCIE_IO_RCY_WDT_MODE_E0 BIT(3) 73 #define B_AX_PCIE_IO_RCY_TRIG_E0 BIT(0) 74 75 #define R_AX_PCIE_WDT_TIMER_E0 0x311C 76 #define B_AX_PCIE_WDT_TIMER_E0_MASK GENMASK(31, 0) 77 78 #define R_AX_PCIE_IO_RCY_S1 0x3124 79 #define B_AX_PCIE_IO_RCY_RP_S1 BIT(7) 80 #define B_AX_PCIE_IO_RCY_WP_S1 BIT(6) 81 #define B_AX_PCIE_IO_RCY_WDT_RP_S1 BIT(5) 82 #define B_AX_PCIE_IO_RCY_WDT_WP_S1 BIT(4) 83 #define B_AX_PCIE_IO_RCY_WDT_MODE_S1 BIT(3) 84 #define B_AX_PCIE_IO_RCY_RTRIG_S1 BIT(1) 85 #define B_AX_PCIE_IO_RCY_WTRIG_S1 BIT(0) 86 87 #define R_AX_PCIE_WDT_TIMER_S1 0x3128 88 #define B_AX_PCIE_WDT_TIMER_S1_MASK GENMASK(31, 0) 89 90 #define R_RAC_DIRECT_OFFSET_G1 0x3800 91 #define R_RAC_DIRECT_OFFSET_G2 0x3880 92 93 #define RTW89_PCI_WR_RETRY_CNT 20 94 95 /* Interrupts */ 96 #define R_AX_HIMR0 0x01A0 97 #define B_AX_HALT_C2H_INT_EN BIT(21) 98 #define R_AX_HISR0 0x01A4 99 100 #define R_AX_HIMR1 0x01A8 101 #define B_AX_GPIO18_INT_EN BIT(2) 102 #define B_AX_GPIO17_INT_EN BIT(1) 103 #define B_AX_GPIO16_INT_EN BIT(0) 104 105 #define R_AX_HISR1 0x01AC 106 #define B_AX_GPIO18_INT BIT(2) 107 #define B_AX_GPIO17_INT BIT(1) 108 #define B_AX_GPIO16_INT BIT(0) 109 110 #define R_AX_MDIO_CFG 0x10A0 111 #define B_AX_MDIO_PHY_ADDR_MASK GENMASK(13, 12) 112 #define B_AX_MDIO_RFLAG BIT(9) 113 #define B_AX_MDIO_WFLAG BIT(8) 114 #define B_AX_MDIO_ADDR_MASK GENMASK(4, 0) 115 116 #define R_AX_PCIE_HIMR00 0x10B0 117 #define R_AX_HAXI_HIMR00 0x10B0 118 #define B_AX_HC00ISR_IND_INT_EN BIT(27) 119 #define B_AX_HD1ISR_IND_INT_EN BIT(26) 120 #define B_AX_HD0ISR_IND_INT_EN BIT(25) 121 #define B_AX_HS0ISR_IND_INT_EN BIT(24) 122 #define B_AX_RETRAIN_INT_EN BIT(21) 123 #define B_AX_RPQBD_FULL_INT_EN BIT(20) 124 #define B_AX_RDU_INT_EN BIT(19) 125 #define B_AX_RXDMA_STUCK_INT_EN BIT(18) 126 #define B_AX_TXDMA_STUCK_INT_EN BIT(17) 127 #define B_AX_PCIE_HOTRST_INT_EN BIT(16) 128 #define B_AX_PCIE_FLR_INT_EN BIT(15) 129 #define B_AX_PCIE_PERST_INT_EN BIT(14) 130 #define B_AX_TXDMA_CH12_INT_EN BIT(13) 131 #define B_AX_TXDMA_CH9_INT_EN BIT(12) 132 #define B_AX_TXDMA_CH8_INT_EN BIT(11) 133 #define B_AX_TXDMA_ACH7_INT_EN BIT(10) 134 #define B_AX_TXDMA_ACH6_INT_EN BIT(9) 135 #define B_AX_TXDMA_ACH5_INT_EN BIT(8) 136 #define B_AX_TXDMA_ACH4_INT_EN BIT(7) 137 #define B_AX_TXDMA_ACH3_INT_EN BIT(6) 138 #define B_AX_TXDMA_ACH2_INT_EN BIT(5) 139 #define B_AX_TXDMA_ACH1_INT_EN BIT(4) 140 #define B_AX_TXDMA_ACH0_INT_EN BIT(3) 141 #define B_AX_RPQDMA_INT_EN BIT(2) 142 #define B_AX_RXP1DMA_INT_EN BIT(1) 143 #define B_AX_RXDMA_INT_EN BIT(0) 144 145 #define R_AX_PCIE_HISR00 0x10B4 146 #define R_AX_HAXI_HISR00 0x10B4 147 #define B_AX_HC00ISR_IND_INT BIT(27) 148 #define B_AX_HD1ISR_IND_INT BIT(26) 149 #define B_AX_HD0ISR_IND_INT BIT(25) 150 #define B_AX_HS0ISR_IND_INT BIT(24) 151 #define B_AX_RETRAIN_INT BIT(21) 152 #define B_AX_RPQBD_FULL_INT BIT(20) 153 #define B_AX_RDU_INT BIT(19) 154 #define B_AX_RXDMA_STUCK_INT BIT(18) 155 #define B_AX_TXDMA_STUCK_INT BIT(17) 156 #define B_AX_PCIE_HOTRST_INT BIT(16) 157 #define B_AX_PCIE_FLR_INT BIT(15) 158 #define B_AX_PCIE_PERST_INT BIT(14) 159 #define B_AX_TXDMA_CH12_INT BIT(13) 160 #define B_AX_TXDMA_CH9_INT BIT(12) 161 #define B_AX_TXDMA_CH8_INT BIT(11) 162 #define B_AX_TXDMA_ACH7_INT BIT(10) 163 #define B_AX_TXDMA_ACH6_INT BIT(9) 164 #define B_AX_TXDMA_ACH5_INT BIT(8) 165 #define B_AX_TXDMA_ACH4_INT BIT(7) 166 #define B_AX_TXDMA_ACH3_INT BIT(6) 167 #define B_AX_TXDMA_ACH2_INT BIT(5) 168 #define B_AX_TXDMA_ACH1_INT BIT(4) 169 #define B_AX_TXDMA_ACH0_INT BIT(3) 170 #define B_AX_RPQDMA_INT BIT(2) 171 #define B_AX_RXP1DMA_INT BIT(1) 172 #define B_AX_RXDMA_INT BIT(0) 173 174 #define R_AX_HAXI_HIMR10 0x11E0 175 #define B_AX_TXDMA_CH11_INT_EN_V1 BIT(1) 176 #define B_AX_TXDMA_CH10_INT_EN_V1 BIT(0) 177 178 #define R_AX_PCIE_HIMR10 0x13B0 179 #define B_AX_HC10ISR_IND_INT_EN BIT(28) 180 #define B_AX_TXDMA_CH11_INT_EN BIT(12) 181 #define B_AX_TXDMA_CH10_INT_EN BIT(11) 182 183 #define R_AX_PCIE_HISR10 0x13B4 184 #define B_AX_HC10ISR_IND_INT BIT(28) 185 #define B_AX_TXDMA_CH11_INT BIT(12) 186 #define B_AX_TXDMA_CH10_INT BIT(11) 187 188 #define R_AX_PCIE_HIMR00_V1 0x30B0 189 #define B_AX_HCI_AXIDMA_INT_EN BIT(29) 190 #define B_AX_HC00ISR_IND_INT_EN_V1 BIT(28) 191 #define B_AX_HD1ISR_IND_INT_EN_V1 BIT(27) 192 #define B_AX_HD0ISR_IND_INT_EN_V1 BIT(26) 193 #define B_AX_HS1ISR_IND_INT_EN BIT(25) 194 #define B_AX_PCIE_DBG_STE_INT_EN BIT(13) 195 196 #define R_AX_PCIE_HISR00_V1 0x30B4 197 #define B_AX_HCI_AXIDMA_INT BIT(29) 198 #define B_AX_HC00ISR_IND_INT_V1 BIT(28) 199 #define B_AX_HD1ISR_IND_INT_V1 BIT(27) 200 #define B_AX_HD0ISR_IND_INT_V1 BIT(26) 201 #define B_AX_HS1ISR_IND_INT BIT(25) 202 #define B_AX_PCIE_DBG_STE_INT BIT(13) 203 204 /* TX/RX */ 205 #define R_AX_DRV_FW_HSK_0 0x01B0 206 #define R_AX_DRV_FW_HSK_1 0x01B4 207 #define R_AX_DRV_FW_HSK_2 0x01B8 208 #define R_AX_DRV_FW_HSK_3 0x01BC 209 #define R_AX_DRV_FW_HSK_4 0x01C0 210 #define R_AX_DRV_FW_HSK_5 0x01C4 211 #define R_AX_DRV_FW_HSK_6 0x01C8 212 #define R_AX_DRV_FW_HSK_7 0x01CC 213 214 #define R_AX_RXQ_RXBD_IDX 0x1050 215 #define R_AX_RPQ_RXBD_IDX 0x1054 216 #define R_AX_ACH0_TXBD_IDX 0x1058 217 #define R_AX_ACH1_TXBD_IDX 0x105C 218 #define R_AX_ACH2_TXBD_IDX 0x1060 219 #define R_AX_ACH3_TXBD_IDX 0x1064 220 #define R_AX_ACH4_TXBD_IDX 0x1068 221 #define R_AX_ACH5_TXBD_IDX 0x106C 222 #define R_AX_ACH6_TXBD_IDX 0x1070 223 #define R_AX_ACH7_TXBD_IDX 0x1074 224 #define R_AX_CH8_TXBD_IDX 0x1078 /* Management Queue band 0 */ 225 #define R_AX_CH9_TXBD_IDX 0x107C /* HI Queue band 0 */ 226 #define R_AX_CH10_TXBD_IDX 0x137C /* Management Queue band 1 */ 227 #define R_AX_CH11_TXBD_IDX 0x1380 /* HI Queue band 1 */ 228 #define R_AX_CH12_TXBD_IDX 0x1080 /* FWCMD Queue */ 229 #define R_AX_CH10_TXBD_IDX_V1 0x11D0 230 #define R_AX_CH11_TXBD_IDX_V1 0x11D4 231 #define R_AX_RXQ_RXBD_IDX_V1 0x1218 232 #define R_AX_RPQ_RXBD_IDX_V1 0x121C 233 #define TXBD_HW_IDX_MASK GENMASK(27, 16) 234 #define TXBD_HOST_IDX_MASK GENMASK(11, 0) 235 236 #define R_AX_ACH0_TXBD_DESA_L 0x1110 237 #define R_AX_ACH0_TXBD_DESA_H 0x1114 238 #define R_AX_ACH1_TXBD_DESA_L 0x1118 239 #define R_AX_ACH1_TXBD_DESA_H 0x111C 240 #define R_AX_ACH2_TXBD_DESA_L 0x1120 241 #define R_AX_ACH2_TXBD_DESA_H 0x1124 242 #define R_AX_ACH3_TXBD_DESA_L 0x1128 243 #define R_AX_ACH3_TXBD_DESA_H 0x112C 244 #define R_AX_ACH4_TXBD_DESA_L 0x1130 245 #define R_AX_ACH4_TXBD_DESA_H 0x1134 246 #define R_AX_ACH5_TXBD_DESA_L 0x1138 247 #define R_AX_ACH5_TXBD_DESA_H 0x113C 248 #define R_AX_ACH6_TXBD_DESA_L 0x1140 249 #define R_AX_ACH6_TXBD_DESA_H 0x1144 250 #define R_AX_ACH7_TXBD_DESA_L 0x1148 251 #define R_AX_ACH7_TXBD_DESA_H 0x114C 252 #define R_AX_CH8_TXBD_DESA_L 0x1150 253 #define R_AX_CH8_TXBD_DESA_H 0x1154 254 #define R_AX_CH9_TXBD_DESA_L 0x1158 255 #define R_AX_CH9_TXBD_DESA_H 0x115C 256 #define R_AX_CH10_TXBD_DESA_L 0x1358 257 #define R_AX_CH10_TXBD_DESA_H 0x135C 258 #define R_AX_CH11_TXBD_DESA_L 0x1360 259 #define R_AX_CH11_TXBD_DESA_H 0x1364 260 #define R_AX_CH12_TXBD_DESA_L 0x1160 261 #define R_AX_CH12_TXBD_DESA_H 0x1164 262 #define R_AX_RXQ_RXBD_DESA_L 0x1100 263 #define R_AX_RXQ_RXBD_DESA_H 0x1104 264 #define R_AX_RPQ_RXBD_DESA_L 0x1108 265 #define R_AX_RPQ_RXBD_DESA_H 0x110C 266 #define R_AX_RXQ_RXBD_DESA_L_V1 0x1220 267 #define R_AX_RXQ_RXBD_DESA_H_V1 0x1224 268 #define R_AX_RPQ_RXBD_DESA_L_V1 0x1228 269 #define R_AX_RPQ_RXBD_DESA_H_V1 0x122C 270 #define R_AX_ACH0_TXBD_DESA_L_V1 0x1230 271 #define R_AX_ACH0_TXBD_DESA_H_V1 0x1234 272 #define R_AX_ACH1_TXBD_DESA_L_V1 0x1238 273 #define R_AX_ACH1_TXBD_DESA_H_V1 0x123C 274 #define R_AX_ACH2_TXBD_DESA_L_V1 0x1240 275 #define R_AX_ACH2_TXBD_DESA_H_V1 0x1244 276 #define R_AX_ACH3_TXBD_DESA_L_V1 0x1248 277 #define R_AX_ACH3_TXBD_DESA_H_V1 0x124C 278 #define R_AX_ACH4_TXBD_DESA_L_V1 0x1250 279 #define R_AX_ACH4_TXBD_DESA_H_V1 0x1254 280 #define R_AX_ACH5_TXBD_DESA_L_V1 0x1258 281 #define R_AX_ACH5_TXBD_DESA_H_V1 0x125C 282 #define R_AX_ACH6_TXBD_DESA_L_V1 0x1260 283 #define R_AX_ACH6_TXBD_DESA_H_V1 0x1264 284 #define R_AX_ACH7_TXBD_DESA_L_V1 0x1268 285 #define R_AX_ACH7_TXBD_DESA_H_V1 0x126C 286 #define R_AX_CH8_TXBD_DESA_L_V1 0x1270 287 #define R_AX_CH8_TXBD_DESA_H_V1 0x1274 288 #define R_AX_CH9_TXBD_DESA_L_V1 0x1278 289 #define R_AX_CH9_TXBD_DESA_H_V1 0x127C 290 #define R_AX_CH12_TXBD_DESA_L_V1 0x1280 291 #define R_AX_CH12_TXBD_DESA_H_V1 0x1284 292 #define R_AX_CH10_TXBD_DESA_L_V1 0x1458 293 #define R_AX_CH10_TXBD_DESA_H_V1 0x145C 294 #define R_AX_CH11_TXBD_DESA_L_V1 0x1460 295 #define R_AX_CH11_TXBD_DESA_H_V1 0x1464 296 #define B_AX_DESC_NUM_MSK GENMASK(11, 0) 297 298 #define R_AX_RXQ_RXBD_NUM 0x1020 299 #define R_AX_RPQ_RXBD_NUM 0x1022 300 #define R_AX_ACH0_TXBD_NUM 0x1024 301 #define R_AX_ACH1_TXBD_NUM 0x1026 302 #define R_AX_ACH2_TXBD_NUM 0x1028 303 #define R_AX_ACH3_TXBD_NUM 0x102A 304 #define R_AX_ACH4_TXBD_NUM 0x102C 305 #define R_AX_ACH5_TXBD_NUM 0x102E 306 #define R_AX_ACH6_TXBD_NUM 0x1030 307 #define R_AX_ACH7_TXBD_NUM 0x1032 308 #define R_AX_CH8_TXBD_NUM 0x1034 309 #define R_AX_CH9_TXBD_NUM 0x1036 310 #define R_AX_CH10_TXBD_NUM 0x1338 311 #define R_AX_CH11_TXBD_NUM 0x133A 312 #define R_AX_CH12_TXBD_NUM 0x1038 313 #define R_AX_RXQ_RXBD_NUM_V1 0x1210 314 #define R_AX_RPQ_RXBD_NUM_V1 0x1212 315 #define R_AX_CH10_TXBD_NUM_V1 0x1438 316 #define R_AX_CH11_TXBD_NUM_V1 0x143A 317 318 #define R_AX_ACH0_BDRAM_CTRL 0x1200 319 #define R_AX_ACH1_BDRAM_CTRL 0x1204 320 #define R_AX_ACH2_BDRAM_CTRL 0x1208 321 #define R_AX_ACH3_BDRAM_CTRL 0x120C 322 #define R_AX_ACH4_BDRAM_CTRL 0x1210 323 #define R_AX_ACH5_BDRAM_CTRL 0x1214 324 #define R_AX_ACH6_BDRAM_CTRL 0x1218 325 #define R_AX_ACH7_BDRAM_CTRL 0x121C 326 #define R_AX_CH8_BDRAM_CTRL 0x1220 327 #define R_AX_CH9_BDRAM_CTRL 0x1224 328 #define R_AX_CH10_BDRAM_CTRL 0x1320 329 #define R_AX_CH11_BDRAM_CTRL 0x1324 330 #define R_AX_CH12_BDRAM_CTRL 0x1228 331 #define R_AX_ACH0_BDRAM_CTRL_V1 0x1300 332 #define R_AX_ACH1_BDRAM_CTRL_V1 0x1304 333 #define R_AX_ACH2_BDRAM_CTRL_V1 0x1308 334 #define R_AX_ACH3_BDRAM_CTRL_V1 0x130C 335 #define R_AX_ACH4_BDRAM_CTRL_V1 0x1310 336 #define R_AX_ACH5_BDRAM_CTRL_V1 0x1314 337 #define R_AX_ACH6_BDRAM_CTRL_V1 0x1318 338 #define R_AX_ACH7_BDRAM_CTRL_V1 0x131C 339 #define R_AX_CH8_BDRAM_CTRL_V1 0x1320 340 #define R_AX_CH9_BDRAM_CTRL_V1 0x1324 341 #define R_AX_CH12_BDRAM_CTRL_V1 0x1328 342 #define R_AX_CH10_BDRAM_CTRL_V1 0x1420 343 #define R_AX_CH11_BDRAM_CTRL_V1 0x1424 344 #define BDRAM_SIDX_MASK GENMASK(7, 0) 345 #define BDRAM_MAX_MASK GENMASK(15, 8) 346 #define BDRAM_MIN_MASK GENMASK(23, 16) 347 348 #define R_AX_PCIE_INIT_CFG1 0x1000 349 #define B_AX_PCIE_RXRST_KEEP_REG BIT(23) 350 #define B_AX_PCIE_TXRST_KEEP_REG BIT(22) 351 #define B_AX_PCIE_PERST_KEEP_REG BIT(21) 352 #define B_AX_PCIE_FLR_KEEP_REG BIT(20) 353 #define B_AX_PCIE_TRAIN_KEEP_REG BIT(19) 354 #define B_AX_RXBD_MODE BIT(18) 355 #define B_AX_PCIE_MAX_RXDMA_MASK GENMASK(16, 14) 356 #define B_AX_RXHCI_EN BIT(13) 357 #define B_AX_LATENCY_CONTROL BIT(12) 358 #define B_AX_TXHCI_EN BIT(11) 359 #define B_AX_PCIE_MAX_TXDMA_MASK GENMASK(10, 8) 360 #define B_AX_TX_TRUNC_MODE BIT(5) 361 #define B_AX_RX_TRUNC_MODE BIT(4) 362 #define B_AX_RST_BDRAM BIT(3) 363 #define B_AX_DIS_RXDMA_PRE BIT(2) 364 365 #define R_AX_TXDMA_ADDR_H 0x10F0 366 #define R_AX_RXDMA_ADDR_H 0x10F4 367 368 #define R_AX_PCIE_DMA_STOP1 0x1010 369 #define B_AX_STOP_PCIEIO BIT(20) 370 #define B_AX_STOP_WPDMA BIT(19) 371 #define B_AX_STOP_CH12 BIT(18) 372 #define B_AX_STOP_CH9 BIT(17) 373 #define B_AX_STOP_CH8 BIT(16) 374 #define B_AX_STOP_ACH7 BIT(15) 375 #define B_AX_STOP_ACH6 BIT(14) 376 #define B_AX_STOP_ACH5 BIT(13) 377 #define B_AX_STOP_ACH4 BIT(12) 378 #define B_AX_STOP_ACH3 BIT(11) 379 #define B_AX_STOP_ACH2 BIT(10) 380 #define B_AX_STOP_ACH1 BIT(9) 381 #define B_AX_STOP_ACH0 BIT(8) 382 #define B_AX_STOP_RPQ BIT(1) 383 #define B_AX_STOP_RXQ BIT(0) 384 #define B_AX_TX_STOP1_ALL GENMASK(18, 8) 385 386 #define R_AX_PCIE_DMA_STOP2 0x1310 387 #define B_AX_STOP_CH11 BIT(1) 388 #define B_AX_STOP_CH10 BIT(0) 389 #define B_AX_TX_STOP2_ALL GENMASK(1, 0) 390 391 #define R_AX_TXBD_RWPTR_CLR1 0x1014 392 #define B_AX_CLR_CH12_IDX BIT(10) 393 #define B_AX_CLR_CH9_IDX BIT(9) 394 #define B_AX_CLR_CH8_IDX BIT(8) 395 #define B_AX_CLR_ACH7_IDX BIT(7) 396 #define B_AX_CLR_ACH6_IDX BIT(6) 397 #define B_AX_CLR_ACH5_IDX BIT(5) 398 #define B_AX_CLR_ACH4_IDX BIT(4) 399 #define B_AX_CLR_ACH3_IDX BIT(3) 400 #define B_AX_CLR_ACH2_IDX BIT(2) 401 #define B_AX_CLR_ACH1_IDX BIT(1) 402 #define B_AX_CLR_ACH0_IDX BIT(0) 403 #define B_AX_TXBD_CLR1_ALL GENMASK(10, 0) 404 405 #define R_AX_RXBD_RWPTR_CLR 0x1018 406 #define B_AX_CLR_RPQ_IDX BIT(1) 407 #define B_AX_CLR_RXQ_IDX BIT(0) 408 #define B_AX_RXBD_CLR_ALL GENMASK(1, 0) 409 410 #define R_AX_TXBD_RWPTR_CLR2 0x1314 411 #define B_AX_CLR_CH11_IDX BIT(1) 412 #define B_AX_CLR_CH10_IDX BIT(0) 413 #define B_AX_TXBD_CLR2_ALL GENMASK(1, 0) 414 415 #define R_AX_PCIE_DMA_BUSY1 0x101C 416 #define B_AX_PCIEIO_RX_BUSY BIT(22) 417 #define B_AX_PCIEIO_TX_BUSY BIT(21) 418 #define B_AX_PCIEIO_BUSY BIT(20) 419 #define B_AX_WPDMA_BUSY BIT(19) 420 #define B_AX_CH12_BUSY BIT(18) 421 #define B_AX_CH9_BUSY BIT(17) 422 #define B_AX_CH8_BUSY BIT(16) 423 #define B_AX_ACH7_BUSY BIT(15) 424 #define B_AX_ACH6_BUSY BIT(14) 425 #define B_AX_ACH5_BUSY BIT(13) 426 #define B_AX_ACH4_BUSY BIT(12) 427 #define B_AX_ACH3_BUSY BIT(11) 428 #define B_AX_ACH2_BUSY BIT(10) 429 #define B_AX_ACH1_BUSY BIT(9) 430 #define B_AX_ACH0_BUSY BIT(8) 431 #define B_AX_RPQ_BUSY BIT(1) 432 #define B_AX_RXQ_BUSY BIT(0) 433 434 #define R_AX_PCIE_DMA_BUSY2 0x131C 435 #define B_AX_CH11_BUSY BIT(1) 436 #define B_AX_CH10_BUSY BIT(0) 437 438 /* Configure */ 439 #define R_AX_PCIE_INIT_CFG2 0x1004 440 #define B_AX_WD_ITVL_IDLE GENMASK(27, 24) 441 #define B_AX_WD_ITVL_ACT GENMASK(19, 16) 442 #define B_AX_PCIE_RX_APPLEN_MASK GENMASK(13, 0) 443 444 #define R_AX_PCIE_PS_CTRL 0x1008 445 #define B_AX_L1OFF_PWR_OFF_EN BIT(5) 446 447 #define R_AX_INT_MIT_RX 0x10D4 448 #define B_AX_RXMIT_RXP2_SEL BIT(19) 449 #define B_AX_RXMIT_RXP1_SEL BIT(18) 450 #define B_AX_RXTIMER_UNIT_MASK GENMASK(17, 16) 451 #define AX_RXTIMER_UNIT_64US 0 452 #define AX_RXTIMER_UNIT_128US 1 453 #define AX_RXTIMER_UNIT_256US 2 454 #define AX_RXTIMER_UNIT_512US 3 455 #define B_AX_RXCOUNTER_MATCH_MASK GENMASK(15, 8) 456 #define B_AX_RXTIMER_MATCH_MASK GENMASK(7, 0) 457 458 #define R_AX_DBG_ERR_FLAG 0x11C4 459 #define B_AX_PCIE_RPQ_FULL BIT(29) 460 #define B_AX_PCIE_RXQ_FULL BIT(28) 461 #define B_AX_CPL_STATUS_MASK GENMASK(27, 25) 462 #define B_AX_RX_STUCK BIT(22) 463 #define B_AX_TX_STUCK BIT(21) 464 #define B_AX_PCIEDBG_TXERR0 BIT(16) 465 #define B_AX_PCIE_RXP1_ERR0 BIT(4) 466 #define B_AX_PCIE_TXBD_LEN0 BIT(1) 467 #define B_AX_PCIE_TXBD_4KBOUD_LENERR BIT(0) 468 469 #define R_AX_TXBD_RWPTR_CLR2_V1 0x11C4 470 #define B_AX_CLR_CH11_IDX BIT(1) 471 #define B_AX_CLR_CH10_IDX BIT(0) 472 473 #define R_AX_LBC_WATCHDOG 0x11D8 474 #define B_AX_LBC_TIMER GENMASK(7, 4) 475 #define B_AX_LBC_FLAG BIT(1) 476 #define B_AX_LBC_EN BIT(0) 477 478 #define R_AX_RXBD_RWPTR_CLR_V1 0x1200 479 #define B_AX_CLR_RPQ_IDX BIT(1) 480 #define B_AX_CLR_RXQ_IDX BIT(0) 481 482 #define R_AX_HAXI_EXP_CTRL 0x1204 483 #define B_AX_MAX_TAG_NUM_V1_MASK GENMASK(2, 0) 484 485 #define R_AX_PCIE_EXP_CTRL 0x13F0 486 #define B_AX_EN_CHKDSC_NO_RX_STUCK BIT(20) 487 #define B_AX_MAX_TAG_NUM GENMASK(18, 16) 488 #define B_AX_SIC_EN_FORCE_CLKREQ BIT(4) 489 490 #define R_AX_PCIE_RX_PREF_ADV 0x13F4 491 #define B_AX_RXDMA_PREF_ADV_EN BIT(0) 492 493 #define R_AX_PCIE_HRPWM_V1 0x30C0 494 #define R_AX_PCIE_CRPWM 0x30C4 495 496 #define RTW89_PCI_TXBD_NUM_MAX 256 497 #define RTW89_PCI_RXBD_NUM_MAX 256 498 #define RTW89_PCI_TXWD_NUM_MAX 512 499 #define RTW89_PCI_TXWD_PAGE_SIZE 128 500 #define RTW89_PCI_ADDRINFO_MAX 4 501 #define RTW89_PCI_RX_BUF_SIZE 11460 502 503 #define RTW89_PCI_POLL_BDRAM_RST_CNT 100 504 #define RTW89_PCI_MULTITAG 8 505 506 /* PCIE CFG register */ 507 #define RTW89_PCIE_ASPM_CTRL 0x070F 508 #define RTW89_L1DLY_MASK GENMASK(5, 3) 509 #define RTW89_L0DLY_MASK GENMASK(2, 0) 510 #define RTW89_PCIE_TIMER_CTRL 0x0718 511 #define RTW89_PCIE_BIT_L1SUB BIT(5) 512 #define RTW89_PCIE_L1_CTRL 0x0719 513 #define RTW89_PCIE_BIT_CLK BIT(4) 514 #define RTW89_PCIE_BIT_L1 BIT(3) 515 #define RTW89_PCIE_CLK_CTRL 0x0725 516 #define RTW89_PCIE_RST_MSTATE 0x0B48 517 #define RTW89_PCIE_BIT_CFG_RST_MSTATE BIT(0) 518 #define RTW89_PCIE_PHY_RATE 0x82 519 #define RTW89_PCIE_PHY_RATE_MASK GENMASK(1, 0) 520 #define INTF_INTGRA_MINREF_V1 90 521 #define INTF_INTGRA_HOSTREF_V1 100 522 523 enum rtw89_pcie_phy { 524 PCIE_PHY_GEN1, 525 PCIE_PHY_GEN2, 526 PCIE_PHY_GEN1_UNDEFINE = 0x7F, 527 }; 528 529 enum mac_ax_func_sw { 530 MAC_AX_FUNC_DIS, 531 MAC_AX_FUNC_EN, 532 }; 533 534 enum rtw89_pcie_l0sdly { 535 PCIE_L0SDLY_1US = 0, 536 PCIE_L0SDLY_2US = 1, 537 PCIE_L0SDLY_3US = 2, 538 PCIE_L0SDLY_4US = 3, 539 PCIE_L0SDLY_5US = 4, 540 PCIE_L0SDLY_6US = 5, 541 PCIE_L0SDLY_7US = 6, 542 }; 543 544 enum rtw89_pcie_l1dly { 545 PCIE_L1DLY_16US = 4, 546 PCIE_L1DLY_32US = 5, 547 PCIE_L1DLY_64US = 6, 548 PCIE_L1DLY_HW_INFI = 7, 549 }; 550 551 enum rtw89_pcie_clkdly_hw { 552 PCIE_CLKDLY_HW_0 = 0, 553 PCIE_CLKDLY_HW_30US = 0x1, 554 PCIE_CLKDLY_HW_50US = 0x2, 555 PCIE_CLKDLY_HW_100US = 0x3, 556 PCIE_CLKDLY_HW_150US = 0x4, 557 PCIE_CLKDLY_HW_200US = 0x5, 558 }; 559 560 enum mac_ax_bd_trunc_mode { 561 MAC_AX_BD_NORM, 562 MAC_AX_BD_TRUNC, 563 MAC_AX_BD_DEF = 0xFE 564 }; 565 566 enum mac_ax_rxbd_mode { 567 MAC_AX_RXBD_PKT, 568 MAC_AX_RXBD_SEP, 569 MAC_AX_RXBD_DEF = 0xFE 570 }; 571 572 enum mac_ax_tag_mode { 573 MAC_AX_TAG_SGL, 574 MAC_AX_TAG_MULTI, 575 MAC_AX_TAG_DEF = 0xFE 576 }; 577 578 enum mac_ax_tx_burst { 579 MAC_AX_TX_BURST_16B = 0, 580 MAC_AX_TX_BURST_32B = 1, 581 MAC_AX_TX_BURST_64B = 2, 582 MAC_AX_TX_BURST_V1_64B = 0, 583 MAC_AX_TX_BURST_128B = 3, 584 MAC_AX_TX_BURST_V1_128B = 1, 585 MAC_AX_TX_BURST_256B = 4, 586 MAC_AX_TX_BURST_V1_256B = 2, 587 MAC_AX_TX_BURST_512B = 5, 588 MAC_AX_TX_BURST_1024B = 6, 589 MAC_AX_TX_BURST_2048B = 7, 590 MAC_AX_TX_BURST_DEF = 0xFE 591 }; 592 593 enum mac_ax_rx_burst { 594 MAC_AX_RX_BURST_16B = 0, 595 MAC_AX_RX_BURST_32B = 1, 596 MAC_AX_RX_BURST_64B = 2, 597 MAC_AX_RX_BURST_V1_64B = 0, 598 MAC_AX_RX_BURST_128B = 3, 599 MAC_AX_RX_BURST_V1_128B = 1, 600 MAC_AX_RX_BURST_V1_256B = 0, 601 MAC_AX_RX_BURST_DEF = 0xFE 602 }; 603 604 enum mac_ax_wd_dma_intvl { 605 MAC_AX_WD_DMA_INTVL_0S, 606 MAC_AX_WD_DMA_INTVL_256NS, 607 MAC_AX_WD_DMA_INTVL_512NS, 608 MAC_AX_WD_DMA_INTVL_768NS, 609 MAC_AX_WD_DMA_INTVL_1US, 610 MAC_AX_WD_DMA_INTVL_1_5US, 611 MAC_AX_WD_DMA_INTVL_2US, 612 MAC_AX_WD_DMA_INTVL_4US, 613 MAC_AX_WD_DMA_INTVL_8US, 614 MAC_AX_WD_DMA_INTVL_16US, 615 MAC_AX_WD_DMA_INTVL_DEF = 0xFE 616 }; 617 618 enum mac_ax_multi_tag_num { 619 MAC_AX_TAG_NUM_1, 620 MAC_AX_TAG_NUM_2, 621 MAC_AX_TAG_NUM_3, 622 MAC_AX_TAG_NUM_4, 623 MAC_AX_TAG_NUM_5, 624 MAC_AX_TAG_NUM_6, 625 MAC_AX_TAG_NUM_7, 626 MAC_AX_TAG_NUM_8, 627 MAC_AX_TAG_NUM_DEF = 0xFE 628 }; 629 630 enum mac_ax_lbc_tmr { 631 MAC_AX_LBC_TMR_8US = 0, 632 MAC_AX_LBC_TMR_16US, 633 MAC_AX_LBC_TMR_32US, 634 MAC_AX_LBC_TMR_64US, 635 MAC_AX_LBC_TMR_128US, 636 MAC_AX_LBC_TMR_256US, 637 MAC_AX_LBC_TMR_512US, 638 MAC_AX_LBC_TMR_1MS, 639 MAC_AX_LBC_TMR_2MS, 640 MAC_AX_LBC_TMR_4MS, 641 MAC_AX_LBC_TMR_8MS, 642 MAC_AX_LBC_TMR_DEF = 0xFE 643 }; 644 645 enum mac_ax_pcie_func_ctrl { 646 MAC_AX_PCIE_DISABLE = 0, 647 MAC_AX_PCIE_ENABLE = 1, 648 MAC_AX_PCIE_DEFAULT = 0xFE, 649 MAC_AX_PCIE_IGNORE = 0xFF 650 }; 651 652 enum mac_ax_io_rcy_tmr { 653 MAC_AX_IO_RCY_ANA_TMR_2MS = 24000, 654 MAC_AX_IO_RCY_ANA_TMR_4MS = 48000, 655 MAC_AX_IO_RCY_ANA_TMR_6MS = 72000, 656 MAC_AX_IO_RCY_ANA_TMR_DEF = 0xFE 657 }; 658 659 enum rtw89_pci_intr_mask_cfg { 660 RTW89_PCI_INTR_MASK_RESET, 661 RTW89_PCI_INTR_MASK_NORMAL, 662 RTW89_PCI_INTR_MASK_LOW_POWER, 663 RTW89_PCI_INTR_MASK_RECOVERY_START, 664 RTW89_PCI_INTR_MASK_RECOVERY_COMPLETE, 665 }; 666 667 struct rtw89_pci_isrs; 668 struct rtw89_pci; 669 670 struct rtw89_pci_bd_idx_addr { 671 u32 tx_bd_addrs[RTW89_TXCH_NUM]; 672 u32 rx_bd_addrs[RTW89_RXCH_NUM]; 673 }; 674 675 struct rtw89_pci_ch_dma_addr { 676 u32 num; 677 u32 idx; 678 u32 bdram; 679 u32 desa_l; 680 u32 desa_h; 681 }; 682 683 struct rtw89_pci_ch_dma_addr_set { 684 struct rtw89_pci_ch_dma_addr tx[RTW89_TXCH_NUM]; 685 struct rtw89_pci_ch_dma_addr rx[RTW89_RXCH_NUM]; 686 }; 687 688 struct rtw89_pci_info { 689 enum mac_ax_bd_trunc_mode txbd_trunc_mode; 690 enum mac_ax_bd_trunc_mode rxbd_trunc_mode; 691 enum mac_ax_rxbd_mode rxbd_mode; 692 enum mac_ax_tag_mode tag_mode; 693 enum mac_ax_tx_burst tx_burst; 694 enum mac_ax_rx_burst rx_burst; 695 enum mac_ax_wd_dma_intvl wd_dma_idle_intvl; 696 enum mac_ax_wd_dma_intvl wd_dma_act_intvl; 697 enum mac_ax_multi_tag_num multi_tag_num; 698 enum mac_ax_pcie_func_ctrl lbc_en; 699 enum mac_ax_lbc_tmr lbc_tmr; 700 enum mac_ax_pcie_func_ctrl autok_en; 701 enum mac_ax_pcie_func_ctrl io_rcy_en; 702 enum mac_ax_io_rcy_tmr io_rcy_tmr; 703 704 u32 init_cfg_reg; 705 u32 txhci_en_bit; 706 u32 rxhci_en_bit; 707 u32 rxbd_mode_bit; 708 u32 exp_ctrl_reg; 709 u32 max_tag_num_mask; 710 u32 rxbd_rwptr_clr_reg; 711 u32 txbd_rwptr_clr2_reg; 712 u32 dma_stop1_reg; 713 u32 dma_stop2_reg; 714 u32 dma_busy1_reg; 715 u32 dma_busy2_reg; 716 u32 dma_busy3_reg; 717 718 u32 rpwm_addr; 719 u32 cpwm_addr; 720 const struct rtw89_pci_bd_idx_addr *bd_idx_addr_low_power; 721 const struct rtw89_pci_ch_dma_addr_set *dma_addr_set; 722 723 int (*ltr_set)(struct rtw89_dev *rtwdev, bool en); 724 u32 (*fill_txaddr_info)(struct rtw89_dev *rtwdev, 725 void *txaddr_info_addr, u32 total_len, 726 dma_addr_t dma, u8 *add_info_nr); 727 void (*config_intr_mask)(struct rtw89_dev *rtwdev); 728 void (*enable_intr)(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci); 729 void (*disable_intr)(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci); 730 void (*recognize_intrs)(struct rtw89_dev *rtwdev, 731 struct rtw89_pci *rtwpci, 732 struct rtw89_pci_isrs *isrs); 733 }; 734 735 struct rtw89_pci_bd_ram { 736 u8 start_idx; 737 u8 max_num; 738 u8 min_num; 739 }; 740 741 struct rtw89_pci_tx_data { 742 dma_addr_t dma; 743 }; 744 745 struct rtw89_pci_rx_info { 746 dma_addr_t dma; 747 u32 fs:1, ls:1, tag:11, len:14; 748 }; 749 750 #define RTW89_PCI_TXBD_OPTION_LS BIT(14) 751 752 struct rtw89_pci_tx_bd_32 { 753 __le16 length; 754 __le16 option; 755 __le32 dma; 756 } __packed; 757 758 #define RTW89_PCI_TXWP_VALID BIT(15) 759 760 struct rtw89_pci_tx_wp_info { 761 __le16 seq0; 762 __le16 seq1; 763 __le16 seq2; 764 __le16 seq3; 765 } __packed; 766 767 #define RTW89_PCI_ADDR_MSDU_LS BIT(15) 768 #define RTW89_PCI_ADDR_LS BIT(14) 769 #define RTW89_PCI_ADDR_HIGH(a) (((a) << 6) & GENMASK(13, 6)) 770 #define RTW89_PCI_ADDR_NUM(x) ((x) & GENMASK(5, 0)) 771 772 struct rtw89_pci_tx_addr_info_32 { 773 __le16 length; 774 __le16 option; 775 __le32 dma; 776 } __packed; 777 778 #define RTW89_TXADDR_INFO_NR_V1 10 779 780 struct rtw89_pci_tx_addr_info_32_v1 { 781 __le16 length_opt; 782 #define B_PCIADDR_LEN_V1_MASK GENMASK(10, 0) 783 #define B_PCIADDR_HIGH_SEL_V1_MASK GENMASK(14, 11) 784 #define B_PCIADDR_LS_V1_MASK BIT(15) 785 #define TXADDR_INFO_LENTHG_V1_MAX ALIGN_DOWN(BIT(11) - 1, 4) 786 __le16 dma_low_lsb; 787 __le16 dma_low_msb; 788 } __packed; 789 790 #define RTW89_PCI_RPP_POLLUTED BIT(31) 791 #define RTW89_PCI_RPP_SEQ GENMASK(30, 16) 792 #define RTW89_PCI_RPP_TX_STATUS GENMASK(15, 13) 793 #define RTW89_TX_DONE 0x0 794 #define RTW89_TX_RETRY_LIMIT 0x1 795 #define RTW89_TX_LIFE_TIME 0x2 796 #define RTW89_TX_MACID_DROP 0x3 797 #define RTW89_PCI_RPP_QSEL GENMASK(12, 8) 798 #define RTW89_PCI_RPP_MACID GENMASK(7, 0) 799 800 struct rtw89_pci_rpp_fmt { 801 __le32 dword; 802 } __packed; 803 804 struct rtw89_pci_rx_bd_32 { 805 __le16 buf_size; 806 __le16 rsvd; 807 __le32 dma; 808 } __packed; 809 810 #define RTW89_PCI_RXBD_FS BIT(15) 811 #define RTW89_PCI_RXBD_LS BIT(14) 812 #define RTW89_PCI_RXBD_WRITE_SIZE GENMASK(13, 0) 813 #define RTW89_PCI_RXBD_TAG GENMASK(28, 16) 814 815 struct rtw89_pci_rxbd_info { 816 __le32 dword; 817 }; 818 819 struct rtw89_pci_tx_wd { 820 struct list_head list; 821 struct sk_buff_head queue; 822 823 void *vaddr; 824 dma_addr_t paddr; 825 u32 len; 826 u32 seq; 827 }; 828 829 struct rtw89_pci_dma_ring { 830 void *head; 831 u8 desc_size; 832 dma_addr_t dma; 833 834 struct rtw89_pci_ch_dma_addr addr; 835 836 u32 len; 837 u32 wp; /* host idx */ 838 u32 rp; /* hw idx */ 839 }; 840 841 struct rtw89_pci_tx_wd_ring { 842 void *head; 843 dma_addr_t dma; 844 845 struct rtw89_pci_tx_wd pages[RTW89_PCI_TXWD_NUM_MAX]; 846 struct list_head free_pages; 847 848 u32 page_size; 849 u32 page_num; 850 u32 curr_num; 851 }; 852 853 #define RTW89_RX_TAG_MAX 0x1fff 854 855 struct rtw89_pci_tx_ring { 856 struct rtw89_pci_tx_wd_ring wd_ring; 857 struct rtw89_pci_dma_ring bd_ring; 858 struct list_head busy_pages; 859 u8 txch; 860 bool dma_enabled; 861 u16 tag; /* range from 0x0001 ~ 0x1fff */ 862 863 u64 tx_cnt; 864 u64 tx_acked; 865 u64 tx_retry_lmt; 866 u64 tx_life_time; 867 u64 tx_mac_id_drop; 868 }; 869 870 struct rtw89_pci_rx_ring { 871 struct rtw89_pci_dma_ring bd_ring; 872 struct sk_buff *buf[RTW89_PCI_RXBD_NUM_MAX]; 873 u32 buf_sz; 874 struct sk_buff *diliver_skb; 875 struct rtw89_rx_desc_info diliver_desc; 876 }; 877 878 struct rtw89_pci_isrs { 879 u32 ind_isrs; 880 u32 halt_c2h_isrs; 881 u32 isrs[2]; 882 }; 883 884 struct rtw89_pci { 885 struct pci_dev *pdev; 886 887 /* protect HW irq related registers */ 888 spinlock_t irq_lock; 889 /* protect TRX resources (exclude RXQ) */ 890 spinlock_t trx_lock; 891 bool running; 892 bool low_power; 893 bool under_recovery; 894 struct rtw89_pci_tx_ring tx_rings[RTW89_TXCH_NUM]; 895 struct rtw89_pci_rx_ring rx_rings[RTW89_RXCH_NUM]; 896 struct sk_buff_head h2c_queue; 897 struct sk_buff_head h2c_release_queue; 898 DECLARE_BITMAP(kick_map, RTW89_TXCH_NUM); 899 900 u32 ind_intrs; 901 u32 halt_c2h_intrs; 902 u32 intrs[2]; 903 void __iomem *mmap; 904 }; 905 906 static inline struct rtw89_pci_rx_info *RTW89_PCI_RX_SKB_CB(struct sk_buff *skb) 907 { 908 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 909 910 BUILD_BUG_ON(sizeof(struct rtw89_pci_tx_data) > 911 sizeof(info->status.status_driver_data)); 912 913 return (struct rtw89_pci_rx_info *)skb->cb; 914 } 915 916 static inline struct rtw89_pci_rx_bd_32 * 917 RTW89_PCI_RX_BD(struct rtw89_pci_rx_ring *rx_ring, u32 idx) 918 { 919 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 920 u8 *head = bd_ring->head; 921 u32 desc_size = bd_ring->desc_size; 922 u32 offset = idx * desc_size; 923 924 return (struct rtw89_pci_rx_bd_32 *)(head + offset); 925 } 926 927 static inline void 928 rtw89_pci_rxbd_increase(struct rtw89_pci_rx_ring *rx_ring, u32 cnt) 929 { 930 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 931 932 bd_ring->wp += cnt; 933 934 if (bd_ring->wp >= bd_ring->len) 935 bd_ring->wp -= bd_ring->len; 936 } 937 938 static inline struct rtw89_pci_tx_data *RTW89_PCI_TX_SKB_CB(struct sk_buff *skb) 939 { 940 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 941 942 return (struct rtw89_pci_tx_data *)info->status.status_driver_data; 943 } 944 945 static inline struct rtw89_pci_tx_bd_32 * 946 rtw89_pci_get_next_txbd(struct rtw89_pci_tx_ring *tx_ring) 947 { 948 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; 949 struct rtw89_pci_tx_bd_32 *tx_bd, *head; 950 951 head = bd_ring->head; 952 tx_bd = head + bd_ring->wp; 953 954 return tx_bd; 955 } 956 957 static inline struct rtw89_pci_tx_wd * 958 rtw89_pci_dequeue_txwd(struct rtw89_pci_tx_ring *tx_ring) 959 { 960 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 961 struct rtw89_pci_tx_wd *txwd; 962 963 txwd = list_first_entry_or_null(&wd_ring->free_pages, 964 struct rtw89_pci_tx_wd, list); 965 if (!txwd) 966 return NULL; 967 968 list_del_init(&txwd->list); 969 txwd->len = 0; 970 wd_ring->curr_num--; 971 972 return txwd; 973 } 974 975 static inline void 976 rtw89_pci_enqueue_txwd(struct rtw89_pci_tx_ring *tx_ring, 977 struct rtw89_pci_tx_wd *txwd) 978 { 979 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 980 981 memset(txwd->vaddr, 0, wd_ring->page_size); 982 list_add_tail(&txwd->list, &wd_ring->free_pages); 983 wd_ring->curr_num++; 984 } 985 986 static inline bool rtw89_pci_ltr_is_err_reg_val(u32 val) 987 { 988 return val == 0xffffffff || val == 0xeaeaeaea; 989 } 990 991 extern const struct dev_pm_ops rtw89_pm_ops; 992 extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set; 993 extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_v1; 994 995 struct pci_device_id; 996 997 int rtw89_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id); 998 void rtw89_pci_remove(struct pci_dev *pdev); 999 int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev, bool en); 1000 int rtw89_pci_ltr_set_v1(struct rtw89_dev *rtwdev, bool en); 1001 u32 rtw89_pci_fill_txaddr_info(struct rtw89_dev *rtwdev, 1002 void *txaddr_info_addr, u32 total_len, 1003 dma_addr_t dma, u8 *add_info_nr); 1004 u32 rtw89_pci_fill_txaddr_info_v1(struct rtw89_dev *rtwdev, 1005 void *txaddr_info_addr, u32 total_len, 1006 dma_addr_t dma, u8 *add_info_nr); 1007 void rtw89_pci_config_intr_mask(struct rtw89_dev *rtwdev); 1008 void rtw89_pci_config_intr_mask_v1(struct rtw89_dev *rtwdev); 1009 void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci); 1010 void rtw89_pci_disable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci); 1011 void rtw89_pci_enable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci); 1012 void rtw89_pci_disable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci); 1013 void rtw89_pci_recognize_intrs(struct rtw89_dev *rtwdev, 1014 struct rtw89_pci *rtwpci, 1015 struct rtw89_pci_isrs *isrs); 1016 void rtw89_pci_recognize_intrs_v1(struct rtw89_dev *rtwdev, 1017 struct rtw89_pci *rtwpci, 1018 struct rtw89_pci_isrs *isrs); 1019 1020 static inline 1021 u32 rtw89_chip_fill_txaddr_info(struct rtw89_dev *rtwdev, 1022 void *txaddr_info_addr, u32 total_len, 1023 dma_addr_t dma, u8 *add_info_nr) 1024 { 1025 const struct rtw89_pci_info *info = rtwdev->pci_info; 1026 1027 return info->fill_txaddr_info(rtwdev, txaddr_info_addr, total_len, 1028 dma, add_info_nr); 1029 } 1030 1031 static inline void rtw89_chip_config_intr_mask(struct rtw89_dev *rtwdev, 1032 enum rtw89_pci_intr_mask_cfg cfg) 1033 { 1034 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1035 const struct rtw89_pci_info *info = rtwdev->pci_info; 1036 1037 switch (cfg) { 1038 default: 1039 case RTW89_PCI_INTR_MASK_RESET: 1040 rtwpci->low_power = false; 1041 rtwpci->under_recovery = false; 1042 break; 1043 case RTW89_PCI_INTR_MASK_NORMAL: 1044 rtwpci->low_power = false; 1045 break; 1046 case RTW89_PCI_INTR_MASK_LOW_POWER: 1047 rtwpci->low_power = true; 1048 break; 1049 case RTW89_PCI_INTR_MASK_RECOVERY_START: 1050 rtwpci->under_recovery = true; 1051 break; 1052 case RTW89_PCI_INTR_MASK_RECOVERY_COMPLETE: 1053 rtwpci->under_recovery = false; 1054 break; 1055 } 1056 1057 rtw89_debug(rtwdev, RTW89_DBG_HCI, 1058 "Configure PCI interrupt mask mode low_power=%d under_recovery=%d\n", 1059 rtwpci->low_power, rtwpci->under_recovery); 1060 1061 info->config_intr_mask(rtwdev); 1062 } 1063 1064 static inline 1065 void rtw89_chip_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) 1066 { 1067 const struct rtw89_pci_info *info = rtwdev->pci_info; 1068 1069 info->enable_intr(rtwdev, rtwpci); 1070 } 1071 1072 static inline 1073 void rtw89_chip_disable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) 1074 { 1075 const struct rtw89_pci_info *info = rtwdev->pci_info; 1076 1077 info->disable_intr(rtwdev, rtwpci); 1078 } 1079 1080 static inline 1081 void rtw89_chip_recognize_intrs(struct rtw89_dev *rtwdev, 1082 struct rtw89_pci *rtwpci, 1083 struct rtw89_pci_isrs *isrs) 1084 { 1085 const struct rtw89_pci_info *info = rtwdev->pci_info; 1086 1087 info->recognize_intrs(rtwdev, rtwpci, isrs); 1088 } 1089 1090 #endif 1091