1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2020  Realtek Corporation
3  */
4 
5 #ifndef __RTW89_PCI_H__
6 #define __RTW89_PCI_H__
7 
8 #include "txrx.h"
9 
10 #define MDIO_PG0_G1 0
11 #define MDIO_PG1_G1 1
12 #define MDIO_PG0_G2 2
13 #define MDIO_PG1_G2 3
14 #define RAC_CTRL_PPR			0x00
15 #define RAC_ANA0A			0x0A
16 #define B_BAC_EQ_SEL			BIT(5)
17 #define RAC_ANA0C			0x0C
18 #define B_PCIE_BIT_PSAVE		BIT(15)
19 #define RAC_ANA10			0x10
20 #define B_PCIE_BIT_PINOUT_DIS		BIT(3)
21 #define RAC_REG_REV2			0x1B
22 #define BAC_CMU_EN_DLY_MASK		GENMASK(15, 12)
23 #define PCIE_DPHY_DLY_25US		0x1
24 #define RAC_ANA19			0x19
25 #define B_PCIE_BIT_RD_SEL		BIT(2)
26 #define RAC_REG_FLD_0			0x1D
27 #define BAC_AUTOK_N_MASK		GENMASK(3, 2)
28 #define PCIE_AUTOK_4			0x3
29 #define RAC_ANA1F			0x1F
30 #define RAC_ANA24			0x24
31 #define B_AX_DEGLITCH			GENMASK(11, 8)
32 #define RAC_ANA26			0x26
33 #define B_AX_RXEN			GENMASK(15, 14)
34 #define RAC_CTRL_PPR_V1			0x30
35 #define B_AX_CLK_CALIB_EN		BIT(12)
36 #define B_AX_CALIB_EN			BIT(13)
37 #define B_AX_DIV			GENMASK(15, 14)
38 #define RAC_SET_PPR_V1			0x31
39 
40 #define R_AX_DBI_FLAG			0x1090
41 #define B_AX_DBI_RFLAG			BIT(17)
42 #define B_AX_DBI_WFLAG			BIT(16)
43 #define B_AX_DBI_WREN_MSK		GENMASK(15, 12)
44 #define B_AX_DBI_ADDR_MSK		GENMASK(11, 2)
45 #define R_AX_DBI_WDATA			0x1094
46 #define R_AX_DBI_RDATA			0x1098
47 
48 #define R_AX_MDIO_WDATA			0x10A4
49 #define R_AX_MDIO_RDATA			0x10A6
50 
51 #define R_AX_PCIE_PS_CTRL_V1		0x3008
52 #define B_AX_CMAC_EXIT_L1_EN		BIT(7)
53 #define B_AX_DMAC0_EXIT_L1_EN		BIT(6)
54 #define B_AX_SEL_XFER_PENDING		BIT(3)
55 #define B_AX_SEL_REQ_ENTR_L1		BIT(2)
56 #define B_AX_SEL_REQ_EXIT_L1		BIT(0)
57 
58 #define R_AX_PCIE_MIX_CFG_V1		0x300C
59 #define B_AX_ASPM_CTRL_L1		BIT(17)
60 #define B_AX_ASPM_CTRL_L0		BIT(16)
61 #define B_AX_ASPM_CTRL_MASK		GENMASK(17, 16)
62 #define B_AX_XFER_PENDING_FW		BIT(11)
63 #define B_AX_XFER_PENDING		BIT(10)
64 #define B_AX_REQ_EXIT_L1		BIT(9)
65 #define B_AX_REQ_ENTR_L1		BIT(8)
66 #define B_AX_L1SUB_DISABLE		BIT(0)
67 
68 #define R_AX_L1_CLK_CTRL		0x3010
69 #define B_AX_CLK_REQ_N			BIT(1)
70 
71 #define R_AX_PCIE_BG_CLR		0x303C
72 #define B_AX_BG_CLR_ASYNC_M3		BIT(4)
73 
74 #define R_AX_PCIE_LAT_CTRL		0x3044
75 #define B_AX_CLK_REQ_SEL_OPT		BIT(1)
76 #define B_AX_CLK_REQ_SEL		BIT(0)
77 
78 #define R_AX_PCIE_IO_RCY_M1 0x3100
79 #define B_AX_PCIE_IO_RCY_P_M1 BIT(5)
80 #define B_AX_PCIE_IO_RCY_WDT_P_M1 BIT(4)
81 #define B_AX_PCIE_IO_RCY_WDT_MODE_M1 BIT(3)
82 #define B_AX_PCIE_IO_RCY_TRIG_M1 BIT(0)
83 
84 #define R_AX_PCIE_WDT_TIMER_M1 0x3104
85 #define B_AX_PCIE_WDT_TIMER_M1_MASK GENMASK(31, 0)
86 
87 #define R_AX_PCIE_IO_RCY_M2 0x310C
88 #define B_AX_PCIE_IO_RCY_P_M2 BIT(5)
89 #define B_AX_PCIE_IO_RCY_WDT_P_M2 BIT(4)
90 #define B_AX_PCIE_IO_RCY_WDT_MODE_M2 BIT(3)
91 #define B_AX_PCIE_IO_RCY_TRIG_M2 BIT(0)
92 
93 #define R_AX_PCIE_WDT_TIMER_M2 0x3110
94 #define B_AX_PCIE_WDT_TIMER_M2_MASK GENMASK(31, 0)
95 
96 #define R_AX_PCIE_IO_RCY_E0 0x3118
97 #define B_AX_PCIE_IO_RCY_P_E0 BIT(5)
98 #define B_AX_PCIE_IO_RCY_WDT_P_E0 BIT(4)
99 #define B_AX_PCIE_IO_RCY_WDT_MODE_E0 BIT(3)
100 #define B_AX_PCIE_IO_RCY_TRIG_E0 BIT(0)
101 
102 #define R_AX_PCIE_WDT_TIMER_E0 0x311C
103 #define B_AX_PCIE_WDT_TIMER_E0_MASK GENMASK(31, 0)
104 
105 #define R_AX_PCIE_IO_RCY_S1 0x3124
106 #define B_AX_PCIE_IO_RCY_RP_S1 BIT(7)
107 #define B_AX_PCIE_IO_RCY_WP_S1 BIT(6)
108 #define B_AX_PCIE_IO_RCY_WDT_RP_S1 BIT(5)
109 #define B_AX_PCIE_IO_RCY_WDT_WP_S1 BIT(4)
110 #define B_AX_PCIE_IO_RCY_WDT_MODE_S1 BIT(3)
111 #define B_AX_PCIE_IO_RCY_RTRIG_S1 BIT(1)
112 #define B_AX_PCIE_IO_RCY_WTRIG_S1 BIT(0)
113 
114 #define R_AX_PCIE_WDT_TIMER_S1 0x3128
115 #define B_AX_PCIE_WDT_TIMER_S1_MASK GENMASK(31, 0)
116 
117 #define R_RAC_DIRECT_OFFSET_G1 0x3800
118 #define FILTER_OUT_EQ_MASK GENMASK(14, 10)
119 #define R_RAC_DIRECT_OFFSET_G2 0x3880
120 #define REG_FILTER_OUT_MASK GENMASK(6, 2)
121 #define RAC_MULT 2
122 
123 #define RTW89_PCI_WR_RETRY_CNT		20
124 
125 /* Interrupts */
126 #define R_AX_HIMR0 0x01A0
127 #define B_AX_WDT_TIMEOUT_INT_EN BIT(22)
128 #define B_AX_HALT_C2H_INT_EN BIT(21)
129 #define R_AX_HISR0 0x01A4
130 
131 #define R_AX_HIMR1 0x01A8
132 #define B_AX_GPIO18_INT_EN BIT(2)
133 #define B_AX_GPIO17_INT_EN BIT(1)
134 #define B_AX_GPIO16_INT_EN BIT(0)
135 
136 #define R_AX_HISR1 0x01AC
137 #define B_AX_GPIO18_INT BIT(2)
138 #define B_AX_GPIO17_INT BIT(1)
139 #define B_AX_GPIO16_INT BIT(0)
140 
141 #define R_AX_MDIO_CFG			0x10A0
142 #define B_AX_MDIO_PHY_ADDR_MASK		GENMASK(13, 12)
143 #define B_AX_MDIO_RFLAG			BIT(9)
144 #define B_AX_MDIO_WFLAG			BIT(8)
145 #define B_AX_MDIO_ADDR_MASK		GENMASK(4, 0)
146 
147 #define R_AX_PCIE_HIMR00	0x10B0
148 #define R_AX_HAXI_HIMR00 0x10B0
149 #define B_AX_HC00ISR_IND_INT_EN		BIT(27)
150 #define B_AX_HD1ISR_IND_INT_EN		BIT(26)
151 #define B_AX_HD0ISR_IND_INT_EN		BIT(25)
152 #define B_AX_HS0ISR_IND_INT_EN		BIT(24)
153 #define B_AX_RETRAIN_INT_EN		BIT(21)
154 #define B_AX_RPQBD_FULL_INT_EN		BIT(20)
155 #define B_AX_RDU_INT_EN			BIT(19)
156 #define B_AX_RXDMA_STUCK_INT_EN		BIT(18)
157 #define B_AX_TXDMA_STUCK_INT_EN		BIT(17)
158 #define B_AX_PCIE_HOTRST_INT_EN		BIT(16)
159 #define B_AX_PCIE_FLR_INT_EN		BIT(15)
160 #define B_AX_PCIE_PERST_INT_EN		BIT(14)
161 #define B_AX_TXDMA_CH12_INT_EN		BIT(13)
162 #define B_AX_TXDMA_CH9_INT_EN		BIT(12)
163 #define B_AX_TXDMA_CH8_INT_EN		BIT(11)
164 #define B_AX_TXDMA_ACH7_INT_EN		BIT(10)
165 #define B_AX_TXDMA_ACH6_INT_EN		BIT(9)
166 #define B_AX_TXDMA_ACH5_INT_EN		BIT(8)
167 #define B_AX_TXDMA_ACH4_INT_EN		BIT(7)
168 #define B_AX_TXDMA_ACH3_INT_EN		BIT(6)
169 #define B_AX_TXDMA_ACH2_INT_EN		BIT(5)
170 #define B_AX_TXDMA_ACH1_INT_EN		BIT(4)
171 #define B_AX_TXDMA_ACH0_INT_EN		BIT(3)
172 #define B_AX_RPQDMA_INT_EN		BIT(2)
173 #define B_AX_RXP1DMA_INT_EN		BIT(1)
174 #define B_AX_RXDMA_INT_EN		BIT(0)
175 
176 #define R_AX_PCIE_HISR00	0x10B4
177 #define R_AX_HAXI_HISR00 0x10B4
178 #define B_AX_HC00ISR_IND_INT		BIT(27)
179 #define B_AX_HD1ISR_IND_INT		BIT(26)
180 #define B_AX_HD0ISR_IND_INT		BIT(25)
181 #define B_AX_HS0ISR_IND_INT		BIT(24)
182 #define B_AX_RETRAIN_INT		BIT(21)
183 #define B_AX_RPQBD_FULL_INT		BIT(20)
184 #define B_AX_RDU_INT			BIT(19)
185 #define B_AX_RXDMA_STUCK_INT		BIT(18)
186 #define B_AX_TXDMA_STUCK_INT		BIT(17)
187 #define B_AX_PCIE_HOTRST_INT		BIT(16)
188 #define B_AX_PCIE_FLR_INT		BIT(15)
189 #define B_AX_PCIE_PERST_INT		BIT(14)
190 #define B_AX_TXDMA_CH12_INT		BIT(13)
191 #define B_AX_TXDMA_CH9_INT		BIT(12)
192 #define B_AX_TXDMA_CH8_INT		BIT(11)
193 #define B_AX_TXDMA_ACH7_INT		BIT(10)
194 #define B_AX_TXDMA_ACH6_INT		BIT(9)
195 #define B_AX_TXDMA_ACH5_INT		BIT(8)
196 #define B_AX_TXDMA_ACH4_INT		BIT(7)
197 #define B_AX_TXDMA_ACH3_INT		BIT(6)
198 #define B_AX_TXDMA_ACH2_INT		BIT(5)
199 #define B_AX_TXDMA_ACH1_INT		BIT(4)
200 #define B_AX_TXDMA_ACH0_INT		BIT(3)
201 #define B_AX_RPQDMA_INT			BIT(2)
202 #define B_AX_RXP1DMA_INT		BIT(1)
203 #define B_AX_RXDMA_INT			BIT(0)
204 
205 #define R_AX_HAXI_HIMR10 0x11E0
206 #define B_AX_TXDMA_CH11_INT_EN_V1 BIT(1)
207 #define B_AX_TXDMA_CH10_INT_EN_V1 BIT(0)
208 
209 #define R_AX_PCIE_HIMR10	0x13B0
210 #define B_AX_HC10ISR_IND_INT_EN		BIT(28)
211 #define B_AX_TXDMA_CH11_INT_EN		BIT(12)
212 #define B_AX_TXDMA_CH10_INT_EN		BIT(11)
213 
214 #define R_AX_PCIE_HISR10	0x13B4
215 #define B_AX_HC10ISR_IND_INT		BIT(28)
216 #define B_AX_TXDMA_CH11_INT		BIT(12)
217 #define B_AX_TXDMA_CH10_INT		BIT(11)
218 
219 #define R_AX_PCIE_HIMR00_V1 0x30B0
220 #define B_AX_HCI_AXIDMA_INT_EN BIT(29)
221 #define B_AX_HC00ISR_IND_INT_EN_V1 BIT(28)
222 #define B_AX_HD1ISR_IND_INT_EN_V1 BIT(27)
223 #define B_AX_HD0ISR_IND_INT_EN_V1 BIT(26)
224 #define B_AX_HS1ISR_IND_INT_EN BIT(25)
225 #define B_AX_PCIE_DBG_STE_INT_EN BIT(13)
226 
227 #define R_AX_PCIE_HISR00_V1 0x30B4
228 #define B_AX_HCI_AXIDMA_INT BIT(29)
229 #define B_AX_HC00ISR_IND_INT_V1 BIT(28)
230 #define B_AX_HD1ISR_IND_INT_V1 BIT(27)
231 #define B_AX_HD0ISR_IND_INT_V1 BIT(26)
232 #define B_AX_HS1ISR_IND_INT BIT(25)
233 #define B_AX_PCIE_DBG_STE_INT BIT(13)
234 
235 /* TX/RX */
236 #define R_AX_DRV_FW_HSK_0	0x01B0
237 #define R_AX_DRV_FW_HSK_1	0x01B4
238 #define R_AX_DRV_FW_HSK_2	0x01B8
239 #define R_AX_DRV_FW_HSK_3	0x01BC
240 #define R_AX_DRV_FW_HSK_4	0x01C0
241 #define R_AX_DRV_FW_HSK_5	0x01C4
242 #define R_AX_DRV_FW_HSK_6	0x01C8
243 #define R_AX_DRV_FW_HSK_7	0x01CC
244 
245 #define R_AX_RXQ_RXBD_IDX	0x1050
246 #define R_AX_RPQ_RXBD_IDX	0x1054
247 #define R_AX_ACH0_TXBD_IDX	0x1058
248 #define R_AX_ACH1_TXBD_IDX	0x105C
249 #define R_AX_ACH2_TXBD_IDX	0x1060
250 #define R_AX_ACH3_TXBD_IDX	0x1064
251 #define R_AX_ACH4_TXBD_IDX	0x1068
252 #define R_AX_ACH5_TXBD_IDX	0x106C
253 #define R_AX_ACH6_TXBD_IDX	0x1070
254 #define R_AX_ACH7_TXBD_IDX	0x1074
255 #define R_AX_CH8_TXBD_IDX	0x1078 /* Management Queue band 0 */
256 #define R_AX_CH9_TXBD_IDX	0x107C /* HI Queue band 0 */
257 #define R_AX_CH10_TXBD_IDX	0x137C /* Management Queue band 1 */
258 #define R_AX_CH11_TXBD_IDX	0x1380 /* HI Queue band 1 */
259 #define R_AX_CH12_TXBD_IDX	0x1080 /* FWCMD Queue */
260 #define R_AX_CH10_TXBD_IDX_V1	0x11D0
261 #define R_AX_CH11_TXBD_IDX_V1	0x11D4
262 #define R_AX_RXQ_RXBD_IDX_V1	0x1218
263 #define R_AX_RPQ_RXBD_IDX_V1	0x121C
264 #define TXBD_HW_IDX_MASK	GENMASK(27, 16)
265 #define TXBD_HOST_IDX_MASK	GENMASK(11, 0)
266 
267 #define R_AX_ACH0_TXBD_DESA_L	0x1110
268 #define R_AX_ACH0_TXBD_DESA_H	0x1114
269 #define R_AX_ACH1_TXBD_DESA_L	0x1118
270 #define R_AX_ACH1_TXBD_DESA_H	0x111C
271 #define R_AX_ACH2_TXBD_DESA_L	0x1120
272 #define R_AX_ACH2_TXBD_DESA_H	0x1124
273 #define R_AX_ACH3_TXBD_DESA_L	0x1128
274 #define R_AX_ACH3_TXBD_DESA_H	0x112C
275 #define R_AX_ACH4_TXBD_DESA_L	0x1130
276 #define R_AX_ACH4_TXBD_DESA_H	0x1134
277 #define R_AX_ACH5_TXBD_DESA_L	0x1138
278 #define R_AX_ACH5_TXBD_DESA_H	0x113C
279 #define R_AX_ACH6_TXBD_DESA_L	0x1140
280 #define R_AX_ACH6_TXBD_DESA_H	0x1144
281 #define R_AX_ACH7_TXBD_DESA_L	0x1148
282 #define R_AX_ACH7_TXBD_DESA_H	0x114C
283 #define R_AX_CH8_TXBD_DESA_L	0x1150
284 #define R_AX_CH8_TXBD_DESA_H	0x1154
285 #define R_AX_CH9_TXBD_DESA_L	0x1158
286 #define R_AX_CH9_TXBD_DESA_H	0x115C
287 #define R_AX_CH10_TXBD_DESA_L	0x1358
288 #define R_AX_CH10_TXBD_DESA_H	0x135C
289 #define R_AX_CH11_TXBD_DESA_L	0x1360
290 #define R_AX_CH11_TXBD_DESA_H	0x1364
291 #define R_AX_CH12_TXBD_DESA_L	0x1160
292 #define R_AX_CH12_TXBD_DESA_H	0x1164
293 #define R_AX_RXQ_RXBD_DESA_L	0x1100
294 #define R_AX_RXQ_RXBD_DESA_H	0x1104
295 #define R_AX_RPQ_RXBD_DESA_L	0x1108
296 #define R_AX_RPQ_RXBD_DESA_H	0x110C
297 #define R_AX_RXQ_RXBD_DESA_L_V1 0x1220
298 #define R_AX_RXQ_RXBD_DESA_H_V1 0x1224
299 #define R_AX_RPQ_RXBD_DESA_L_V1 0x1228
300 #define R_AX_RPQ_RXBD_DESA_H_V1 0x122C
301 #define R_AX_ACH0_TXBD_DESA_L_V1 0x1230
302 #define R_AX_ACH0_TXBD_DESA_H_V1 0x1234
303 #define R_AX_ACH1_TXBD_DESA_L_V1 0x1238
304 #define R_AX_ACH1_TXBD_DESA_H_V1 0x123C
305 #define R_AX_ACH2_TXBD_DESA_L_V1 0x1240
306 #define R_AX_ACH2_TXBD_DESA_H_V1 0x1244
307 #define R_AX_ACH3_TXBD_DESA_L_V1 0x1248
308 #define R_AX_ACH3_TXBD_DESA_H_V1 0x124C
309 #define R_AX_ACH4_TXBD_DESA_L_V1 0x1250
310 #define R_AX_ACH4_TXBD_DESA_H_V1 0x1254
311 #define R_AX_ACH5_TXBD_DESA_L_V1 0x1258
312 #define R_AX_ACH5_TXBD_DESA_H_V1 0x125C
313 #define R_AX_ACH6_TXBD_DESA_L_V1 0x1260
314 #define R_AX_ACH6_TXBD_DESA_H_V1 0x1264
315 #define R_AX_ACH7_TXBD_DESA_L_V1 0x1268
316 #define R_AX_ACH7_TXBD_DESA_H_V1 0x126C
317 #define R_AX_CH8_TXBD_DESA_L_V1 0x1270
318 #define R_AX_CH8_TXBD_DESA_H_V1 0x1274
319 #define R_AX_CH9_TXBD_DESA_L_V1 0x1278
320 #define R_AX_CH9_TXBD_DESA_H_V1 0x127C
321 #define R_AX_CH12_TXBD_DESA_L_V1 0x1280
322 #define R_AX_CH12_TXBD_DESA_H_V1 0x1284
323 #define R_AX_CH10_TXBD_DESA_L_V1 0x1458
324 #define R_AX_CH10_TXBD_DESA_H_V1 0x145C
325 #define R_AX_CH11_TXBD_DESA_L_V1 0x1460
326 #define R_AX_CH11_TXBD_DESA_H_V1 0x1464
327 #define B_AX_DESC_NUM_MSK		GENMASK(11, 0)
328 
329 #define R_AX_RXQ_RXBD_NUM	0x1020
330 #define R_AX_RPQ_RXBD_NUM	0x1022
331 #define R_AX_ACH0_TXBD_NUM	0x1024
332 #define R_AX_ACH1_TXBD_NUM	0x1026
333 #define R_AX_ACH2_TXBD_NUM	0x1028
334 #define R_AX_ACH3_TXBD_NUM	0x102A
335 #define R_AX_ACH4_TXBD_NUM	0x102C
336 #define R_AX_ACH5_TXBD_NUM	0x102E
337 #define R_AX_ACH6_TXBD_NUM	0x1030
338 #define R_AX_ACH7_TXBD_NUM	0x1032
339 #define R_AX_CH8_TXBD_NUM	0x1034
340 #define R_AX_CH9_TXBD_NUM	0x1036
341 #define R_AX_CH10_TXBD_NUM	0x1338
342 #define R_AX_CH11_TXBD_NUM	0x133A
343 #define R_AX_CH12_TXBD_NUM	0x1038
344 #define R_AX_RXQ_RXBD_NUM_V1	0x1210
345 #define R_AX_RPQ_RXBD_NUM_V1	0x1212
346 #define R_AX_CH10_TXBD_NUM_V1	0x1438
347 #define R_AX_CH11_TXBD_NUM_V1	0x143A
348 
349 #define R_AX_ACH0_BDRAM_CTRL	0x1200
350 #define R_AX_ACH1_BDRAM_CTRL	0x1204
351 #define R_AX_ACH2_BDRAM_CTRL	0x1208
352 #define R_AX_ACH3_BDRAM_CTRL	0x120C
353 #define R_AX_ACH4_BDRAM_CTRL	0x1210
354 #define R_AX_ACH5_BDRAM_CTRL	0x1214
355 #define R_AX_ACH6_BDRAM_CTRL	0x1218
356 #define R_AX_ACH7_BDRAM_CTRL	0x121C
357 #define R_AX_CH8_BDRAM_CTRL	0x1220
358 #define R_AX_CH9_BDRAM_CTRL	0x1224
359 #define R_AX_CH10_BDRAM_CTRL	0x1320
360 #define R_AX_CH11_BDRAM_CTRL	0x1324
361 #define R_AX_CH12_BDRAM_CTRL	0x1228
362 #define R_AX_ACH0_BDRAM_CTRL_V1 0x1300
363 #define R_AX_ACH1_BDRAM_CTRL_V1 0x1304
364 #define R_AX_ACH2_BDRAM_CTRL_V1 0x1308
365 #define R_AX_ACH3_BDRAM_CTRL_V1 0x130C
366 #define R_AX_ACH4_BDRAM_CTRL_V1 0x1310
367 #define R_AX_ACH5_BDRAM_CTRL_V1 0x1314
368 #define R_AX_ACH6_BDRAM_CTRL_V1 0x1318
369 #define R_AX_ACH7_BDRAM_CTRL_V1 0x131C
370 #define R_AX_CH8_BDRAM_CTRL_V1 0x1320
371 #define R_AX_CH9_BDRAM_CTRL_V1 0x1324
372 #define R_AX_CH12_BDRAM_CTRL_V1 0x1328
373 #define R_AX_CH10_BDRAM_CTRL_V1 0x1420
374 #define R_AX_CH11_BDRAM_CTRL_V1 0x1424
375 #define BDRAM_SIDX_MASK		GENMASK(7, 0)
376 #define BDRAM_MAX_MASK		GENMASK(15, 8)
377 #define BDRAM_MIN_MASK		GENMASK(23, 16)
378 
379 #define R_AX_PCIE_INIT_CFG1	0x1000
380 #define B_AX_PCIE_RXRST_KEEP_REG	BIT(23)
381 #define B_AX_PCIE_TXRST_KEEP_REG	BIT(22)
382 #define B_AX_PCIE_PERST_KEEP_REG	BIT(21)
383 #define B_AX_PCIE_FLR_KEEP_REG		BIT(20)
384 #define B_AX_PCIE_TRAIN_KEEP_REG	BIT(19)
385 #define B_AX_RXBD_MODE			BIT(18)
386 #define B_AX_PCIE_MAX_RXDMA_MASK	GENMASK(16, 14)
387 #define B_AX_RXHCI_EN			BIT(13)
388 #define B_AX_LATENCY_CONTROL		BIT(12)
389 #define B_AX_TXHCI_EN			BIT(11)
390 #define B_AX_PCIE_MAX_TXDMA_MASK	GENMASK(10, 8)
391 #define B_AX_TX_TRUNC_MODE		BIT(5)
392 #define B_AX_RX_TRUNC_MODE		BIT(4)
393 #define B_AX_RST_BDRAM			BIT(3)
394 #define B_AX_DIS_RXDMA_PRE		BIT(2)
395 
396 #define R_AX_TXDMA_ADDR_H	0x10F0
397 #define R_AX_RXDMA_ADDR_H	0x10F4
398 
399 #define R_AX_PCIE_DMA_STOP1	0x1010
400 #define B_AX_STOP_PCIEIO		BIT(20)
401 #define B_AX_STOP_WPDMA			BIT(19)
402 #define B_AX_STOP_CH12			BIT(18)
403 #define B_AX_STOP_CH9			BIT(17)
404 #define B_AX_STOP_CH8			BIT(16)
405 #define B_AX_STOP_ACH7			BIT(15)
406 #define B_AX_STOP_ACH6			BIT(14)
407 #define B_AX_STOP_ACH5			BIT(13)
408 #define B_AX_STOP_ACH4			BIT(12)
409 #define B_AX_STOP_ACH3			BIT(11)
410 #define B_AX_STOP_ACH2			BIT(10)
411 #define B_AX_STOP_ACH1			BIT(9)
412 #define B_AX_STOP_ACH0			BIT(8)
413 #define B_AX_STOP_RPQ			BIT(1)
414 #define B_AX_STOP_RXQ			BIT(0)
415 #define B_AX_TX_STOP1_ALL		GENMASK(18, 8)
416 #define B_AX_TX_STOP1_MASK		(B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | \
417 					 B_AX_STOP_ACH2 | B_AX_STOP_ACH3 | \
418 					 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | \
419 					 B_AX_STOP_ACH6 | B_AX_STOP_ACH7 | \
420 					 B_AX_STOP_CH8 | B_AX_STOP_CH9 | \
421 					 B_AX_STOP_CH12)
422 #define B_AX_TX_STOP1_MASK_V1		(B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | \
423 					 B_AX_STOP_ACH2 | B_AX_STOP_ACH3 | \
424 					 B_AX_STOP_CH8 | B_AX_STOP_CH9 | \
425 					 B_AX_STOP_CH12)
426 
427 #define R_AX_PCIE_DMA_STOP2	0x1310
428 #define B_AX_STOP_CH11			BIT(1)
429 #define B_AX_STOP_CH10			BIT(0)
430 #define B_AX_TX_STOP2_ALL		GENMASK(1, 0)
431 
432 #define R_AX_TXBD_RWPTR_CLR1	0x1014
433 #define B_AX_CLR_CH12_IDX		BIT(10)
434 #define B_AX_CLR_CH9_IDX		BIT(9)
435 #define B_AX_CLR_CH8_IDX		BIT(8)
436 #define B_AX_CLR_ACH7_IDX		BIT(7)
437 #define B_AX_CLR_ACH6_IDX		BIT(6)
438 #define B_AX_CLR_ACH5_IDX		BIT(5)
439 #define B_AX_CLR_ACH4_IDX		BIT(4)
440 #define B_AX_CLR_ACH3_IDX		BIT(3)
441 #define B_AX_CLR_ACH2_IDX		BIT(2)
442 #define B_AX_CLR_ACH1_IDX		BIT(1)
443 #define B_AX_CLR_ACH0_IDX		BIT(0)
444 #define B_AX_TXBD_CLR1_ALL		GENMASK(10, 0)
445 
446 #define R_AX_RXBD_RWPTR_CLR	0x1018
447 #define B_AX_CLR_RPQ_IDX		BIT(1)
448 #define B_AX_CLR_RXQ_IDX		BIT(0)
449 #define B_AX_RXBD_CLR_ALL		GENMASK(1, 0)
450 
451 #define R_AX_TXBD_RWPTR_CLR2	0x1314
452 #define B_AX_CLR_CH11_IDX		BIT(1)
453 #define B_AX_CLR_CH10_IDX		BIT(0)
454 #define B_AX_TXBD_CLR2_ALL		GENMASK(1, 0)
455 
456 #define R_AX_PCIE_DMA_BUSY1	0x101C
457 #define B_AX_PCIEIO_RX_BUSY		BIT(22)
458 #define B_AX_PCIEIO_TX_BUSY		BIT(21)
459 #define B_AX_PCIEIO_BUSY		BIT(20)
460 #define B_AX_WPDMA_BUSY			BIT(19)
461 #define B_AX_CH12_BUSY			BIT(18)
462 #define B_AX_CH9_BUSY			BIT(17)
463 #define B_AX_CH8_BUSY			BIT(16)
464 #define B_AX_ACH7_BUSY			BIT(15)
465 #define B_AX_ACH6_BUSY			BIT(14)
466 #define B_AX_ACH5_BUSY			BIT(13)
467 #define B_AX_ACH4_BUSY			BIT(12)
468 #define B_AX_ACH3_BUSY			BIT(11)
469 #define B_AX_ACH2_BUSY			BIT(10)
470 #define B_AX_ACH1_BUSY			BIT(9)
471 #define B_AX_ACH0_BUSY			BIT(8)
472 #define B_AX_RPQ_BUSY			BIT(1)
473 #define B_AX_RXQ_BUSY			BIT(0)
474 #define DMA_BUSY1_CHECK		(B_AX_ACH0_BUSY | B_AX_ACH1_BUSY | B_AX_ACH2_BUSY | \
475 				 B_AX_ACH3_BUSY | B_AX_ACH4_BUSY | B_AX_ACH5_BUSY | \
476 				 B_AX_ACH6_BUSY | B_AX_ACH7_BUSY | B_AX_CH8_BUSY | \
477 				 B_AX_CH9_BUSY | B_AX_CH12_BUSY)
478 #define DMA_BUSY1_CHECK_V1	(B_AX_ACH0_BUSY | B_AX_ACH1_BUSY | B_AX_ACH2_BUSY | \
479 				 B_AX_ACH3_BUSY | B_AX_CH8_BUSY | B_AX_CH9_BUSY | \
480 				 B_AX_CH12_BUSY)
481 
482 #define R_AX_PCIE_DMA_BUSY2	0x131C
483 #define B_AX_CH11_BUSY			BIT(1)
484 #define B_AX_CH10_BUSY			BIT(0)
485 
486 /* Configure */
487 #define R_AX_PCIE_INIT_CFG2		0x1004
488 #define B_AX_WD_ITVL_IDLE		GENMASK(27, 24)
489 #define B_AX_WD_ITVL_ACT		GENMASK(19, 16)
490 #define B_AX_PCIE_RX_APPLEN_MASK	GENMASK(13, 0)
491 
492 #define R_AX_PCIE_PS_CTRL		0x1008
493 #define B_AX_L1OFF_PWR_OFF_EN		BIT(5)
494 
495 #define R_AX_INT_MIT_RX			0x10D4
496 #define B_AX_RXMIT_RXP2_SEL		BIT(19)
497 #define B_AX_RXMIT_RXP1_SEL		BIT(18)
498 #define B_AX_RXTIMER_UNIT_MASK		GENMASK(17, 16)
499 #define AX_RXTIMER_UNIT_64US		0
500 #define AX_RXTIMER_UNIT_128US		1
501 #define AX_RXTIMER_UNIT_256US		2
502 #define AX_RXTIMER_UNIT_512US		3
503 #define B_AX_RXCOUNTER_MATCH_MASK	GENMASK(15, 8)
504 #define B_AX_RXTIMER_MATCH_MASK		GENMASK(7, 0)
505 
506 #define R_AX_DBG_ERR_FLAG		0x11C4
507 #define B_AX_PCIE_RPQ_FULL		BIT(29)
508 #define B_AX_PCIE_RXQ_FULL		BIT(28)
509 #define B_AX_CPL_STATUS_MASK		GENMASK(27, 25)
510 #define B_AX_RX_STUCK			BIT(22)
511 #define B_AX_TX_STUCK			BIT(21)
512 #define B_AX_PCIEDBG_TXERR0		BIT(16)
513 #define B_AX_PCIE_RXP1_ERR0		BIT(4)
514 #define B_AX_PCIE_TXBD_LEN0		BIT(1)
515 #define B_AX_PCIE_TXBD_4KBOUD_LENERR	BIT(0)
516 
517 #define R_AX_TXBD_RWPTR_CLR2_V1		0x11C4
518 #define B_AX_CLR_CH11_IDX		BIT(1)
519 #define B_AX_CLR_CH10_IDX		BIT(0)
520 
521 #define R_AX_LBC_WATCHDOG		0x11D8
522 #define B_AX_LBC_TIMER			GENMASK(7, 4)
523 #define B_AX_LBC_FLAG			BIT(1)
524 #define B_AX_LBC_EN			BIT(0)
525 
526 #define R_AX_RXBD_RWPTR_CLR_V1		0x1200
527 #define B_AX_CLR_RPQ_IDX		BIT(1)
528 #define B_AX_CLR_RXQ_IDX		BIT(0)
529 
530 #define R_AX_HAXI_EXP_CTRL		0x1204
531 #define B_AX_MAX_TAG_NUM_V1_MASK	GENMASK(2, 0)
532 
533 #define R_AX_PCIE_EXP_CTRL		0x13F0
534 #define B_AX_EN_CHKDSC_NO_RX_STUCK	BIT(20)
535 #define B_AX_MAX_TAG_NUM		GENMASK(18, 16)
536 #define B_AX_SIC_EN_FORCE_CLKREQ	BIT(4)
537 
538 #define R_AX_PCIE_RX_PREF_ADV		0x13F4
539 #define B_AX_RXDMA_PREF_ADV_EN		BIT(0)
540 
541 #define R_AX_PCIE_HRPWM_V1		0x30C0
542 #define R_AX_PCIE_CRPWM			0x30C4
543 
544 #define RTW89_PCI_TXBD_NUM_MAX		256
545 #define RTW89_PCI_RXBD_NUM_MAX		256
546 #define RTW89_PCI_TXWD_NUM_MAX		512
547 #define RTW89_PCI_TXWD_PAGE_SIZE	128
548 #define RTW89_PCI_ADDRINFO_MAX		4
549 #define RTW89_PCI_RX_BUF_SIZE		11460
550 
551 #define RTW89_PCI_POLL_BDRAM_RST_CNT	100
552 #define RTW89_PCI_MULTITAG		8
553 
554 /* PCIE CFG register */
555 #define RTW89_PCIE_L1_STS_V1		0x80
556 #define RTW89_BCFG_LINK_SPEED_MASK	GENMASK(19, 16)
557 #define RTW89_PCIE_GEN1_SPEED		0x01
558 #define RTW89_PCIE_GEN2_SPEED		0x02
559 #define RTW89_PCIE_PHY_RATE		0x82
560 #define RTW89_PCIE_PHY_RATE_MASK	GENMASK(1, 0)
561 #define RTW89_PCIE_L1SS_STS_V1		0x0168
562 #define RTW89_PCIE_BIT_ASPM_L11		BIT(3)
563 #define RTW89_PCIE_BIT_ASPM_L12		BIT(2)
564 #define RTW89_PCIE_BIT_PCI_L11		BIT(1)
565 #define RTW89_PCIE_BIT_PCI_L12		BIT(0)
566 #define RTW89_PCIE_ASPM_CTRL		0x070F
567 #define RTW89_L1DLY_MASK		GENMASK(5, 3)
568 #define RTW89_L0DLY_MASK		GENMASK(2, 0)
569 #define RTW89_PCIE_TIMER_CTRL		0x0718
570 #define RTW89_PCIE_BIT_L1SUB		BIT(5)
571 #define RTW89_PCIE_L1_CTRL		0x0719
572 #define RTW89_PCIE_BIT_CLK		BIT(4)
573 #define RTW89_PCIE_BIT_L1		BIT(3)
574 #define RTW89_PCIE_CLK_CTRL		0x0725
575 #define RTW89_PCIE_RST_MSTATE		0x0B48
576 #define RTW89_PCIE_BIT_CFG_RST_MSTATE	BIT(0)
577 
578 #define INTF_INTGRA_MINREF_V1	90
579 #define INTF_INTGRA_HOSTREF_V1	100
580 
581 enum rtw89_pcie_phy {
582 	PCIE_PHY_GEN1,
583 	PCIE_PHY_GEN2,
584 	PCIE_PHY_GEN1_UNDEFINE = 0x7F,
585 };
586 
587 enum rtw89_pcie_l0sdly {
588 	PCIE_L0SDLY_1US = 0,
589 	PCIE_L0SDLY_2US = 1,
590 	PCIE_L0SDLY_3US = 2,
591 	PCIE_L0SDLY_4US = 3,
592 	PCIE_L0SDLY_5US = 4,
593 	PCIE_L0SDLY_6US = 5,
594 	PCIE_L0SDLY_7US = 6,
595 };
596 
597 enum rtw89_pcie_l1dly {
598 	PCIE_L1DLY_16US = 4,
599 	PCIE_L1DLY_32US = 5,
600 	PCIE_L1DLY_64US = 6,
601 	PCIE_L1DLY_HW_INFI = 7,
602 };
603 
604 enum rtw89_pcie_clkdly_hw {
605 	PCIE_CLKDLY_HW_0 = 0,
606 	PCIE_CLKDLY_HW_30US = 0x1,
607 	PCIE_CLKDLY_HW_50US = 0x2,
608 	PCIE_CLKDLY_HW_100US = 0x3,
609 	PCIE_CLKDLY_HW_150US = 0x4,
610 	PCIE_CLKDLY_HW_200US = 0x5,
611 };
612 
613 enum mac_ax_bd_trunc_mode {
614 	MAC_AX_BD_NORM,
615 	MAC_AX_BD_TRUNC,
616 	MAC_AX_BD_DEF = 0xFE
617 };
618 
619 enum mac_ax_rxbd_mode {
620 	MAC_AX_RXBD_PKT,
621 	MAC_AX_RXBD_SEP,
622 	MAC_AX_RXBD_DEF = 0xFE
623 };
624 
625 enum mac_ax_tag_mode {
626 	MAC_AX_TAG_SGL,
627 	MAC_AX_TAG_MULTI,
628 	MAC_AX_TAG_DEF = 0xFE
629 };
630 
631 enum mac_ax_tx_burst {
632 	MAC_AX_TX_BURST_16B = 0,
633 	MAC_AX_TX_BURST_32B = 1,
634 	MAC_AX_TX_BURST_64B = 2,
635 	MAC_AX_TX_BURST_V1_64B = 0,
636 	MAC_AX_TX_BURST_128B = 3,
637 	MAC_AX_TX_BURST_V1_128B = 1,
638 	MAC_AX_TX_BURST_256B = 4,
639 	MAC_AX_TX_BURST_V1_256B = 2,
640 	MAC_AX_TX_BURST_512B = 5,
641 	MAC_AX_TX_BURST_1024B = 6,
642 	MAC_AX_TX_BURST_2048B = 7,
643 	MAC_AX_TX_BURST_DEF = 0xFE
644 };
645 
646 enum mac_ax_rx_burst {
647 	MAC_AX_RX_BURST_16B = 0,
648 	MAC_AX_RX_BURST_32B = 1,
649 	MAC_AX_RX_BURST_64B = 2,
650 	MAC_AX_RX_BURST_V1_64B = 0,
651 	MAC_AX_RX_BURST_128B = 3,
652 	MAC_AX_RX_BURST_V1_128B = 1,
653 	MAC_AX_RX_BURST_V1_256B = 0,
654 	MAC_AX_RX_BURST_DEF = 0xFE
655 };
656 
657 enum mac_ax_wd_dma_intvl {
658 	MAC_AX_WD_DMA_INTVL_0S,
659 	MAC_AX_WD_DMA_INTVL_256NS,
660 	MAC_AX_WD_DMA_INTVL_512NS,
661 	MAC_AX_WD_DMA_INTVL_768NS,
662 	MAC_AX_WD_DMA_INTVL_1US,
663 	MAC_AX_WD_DMA_INTVL_1_5US,
664 	MAC_AX_WD_DMA_INTVL_2US,
665 	MAC_AX_WD_DMA_INTVL_4US,
666 	MAC_AX_WD_DMA_INTVL_8US,
667 	MAC_AX_WD_DMA_INTVL_16US,
668 	MAC_AX_WD_DMA_INTVL_DEF = 0xFE
669 };
670 
671 enum mac_ax_multi_tag_num {
672 	MAC_AX_TAG_NUM_1,
673 	MAC_AX_TAG_NUM_2,
674 	MAC_AX_TAG_NUM_3,
675 	MAC_AX_TAG_NUM_4,
676 	MAC_AX_TAG_NUM_5,
677 	MAC_AX_TAG_NUM_6,
678 	MAC_AX_TAG_NUM_7,
679 	MAC_AX_TAG_NUM_8,
680 	MAC_AX_TAG_NUM_DEF = 0xFE
681 };
682 
683 enum mac_ax_lbc_tmr {
684 	MAC_AX_LBC_TMR_8US = 0,
685 	MAC_AX_LBC_TMR_16US,
686 	MAC_AX_LBC_TMR_32US,
687 	MAC_AX_LBC_TMR_64US,
688 	MAC_AX_LBC_TMR_128US,
689 	MAC_AX_LBC_TMR_256US,
690 	MAC_AX_LBC_TMR_512US,
691 	MAC_AX_LBC_TMR_1MS,
692 	MAC_AX_LBC_TMR_2MS,
693 	MAC_AX_LBC_TMR_4MS,
694 	MAC_AX_LBC_TMR_8MS,
695 	MAC_AX_LBC_TMR_DEF = 0xFE
696 };
697 
698 enum mac_ax_pcie_func_ctrl {
699 	MAC_AX_PCIE_DISABLE = 0,
700 	MAC_AX_PCIE_ENABLE = 1,
701 	MAC_AX_PCIE_DEFAULT = 0xFE,
702 	MAC_AX_PCIE_IGNORE = 0xFF
703 };
704 
705 enum mac_ax_io_rcy_tmr {
706 	MAC_AX_IO_RCY_ANA_TMR_2MS = 24000,
707 	MAC_AX_IO_RCY_ANA_TMR_4MS = 48000,
708 	MAC_AX_IO_RCY_ANA_TMR_6MS = 72000,
709 	MAC_AX_IO_RCY_ANA_TMR_DEF = 0xFE
710 };
711 
712 enum rtw89_pci_intr_mask_cfg {
713 	RTW89_PCI_INTR_MASK_RESET,
714 	RTW89_PCI_INTR_MASK_NORMAL,
715 	RTW89_PCI_INTR_MASK_LOW_POWER,
716 	RTW89_PCI_INTR_MASK_RECOVERY_START,
717 	RTW89_PCI_INTR_MASK_RECOVERY_COMPLETE,
718 };
719 
720 struct rtw89_pci_isrs;
721 struct rtw89_pci;
722 
723 struct rtw89_pci_bd_idx_addr {
724 	u32 tx_bd_addrs[RTW89_TXCH_NUM];
725 	u32 rx_bd_addrs[RTW89_RXCH_NUM];
726 };
727 
728 struct rtw89_pci_ch_dma_addr {
729 	u32 num;
730 	u32 idx;
731 	u32 bdram;
732 	u32 desa_l;
733 	u32 desa_h;
734 };
735 
736 struct rtw89_pci_ch_dma_addr_set {
737 	struct rtw89_pci_ch_dma_addr tx[RTW89_TXCH_NUM];
738 	struct rtw89_pci_ch_dma_addr rx[RTW89_RXCH_NUM];
739 };
740 
741 struct rtw89_pci_info {
742 	enum mac_ax_bd_trunc_mode txbd_trunc_mode;
743 	enum mac_ax_bd_trunc_mode rxbd_trunc_mode;
744 	enum mac_ax_rxbd_mode rxbd_mode;
745 	enum mac_ax_tag_mode tag_mode;
746 	enum mac_ax_tx_burst tx_burst;
747 	enum mac_ax_rx_burst rx_burst;
748 	enum mac_ax_wd_dma_intvl wd_dma_idle_intvl;
749 	enum mac_ax_wd_dma_intvl wd_dma_act_intvl;
750 	enum mac_ax_multi_tag_num multi_tag_num;
751 	enum mac_ax_pcie_func_ctrl lbc_en;
752 	enum mac_ax_lbc_tmr lbc_tmr;
753 	enum mac_ax_pcie_func_ctrl autok_en;
754 	enum mac_ax_pcie_func_ctrl io_rcy_en;
755 	enum mac_ax_io_rcy_tmr io_rcy_tmr;
756 
757 	u32 init_cfg_reg;
758 	u32 txhci_en_bit;
759 	u32 rxhci_en_bit;
760 	u32 rxbd_mode_bit;
761 	u32 exp_ctrl_reg;
762 	u32 max_tag_num_mask;
763 	u32 rxbd_rwptr_clr_reg;
764 	u32 txbd_rwptr_clr2_reg;
765 	struct rtw89_reg_def dma_stop1;
766 	struct rtw89_reg_def dma_stop2;
767 	struct rtw89_reg_def dma_busy1;
768 	u32 dma_busy2_reg;
769 	u32 dma_busy3_reg;
770 
771 	u32 rpwm_addr;
772 	u32 cpwm_addr;
773 	u32 tx_dma_ch_mask;
774 	const struct rtw89_pci_bd_idx_addr *bd_idx_addr_low_power;
775 	const struct rtw89_pci_ch_dma_addr_set *dma_addr_set;
776 
777 	int (*ltr_set)(struct rtw89_dev *rtwdev, bool en);
778 	u32 (*fill_txaddr_info)(struct rtw89_dev *rtwdev,
779 				void *txaddr_info_addr, u32 total_len,
780 				dma_addr_t dma, u8 *add_info_nr);
781 	void (*config_intr_mask)(struct rtw89_dev *rtwdev);
782 	void (*enable_intr)(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
783 	void (*disable_intr)(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
784 	void (*recognize_intrs)(struct rtw89_dev *rtwdev,
785 				struct rtw89_pci *rtwpci,
786 				struct rtw89_pci_isrs *isrs);
787 };
788 
789 struct rtw89_pci_bd_ram {
790 	u8 start_idx;
791 	u8 max_num;
792 	u8 min_num;
793 };
794 
795 struct rtw89_pci_tx_data {
796 	dma_addr_t dma;
797 };
798 
799 struct rtw89_pci_rx_info {
800 	dma_addr_t dma;
801 	u32 fs:1, ls:1, tag:11, len:14;
802 };
803 
804 #define RTW89_PCI_TXBD_OPTION_LS	BIT(14)
805 
806 struct rtw89_pci_tx_bd_32 {
807 	__le16 length;
808 	__le16 option;
809 	__le32 dma;
810 } __packed;
811 
812 #define RTW89_PCI_TXWP_VALID		BIT(15)
813 
814 struct rtw89_pci_tx_wp_info {
815 	__le16 seq0;
816 	__le16 seq1;
817 	__le16 seq2;
818 	__le16 seq3;
819 } __packed;
820 
821 #define RTW89_PCI_ADDR_MSDU_LS		BIT(15)
822 #define RTW89_PCI_ADDR_LS		BIT(14)
823 #define RTW89_PCI_ADDR_HIGH(a)		(((a) << 6) & GENMASK(13, 6))
824 #define RTW89_PCI_ADDR_NUM(x)		((x) & GENMASK(5, 0))
825 
826 struct rtw89_pci_tx_addr_info_32 {
827 	__le16 length;
828 	__le16 option;
829 	__le32 dma;
830 } __packed;
831 
832 #define RTW89_TXADDR_INFO_NR_V1		10
833 
834 struct rtw89_pci_tx_addr_info_32_v1 {
835 	__le16 length_opt;
836 #define B_PCIADDR_LEN_V1_MASK		GENMASK(10, 0)
837 #define B_PCIADDR_HIGH_SEL_V1_MASK	GENMASK(14, 11)
838 #define B_PCIADDR_LS_V1_MASK		BIT(15)
839 #define TXADDR_INFO_LENTHG_V1_MAX	ALIGN_DOWN(BIT(11) - 1, 4)
840 	__le16 dma_low_lsb;
841 	__le16 dma_low_msb;
842 } __packed;
843 
844 #define RTW89_PCI_RPP_POLLUTED		BIT(31)
845 #define RTW89_PCI_RPP_SEQ		GENMASK(30, 16)
846 #define RTW89_PCI_RPP_TX_STATUS		GENMASK(15, 13)
847 #define RTW89_TX_DONE			0x0
848 #define RTW89_TX_RETRY_LIMIT		0x1
849 #define RTW89_TX_LIFE_TIME		0x2
850 #define RTW89_TX_MACID_DROP		0x3
851 #define RTW89_PCI_RPP_QSEL		GENMASK(12, 8)
852 #define RTW89_PCI_RPP_MACID		GENMASK(7, 0)
853 
854 struct rtw89_pci_rpp_fmt {
855 	__le32 dword;
856 } __packed;
857 
858 struct rtw89_pci_rx_bd_32 {
859 	__le16 buf_size;
860 	__le16 rsvd;
861 	__le32 dma;
862 } __packed;
863 
864 #define RTW89_PCI_RXBD_FS		BIT(15)
865 #define RTW89_PCI_RXBD_LS		BIT(14)
866 #define RTW89_PCI_RXBD_WRITE_SIZE	GENMASK(13, 0)
867 #define RTW89_PCI_RXBD_TAG		GENMASK(28, 16)
868 
869 struct rtw89_pci_rxbd_info {
870 	__le32 dword;
871 };
872 
873 struct rtw89_pci_tx_wd {
874 	struct list_head list;
875 	struct sk_buff_head queue;
876 
877 	void *vaddr;
878 	dma_addr_t paddr;
879 	u32 len;
880 	u32 seq;
881 };
882 
883 struct rtw89_pci_dma_ring {
884 	void *head;
885 	u8 desc_size;
886 	dma_addr_t dma;
887 
888 	struct rtw89_pci_ch_dma_addr addr;
889 
890 	u32 len;
891 	u32 wp; /* host idx */
892 	u32 rp; /* hw idx */
893 };
894 
895 struct rtw89_pci_tx_wd_ring {
896 	void *head;
897 	dma_addr_t dma;
898 
899 	struct rtw89_pci_tx_wd pages[RTW89_PCI_TXWD_NUM_MAX];
900 	struct list_head free_pages;
901 
902 	u32 page_size;
903 	u32 page_num;
904 	u32 curr_num;
905 };
906 
907 #define RTW89_RX_TAG_MAX		0x1fff
908 
909 struct rtw89_pci_tx_ring {
910 	struct rtw89_pci_tx_wd_ring wd_ring;
911 	struct rtw89_pci_dma_ring bd_ring;
912 	struct list_head busy_pages;
913 	u8 txch;
914 	bool dma_enabled;
915 	u16 tag; /* range from 0x0001 ~ 0x1fff */
916 
917 	u64 tx_cnt;
918 	u64 tx_acked;
919 	u64 tx_retry_lmt;
920 	u64 tx_life_time;
921 	u64 tx_mac_id_drop;
922 };
923 
924 struct rtw89_pci_rx_ring {
925 	struct rtw89_pci_dma_ring bd_ring;
926 	struct sk_buff *buf[RTW89_PCI_RXBD_NUM_MAX];
927 	u32 buf_sz;
928 	struct sk_buff *diliver_skb;
929 	struct rtw89_rx_desc_info diliver_desc;
930 };
931 
932 struct rtw89_pci_isrs {
933 	u32 ind_isrs;
934 	u32 halt_c2h_isrs;
935 	u32 isrs[2];
936 };
937 
938 struct rtw89_pci {
939 	struct pci_dev *pdev;
940 
941 	/* protect HW irq related registers */
942 	spinlock_t irq_lock;
943 	/* protect TRX resources (exclude RXQ) */
944 	spinlock_t trx_lock;
945 	bool running;
946 	bool low_power;
947 	bool under_recovery;
948 	struct rtw89_pci_tx_ring tx_rings[RTW89_TXCH_NUM];
949 	struct rtw89_pci_rx_ring rx_rings[RTW89_RXCH_NUM];
950 	struct sk_buff_head h2c_queue;
951 	struct sk_buff_head h2c_release_queue;
952 	DECLARE_BITMAP(kick_map, RTW89_TXCH_NUM);
953 
954 	u32 ind_intrs;
955 	u32 halt_c2h_intrs;
956 	u32 intrs[2];
957 	void __iomem *mmap;
958 };
959 
960 static inline struct rtw89_pci_rx_info *RTW89_PCI_RX_SKB_CB(struct sk_buff *skb)
961 {
962 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
963 
964 	BUILD_BUG_ON(sizeof(struct rtw89_pci_tx_data) >
965 		     sizeof(info->status.status_driver_data));
966 
967 	return (struct rtw89_pci_rx_info *)skb->cb;
968 }
969 
970 static inline struct rtw89_pci_rx_bd_32 *
971 RTW89_PCI_RX_BD(struct rtw89_pci_rx_ring *rx_ring, u32 idx)
972 {
973 	struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
974 	u8 *head = bd_ring->head;
975 	u32 desc_size = bd_ring->desc_size;
976 	u32 offset = idx * desc_size;
977 
978 	return (struct rtw89_pci_rx_bd_32 *)(head + offset);
979 }
980 
981 static inline void
982 rtw89_pci_rxbd_increase(struct rtw89_pci_rx_ring *rx_ring, u32 cnt)
983 {
984 	struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
985 
986 	bd_ring->wp += cnt;
987 
988 	if (bd_ring->wp >= bd_ring->len)
989 		bd_ring->wp -= bd_ring->len;
990 }
991 
992 static inline struct rtw89_pci_tx_data *RTW89_PCI_TX_SKB_CB(struct sk_buff *skb)
993 {
994 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
995 
996 	return (struct rtw89_pci_tx_data *)info->status.status_driver_data;
997 }
998 
999 static inline struct rtw89_pci_tx_bd_32 *
1000 rtw89_pci_get_next_txbd(struct rtw89_pci_tx_ring *tx_ring)
1001 {
1002 	struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring;
1003 	struct rtw89_pci_tx_bd_32 *tx_bd, *head;
1004 
1005 	head = bd_ring->head;
1006 	tx_bd = head + bd_ring->wp;
1007 
1008 	return tx_bd;
1009 }
1010 
1011 static inline struct rtw89_pci_tx_wd *
1012 rtw89_pci_dequeue_txwd(struct rtw89_pci_tx_ring *tx_ring)
1013 {
1014 	struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
1015 	struct rtw89_pci_tx_wd *txwd;
1016 
1017 	txwd = list_first_entry_or_null(&wd_ring->free_pages,
1018 					struct rtw89_pci_tx_wd, list);
1019 	if (!txwd)
1020 		return NULL;
1021 
1022 	list_del_init(&txwd->list);
1023 	txwd->len = 0;
1024 	wd_ring->curr_num--;
1025 
1026 	return txwd;
1027 }
1028 
1029 static inline void
1030 rtw89_pci_enqueue_txwd(struct rtw89_pci_tx_ring *tx_ring,
1031 		       struct rtw89_pci_tx_wd *txwd)
1032 {
1033 	struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
1034 
1035 	memset(txwd->vaddr, 0, wd_ring->page_size);
1036 	list_add_tail(&txwd->list, &wd_ring->free_pages);
1037 	wd_ring->curr_num++;
1038 }
1039 
1040 static inline bool rtw89_pci_ltr_is_err_reg_val(u32 val)
1041 {
1042 	return val == 0xffffffff || val == 0xeaeaeaea;
1043 }
1044 
1045 extern const struct dev_pm_ops rtw89_pm_ops;
1046 extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set;
1047 extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_v1;
1048 
1049 struct pci_device_id;
1050 
1051 int rtw89_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
1052 void rtw89_pci_remove(struct pci_dev *pdev);
1053 int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev, bool en);
1054 int rtw89_pci_ltr_set_v1(struct rtw89_dev *rtwdev, bool en);
1055 u32 rtw89_pci_fill_txaddr_info(struct rtw89_dev *rtwdev,
1056 			       void *txaddr_info_addr, u32 total_len,
1057 			       dma_addr_t dma, u8 *add_info_nr);
1058 u32 rtw89_pci_fill_txaddr_info_v1(struct rtw89_dev *rtwdev,
1059 				  void *txaddr_info_addr, u32 total_len,
1060 				  dma_addr_t dma, u8 *add_info_nr);
1061 void rtw89_pci_config_intr_mask(struct rtw89_dev *rtwdev);
1062 void rtw89_pci_config_intr_mask_v1(struct rtw89_dev *rtwdev);
1063 void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1064 void rtw89_pci_disable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1065 void rtw89_pci_enable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1066 void rtw89_pci_disable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1067 void rtw89_pci_recognize_intrs(struct rtw89_dev *rtwdev,
1068 			       struct rtw89_pci *rtwpci,
1069 			       struct rtw89_pci_isrs *isrs);
1070 void rtw89_pci_recognize_intrs_v1(struct rtw89_dev *rtwdev,
1071 				  struct rtw89_pci *rtwpci,
1072 				  struct rtw89_pci_isrs *isrs);
1073 
1074 static inline
1075 u32 rtw89_chip_fill_txaddr_info(struct rtw89_dev *rtwdev,
1076 				void *txaddr_info_addr, u32 total_len,
1077 				dma_addr_t dma, u8 *add_info_nr)
1078 {
1079 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1080 
1081 	return info->fill_txaddr_info(rtwdev, txaddr_info_addr, total_len,
1082 				      dma, add_info_nr);
1083 }
1084 
1085 static inline void rtw89_chip_config_intr_mask(struct rtw89_dev *rtwdev,
1086 					       enum rtw89_pci_intr_mask_cfg cfg)
1087 {
1088 	struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1089 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1090 
1091 	switch (cfg) {
1092 	default:
1093 	case RTW89_PCI_INTR_MASK_RESET:
1094 		rtwpci->low_power = false;
1095 		rtwpci->under_recovery = false;
1096 		break;
1097 	case RTW89_PCI_INTR_MASK_NORMAL:
1098 		rtwpci->low_power = false;
1099 		break;
1100 	case RTW89_PCI_INTR_MASK_LOW_POWER:
1101 		rtwpci->low_power = true;
1102 		break;
1103 	case RTW89_PCI_INTR_MASK_RECOVERY_START:
1104 		rtwpci->under_recovery = true;
1105 		break;
1106 	case RTW89_PCI_INTR_MASK_RECOVERY_COMPLETE:
1107 		rtwpci->under_recovery = false;
1108 		break;
1109 	}
1110 
1111 	rtw89_debug(rtwdev, RTW89_DBG_HCI,
1112 		    "Configure PCI interrupt mask mode low_power=%d under_recovery=%d\n",
1113 		    rtwpci->low_power, rtwpci->under_recovery);
1114 
1115 	info->config_intr_mask(rtwdev);
1116 }
1117 
1118 static inline
1119 void rtw89_chip_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
1120 {
1121 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1122 
1123 	info->enable_intr(rtwdev, rtwpci);
1124 }
1125 
1126 static inline
1127 void rtw89_chip_disable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
1128 {
1129 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1130 
1131 	info->disable_intr(rtwdev, rtwpci);
1132 }
1133 
1134 static inline
1135 void rtw89_chip_recognize_intrs(struct rtw89_dev *rtwdev,
1136 				struct rtw89_pci *rtwpci,
1137 				struct rtw89_pci_isrs *isrs)
1138 {
1139 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1140 
1141 	info->recognize_intrs(rtwdev, rtwpci, isrs);
1142 }
1143 
1144 #endif
1145