1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2020  Realtek Corporation
3  */
4 
5 #ifndef __RTW89_PCI_H__
6 #define __RTW89_PCI_H__
7 
8 #include "txrx.h"
9 
10 #define MDIO_PG0_G1 0
11 #define MDIO_PG1_G1 1
12 #define MDIO_PG0_G2 2
13 #define MDIO_PG1_G2 3
14 #define RAC_CTRL_PPR			0x00
15 #define RAC_ANA0A			0x0A
16 #define B_BAC_EQ_SEL			BIT(5)
17 #define RAC_ANA0C			0x0C
18 #define B_PCIE_BIT_PSAVE		BIT(15)
19 #define RAC_ANA10			0x10
20 #define B_PCIE_BIT_PINOUT_DIS		BIT(3)
21 #define RAC_REG_REV2			0x1B
22 #define BAC_CMU_EN_DLY_MASK		GENMASK(15, 12)
23 #define PCIE_DPHY_DLY_25US		0x1
24 #define RAC_ANA19			0x19
25 #define B_PCIE_BIT_RD_SEL		BIT(2)
26 #define RAC_REG_FLD_0			0x1D
27 #define BAC_AUTOK_N_MASK		GENMASK(3, 2)
28 #define PCIE_AUTOK_4			0x3
29 #define RAC_ANA1F			0x1F
30 #define RAC_ANA24			0x24
31 #define B_AX_DEGLITCH			GENMASK(11, 8)
32 #define RAC_ANA26			0x26
33 #define B_AX_RXEN			GENMASK(15, 14)
34 #define RAC_CTRL_PPR_V1			0x30
35 #define B_AX_CLK_CALIB_EN		BIT(12)
36 #define B_AX_CALIB_EN			BIT(13)
37 #define B_AX_DIV			GENMASK(15, 14)
38 #define RAC_SET_PPR_V1			0x31
39 
40 #define R_AX_DBI_FLAG			0x1090
41 #define B_AX_DBI_RFLAG			BIT(17)
42 #define B_AX_DBI_WFLAG			BIT(16)
43 #define B_AX_DBI_WREN_MSK		GENMASK(15, 12)
44 #define B_AX_DBI_ADDR_MSK		GENMASK(11, 2)
45 #define R_AX_DBI_WDATA			0x1094
46 #define R_AX_DBI_RDATA			0x1098
47 
48 #define R_AX_MDIO_WDATA			0x10A4
49 #define R_AX_MDIO_RDATA			0x10A6
50 
51 #define R_AX_PCIE_PS_CTRL_V1		0x3008
52 #define B_AX_CMAC_EXIT_L1_EN		BIT(7)
53 #define B_AX_DMAC0_EXIT_L1_EN		BIT(6)
54 #define B_AX_SEL_XFER_PENDING		BIT(3)
55 #define B_AX_SEL_REQ_ENTR_L1		BIT(2)
56 #define B_AX_SEL_REQ_EXIT_L1		BIT(0)
57 
58 #define R_AX_PCIE_MIX_CFG_V1		0x300C
59 #define B_AX_ASPM_CTRL_L1		BIT(17)
60 #define B_AX_ASPM_CTRL_L0		BIT(16)
61 #define B_AX_ASPM_CTRL_MASK		GENMASK(17, 16)
62 #define B_AX_XFER_PENDING_FW		BIT(11)
63 #define B_AX_XFER_PENDING		BIT(10)
64 #define B_AX_REQ_EXIT_L1		BIT(9)
65 #define B_AX_REQ_ENTR_L1		BIT(8)
66 #define B_AX_L1SUB_DISABLE		BIT(0)
67 
68 #define R_AX_L1_CLK_CTRL		0x3010
69 #define B_AX_CLK_REQ_N			BIT(1)
70 
71 #define R_AX_PCIE_BG_CLR		0x303C
72 #define B_AX_BG_CLR_ASYNC_M3		BIT(4)
73 
74 #define R_AX_PCIE_LAT_CTRL		0x3044
75 #define B_AX_CLK_REQ_SEL_OPT		BIT(1)
76 #define B_AX_CLK_REQ_SEL		BIT(0)
77 
78 #define R_AX_PCIE_IO_RCY_M1 0x3100
79 #define B_AX_PCIE_IO_RCY_P_M1 BIT(5)
80 #define B_AX_PCIE_IO_RCY_WDT_P_M1 BIT(4)
81 #define B_AX_PCIE_IO_RCY_WDT_MODE_M1 BIT(3)
82 #define B_AX_PCIE_IO_RCY_TRIG_M1 BIT(0)
83 
84 #define R_AX_PCIE_WDT_TIMER_M1 0x3104
85 #define B_AX_PCIE_WDT_TIMER_M1_MASK GENMASK(31, 0)
86 
87 #define R_AX_PCIE_IO_RCY_M2 0x310C
88 #define B_AX_PCIE_IO_RCY_P_M2 BIT(5)
89 #define B_AX_PCIE_IO_RCY_WDT_P_M2 BIT(4)
90 #define B_AX_PCIE_IO_RCY_WDT_MODE_M2 BIT(3)
91 #define B_AX_PCIE_IO_RCY_TRIG_M2 BIT(0)
92 
93 #define R_AX_PCIE_WDT_TIMER_M2 0x3110
94 #define B_AX_PCIE_WDT_TIMER_M2_MASK GENMASK(31, 0)
95 
96 #define R_AX_PCIE_IO_RCY_E0 0x3118
97 #define B_AX_PCIE_IO_RCY_P_E0 BIT(5)
98 #define B_AX_PCIE_IO_RCY_WDT_P_E0 BIT(4)
99 #define B_AX_PCIE_IO_RCY_WDT_MODE_E0 BIT(3)
100 #define B_AX_PCIE_IO_RCY_TRIG_E0 BIT(0)
101 
102 #define R_AX_PCIE_WDT_TIMER_E0 0x311C
103 #define B_AX_PCIE_WDT_TIMER_E0_MASK GENMASK(31, 0)
104 
105 #define R_AX_PCIE_IO_RCY_S1 0x3124
106 #define B_AX_PCIE_IO_RCY_RP_S1 BIT(7)
107 #define B_AX_PCIE_IO_RCY_WP_S1 BIT(6)
108 #define B_AX_PCIE_IO_RCY_WDT_RP_S1 BIT(5)
109 #define B_AX_PCIE_IO_RCY_WDT_WP_S1 BIT(4)
110 #define B_AX_PCIE_IO_RCY_WDT_MODE_S1 BIT(3)
111 #define B_AX_PCIE_IO_RCY_RTRIG_S1 BIT(1)
112 #define B_AX_PCIE_IO_RCY_WTRIG_S1 BIT(0)
113 
114 #define R_AX_PCIE_WDT_TIMER_S1 0x3128
115 #define B_AX_PCIE_WDT_TIMER_S1_MASK GENMASK(31, 0)
116 
117 #define R_RAC_DIRECT_OFFSET_G1 0x3800
118 #define FILTER_OUT_EQ_MASK GENMASK(14, 10)
119 #define R_RAC_DIRECT_OFFSET_G2 0x3880
120 #define REG_FILTER_OUT_MASK GENMASK(6, 2)
121 #define RAC_MULT 2
122 
123 #define RTW89_PCI_WR_RETRY_CNT		20
124 
125 /* Interrupts */
126 #define R_AX_HIMR0 0x01A0
127 #define B_AX_WDT_TIMEOUT_INT_EN BIT(22)
128 #define B_AX_HALT_C2H_INT_EN BIT(21)
129 #define R_AX_HISR0 0x01A4
130 
131 #define R_AX_HIMR1 0x01A8
132 #define B_AX_GPIO18_INT_EN BIT(2)
133 #define B_AX_GPIO17_INT_EN BIT(1)
134 #define B_AX_GPIO16_INT_EN BIT(0)
135 
136 #define R_AX_HISR1 0x01AC
137 #define B_AX_GPIO18_INT BIT(2)
138 #define B_AX_GPIO17_INT BIT(1)
139 #define B_AX_GPIO16_INT BIT(0)
140 
141 #define R_AX_MDIO_CFG			0x10A0
142 #define B_AX_MDIO_PHY_ADDR_MASK		GENMASK(13, 12)
143 #define B_AX_MDIO_RFLAG			BIT(9)
144 #define B_AX_MDIO_WFLAG			BIT(8)
145 #define B_AX_MDIO_ADDR_MASK		GENMASK(4, 0)
146 
147 #define R_AX_PCIE_HIMR00	0x10B0
148 #define R_AX_HAXI_HIMR00 0x10B0
149 #define B_AX_HC00ISR_IND_INT_EN		BIT(27)
150 #define B_AX_HD1ISR_IND_INT_EN		BIT(26)
151 #define B_AX_HD0ISR_IND_INT_EN		BIT(25)
152 #define B_AX_HS0ISR_IND_INT_EN		BIT(24)
153 #define B_AX_RETRAIN_INT_EN		BIT(21)
154 #define B_AX_RPQBD_FULL_INT_EN		BIT(20)
155 #define B_AX_RDU_INT_EN			BIT(19)
156 #define B_AX_RXDMA_STUCK_INT_EN		BIT(18)
157 #define B_AX_TXDMA_STUCK_INT_EN		BIT(17)
158 #define B_AX_PCIE_HOTRST_INT_EN		BIT(16)
159 #define B_AX_PCIE_FLR_INT_EN		BIT(15)
160 #define B_AX_PCIE_PERST_INT_EN		BIT(14)
161 #define B_AX_TXDMA_CH12_INT_EN		BIT(13)
162 #define B_AX_TXDMA_CH9_INT_EN		BIT(12)
163 #define B_AX_TXDMA_CH8_INT_EN		BIT(11)
164 #define B_AX_TXDMA_ACH7_INT_EN		BIT(10)
165 #define B_AX_TXDMA_ACH6_INT_EN		BIT(9)
166 #define B_AX_TXDMA_ACH5_INT_EN		BIT(8)
167 #define B_AX_TXDMA_ACH4_INT_EN		BIT(7)
168 #define B_AX_TXDMA_ACH3_INT_EN		BIT(6)
169 #define B_AX_TXDMA_ACH2_INT_EN		BIT(5)
170 #define B_AX_TXDMA_ACH1_INT_EN		BIT(4)
171 #define B_AX_TXDMA_ACH0_INT_EN		BIT(3)
172 #define B_AX_RPQDMA_INT_EN		BIT(2)
173 #define B_AX_RXP1DMA_INT_EN		BIT(1)
174 #define B_AX_RXDMA_INT_EN		BIT(0)
175 
176 #define R_AX_PCIE_HISR00	0x10B4
177 #define R_AX_HAXI_HISR00 0x10B4
178 #define B_AX_HC00ISR_IND_INT		BIT(27)
179 #define B_AX_HD1ISR_IND_INT		BIT(26)
180 #define B_AX_HD0ISR_IND_INT		BIT(25)
181 #define B_AX_HS0ISR_IND_INT		BIT(24)
182 #define B_AX_RETRAIN_INT		BIT(21)
183 #define B_AX_RPQBD_FULL_INT		BIT(20)
184 #define B_AX_RDU_INT			BIT(19)
185 #define B_AX_RXDMA_STUCK_INT		BIT(18)
186 #define B_AX_TXDMA_STUCK_INT		BIT(17)
187 #define B_AX_PCIE_HOTRST_INT		BIT(16)
188 #define B_AX_PCIE_FLR_INT		BIT(15)
189 #define B_AX_PCIE_PERST_INT		BIT(14)
190 #define B_AX_TXDMA_CH12_INT		BIT(13)
191 #define B_AX_TXDMA_CH9_INT		BIT(12)
192 #define B_AX_TXDMA_CH8_INT		BIT(11)
193 #define B_AX_TXDMA_ACH7_INT		BIT(10)
194 #define B_AX_TXDMA_ACH6_INT		BIT(9)
195 #define B_AX_TXDMA_ACH5_INT		BIT(8)
196 #define B_AX_TXDMA_ACH4_INT		BIT(7)
197 #define B_AX_TXDMA_ACH3_INT		BIT(6)
198 #define B_AX_TXDMA_ACH2_INT		BIT(5)
199 #define B_AX_TXDMA_ACH1_INT		BIT(4)
200 #define B_AX_TXDMA_ACH0_INT		BIT(3)
201 #define B_AX_RPQDMA_INT			BIT(2)
202 #define B_AX_RXP1DMA_INT		BIT(1)
203 #define B_AX_RXDMA_INT			BIT(0)
204 
205 #define R_AX_HAXI_IDCT_MSK 0x10B8
206 #define B_AX_TXBD_LEN0_ERR_IDCT_MSK BIT(3)
207 #define B_AX_TXBD_4KBOUND_ERR_IDCT_MSK BIT(2)
208 #define B_AX_RXMDA_STUCK_IDCT_MSK BIT(1)
209 #define B_AX_TXMDA_STUCK_IDCT_MSK BIT(0)
210 
211 #define R_AX_HAXI_IDCT 0x10BC
212 #define B_AX_TXBD_LEN0_ERR_IDCT BIT(3)
213 #define B_AX_TXBD_4KBOUND_ERR_IDCT BIT(2)
214 #define B_AX_RXMDA_STUCK_IDCT BIT(1)
215 #define B_AX_TXMDA_STUCK_IDCT BIT(0)
216 
217 #define R_AX_HAXI_HIMR10 0x11E0
218 #define B_AX_TXDMA_CH11_INT_EN_V1 BIT(1)
219 #define B_AX_TXDMA_CH10_INT_EN_V1 BIT(0)
220 
221 #define R_AX_PCIE_HIMR10	0x13B0
222 #define B_AX_HC10ISR_IND_INT_EN		BIT(28)
223 #define B_AX_TXDMA_CH11_INT_EN		BIT(12)
224 #define B_AX_TXDMA_CH10_INT_EN		BIT(11)
225 
226 #define R_AX_PCIE_HISR10	0x13B4
227 #define B_AX_HC10ISR_IND_INT		BIT(28)
228 #define B_AX_TXDMA_CH11_INT		BIT(12)
229 #define B_AX_TXDMA_CH10_INT		BIT(11)
230 
231 #define R_AX_PCIE_HIMR00_V1 0x30B0
232 #define B_AX_HCI_AXIDMA_INT_EN BIT(29)
233 #define B_AX_HC00ISR_IND_INT_EN_V1 BIT(28)
234 #define B_AX_HD1ISR_IND_INT_EN_V1 BIT(27)
235 #define B_AX_HD0ISR_IND_INT_EN_V1 BIT(26)
236 #define B_AX_HS1ISR_IND_INT_EN BIT(25)
237 #define B_AX_PCIE_DBG_STE_INT_EN BIT(13)
238 
239 #define R_AX_PCIE_HISR00_V1 0x30B4
240 #define B_AX_HCI_AXIDMA_INT BIT(29)
241 #define B_AX_HC00ISR_IND_INT_V1 BIT(28)
242 #define B_AX_HD1ISR_IND_INT_V1 BIT(27)
243 #define B_AX_HD0ISR_IND_INT_V1 BIT(26)
244 #define B_AX_HS1ISR_IND_INT BIT(25)
245 #define B_AX_PCIE_DBG_STE_INT BIT(13)
246 
247 /* TX/RX */
248 #define R_AX_DRV_FW_HSK_0	0x01B0
249 #define R_AX_DRV_FW_HSK_1	0x01B4
250 #define R_AX_DRV_FW_HSK_2	0x01B8
251 #define R_AX_DRV_FW_HSK_3	0x01BC
252 #define R_AX_DRV_FW_HSK_4	0x01C0
253 #define R_AX_DRV_FW_HSK_5	0x01C4
254 #define R_AX_DRV_FW_HSK_6	0x01C8
255 #define R_AX_DRV_FW_HSK_7	0x01CC
256 
257 #define R_AX_RXQ_RXBD_IDX	0x1050
258 #define R_AX_RPQ_RXBD_IDX	0x1054
259 #define R_AX_ACH0_TXBD_IDX	0x1058
260 #define R_AX_ACH1_TXBD_IDX	0x105C
261 #define R_AX_ACH2_TXBD_IDX	0x1060
262 #define R_AX_ACH3_TXBD_IDX	0x1064
263 #define R_AX_ACH4_TXBD_IDX	0x1068
264 #define R_AX_ACH5_TXBD_IDX	0x106C
265 #define R_AX_ACH6_TXBD_IDX	0x1070
266 #define R_AX_ACH7_TXBD_IDX	0x1074
267 #define R_AX_CH8_TXBD_IDX	0x1078 /* Management Queue band 0 */
268 #define R_AX_CH9_TXBD_IDX	0x107C /* HI Queue band 0 */
269 #define R_AX_CH10_TXBD_IDX	0x137C /* Management Queue band 1 */
270 #define R_AX_CH11_TXBD_IDX	0x1380 /* HI Queue band 1 */
271 #define R_AX_CH12_TXBD_IDX	0x1080 /* FWCMD Queue */
272 #define R_AX_CH10_TXBD_IDX_V1	0x11D0
273 #define R_AX_CH11_TXBD_IDX_V1	0x11D4
274 #define R_AX_RXQ_RXBD_IDX_V1	0x1218
275 #define R_AX_RPQ_RXBD_IDX_V1	0x121C
276 #define TXBD_HW_IDX_MASK	GENMASK(27, 16)
277 #define TXBD_HOST_IDX_MASK	GENMASK(11, 0)
278 
279 #define R_AX_ACH0_TXBD_DESA_L	0x1110
280 #define R_AX_ACH0_TXBD_DESA_H	0x1114
281 #define R_AX_ACH1_TXBD_DESA_L	0x1118
282 #define R_AX_ACH1_TXBD_DESA_H	0x111C
283 #define R_AX_ACH2_TXBD_DESA_L	0x1120
284 #define R_AX_ACH2_TXBD_DESA_H	0x1124
285 #define R_AX_ACH3_TXBD_DESA_L	0x1128
286 #define R_AX_ACH3_TXBD_DESA_H	0x112C
287 #define R_AX_ACH4_TXBD_DESA_L	0x1130
288 #define R_AX_ACH4_TXBD_DESA_H	0x1134
289 #define R_AX_ACH5_TXBD_DESA_L	0x1138
290 #define R_AX_ACH5_TXBD_DESA_H	0x113C
291 #define R_AX_ACH6_TXBD_DESA_L	0x1140
292 #define R_AX_ACH6_TXBD_DESA_H	0x1144
293 #define R_AX_ACH7_TXBD_DESA_L	0x1148
294 #define R_AX_ACH7_TXBD_DESA_H	0x114C
295 #define R_AX_CH8_TXBD_DESA_L	0x1150
296 #define R_AX_CH8_TXBD_DESA_H	0x1154
297 #define R_AX_CH9_TXBD_DESA_L	0x1158
298 #define R_AX_CH9_TXBD_DESA_H	0x115C
299 #define R_AX_CH10_TXBD_DESA_L	0x1358
300 #define R_AX_CH10_TXBD_DESA_H	0x135C
301 #define R_AX_CH11_TXBD_DESA_L	0x1360
302 #define R_AX_CH11_TXBD_DESA_H	0x1364
303 #define R_AX_CH12_TXBD_DESA_L	0x1160
304 #define R_AX_CH12_TXBD_DESA_H	0x1164
305 #define R_AX_RXQ_RXBD_DESA_L	0x1100
306 #define R_AX_RXQ_RXBD_DESA_H	0x1104
307 #define R_AX_RPQ_RXBD_DESA_L	0x1108
308 #define R_AX_RPQ_RXBD_DESA_H	0x110C
309 #define R_AX_RXQ_RXBD_DESA_L_V1 0x1220
310 #define R_AX_RXQ_RXBD_DESA_H_V1 0x1224
311 #define R_AX_RPQ_RXBD_DESA_L_V1 0x1228
312 #define R_AX_RPQ_RXBD_DESA_H_V1 0x122C
313 #define R_AX_ACH0_TXBD_DESA_L_V1 0x1230
314 #define R_AX_ACH0_TXBD_DESA_H_V1 0x1234
315 #define R_AX_ACH1_TXBD_DESA_L_V1 0x1238
316 #define R_AX_ACH1_TXBD_DESA_H_V1 0x123C
317 #define R_AX_ACH2_TXBD_DESA_L_V1 0x1240
318 #define R_AX_ACH2_TXBD_DESA_H_V1 0x1244
319 #define R_AX_ACH3_TXBD_DESA_L_V1 0x1248
320 #define R_AX_ACH3_TXBD_DESA_H_V1 0x124C
321 #define R_AX_ACH4_TXBD_DESA_L_V1 0x1250
322 #define R_AX_ACH4_TXBD_DESA_H_V1 0x1254
323 #define R_AX_ACH5_TXBD_DESA_L_V1 0x1258
324 #define R_AX_ACH5_TXBD_DESA_H_V1 0x125C
325 #define R_AX_ACH6_TXBD_DESA_L_V1 0x1260
326 #define R_AX_ACH6_TXBD_DESA_H_V1 0x1264
327 #define R_AX_ACH7_TXBD_DESA_L_V1 0x1268
328 #define R_AX_ACH7_TXBD_DESA_H_V1 0x126C
329 #define R_AX_CH8_TXBD_DESA_L_V1 0x1270
330 #define R_AX_CH8_TXBD_DESA_H_V1 0x1274
331 #define R_AX_CH9_TXBD_DESA_L_V1 0x1278
332 #define R_AX_CH9_TXBD_DESA_H_V1 0x127C
333 #define R_AX_CH12_TXBD_DESA_L_V1 0x1280
334 #define R_AX_CH12_TXBD_DESA_H_V1 0x1284
335 #define R_AX_CH10_TXBD_DESA_L_V1 0x1458
336 #define R_AX_CH10_TXBD_DESA_H_V1 0x145C
337 #define R_AX_CH11_TXBD_DESA_L_V1 0x1460
338 #define R_AX_CH11_TXBD_DESA_H_V1 0x1464
339 #define B_AX_DESC_NUM_MSK		GENMASK(11, 0)
340 
341 #define R_AX_RXQ_RXBD_NUM	0x1020
342 #define R_AX_RPQ_RXBD_NUM	0x1022
343 #define R_AX_ACH0_TXBD_NUM	0x1024
344 #define R_AX_ACH1_TXBD_NUM	0x1026
345 #define R_AX_ACH2_TXBD_NUM	0x1028
346 #define R_AX_ACH3_TXBD_NUM	0x102A
347 #define R_AX_ACH4_TXBD_NUM	0x102C
348 #define R_AX_ACH5_TXBD_NUM	0x102E
349 #define R_AX_ACH6_TXBD_NUM	0x1030
350 #define R_AX_ACH7_TXBD_NUM	0x1032
351 #define R_AX_CH8_TXBD_NUM	0x1034
352 #define R_AX_CH9_TXBD_NUM	0x1036
353 #define R_AX_CH10_TXBD_NUM	0x1338
354 #define R_AX_CH11_TXBD_NUM	0x133A
355 #define R_AX_CH12_TXBD_NUM	0x1038
356 #define R_AX_RXQ_RXBD_NUM_V1	0x1210
357 #define R_AX_RPQ_RXBD_NUM_V1	0x1212
358 #define R_AX_CH10_TXBD_NUM_V1	0x1438
359 #define R_AX_CH11_TXBD_NUM_V1	0x143A
360 
361 #define R_AX_ACH0_BDRAM_CTRL	0x1200
362 #define R_AX_ACH1_BDRAM_CTRL	0x1204
363 #define R_AX_ACH2_BDRAM_CTRL	0x1208
364 #define R_AX_ACH3_BDRAM_CTRL	0x120C
365 #define R_AX_ACH4_BDRAM_CTRL	0x1210
366 #define R_AX_ACH5_BDRAM_CTRL	0x1214
367 #define R_AX_ACH6_BDRAM_CTRL	0x1218
368 #define R_AX_ACH7_BDRAM_CTRL	0x121C
369 #define R_AX_CH8_BDRAM_CTRL	0x1220
370 #define R_AX_CH9_BDRAM_CTRL	0x1224
371 #define R_AX_CH10_BDRAM_CTRL	0x1320
372 #define R_AX_CH11_BDRAM_CTRL	0x1324
373 #define R_AX_CH12_BDRAM_CTRL	0x1228
374 #define R_AX_ACH0_BDRAM_CTRL_V1 0x1300
375 #define R_AX_ACH1_BDRAM_CTRL_V1 0x1304
376 #define R_AX_ACH2_BDRAM_CTRL_V1 0x1308
377 #define R_AX_ACH3_BDRAM_CTRL_V1 0x130C
378 #define R_AX_ACH4_BDRAM_CTRL_V1 0x1310
379 #define R_AX_ACH5_BDRAM_CTRL_V1 0x1314
380 #define R_AX_ACH6_BDRAM_CTRL_V1 0x1318
381 #define R_AX_ACH7_BDRAM_CTRL_V1 0x131C
382 #define R_AX_CH8_BDRAM_CTRL_V1 0x1320
383 #define R_AX_CH9_BDRAM_CTRL_V1 0x1324
384 #define R_AX_CH12_BDRAM_CTRL_V1 0x1328
385 #define R_AX_CH10_BDRAM_CTRL_V1 0x1420
386 #define R_AX_CH11_BDRAM_CTRL_V1 0x1424
387 #define BDRAM_SIDX_MASK		GENMASK(7, 0)
388 #define BDRAM_MAX_MASK		GENMASK(15, 8)
389 #define BDRAM_MIN_MASK		GENMASK(23, 16)
390 
391 #define R_AX_PCIE_INIT_CFG1	0x1000
392 #define B_AX_PCIE_RXRST_KEEP_REG	BIT(23)
393 #define B_AX_PCIE_TXRST_KEEP_REG	BIT(22)
394 #define B_AX_PCIE_PERST_KEEP_REG	BIT(21)
395 #define B_AX_PCIE_FLR_KEEP_REG		BIT(20)
396 #define B_AX_PCIE_TRAIN_KEEP_REG	BIT(19)
397 #define B_AX_RXBD_MODE			BIT(18)
398 #define B_AX_PCIE_MAX_RXDMA_MASK	GENMASK(16, 14)
399 #define B_AX_RXHCI_EN			BIT(13)
400 #define B_AX_LATENCY_CONTROL		BIT(12)
401 #define B_AX_TXHCI_EN			BIT(11)
402 #define B_AX_PCIE_MAX_TXDMA_MASK	GENMASK(10, 8)
403 #define B_AX_TX_TRUNC_MODE		BIT(5)
404 #define B_AX_RX_TRUNC_MODE		BIT(4)
405 #define B_AX_RST_BDRAM			BIT(3)
406 #define B_AX_DIS_RXDMA_PRE		BIT(2)
407 
408 #define R_AX_TXDMA_ADDR_H	0x10F0
409 #define R_AX_RXDMA_ADDR_H	0x10F4
410 
411 #define R_AX_PCIE_DMA_STOP1	0x1010
412 #define B_AX_STOP_PCIEIO		BIT(20)
413 #define B_AX_STOP_WPDMA			BIT(19)
414 #define B_AX_STOP_CH12			BIT(18)
415 #define B_AX_STOP_CH9			BIT(17)
416 #define B_AX_STOP_CH8			BIT(16)
417 #define B_AX_STOP_ACH7			BIT(15)
418 #define B_AX_STOP_ACH6			BIT(14)
419 #define B_AX_STOP_ACH5			BIT(13)
420 #define B_AX_STOP_ACH4			BIT(12)
421 #define B_AX_STOP_ACH3			BIT(11)
422 #define B_AX_STOP_ACH2			BIT(10)
423 #define B_AX_STOP_ACH1			BIT(9)
424 #define B_AX_STOP_ACH0			BIT(8)
425 #define B_AX_STOP_RPQ			BIT(1)
426 #define B_AX_STOP_RXQ			BIT(0)
427 #define B_AX_TX_STOP1_ALL		GENMASK(18, 8)
428 #define B_AX_TX_STOP1_MASK		(B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | \
429 					 B_AX_STOP_ACH2 | B_AX_STOP_ACH3 | \
430 					 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | \
431 					 B_AX_STOP_ACH6 | B_AX_STOP_ACH7 | \
432 					 B_AX_STOP_CH8 | B_AX_STOP_CH9 | \
433 					 B_AX_STOP_CH12)
434 #define B_AX_TX_STOP1_MASK_V1		(B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | \
435 					 B_AX_STOP_ACH2 | B_AX_STOP_ACH3 | \
436 					 B_AX_STOP_CH8 | B_AX_STOP_CH9 | \
437 					 B_AX_STOP_CH12)
438 
439 #define R_AX_PCIE_DMA_STOP2	0x1310
440 #define B_AX_STOP_CH11			BIT(1)
441 #define B_AX_STOP_CH10			BIT(0)
442 #define B_AX_TX_STOP2_ALL		GENMASK(1, 0)
443 
444 #define R_AX_TXBD_RWPTR_CLR1	0x1014
445 #define B_AX_CLR_CH12_IDX		BIT(10)
446 #define B_AX_CLR_CH9_IDX		BIT(9)
447 #define B_AX_CLR_CH8_IDX		BIT(8)
448 #define B_AX_CLR_ACH7_IDX		BIT(7)
449 #define B_AX_CLR_ACH6_IDX		BIT(6)
450 #define B_AX_CLR_ACH5_IDX		BIT(5)
451 #define B_AX_CLR_ACH4_IDX		BIT(4)
452 #define B_AX_CLR_ACH3_IDX		BIT(3)
453 #define B_AX_CLR_ACH2_IDX		BIT(2)
454 #define B_AX_CLR_ACH1_IDX		BIT(1)
455 #define B_AX_CLR_ACH0_IDX		BIT(0)
456 #define B_AX_TXBD_CLR1_ALL		GENMASK(10, 0)
457 
458 #define R_AX_RXBD_RWPTR_CLR	0x1018
459 #define B_AX_CLR_RPQ_IDX		BIT(1)
460 #define B_AX_CLR_RXQ_IDX		BIT(0)
461 #define B_AX_RXBD_CLR_ALL		GENMASK(1, 0)
462 
463 #define R_AX_TXBD_RWPTR_CLR2	0x1314
464 #define B_AX_CLR_CH11_IDX		BIT(1)
465 #define B_AX_CLR_CH10_IDX		BIT(0)
466 #define B_AX_TXBD_CLR2_ALL		GENMASK(1, 0)
467 
468 #define R_AX_PCIE_DMA_BUSY1	0x101C
469 #define B_AX_PCIEIO_RX_BUSY		BIT(22)
470 #define B_AX_PCIEIO_TX_BUSY		BIT(21)
471 #define B_AX_PCIEIO_BUSY		BIT(20)
472 #define B_AX_WPDMA_BUSY			BIT(19)
473 #define B_AX_CH12_BUSY			BIT(18)
474 #define B_AX_CH9_BUSY			BIT(17)
475 #define B_AX_CH8_BUSY			BIT(16)
476 #define B_AX_ACH7_BUSY			BIT(15)
477 #define B_AX_ACH6_BUSY			BIT(14)
478 #define B_AX_ACH5_BUSY			BIT(13)
479 #define B_AX_ACH4_BUSY			BIT(12)
480 #define B_AX_ACH3_BUSY			BIT(11)
481 #define B_AX_ACH2_BUSY			BIT(10)
482 #define B_AX_ACH1_BUSY			BIT(9)
483 #define B_AX_ACH0_BUSY			BIT(8)
484 #define B_AX_RPQ_BUSY			BIT(1)
485 #define B_AX_RXQ_BUSY			BIT(0)
486 #define DMA_BUSY1_CHECK		(B_AX_ACH0_BUSY | B_AX_ACH1_BUSY | B_AX_ACH2_BUSY | \
487 				 B_AX_ACH3_BUSY | B_AX_ACH4_BUSY | B_AX_ACH5_BUSY | \
488 				 B_AX_ACH6_BUSY | B_AX_ACH7_BUSY | B_AX_CH8_BUSY | \
489 				 B_AX_CH9_BUSY | B_AX_CH12_BUSY)
490 #define DMA_BUSY1_CHECK_V1	(B_AX_ACH0_BUSY | B_AX_ACH1_BUSY | B_AX_ACH2_BUSY | \
491 				 B_AX_ACH3_BUSY | B_AX_CH8_BUSY | B_AX_CH9_BUSY | \
492 				 B_AX_CH12_BUSY)
493 
494 #define R_AX_PCIE_DMA_BUSY2	0x131C
495 #define B_AX_CH11_BUSY			BIT(1)
496 #define B_AX_CH10_BUSY			BIT(0)
497 
498 /* Configure */
499 #define R_AX_PCIE_INIT_CFG2		0x1004
500 #define B_AX_WD_ITVL_IDLE		GENMASK(27, 24)
501 #define B_AX_WD_ITVL_ACT		GENMASK(19, 16)
502 #define B_AX_PCIE_RX_APPLEN_MASK	GENMASK(13, 0)
503 
504 #define R_AX_PCIE_PS_CTRL		0x1008
505 #define B_AX_L1OFF_PWR_OFF_EN		BIT(5)
506 
507 #define R_AX_INT_MIT_RX			0x10D4
508 #define B_AX_RXMIT_RXP2_SEL		BIT(19)
509 #define B_AX_RXMIT_RXP1_SEL		BIT(18)
510 #define B_AX_RXTIMER_UNIT_MASK		GENMASK(17, 16)
511 #define AX_RXTIMER_UNIT_64US		0
512 #define AX_RXTIMER_UNIT_128US		1
513 #define AX_RXTIMER_UNIT_256US		2
514 #define AX_RXTIMER_UNIT_512US		3
515 #define B_AX_RXCOUNTER_MATCH_MASK	GENMASK(15, 8)
516 #define B_AX_RXTIMER_MATCH_MASK		GENMASK(7, 0)
517 
518 #define R_AX_DBG_ERR_FLAG		0x11C4
519 #define B_AX_PCIE_RPQ_FULL		BIT(29)
520 #define B_AX_PCIE_RXQ_FULL		BIT(28)
521 #define B_AX_CPL_STATUS_MASK		GENMASK(27, 25)
522 #define B_AX_RX_STUCK			BIT(22)
523 #define B_AX_TX_STUCK			BIT(21)
524 #define B_AX_PCIEDBG_TXERR0		BIT(16)
525 #define B_AX_PCIE_RXP1_ERR0		BIT(4)
526 #define B_AX_PCIE_TXBD_LEN0		BIT(1)
527 #define B_AX_PCIE_TXBD_4KBOUD_LENERR	BIT(0)
528 
529 #define R_AX_TXBD_RWPTR_CLR2_V1		0x11C4
530 #define B_AX_CLR_CH11_IDX		BIT(1)
531 #define B_AX_CLR_CH10_IDX		BIT(0)
532 
533 #define R_AX_LBC_WATCHDOG		0x11D8
534 #define B_AX_LBC_TIMER			GENMASK(7, 4)
535 #define B_AX_LBC_FLAG			BIT(1)
536 #define B_AX_LBC_EN			BIT(0)
537 
538 #define R_AX_RXBD_RWPTR_CLR_V1		0x1200
539 #define B_AX_CLR_RPQ_IDX		BIT(1)
540 #define B_AX_CLR_RXQ_IDX		BIT(0)
541 
542 #define R_AX_HAXI_EXP_CTRL		0x1204
543 #define B_AX_MAX_TAG_NUM_V1_MASK	GENMASK(2, 0)
544 
545 #define R_AX_PCIE_EXP_CTRL		0x13F0
546 #define B_AX_EN_CHKDSC_NO_RX_STUCK	BIT(20)
547 #define B_AX_MAX_TAG_NUM		GENMASK(18, 16)
548 #define B_AX_SIC_EN_FORCE_CLKREQ	BIT(4)
549 
550 #define R_AX_PCIE_RX_PREF_ADV		0x13F4
551 #define B_AX_RXDMA_PREF_ADV_EN		BIT(0)
552 
553 #define R_AX_PCIE_HRPWM_V1		0x30C0
554 #define R_AX_PCIE_CRPWM			0x30C4
555 
556 #define RTW89_PCI_TXBD_NUM_MAX		256
557 #define RTW89_PCI_RXBD_NUM_MAX		256
558 #define RTW89_PCI_TXWD_NUM_MAX		512
559 #define RTW89_PCI_TXWD_PAGE_SIZE	128
560 #define RTW89_PCI_ADDRINFO_MAX		4
561 #define RTW89_PCI_RX_BUF_SIZE		11460
562 
563 #define RTW89_PCI_POLL_BDRAM_RST_CNT	100
564 #define RTW89_PCI_MULTITAG		8
565 
566 /* PCIE CFG register */
567 #define RTW89_PCIE_L1_STS_V1		0x80
568 #define RTW89_BCFG_LINK_SPEED_MASK	GENMASK(19, 16)
569 #define RTW89_PCIE_GEN1_SPEED		0x01
570 #define RTW89_PCIE_GEN2_SPEED		0x02
571 #define RTW89_PCIE_PHY_RATE		0x82
572 #define RTW89_PCIE_PHY_RATE_MASK	GENMASK(1, 0)
573 #define RTW89_PCIE_L1SS_STS_V1		0x0168
574 #define RTW89_PCIE_BIT_ASPM_L11		BIT(3)
575 #define RTW89_PCIE_BIT_ASPM_L12		BIT(2)
576 #define RTW89_PCIE_BIT_PCI_L11		BIT(1)
577 #define RTW89_PCIE_BIT_PCI_L12		BIT(0)
578 #define RTW89_PCIE_ASPM_CTRL		0x070F
579 #define RTW89_L1DLY_MASK		GENMASK(5, 3)
580 #define RTW89_L0DLY_MASK		GENMASK(2, 0)
581 #define RTW89_PCIE_TIMER_CTRL		0x0718
582 #define RTW89_PCIE_BIT_L1SUB		BIT(5)
583 #define RTW89_PCIE_L1_CTRL		0x0719
584 #define RTW89_PCIE_BIT_CLK		BIT(4)
585 #define RTW89_PCIE_BIT_L1		BIT(3)
586 #define RTW89_PCIE_CLK_CTRL		0x0725
587 #define RTW89_PCIE_RST_MSTATE		0x0B48
588 #define RTW89_PCIE_BIT_CFG_RST_MSTATE	BIT(0)
589 
590 #define INTF_INTGRA_MINREF_V1	90
591 #define INTF_INTGRA_HOSTREF_V1	100
592 
593 enum rtw89_pcie_phy {
594 	PCIE_PHY_GEN1,
595 	PCIE_PHY_GEN2,
596 	PCIE_PHY_GEN1_UNDEFINE = 0x7F,
597 };
598 
599 enum rtw89_pcie_l0sdly {
600 	PCIE_L0SDLY_1US = 0,
601 	PCIE_L0SDLY_2US = 1,
602 	PCIE_L0SDLY_3US = 2,
603 	PCIE_L0SDLY_4US = 3,
604 	PCIE_L0SDLY_5US = 4,
605 	PCIE_L0SDLY_6US = 5,
606 	PCIE_L0SDLY_7US = 6,
607 };
608 
609 enum rtw89_pcie_l1dly {
610 	PCIE_L1DLY_16US = 4,
611 	PCIE_L1DLY_32US = 5,
612 	PCIE_L1DLY_64US = 6,
613 	PCIE_L1DLY_HW_INFI = 7,
614 };
615 
616 enum rtw89_pcie_clkdly_hw {
617 	PCIE_CLKDLY_HW_0 = 0,
618 	PCIE_CLKDLY_HW_30US = 0x1,
619 	PCIE_CLKDLY_HW_50US = 0x2,
620 	PCIE_CLKDLY_HW_100US = 0x3,
621 	PCIE_CLKDLY_HW_150US = 0x4,
622 	PCIE_CLKDLY_HW_200US = 0x5,
623 };
624 
625 enum mac_ax_bd_trunc_mode {
626 	MAC_AX_BD_NORM,
627 	MAC_AX_BD_TRUNC,
628 	MAC_AX_BD_DEF = 0xFE
629 };
630 
631 enum mac_ax_rxbd_mode {
632 	MAC_AX_RXBD_PKT,
633 	MAC_AX_RXBD_SEP,
634 	MAC_AX_RXBD_DEF = 0xFE
635 };
636 
637 enum mac_ax_tag_mode {
638 	MAC_AX_TAG_SGL,
639 	MAC_AX_TAG_MULTI,
640 	MAC_AX_TAG_DEF = 0xFE
641 };
642 
643 enum mac_ax_tx_burst {
644 	MAC_AX_TX_BURST_16B = 0,
645 	MAC_AX_TX_BURST_32B = 1,
646 	MAC_AX_TX_BURST_64B = 2,
647 	MAC_AX_TX_BURST_V1_64B = 0,
648 	MAC_AX_TX_BURST_128B = 3,
649 	MAC_AX_TX_BURST_V1_128B = 1,
650 	MAC_AX_TX_BURST_256B = 4,
651 	MAC_AX_TX_BURST_V1_256B = 2,
652 	MAC_AX_TX_BURST_512B = 5,
653 	MAC_AX_TX_BURST_1024B = 6,
654 	MAC_AX_TX_BURST_2048B = 7,
655 	MAC_AX_TX_BURST_DEF = 0xFE
656 };
657 
658 enum mac_ax_rx_burst {
659 	MAC_AX_RX_BURST_16B = 0,
660 	MAC_AX_RX_BURST_32B = 1,
661 	MAC_AX_RX_BURST_64B = 2,
662 	MAC_AX_RX_BURST_V1_64B = 0,
663 	MAC_AX_RX_BURST_128B = 3,
664 	MAC_AX_RX_BURST_V1_128B = 1,
665 	MAC_AX_RX_BURST_V1_256B = 0,
666 	MAC_AX_RX_BURST_DEF = 0xFE
667 };
668 
669 enum mac_ax_wd_dma_intvl {
670 	MAC_AX_WD_DMA_INTVL_0S,
671 	MAC_AX_WD_DMA_INTVL_256NS,
672 	MAC_AX_WD_DMA_INTVL_512NS,
673 	MAC_AX_WD_DMA_INTVL_768NS,
674 	MAC_AX_WD_DMA_INTVL_1US,
675 	MAC_AX_WD_DMA_INTVL_1_5US,
676 	MAC_AX_WD_DMA_INTVL_2US,
677 	MAC_AX_WD_DMA_INTVL_4US,
678 	MAC_AX_WD_DMA_INTVL_8US,
679 	MAC_AX_WD_DMA_INTVL_16US,
680 	MAC_AX_WD_DMA_INTVL_DEF = 0xFE
681 };
682 
683 enum mac_ax_multi_tag_num {
684 	MAC_AX_TAG_NUM_1,
685 	MAC_AX_TAG_NUM_2,
686 	MAC_AX_TAG_NUM_3,
687 	MAC_AX_TAG_NUM_4,
688 	MAC_AX_TAG_NUM_5,
689 	MAC_AX_TAG_NUM_6,
690 	MAC_AX_TAG_NUM_7,
691 	MAC_AX_TAG_NUM_8,
692 	MAC_AX_TAG_NUM_DEF = 0xFE
693 };
694 
695 enum mac_ax_lbc_tmr {
696 	MAC_AX_LBC_TMR_8US = 0,
697 	MAC_AX_LBC_TMR_16US,
698 	MAC_AX_LBC_TMR_32US,
699 	MAC_AX_LBC_TMR_64US,
700 	MAC_AX_LBC_TMR_128US,
701 	MAC_AX_LBC_TMR_256US,
702 	MAC_AX_LBC_TMR_512US,
703 	MAC_AX_LBC_TMR_1MS,
704 	MAC_AX_LBC_TMR_2MS,
705 	MAC_AX_LBC_TMR_4MS,
706 	MAC_AX_LBC_TMR_8MS,
707 	MAC_AX_LBC_TMR_DEF = 0xFE
708 };
709 
710 enum mac_ax_pcie_func_ctrl {
711 	MAC_AX_PCIE_DISABLE = 0,
712 	MAC_AX_PCIE_ENABLE = 1,
713 	MAC_AX_PCIE_DEFAULT = 0xFE,
714 	MAC_AX_PCIE_IGNORE = 0xFF
715 };
716 
717 enum mac_ax_io_rcy_tmr {
718 	MAC_AX_IO_RCY_ANA_TMR_2MS = 24000,
719 	MAC_AX_IO_RCY_ANA_TMR_4MS = 48000,
720 	MAC_AX_IO_RCY_ANA_TMR_6MS = 72000,
721 	MAC_AX_IO_RCY_ANA_TMR_DEF = 0xFE
722 };
723 
724 enum rtw89_pci_intr_mask_cfg {
725 	RTW89_PCI_INTR_MASK_RESET,
726 	RTW89_PCI_INTR_MASK_NORMAL,
727 	RTW89_PCI_INTR_MASK_LOW_POWER,
728 	RTW89_PCI_INTR_MASK_RECOVERY_START,
729 	RTW89_PCI_INTR_MASK_RECOVERY_COMPLETE,
730 };
731 
732 struct rtw89_pci_isrs;
733 struct rtw89_pci;
734 
735 struct rtw89_pci_bd_idx_addr {
736 	u32 tx_bd_addrs[RTW89_TXCH_NUM];
737 	u32 rx_bd_addrs[RTW89_RXCH_NUM];
738 };
739 
740 struct rtw89_pci_ch_dma_addr {
741 	u32 num;
742 	u32 idx;
743 	u32 bdram;
744 	u32 desa_l;
745 	u32 desa_h;
746 };
747 
748 struct rtw89_pci_ch_dma_addr_set {
749 	struct rtw89_pci_ch_dma_addr tx[RTW89_TXCH_NUM];
750 	struct rtw89_pci_ch_dma_addr rx[RTW89_RXCH_NUM];
751 };
752 
753 struct rtw89_pci_bd_ram {
754 	u8 start_idx;
755 	u8 max_num;
756 	u8 min_num;
757 };
758 
759 struct rtw89_pci_info {
760 	enum mac_ax_bd_trunc_mode txbd_trunc_mode;
761 	enum mac_ax_bd_trunc_mode rxbd_trunc_mode;
762 	enum mac_ax_rxbd_mode rxbd_mode;
763 	enum mac_ax_tag_mode tag_mode;
764 	enum mac_ax_tx_burst tx_burst;
765 	enum mac_ax_rx_burst rx_burst;
766 	enum mac_ax_wd_dma_intvl wd_dma_idle_intvl;
767 	enum mac_ax_wd_dma_intvl wd_dma_act_intvl;
768 	enum mac_ax_multi_tag_num multi_tag_num;
769 	enum mac_ax_pcie_func_ctrl lbc_en;
770 	enum mac_ax_lbc_tmr lbc_tmr;
771 	enum mac_ax_pcie_func_ctrl autok_en;
772 	enum mac_ax_pcie_func_ctrl io_rcy_en;
773 	enum mac_ax_io_rcy_tmr io_rcy_tmr;
774 
775 	u32 init_cfg_reg;
776 	u32 txhci_en_bit;
777 	u32 rxhci_en_bit;
778 	u32 rxbd_mode_bit;
779 	u32 exp_ctrl_reg;
780 	u32 max_tag_num_mask;
781 	u32 rxbd_rwptr_clr_reg;
782 	u32 txbd_rwptr_clr2_reg;
783 	struct rtw89_reg_def dma_stop1;
784 	struct rtw89_reg_def dma_stop2;
785 	struct rtw89_reg_def dma_busy1;
786 	u32 dma_busy2_reg;
787 	u32 dma_busy3_reg;
788 
789 	u32 rpwm_addr;
790 	u32 cpwm_addr;
791 	u32 tx_dma_ch_mask;
792 	const struct rtw89_pci_bd_idx_addr *bd_idx_addr_low_power;
793 	const struct rtw89_pci_ch_dma_addr_set *dma_addr_set;
794 	const struct rtw89_pci_bd_ram (*bd_ram_table)[RTW89_TXCH_NUM];
795 
796 	int (*ltr_set)(struct rtw89_dev *rtwdev, bool en);
797 	u32 (*fill_txaddr_info)(struct rtw89_dev *rtwdev,
798 				void *txaddr_info_addr, u32 total_len,
799 				dma_addr_t dma, u8 *add_info_nr);
800 	void (*config_intr_mask)(struct rtw89_dev *rtwdev);
801 	void (*enable_intr)(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
802 	void (*disable_intr)(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
803 	void (*recognize_intrs)(struct rtw89_dev *rtwdev,
804 				struct rtw89_pci *rtwpci,
805 				struct rtw89_pci_isrs *isrs);
806 };
807 
808 struct rtw89_pci_tx_data {
809 	dma_addr_t dma;
810 };
811 
812 struct rtw89_pci_rx_info {
813 	dma_addr_t dma;
814 	u32 fs:1, ls:1, tag:11, len:14;
815 };
816 
817 #define RTW89_PCI_TXBD_OPTION_LS	BIT(14)
818 
819 struct rtw89_pci_tx_bd_32 {
820 	__le16 length;
821 	__le16 option;
822 	__le32 dma;
823 } __packed;
824 
825 #define RTW89_PCI_TXWP_VALID		BIT(15)
826 
827 struct rtw89_pci_tx_wp_info {
828 	__le16 seq0;
829 	__le16 seq1;
830 	__le16 seq2;
831 	__le16 seq3;
832 } __packed;
833 
834 #define RTW89_PCI_ADDR_MSDU_LS		BIT(15)
835 #define RTW89_PCI_ADDR_LS		BIT(14)
836 #define RTW89_PCI_ADDR_HIGH(a)		(((a) << 6) & GENMASK(13, 6))
837 #define RTW89_PCI_ADDR_NUM(x)		((x) & GENMASK(5, 0))
838 
839 struct rtw89_pci_tx_addr_info_32 {
840 	__le16 length;
841 	__le16 option;
842 	__le32 dma;
843 } __packed;
844 
845 #define RTW89_TXADDR_INFO_NR_V1		10
846 
847 struct rtw89_pci_tx_addr_info_32_v1 {
848 	__le16 length_opt;
849 #define B_PCIADDR_LEN_V1_MASK		GENMASK(10, 0)
850 #define B_PCIADDR_HIGH_SEL_V1_MASK	GENMASK(14, 11)
851 #define B_PCIADDR_LS_V1_MASK		BIT(15)
852 #define TXADDR_INFO_LENTHG_V1_MAX	ALIGN_DOWN(BIT(11) - 1, 4)
853 	__le16 dma_low_lsb;
854 	__le16 dma_low_msb;
855 } __packed;
856 
857 #define RTW89_PCI_RPP_POLLUTED		BIT(31)
858 #define RTW89_PCI_RPP_SEQ		GENMASK(30, 16)
859 #define RTW89_PCI_RPP_TX_STATUS		GENMASK(15, 13)
860 #define RTW89_TX_DONE			0x0
861 #define RTW89_TX_RETRY_LIMIT		0x1
862 #define RTW89_TX_LIFE_TIME		0x2
863 #define RTW89_TX_MACID_DROP		0x3
864 #define RTW89_PCI_RPP_QSEL		GENMASK(12, 8)
865 #define RTW89_PCI_RPP_MACID		GENMASK(7, 0)
866 
867 struct rtw89_pci_rpp_fmt {
868 	__le32 dword;
869 } __packed;
870 
871 struct rtw89_pci_rx_bd_32 {
872 	__le16 buf_size;
873 	__le16 rsvd;
874 	__le32 dma;
875 } __packed;
876 
877 #define RTW89_PCI_RXBD_FS		BIT(15)
878 #define RTW89_PCI_RXBD_LS		BIT(14)
879 #define RTW89_PCI_RXBD_WRITE_SIZE	GENMASK(13, 0)
880 #define RTW89_PCI_RXBD_TAG		GENMASK(28, 16)
881 
882 struct rtw89_pci_rxbd_info {
883 	__le32 dword;
884 };
885 
886 struct rtw89_pci_tx_wd {
887 	struct list_head list;
888 	struct sk_buff_head queue;
889 
890 	void *vaddr;
891 	dma_addr_t paddr;
892 	u32 len;
893 	u32 seq;
894 };
895 
896 struct rtw89_pci_dma_ring {
897 	void *head;
898 	u8 desc_size;
899 	dma_addr_t dma;
900 
901 	struct rtw89_pci_ch_dma_addr addr;
902 
903 	u32 len;
904 	u32 wp; /* host idx */
905 	u32 rp; /* hw idx */
906 };
907 
908 struct rtw89_pci_tx_wd_ring {
909 	void *head;
910 	dma_addr_t dma;
911 
912 	struct rtw89_pci_tx_wd pages[RTW89_PCI_TXWD_NUM_MAX];
913 	struct list_head free_pages;
914 
915 	u32 page_size;
916 	u32 page_num;
917 	u32 curr_num;
918 };
919 
920 #define RTW89_RX_TAG_MAX		0x1fff
921 
922 struct rtw89_pci_tx_ring {
923 	struct rtw89_pci_tx_wd_ring wd_ring;
924 	struct rtw89_pci_dma_ring bd_ring;
925 	struct list_head busy_pages;
926 	u8 txch;
927 	bool dma_enabled;
928 	u16 tag; /* range from 0x0001 ~ 0x1fff */
929 
930 	u64 tx_cnt;
931 	u64 tx_acked;
932 	u64 tx_retry_lmt;
933 	u64 tx_life_time;
934 	u64 tx_mac_id_drop;
935 };
936 
937 struct rtw89_pci_rx_ring {
938 	struct rtw89_pci_dma_ring bd_ring;
939 	struct sk_buff *buf[RTW89_PCI_RXBD_NUM_MAX];
940 	u32 buf_sz;
941 	struct sk_buff *diliver_skb;
942 	struct rtw89_rx_desc_info diliver_desc;
943 };
944 
945 struct rtw89_pci_isrs {
946 	u32 ind_isrs;
947 	u32 halt_c2h_isrs;
948 	u32 isrs[2];
949 };
950 
951 struct rtw89_pci {
952 	struct pci_dev *pdev;
953 
954 	/* protect HW irq related registers */
955 	spinlock_t irq_lock;
956 	/* protect TRX resources (exclude RXQ) */
957 	spinlock_t trx_lock;
958 	bool running;
959 	bool low_power;
960 	bool under_recovery;
961 	struct rtw89_pci_tx_ring tx_rings[RTW89_TXCH_NUM];
962 	struct rtw89_pci_rx_ring rx_rings[RTW89_RXCH_NUM];
963 	struct sk_buff_head h2c_queue;
964 	struct sk_buff_head h2c_release_queue;
965 	DECLARE_BITMAP(kick_map, RTW89_TXCH_NUM);
966 
967 	u32 ind_intrs;
968 	u32 halt_c2h_intrs;
969 	u32 intrs[2];
970 	void __iomem *mmap;
971 };
972 
973 static inline struct rtw89_pci_rx_info *RTW89_PCI_RX_SKB_CB(struct sk_buff *skb)
974 {
975 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
976 
977 	BUILD_BUG_ON(sizeof(struct rtw89_pci_tx_data) >
978 		     sizeof(info->status.status_driver_data));
979 
980 	return (struct rtw89_pci_rx_info *)skb->cb;
981 }
982 
983 static inline struct rtw89_pci_rx_bd_32 *
984 RTW89_PCI_RX_BD(struct rtw89_pci_rx_ring *rx_ring, u32 idx)
985 {
986 	struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
987 	u8 *head = bd_ring->head;
988 	u32 desc_size = bd_ring->desc_size;
989 	u32 offset = idx * desc_size;
990 
991 	return (struct rtw89_pci_rx_bd_32 *)(head + offset);
992 }
993 
994 static inline void
995 rtw89_pci_rxbd_increase(struct rtw89_pci_rx_ring *rx_ring, u32 cnt)
996 {
997 	struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
998 
999 	bd_ring->wp += cnt;
1000 
1001 	if (bd_ring->wp >= bd_ring->len)
1002 		bd_ring->wp -= bd_ring->len;
1003 }
1004 
1005 static inline struct rtw89_pci_tx_data *RTW89_PCI_TX_SKB_CB(struct sk_buff *skb)
1006 {
1007 	struct rtw89_tx_skb_data *data = RTW89_TX_SKB_CB(skb);
1008 
1009 	return (struct rtw89_pci_tx_data *)data->hci_priv;
1010 }
1011 
1012 static inline struct rtw89_pci_tx_bd_32 *
1013 rtw89_pci_get_next_txbd(struct rtw89_pci_tx_ring *tx_ring)
1014 {
1015 	struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring;
1016 	struct rtw89_pci_tx_bd_32 *tx_bd, *head;
1017 
1018 	head = bd_ring->head;
1019 	tx_bd = head + bd_ring->wp;
1020 
1021 	return tx_bd;
1022 }
1023 
1024 static inline struct rtw89_pci_tx_wd *
1025 rtw89_pci_dequeue_txwd(struct rtw89_pci_tx_ring *tx_ring)
1026 {
1027 	struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
1028 	struct rtw89_pci_tx_wd *txwd;
1029 
1030 	txwd = list_first_entry_or_null(&wd_ring->free_pages,
1031 					struct rtw89_pci_tx_wd, list);
1032 	if (!txwd)
1033 		return NULL;
1034 
1035 	list_del_init(&txwd->list);
1036 	txwd->len = 0;
1037 	wd_ring->curr_num--;
1038 
1039 	return txwd;
1040 }
1041 
1042 static inline void
1043 rtw89_pci_enqueue_txwd(struct rtw89_pci_tx_ring *tx_ring,
1044 		       struct rtw89_pci_tx_wd *txwd)
1045 {
1046 	struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
1047 
1048 	memset(txwd->vaddr, 0, wd_ring->page_size);
1049 	list_add_tail(&txwd->list, &wd_ring->free_pages);
1050 	wd_ring->curr_num++;
1051 }
1052 
1053 static inline bool rtw89_pci_ltr_is_err_reg_val(u32 val)
1054 {
1055 	return val == 0xffffffff || val == 0xeaeaeaea;
1056 }
1057 
1058 extern const struct dev_pm_ops rtw89_pm_ops;
1059 extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set;
1060 extern const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_v1;
1061 extern const struct rtw89_pci_bd_ram rtw89_bd_ram_table_dual[RTW89_TXCH_NUM];
1062 extern const struct rtw89_pci_bd_ram rtw89_bd_ram_table_single[RTW89_TXCH_NUM];
1063 
1064 struct pci_device_id;
1065 
1066 int rtw89_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
1067 void rtw89_pci_remove(struct pci_dev *pdev);
1068 int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev, bool en);
1069 int rtw89_pci_ltr_set_v1(struct rtw89_dev *rtwdev, bool en);
1070 u32 rtw89_pci_fill_txaddr_info(struct rtw89_dev *rtwdev,
1071 			       void *txaddr_info_addr, u32 total_len,
1072 			       dma_addr_t dma, u8 *add_info_nr);
1073 u32 rtw89_pci_fill_txaddr_info_v1(struct rtw89_dev *rtwdev,
1074 				  void *txaddr_info_addr, u32 total_len,
1075 				  dma_addr_t dma, u8 *add_info_nr);
1076 void rtw89_pci_config_intr_mask(struct rtw89_dev *rtwdev);
1077 void rtw89_pci_config_intr_mask_v1(struct rtw89_dev *rtwdev);
1078 void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1079 void rtw89_pci_disable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1080 void rtw89_pci_enable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1081 void rtw89_pci_disable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci);
1082 void rtw89_pci_recognize_intrs(struct rtw89_dev *rtwdev,
1083 			       struct rtw89_pci *rtwpci,
1084 			       struct rtw89_pci_isrs *isrs);
1085 void rtw89_pci_recognize_intrs_v1(struct rtw89_dev *rtwdev,
1086 				  struct rtw89_pci *rtwpci,
1087 				  struct rtw89_pci_isrs *isrs);
1088 
1089 static inline
1090 u32 rtw89_chip_fill_txaddr_info(struct rtw89_dev *rtwdev,
1091 				void *txaddr_info_addr, u32 total_len,
1092 				dma_addr_t dma, u8 *add_info_nr)
1093 {
1094 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1095 
1096 	return info->fill_txaddr_info(rtwdev, txaddr_info_addr, total_len,
1097 				      dma, add_info_nr);
1098 }
1099 
1100 static inline void rtw89_chip_config_intr_mask(struct rtw89_dev *rtwdev,
1101 					       enum rtw89_pci_intr_mask_cfg cfg)
1102 {
1103 	struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1104 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1105 
1106 	switch (cfg) {
1107 	default:
1108 	case RTW89_PCI_INTR_MASK_RESET:
1109 		rtwpci->low_power = false;
1110 		rtwpci->under_recovery = false;
1111 		break;
1112 	case RTW89_PCI_INTR_MASK_NORMAL:
1113 		rtwpci->low_power = false;
1114 		break;
1115 	case RTW89_PCI_INTR_MASK_LOW_POWER:
1116 		rtwpci->low_power = true;
1117 		break;
1118 	case RTW89_PCI_INTR_MASK_RECOVERY_START:
1119 		rtwpci->under_recovery = true;
1120 		break;
1121 	case RTW89_PCI_INTR_MASK_RECOVERY_COMPLETE:
1122 		rtwpci->under_recovery = false;
1123 		break;
1124 	}
1125 
1126 	rtw89_debug(rtwdev, RTW89_DBG_HCI,
1127 		    "Configure PCI interrupt mask mode low_power=%d under_recovery=%d\n",
1128 		    rtwpci->low_power, rtwpci->under_recovery);
1129 
1130 	info->config_intr_mask(rtwdev);
1131 }
1132 
1133 static inline
1134 void rtw89_chip_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
1135 {
1136 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1137 
1138 	info->enable_intr(rtwdev, rtwpci);
1139 }
1140 
1141 static inline
1142 void rtw89_chip_disable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
1143 {
1144 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1145 
1146 	info->disable_intr(rtwdev, rtwpci);
1147 }
1148 
1149 static inline
1150 void rtw89_chip_recognize_intrs(struct rtw89_dev *rtwdev,
1151 				struct rtw89_pci *rtwpci,
1152 				struct rtw89_pci_isrs *isrs)
1153 {
1154 	const struct rtw89_pci_info *info = rtwdev->pci_info;
1155 
1156 	info->recognize_intrs(rtwdev, rtwpci, isrs);
1157 }
1158 
1159 #endif
1160