1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2020 Realtek Corporation 3 */ 4 5 #include <linux/pci.h> 6 7 #include "mac.h" 8 #include "pci.h" 9 #include "reg.h" 10 #include "ser.h" 11 12 static bool rtw89_pci_disable_clkreq; 13 static bool rtw89_pci_disable_aspm_l1; 14 static bool rtw89_pci_disable_l1ss; 15 module_param_named(disable_clkreq, rtw89_pci_disable_clkreq, bool, 0644); 16 module_param_named(disable_aspm_l1, rtw89_pci_disable_aspm_l1, bool, 0644); 17 module_param_named(disable_aspm_l1ss, rtw89_pci_disable_l1ss, bool, 0644); 18 MODULE_PARM_DESC(disable_clkreq, "Set Y to disable PCI clkreq support"); 19 MODULE_PARM_DESC(disable_aspm_l1, "Set Y to disable PCI ASPM L1 support"); 20 MODULE_PARM_DESC(disable_aspm_l1ss, "Set Y to disable PCI L1SS support"); 21 22 static int rtw89_pci_rst_bdram_pcie(struct rtw89_dev *rtwdev) 23 { 24 u32 val; 25 int ret; 26 27 rtw89_write32(rtwdev, R_AX_PCIE_INIT_CFG1, 28 rtw89_read32(rtwdev, R_AX_PCIE_INIT_CFG1) | B_AX_RST_BDRAM); 29 30 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_RST_BDRAM), 31 1, RTW89_PCI_POLL_BDRAM_RST_CNT, false, 32 rtwdev, R_AX_PCIE_INIT_CFG1); 33 34 if (ret) 35 return -EBUSY; 36 37 return 0; 38 } 39 40 static u32 rtw89_pci_dma_recalc(struct rtw89_dev *rtwdev, 41 struct rtw89_pci_dma_ring *bd_ring, 42 u32 cur_idx, bool tx) 43 { 44 u32 cnt, cur_rp, wp, rp, len; 45 46 rp = bd_ring->rp; 47 wp = bd_ring->wp; 48 len = bd_ring->len; 49 50 cur_rp = FIELD_GET(TXBD_HW_IDX_MASK, cur_idx); 51 if (tx) 52 cnt = cur_rp >= rp ? cur_rp - rp : len - (rp - cur_rp); 53 else 54 cnt = cur_rp >= wp ? cur_rp - wp : len - (wp - cur_rp); 55 56 bd_ring->rp = cur_rp; 57 58 return cnt; 59 } 60 61 static u32 rtw89_pci_txbd_recalc(struct rtw89_dev *rtwdev, 62 struct rtw89_pci_tx_ring *tx_ring) 63 { 64 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; 65 u32 addr_idx = bd_ring->addr.idx; 66 u32 cnt, idx; 67 68 idx = rtw89_read32(rtwdev, addr_idx); 69 cnt = rtw89_pci_dma_recalc(rtwdev, bd_ring, idx, true); 70 71 return cnt; 72 } 73 74 static void rtw89_pci_release_fwcmd(struct rtw89_dev *rtwdev, 75 struct rtw89_pci *rtwpci, 76 u32 cnt, bool release_all) 77 { 78 struct rtw89_pci_tx_data *tx_data; 79 struct sk_buff *skb; 80 u32 qlen; 81 82 while (cnt--) { 83 skb = skb_dequeue(&rtwpci->h2c_queue); 84 if (!skb) { 85 rtw89_err(rtwdev, "failed to pre-release fwcmd\n"); 86 return; 87 } 88 skb_queue_tail(&rtwpci->h2c_release_queue, skb); 89 } 90 91 qlen = skb_queue_len(&rtwpci->h2c_release_queue); 92 if (!release_all) 93 qlen = qlen > RTW89_PCI_MULTITAG ? qlen - RTW89_PCI_MULTITAG : 0; 94 95 while (qlen--) { 96 skb = skb_dequeue(&rtwpci->h2c_release_queue); 97 if (!skb) { 98 rtw89_err(rtwdev, "failed to release fwcmd\n"); 99 return; 100 } 101 tx_data = RTW89_PCI_TX_SKB_CB(skb); 102 dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len, 103 DMA_TO_DEVICE); 104 dev_kfree_skb_any(skb); 105 } 106 } 107 108 static void rtw89_pci_reclaim_tx_fwcmd(struct rtw89_dev *rtwdev, 109 struct rtw89_pci *rtwpci) 110 { 111 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[RTW89_TXCH_CH12]; 112 u32 cnt; 113 114 cnt = rtw89_pci_txbd_recalc(rtwdev, tx_ring); 115 if (!cnt) 116 return; 117 rtw89_pci_release_fwcmd(rtwdev, rtwpci, cnt, false); 118 } 119 120 static u32 rtw89_pci_rxbd_recalc(struct rtw89_dev *rtwdev, 121 struct rtw89_pci_rx_ring *rx_ring) 122 { 123 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 124 u32 addr_idx = bd_ring->addr.idx; 125 u32 cnt, idx; 126 127 idx = rtw89_read32(rtwdev, addr_idx); 128 cnt = rtw89_pci_dma_recalc(rtwdev, bd_ring, idx, false); 129 130 return cnt; 131 } 132 133 static void rtw89_pci_sync_skb_for_cpu(struct rtw89_dev *rtwdev, 134 struct sk_buff *skb) 135 { 136 struct rtw89_pci_rx_info *rx_info; 137 dma_addr_t dma; 138 139 rx_info = RTW89_PCI_RX_SKB_CB(skb); 140 dma = rx_info->dma; 141 dma_sync_single_for_cpu(rtwdev->dev, dma, RTW89_PCI_RX_BUF_SIZE, 142 DMA_FROM_DEVICE); 143 } 144 145 static void rtw89_pci_sync_skb_for_device(struct rtw89_dev *rtwdev, 146 struct sk_buff *skb) 147 { 148 struct rtw89_pci_rx_info *rx_info; 149 dma_addr_t dma; 150 151 rx_info = RTW89_PCI_RX_SKB_CB(skb); 152 dma = rx_info->dma; 153 dma_sync_single_for_device(rtwdev->dev, dma, RTW89_PCI_RX_BUF_SIZE, 154 DMA_FROM_DEVICE); 155 } 156 157 static int rtw89_pci_rxbd_info_update(struct rtw89_dev *rtwdev, 158 struct sk_buff *skb) 159 { 160 struct rtw89_pci_rxbd_info *rxbd_info; 161 struct rtw89_pci_rx_info *rx_info = RTW89_PCI_RX_SKB_CB(skb); 162 163 rxbd_info = (struct rtw89_pci_rxbd_info *)skb->data; 164 rx_info->fs = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_FS); 165 rx_info->ls = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_LS); 166 rx_info->len = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_WRITE_SIZE); 167 rx_info->tag = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_TAG); 168 169 return 0; 170 } 171 172 static void rtw89_pci_ctrl_txdma_ch_pcie(struct rtw89_dev *rtwdev, bool enable) 173 { 174 const struct rtw89_pci_info *info = rtwdev->pci_info; 175 const struct rtw89_reg_def *dma_stop1 = &info->dma_stop1; 176 const struct rtw89_reg_def *dma_stop2 = &info->dma_stop2; 177 178 if (enable) { 179 rtw89_write32_clr(rtwdev, dma_stop1->addr, dma_stop1->mask); 180 if (dma_stop2->addr) 181 rtw89_write32_clr(rtwdev, dma_stop2->addr, dma_stop2->mask); 182 } else { 183 rtw89_write32_set(rtwdev, dma_stop1->addr, dma_stop1->mask); 184 if (dma_stop2->addr) 185 rtw89_write32_set(rtwdev, dma_stop2->addr, dma_stop2->mask); 186 } 187 } 188 189 static void rtw89_pci_ctrl_txdma_fw_ch_pcie(struct rtw89_dev *rtwdev, bool enable) 190 { 191 const struct rtw89_pci_info *info = rtwdev->pci_info; 192 const struct rtw89_reg_def *dma_stop1 = &info->dma_stop1; 193 194 if (enable) 195 rtw89_write32_clr(rtwdev, dma_stop1->addr, B_AX_STOP_CH12); 196 else 197 rtw89_write32_set(rtwdev, dma_stop1->addr, B_AX_STOP_CH12); 198 } 199 200 static bool 201 rtw89_skb_put_rx_data(struct rtw89_dev *rtwdev, bool fs, bool ls, 202 struct sk_buff *new, 203 const struct sk_buff *skb, u32 offset, 204 const struct rtw89_pci_rx_info *rx_info, 205 const struct rtw89_rx_desc_info *desc_info) 206 { 207 u32 copy_len = rx_info->len - offset; 208 209 if (unlikely(skb_tailroom(new) < copy_len)) { 210 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 211 "invalid rx data length bd_len=%d desc_len=%d offset=%d (fs=%d ls=%d)\n", 212 rx_info->len, desc_info->pkt_size, offset, fs, ls); 213 rtw89_hex_dump(rtwdev, RTW89_DBG_TXRX, "rx_data: ", 214 skb->data, rx_info->len); 215 /* length of a single segment skb is desc_info->pkt_size */ 216 if (fs && ls) { 217 copy_len = desc_info->pkt_size; 218 } else { 219 rtw89_info(rtwdev, "drop rx data due to invalid length\n"); 220 return false; 221 } 222 } 223 224 skb_put_data(new, skb->data + offset, copy_len); 225 226 return true; 227 } 228 229 static u32 rtw89_pci_rxbd_deliver_skbs(struct rtw89_dev *rtwdev, 230 struct rtw89_pci_rx_ring *rx_ring) 231 { 232 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 233 struct rtw89_pci_rx_info *rx_info; 234 struct rtw89_rx_desc_info *desc_info = &rx_ring->diliver_desc; 235 struct sk_buff *new = rx_ring->diliver_skb; 236 struct sk_buff *skb; 237 u32 rxinfo_size = sizeof(struct rtw89_pci_rxbd_info); 238 u32 offset; 239 u32 cnt = 1; 240 bool fs, ls; 241 int ret; 242 243 skb = rx_ring->buf[bd_ring->wp]; 244 rtw89_pci_sync_skb_for_cpu(rtwdev, skb); 245 246 ret = rtw89_pci_rxbd_info_update(rtwdev, skb); 247 if (ret) { 248 rtw89_err(rtwdev, "failed to update %d RXBD info: %d\n", 249 bd_ring->wp, ret); 250 goto err_sync_device; 251 } 252 253 rx_info = RTW89_PCI_RX_SKB_CB(skb); 254 fs = rx_info->fs; 255 ls = rx_info->ls; 256 257 if (fs) { 258 if (new) { 259 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 260 "skb should not be ready before first segment start\n"); 261 goto err_sync_device; 262 } 263 if (desc_info->ready) { 264 rtw89_warn(rtwdev, "desc info should not be ready before first segment start\n"); 265 goto err_sync_device; 266 } 267 268 rtw89_core_query_rxdesc(rtwdev, desc_info, skb->data, rxinfo_size); 269 270 new = rtw89_alloc_skb_for_rx(rtwdev, desc_info->pkt_size); 271 if (!new) 272 goto err_sync_device; 273 274 rx_ring->diliver_skb = new; 275 276 /* first segment has RX desc */ 277 offset = desc_info->offset; 278 offset += desc_info->long_rxdesc ? sizeof(struct rtw89_rxdesc_long) : 279 sizeof(struct rtw89_rxdesc_short); 280 } else { 281 offset = sizeof(struct rtw89_pci_rxbd_info); 282 if (!new) { 283 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "no last skb\n"); 284 goto err_sync_device; 285 } 286 } 287 if (!rtw89_skb_put_rx_data(rtwdev, fs, ls, new, skb, offset, rx_info, desc_info)) 288 goto err_sync_device; 289 rtw89_pci_sync_skb_for_device(rtwdev, skb); 290 rtw89_pci_rxbd_increase(rx_ring, 1); 291 292 if (!desc_info->ready) { 293 rtw89_warn(rtwdev, "no rx desc information\n"); 294 goto err_free_resource; 295 } 296 if (ls) { 297 rtw89_core_rx(rtwdev, desc_info, new); 298 rx_ring->diliver_skb = NULL; 299 desc_info->ready = false; 300 } 301 302 return cnt; 303 304 err_sync_device: 305 rtw89_pci_sync_skb_for_device(rtwdev, skb); 306 rtw89_pci_rxbd_increase(rx_ring, 1); 307 err_free_resource: 308 if (new) 309 dev_kfree_skb_any(new); 310 rx_ring->diliver_skb = NULL; 311 desc_info->ready = false; 312 313 return cnt; 314 } 315 316 static void rtw89_pci_rxbd_deliver(struct rtw89_dev *rtwdev, 317 struct rtw89_pci_rx_ring *rx_ring, 318 u32 cnt) 319 { 320 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 321 u32 rx_cnt; 322 323 while (cnt && rtwdev->napi_budget_countdown > 0) { 324 rx_cnt = rtw89_pci_rxbd_deliver_skbs(rtwdev, rx_ring); 325 if (!rx_cnt) { 326 rtw89_err(rtwdev, "failed to deliver RXBD skb\n"); 327 328 /* skip the rest RXBD bufs */ 329 rtw89_pci_rxbd_increase(rx_ring, cnt); 330 break; 331 } 332 333 cnt -= rx_cnt; 334 } 335 336 rtw89_write16(rtwdev, bd_ring->addr.idx, bd_ring->wp); 337 } 338 339 static int rtw89_pci_poll_rxq_dma(struct rtw89_dev *rtwdev, 340 struct rtw89_pci *rtwpci, int budget) 341 { 342 struct rtw89_pci_rx_ring *rx_ring; 343 int countdown = rtwdev->napi_budget_countdown; 344 u32 cnt; 345 346 rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RXQ]; 347 348 cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring); 349 if (!cnt) 350 return 0; 351 352 cnt = min_t(u32, budget, cnt); 353 354 rtw89_pci_rxbd_deliver(rtwdev, rx_ring, cnt); 355 356 /* In case of flushing pending SKBs, the countdown may exceed. */ 357 if (rtwdev->napi_budget_countdown <= 0) 358 return budget; 359 360 return budget - countdown; 361 } 362 363 static void rtw89_pci_tx_status(struct rtw89_dev *rtwdev, 364 struct rtw89_pci_tx_ring *tx_ring, 365 struct sk_buff *skb, u8 tx_status) 366 { 367 struct ieee80211_tx_info *info; 368 369 info = IEEE80211_SKB_CB(skb); 370 ieee80211_tx_info_clear_status(info); 371 372 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 373 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 374 if (tx_status == RTW89_TX_DONE) { 375 info->flags |= IEEE80211_TX_STAT_ACK; 376 tx_ring->tx_acked++; 377 } else { 378 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) 379 rtw89_debug(rtwdev, RTW89_DBG_FW, 380 "failed to TX of status %x\n", tx_status); 381 switch (tx_status) { 382 case RTW89_TX_RETRY_LIMIT: 383 tx_ring->tx_retry_lmt++; 384 break; 385 case RTW89_TX_LIFE_TIME: 386 tx_ring->tx_life_time++; 387 break; 388 case RTW89_TX_MACID_DROP: 389 tx_ring->tx_mac_id_drop++; 390 break; 391 default: 392 rtw89_warn(rtwdev, "invalid TX status %x\n", tx_status); 393 break; 394 } 395 } 396 397 ieee80211_tx_status_ni(rtwdev->hw, skb); 398 } 399 400 static void rtw89_pci_reclaim_txbd(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring) 401 { 402 struct rtw89_pci_tx_wd *txwd; 403 u32 cnt; 404 405 cnt = rtw89_pci_txbd_recalc(rtwdev, tx_ring); 406 while (cnt--) { 407 txwd = list_first_entry_or_null(&tx_ring->busy_pages, struct rtw89_pci_tx_wd, list); 408 if (!txwd) { 409 rtw89_warn(rtwdev, "No busy txwd pages available\n"); 410 break; 411 } 412 413 list_del_init(&txwd->list); 414 415 /* this skb has been freed by RPP */ 416 if (skb_queue_len(&txwd->queue) == 0) 417 rtw89_pci_enqueue_txwd(tx_ring, txwd); 418 } 419 } 420 421 static void rtw89_pci_release_busy_txwd(struct rtw89_dev *rtwdev, 422 struct rtw89_pci_tx_ring *tx_ring) 423 { 424 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 425 struct rtw89_pci_tx_wd *txwd; 426 int i; 427 428 for (i = 0; i < wd_ring->page_num; i++) { 429 txwd = list_first_entry_or_null(&tx_ring->busy_pages, struct rtw89_pci_tx_wd, list); 430 if (!txwd) 431 break; 432 433 list_del_init(&txwd->list); 434 } 435 } 436 437 static void rtw89_pci_release_txwd_skb(struct rtw89_dev *rtwdev, 438 struct rtw89_pci_tx_ring *tx_ring, 439 struct rtw89_pci_tx_wd *txwd, u16 seq, 440 u8 tx_status) 441 { 442 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 443 struct rtw89_pci_tx_data *tx_data; 444 struct sk_buff *skb, *tmp; 445 u8 txch = tx_ring->txch; 446 447 if (!list_empty(&txwd->list)) { 448 rtw89_pci_reclaim_txbd(rtwdev, tx_ring); 449 /* In low power mode, RPP can receive before updating of TX BD. 450 * In normal mode, it should not happen so give it a warning. 451 */ 452 if (!rtwpci->low_power && !list_empty(&txwd->list)) 453 rtw89_warn(rtwdev, "queue %d txwd %d is not idle\n", 454 txch, seq); 455 } 456 457 skb_queue_walk_safe(&txwd->queue, skb, tmp) { 458 skb_unlink(skb, &txwd->queue); 459 460 tx_data = RTW89_PCI_TX_SKB_CB(skb); 461 dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len, 462 DMA_TO_DEVICE); 463 464 rtw89_pci_tx_status(rtwdev, tx_ring, skb, tx_status); 465 } 466 467 if (list_empty(&txwd->list)) 468 rtw89_pci_enqueue_txwd(tx_ring, txwd); 469 } 470 471 static void rtw89_pci_release_rpp(struct rtw89_dev *rtwdev, 472 struct rtw89_pci_rpp_fmt *rpp) 473 { 474 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 475 struct rtw89_pci_tx_ring *tx_ring; 476 struct rtw89_pci_tx_wd_ring *wd_ring; 477 struct rtw89_pci_tx_wd *txwd; 478 u16 seq; 479 u8 qsel, tx_status, txch; 480 481 seq = le32_get_bits(rpp->dword, RTW89_PCI_RPP_SEQ); 482 qsel = le32_get_bits(rpp->dword, RTW89_PCI_RPP_QSEL); 483 tx_status = le32_get_bits(rpp->dword, RTW89_PCI_RPP_TX_STATUS); 484 txch = rtw89_core_get_ch_dma(rtwdev, qsel); 485 486 if (txch == RTW89_TXCH_CH12) { 487 rtw89_warn(rtwdev, "should no fwcmd release report\n"); 488 return; 489 } 490 491 tx_ring = &rtwpci->tx_rings[txch]; 492 wd_ring = &tx_ring->wd_ring; 493 txwd = &wd_ring->pages[seq]; 494 495 rtw89_pci_release_txwd_skb(rtwdev, tx_ring, txwd, seq, tx_status); 496 } 497 498 static void rtw89_pci_release_pending_txwd_skb(struct rtw89_dev *rtwdev, 499 struct rtw89_pci_tx_ring *tx_ring) 500 { 501 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 502 struct rtw89_pci_tx_wd *txwd; 503 int i; 504 505 for (i = 0; i < wd_ring->page_num; i++) { 506 txwd = &wd_ring->pages[i]; 507 508 if (!list_empty(&txwd->list)) 509 continue; 510 511 rtw89_pci_release_txwd_skb(rtwdev, tx_ring, txwd, i, RTW89_TX_MACID_DROP); 512 } 513 } 514 515 static u32 rtw89_pci_release_tx_skbs(struct rtw89_dev *rtwdev, 516 struct rtw89_pci_rx_ring *rx_ring, 517 u32 max_cnt) 518 { 519 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 520 struct rtw89_pci_rx_info *rx_info; 521 struct rtw89_pci_rpp_fmt *rpp; 522 struct rtw89_rx_desc_info desc_info = {}; 523 struct sk_buff *skb; 524 u32 cnt = 0; 525 u32 rpp_size = sizeof(struct rtw89_pci_rpp_fmt); 526 u32 rxinfo_size = sizeof(struct rtw89_pci_rxbd_info); 527 u32 offset; 528 int ret; 529 530 skb = rx_ring->buf[bd_ring->wp]; 531 rtw89_pci_sync_skb_for_cpu(rtwdev, skb); 532 533 ret = rtw89_pci_rxbd_info_update(rtwdev, skb); 534 if (ret) { 535 rtw89_err(rtwdev, "failed to update %d RXBD info: %d\n", 536 bd_ring->wp, ret); 537 goto err_sync_device; 538 } 539 540 rx_info = RTW89_PCI_RX_SKB_CB(skb); 541 if (!rx_info->fs || !rx_info->ls) { 542 rtw89_err(rtwdev, "cannot process RP frame not set FS/LS\n"); 543 return cnt; 544 } 545 546 rtw89_core_query_rxdesc(rtwdev, &desc_info, skb->data, rxinfo_size); 547 548 /* first segment has RX desc */ 549 offset = desc_info.offset; 550 offset += desc_info.long_rxdesc ? sizeof(struct rtw89_rxdesc_long) : 551 sizeof(struct rtw89_rxdesc_short); 552 for (; offset + rpp_size <= rx_info->len; offset += rpp_size) { 553 rpp = (struct rtw89_pci_rpp_fmt *)(skb->data + offset); 554 rtw89_pci_release_rpp(rtwdev, rpp); 555 } 556 557 rtw89_pci_sync_skb_for_device(rtwdev, skb); 558 rtw89_pci_rxbd_increase(rx_ring, 1); 559 cnt++; 560 561 return cnt; 562 563 err_sync_device: 564 rtw89_pci_sync_skb_for_device(rtwdev, skb); 565 return 0; 566 } 567 568 static void rtw89_pci_release_tx(struct rtw89_dev *rtwdev, 569 struct rtw89_pci_rx_ring *rx_ring, 570 u32 cnt) 571 { 572 struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring; 573 u32 release_cnt; 574 575 while (cnt) { 576 release_cnt = rtw89_pci_release_tx_skbs(rtwdev, rx_ring, cnt); 577 if (!release_cnt) { 578 rtw89_err(rtwdev, "failed to release TX skbs\n"); 579 580 /* skip the rest RXBD bufs */ 581 rtw89_pci_rxbd_increase(rx_ring, cnt); 582 break; 583 } 584 585 cnt -= release_cnt; 586 } 587 588 rtw89_write16(rtwdev, bd_ring->addr.idx, bd_ring->wp); 589 } 590 591 static int rtw89_pci_poll_rpq_dma(struct rtw89_dev *rtwdev, 592 struct rtw89_pci *rtwpci, int budget) 593 { 594 struct rtw89_pci_rx_ring *rx_ring; 595 u32 cnt; 596 int work_done; 597 598 rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ]; 599 600 spin_lock_bh(&rtwpci->trx_lock); 601 602 cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring); 603 if (cnt == 0) 604 goto out_unlock; 605 606 rtw89_pci_release_tx(rtwdev, rx_ring, cnt); 607 608 out_unlock: 609 spin_unlock_bh(&rtwpci->trx_lock); 610 611 /* always release all RPQ */ 612 work_done = min_t(int, cnt, budget); 613 rtwdev->napi_budget_countdown -= work_done; 614 615 return work_done; 616 } 617 618 static void rtw89_pci_isr_rxd_unavail(struct rtw89_dev *rtwdev, 619 struct rtw89_pci *rtwpci) 620 { 621 struct rtw89_pci_rx_ring *rx_ring; 622 struct rtw89_pci_dma_ring *bd_ring; 623 u32 reg_idx; 624 u16 hw_idx, hw_idx_next, host_idx; 625 int i; 626 627 for (i = 0; i < RTW89_RXCH_NUM; i++) { 628 rx_ring = &rtwpci->rx_rings[i]; 629 bd_ring = &rx_ring->bd_ring; 630 631 reg_idx = rtw89_read32(rtwdev, bd_ring->addr.idx); 632 hw_idx = FIELD_GET(TXBD_HW_IDX_MASK, reg_idx); 633 host_idx = FIELD_GET(TXBD_HOST_IDX_MASK, reg_idx); 634 hw_idx_next = (hw_idx + 1) % bd_ring->len; 635 636 if (hw_idx_next == host_idx) 637 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "%d RXD unavailable\n", i); 638 639 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 640 "%d RXD unavailable, idx=0x%08x, len=%d\n", 641 i, reg_idx, bd_ring->len); 642 } 643 } 644 645 void rtw89_pci_recognize_intrs(struct rtw89_dev *rtwdev, 646 struct rtw89_pci *rtwpci, 647 struct rtw89_pci_isrs *isrs) 648 { 649 isrs->halt_c2h_isrs = rtw89_read32(rtwdev, R_AX_HISR0) & rtwpci->halt_c2h_intrs; 650 isrs->isrs[0] = rtw89_read32(rtwdev, R_AX_PCIE_HISR00) & rtwpci->intrs[0]; 651 isrs->isrs[1] = rtw89_read32(rtwdev, R_AX_PCIE_HISR10) & rtwpci->intrs[1]; 652 653 rtw89_write32(rtwdev, R_AX_HISR0, isrs->halt_c2h_isrs); 654 rtw89_write32(rtwdev, R_AX_PCIE_HISR00, isrs->isrs[0]); 655 rtw89_write32(rtwdev, R_AX_PCIE_HISR10, isrs->isrs[1]); 656 } 657 EXPORT_SYMBOL(rtw89_pci_recognize_intrs); 658 659 void rtw89_pci_recognize_intrs_v1(struct rtw89_dev *rtwdev, 660 struct rtw89_pci *rtwpci, 661 struct rtw89_pci_isrs *isrs) 662 { 663 isrs->ind_isrs = rtw89_read32(rtwdev, R_AX_PCIE_HISR00_V1) & rtwpci->ind_intrs; 664 isrs->halt_c2h_isrs = isrs->ind_isrs & B_AX_HS0ISR_IND_INT_EN ? 665 rtw89_read32(rtwdev, R_AX_HISR0) & rtwpci->halt_c2h_intrs : 0; 666 isrs->isrs[0] = isrs->ind_isrs & B_AX_HCI_AXIDMA_INT_EN ? 667 rtw89_read32(rtwdev, R_AX_HAXI_HISR00) & rtwpci->intrs[0] : 0; 668 isrs->isrs[1] = isrs->ind_isrs & B_AX_HS1ISR_IND_INT_EN ? 669 rtw89_read32(rtwdev, R_AX_HISR1) & rtwpci->intrs[1] : 0; 670 671 if (isrs->halt_c2h_isrs) 672 rtw89_write32(rtwdev, R_AX_HISR0, isrs->halt_c2h_isrs); 673 if (isrs->isrs[0]) 674 rtw89_write32(rtwdev, R_AX_HAXI_HISR00, isrs->isrs[0]); 675 if (isrs->isrs[1]) 676 rtw89_write32(rtwdev, R_AX_HISR1, isrs->isrs[1]); 677 } 678 EXPORT_SYMBOL(rtw89_pci_recognize_intrs_v1); 679 680 static void rtw89_pci_clear_isr0(struct rtw89_dev *rtwdev, u32 isr00) 681 { 682 /* write 1 clear */ 683 rtw89_write32(rtwdev, R_AX_PCIE_HISR00, isr00); 684 } 685 686 void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) 687 { 688 rtw89_write32(rtwdev, R_AX_HIMR0, rtwpci->halt_c2h_intrs); 689 rtw89_write32(rtwdev, R_AX_PCIE_HIMR00, rtwpci->intrs[0]); 690 rtw89_write32(rtwdev, R_AX_PCIE_HIMR10, rtwpci->intrs[1]); 691 } 692 EXPORT_SYMBOL(rtw89_pci_enable_intr); 693 694 void rtw89_pci_disable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) 695 { 696 rtw89_write32(rtwdev, R_AX_HIMR0, 0); 697 rtw89_write32(rtwdev, R_AX_PCIE_HIMR00, 0); 698 rtw89_write32(rtwdev, R_AX_PCIE_HIMR10, 0); 699 } 700 EXPORT_SYMBOL(rtw89_pci_disable_intr); 701 702 void rtw89_pci_enable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) 703 { 704 rtw89_write32(rtwdev, R_AX_PCIE_HIMR00_V1, rtwpci->ind_intrs); 705 rtw89_write32(rtwdev, R_AX_HIMR0, rtwpci->halt_c2h_intrs); 706 rtw89_write32(rtwdev, R_AX_HAXI_HIMR00, rtwpci->intrs[0]); 707 rtw89_write32(rtwdev, R_AX_HIMR1, rtwpci->intrs[1]); 708 } 709 EXPORT_SYMBOL(rtw89_pci_enable_intr_v1); 710 711 void rtw89_pci_disable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) 712 { 713 rtw89_write32(rtwdev, R_AX_PCIE_HIMR00_V1, 0); 714 } 715 EXPORT_SYMBOL(rtw89_pci_disable_intr_v1); 716 717 static void rtw89_pci_ops_recovery_start(struct rtw89_dev *rtwdev) 718 { 719 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 720 unsigned long flags; 721 722 spin_lock_irqsave(&rtwpci->irq_lock, flags); 723 rtw89_chip_disable_intr(rtwdev, rtwpci); 724 rtw89_chip_config_intr_mask(rtwdev, RTW89_PCI_INTR_MASK_RECOVERY_START); 725 rtw89_chip_enable_intr(rtwdev, rtwpci); 726 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 727 } 728 729 static void rtw89_pci_ops_recovery_complete(struct rtw89_dev *rtwdev) 730 { 731 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 732 unsigned long flags; 733 734 spin_lock_irqsave(&rtwpci->irq_lock, flags); 735 rtw89_chip_disable_intr(rtwdev, rtwpci); 736 rtw89_chip_config_intr_mask(rtwdev, RTW89_PCI_INTR_MASK_RECOVERY_COMPLETE); 737 rtw89_chip_enable_intr(rtwdev, rtwpci); 738 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 739 } 740 741 static void rtw89_pci_low_power_interrupt_handler(struct rtw89_dev *rtwdev) 742 { 743 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 744 int budget = NAPI_POLL_WEIGHT; 745 746 /* To prevent RXQ get stuck due to run out of budget. */ 747 rtwdev->napi_budget_countdown = budget; 748 749 rtw89_pci_poll_rpq_dma(rtwdev, rtwpci, budget); 750 rtw89_pci_poll_rxq_dma(rtwdev, rtwpci, budget); 751 } 752 753 static irqreturn_t rtw89_pci_interrupt_threadfn(int irq, void *dev) 754 { 755 struct rtw89_dev *rtwdev = dev; 756 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 757 struct rtw89_pci_isrs isrs; 758 unsigned long flags; 759 760 spin_lock_irqsave(&rtwpci->irq_lock, flags); 761 rtw89_chip_recognize_intrs(rtwdev, rtwpci, &isrs); 762 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 763 764 if (unlikely(isrs.isrs[0] & B_AX_RDU_INT)) 765 rtw89_pci_isr_rxd_unavail(rtwdev, rtwpci); 766 767 if (unlikely(isrs.halt_c2h_isrs & B_AX_HALT_C2H_INT_EN)) 768 rtw89_ser_notify(rtwdev, rtw89_mac_get_err_status(rtwdev)); 769 770 if (unlikely(isrs.halt_c2h_isrs & B_AX_WDT_TIMEOUT_INT_EN)) 771 rtw89_ser_notify(rtwdev, MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT); 772 773 if (unlikely(rtwpci->under_recovery)) 774 goto enable_intr; 775 776 if (unlikely(rtwpci->low_power)) { 777 rtw89_pci_low_power_interrupt_handler(rtwdev); 778 goto enable_intr; 779 } 780 781 if (likely(rtwpci->running)) { 782 local_bh_disable(); 783 napi_schedule(&rtwdev->napi); 784 local_bh_enable(); 785 } 786 787 return IRQ_HANDLED; 788 789 enable_intr: 790 spin_lock_irqsave(&rtwpci->irq_lock, flags); 791 if (likely(rtwpci->running)) 792 rtw89_chip_enable_intr(rtwdev, rtwpci); 793 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 794 return IRQ_HANDLED; 795 } 796 797 static irqreturn_t rtw89_pci_interrupt_handler(int irq, void *dev) 798 { 799 struct rtw89_dev *rtwdev = dev; 800 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 801 unsigned long flags; 802 irqreturn_t irqret = IRQ_WAKE_THREAD; 803 804 spin_lock_irqsave(&rtwpci->irq_lock, flags); 805 806 /* If interrupt event is on the road, it is still trigger interrupt 807 * even we have done pci_stop() to turn off IMR. 808 */ 809 if (unlikely(!rtwpci->running)) { 810 irqret = IRQ_HANDLED; 811 goto exit; 812 } 813 814 rtw89_chip_disable_intr(rtwdev, rtwpci); 815 exit: 816 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 817 818 return irqret; 819 } 820 821 #define DEF_TXCHADDRS_TYPE1(info, txch, v...) \ 822 [RTW89_TXCH_##txch] = { \ 823 .num = R_AX_##txch##_TXBD_NUM ##v, \ 824 .idx = R_AX_##txch##_TXBD_IDX ##v, \ 825 .bdram = R_AX_##txch##_BDRAM_CTRL ##v, \ 826 .desa_l = R_AX_##txch##_TXBD_DESA_L ##v, \ 827 .desa_h = R_AX_##txch##_TXBD_DESA_H ##v, \ 828 } 829 830 #define DEF_TXCHADDRS(info, txch, v...) \ 831 [RTW89_TXCH_##txch] = { \ 832 .num = R_AX_##txch##_TXBD_NUM, \ 833 .idx = R_AX_##txch##_TXBD_IDX, \ 834 .bdram = R_AX_##txch##_BDRAM_CTRL ##v, \ 835 .desa_l = R_AX_##txch##_TXBD_DESA_L ##v, \ 836 .desa_h = R_AX_##txch##_TXBD_DESA_H ##v, \ 837 } 838 839 #define DEF_RXCHADDRS(info, rxch, v...) \ 840 [RTW89_RXCH_##rxch] = { \ 841 .num = R_AX_##rxch##_RXBD_NUM ##v, \ 842 .idx = R_AX_##rxch##_RXBD_IDX ##v, \ 843 .desa_l = R_AX_##rxch##_RXBD_DESA_L ##v, \ 844 .desa_h = R_AX_##rxch##_RXBD_DESA_H ##v, \ 845 } 846 847 const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set = { 848 .tx = { 849 DEF_TXCHADDRS(info, ACH0), 850 DEF_TXCHADDRS(info, ACH1), 851 DEF_TXCHADDRS(info, ACH2), 852 DEF_TXCHADDRS(info, ACH3), 853 DEF_TXCHADDRS(info, ACH4), 854 DEF_TXCHADDRS(info, ACH5), 855 DEF_TXCHADDRS(info, ACH6), 856 DEF_TXCHADDRS(info, ACH7), 857 DEF_TXCHADDRS(info, CH8), 858 DEF_TXCHADDRS(info, CH9), 859 DEF_TXCHADDRS_TYPE1(info, CH10), 860 DEF_TXCHADDRS_TYPE1(info, CH11), 861 DEF_TXCHADDRS(info, CH12), 862 }, 863 .rx = { 864 DEF_RXCHADDRS(info, RXQ), 865 DEF_RXCHADDRS(info, RPQ), 866 }, 867 }; 868 EXPORT_SYMBOL(rtw89_pci_ch_dma_addr_set); 869 870 const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set_v1 = { 871 .tx = { 872 DEF_TXCHADDRS(info, ACH0, _V1), 873 DEF_TXCHADDRS(info, ACH1, _V1), 874 DEF_TXCHADDRS(info, ACH2, _V1), 875 DEF_TXCHADDRS(info, ACH3, _V1), 876 DEF_TXCHADDRS(info, ACH4, _V1), 877 DEF_TXCHADDRS(info, ACH5, _V1), 878 DEF_TXCHADDRS(info, ACH6, _V1), 879 DEF_TXCHADDRS(info, ACH7, _V1), 880 DEF_TXCHADDRS(info, CH8, _V1), 881 DEF_TXCHADDRS(info, CH9, _V1), 882 DEF_TXCHADDRS_TYPE1(info, CH10, _V1), 883 DEF_TXCHADDRS_TYPE1(info, CH11, _V1), 884 DEF_TXCHADDRS(info, CH12, _V1), 885 }, 886 .rx = { 887 DEF_RXCHADDRS(info, RXQ, _V1), 888 DEF_RXCHADDRS(info, RPQ, _V1), 889 }, 890 }; 891 EXPORT_SYMBOL(rtw89_pci_ch_dma_addr_set_v1); 892 893 #undef DEF_TXCHADDRS_TYPE1 894 #undef DEF_TXCHADDRS 895 #undef DEF_RXCHADDRS 896 897 static int rtw89_pci_get_txch_addrs(struct rtw89_dev *rtwdev, 898 enum rtw89_tx_channel txch, 899 const struct rtw89_pci_ch_dma_addr **addr) 900 { 901 const struct rtw89_pci_info *info = rtwdev->pci_info; 902 903 if (txch >= RTW89_TXCH_NUM) 904 return -EINVAL; 905 906 *addr = &info->dma_addr_set->tx[txch]; 907 908 return 0; 909 } 910 911 static int rtw89_pci_get_rxch_addrs(struct rtw89_dev *rtwdev, 912 enum rtw89_rx_channel rxch, 913 const struct rtw89_pci_ch_dma_addr **addr) 914 { 915 const struct rtw89_pci_info *info = rtwdev->pci_info; 916 917 if (rxch >= RTW89_RXCH_NUM) 918 return -EINVAL; 919 920 *addr = &info->dma_addr_set->rx[rxch]; 921 922 return 0; 923 } 924 925 static u32 rtw89_pci_get_avail_txbd_num(struct rtw89_pci_tx_ring *ring) 926 { 927 struct rtw89_pci_dma_ring *bd_ring = &ring->bd_ring; 928 929 /* reserved 1 desc check ring is full or not */ 930 if (bd_ring->rp > bd_ring->wp) 931 return bd_ring->rp - bd_ring->wp - 1; 932 933 return bd_ring->len - (bd_ring->wp - bd_ring->rp) - 1; 934 } 935 936 static 937 u32 __rtw89_pci_check_and_reclaim_tx_fwcmd_resource(struct rtw89_dev *rtwdev) 938 { 939 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 940 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[RTW89_TXCH_CH12]; 941 u32 cnt; 942 943 spin_lock_bh(&rtwpci->trx_lock); 944 rtw89_pci_reclaim_tx_fwcmd(rtwdev, rtwpci); 945 cnt = rtw89_pci_get_avail_txbd_num(tx_ring); 946 spin_unlock_bh(&rtwpci->trx_lock); 947 948 return cnt; 949 } 950 951 static 952 u32 __rtw89_pci_check_and_reclaim_tx_resource_noio(struct rtw89_dev *rtwdev, 953 u8 txch) 954 { 955 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 956 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; 957 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 958 u32 cnt; 959 960 spin_lock_bh(&rtwpci->trx_lock); 961 cnt = rtw89_pci_get_avail_txbd_num(tx_ring); 962 cnt = min(cnt, wd_ring->curr_num); 963 spin_unlock_bh(&rtwpci->trx_lock); 964 965 return cnt; 966 } 967 968 static u32 __rtw89_pci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, 969 u8 txch) 970 { 971 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 972 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; 973 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 974 const struct rtw89_chip_info *chip = rtwdev->chip; 975 u32 bd_cnt, wd_cnt, min_cnt = 0; 976 struct rtw89_pci_rx_ring *rx_ring; 977 enum rtw89_debug_mask debug_mask; 978 u32 cnt; 979 980 rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ]; 981 982 spin_lock_bh(&rtwpci->trx_lock); 983 bd_cnt = rtw89_pci_get_avail_txbd_num(tx_ring); 984 wd_cnt = wd_ring->curr_num; 985 986 if (wd_cnt == 0 || bd_cnt == 0) { 987 cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring); 988 if (cnt) 989 rtw89_pci_release_tx(rtwdev, rx_ring, cnt); 990 else if (wd_cnt == 0) 991 goto out_unlock; 992 993 bd_cnt = rtw89_pci_get_avail_txbd_num(tx_ring); 994 if (bd_cnt == 0) 995 rtw89_pci_reclaim_txbd(rtwdev, tx_ring); 996 } 997 998 bd_cnt = rtw89_pci_get_avail_txbd_num(tx_ring); 999 wd_cnt = wd_ring->curr_num; 1000 min_cnt = min(bd_cnt, wd_cnt); 1001 if (min_cnt == 0) { 1002 /* This message can be frequently shown in low power mode or 1003 * high traffic with 8852B, and we have recognized it as normal 1004 * behavior, so print with mask RTW89_DBG_TXRX in these situations. 1005 */ 1006 if (rtwpci->low_power || chip->chip_id == RTL8852B) 1007 debug_mask = RTW89_DBG_TXRX; 1008 else 1009 debug_mask = RTW89_DBG_UNEXP; 1010 1011 rtw89_debug(rtwdev, debug_mask, 1012 "still no tx resource after reclaim: wd_cnt=%d bd_cnt=%d\n", 1013 wd_cnt, bd_cnt); 1014 } 1015 1016 out_unlock: 1017 spin_unlock_bh(&rtwpci->trx_lock); 1018 1019 return min_cnt; 1020 } 1021 1022 static u32 rtw89_pci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, 1023 u8 txch) 1024 { 1025 if (rtwdev->hci.paused) 1026 return __rtw89_pci_check_and_reclaim_tx_resource_noio(rtwdev, txch); 1027 1028 if (txch == RTW89_TXCH_CH12) 1029 return __rtw89_pci_check_and_reclaim_tx_fwcmd_resource(rtwdev); 1030 1031 return __rtw89_pci_check_and_reclaim_tx_resource(rtwdev, txch); 1032 } 1033 1034 static void __rtw89_pci_tx_kick_off(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring) 1035 { 1036 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1037 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; 1038 u32 host_idx, addr; 1039 1040 spin_lock_bh(&rtwpci->trx_lock); 1041 1042 addr = bd_ring->addr.idx; 1043 host_idx = bd_ring->wp; 1044 rtw89_write16(rtwdev, addr, host_idx); 1045 1046 spin_unlock_bh(&rtwpci->trx_lock); 1047 } 1048 1049 static void rtw89_pci_tx_bd_ring_update(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring, 1050 int n_txbd) 1051 { 1052 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; 1053 u32 host_idx, len; 1054 1055 len = bd_ring->len; 1056 host_idx = bd_ring->wp + n_txbd; 1057 host_idx = host_idx < len ? host_idx : host_idx - len; 1058 1059 bd_ring->wp = host_idx; 1060 } 1061 1062 static void rtw89_pci_ops_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 1063 { 1064 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1065 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; 1066 1067 if (rtwdev->hci.paused) { 1068 set_bit(txch, rtwpci->kick_map); 1069 return; 1070 } 1071 1072 __rtw89_pci_tx_kick_off(rtwdev, tx_ring); 1073 } 1074 1075 static void rtw89_pci_tx_kick_off_pending(struct rtw89_dev *rtwdev) 1076 { 1077 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1078 struct rtw89_pci_tx_ring *tx_ring; 1079 int txch; 1080 1081 for (txch = 0; txch < RTW89_TXCH_NUM; txch++) { 1082 if (!test_and_clear_bit(txch, rtwpci->kick_map)) 1083 continue; 1084 1085 tx_ring = &rtwpci->tx_rings[txch]; 1086 __rtw89_pci_tx_kick_off(rtwdev, tx_ring); 1087 } 1088 } 1089 1090 static void __pci_flush_txch(struct rtw89_dev *rtwdev, u8 txch, bool drop) 1091 { 1092 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1093 struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[txch]; 1094 struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring; 1095 u32 cur_idx, cur_rp; 1096 u8 i; 1097 1098 /* Because the time taked by the I/O is a bit dynamic, it's hard to 1099 * define a reasonable fixed total timeout to use read_poll_timeout* 1100 * helper. Instead, we can ensure a reasonable polling times, so we 1101 * just use for loop with udelay here. 1102 */ 1103 for (i = 0; i < 60; i++) { 1104 cur_idx = rtw89_read32(rtwdev, bd_ring->addr.idx); 1105 cur_rp = FIELD_GET(TXBD_HW_IDX_MASK, cur_idx); 1106 if (cur_rp == bd_ring->wp) 1107 return; 1108 1109 udelay(1); 1110 } 1111 1112 if (!drop) 1113 rtw89_info(rtwdev, "timed out to flush pci txch: %d\n", txch); 1114 } 1115 1116 static void __rtw89_pci_ops_flush_txchs(struct rtw89_dev *rtwdev, u32 txchs, 1117 bool drop) 1118 { 1119 const struct rtw89_pci_info *info = rtwdev->pci_info; 1120 u8 i; 1121 1122 for (i = 0; i < RTW89_TXCH_NUM; i++) { 1123 /* It may be unnecessary to flush FWCMD queue. */ 1124 if (i == RTW89_TXCH_CH12) 1125 continue; 1126 if (info->tx_dma_ch_mask & BIT(i)) 1127 continue; 1128 1129 if (txchs & BIT(i)) 1130 __pci_flush_txch(rtwdev, i, drop); 1131 } 1132 } 1133 1134 static void rtw89_pci_ops_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 1135 bool drop) 1136 { 1137 __rtw89_pci_ops_flush_txchs(rtwdev, BIT(RTW89_TXCH_NUM) - 1, drop); 1138 } 1139 1140 u32 rtw89_pci_fill_txaddr_info(struct rtw89_dev *rtwdev, 1141 void *txaddr_info_addr, u32 total_len, 1142 dma_addr_t dma, u8 *add_info_nr) 1143 { 1144 struct rtw89_pci_tx_addr_info_32 *txaddr_info = txaddr_info_addr; 1145 1146 txaddr_info->length = cpu_to_le16(total_len); 1147 txaddr_info->option = cpu_to_le16(RTW89_PCI_ADDR_MSDU_LS | 1148 RTW89_PCI_ADDR_NUM(1)); 1149 txaddr_info->dma = cpu_to_le32(dma); 1150 1151 *add_info_nr = 1; 1152 1153 return sizeof(*txaddr_info); 1154 } 1155 EXPORT_SYMBOL(rtw89_pci_fill_txaddr_info); 1156 1157 u32 rtw89_pci_fill_txaddr_info_v1(struct rtw89_dev *rtwdev, 1158 void *txaddr_info_addr, u32 total_len, 1159 dma_addr_t dma, u8 *add_info_nr) 1160 { 1161 struct rtw89_pci_tx_addr_info_32_v1 *txaddr_info = txaddr_info_addr; 1162 u32 remain = total_len; 1163 u32 len; 1164 u16 length_option; 1165 int n; 1166 1167 for (n = 0; n < RTW89_TXADDR_INFO_NR_V1 && remain; n++) { 1168 len = remain >= TXADDR_INFO_LENTHG_V1_MAX ? 1169 TXADDR_INFO_LENTHG_V1_MAX : remain; 1170 remain -= len; 1171 1172 length_option = FIELD_PREP(B_PCIADDR_LEN_V1_MASK, len) | 1173 FIELD_PREP(B_PCIADDR_HIGH_SEL_V1_MASK, 0) | 1174 FIELD_PREP(B_PCIADDR_LS_V1_MASK, remain == 0); 1175 txaddr_info->length_opt = cpu_to_le16(length_option); 1176 txaddr_info->dma_low_lsb = cpu_to_le16(FIELD_GET(GENMASK(15, 0), dma)); 1177 txaddr_info->dma_low_msb = cpu_to_le16(FIELD_GET(GENMASK(31, 16), dma)); 1178 1179 dma += len; 1180 txaddr_info++; 1181 } 1182 1183 WARN_ONCE(remain, "length overflow remain=%u total_len=%u", 1184 remain, total_len); 1185 1186 *add_info_nr = n; 1187 1188 return n * sizeof(*txaddr_info); 1189 } 1190 EXPORT_SYMBOL(rtw89_pci_fill_txaddr_info_v1); 1191 1192 static int rtw89_pci_txwd_submit(struct rtw89_dev *rtwdev, 1193 struct rtw89_pci_tx_ring *tx_ring, 1194 struct rtw89_pci_tx_wd *txwd, 1195 struct rtw89_core_tx_request *tx_req) 1196 { 1197 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1198 const struct rtw89_chip_info *chip = rtwdev->chip; 1199 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1200 struct rtw89_txwd_info *txwd_info; 1201 struct rtw89_pci_tx_wp_info *txwp_info; 1202 void *txaddr_info_addr; 1203 struct pci_dev *pdev = rtwpci->pdev; 1204 struct sk_buff *skb = tx_req->skb; 1205 struct rtw89_pci_tx_data *tx_data = RTW89_PCI_TX_SKB_CB(skb); 1206 bool en_wd_info = desc_info->en_wd_info; 1207 u32 txwd_len; 1208 u32 txwp_len; 1209 u32 txaddr_info_len; 1210 dma_addr_t dma; 1211 int ret; 1212 1213 dma = dma_map_single(&pdev->dev, skb->data, skb->len, DMA_TO_DEVICE); 1214 if (dma_mapping_error(&pdev->dev, dma)) { 1215 rtw89_err(rtwdev, "failed to map skb dma data\n"); 1216 ret = -EBUSY; 1217 goto err; 1218 } 1219 1220 tx_data->dma = dma; 1221 1222 txwp_len = sizeof(*txwp_info); 1223 txwd_len = chip->txwd_body_size; 1224 txwd_len += en_wd_info ? sizeof(*txwd_info) : 0; 1225 1226 txwp_info = txwd->vaddr + txwd_len; 1227 txwp_info->seq0 = cpu_to_le16(txwd->seq | RTW89_PCI_TXWP_VALID); 1228 txwp_info->seq1 = 0; 1229 txwp_info->seq2 = 0; 1230 txwp_info->seq3 = 0; 1231 1232 tx_ring->tx_cnt++; 1233 txaddr_info_addr = txwd->vaddr + txwd_len + txwp_len; 1234 txaddr_info_len = 1235 rtw89_chip_fill_txaddr_info(rtwdev, txaddr_info_addr, skb->len, 1236 dma, &desc_info->addr_info_nr); 1237 1238 txwd->len = txwd_len + txwp_len + txaddr_info_len; 1239 1240 rtw89_chip_fill_txdesc(rtwdev, desc_info, txwd->vaddr); 1241 1242 skb_queue_tail(&txwd->queue, skb); 1243 1244 return 0; 1245 1246 err: 1247 return ret; 1248 } 1249 1250 static int rtw89_pci_fwcmd_submit(struct rtw89_dev *rtwdev, 1251 struct rtw89_pci_tx_ring *tx_ring, 1252 struct rtw89_pci_tx_bd_32 *txbd, 1253 struct rtw89_core_tx_request *tx_req) 1254 { 1255 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1256 const struct rtw89_chip_info *chip = rtwdev->chip; 1257 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1258 void *txdesc; 1259 int txdesc_size = chip->h2c_desc_size; 1260 struct pci_dev *pdev = rtwpci->pdev; 1261 struct sk_buff *skb = tx_req->skb; 1262 struct rtw89_pci_tx_data *tx_data = RTW89_PCI_TX_SKB_CB(skb); 1263 dma_addr_t dma; 1264 1265 txdesc = skb_push(skb, txdesc_size); 1266 memset(txdesc, 0, txdesc_size); 1267 rtw89_chip_fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 1268 1269 dma = dma_map_single(&pdev->dev, skb->data, skb->len, DMA_TO_DEVICE); 1270 if (dma_mapping_error(&pdev->dev, dma)) { 1271 rtw89_err(rtwdev, "failed to map fwcmd dma data\n"); 1272 return -EBUSY; 1273 } 1274 1275 tx_data->dma = dma; 1276 txbd->option = cpu_to_le16(RTW89_PCI_TXBD_OPTION_LS); 1277 txbd->length = cpu_to_le16(skb->len); 1278 txbd->dma = cpu_to_le32(tx_data->dma); 1279 skb_queue_tail(&rtwpci->h2c_queue, skb); 1280 1281 rtw89_pci_tx_bd_ring_update(rtwdev, tx_ring, 1); 1282 1283 return 0; 1284 } 1285 1286 static int rtw89_pci_txbd_submit(struct rtw89_dev *rtwdev, 1287 struct rtw89_pci_tx_ring *tx_ring, 1288 struct rtw89_pci_tx_bd_32 *txbd, 1289 struct rtw89_core_tx_request *tx_req) 1290 { 1291 struct rtw89_pci_tx_wd *txwd; 1292 int ret; 1293 1294 /* FWCMD queue doesn't have wd pages. Instead, it submits the CMD 1295 * buffer with WD BODY only. So here we don't need to check the free 1296 * pages of the wd ring. 1297 */ 1298 if (tx_ring->txch == RTW89_TXCH_CH12) 1299 return rtw89_pci_fwcmd_submit(rtwdev, tx_ring, txbd, tx_req); 1300 1301 txwd = rtw89_pci_dequeue_txwd(tx_ring); 1302 if (!txwd) { 1303 rtw89_err(rtwdev, "no available TXWD\n"); 1304 ret = -ENOSPC; 1305 goto err; 1306 } 1307 1308 ret = rtw89_pci_txwd_submit(rtwdev, tx_ring, txwd, tx_req); 1309 if (ret) { 1310 rtw89_err(rtwdev, "failed to submit TXWD %d\n", txwd->seq); 1311 goto err_enqueue_wd; 1312 } 1313 1314 list_add_tail(&txwd->list, &tx_ring->busy_pages); 1315 1316 txbd->option = cpu_to_le16(RTW89_PCI_TXBD_OPTION_LS); 1317 txbd->length = cpu_to_le16(txwd->len); 1318 txbd->dma = cpu_to_le32(txwd->paddr); 1319 1320 rtw89_pci_tx_bd_ring_update(rtwdev, tx_ring, 1); 1321 1322 return 0; 1323 1324 err_enqueue_wd: 1325 rtw89_pci_enqueue_txwd(tx_ring, txwd); 1326 err: 1327 return ret; 1328 } 1329 1330 static int rtw89_pci_tx_write(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req, 1331 u8 txch) 1332 { 1333 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1334 struct rtw89_pci_tx_ring *tx_ring; 1335 struct rtw89_pci_tx_bd_32 *txbd; 1336 u32 n_avail_txbd; 1337 int ret = 0; 1338 1339 /* check the tx type and dma channel for fw cmd queue */ 1340 if ((txch == RTW89_TXCH_CH12 || 1341 tx_req->tx_type == RTW89_CORE_TX_TYPE_FWCMD) && 1342 (txch != RTW89_TXCH_CH12 || 1343 tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD)) { 1344 rtw89_err(rtwdev, "only fw cmd uses dma channel 12\n"); 1345 return -EINVAL; 1346 } 1347 1348 tx_ring = &rtwpci->tx_rings[txch]; 1349 spin_lock_bh(&rtwpci->trx_lock); 1350 1351 n_avail_txbd = rtw89_pci_get_avail_txbd_num(tx_ring); 1352 if (n_avail_txbd == 0) { 1353 rtw89_err(rtwdev, "no available TXBD\n"); 1354 ret = -ENOSPC; 1355 goto err_unlock; 1356 } 1357 1358 txbd = rtw89_pci_get_next_txbd(tx_ring); 1359 ret = rtw89_pci_txbd_submit(rtwdev, tx_ring, txbd, tx_req); 1360 if (ret) { 1361 rtw89_err(rtwdev, "failed to submit TXBD\n"); 1362 goto err_unlock; 1363 } 1364 1365 spin_unlock_bh(&rtwpci->trx_lock); 1366 return 0; 1367 1368 err_unlock: 1369 spin_unlock_bh(&rtwpci->trx_lock); 1370 return ret; 1371 } 1372 1373 static int rtw89_pci_ops_tx_write(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req) 1374 { 1375 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1376 int ret; 1377 1378 ret = rtw89_pci_tx_write(rtwdev, tx_req, desc_info->ch_dma); 1379 if (ret) { 1380 rtw89_err(rtwdev, "failed to TX Queue %d\n", desc_info->ch_dma); 1381 return ret; 1382 } 1383 1384 return 0; 1385 } 1386 1387 const struct rtw89_pci_bd_ram rtw89_bd_ram_table_dual[RTW89_TXCH_NUM] = { 1388 [RTW89_TXCH_ACH0] = {.start_idx = 0, .max_num = 5, .min_num = 2}, 1389 [RTW89_TXCH_ACH1] = {.start_idx = 5, .max_num = 5, .min_num = 2}, 1390 [RTW89_TXCH_ACH2] = {.start_idx = 10, .max_num = 5, .min_num = 2}, 1391 [RTW89_TXCH_ACH3] = {.start_idx = 15, .max_num = 5, .min_num = 2}, 1392 [RTW89_TXCH_ACH4] = {.start_idx = 20, .max_num = 5, .min_num = 2}, 1393 [RTW89_TXCH_ACH5] = {.start_idx = 25, .max_num = 5, .min_num = 2}, 1394 [RTW89_TXCH_ACH6] = {.start_idx = 30, .max_num = 5, .min_num = 2}, 1395 [RTW89_TXCH_ACH7] = {.start_idx = 35, .max_num = 5, .min_num = 2}, 1396 [RTW89_TXCH_CH8] = {.start_idx = 40, .max_num = 5, .min_num = 1}, 1397 [RTW89_TXCH_CH9] = {.start_idx = 45, .max_num = 5, .min_num = 1}, 1398 [RTW89_TXCH_CH10] = {.start_idx = 50, .max_num = 5, .min_num = 1}, 1399 [RTW89_TXCH_CH11] = {.start_idx = 55, .max_num = 5, .min_num = 1}, 1400 [RTW89_TXCH_CH12] = {.start_idx = 60, .max_num = 4, .min_num = 1}, 1401 }; 1402 EXPORT_SYMBOL(rtw89_bd_ram_table_dual); 1403 1404 const struct rtw89_pci_bd_ram rtw89_bd_ram_table_single[RTW89_TXCH_NUM] = { 1405 [RTW89_TXCH_ACH0] = {.start_idx = 0, .max_num = 5, .min_num = 2}, 1406 [RTW89_TXCH_ACH1] = {.start_idx = 5, .max_num = 5, .min_num = 2}, 1407 [RTW89_TXCH_ACH2] = {.start_idx = 10, .max_num = 5, .min_num = 2}, 1408 [RTW89_TXCH_ACH3] = {.start_idx = 15, .max_num = 5, .min_num = 2}, 1409 [RTW89_TXCH_CH8] = {.start_idx = 20, .max_num = 4, .min_num = 1}, 1410 [RTW89_TXCH_CH9] = {.start_idx = 24, .max_num = 4, .min_num = 1}, 1411 [RTW89_TXCH_CH12] = {.start_idx = 28, .max_num = 4, .min_num = 1}, 1412 }; 1413 EXPORT_SYMBOL(rtw89_bd_ram_table_single); 1414 1415 static void rtw89_pci_reset_trx_rings(struct rtw89_dev *rtwdev) 1416 { 1417 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1418 const struct rtw89_pci_info *info = rtwdev->pci_info; 1419 const struct rtw89_pci_bd_ram *bd_ram_table = *info->bd_ram_table; 1420 struct rtw89_pci_tx_ring *tx_ring; 1421 struct rtw89_pci_rx_ring *rx_ring; 1422 struct rtw89_pci_dma_ring *bd_ring; 1423 const struct rtw89_pci_bd_ram *bd_ram; 1424 u32 addr_num; 1425 u32 addr_bdram; 1426 u32 addr_desa_l; 1427 u32 val32; 1428 int i; 1429 1430 for (i = 0; i < RTW89_TXCH_NUM; i++) { 1431 if (info->tx_dma_ch_mask & BIT(i)) 1432 continue; 1433 1434 tx_ring = &rtwpci->tx_rings[i]; 1435 bd_ring = &tx_ring->bd_ring; 1436 bd_ram = &bd_ram_table[i]; 1437 addr_num = bd_ring->addr.num; 1438 addr_bdram = bd_ring->addr.bdram; 1439 addr_desa_l = bd_ring->addr.desa_l; 1440 bd_ring->wp = 0; 1441 bd_ring->rp = 0; 1442 1443 val32 = FIELD_PREP(BDRAM_SIDX_MASK, bd_ram->start_idx) | 1444 FIELD_PREP(BDRAM_MAX_MASK, bd_ram->max_num) | 1445 FIELD_PREP(BDRAM_MIN_MASK, bd_ram->min_num); 1446 1447 rtw89_write16(rtwdev, addr_num, bd_ring->len); 1448 rtw89_write32(rtwdev, addr_bdram, val32); 1449 rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma); 1450 } 1451 1452 for (i = 0; i < RTW89_RXCH_NUM; i++) { 1453 rx_ring = &rtwpci->rx_rings[i]; 1454 bd_ring = &rx_ring->bd_ring; 1455 addr_num = bd_ring->addr.num; 1456 addr_desa_l = bd_ring->addr.desa_l; 1457 bd_ring->wp = 0; 1458 bd_ring->rp = 0; 1459 rx_ring->diliver_skb = NULL; 1460 rx_ring->diliver_desc.ready = false; 1461 1462 rtw89_write16(rtwdev, addr_num, bd_ring->len); 1463 rtw89_write32(rtwdev, addr_desa_l, bd_ring->dma); 1464 } 1465 } 1466 1467 static void rtw89_pci_release_tx_ring(struct rtw89_dev *rtwdev, 1468 struct rtw89_pci_tx_ring *tx_ring) 1469 { 1470 rtw89_pci_release_busy_txwd(rtwdev, tx_ring); 1471 rtw89_pci_release_pending_txwd_skb(rtwdev, tx_ring); 1472 } 1473 1474 static void rtw89_pci_ops_reset(struct rtw89_dev *rtwdev) 1475 { 1476 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1477 const struct rtw89_pci_info *info = rtwdev->pci_info; 1478 int txch; 1479 1480 rtw89_pci_reset_trx_rings(rtwdev); 1481 1482 spin_lock_bh(&rtwpci->trx_lock); 1483 for (txch = 0; txch < RTW89_TXCH_NUM; txch++) { 1484 if (info->tx_dma_ch_mask & BIT(txch)) 1485 continue; 1486 if (txch == RTW89_TXCH_CH12) { 1487 rtw89_pci_release_fwcmd(rtwdev, rtwpci, 1488 skb_queue_len(&rtwpci->h2c_queue), true); 1489 continue; 1490 } 1491 rtw89_pci_release_tx_ring(rtwdev, &rtwpci->tx_rings[txch]); 1492 } 1493 spin_unlock_bh(&rtwpci->trx_lock); 1494 } 1495 1496 static void rtw89_pci_enable_intr_lock(struct rtw89_dev *rtwdev) 1497 { 1498 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1499 unsigned long flags; 1500 1501 spin_lock_irqsave(&rtwpci->irq_lock, flags); 1502 rtwpci->running = true; 1503 rtw89_chip_enable_intr(rtwdev, rtwpci); 1504 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 1505 } 1506 1507 static void rtw89_pci_disable_intr_lock(struct rtw89_dev *rtwdev) 1508 { 1509 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1510 unsigned long flags; 1511 1512 spin_lock_irqsave(&rtwpci->irq_lock, flags); 1513 rtwpci->running = false; 1514 rtw89_chip_disable_intr(rtwdev, rtwpci); 1515 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 1516 } 1517 1518 static int rtw89_pci_ops_start(struct rtw89_dev *rtwdev) 1519 { 1520 rtw89_core_napi_start(rtwdev); 1521 rtw89_pci_enable_intr_lock(rtwdev); 1522 1523 return 0; 1524 } 1525 1526 static void rtw89_pci_ops_stop(struct rtw89_dev *rtwdev) 1527 { 1528 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1529 struct pci_dev *pdev = rtwpci->pdev; 1530 1531 rtw89_pci_disable_intr_lock(rtwdev); 1532 synchronize_irq(pdev->irq); 1533 rtw89_core_napi_stop(rtwdev); 1534 } 1535 1536 static void rtw89_pci_ops_pause(struct rtw89_dev *rtwdev, bool pause) 1537 { 1538 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1539 struct pci_dev *pdev = rtwpci->pdev; 1540 1541 if (pause) { 1542 rtw89_pci_disable_intr_lock(rtwdev); 1543 synchronize_irq(pdev->irq); 1544 if (test_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 1545 napi_synchronize(&rtwdev->napi); 1546 } else { 1547 rtw89_pci_enable_intr_lock(rtwdev); 1548 rtw89_pci_tx_kick_off_pending(rtwdev); 1549 } 1550 } 1551 1552 static 1553 void rtw89_pci_switch_bd_idx_addr(struct rtw89_dev *rtwdev, bool low_power) 1554 { 1555 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1556 const struct rtw89_pci_info *info = rtwdev->pci_info; 1557 const struct rtw89_pci_bd_idx_addr *bd_idx_addr = info->bd_idx_addr_low_power; 1558 const struct rtw89_pci_ch_dma_addr_set *dma_addr_set = info->dma_addr_set; 1559 struct rtw89_pci_tx_ring *tx_ring; 1560 struct rtw89_pci_rx_ring *rx_ring; 1561 int i; 1562 1563 if (WARN(!bd_idx_addr, "only HCI with low power mode needs this\n")) 1564 return; 1565 1566 for (i = 0; i < RTW89_TXCH_NUM; i++) { 1567 tx_ring = &rtwpci->tx_rings[i]; 1568 tx_ring->bd_ring.addr.idx = low_power ? 1569 bd_idx_addr->tx_bd_addrs[i] : 1570 dma_addr_set->tx[i].idx; 1571 } 1572 1573 for (i = 0; i < RTW89_RXCH_NUM; i++) { 1574 rx_ring = &rtwpci->rx_rings[i]; 1575 rx_ring->bd_ring.addr.idx = low_power ? 1576 bd_idx_addr->rx_bd_addrs[i] : 1577 dma_addr_set->rx[i].idx; 1578 } 1579 } 1580 1581 static void rtw89_pci_ops_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 1582 { 1583 enum rtw89_pci_intr_mask_cfg cfg; 1584 1585 WARN(!rtwdev->hci.paused, "HCI isn't paused\n"); 1586 1587 cfg = low_power ? RTW89_PCI_INTR_MASK_LOW_POWER : RTW89_PCI_INTR_MASK_NORMAL; 1588 rtw89_chip_config_intr_mask(rtwdev, cfg); 1589 rtw89_pci_switch_bd_idx_addr(rtwdev, low_power); 1590 } 1591 1592 static void rtw89_pci_ops_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data); 1593 1594 static u32 rtw89_pci_ops_read32_cmac(struct rtw89_dev *rtwdev, u32 addr) 1595 { 1596 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1597 u32 val = readl(rtwpci->mmap + addr); 1598 int count; 1599 1600 for (count = 0; ; count++) { 1601 if (val != RTW89_R32_DEAD) 1602 return val; 1603 if (count >= MAC_REG_POOL_COUNT) { 1604 rtw89_warn(rtwdev, "addr %#x = %#x\n", addr, val); 1605 return RTW89_R32_DEAD; 1606 } 1607 rtw89_pci_ops_write32(rtwdev, R_AX_CK_EN, B_AX_CMAC_ALLCKEN); 1608 val = readl(rtwpci->mmap + addr); 1609 } 1610 1611 return val; 1612 } 1613 1614 static u8 rtw89_pci_ops_read8(struct rtw89_dev *rtwdev, u32 addr) 1615 { 1616 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1617 u32 addr32, val32, shift; 1618 1619 if (!ACCESS_CMAC(addr)) 1620 return readb(rtwpci->mmap + addr); 1621 1622 addr32 = addr & ~0x3; 1623 shift = (addr & 0x3) * 8; 1624 val32 = rtw89_pci_ops_read32_cmac(rtwdev, addr32); 1625 return val32 >> shift; 1626 } 1627 1628 static u16 rtw89_pci_ops_read16(struct rtw89_dev *rtwdev, u32 addr) 1629 { 1630 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1631 u32 addr32, val32, shift; 1632 1633 if (!ACCESS_CMAC(addr)) 1634 return readw(rtwpci->mmap + addr); 1635 1636 addr32 = addr & ~0x3; 1637 shift = (addr & 0x3) * 8; 1638 val32 = rtw89_pci_ops_read32_cmac(rtwdev, addr32); 1639 return val32 >> shift; 1640 } 1641 1642 static u32 rtw89_pci_ops_read32(struct rtw89_dev *rtwdev, u32 addr) 1643 { 1644 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1645 1646 if (!ACCESS_CMAC(addr)) 1647 return readl(rtwpci->mmap + addr); 1648 1649 return rtw89_pci_ops_read32_cmac(rtwdev, addr); 1650 } 1651 1652 static void rtw89_pci_ops_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 1653 { 1654 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1655 1656 writeb(data, rtwpci->mmap + addr); 1657 } 1658 1659 static void rtw89_pci_ops_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 1660 { 1661 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1662 1663 writew(data, rtwpci->mmap + addr); 1664 } 1665 1666 static void rtw89_pci_ops_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 1667 { 1668 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1669 1670 writel(data, rtwpci->mmap + addr); 1671 } 1672 1673 static void rtw89_pci_ctrl_dma_trx(struct rtw89_dev *rtwdev, bool enable) 1674 { 1675 const struct rtw89_pci_info *info = rtwdev->pci_info; 1676 1677 if (enable) 1678 rtw89_write32_set(rtwdev, info->init_cfg_reg, 1679 info->rxhci_en_bit | info->txhci_en_bit); 1680 else 1681 rtw89_write32_clr(rtwdev, info->init_cfg_reg, 1682 info->rxhci_en_bit | info->txhci_en_bit); 1683 } 1684 1685 static void rtw89_pci_ctrl_dma_io(struct rtw89_dev *rtwdev, bool enable) 1686 { 1687 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1688 u32 reg, mask; 1689 1690 if (chip_id == RTL8852C) { 1691 reg = R_AX_HAXI_INIT_CFG1; 1692 mask = B_AX_STOP_AXI_MST; 1693 } else { 1694 reg = R_AX_PCIE_DMA_STOP1; 1695 mask = B_AX_STOP_PCIEIO; 1696 } 1697 1698 if (enable) 1699 rtw89_write32_clr(rtwdev, reg, mask); 1700 else 1701 rtw89_write32_set(rtwdev, reg, mask); 1702 } 1703 1704 static void rtw89_pci_ctrl_dma_all(struct rtw89_dev *rtwdev, bool enable) 1705 { 1706 rtw89_pci_ctrl_dma_io(rtwdev, enable); 1707 rtw89_pci_ctrl_dma_trx(rtwdev, enable); 1708 } 1709 1710 static int rtw89_pci_check_mdio(struct rtw89_dev *rtwdev, u8 addr, u8 speed, u16 rw_bit) 1711 { 1712 u16 val; 1713 1714 rtw89_write8(rtwdev, R_AX_MDIO_CFG, addr & 0x1F); 1715 1716 val = rtw89_read16(rtwdev, R_AX_MDIO_CFG); 1717 switch (speed) { 1718 case PCIE_PHY_GEN1: 1719 if (addr < 0x20) 1720 val = u16_replace_bits(val, MDIO_PG0_G1, B_AX_MDIO_PHY_ADDR_MASK); 1721 else 1722 val = u16_replace_bits(val, MDIO_PG1_G1, B_AX_MDIO_PHY_ADDR_MASK); 1723 break; 1724 case PCIE_PHY_GEN2: 1725 if (addr < 0x20) 1726 val = u16_replace_bits(val, MDIO_PG0_G2, B_AX_MDIO_PHY_ADDR_MASK); 1727 else 1728 val = u16_replace_bits(val, MDIO_PG1_G2, B_AX_MDIO_PHY_ADDR_MASK); 1729 break; 1730 default: 1731 rtw89_err(rtwdev, "[ERR]Error Speed %d!\n", speed); 1732 return -EINVAL; 1733 } 1734 rtw89_write16(rtwdev, R_AX_MDIO_CFG, val); 1735 rtw89_write16_set(rtwdev, R_AX_MDIO_CFG, rw_bit); 1736 1737 return read_poll_timeout(rtw89_read16, val, !(val & rw_bit), 10, 2000, 1738 false, rtwdev, R_AX_MDIO_CFG); 1739 } 1740 1741 static int 1742 rtw89_read16_mdio(struct rtw89_dev *rtwdev, u8 addr, u8 speed, u16 *val) 1743 { 1744 int ret; 1745 1746 ret = rtw89_pci_check_mdio(rtwdev, addr, speed, B_AX_MDIO_RFLAG); 1747 if (ret) { 1748 rtw89_err(rtwdev, "[ERR]MDIO R16 0x%X fail ret=%d!\n", addr, ret); 1749 return ret; 1750 } 1751 *val = rtw89_read16(rtwdev, R_AX_MDIO_RDATA); 1752 1753 return 0; 1754 } 1755 1756 static int 1757 rtw89_write16_mdio(struct rtw89_dev *rtwdev, u8 addr, u16 data, u8 speed) 1758 { 1759 int ret; 1760 1761 rtw89_write16(rtwdev, R_AX_MDIO_WDATA, data); 1762 ret = rtw89_pci_check_mdio(rtwdev, addr, speed, B_AX_MDIO_WFLAG); 1763 if (ret) { 1764 rtw89_err(rtwdev, "[ERR]MDIO W16 0x%X = %x fail ret=%d!\n", addr, data, ret); 1765 return ret; 1766 } 1767 1768 return 0; 1769 } 1770 1771 static int 1772 rtw89_write16_mdio_mask(struct rtw89_dev *rtwdev, u8 addr, u16 mask, u16 data, u8 speed) 1773 { 1774 u32 shift; 1775 int ret; 1776 u16 val; 1777 1778 ret = rtw89_read16_mdio(rtwdev, addr, speed, &val); 1779 if (ret) 1780 return ret; 1781 1782 shift = __ffs(mask); 1783 val &= ~mask; 1784 val |= ((data << shift) & mask); 1785 1786 ret = rtw89_write16_mdio(rtwdev, addr, val, speed); 1787 if (ret) 1788 return ret; 1789 1790 return 0; 1791 } 1792 1793 static int rtw89_write16_mdio_set(struct rtw89_dev *rtwdev, u8 addr, u16 mask, u8 speed) 1794 { 1795 int ret; 1796 u16 val; 1797 1798 ret = rtw89_read16_mdio(rtwdev, addr, speed, &val); 1799 if (ret) 1800 return ret; 1801 ret = rtw89_write16_mdio(rtwdev, addr, val | mask, speed); 1802 if (ret) 1803 return ret; 1804 1805 return 0; 1806 } 1807 1808 static int rtw89_write16_mdio_clr(struct rtw89_dev *rtwdev, u8 addr, u16 mask, u8 speed) 1809 { 1810 int ret; 1811 u16 val; 1812 1813 ret = rtw89_read16_mdio(rtwdev, addr, speed, &val); 1814 if (ret) 1815 return ret; 1816 ret = rtw89_write16_mdio(rtwdev, addr, val & ~mask, speed); 1817 if (ret) 1818 return ret; 1819 1820 return 0; 1821 } 1822 1823 static int rtw89_pci_write_config_byte(struct rtw89_dev *rtwdev, u16 addr, 1824 u8 data) 1825 { 1826 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1827 struct pci_dev *pdev = rtwpci->pdev; 1828 1829 return pci_write_config_byte(pdev, addr, data); 1830 } 1831 1832 static int rtw89_pci_read_config_byte(struct rtw89_dev *rtwdev, u16 addr, 1833 u8 *value) 1834 { 1835 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 1836 struct pci_dev *pdev = rtwpci->pdev; 1837 1838 return pci_read_config_byte(pdev, addr, value); 1839 } 1840 1841 static int rtw89_pci_config_byte_set(struct rtw89_dev *rtwdev, u16 addr, 1842 u8 bit) 1843 { 1844 u8 value; 1845 int ret; 1846 1847 ret = rtw89_pci_read_config_byte(rtwdev, addr, &value); 1848 if (ret) 1849 return ret; 1850 1851 value |= bit; 1852 ret = rtw89_pci_write_config_byte(rtwdev, addr, value); 1853 1854 return ret; 1855 } 1856 1857 static int rtw89_pci_config_byte_clr(struct rtw89_dev *rtwdev, u16 addr, 1858 u8 bit) 1859 { 1860 u8 value; 1861 int ret; 1862 1863 ret = rtw89_pci_read_config_byte(rtwdev, addr, &value); 1864 if (ret) 1865 return ret; 1866 1867 value &= ~bit; 1868 ret = rtw89_pci_write_config_byte(rtwdev, addr, value); 1869 1870 return ret; 1871 } 1872 1873 static int 1874 __get_target(struct rtw89_dev *rtwdev, u16 *target, enum rtw89_pcie_phy phy_rate) 1875 { 1876 u16 val, tar; 1877 int ret; 1878 1879 /* Enable counter */ 1880 ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val); 1881 if (ret) 1882 return ret; 1883 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val & ~B_AX_CLK_CALIB_EN, 1884 phy_rate); 1885 if (ret) 1886 return ret; 1887 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val | B_AX_CLK_CALIB_EN, 1888 phy_rate); 1889 if (ret) 1890 return ret; 1891 1892 fsleep(300); 1893 1894 ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &tar); 1895 if (ret) 1896 return ret; 1897 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val & ~B_AX_CLK_CALIB_EN, 1898 phy_rate); 1899 if (ret) 1900 return ret; 1901 1902 tar = tar & 0x0FFF; 1903 if (tar == 0 || tar == 0x0FFF) { 1904 rtw89_err(rtwdev, "[ERR]Get target failed.\n"); 1905 return -EINVAL; 1906 } 1907 1908 *target = tar; 1909 1910 return 0; 1911 } 1912 1913 static int rtw89_pci_autok_x(struct rtw89_dev *rtwdev) 1914 { 1915 int ret; 1916 1917 if (rtwdev->chip->chip_id != RTL8852B) 1918 return 0; 1919 1920 ret = rtw89_write16_mdio_mask(rtwdev, RAC_REG_FLD_0, BAC_AUTOK_N_MASK, 1921 PCIE_AUTOK_4, PCIE_PHY_GEN1); 1922 return ret; 1923 } 1924 1925 static int rtw89_pci_auto_refclk_cal(struct rtw89_dev *rtwdev, bool autook_en) 1926 { 1927 enum rtw89_pcie_phy phy_rate; 1928 u16 val16, mgn_set, div_set, tar; 1929 u8 val8, bdr_ori; 1930 bool l1_flag = false; 1931 int ret = 0; 1932 1933 if (rtwdev->chip->chip_id != RTL8852B) 1934 return 0; 1935 1936 ret = rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_PHY_RATE, &val8); 1937 if (ret) { 1938 rtw89_err(rtwdev, "[ERR]pci config read %X\n", 1939 RTW89_PCIE_PHY_RATE); 1940 return ret; 1941 } 1942 1943 if (FIELD_GET(RTW89_PCIE_PHY_RATE_MASK, val8) == 0x1) { 1944 phy_rate = PCIE_PHY_GEN1; 1945 } else if (FIELD_GET(RTW89_PCIE_PHY_RATE_MASK, val8) == 0x2) { 1946 phy_rate = PCIE_PHY_GEN2; 1947 } else { 1948 rtw89_err(rtwdev, "[ERR]PCIe PHY rate %#x not support\n", val8); 1949 return -EOPNOTSUPP; 1950 } 1951 /* Disable L1BD */ 1952 ret = rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_L1_CTRL, &bdr_ori); 1953 if (ret) { 1954 rtw89_err(rtwdev, "[ERR]pci config read %X\n", RTW89_PCIE_L1_CTRL); 1955 return ret; 1956 } 1957 1958 if (bdr_ori & RTW89_PCIE_BIT_L1) { 1959 ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_L1_CTRL, 1960 bdr_ori & ~RTW89_PCIE_BIT_L1); 1961 if (ret) { 1962 rtw89_err(rtwdev, "[ERR]pci config write %X\n", 1963 RTW89_PCIE_L1_CTRL); 1964 return ret; 1965 } 1966 l1_flag = true; 1967 } 1968 1969 ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val16); 1970 if (ret) { 1971 rtw89_err(rtwdev, "[ERR]mdio_r16_pcie %X\n", RAC_CTRL_PPR_V1); 1972 goto end; 1973 } 1974 1975 if (val16 & B_AX_CALIB_EN) { 1976 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, 1977 val16 & ~B_AX_CALIB_EN, phy_rate); 1978 if (ret) { 1979 rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); 1980 goto end; 1981 } 1982 } 1983 1984 if (!autook_en) 1985 goto end; 1986 /* Set div */ 1987 ret = rtw89_write16_mdio_clr(rtwdev, RAC_CTRL_PPR_V1, B_AX_DIV, phy_rate); 1988 if (ret) { 1989 rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); 1990 goto end; 1991 } 1992 1993 /* Obtain div and margin */ 1994 ret = __get_target(rtwdev, &tar, phy_rate); 1995 if (ret) { 1996 rtw89_err(rtwdev, "[ERR]1st get target fail %d\n", ret); 1997 goto end; 1998 } 1999 2000 mgn_set = tar * INTF_INTGRA_HOSTREF_V1 / INTF_INTGRA_MINREF_V1 - tar; 2001 2002 if (mgn_set >= 128) { 2003 div_set = 0x0003; 2004 mgn_set = 0x000F; 2005 } else if (mgn_set >= 64) { 2006 div_set = 0x0003; 2007 mgn_set >>= 3; 2008 } else if (mgn_set >= 32) { 2009 div_set = 0x0002; 2010 mgn_set >>= 2; 2011 } else if (mgn_set >= 16) { 2012 div_set = 0x0001; 2013 mgn_set >>= 1; 2014 } else if (mgn_set == 0) { 2015 rtw89_err(rtwdev, "[ERR]cal mgn is 0,tar = %d\n", tar); 2016 goto end; 2017 } else { 2018 div_set = 0x0000; 2019 } 2020 2021 ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val16); 2022 if (ret) { 2023 rtw89_err(rtwdev, "[ERR]mdio_r16_pcie %X\n", RAC_CTRL_PPR_V1); 2024 goto end; 2025 } 2026 2027 val16 |= u16_encode_bits(div_set, B_AX_DIV); 2028 2029 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val16, phy_rate); 2030 if (ret) { 2031 rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); 2032 goto end; 2033 } 2034 2035 ret = __get_target(rtwdev, &tar, phy_rate); 2036 if (ret) { 2037 rtw89_err(rtwdev, "[ERR]2nd get target fail %d\n", ret); 2038 goto end; 2039 } 2040 2041 rtw89_debug(rtwdev, RTW89_DBG_HCI, "[TRACE]target = 0x%X, div = 0x%X, margin = 0x%X\n", 2042 tar, div_set, mgn_set); 2043 ret = rtw89_write16_mdio(rtwdev, RAC_SET_PPR_V1, 2044 (tar & 0x0FFF) | (mgn_set << 12), phy_rate); 2045 if (ret) { 2046 rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_SET_PPR_V1); 2047 goto end; 2048 } 2049 2050 /* Enable function */ 2051 ret = rtw89_write16_mdio_set(rtwdev, RAC_CTRL_PPR_V1, B_AX_CALIB_EN, phy_rate); 2052 if (ret) { 2053 rtw89_err(rtwdev, "[ERR]mdio_w16_pcie %X\n", RAC_CTRL_PPR_V1); 2054 goto end; 2055 } 2056 2057 /* CLK delay = 0 */ 2058 ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_CLK_CTRL, 2059 PCIE_CLKDLY_HW_0); 2060 2061 end: 2062 /* Set L1BD to ori */ 2063 if (l1_flag) { 2064 ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_L1_CTRL, 2065 bdr_ori); 2066 if (ret) { 2067 rtw89_err(rtwdev, "[ERR]pci config write %X\n", 2068 RTW89_PCIE_L1_CTRL); 2069 return ret; 2070 } 2071 } 2072 2073 return ret; 2074 } 2075 2076 static int rtw89_pci_deglitch_setting(struct rtw89_dev *rtwdev) 2077 { 2078 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2079 int ret; 2080 2081 if (chip_id == RTL8852A) { 2082 ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH, 2083 PCIE_PHY_GEN1); 2084 if (ret) 2085 return ret; 2086 ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH, 2087 PCIE_PHY_GEN2); 2088 if (ret) 2089 return ret; 2090 } else if (chip_id == RTL8852C) { 2091 rtw89_write16_clr(rtwdev, R_RAC_DIRECT_OFFSET_G1 + RAC_ANA24 * 2, 2092 B_AX_DEGLITCH); 2093 rtw89_write16_clr(rtwdev, R_RAC_DIRECT_OFFSET_G2 + RAC_ANA24 * 2, 2094 B_AX_DEGLITCH); 2095 } 2096 2097 return 0; 2098 } 2099 2100 static void rtw89_pci_rxdma_prefth(struct rtw89_dev *rtwdev) 2101 { 2102 if (rtwdev->chip->chip_id != RTL8852A) 2103 return; 2104 2105 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_DIS_RXDMA_PRE); 2106 } 2107 2108 static void rtw89_pci_l1off_pwroff(struct rtw89_dev *rtwdev) 2109 { 2110 if (rtwdev->chip->chip_id != RTL8852A && rtwdev->chip->chip_id != RTL8852B) 2111 return; 2112 2113 rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL, B_AX_L1OFF_PWR_OFF_EN); 2114 } 2115 2116 static u32 rtw89_pci_l2_rxen_lat(struct rtw89_dev *rtwdev) 2117 { 2118 int ret; 2119 2120 if (rtwdev->chip->chip_id != RTL8852A) 2121 return 0; 2122 2123 ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA26, B_AX_RXEN, 2124 PCIE_PHY_GEN1); 2125 if (ret) 2126 return ret; 2127 2128 ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA26, B_AX_RXEN, 2129 PCIE_PHY_GEN2); 2130 if (ret) 2131 return ret; 2132 2133 return 0; 2134 } 2135 2136 static void rtw89_pci_aphy_pwrcut(struct rtw89_dev *rtwdev) 2137 { 2138 if (rtwdev->chip->chip_id != RTL8852A && rtwdev->chip->chip_id != RTL8852B) 2139 return; 2140 2141 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_PSUS_OFF_CAPC_EN); 2142 } 2143 2144 static void rtw89_pci_hci_ldo(struct rtw89_dev *rtwdev) 2145 { 2146 if (rtwdev->chip->chip_id == RTL8852A || 2147 rtwdev->chip->chip_id == RTL8852B) { 2148 rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, 2149 B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); 2150 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, 2151 B_AX_PCIE_DIS_WLSUS_AFT_PDN); 2152 } else if (rtwdev->chip->chip_id == RTL8852C) { 2153 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, 2154 B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); 2155 } 2156 } 2157 2158 static int rtw89_pci_dphy_delay(struct rtw89_dev *rtwdev) 2159 { 2160 if (rtwdev->chip->chip_id != RTL8852B) 2161 return 0; 2162 2163 return rtw89_write16_mdio_mask(rtwdev, RAC_REG_REV2, BAC_CMU_EN_DLY_MASK, 2164 PCIE_DPHY_DLY_25US, PCIE_PHY_GEN1); 2165 } 2166 2167 static void rtw89_pci_power_wake(struct rtw89_dev *rtwdev, bool pwr_up) 2168 { 2169 if (pwr_up) 2170 rtw89_write32_set(rtwdev, R_AX_HCI_OPT_CTRL, BIT_WAKE_CTRL); 2171 else 2172 rtw89_write32_clr(rtwdev, R_AX_HCI_OPT_CTRL, BIT_WAKE_CTRL); 2173 } 2174 2175 static void rtw89_pci_autoload_hang(struct rtw89_dev *rtwdev) 2176 { 2177 if (rtwdev->chip->chip_id != RTL8852C) 2178 return; 2179 2180 rtw89_write32_set(rtwdev, R_AX_PCIE_BG_CLR, B_AX_BG_CLR_ASYNC_M3); 2181 rtw89_write32_clr(rtwdev, R_AX_PCIE_BG_CLR, B_AX_BG_CLR_ASYNC_M3); 2182 } 2183 2184 static void rtw89_pci_l12_vmain(struct rtw89_dev *rtwdev) 2185 { 2186 if (!(rtwdev->chip->chip_id == RTL8852C && rtwdev->hal.cv == CHIP_CAV)) 2187 return; 2188 2189 rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_FORCE_PWR_NGAT); 2190 } 2191 2192 static void rtw89_pci_gen2_force_ib(struct rtw89_dev *rtwdev) 2193 { 2194 if (!(rtwdev->chip->chip_id == RTL8852C && rtwdev->hal.cv == CHIP_CAV)) 2195 return; 2196 2197 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, 2198 B_AX_SYSON_DIS_PMCR_AX_WRMSK); 2199 rtw89_write32_set(rtwdev, R_AX_HCI_BG_CTRL, B_AX_BG_CLR_ASYNC_M3); 2200 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, 2201 B_AX_SYSON_DIS_PMCR_AX_WRMSK); 2202 } 2203 2204 static void rtw89_pci_l1_ent_lat(struct rtw89_dev *rtwdev) 2205 { 2206 if (rtwdev->chip->chip_id != RTL8852C) 2207 return; 2208 2209 rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL_V1, B_AX_SEL_REQ_ENTR_L1); 2210 } 2211 2212 static void rtw89_pci_wd_exit_l1(struct rtw89_dev *rtwdev) 2213 { 2214 if (rtwdev->chip->chip_id != RTL8852C) 2215 return; 2216 2217 rtw89_write32_set(rtwdev, R_AX_PCIE_PS_CTRL_V1, B_AX_DMAC0_EXIT_L1_EN); 2218 } 2219 2220 static void rtw89_pci_set_sic(struct rtw89_dev *rtwdev) 2221 { 2222 if (rtwdev->chip->chip_id == RTL8852C) 2223 return; 2224 2225 rtw89_write32_clr(rtwdev, R_AX_PCIE_EXP_CTRL, 2226 B_AX_SIC_EN_FORCE_CLKREQ); 2227 } 2228 2229 static void rtw89_pci_set_lbc(struct rtw89_dev *rtwdev) 2230 { 2231 const struct rtw89_pci_info *info = rtwdev->pci_info; 2232 u32 lbc; 2233 2234 if (rtwdev->chip->chip_id == RTL8852C) 2235 return; 2236 2237 lbc = rtw89_read32(rtwdev, R_AX_LBC_WATCHDOG); 2238 if (info->lbc_en == MAC_AX_PCIE_ENABLE) { 2239 lbc = u32_replace_bits(lbc, info->lbc_tmr, B_AX_LBC_TIMER); 2240 lbc |= B_AX_LBC_FLAG | B_AX_LBC_EN; 2241 rtw89_write32(rtwdev, R_AX_LBC_WATCHDOG, lbc); 2242 } else { 2243 lbc &= ~B_AX_LBC_EN; 2244 } 2245 rtw89_write32_set(rtwdev, R_AX_LBC_WATCHDOG, lbc); 2246 } 2247 2248 static void rtw89_pci_set_io_rcy(struct rtw89_dev *rtwdev) 2249 { 2250 const struct rtw89_pci_info *info = rtwdev->pci_info; 2251 u32 val32; 2252 2253 if (rtwdev->chip->chip_id != RTL8852C) 2254 return; 2255 2256 if (info->io_rcy_en == MAC_AX_PCIE_ENABLE) { 2257 val32 = FIELD_PREP(B_AX_PCIE_WDT_TIMER_M1_MASK, 2258 info->io_rcy_tmr); 2259 rtw89_write32(rtwdev, R_AX_PCIE_WDT_TIMER_M1, val32); 2260 rtw89_write32(rtwdev, R_AX_PCIE_WDT_TIMER_M2, val32); 2261 rtw89_write32(rtwdev, R_AX_PCIE_WDT_TIMER_E0, val32); 2262 2263 rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_M1, B_AX_PCIE_IO_RCY_WDT_MODE_M1); 2264 rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_M2, B_AX_PCIE_IO_RCY_WDT_MODE_M2); 2265 rtw89_write32_set(rtwdev, R_AX_PCIE_IO_RCY_E0, B_AX_PCIE_IO_RCY_WDT_MODE_E0); 2266 } else { 2267 rtw89_write32_clr(rtwdev, R_AX_PCIE_IO_RCY_M1, B_AX_PCIE_IO_RCY_WDT_MODE_M1); 2268 rtw89_write32_clr(rtwdev, R_AX_PCIE_IO_RCY_M2, B_AX_PCIE_IO_RCY_WDT_MODE_M2); 2269 rtw89_write32_clr(rtwdev, R_AX_PCIE_IO_RCY_E0, B_AX_PCIE_IO_RCY_WDT_MODE_E0); 2270 } 2271 2272 rtw89_write32_clr(rtwdev, R_AX_PCIE_IO_RCY_S1, B_AX_PCIE_IO_RCY_WDT_MODE_S1); 2273 } 2274 2275 static void rtw89_pci_set_dbg(struct rtw89_dev *rtwdev) 2276 { 2277 if (rtwdev->chip->chip_id == RTL8852C) 2278 return; 2279 2280 rtw89_write32_set(rtwdev, R_AX_PCIE_DBG_CTRL, 2281 B_AX_ASFF_FULL_NO_STK | B_AX_EN_STUCK_DBG); 2282 2283 if (rtwdev->chip->chip_id == RTL8852A) 2284 rtw89_write32_set(rtwdev, R_AX_PCIE_EXP_CTRL, 2285 B_AX_EN_CHKDSC_NO_RX_STUCK); 2286 } 2287 2288 static void rtw89_pci_set_keep_reg(struct rtw89_dev *rtwdev) 2289 { 2290 if (rtwdev->chip->chip_id == RTL8852C) 2291 return; 2292 2293 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, 2294 B_AX_PCIE_TXRST_KEEP_REG | B_AX_PCIE_RXRST_KEEP_REG); 2295 } 2296 2297 static void rtw89_pci_clr_idx_all(struct rtw89_dev *rtwdev) 2298 { 2299 const struct rtw89_pci_info *info = rtwdev->pci_info; 2300 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2301 u32 val = B_AX_CLR_ACH0_IDX | B_AX_CLR_ACH1_IDX | B_AX_CLR_ACH2_IDX | 2302 B_AX_CLR_ACH3_IDX | B_AX_CLR_CH8_IDX | B_AX_CLR_CH9_IDX | 2303 B_AX_CLR_CH12_IDX; 2304 u32 rxbd_rwptr_clr = info->rxbd_rwptr_clr_reg; 2305 u32 txbd_rwptr_clr2 = info->txbd_rwptr_clr2_reg; 2306 2307 if (chip_id == RTL8852A || chip_id == RTL8852C) 2308 val |= B_AX_CLR_ACH4_IDX | B_AX_CLR_ACH5_IDX | 2309 B_AX_CLR_ACH6_IDX | B_AX_CLR_ACH7_IDX; 2310 /* clear DMA indexes */ 2311 rtw89_write32_set(rtwdev, R_AX_TXBD_RWPTR_CLR1, val); 2312 if (chip_id == RTL8852A || chip_id == RTL8852C) 2313 rtw89_write32_set(rtwdev, txbd_rwptr_clr2, 2314 B_AX_CLR_CH10_IDX | B_AX_CLR_CH11_IDX); 2315 rtw89_write32_set(rtwdev, rxbd_rwptr_clr, 2316 B_AX_CLR_RXQ_IDX | B_AX_CLR_RPQ_IDX); 2317 } 2318 2319 static int rtw89_poll_txdma_ch_idle_pcie(struct rtw89_dev *rtwdev) 2320 { 2321 const struct rtw89_pci_info *info = rtwdev->pci_info; 2322 u32 ret, check, dma_busy; 2323 u32 dma_busy1 = info->dma_busy1.addr; 2324 u32 dma_busy2 = info->dma_busy2_reg; 2325 2326 check = info->dma_busy1.mask; 2327 2328 ret = read_poll_timeout(rtw89_read32, dma_busy, (dma_busy & check) == 0, 2329 10, 100, false, rtwdev, dma_busy1); 2330 if (ret) 2331 return ret; 2332 2333 if (!dma_busy2) 2334 return 0; 2335 2336 check = B_AX_CH10_BUSY | B_AX_CH11_BUSY; 2337 2338 ret = read_poll_timeout(rtw89_read32, dma_busy, (dma_busy & check) == 0, 2339 10, 100, false, rtwdev, dma_busy2); 2340 if (ret) 2341 return ret; 2342 2343 return 0; 2344 } 2345 2346 static int rtw89_poll_rxdma_ch_idle_pcie(struct rtw89_dev *rtwdev) 2347 { 2348 const struct rtw89_pci_info *info = rtwdev->pci_info; 2349 u32 ret, check, dma_busy; 2350 u32 dma_busy3 = info->dma_busy3_reg; 2351 2352 check = B_AX_RXQ_BUSY | B_AX_RPQ_BUSY; 2353 2354 ret = read_poll_timeout(rtw89_read32, dma_busy, (dma_busy & check) == 0, 2355 10, 100, false, rtwdev, dma_busy3); 2356 if (ret) 2357 return ret; 2358 2359 return 0; 2360 } 2361 2362 static int rtw89_pci_poll_dma_all_idle(struct rtw89_dev *rtwdev) 2363 { 2364 u32 ret; 2365 2366 ret = rtw89_poll_txdma_ch_idle_pcie(rtwdev); 2367 if (ret) { 2368 rtw89_err(rtwdev, "txdma ch busy\n"); 2369 return ret; 2370 } 2371 2372 ret = rtw89_poll_rxdma_ch_idle_pcie(rtwdev); 2373 if (ret) { 2374 rtw89_err(rtwdev, "rxdma ch busy\n"); 2375 return ret; 2376 } 2377 2378 return 0; 2379 } 2380 2381 static int rtw89_pci_mode_op(struct rtw89_dev *rtwdev) 2382 { 2383 const struct rtw89_pci_info *info = rtwdev->pci_info; 2384 enum mac_ax_bd_trunc_mode txbd_trunc_mode = info->txbd_trunc_mode; 2385 enum mac_ax_bd_trunc_mode rxbd_trunc_mode = info->rxbd_trunc_mode; 2386 enum mac_ax_rxbd_mode rxbd_mode = info->rxbd_mode; 2387 enum mac_ax_tag_mode tag_mode = info->tag_mode; 2388 enum mac_ax_wd_dma_intvl wd_dma_idle_intvl = info->wd_dma_idle_intvl; 2389 enum mac_ax_wd_dma_intvl wd_dma_act_intvl = info->wd_dma_act_intvl; 2390 enum mac_ax_tx_burst tx_burst = info->tx_burst; 2391 enum mac_ax_rx_burst rx_burst = info->rx_burst; 2392 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2393 u8 cv = rtwdev->hal.cv; 2394 u32 val32; 2395 2396 if (txbd_trunc_mode == MAC_AX_BD_TRUNC) { 2397 if (chip_id == RTL8852A && cv == CHIP_CBV) 2398 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_TX_TRUNC_MODE); 2399 } else if (txbd_trunc_mode == MAC_AX_BD_NORM) { 2400 if (chip_id == RTL8852A || chip_id == RTL8852B) 2401 rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_TX_TRUNC_MODE); 2402 } 2403 2404 if (rxbd_trunc_mode == MAC_AX_BD_TRUNC) { 2405 if (chip_id == RTL8852A && cv == CHIP_CBV) 2406 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_RX_TRUNC_MODE); 2407 } else if (rxbd_trunc_mode == MAC_AX_BD_NORM) { 2408 if (chip_id == RTL8852A || chip_id == RTL8852B) 2409 rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_RX_TRUNC_MODE); 2410 } 2411 2412 if (rxbd_mode == MAC_AX_RXBD_PKT) { 2413 rtw89_write32_clr(rtwdev, info->init_cfg_reg, info->rxbd_mode_bit); 2414 } else if (rxbd_mode == MAC_AX_RXBD_SEP) { 2415 rtw89_write32_set(rtwdev, info->init_cfg_reg, info->rxbd_mode_bit); 2416 2417 if (chip_id == RTL8852A || chip_id == RTL8852B) 2418 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, 2419 B_AX_PCIE_RX_APPLEN_MASK, 0); 2420 } 2421 2422 if (chip_id == RTL8852A || chip_id == RTL8852B) { 2423 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_TXDMA_MASK, tx_burst); 2424 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_PCIE_MAX_RXDMA_MASK, rx_burst); 2425 } else if (chip_id == RTL8852C) { 2426 rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_HAXI_MAX_TXDMA_MASK, tx_burst); 2427 rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_HAXI_MAX_RXDMA_MASK, rx_burst); 2428 } 2429 2430 if (chip_id == RTL8852A || chip_id == RTL8852B) { 2431 if (tag_mode == MAC_AX_TAG_SGL) { 2432 val32 = rtw89_read32(rtwdev, R_AX_PCIE_INIT_CFG1) & 2433 ~B_AX_LATENCY_CONTROL; 2434 rtw89_write32(rtwdev, R_AX_PCIE_INIT_CFG1, val32); 2435 } else if (tag_mode == MAC_AX_TAG_MULTI) { 2436 val32 = rtw89_read32(rtwdev, R_AX_PCIE_INIT_CFG1) | 2437 B_AX_LATENCY_CONTROL; 2438 rtw89_write32(rtwdev, R_AX_PCIE_INIT_CFG1, val32); 2439 } 2440 } 2441 2442 rtw89_write32_mask(rtwdev, info->exp_ctrl_reg, info->max_tag_num_mask, 2443 info->multi_tag_num); 2444 2445 if (chip_id == RTL8852A || chip_id == RTL8852B) { 2446 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_IDLE, 2447 wd_dma_idle_intvl); 2448 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_ACT, 2449 wd_dma_act_intvl); 2450 } else if (chip_id == RTL8852C) { 2451 rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_WD_ITVL_IDLE_V1_MASK, 2452 wd_dma_idle_intvl); 2453 rtw89_write32_mask(rtwdev, R_AX_HAXI_INIT_CFG1, B_AX_WD_ITVL_ACT_V1_MASK, 2454 wd_dma_act_intvl); 2455 } 2456 2457 if (txbd_trunc_mode == MAC_AX_BD_TRUNC) { 2458 rtw89_write32_set(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING, 2459 B_AX_HOST_ADDR_INFO_8B_SEL); 2460 rtw89_write32_clr(rtwdev, R_AX_PKTIN_SETTING, B_AX_WD_ADDR_INFO_LENGTH); 2461 } else if (txbd_trunc_mode == MAC_AX_BD_NORM) { 2462 rtw89_write32_clr(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING, 2463 B_AX_HOST_ADDR_INFO_8B_SEL); 2464 rtw89_write32_set(rtwdev, R_AX_PKTIN_SETTING, B_AX_WD_ADDR_INFO_LENGTH); 2465 } 2466 2467 return 0; 2468 } 2469 2470 static int rtw89_pci_ops_deinit(struct rtw89_dev *rtwdev) 2471 { 2472 const struct rtw89_pci_info *info = rtwdev->pci_info; 2473 2474 if (rtwdev->chip->chip_id == RTL8852A) { 2475 /* ltr sw trigger */ 2476 rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_APP_LTR_IDLE); 2477 } 2478 info->ltr_set(rtwdev, false); 2479 rtw89_pci_ctrl_dma_all(rtwdev, false); 2480 rtw89_pci_clr_idx_all(rtwdev); 2481 2482 return 0; 2483 } 2484 2485 static int rtw89_pci_ops_mac_pre_init(struct rtw89_dev *rtwdev) 2486 { 2487 const struct rtw89_pci_info *info = rtwdev->pci_info; 2488 int ret; 2489 2490 rtw89_pci_rxdma_prefth(rtwdev); 2491 rtw89_pci_l1off_pwroff(rtwdev); 2492 rtw89_pci_deglitch_setting(rtwdev); 2493 ret = rtw89_pci_l2_rxen_lat(rtwdev); 2494 if (ret) { 2495 rtw89_err(rtwdev, "[ERR] pcie l2 rxen lat %d\n", ret); 2496 return ret; 2497 } 2498 2499 rtw89_pci_aphy_pwrcut(rtwdev); 2500 rtw89_pci_hci_ldo(rtwdev); 2501 rtw89_pci_dphy_delay(rtwdev); 2502 2503 ret = rtw89_pci_autok_x(rtwdev); 2504 if (ret) { 2505 rtw89_err(rtwdev, "[ERR] pcie autok_x fail %d\n", ret); 2506 return ret; 2507 } 2508 2509 ret = rtw89_pci_auto_refclk_cal(rtwdev, false); 2510 if (ret) { 2511 rtw89_err(rtwdev, "[ERR] pcie autok fail %d\n", ret); 2512 return ret; 2513 } 2514 2515 rtw89_pci_power_wake(rtwdev, true); 2516 rtw89_pci_autoload_hang(rtwdev); 2517 rtw89_pci_l12_vmain(rtwdev); 2518 rtw89_pci_gen2_force_ib(rtwdev); 2519 rtw89_pci_l1_ent_lat(rtwdev); 2520 rtw89_pci_wd_exit_l1(rtwdev); 2521 rtw89_pci_set_sic(rtwdev); 2522 rtw89_pci_set_lbc(rtwdev); 2523 rtw89_pci_set_io_rcy(rtwdev); 2524 rtw89_pci_set_dbg(rtwdev); 2525 rtw89_pci_set_keep_reg(rtwdev); 2526 2527 rtw89_write32_set(rtwdev, info->dma_stop1.addr, B_AX_STOP_WPDMA); 2528 2529 /* stop DMA activities */ 2530 rtw89_pci_ctrl_dma_all(rtwdev, false); 2531 2532 ret = rtw89_pci_poll_dma_all_idle(rtwdev); 2533 if (ret) { 2534 rtw89_err(rtwdev, "[ERR] poll pcie dma all idle\n"); 2535 return ret; 2536 } 2537 2538 rtw89_pci_clr_idx_all(rtwdev); 2539 rtw89_pci_mode_op(rtwdev); 2540 2541 /* fill TRX BD indexes */ 2542 rtw89_pci_ops_reset(rtwdev); 2543 2544 ret = rtw89_pci_rst_bdram_pcie(rtwdev); 2545 if (ret) { 2546 rtw89_warn(rtwdev, "reset bdram busy\n"); 2547 return ret; 2548 } 2549 2550 /* disable all channels except to FW CMD channel to download firmware */ 2551 rtw89_pci_ctrl_txdma_ch_pcie(rtwdev, false); 2552 rtw89_pci_ctrl_txdma_fw_ch_pcie(rtwdev, true); 2553 2554 /* start DMA activities */ 2555 rtw89_pci_ctrl_dma_all(rtwdev, true); 2556 2557 return 0; 2558 } 2559 2560 int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev, bool en) 2561 { 2562 u32 val; 2563 2564 if (!en) 2565 return 0; 2566 2567 val = rtw89_read32(rtwdev, R_AX_LTR_CTRL_0); 2568 if (rtw89_pci_ltr_is_err_reg_val(val)) 2569 return -EINVAL; 2570 val = rtw89_read32(rtwdev, R_AX_LTR_CTRL_1); 2571 if (rtw89_pci_ltr_is_err_reg_val(val)) 2572 return -EINVAL; 2573 val = rtw89_read32(rtwdev, R_AX_LTR_IDLE_LATENCY); 2574 if (rtw89_pci_ltr_is_err_reg_val(val)) 2575 return -EINVAL; 2576 val = rtw89_read32(rtwdev, R_AX_LTR_ACTIVE_LATENCY); 2577 if (rtw89_pci_ltr_is_err_reg_val(val)) 2578 return -EINVAL; 2579 2580 rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_HW_EN | B_AX_LTR_EN | 2581 B_AX_LTR_WD_NOEMP_CHK); 2582 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_SPACE_IDX_MASK, 2583 PCI_LTR_SPC_500US); 2584 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_IDLE_TIMER_IDX_MASK, 2585 PCI_LTR_IDLE_TIMER_3_2MS); 2586 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX0_TH_MASK, 0x28); 2587 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX1_TH_MASK, 0x28); 2588 rtw89_write32(rtwdev, R_AX_LTR_IDLE_LATENCY, 0x90039003); 2589 rtw89_write32(rtwdev, R_AX_LTR_ACTIVE_LATENCY, 0x880b880b); 2590 2591 return 0; 2592 } 2593 EXPORT_SYMBOL(rtw89_pci_ltr_set); 2594 2595 int rtw89_pci_ltr_set_v1(struct rtw89_dev *rtwdev, bool en) 2596 { 2597 u32 dec_ctrl; 2598 u32 val32; 2599 2600 val32 = rtw89_read32(rtwdev, R_AX_LTR_CTRL_0); 2601 if (rtw89_pci_ltr_is_err_reg_val(val32)) 2602 return -EINVAL; 2603 val32 = rtw89_read32(rtwdev, R_AX_LTR_CTRL_1); 2604 if (rtw89_pci_ltr_is_err_reg_val(val32)) 2605 return -EINVAL; 2606 dec_ctrl = rtw89_read32(rtwdev, R_AX_LTR_DEC_CTRL); 2607 if (rtw89_pci_ltr_is_err_reg_val(dec_ctrl)) 2608 return -EINVAL; 2609 val32 = rtw89_read32(rtwdev, R_AX_LTR_LATENCY_IDX3); 2610 if (rtw89_pci_ltr_is_err_reg_val(val32)) 2611 return -EINVAL; 2612 val32 = rtw89_read32(rtwdev, R_AX_LTR_LATENCY_IDX0); 2613 if (rtw89_pci_ltr_is_err_reg_val(val32)) 2614 return -EINVAL; 2615 2616 if (!en) { 2617 dec_ctrl &= ~(LTR_EN_BITS | B_AX_LTR_IDX_DRV_MASK | B_AX_LTR_HW_DEC_EN); 2618 dec_ctrl |= FIELD_PREP(B_AX_LTR_IDX_DRV_MASK, PCIE_LTR_IDX_IDLE) | 2619 B_AX_LTR_REQ_DRV; 2620 } else { 2621 dec_ctrl |= B_AX_LTR_HW_DEC_EN; 2622 } 2623 2624 dec_ctrl &= ~B_AX_LTR_SPACE_IDX_V1_MASK; 2625 dec_ctrl |= FIELD_PREP(B_AX_LTR_SPACE_IDX_V1_MASK, PCI_LTR_SPC_500US); 2626 2627 if (en) 2628 rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, 2629 B_AX_LTR_WD_NOEMP_CHK_V1 | B_AX_LTR_HW_EN); 2630 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_IDLE_TIMER_IDX_MASK, 2631 PCI_LTR_IDLE_TIMER_3_2MS); 2632 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX0_TH_MASK, 0x28); 2633 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX1_TH_MASK, 0x28); 2634 rtw89_write32(rtwdev, R_AX_LTR_DEC_CTRL, dec_ctrl); 2635 rtw89_write32(rtwdev, R_AX_LTR_LATENCY_IDX3, 0x90039003); 2636 rtw89_write32(rtwdev, R_AX_LTR_LATENCY_IDX0, 0x880b880b); 2637 2638 return 0; 2639 } 2640 EXPORT_SYMBOL(rtw89_pci_ltr_set_v1); 2641 2642 static int rtw89_pci_ops_mac_post_init(struct rtw89_dev *rtwdev) 2643 { 2644 const struct rtw89_pci_info *info = rtwdev->pci_info; 2645 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2646 int ret; 2647 2648 ret = info->ltr_set(rtwdev, true); 2649 if (ret) { 2650 rtw89_err(rtwdev, "pci ltr set fail\n"); 2651 return ret; 2652 } 2653 if (chip_id == RTL8852A) { 2654 /* ltr sw trigger */ 2655 rtw89_write32_set(rtwdev, R_AX_LTR_CTRL_0, B_AX_APP_LTR_ACT); 2656 } 2657 if (chip_id == RTL8852A || chip_id == RTL8852B) { 2658 /* ADDR info 8-byte mode */ 2659 rtw89_write32_set(rtwdev, R_AX_TX_ADDRESS_INFO_MODE_SETTING, 2660 B_AX_HOST_ADDR_INFO_8B_SEL); 2661 rtw89_write32_clr(rtwdev, R_AX_PKTIN_SETTING, B_AX_WD_ADDR_INFO_LENGTH); 2662 } 2663 2664 /* enable DMA for all queues */ 2665 rtw89_pci_ctrl_txdma_ch_pcie(rtwdev, true); 2666 2667 /* Release PCI IO */ 2668 rtw89_write32_clr(rtwdev, info->dma_stop1.addr, 2669 B_AX_STOP_WPDMA | B_AX_STOP_PCIEIO); 2670 2671 return 0; 2672 } 2673 2674 static int rtw89_pci_claim_device(struct rtw89_dev *rtwdev, 2675 struct pci_dev *pdev) 2676 { 2677 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2678 int ret; 2679 2680 ret = pci_enable_device(pdev); 2681 if (ret) { 2682 rtw89_err(rtwdev, "failed to enable pci device\n"); 2683 return ret; 2684 } 2685 2686 pci_set_master(pdev); 2687 pci_set_drvdata(pdev, rtwdev->hw); 2688 2689 rtwpci->pdev = pdev; 2690 2691 return 0; 2692 } 2693 2694 static void rtw89_pci_declaim_device(struct rtw89_dev *rtwdev, 2695 struct pci_dev *pdev) 2696 { 2697 pci_clear_master(pdev); 2698 pci_disable_device(pdev); 2699 } 2700 2701 static int rtw89_pci_setup_mapping(struct rtw89_dev *rtwdev, 2702 struct pci_dev *pdev) 2703 { 2704 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2705 unsigned long resource_len; 2706 u8 bar_id = 2; 2707 int ret; 2708 2709 ret = pci_request_regions(pdev, KBUILD_MODNAME); 2710 if (ret) { 2711 rtw89_err(rtwdev, "failed to request pci regions\n"); 2712 goto err; 2713 } 2714 2715 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 2716 if (ret) { 2717 rtw89_err(rtwdev, "failed to set dma mask to 32-bit\n"); 2718 goto err_release_regions; 2719 } 2720 2721 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 2722 if (ret) { 2723 rtw89_err(rtwdev, "failed to set consistent dma mask to 32-bit\n"); 2724 goto err_release_regions; 2725 } 2726 2727 resource_len = pci_resource_len(pdev, bar_id); 2728 rtwpci->mmap = pci_iomap(pdev, bar_id, resource_len); 2729 if (!rtwpci->mmap) { 2730 rtw89_err(rtwdev, "failed to map pci io\n"); 2731 ret = -EIO; 2732 goto err_release_regions; 2733 } 2734 2735 return 0; 2736 2737 err_release_regions: 2738 pci_release_regions(pdev); 2739 err: 2740 return ret; 2741 } 2742 2743 static void rtw89_pci_clear_mapping(struct rtw89_dev *rtwdev, 2744 struct pci_dev *pdev) 2745 { 2746 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2747 2748 if (rtwpci->mmap) { 2749 pci_iounmap(pdev, rtwpci->mmap); 2750 pci_release_regions(pdev); 2751 } 2752 } 2753 2754 static void rtw89_pci_free_tx_wd_ring(struct rtw89_dev *rtwdev, 2755 struct pci_dev *pdev, 2756 struct rtw89_pci_tx_ring *tx_ring) 2757 { 2758 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 2759 u8 *head = wd_ring->head; 2760 dma_addr_t dma = wd_ring->dma; 2761 u32 page_size = wd_ring->page_size; 2762 u32 page_num = wd_ring->page_num; 2763 u32 ring_sz = page_size * page_num; 2764 2765 dma_free_coherent(&pdev->dev, ring_sz, head, dma); 2766 wd_ring->head = NULL; 2767 } 2768 2769 static void rtw89_pci_free_tx_ring(struct rtw89_dev *rtwdev, 2770 struct pci_dev *pdev, 2771 struct rtw89_pci_tx_ring *tx_ring) 2772 { 2773 int ring_sz; 2774 u8 *head; 2775 dma_addr_t dma; 2776 2777 head = tx_ring->bd_ring.head; 2778 dma = tx_ring->bd_ring.dma; 2779 ring_sz = tx_ring->bd_ring.desc_size * tx_ring->bd_ring.len; 2780 dma_free_coherent(&pdev->dev, ring_sz, head, dma); 2781 2782 tx_ring->bd_ring.head = NULL; 2783 } 2784 2785 static void rtw89_pci_free_tx_rings(struct rtw89_dev *rtwdev, 2786 struct pci_dev *pdev) 2787 { 2788 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2789 const struct rtw89_pci_info *info = rtwdev->pci_info; 2790 struct rtw89_pci_tx_ring *tx_ring; 2791 int i; 2792 2793 for (i = 0; i < RTW89_TXCH_NUM; i++) { 2794 if (info->tx_dma_ch_mask & BIT(i)) 2795 continue; 2796 tx_ring = &rtwpci->tx_rings[i]; 2797 rtw89_pci_free_tx_wd_ring(rtwdev, pdev, tx_ring); 2798 rtw89_pci_free_tx_ring(rtwdev, pdev, tx_ring); 2799 } 2800 } 2801 2802 static void rtw89_pci_free_rx_ring(struct rtw89_dev *rtwdev, 2803 struct pci_dev *pdev, 2804 struct rtw89_pci_rx_ring *rx_ring) 2805 { 2806 struct rtw89_pci_rx_info *rx_info; 2807 struct sk_buff *skb; 2808 dma_addr_t dma; 2809 u32 buf_sz; 2810 u8 *head; 2811 int ring_sz = rx_ring->bd_ring.desc_size * rx_ring->bd_ring.len; 2812 int i; 2813 2814 buf_sz = rx_ring->buf_sz; 2815 for (i = 0; i < rx_ring->bd_ring.len; i++) { 2816 skb = rx_ring->buf[i]; 2817 if (!skb) 2818 continue; 2819 2820 rx_info = RTW89_PCI_RX_SKB_CB(skb); 2821 dma = rx_info->dma; 2822 dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE); 2823 dev_kfree_skb(skb); 2824 rx_ring->buf[i] = NULL; 2825 } 2826 2827 head = rx_ring->bd_ring.head; 2828 dma = rx_ring->bd_ring.dma; 2829 dma_free_coherent(&pdev->dev, ring_sz, head, dma); 2830 2831 rx_ring->bd_ring.head = NULL; 2832 } 2833 2834 static void rtw89_pci_free_rx_rings(struct rtw89_dev *rtwdev, 2835 struct pci_dev *pdev) 2836 { 2837 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2838 struct rtw89_pci_rx_ring *rx_ring; 2839 int i; 2840 2841 for (i = 0; i < RTW89_RXCH_NUM; i++) { 2842 rx_ring = &rtwpci->rx_rings[i]; 2843 rtw89_pci_free_rx_ring(rtwdev, pdev, rx_ring); 2844 } 2845 } 2846 2847 static void rtw89_pci_free_trx_rings(struct rtw89_dev *rtwdev, 2848 struct pci_dev *pdev) 2849 { 2850 rtw89_pci_free_rx_rings(rtwdev, pdev); 2851 rtw89_pci_free_tx_rings(rtwdev, pdev); 2852 } 2853 2854 static int rtw89_pci_init_rx_bd(struct rtw89_dev *rtwdev, struct pci_dev *pdev, 2855 struct rtw89_pci_rx_ring *rx_ring, 2856 struct sk_buff *skb, int buf_sz, u32 idx) 2857 { 2858 struct rtw89_pci_rx_info *rx_info; 2859 struct rtw89_pci_rx_bd_32 *rx_bd; 2860 dma_addr_t dma; 2861 2862 if (!skb) 2863 return -EINVAL; 2864 2865 dma = dma_map_single(&pdev->dev, skb->data, buf_sz, DMA_FROM_DEVICE); 2866 if (dma_mapping_error(&pdev->dev, dma)) 2867 return -EBUSY; 2868 2869 rx_info = RTW89_PCI_RX_SKB_CB(skb); 2870 rx_bd = RTW89_PCI_RX_BD(rx_ring, idx); 2871 2872 memset(rx_bd, 0, sizeof(*rx_bd)); 2873 rx_bd->buf_size = cpu_to_le16(buf_sz); 2874 rx_bd->dma = cpu_to_le32(dma); 2875 rx_info->dma = dma; 2876 2877 return 0; 2878 } 2879 2880 static int rtw89_pci_alloc_tx_wd_ring(struct rtw89_dev *rtwdev, 2881 struct pci_dev *pdev, 2882 struct rtw89_pci_tx_ring *tx_ring, 2883 enum rtw89_tx_channel txch) 2884 { 2885 struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring; 2886 struct rtw89_pci_tx_wd *txwd; 2887 dma_addr_t dma; 2888 dma_addr_t cur_paddr; 2889 u8 *head; 2890 u8 *cur_vaddr; 2891 u32 page_size = RTW89_PCI_TXWD_PAGE_SIZE; 2892 u32 page_num = RTW89_PCI_TXWD_NUM_MAX; 2893 u32 ring_sz = page_size * page_num; 2894 u32 page_offset; 2895 int i; 2896 2897 /* FWCMD queue doesn't use txwd as pages */ 2898 if (txch == RTW89_TXCH_CH12) 2899 return 0; 2900 2901 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); 2902 if (!head) 2903 return -ENOMEM; 2904 2905 INIT_LIST_HEAD(&wd_ring->free_pages); 2906 wd_ring->head = head; 2907 wd_ring->dma = dma; 2908 wd_ring->page_size = page_size; 2909 wd_ring->page_num = page_num; 2910 2911 page_offset = 0; 2912 for (i = 0; i < page_num; i++) { 2913 txwd = &wd_ring->pages[i]; 2914 cur_paddr = dma + page_offset; 2915 cur_vaddr = head + page_offset; 2916 2917 skb_queue_head_init(&txwd->queue); 2918 INIT_LIST_HEAD(&txwd->list); 2919 txwd->paddr = cur_paddr; 2920 txwd->vaddr = cur_vaddr; 2921 txwd->len = page_size; 2922 txwd->seq = i; 2923 rtw89_pci_enqueue_txwd(tx_ring, txwd); 2924 2925 page_offset += page_size; 2926 } 2927 2928 return 0; 2929 } 2930 2931 static int rtw89_pci_alloc_tx_ring(struct rtw89_dev *rtwdev, 2932 struct pci_dev *pdev, 2933 struct rtw89_pci_tx_ring *tx_ring, 2934 u32 desc_size, u32 len, 2935 enum rtw89_tx_channel txch) 2936 { 2937 const struct rtw89_pci_ch_dma_addr *txch_addr; 2938 int ring_sz = desc_size * len; 2939 u8 *head; 2940 dma_addr_t dma; 2941 int ret; 2942 2943 ret = rtw89_pci_alloc_tx_wd_ring(rtwdev, pdev, tx_ring, txch); 2944 if (ret) { 2945 rtw89_err(rtwdev, "failed to alloc txwd ring of txch %d\n", txch); 2946 goto err; 2947 } 2948 2949 ret = rtw89_pci_get_txch_addrs(rtwdev, txch, &txch_addr); 2950 if (ret) { 2951 rtw89_err(rtwdev, "failed to get address of txch %d", txch); 2952 goto err_free_wd_ring; 2953 } 2954 2955 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); 2956 if (!head) { 2957 ret = -ENOMEM; 2958 goto err_free_wd_ring; 2959 } 2960 2961 INIT_LIST_HEAD(&tx_ring->busy_pages); 2962 tx_ring->bd_ring.head = head; 2963 tx_ring->bd_ring.dma = dma; 2964 tx_ring->bd_ring.len = len; 2965 tx_ring->bd_ring.desc_size = desc_size; 2966 tx_ring->bd_ring.addr = *txch_addr; 2967 tx_ring->bd_ring.wp = 0; 2968 tx_ring->bd_ring.rp = 0; 2969 tx_ring->txch = txch; 2970 2971 return 0; 2972 2973 err_free_wd_ring: 2974 rtw89_pci_free_tx_wd_ring(rtwdev, pdev, tx_ring); 2975 err: 2976 return ret; 2977 } 2978 2979 static int rtw89_pci_alloc_tx_rings(struct rtw89_dev *rtwdev, 2980 struct pci_dev *pdev) 2981 { 2982 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 2983 const struct rtw89_pci_info *info = rtwdev->pci_info; 2984 struct rtw89_pci_tx_ring *tx_ring; 2985 u32 desc_size; 2986 u32 len; 2987 u32 i, tx_allocated; 2988 int ret; 2989 2990 for (i = 0; i < RTW89_TXCH_NUM; i++) { 2991 if (info->tx_dma_ch_mask & BIT(i)) 2992 continue; 2993 tx_ring = &rtwpci->tx_rings[i]; 2994 desc_size = sizeof(struct rtw89_pci_tx_bd_32); 2995 len = RTW89_PCI_TXBD_NUM_MAX; 2996 ret = rtw89_pci_alloc_tx_ring(rtwdev, pdev, tx_ring, 2997 desc_size, len, i); 2998 if (ret) { 2999 rtw89_err(rtwdev, "failed to alloc tx ring %d\n", i); 3000 goto err_free; 3001 } 3002 } 3003 3004 return 0; 3005 3006 err_free: 3007 tx_allocated = i; 3008 for (i = 0; i < tx_allocated; i++) { 3009 tx_ring = &rtwpci->tx_rings[i]; 3010 rtw89_pci_free_tx_ring(rtwdev, pdev, tx_ring); 3011 } 3012 3013 return ret; 3014 } 3015 3016 static int rtw89_pci_alloc_rx_ring(struct rtw89_dev *rtwdev, 3017 struct pci_dev *pdev, 3018 struct rtw89_pci_rx_ring *rx_ring, 3019 u32 desc_size, u32 len, u32 rxch) 3020 { 3021 const struct rtw89_pci_ch_dma_addr *rxch_addr; 3022 struct sk_buff *skb; 3023 u8 *head; 3024 dma_addr_t dma; 3025 int ring_sz = desc_size * len; 3026 int buf_sz = RTW89_PCI_RX_BUF_SIZE; 3027 int i, allocated; 3028 int ret; 3029 3030 ret = rtw89_pci_get_rxch_addrs(rtwdev, rxch, &rxch_addr); 3031 if (ret) { 3032 rtw89_err(rtwdev, "failed to get address of rxch %d", rxch); 3033 return ret; 3034 } 3035 3036 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); 3037 if (!head) { 3038 ret = -ENOMEM; 3039 goto err; 3040 } 3041 3042 rx_ring->bd_ring.head = head; 3043 rx_ring->bd_ring.dma = dma; 3044 rx_ring->bd_ring.len = len; 3045 rx_ring->bd_ring.desc_size = desc_size; 3046 rx_ring->bd_ring.addr = *rxch_addr; 3047 rx_ring->bd_ring.wp = 0; 3048 rx_ring->bd_ring.rp = 0; 3049 rx_ring->buf_sz = buf_sz; 3050 rx_ring->diliver_skb = NULL; 3051 rx_ring->diliver_desc.ready = false; 3052 3053 for (i = 0; i < len; i++) { 3054 skb = dev_alloc_skb(buf_sz); 3055 if (!skb) { 3056 ret = -ENOMEM; 3057 goto err_free; 3058 } 3059 3060 memset(skb->data, 0, buf_sz); 3061 rx_ring->buf[i] = skb; 3062 ret = rtw89_pci_init_rx_bd(rtwdev, pdev, rx_ring, skb, 3063 buf_sz, i); 3064 if (ret) { 3065 rtw89_err(rtwdev, "failed to init rx buf %d\n", i); 3066 dev_kfree_skb_any(skb); 3067 rx_ring->buf[i] = NULL; 3068 goto err_free; 3069 } 3070 } 3071 3072 return 0; 3073 3074 err_free: 3075 allocated = i; 3076 for (i = 0; i < allocated; i++) { 3077 skb = rx_ring->buf[i]; 3078 if (!skb) 3079 continue; 3080 dma = *((dma_addr_t *)skb->cb); 3081 dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE); 3082 dev_kfree_skb(skb); 3083 rx_ring->buf[i] = NULL; 3084 } 3085 3086 head = rx_ring->bd_ring.head; 3087 dma = rx_ring->bd_ring.dma; 3088 dma_free_coherent(&pdev->dev, ring_sz, head, dma); 3089 3090 rx_ring->bd_ring.head = NULL; 3091 err: 3092 return ret; 3093 } 3094 3095 static int rtw89_pci_alloc_rx_rings(struct rtw89_dev *rtwdev, 3096 struct pci_dev *pdev) 3097 { 3098 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3099 struct rtw89_pci_rx_ring *rx_ring; 3100 u32 desc_size; 3101 u32 len; 3102 int i, rx_allocated; 3103 int ret; 3104 3105 for (i = 0; i < RTW89_RXCH_NUM; i++) { 3106 rx_ring = &rtwpci->rx_rings[i]; 3107 desc_size = sizeof(struct rtw89_pci_rx_bd_32); 3108 len = RTW89_PCI_RXBD_NUM_MAX; 3109 ret = rtw89_pci_alloc_rx_ring(rtwdev, pdev, rx_ring, 3110 desc_size, len, i); 3111 if (ret) { 3112 rtw89_err(rtwdev, "failed to alloc rx ring %d\n", i); 3113 goto err_free; 3114 } 3115 } 3116 3117 return 0; 3118 3119 err_free: 3120 rx_allocated = i; 3121 for (i = 0; i < rx_allocated; i++) { 3122 rx_ring = &rtwpci->rx_rings[i]; 3123 rtw89_pci_free_rx_ring(rtwdev, pdev, rx_ring); 3124 } 3125 3126 return ret; 3127 } 3128 3129 static int rtw89_pci_alloc_trx_rings(struct rtw89_dev *rtwdev, 3130 struct pci_dev *pdev) 3131 { 3132 int ret; 3133 3134 ret = rtw89_pci_alloc_tx_rings(rtwdev, pdev); 3135 if (ret) { 3136 rtw89_err(rtwdev, "failed to alloc dma tx rings\n"); 3137 goto err; 3138 } 3139 3140 ret = rtw89_pci_alloc_rx_rings(rtwdev, pdev); 3141 if (ret) { 3142 rtw89_err(rtwdev, "failed to alloc dma rx rings\n"); 3143 goto err_free_tx_rings; 3144 } 3145 3146 return 0; 3147 3148 err_free_tx_rings: 3149 rtw89_pci_free_tx_rings(rtwdev, pdev); 3150 err: 3151 return ret; 3152 } 3153 3154 static void rtw89_pci_h2c_init(struct rtw89_dev *rtwdev, 3155 struct rtw89_pci *rtwpci) 3156 { 3157 skb_queue_head_init(&rtwpci->h2c_queue); 3158 skb_queue_head_init(&rtwpci->h2c_release_queue); 3159 } 3160 3161 static int rtw89_pci_setup_resource(struct rtw89_dev *rtwdev, 3162 struct pci_dev *pdev) 3163 { 3164 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3165 int ret; 3166 3167 ret = rtw89_pci_setup_mapping(rtwdev, pdev); 3168 if (ret) { 3169 rtw89_err(rtwdev, "failed to setup pci mapping\n"); 3170 goto err; 3171 } 3172 3173 ret = rtw89_pci_alloc_trx_rings(rtwdev, pdev); 3174 if (ret) { 3175 rtw89_err(rtwdev, "failed to alloc pci trx rings\n"); 3176 goto err_pci_unmap; 3177 } 3178 3179 rtw89_pci_h2c_init(rtwdev, rtwpci); 3180 3181 spin_lock_init(&rtwpci->irq_lock); 3182 spin_lock_init(&rtwpci->trx_lock); 3183 3184 return 0; 3185 3186 err_pci_unmap: 3187 rtw89_pci_clear_mapping(rtwdev, pdev); 3188 err: 3189 return ret; 3190 } 3191 3192 static void rtw89_pci_clear_resource(struct rtw89_dev *rtwdev, 3193 struct pci_dev *pdev) 3194 { 3195 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3196 3197 rtw89_pci_free_trx_rings(rtwdev, pdev); 3198 rtw89_pci_clear_mapping(rtwdev, pdev); 3199 rtw89_pci_release_fwcmd(rtwdev, rtwpci, 3200 skb_queue_len(&rtwpci->h2c_queue), true); 3201 } 3202 3203 void rtw89_pci_config_intr_mask(struct rtw89_dev *rtwdev) 3204 { 3205 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3206 3207 rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | 0; 3208 3209 if (rtwpci->under_recovery) { 3210 rtwpci->intrs[0] = B_AX_HS0ISR_IND_INT_EN; 3211 rtwpci->intrs[1] = 0; 3212 } else { 3213 rtwpci->intrs[0] = B_AX_TXDMA_STUCK_INT_EN | 3214 B_AX_RXDMA_INT_EN | 3215 B_AX_RXP1DMA_INT_EN | 3216 B_AX_RPQDMA_INT_EN | 3217 B_AX_RXDMA_STUCK_INT_EN | 3218 B_AX_RDU_INT_EN | 3219 B_AX_RPQBD_FULL_INT_EN | 3220 B_AX_HS0ISR_IND_INT_EN; 3221 3222 rtwpci->intrs[1] = B_AX_HC10ISR_IND_INT_EN; 3223 } 3224 } 3225 EXPORT_SYMBOL(rtw89_pci_config_intr_mask); 3226 3227 static void rtw89_pci_recovery_intr_mask_v1(struct rtw89_dev *rtwdev) 3228 { 3229 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3230 3231 rtwpci->ind_intrs = B_AX_HS0ISR_IND_INT_EN; 3232 rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | B_AX_WDT_TIMEOUT_INT_EN; 3233 rtwpci->intrs[0] = 0; 3234 rtwpci->intrs[1] = 0; 3235 } 3236 3237 static void rtw89_pci_default_intr_mask_v1(struct rtw89_dev *rtwdev) 3238 { 3239 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3240 3241 rtwpci->ind_intrs = B_AX_HCI_AXIDMA_INT_EN | 3242 B_AX_HS1ISR_IND_INT_EN | 3243 B_AX_HS0ISR_IND_INT_EN; 3244 rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | B_AX_WDT_TIMEOUT_INT_EN; 3245 rtwpci->intrs[0] = B_AX_TXDMA_STUCK_INT_EN | 3246 B_AX_RXDMA_INT_EN | 3247 B_AX_RXP1DMA_INT_EN | 3248 B_AX_RPQDMA_INT_EN | 3249 B_AX_RXDMA_STUCK_INT_EN | 3250 B_AX_RDU_INT_EN | 3251 B_AX_RPQBD_FULL_INT_EN; 3252 rtwpci->intrs[1] = B_AX_GPIO18_INT_EN; 3253 } 3254 3255 static void rtw89_pci_low_power_intr_mask_v1(struct rtw89_dev *rtwdev) 3256 { 3257 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3258 3259 rtwpci->ind_intrs = B_AX_HS1ISR_IND_INT_EN | 3260 B_AX_HS0ISR_IND_INT_EN; 3261 rtwpci->halt_c2h_intrs = B_AX_HALT_C2H_INT_EN | B_AX_WDT_TIMEOUT_INT_EN; 3262 rtwpci->intrs[0] = 0; 3263 rtwpci->intrs[1] = B_AX_GPIO18_INT_EN; 3264 } 3265 3266 void rtw89_pci_config_intr_mask_v1(struct rtw89_dev *rtwdev) 3267 { 3268 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3269 3270 if (rtwpci->under_recovery) 3271 rtw89_pci_recovery_intr_mask_v1(rtwdev); 3272 else if (rtwpci->low_power) 3273 rtw89_pci_low_power_intr_mask_v1(rtwdev); 3274 else 3275 rtw89_pci_default_intr_mask_v1(rtwdev); 3276 } 3277 EXPORT_SYMBOL(rtw89_pci_config_intr_mask_v1); 3278 3279 static int rtw89_pci_request_irq(struct rtw89_dev *rtwdev, 3280 struct pci_dev *pdev) 3281 { 3282 unsigned long flags = 0; 3283 int ret; 3284 3285 flags |= PCI_IRQ_LEGACY | PCI_IRQ_MSI; 3286 ret = pci_alloc_irq_vectors(pdev, 1, 1, flags); 3287 if (ret < 0) { 3288 rtw89_err(rtwdev, "failed to alloc irq vectors, ret %d\n", ret); 3289 goto err; 3290 } 3291 3292 ret = devm_request_threaded_irq(rtwdev->dev, pdev->irq, 3293 rtw89_pci_interrupt_handler, 3294 rtw89_pci_interrupt_threadfn, 3295 IRQF_SHARED, KBUILD_MODNAME, rtwdev); 3296 if (ret) { 3297 rtw89_err(rtwdev, "failed to request threaded irq\n"); 3298 goto err_free_vector; 3299 } 3300 3301 rtw89_chip_config_intr_mask(rtwdev, RTW89_PCI_INTR_MASK_RESET); 3302 3303 return 0; 3304 3305 err_free_vector: 3306 pci_free_irq_vectors(pdev); 3307 err: 3308 return ret; 3309 } 3310 3311 static void rtw89_pci_free_irq(struct rtw89_dev *rtwdev, 3312 struct pci_dev *pdev) 3313 { 3314 devm_free_irq(rtwdev->dev, pdev->irq, rtwdev); 3315 pci_free_irq_vectors(pdev); 3316 } 3317 3318 static u16 gray_code_to_bin(u16 gray_code, u32 bit_num) 3319 { 3320 u16 bin = 0, gray_bit; 3321 u32 bit_idx; 3322 3323 for (bit_idx = 0; bit_idx < bit_num; bit_idx++) { 3324 gray_bit = (gray_code >> bit_idx) & 0x1; 3325 if (bit_num - bit_idx > 1) 3326 gray_bit ^= (gray_code >> (bit_idx + 1)) & 0x1; 3327 bin |= (gray_bit << bit_idx); 3328 } 3329 3330 return bin; 3331 } 3332 3333 static int rtw89_pci_filter_out(struct rtw89_dev *rtwdev) 3334 { 3335 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3336 struct pci_dev *pdev = rtwpci->pdev; 3337 u16 val16, filter_out_val; 3338 u32 val, phy_offset; 3339 int ret; 3340 3341 if (rtwdev->chip->chip_id != RTL8852C) 3342 return 0; 3343 3344 val = rtw89_read32_mask(rtwdev, R_AX_PCIE_MIX_CFG_V1, B_AX_ASPM_CTRL_MASK); 3345 if (val == B_AX_ASPM_CTRL_L1) 3346 return 0; 3347 3348 ret = pci_read_config_dword(pdev, RTW89_PCIE_L1_STS_V1, &val); 3349 if (ret) 3350 return ret; 3351 3352 val = FIELD_GET(RTW89_BCFG_LINK_SPEED_MASK, val); 3353 if (val == RTW89_PCIE_GEN1_SPEED) { 3354 phy_offset = R_RAC_DIRECT_OFFSET_G1; 3355 } else if (val == RTW89_PCIE_GEN2_SPEED) { 3356 phy_offset = R_RAC_DIRECT_OFFSET_G2; 3357 val16 = rtw89_read16(rtwdev, phy_offset + RAC_ANA10 * RAC_MULT); 3358 rtw89_write16_set(rtwdev, phy_offset + RAC_ANA10 * RAC_MULT, 3359 val16 | B_PCIE_BIT_PINOUT_DIS); 3360 rtw89_write16_set(rtwdev, phy_offset + RAC_ANA19 * RAC_MULT, 3361 val16 & ~B_PCIE_BIT_RD_SEL); 3362 3363 val16 = rtw89_read16_mask(rtwdev, 3364 phy_offset + RAC_ANA1F * RAC_MULT, 3365 FILTER_OUT_EQ_MASK); 3366 val16 = gray_code_to_bin(val16, hweight16(val16)); 3367 filter_out_val = rtw89_read16(rtwdev, phy_offset + RAC_ANA24 * 3368 RAC_MULT); 3369 filter_out_val &= ~REG_FILTER_OUT_MASK; 3370 filter_out_val |= FIELD_PREP(REG_FILTER_OUT_MASK, val16); 3371 3372 rtw89_write16(rtwdev, phy_offset + RAC_ANA24 * RAC_MULT, 3373 filter_out_val); 3374 rtw89_write16_set(rtwdev, phy_offset + RAC_ANA0A * RAC_MULT, 3375 B_BAC_EQ_SEL); 3376 rtw89_write16_set(rtwdev, 3377 R_RAC_DIRECT_OFFSET_G1 + RAC_ANA0C * RAC_MULT, 3378 B_PCIE_BIT_PSAVE); 3379 } else { 3380 return -EOPNOTSUPP; 3381 } 3382 rtw89_write16_set(rtwdev, phy_offset + RAC_ANA0C * RAC_MULT, 3383 B_PCIE_BIT_PSAVE); 3384 3385 return 0; 3386 } 3387 3388 static void rtw89_pci_clkreq_set(struct rtw89_dev *rtwdev, bool enable) 3389 { 3390 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3391 int ret; 3392 3393 if (rtw89_pci_disable_clkreq) 3394 return; 3395 3396 ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_CLK_CTRL, 3397 PCIE_CLKDLY_HW_30US); 3398 if (ret) 3399 rtw89_err(rtwdev, "failed to set CLKREQ Delay\n"); 3400 3401 if (chip_id == RTL8852A || chip_id == RTL8852B) { 3402 if (enable) 3403 ret = rtw89_pci_config_byte_set(rtwdev, 3404 RTW89_PCIE_L1_CTRL, 3405 RTW89_PCIE_BIT_CLK); 3406 else 3407 ret = rtw89_pci_config_byte_clr(rtwdev, 3408 RTW89_PCIE_L1_CTRL, 3409 RTW89_PCIE_BIT_CLK); 3410 if (ret) 3411 rtw89_err(rtwdev, "failed to %s CLKREQ_L1, ret=%d", 3412 enable ? "set" : "unset", ret); 3413 } else if (chip_id == RTL8852C) { 3414 rtw89_write32_set(rtwdev, R_AX_PCIE_LAT_CTRL, 3415 B_AX_CLK_REQ_SEL_OPT | B_AX_CLK_REQ_SEL); 3416 if (enable) 3417 rtw89_write32_set(rtwdev, R_AX_L1_CLK_CTRL, 3418 B_AX_CLK_REQ_N); 3419 else 3420 rtw89_write32_clr(rtwdev, R_AX_L1_CLK_CTRL, 3421 B_AX_CLK_REQ_N); 3422 } 3423 } 3424 3425 static void rtw89_pci_aspm_set(struct rtw89_dev *rtwdev, bool enable) 3426 { 3427 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3428 u8 value = 0; 3429 int ret; 3430 3431 if (rtw89_pci_disable_aspm_l1) 3432 return; 3433 3434 ret = rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_ASPM_CTRL, &value); 3435 if (ret) 3436 rtw89_err(rtwdev, "failed to read ASPM Delay\n"); 3437 3438 value &= ~(RTW89_L1DLY_MASK | RTW89_L0DLY_MASK); 3439 value |= FIELD_PREP(RTW89_L1DLY_MASK, PCIE_L1DLY_16US) | 3440 FIELD_PREP(RTW89_L0DLY_MASK, PCIE_L0SDLY_4US); 3441 3442 ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_ASPM_CTRL, value); 3443 if (ret) 3444 rtw89_err(rtwdev, "failed to read ASPM Delay\n"); 3445 3446 if (chip_id == RTL8852A || chip_id == RTL8852B) { 3447 if (enable) 3448 ret = rtw89_pci_config_byte_set(rtwdev, 3449 RTW89_PCIE_L1_CTRL, 3450 RTW89_PCIE_BIT_L1); 3451 else 3452 ret = rtw89_pci_config_byte_clr(rtwdev, 3453 RTW89_PCIE_L1_CTRL, 3454 RTW89_PCIE_BIT_L1); 3455 } else if (chip_id == RTL8852C) { 3456 if (enable) 3457 rtw89_write32_set(rtwdev, R_AX_PCIE_MIX_CFG_V1, 3458 B_AX_ASPM_CTRL_L1); 3459 else 3460 rtw89_write32_clr(rtwdev, R_AX_PCIE_MIX_CFG_V1, 3461 B_AX_ASPM_CTRL_L1); 3462 } 3463 if (ret) 3464 rtw89_err(rtwdev, "failed to %s ASPM L1, ret=%d", 3465 enable ? "set" : "unset", ret); 3466 } 3467 3468 static void rtw89_pci_recalc_int_mit(struct rtw89_dev *rtwdev) 3469 { 3470 struct rtw89_traffic_stats *stats = &rtwdev->stats; 3471 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 3472 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 3473 u32 val = 0; 3474 3475 if (!rtwdev->scanning && 3476 (tx_tfc_lv >= RTW89_TFC_HIGH || rx_tfc_lv >= RTW89_TFC_HIGH)) 3477 val = B_AX_RXMIT_RXP2_SEL | B_AX_RXMIT_RXP1_SEL | 3478 FIELD_PREP(B_AX_RXCOUNTER_MATCH_MASK, RTW89_PCI_RXBD_NUM_MAX / 2) | 3479 FIELD_PREP(B_AX_RXTIMER_UNIT_MASK, AX_RXTIMER_UNIT_64US) | 3480 FIELD_PREP(B_AX_RXTIMER_MATCH_MASK, 2048 / 64); 3481 3482 rtw89_write32(rtwdev, R_AX_INT_MIT_RX, val); 3483 } 3484 3485 static void rtw89_pci_link_cfg(struct rtw89_dev *rtwdev) 3486 { 3487 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3488 struct pci_dev *pdev = rtwpci->pdev; 3489 u16 link_ctrl; 3490 int ret; 3491 3492 /* Though there is standard PCIE configuration space to set the 3493 * link control register, but by Realtek's design, driver should 3494 * check if host supports CLKREQ/ASPM to enable the HW module. 3495 * 3496 * These functions are implemented by two HW modules associated, 3497 * one is responsible to access PCIE configuration space to 3498 * follow the host settings, and another is in charge of doing 3499 * CLKREQ/ASPM mechanisms, it is default disabled. Because sometimes 3500 * the host does not support it, and due to some reasons or wrong 3501 * settings (ex. CLKREQ# not Bi-Direction), it could lead to device 3502 * loss if HW misbehaves on the link. 3503 * 3504 * Hence it's designed that driver should first check the PCIE 3505 * configuration space is sync'ed and enabled, then driver can turn 3506 * on the other module that is actually working on the mechanism. 3507 */ 3508 ret = pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &link_ctrl); 3509 if (ret) { 3510 rtw89_err(rtwdev, "failed to read PCI cap, ret=%d\n", ret); 3511 return; 3512 } 3513 3514 if (link_ctrl & PCI_EXP_LNKCTL_CLKREQ_EN) 3515 rtw89_pci_clkreq_set(rtwdev, true); 3516 3517 if (link_ctrl & PCI_EXP_LNKCTL_ASPM_L1) 3518 rtw89_pci_aspm_set(rtwdev, true); 3519 } 3520 3521 static void rtw89_pci_l1ss_set(struct rtw89_dev *rtwdev, bool enable) 3522 { 3523 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3524 int ret; 3525 3526 if (chip_id == RTL8852A || chip_id == RTL8852B) { 3527 if (enable) 3528 ret = rtw89_pci_config_byte_set(rtwdev, 3529 RTW89_PCIE_TIMER_CTRL, 3530 RTW89_PCIE_BIT_L1SUB); 3531 else 3532 ret = rtw89_pci_config_byte_clr(rtwdev, 3533 RTW89_PCIE_TIMER_CTRL, 3534 RTW89_PCIE_BIT_L1SUB); 3535 if (ret) 3536 rtw89_err(rtwdev, "failed to %s L1SS, ret=%d", 3537 enable ? "set" : "unset", ret); 3538 } else if (chip_id == RTL8852C) { 3539 ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_L1SS_STS_V1, 3540 RTW89_PCIE_BIT_ASPM_L11 | 3541 RTW89_PCIE_BIT_PCI_L11); 3542 if (ret) 3543 rtw89_warn(rtwdev, "failed to unset ASPM L1.1, ret=%d", ret); 3544 if (enable) 3545 rtw89_write32_clr(rtwdev, R_AX_PCIE_MIX_CFG_V1, 3546 B_AX_L1SUB_DISABLE); 3547 else 3548 rtw89_write32_set(rtwdev, R_AX_PCIE_MIX_CFG_V1, 3549 B_AX_L1SUB_DISABLE); 3550 } 3551 } 3552 3553 static void rtw89_pci_l1ss_cfg(struct rtw89_dev *rtwdev) 3554 { 3555 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3556 struct pci_dev *pdev = rtwpci->pdev; 3557 u32 l1ss_cap_ptr, l1ss_ctrl; 3558 3559 if (rtw89_pci_disable_l1ss) 3560 return; 3561 3562 l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); 3563 if (!l1ss_cap_ptr) 3564 return; 3565 3566 pci_read_config_dword(pdev, l1ss_cap_ptr + PCI_L1SS_CTL1, &l1ss_ctrl); 3567 3568 if (l1ss_ctrl & PCI_L1SS_CTL1_L1SS_MASK) 3569 rtw89_pci_l1ss_set(rtwdev, true); 3570 } 3571 3572 static int rtw89_pci_poll_io_idle(struct rtw89_dev *rtwdev) 3573 { 3574 int ret = 0; 3575 u32 sts; 3576 u32 busy = B_AX_PCIEIO_BUSY | B_AX_PCIEIO_TX_BUSY | B_AX_PCIEIO_RX_BUSY; 3577 3578 ret = read_poll_timeout_atomic(rtw89_read32, sts, (sts & busy) == 0x0, 3579 10, 1000, false, rtwdev, 3580 R_AX_PCIE_DMA_BUSY1); 3581 if (ret) { 3582 rtw89_err(rtwdev, "pci dmach busy1 0x%X\n", 3583 rtw89_read32(rtwdev, R_AX_PCIE_DMA_BUSY1)); 3584 return -EINVAL; 3585 } 3586 return ret; 3587 } 3588 3589 static int rtw89_pci_lv1rst_stop_dma(struct rtw89_dev *rtwdev) 3590 { 3591 u32 val; 3592 int ret; 3593 3594 if (rtwdev->chip->chip_id == RTL8852C) 3595 return 0; 3596 3597 rtw89_pci_ctrl_dma_all(rtwdev, false); 3598 ret = rtw89_pci_poll_io_idle(rtwdev); 3599 if (ret) { 3600 val = rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG); 3601 rtw89_debug(rtwdev, RTW89_DBG_HCI, 3602 "[PCIe] poll_io_idle fail, before 0x%08x: 0x%08x\n", 3603 R_AX_DBG_ERR_FLAG, val); 3604 if (val & B_AX_TX_STUCK || val & B_AX_PCIE_TXBD_LEN0) 3605 rtw89_mac_ctrl_hci_dma_tx(rtwdev, false); 3606 if (val & B_AX_RX_STUCK) 3607 rtw89_mac_ctrl_hci_dma_rx(rtwdev, false); 3608 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3609 ret = rtw89_pci_poll_io_idle(rtwdev); 3610 val = rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG); 3611 rtw89_debug(rtwdev, RTW89_DBG_HCI, 3612 "[PCIe] poll_io_idle fail, after 0x%08x: 0x%08x\n", 3613 R_AX_DBG_ERR_FLAG, val); 3614 } 3615 3616 return ret; 3617 } 3618 3619 3620 3621 static int rtw89_pci_rst_bdram(struct rtw89_dev *rtwdev) 3622 { 3623 int ret = 0; 3624 u32 val32, sts; 3625 3626 val32 = B_AX_RST_BDRAM; 3627 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, val32); 3628 3629 ret = read_poll_timeout_atomic(rtw89_read32, sts, 3630 (sts & B_AX_RST_BDRAM) == 0x0, 1, 100, 3631 true, rtwdev, R_AX_PCIE_INIT_CFG1); 3632 return ret; 3633 } 3634 3635 static int rtw89_pci_lv1rst_start_dma(struct rtw89_dev *rtwdev) 3636 { 3637 u32 ret; 3638 3639 if (rtwdev->chip->chip_id == RTL8852C) 3640 return 0; 3641 3642 rtw89_mac_ctrl_hci_dma_trx(rtwdev, false); 3643 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3644 rtw89_pci_clr_idx_all(rtwdev); 3645 3646 ret = rtw89_pci_rst_bdram(rtwdev); 3647 if (ret) 3648 return ret; 3649 3650 rtw89_pci_ctrl_dma_all(rtwdev, true); 3651 return ret; 3652 } 3653 3654 static int rtw89_pci_ops_mac_lv1_recovery(struct rtw89_dev *rtwdev, 3655 enum rtw89_lv1_rcvy_step step) 3656 { 3657 int ret; 3658 3659 switch (step) { 3660 case RTW89_LV1_RCVY_STEP_1: 3661 ret = rtw89_pci_lv1rst_stop_dma(rtwdev); 3662 if (ret) 3663 rtw89_err(rtwdev, "lv1 rcvy pci stop dma fail\n"); 3664 3665 break; 3666 3667 case RTW89_LV1_RCVY_STEP_2: 3668 ret = rtw89_pci_lv1rst_start_dma(rtwdev); 3669 if (ret) 3670 rtw89_err(rtwdev, "lv1 rcvy pci start dma fail\n"); 3671 break; 3672 3673 default: 3674 return -EINVAL; 3675 } 3676 3677 return ret; 3678 } 3679 3680 static void rtw89_pci_ops_dump_err_status(struct rtw89_dev *rtwdev) 3681 { 3682 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX =0x%08x\n", 3683 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 3684 rtw89_info(rtwdev, "R_AX_DBG_ERR_FLAG=0x%08x\n", 3685 rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG)); 3686 rtw89_info(rtwdev, "R_AX_LBC_WATCHDOG=0x%08x\n", 3687 rtw89_read32(rtwdev, R_AX_LBC_WATCHDOG)); 3688 } 3689 3690 static int rtw89_pci_napi_poll(struct napi_struct *napi, int budget) 3691 { 3692 struct rtw89_dev *rtwdev = container_of(napi, struct rtw89_dev, napi); 3693 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; 3694 unsigned long flags; 3695 int work_done; 3696 3697 rtwdev->napi_budget_countdown = budget; 3698 3699 rtw89_pci_clear_isr0(rtwdev, B_AX_RPQDMA_INT | B_AX_RPQBD_FULL_INT); 3700 work_done = rtw89_pci_poll_rpq_dma(rtwdev, rtwpci, rtwdev->napi_budget_countdown); 3701 if (work_done == budget) 3702 return budget; 3703 3704 rtw89_pci_clear_isr0(rtwdev, B_AX_RXP1DMA_INT | B_AX_RXDMA_INT | B_AX_RDU_INT); 3705 work_done += rtw89_pci_poll_rxq_dma(rtwdev, rtwpci, rtwdev->napi_budget_countdown); 3706 if (work_done < budget && napi_complete_done(napi, work_done)) { 3707 spin_lock_irqsave(&rtwpci->irq_lock, flags); 3708 if (likely(rtwpci->running)) 3709 rtw89_chip_enable_intr(rtwdev, rtwpci); 3710 spin_unlock_irqrestore(&rtwpci->irq_lock, flags); 3711 } 3712 3713 return work_done; 3714 } 3715 3716 static int __maybe_unused rtw89_pci_suspend(struct device *dev) 3717 { 3718 struct ieee80211_hw *hw = dev_get_drvdata(dev); 3719 struct rtw89_dev *rtwdev = hw->priv; 3720 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3721 3722 rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); 3723 rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST); 3724 rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); 3725 if (chip_id == RTL8852A || chip_id == RTL8852B) { 3726 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, 3727 B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); 3728 rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, 3729 B_AX_PCIE_PERST_KEEP_REG | B_AX_PCIE_TRAIN_KEEP_REG); 3730 } else { 3731 rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL_V1, 3732 B_AX_CMAC_EXIT_L1_EN | B_AX_DMAC0_EXIT_L1_EN); 3733 } 3734 3735 return 0; 3736 } 3737 3738 static void rtw89_pci_l2_hci_ldo(struct rtw89_dev *rtwdev) 3739 { 3740 if (rtwdev->chip->chip_id == RTL8852C) 3741 return; 3742 3743 /* Hardware need write the reg twice to ensure the setting work */ 3744 rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_RST_MSTATE, 3745 RTW89_PCIE_BIT_CFG_RST_MSTATE); 3746 rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_RST_MSTATE, 3747 RTW89_PCIE_BIT_CFG_RST_MSTATE); 3748 } 3749 3750 static int __maybe_unused rtw89_pci_resume(struct device *dev) 3751 { 3752 struct ieee80211_hw *hw = dev_get_drvdata(dev); 3753 struct rtw89_dev *rtwdev = hw->priv; 3754 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3755 3756 rtw89_write32_set(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); 3757 rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST); 3758 rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_WLOCK_1C_BIT6); 3759 if (chip_id == RTL8852A || chip_id == RTL8852B) { 3760 rtw89_write32_set(rtwdev, R_AX_SYS_SDIO_CTRL, 3761 B_AX_PCIE_DIS_L2_CTRL_LDO_HCI); 3762 rtw89_write32_clr(rtwdev, R_AX_PCIE_INIT_CFG1, 3763 B_AX_PCIE_PERST_KEEP_REG | B_AX_PCIE_TRAIN_KEEP_REG); 3764 } else { 3765 rtw89_write32_set(rtwdev, R_AX_PCIE_PS_CTRL_V1, 3766 B_AX_CMAC_EXIT_L1_EN | B_AX_DMAC0_EXIT_L1_EN); 3767 rtw89_write32_clr(rtwdev, R_AX_PCIE_PS_CTRL_V1, 3768 B_AX_SEL_REQ_ENTR_L1); 3769 } 3770 rtw89_pci_l2_hci_ldo(rtwdev); 3771 rtw89_pci_filter_out(rtwdev); 3772 rtw89_pci_link_cfg(rtwdev); 3773 rtw89_pci_l1ss_cfg(rtwdev); 3774 3775 return 0; 3776 } 3777 3778 SIMPLE_DEV_PM_OPS(rtw89_pm_ops, rtw89_pci_suspend, rtw89_pci_resume); 3779 EXPORT_SYMBOL(rtw89_pm_ops); 3780 3781 static const struct rtw89_hci_ops rtw89_pci_ops = { 3782 .tx_write = rtw89_pci_ops_tx_write, 3783 .tx_kick_off = rtw89_pci_ops_tx_kick_off, 3784 .flush_queues = rtw89_pci_ops_flush_queues, 3785 .reset = rtw89_pci_ops_reset, 3786 .start = rtw89_pci_ops_start, 3787 .stop = rtw89_pci_ops_stop, 3788 .pause = rtw89_pci_ops_pause, 3789 .switch_mode = rtw89_pci_ops_switch_mode, 3790 .recalc_int_mit = rtw89_pci_recalc_int_mit, 3791 3792 .read8 = rtw89_pci_ops_read8, 3793 .read16 = rtw89_pci_ops_read16, 3794 .read32 = rtw89_pci_ops_read32, 3795 .write8 = rtw89_pci_ops_write8, 3796 .write16 = rtw89_pci_ops_write16, 3797 .write32 = rtw89_pci_ops_write32, 3798 3799 .mac_pre_init = rtw89_pci_ops_mac_pre_init, 3800 .mac_post_init = rtw89_pci_ops_mac_post_init, 3801 .deinit = rtw89_pci_ops_deinit, 3802 3803 .check_and_reclaim_tx_resource = rtw89_pci_check_and_reclaim_tx_resource, 3804 .mac_lv1_rcvy = rtw89_pci_ops_mac_lv1_recovery, 3805 .dump_err_status = rtw89_pci_ops_dump_err_status, 3806 .napi_poll = rtw89_pci_napi_poll, 3807 3808 .recovery_start = rtw89_pci_ops_recovery_start, 3809 .recovery_complete = rtw89_pci_ops_recovery_complete, 3810 3811 .ctrl_txdma_ch = rtw89_pci_ctrl_txdma_ch_pcie, 3812 .ctrl_txdma_fw_ch = rtw89_pci_ctrl_txdma_fw_ch_pcie, 3813 .ctrl_trxhci = rtw89_pci_ctrl_dma_trx, 3814 .poll_txdma_ch = rtw89_poll_txdma_ch_idle_pcie, 3815 .clr_idx_all = rtw89_pci_clr_idx_all, 3816 .clear = rtw89_pci_clear_resource, 3817 .disable_intr = rtw89_pci_disable_intr_lock, 3818 .enable_intr = rtw89_pci_enable_intr_lock, 3819 .rst_bdram = rtw89_pci_rst_bdram_pcie, 3820 }; 3821 3822 int rtw89_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3823 { 3824 struct rtw89_dev *rtwdev; 3825 const struct rtw89_driver_info *info; 3826 const struct rtw89_pci_info *pci_info; 3827 int ret; 3828 3829 info = (const struct rtw89_driver_info *)id->driver_data; 3830 3831 rtwdev = rtw89_alloc_ieee80211_hw(&pdev->dev, 3832 sizeof(struct rtw89_pci), 3833 info->chip); 3834 if (!rtwdev) { 3835 dev_err(&pdev->dev, "failed to allocate hw\n"); 3836 return -ENOMEM; 3837 } 3838 3839 pci_info = info->bus.pci; 3840 3841 rtwdev->pci_info = info->bus.pci; 3842 rtwdev->hci.ops = &rtw89_pci_ops; 3843 rtwdev->hci.type = RTW89_HCI_TYPE_PCIE; 3844 rtwdev->hci.rpwm_addr = pci_info->rpwm_addr; 3845 rtwdev->hci.cpwm_addr = pci_info->cpwm_addr; 3846 3847 SET_IEEE80211_DEV(rtwdev->hw, &pdev->dev); 3848 3849 ret = rtw89_core_init(rtwdev); 3850 if (ret) { 3851 rtw89_err(rtwdev, "failed to initialise core\n"); 3852 goto err_release_hw; 3853 } 3854 3855 ret = rtw89_pci_claim_device(rtwdev, pdev); 3856 if (ret) { 3857 rtw89_err(rtwdev, "failed to claim pci device\n"); 3858 goto err_core_deinit; 3859 } 3860 3861 ret = rtw89_pci_setup_resource(rtwdev, pdev); 3862 if (ret) { 3863 rtw89_err(rtwdev, "failed to setup pci resource\n"); 3864 goto err_declaim_pci; 3865 } 3866 3867 ret = rtw89_chip_info_setup(rtwdev); 3868 if (ret) { 3869 rtw89_err(rtwdev, "failed to setup chip information\n"); 3870 goto err_clear_resource; 3871 } 3872 3873 rtw89_pci_filter_out(rtwdev); 3874 rtw89_pci_link_cfg(rtwdev); 3875 rtw89_pci_l1ss_cfg(rtwdev); 3876 3877 ret = rtw89_core_register(rtwdev); 3878 if (ret) { 3879 rtw89_err(rtwdev, "failed to register core\n"); 3880 goto err_clear_resource; 3881 } 3882 3883 rtw89_core_napi_init(rtwdev); 3884 3885 ret = rtw89_pci_request_irq(rtwdev, pdev); 3886 if (ret) { 3887 rtw89_err(rtwdev, "failed to request pci irq\n"); 3888 goto err_unregister; 3889 } 3890 3891 return 0; 3892 3893 err_unregister: 3894 rtw89_core_napi_deinit(rtwdev); 3895 rtw89_core_unregister(rtwdev); 3896 err_clear_resource: 3897 rtw89_pci_clear_resource(rtwdev, pdev); 3898 err_declaim_pci: 3899 rtw89_pci_declaim_device(rtwdev, pdev); 3900 err_core_deinit: 3901 rtw89_core_deinit(rtwdev); 3902 err_release_hw: 3903 rtw89_free_ieee80211_hw(rtwdev); 3904 3905 return ret; 3906 } 3907 EXPORT_SYMBOL(rtw89_pci_probe); 3908 3909 void rtw89_pci_remove(struct pci_dev *pdev) 3910 { 3911 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 3912 struct rtw89_dev *rtwdev; 3913 3914 rtwdev = hw->priv; 3915 3916 rtw89_pci_free_irq(rtwdev, pdev); 3917 rtw89_core_napi_deinit(rtwdev); 3918 rtw89_core_unregister(rtwdev); 3919 rtw89_pci_clear_resource(rtwdev, pdev); 3920 rtw89_pci_declaim_device(rtwdev, pdev); 3921 rtw89_core_deinit(rtwdev); 3922 rtw89_free_ieee80211_hw(rtwdev); 3923 } 3924 EXPORT_SYMBOL(rtw89_pci_remove); 3925 3926 MODULE_AUTHOR("Realtek Corporation"); 3927 MODULE_DESCRIPTION("Realtek 802.11ax wireless PCI driver"); 3928 MODULE_LICENSE("Dual BSD/GPL"); 3929