1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_MAC_H__ 6 #define __RTW89_MAC_H__ 7 8 #include "core.h" 9 #include "reg.h" 10 11 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000 12 #define ADDR_CAM_ENT_SIZE 0x40 13 #define BSSID_CAM_ENT_SIZE 0x08 14 #define HFC_PAGE_UNIT 64 15 #define RPWM_TRY_CNT 3 16 17 enum rtw89_mac_hwmod_sel { 18 RTW89_DMAC_SEL = 0, 19 RTW89_CMAC_SEL = 1, 20 21 RTW89_MAC_INVALID, 22 }; 23 24 enum rtw89_mac_fwd_target { 25 RTW89_FWD_DONT_CARE = 0, 26 RTW89_FWD_TO_HOST = 1, 27 RTW89_FWD_TO_WLAN_CPU = 2 28 }; 29 30 enum rtw89_mac_wd_dma_intvl { 31 RTW89_MAC_WD_DMA_INTVL_0S, 32 RTW89_MAC_WD_DMA_INTVL_256NS, 33 RTW89_MAC_WD_DMA_INTVL_512NS, 34 RTW89_MAC_WD_DMA_INTVL_768NS, 35 RTW89_MAC_WD_DMA_INTVL_1US, 36 RTW89_MAC_WD_DMA_INTVL_1_5US, 37 RTW89_MAC_WD_DMA_INTVL_2US, 38 RTW89_MAC_WD_DMA_INTVL_4US, 39 RTW89_MAC_WD_DMA_INTVL_8US, 40 RTW89_MAC_WD_DMA_INTVL_16US, 41 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE 42 }; 43 44 enum rtw89_mac_multi_tag_num { 45 RTW89_MAC_TAG_NUM_1, 46 RTW89_MAC_TAG_NUM_2, 47 RTW89_MAC_TAG_NUM_3, 48 RTW89_MAC_TAG_NUM_4, 49 RTW89_MAC_TAG_NUM_5, 50 RTW89_MAC_TAG_NUM_6, 51 RTW89_MAC_TAG_NUM_7, 52 RTW89_MAC_TAG_NUM_8, 53 RTW89_MAC_TAG_NUM_DEF = 0xFE 54 }; 55 56 enum rtw89_mac_lbc_tmr { 57 RTW89_MAC_LBC_TMR_8US = 0, 58 RTW89_MAC_LBC_TMR_16US, 59 RTW89_MAC_LBC_TMR_32US, 60 RTW89_MAC_LBC_TMR_64US, 61 RTW89_MAC_LBC_TMR_128US, 62 RTW89_MAC_LBC_TMR_256US, 63 RTW89_MAC_LBC_TMR_512US, 64 RTW89_MAC_LBC_TMR_1MS, 65 RTW89_MAC_LBC_TMR_2MS, 66 RTW89_MAC_LBC_TMR_4MS, 67 RTW89_MAC_LBC_TMR_8MS, 68 RTW89_MAC_LBC_TMR_DEF = 0xFE 69 }; 70 71 enum rtw89_mac_cpuio_op_cmd_type { 72 CPUIO_OP_CMD_GET_1ST_PID = 0, 73 CPUIO_OP_CMD_GET_NEXT_PID = 1, 74 CPUIO_OP_CMD_ENQ_TO_TAIL = 4, 75 CPUIO_OP_CMD_ENQ_TO_HEAD = 5, 76 CPUIO_OP_CMD_DEQ = 8, 77 CPUIO_OP_CMD_DEQ_ENQ_ALL = 9, 78 CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12 79 }; 80 81 enum rtw89_mac_wde_dle_port_id { 82 WDE_DLE_PORT_ID_DISPATCH = 0, 83 WDE_DLE_PORT_ID_PKTIN = 1, 84 WDE_DLE_PORT_ID_CMAC0 = 3, 85 WDE_DLE_PORT_ID_CMAC1 = 4, 86 WDE_DLE_PORT_ID_CPU_IO = 6, 87 WDE_DLE_PORT_ID_WDRLS = 7, 88 WDE_DLE_PORT_ID_END = 8 89 }; 90 91 enum rtw89_mac_wde_dle_queid_wdrls { 92 WDE_DLE_QUEID_TXOK = 0, 93 WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1, 94 WDE_DLE_QUEID_DROP_LIFETIME_TO = 2, 95 WDE_DLE_QUEID_DROP_MACID_DROP = 3, 96 WDE_DLE_QUEID_NO_REPORT = 4 97 }; 98 99 enum rtw89_mac_ple_dle_port_id { 100 PLE_DLE_PORT_ID_DISPATCH = 0, 101 PLE_DLE_PORT_ID_MPDU = 1, 102 PLE_DLE_PORT_ID_SEC = 2, 103 PLE_DLE_PORT_ID_CMAC0 = 3, 104 PLE_DLE_PORT_ID_CMAC1 = 4, 105 PLE_DLE_PORT_ID_WDRLS = 5, 106 PLE_DLE_PORT_ID_CPU_IO = 6, 107 PLE_DLE_PORT_ID_PLRLS = 7, 108 PLE_DLE_PORT_ID_END = 8 109 }; 110 111 enum rtw89_mac_ple_dle_queid_plrls { 112 PLE_DLE_QUEID_NO_REPORT = 0x0 113 }; 114 115 enum rtw89_machdr_frame_type { 116 RTW89_MGNT = 0, 117 RTW89_CTRL = 1, 118 RTW89_DATA = 2, 119 }; 120 121 enum rtw89_mac_dle_dfi_type { 122 DLE_DFI_TYPE_FREEPG = 0, 123 DLE_DFI_TYPE_QUOTA = 1, 124 DLE_DFI_TYPE_PAGELLT = 2, 125 DLE_DFI_TYPE_PKTINFO = 3, 126 DLE_DFI_TYPE_PREPKTLLT = 4, 127 DLE_DFI_TYPE_NXTPKTLLT = 5, 128 DLE_DFI_TYPE_QLNKTBL = 6, 129 DLE_DFI_TYPE_QEMPTY = 7, 130 }; 131 132 enum rtw89_mac_dle_wde_quota_id { 133 WDE_QTAID_HOST_IF = 0, 134 WDE_QTAID_WLAN_CPU = 1, 135 WDE_QTAID_DATA_CPU = 2, 136 WDE_QTAID_PKTIN = 3, 137 WDE_QTAID_CPUIO = 4, 138 }; 139 140 enum rtw89_mac_dle_ple_quota_id { 141 PLE_QTAID_B0_TXPL = 0, 142 PLE_QTAID_B1_TXPL = 1, 143 PLE_QTAID_C2H = 2, 144 PLE_QTAID_H2C = 3, 145 PLE_QTAID_WLAN_CPU = 4, 146 PLE_QTAID_MPDU = 5, 147 PLE_QTAID_CMAC0_RX = 6, 148 PLE_QTAID_CMAC1_RX = 7, 149 PLE_QTAID_CMAC1_BBRPT = 8, 150 PLE_QTAID_WDRLS = 9, 151 PLE_QTAID_CPUIO = 10, 152 }; 153 154 enum rtw89_mac_dle_ctrl_type { 155 DLE_CTRL_TYPE_WDE = 0, 156 DLE_CTRL_TYPE_PLE = 1, 157 DLE_CTRL_TYPE_NUM = 2, 158 }; 159 160 enum rtw89_mac_ax_l0_to_l1_event { 161 MAC_AX_L0_TO_L1_CHIF_IDLE = 0, 162 MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1, 163 MAC_AX_L0_TO_L1_RLS_PKID = 2, 164 MAC_AX_L0_TO_L1_PTCL_IDLE = 3, 165 MAC_AX_L0_TO_L1_RX_QTA_LOST = 4, 166 MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5, 167 MAC_AX_L0_TO_L1_PCIE_STUCK = 6, 168 MAC_AX_L0_TO_L1_EVENT_MAX = 15, 169 }; 170 171 enum rtw89_mac_dbg_port_sel { 172 /* CMAC 0 related */ 173 RTW89_DBG_PORT_SEL_PTCL_C0 = 0, 174 RTW89_DBG_PORT_SEL_SCH_C0, 175 RTW89_DBG_PORT_SEL_TMAC_C0, 176 RTW89_DBG_PORT_SEL_RMAC_C0, 177 RTW89_DBG_PORT_SEL_RMACST_C0, 178 RTW89_DBG_PORT_SEL_RMAC_PLCP_C0, 179 RTW89_DBG_PORT_SEL_TRXPTCL_C0, 180 RTW89_DBG_PORT_SEL_TX_INFOL_C0, 181 RTW89_DBG_PORT_SEL_TX_INFOH_C0, 182 RTW89_DBG_PORT_SEL_TXTF_INFOL_C0, 183 RTW89_DBG_PORT_SEL_TXTF_INFOH_C0, 184 /* CMAC 1 related */ 185 RTW89_DBG_PORT_SEL_PTCL_C1, 186 RTW89_DBG_PORT_SEL_SCH_C1, 187 RTW89_DBG_PORT_SEL_TMAC_C1, 188 RTW89_DBG_PORT_SEL_RMAC_C1, 189 RTW89_DBG_PORT_SEL_RMACST_C1, 190 RTW89_DBG_PORT_SEL_RMAC_PLCP_C1, 191 RTW89_DBG_PORT_SEL_TRXPTCL_C1, 192 RTW89_DBG_PORT_SEL_TX_INFOL_C1, 193 RTW89_DBG_PORT_SEL_TX_INFOH_C1, 194 RTW89_DBG_PORT_SEL_TXTF_INFOL_C1, 195 RTW89_DBG_PORT_SEL_TXTF_INFOH_C1, 196 /* DLE related */ 197 RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG, 198 RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA, 199 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT, 200 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO, 201 RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT, 202 RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT, 203 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL, 204 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY, 205 RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG, 206 RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA, 207 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT, 208 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO, 209 RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT, 210 RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT, 211 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL, 212 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY, 213 RTW89_DBG_PORT_SEL_PKTINFO, 214 /* DISPATCHER related */ 215 RTW89_DBG_PORT_SEL_DSPT_HDT_TX0, 216 RTW89_DBG_PORT_SEL_DSPT_HDT_TX1, 217 RTW89_DBG_PORT_SEL_DSPT_HDT_TX2, 218 RTW89_DBG_PORT_SEL_DSPT_HDT_TX3, 219 RTW89_DBG_PORT_SEL_DSPT_HDT_TX4, 220 RTW89_DBG_PORT_SEL_DSPT_HDT_TX5, 221 RTW89_DBG_PORT_SEL_DSPT_HDT_TX6, 222 RTW89_DBG_PORT_SEL_DSPT_HDT_TX7, 223 RTW89_DBG_PORT_SEL_DSPT_HDT_TX8, 224 RTW89_DBG_PORT_SEL_DSPT_HDT_TX9, 225 RTW89_DBG_PORT_SEL_DSPT_HDT_TXA, 226 RTW89_DBG_PORT_SEL_DSPT_HDT_TXB, 227 RTW89_DBG_PORT_SEL_DSPT_HDT_TXC, 228 RTW89_DBG_PORT_SEL_DSPT_HDT_TXD, 229 RTW89_DBG_PORT_SEL_DSPT_HDT_TXE, 230 RTW89_DBG_PORT_SEL_DSPT_HDT_TXF, 231 RTW89_DBG_PORT_SEL_DSPT_CDT_TX0, 232 RTW89_DBG_PORT_SEL_DSPT_CDT_TX1, 233 RTW89_DBG_PORT_SEL_DSPT_CDT_TX3, 234 RTW89_DBG_PORT_SEL_DSPT_CDT_TX4, 235 RTW89_DBG_PORT_SEL_DSPT_CDT_TX5, 236 RTW89_DBG_PORT_SEL_DSPT_CDT_TX6, 237 RTW89_DBG_PORT_SEL_DSPT_CDT_TX7, 238 RTW89_DBG_PORT_SEL_DSPT_CDT_TX8, 239 RTW89_DBG_PORT_SEL_DSPT_CDT_TX9, 240 RTW89_DBG_PORT_SEL_DSPT_CDT_TXA, 241 RTW89_DBG_PORT_SEL_DSPT_CDT_TXB, 242 RTW89_DBG_PORT_SEL_DSPT_CDT_TXC, 243 RTW89_DBG_PORT_SEL_DSPT_HDT_RX0, 244 RTW89_DBG_PORT_SEL_DSPT_HDT_RX1, 245 RTW89_DBG_PORT_SEL_DSPT_HDT_RX2, 246 RTW89_DBG_PORT_SEL_DSPT_HDT_RX3, 247 RTW89_DBG_PORT_SEL_DSPT_HDT_RX4, 248 RTW89_DBG_PORT_SEL_DSPT_HDT_RX5, 249 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0, 250 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0, 251 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1, 252 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2, 253 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1, 254 RTW89_DBG_PORT_SEL_DSPT_STF_CTRL, 255 RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL, 256 RTW89_DBG_PORT_SEL_DSPT_WDE_INTF, 257 RTW89_DBG_PORT_SEL_DSPT_PLE_INTF, 258 RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL, 259 /* PCIE related */ 260 RTW89_DBG_PORT_SEL_PCIE_TXDMA, 261 RTW89_DBG_PORT_SEL_PCIE_RXDMA, 262 RTW89_DBG_PORT_SEL_PCIE_CVT, 263 RTW89_DBG_PORT_SEL_PCIE_CXPL, 264 RTW89_DBG_PORT_SEL_PCIE_IO, 265 RTW89_DBG_PORT_SEL_PCIE_MISC, 266 RTW89_DBG_PORT_SEL_PCIE_MISC2, 267 268 /* keep last */ 269 RTW89_DBG_PORT_SEL_LAST, 270 RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST, 271 RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST, 272 }; 273 274 /* SRAM mem dump */ 275 #define R_AX_INDIR_ACCESS_ENTRY 0x40000 276 277 #define AXIDMA_BASE_ADDR 0x18006000 278 #define STA_SCHED_BASE_ADDR 0x18808000 279 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000 280 #define SECURITY_CAM_BASE_ADDR 0x18814000 281 #define WOW_CAM_BASE_ADDR 0x18815000 282 #define CMAC_TBL_BASE_ADDR 0x18840000 283 #define ADDR_CAM_BASE_ADDR 0x18850000 284 #define BSSID_CAM_BASE_ADDR 0x18853000 285 #define BA_CAM_BASE_ADDR 0x18854000 286 #define BCN_IE_CAM0_BASE_ADDR 0x18855000 287 #define SHARED_BUF_BASE_ADDR 0x18700000 288 #define DMAC_TBL_BASE_ADDR 0x18800000 289 #define SHCUT_MACHDR_BASE_ADDR 0x18800800 290 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000 291 #define TXD_FIFO_0_BASE_ADDR 0x18856200 292 #define TXD_FIFO_1_BASE_ADDR 0x188A1080 293 #define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */ 294 #define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */ 295 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000 296 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000 297 #define CPU_LOCAL_BASE_ADDR 0x18003000 298 299 #define CCTL_INFO_SIZE 32 300 301 enum rtw89_mac_mem_sel { 302 RTW89_MAC_MEM_AXIDMA, 303 RTW89_MAC_MEM_SHARED_BUF, 304 RTW89_MAC_MEM_DMAC_TBL, 305 RTW89_MAC_MEM_SHCUT_MACHDR, 306 RTW89_MAC_MEM_STA_SCHED, 307 RTW89_MAC_MEM_RXPLD_FLTR_CAM, 308 RTW89_MAC_MEM_SECURITY_CAM, 309 RTW89_MAC_MEM_WOW_CAM, 310 RTW89_MAC_MEM_CMAC_TBL, 311 RTW89_MAC_MEM_ADDR_CAM, 312 RTW89_MAC_MEM_BA_CAM, 313 RTW89_MAC_MEM_BCN_IE_CAM0, 314 RTW89_MAC_MEM_BCN_IE_CAM1, 315 RTW89_MAC_MEM_TXD_FIFO_0, 316 RTW89_MAC_MEM_TXD_FIFO_1, 317 RTW89_MAC_MEM_TXDATA_FIFO_0, 318 RTW89_MAC_MEM_TXDATA_FIFO_1, 319 RTW89_MAC_MEM_CPU_LOCAL, 320 RTW89_MAC_MEM_BSSID_CAM, 321 RTW89_MAC_MEM_TXD_FIFO_0_V1, 322 RTW89_MAC_MEM_TXD_FIFO_1_V1, 323 324 /* keep last */ 325 RTW89_MAC_MEM_NUM, 326 }; 327 328 extern const u32 rtw89_mac_mem_base_addrs[]; 329 330 enum rtw89_rpwm_req_pwr_state { 331 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0, 332 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1, 333 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2, 334 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3, 335 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4, 336 RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5, 337 RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6, 338 RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7, 339 RTW89_MAC_RPWM_REQ_PWR_STATE_MAX, 340 }; 341 342 struct rtw89_pwr_cfg { 343 u16 addr; 344 u8 cv_msk; 345 u8 intf_msk; 346 u8 base:4; 347 u8 cmd:4; 348 u8 msk; 349 u8 val; 350 }; 351 352 enum rtw89_mac_c2h_ofld_func { 353 RTW89_MAC_C2H_FUNC_EFUSE_DUMP, 354 RTW89_MAC_C2H_FUNC_READ_RSP, 355 RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP, 356 RTW89_MAC_C2H_FUNC_BCN_RESEND, 357 RTW89_MAC_C2H_FUNC_MACID_PAUSE, 358 RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6, 359 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9, 360 RTW89_MAC_C2H_FUNC_OFLD_MAX, 361 }; 362 363 enum rtw89_mac_c2h_info_func { 364 RTW89_MAC_C2H_FUNC_REC_ACK, 365 RTW89_MAC_C2H_FUNC_DONE_ACK, 366 RTW89_MAC_C2H_FUNC_C2H_LOG, 367 RTW89_MAC_C2H_FUNC_BCN_CNT, 368 RTW89_MAC_C2H_FUNC_INFO_MAX, 369 }; 370 371 enum rtw89_mac_c2h_class { 372 RTW89_MAC_C2H_CLASS_INFO, 373 RTW89_MAC_C2H_CLASS_OFLD, 374 RTW89_MAC_C2H_CLASS_TWT, 375 RTW89_MAC_C2H_CLASS_WOW, 376 RTW89_MAC_C2H_CLASS_MCC, 377 RTW89_MAC_C2H_CLASS_FWDBG, 378 RTW89_MAC_C2H_CLASS_MAX, 379 }; 380 381 struct rtw89_mac_ax_coex { 382 #define RTW89_MAC_AX_COEX_RTK_MODE 0 383 #define RTW89_MAC_AX_COEX_CSR_MODE 1 384 u8 pta_mode; 385 #define RTW89_MAC_AX_COEX_INNER 0 386 #define RTW89_MAC_AX_COEX_OUTPUT 1 387 #define RTW89_MAC_AX_COEX_INPUT 2 388 u8 direction; 389 }; 390 391 struct rtw89_mac_ax_plt { 392 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0) 393 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1) 394 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2) 395 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3) 396 u8 band; 397 u8 tx; 398 u8 rx; 399 }; 400 401 enum rtw89_mac_bf_rrsc_rate { 402 RTW89_MAC_BF_RRSC_6M = 0, 403 RTW89_MAC_BF_RRSC_9M = 1, 404 RTW89_MAC_BF_RRSC_12M, 405 RTW89_MAC_BF_RRSC_18M, 406 RTW89_MAC_BF_RRSC_24M, 407 RTW89_MAC_BF_RRSC_36M, 408 RTW89_MAC_BF_RRSC_48M, 409 RTW89_MAC_BF_RRSC_54M, 410 RTW89_MAC_BF_RRSC_HT_MSC0, 411 RTW89_MAC_BF_RRSC_HT_MSC1, 412 RTW89_MAC_BF_RRSC_HT_MSC2, 413 RTW89_MAC_BF_RRSC_HT_MSC3, 414 RTW89_MAC_BF_RRSC_HT_MSC4, 415 RTW89_MAC_BF_RRSC_HT_MSC5, 416 RTW89_MAC_BF_RRSC_HT_MSC6, 417 RTW89_MAC_BF_RRSC_HT_MSC7, 418 RTW89_MAC_BF_RRSC_VHT_MSC0, 419 RTW89_MAC_BF_RRSC_VHT_MSC1, 420 RTW89_MAC_BF_RRSC_VHT_MSC2, 421 RTW89_MAC_BF_RRSC_VHT_MSC3, 422 RTW89_MAC_BF_RRSC_VHT_MSC4, 423 RTW89_MAC_BF_RRSC_VHT_MSC5, 424 RTW89_MAC_BF_RRSC_VHT_MSC6, 425 RTW89_MAC_BF_RRSC_VHT_MSC7, 426 RTW89_MAC_BF_RRSC_HE_MSC0, 427 RTW89_MAC_BF_RRSC_HE_MSC1, 428 RTW89_MAC_BF_RRSC_HE_MSC2, 429 RTW89_MAC_BF_RRSC_HE_MSC3, 430 RTW89_MAC_BF_RRSC_HE_MSC4, 431 RTW89_MAC_BF_RRSC_HE_MSC5, 432 RTW89_MAC_BF_RRSC_HE_MSC6, 433 RTW89_MAC_BF_RRSC_HE_MSC7 = 31, 434 RTW89_MAC_BF_RRSC_MAX = 32 435 }; 436 437 #define RTW89_R32_EA 0xEAEAEAEA 438 #define RTW89_R32_DEAD 0xDEADBEEF 439 #define MAC_REG_POOL_COUNT 10 440 #define ACCESS_CMAC(_addr) \ 441 ({typeof(_addr) __addr = (_addr); \ 442 __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; }) 443 #define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000 444 445 #define PTCL_IDLE_POLL_CNT 10000 446 #define SW_CVR_DUR_US 8 447 #define SW_CVR_CNT 8 448 449 #define DLE_BOUND_UNIT (8 * 1024) 450 #define DLE_WAIT_CNT 2000 451 #define TRXCFG_WAIT_CNT 2000 452 453 #define RTW89_WDE_PG_64 64 454 #define RTW89_WDE_PG_128 128 455 #define RTW89_WDE_PG_256 256 456 457 #define S_AX_WDE_PAGE_SEL_64 0 458 #define S_AX_WDE_PAGE_SEL_128 1 459 #define S_AX_WDE_PAGE_SEL_256 2 460 461 #define RTW89_PLE_PG_64 64 462 #define RTW89_PLE_PG_128 128 463 #define RTW89_PLE_PG_256 256 464 465 #define S_AX_PLE_PAGE_SEL_64 0 466 #define S_AX_PLE_PAGE_SEL_128 1 467 #define S_AX_PLE_PAGE_SEL_256 2 468 469 #define B_CMAC0_MGQ_NORMAL BIT(2) 470 #define B_CMAC0_MGQ_NO_PWRSAV BIT(3) 471 #define B_CMAC0_CPUMGQ BIT(4) 472 #define B_CMAC1_MGQ_NORMAL BIT(10) 473 #define B_CMAC1_MGQ_NO_PWRSAV BIT(11) 474 #define B_CMAC1_CPUMGQ BIT(12) 475 476 #define QEMP_ACQ_GRP_MACID_NUM 8 477 #define QEMP_ACQ_GRP_QSEL_SH 4 478 #define QEMP_ACQ_GRP_QSEL_MASK 0xF 479 480 #define SDIO_LOCAL_BASE_ADDR 0x80000000 481 482 #define PWR_CMD_WRITE 0 483 #define PWR_CMD_POLL 1 484 #define PWR_CMD_DELAY 2 485 #define PWR_CMD_END 3 486 487 #define PWR_INTF_MSK_SDIO BIT(0) 488 #define PWR_INTF_MSK_USB BIT(1) 489 #define PWR_INTF_MSK_PCIE BIT(2) 490 #define PWR_INTF_MSK_ALL 0x7 491 492 #define PWR_BASE_MAC 0 493 #define PWR_BASE_USB 1 494 #define PWR_BASE_PCIE 2 495 #define PWR_BASE_SDIO 3 496 497 #define PWR_CV_MSK_A BIT(0) 498 #define PWR_CV_MSK_B BIT(1) 499 #define PWR_CV_MSK_C BIT(2) 500 #define PWR_CV_MSK_D BIT(3) 501 #define PWR_CV_MSK_E BIT(4) 502 #define PWR_CV_MSK_F BIT(5) 503 #define PWR_CV_MSK_G BIT(6) 504 #define PWR_CV_MSK_TEST BIT(7) 505 #define PWR_CV_MSK_ALL 0xFF 506 507 #define PWR_DELAY_US 0 508 #define PWR_DELAY_MS 1 509 510 /* STA scheduler */ 511 #define SS_MACID_SH 8 512 #define SS_TX_LEN_MSK 0x1FFFFF 513 #define SS_CTRL1_R_TX_LEN 5 514 #define SS_CTRL1_R_NEXT_LINK 20 515 #define SS_LINK_SIZE 256 516 517 /* MAC debug port */ 518 #define TMAC_DBG_SEL_C0 0xA5 519 #define RMAC_DBG_SEL_C0 0xA6 520 #define TRXPTCL_DBG_SEL_C0 0xA7 521 #define TMAC_DBG_SEL_C1 0xB5 522 #define RMAC_DBG_SEL_C1 0xB6 523 #define TRXPTCL_DBG_SEL_C1 0xB7 524 #define FW_PROG_CNTR_DBG_SEL 0xF2 525 #define PCIE_TXDMA_DBG_SEL 0x30 526 #define PCIE_RXDMA_DBG_SEL 0x31 527 #define PCIE_CVT_DBG_SEL 0x32 528 #define PCIE_CXPL_DBG_SEL 0x33 529 #define PCIE_IO_DBG_SEL 0x37 530 #define PCIE_MISC_DBG_SEL 0x38 531 #define PCIE_MISC2_DBG_SEL 0x00 532 #define MAC_DBG_SEL 1 533 #define RMAC_CMAC_DBG_SEL 1 534 535 /* TRXPTCL dbg port sel */ 536 #define TRXPTRL_DBG_SEL_TMAC 0 537 #define TRXPTRL_DBG_SEL_RMAC 1 538 539 struct rtw89_cpuio_ctrl { 540 u16 pkt_num; 541 u16 start_pktid; 542 u16 end_pktid; 543 u8 cmd_type; 544 u8 macid; 545 u8 src_pid; 546 u8 src_qid; 547 u8 dst_pid; 548 u8 dst_qid; 549 u16 pktid; 550 }; 551 552 struct rtw89_mac_dbg_port_info { 553 u32 sel_addr; 554 u8 sel_byte; 555 u32 sel_msk; 556 u32 srt; 557 u32 end; 558 u32 rd_addr; 559 u8 rd_byte; 560 u32 rd_msk; 561 }; 562 563 #define QLNKTBL_ADDR_INFO_SEL BIT(0) 564 #define QLNKTBL_ADDR_INFO_SEL_0 0 565 #define QLNKTBL_ADDR_INFO_SEL_1 1 566 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1) 567 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0) 568 569 struct rtw89_mac_dle_dfi_ctrl { 570 enum rtw89_mac_dle_ctrl_type type; 571 u32 target; 572 u32 addr; 573 u32 out_data; 574 }; 575 576 struct rtw89_mac_dle_dfi_quota { 577 enum rtw89_mac_dle_ctrl_type dle_type; 578 u32 qtaid; 579 u16 rsv_pgnum; 580 u16 use_pgnum; 581 }; 582 583 struct rtw89_mac_dle_dfi_qempty { 584 enum rtw89_mac_dle_ctrl_type dle_type; 585 u32 grpsel; 586 u32 qempty; 587 }; 588 589 enum rtw89_mac_error_scenario { 590 RTW89_WCPU_CPU_EXCEPTION = 2, 591 RTW89_WCPU_ASSERTION = 3, 592 }; 593 594 #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28) 595 596 /* Define DBG and recovery enum */ 597 enum mac_ax_err_info { 598 /* Get error info */ 599 600 /* L0 */ 601 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001, 602 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002, 603 MAC_AX_ERR_L0_RESET_DONE = 0x0003, 604 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010, 605 606 /* L1 */ 607 MAC_AX_ERR_L1_ERR_DMAC = 0x1000, 608 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001, 609 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002, 610 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010, 611 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011, 612 613 /* L2 */ 614 /* address hole (master) */ 615 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000, 616 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010, 617 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020, 618 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030, 619 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040, 620 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050, 621 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060, 622 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070, 623 624 /* AHB bridge timeout (master) */ 625 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100, 626 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110, 627 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120, 628 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130, 629 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140, 630 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150, 631 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160, 632 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170, 633 634 /* APB_SA bridge timeout (master + slave) */ 635 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200, 636 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201, 637 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202, 638 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203, 639 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204, 640 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205, 641 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206, 642 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207, 643 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208, 644 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209, 645 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A, 646 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210, 647 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211, 648 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212, 649 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213, 650 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214, 651 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215, 652 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216, 653 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218, 654 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219, 655 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A, 656 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220, 657 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221, 658 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222, 659 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223, 660 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224, 661 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225, 662 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226, 663 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227, 664 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228, 665 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229, 666 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A, 667 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230, 668 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231, 669 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232, 670 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233, 671 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234, 672 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235, 673 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236, 674 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237, 675 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238, 676 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239, 677 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A, 678 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240, 679 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241, 680 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242, 681 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243, 682 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244, 683 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245, 684 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246, 685 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247, 686 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248, 687 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249, 688 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A, 689 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250, 690 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251, 691 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252, 692 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253, 693 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254, 694 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255, 695 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256, 696 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257, 697 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258, 698 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259, 699 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A, 700 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260, 701 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261, 702 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262, 703 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263, 704 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264, 705 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265, 706 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266, 707 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267, 708 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268, 709 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269, 710 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A, 711 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270, 712 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271, 713 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272, 714 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273, 715 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274, 716 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275, 717 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276, 718 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277, 719 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278, 720 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279, 721 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A, 722 723 /* APB_BBRF bridge timeout (master) */ 724 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300, 725 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310, 726 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320, 727 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330, 728 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340, 729 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350, 730 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360, 731 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370, 732 MAC_AX_ERR_L2_RESET_DONE = 0x2400, 733 MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599, 734 MAC_AX_ERR_CPU_EXCEPTION = 0x3000, 735 MAC_AX_ERR_ASSERTION = 0x4000, 736 MAC_AX_GET_ERR_MAX, 737 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000, 738 739 /* set error info */ 740 MAC_AX_ERR_L1_DISABLE_EN = 0x0001, 741 MAC_AX_ERR_L1_RCVY_EN = 0x0002, 742 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003, 743 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004, 744 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010, 745 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011, 746 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012, 747 MAC_AX_ERR_L0_RCVY_EN = 0x0013, 748 MAC_AX_SET_ERR_MAX, 749 }; 750 751 struct rtw89_mac_size_set { 752 const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie; 753 const struct rtw89_dle_size wde_size0; 754 const struct rtw89_dle_size wde_size4; 755 const struct rtw89_dle_size wde_size6; 756 const struct rtw89_dle_size wde_size9; 757 const struct rtw89_dle_size wde_size18; 758 const struct rtw89_dle_size wde_size19; 759 const struct rtw89_dle_size ple_size0; 760 const struct rtw89_dle_size ple_size4; 761 const struct rtw89_dle_size ple_size6; 762 const struct rtw89_dle_size ple_size8; 763 const struct rtw89_dle_size ple_size18; 764 const struct rtw89_dle_size ple_size19; 765 const struct rtw89_wde_quota wde_qt0; 766 const struct rtw89_wde_quota wde_qt4; 767 const struct rtw89_wde_quota wde_qt6; 768 const struct rtw89_wde_quota wde_qt17; 769 const struct rtw89_wde_quota wde_qt18; 770 const struct rtw89_ple_quota ple_qt4; 771 const struct rtw89_ple_quota ple_qt5; 772 const struct rtw89_ple_quota ple_qt13; 773 const struct rtw89_ple_quota ple_qt18; 774 const struct rtw89_ple_quota ple_qt44; 775 const struct rtw89_ple_quota ple_qt45; 776 const struct rtw89_ple_quota ple_qt46; 777 const struct rtw89_ple_quota ple_qt47; 778 const struct rtw89_ple_quota ple_qt58; 779 const struct rtw89_ple_quota ple_qt_52a_wow; 780 }; 781 782 extern const struct rtw89_mac_size_set rtw89_mac_size; 783 784 static inline u32 rtw89_mac_reg_by_idx(u32 reg_base, u8 band) 785 { 786 return band == 0 ? reg_base : (reg_base + 0x2000); 787 } 788 789 static inline u32 rtw89_mac_reg_by_port(u32 base, u8 port, u8 mac_idx) 790 { 791 return rtw89_mac_reg_by_idx(base + port * 0x40, mac_idx); 792 } 793 794 static inline u32 795 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 796 u32 base, u32 mask) 797 { 798 u32 reg; 799 800 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 801 return rtw89_read32_mask(rtwdev, reg, mask); 802 } 803 804 static inline void 805 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base, 806 u32 data) 807 { 808 u32 reg; 809 810 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 811 rtw89_write32(rtwdev, reg, data); 812 } 813 814 static inline void 815 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 816 u32 base, u32 mask, u32 data) 817 { 818 u32 reg; 819 820 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 821 rtw89_write32_mask(rtwdev, reg, mask, data); 822 } 823 824 static inline void 825 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 826 u32 base, u32 mask, u16 data) 827 { 828 u32 reg; 829 830 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 831 rtw89_write16_mask(rtwdev, reg, mask, data); 832 } 833 834 static inline void 835 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 836 u32 base, u32 bit) 837 { 838 u32 reg; 839 840 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 841 rtw89_write32_clr(rtwdev, reg, bit); 842 } 843 844 static inline void 845 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 846 u32 base, u16 bit) 847 { 848 u32 reg; 849 850 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 851 rtw89_write16_clr(rtwdev, reg, bit); 852 } 853 854 static inline void 855 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 856 u32 base, u32 bit) 857 { 858 u32 reg; 859 860 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 861 rtw89_write32_set(rtwdev, reg, bit); 862 } 863 864 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev); 865 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev); 866 int rtw89_mac_init(struct rtw89_dev *rtwdev); 867 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band, 868 enum rtw89_mac_hwmod_sel sel); 869 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val); 870 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val); 871 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); 872 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 873 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 874 struct ieee80211_vif *vif); 875 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); 876 void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev); 877 int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw); 878 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev); 879 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev); 880 881 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev) 882 { 883 const struct rtw89_chip_info *chip = rtwdev->chip; 884 885 return chip->ops->enable_bb_rf(rtwdev); 886 } 887 888 static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev) 889 { 890 const struct rtw89_chip_info *chip = rtwdev->chip; 891 892 return chip->ops->disable_bb_rf(rtwdev); 893 } 894 895 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev); 896 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err); 897 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 898 u32 len, u8 class, u8 func); 899 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev); 900 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 901 u32 *tx_en, enum rtw89_sch_tx_sel sel); 902 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 903 u32 *tx_en, enum rtw89_sch_tx_sel sel); 904 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 905 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 906 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_ids, bool enable); 907 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx); 908 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop); 909 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex); 910 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 911 const struct rtw89_mac_ax_coex *coex); 912 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 913 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 914 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 915 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 916 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt); 917 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band); 918 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val); 919 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev); 920 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev); 921 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl); 922 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl); 923 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 924 enum rtw89_phy_idx phy_idx, 925 u32 reg_base, u32 *cr); 926 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter); 927 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev); 928 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 929 struct ieee80211_sta *sta); 930 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 931 struct ieee80211_sta *sta); 932 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 933 struct ieee80211_bss_conf *conf); 934 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 935 struct ieee80211_sta *sta, bool disconnect); 936 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev); 937 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 938 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 939 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 940 struct rtw89_vif *rtwvif, bool en); 941 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause); 942 943 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 944 { 945 if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags)) 946 return; 947 948 _rtw89_mac_bf_monitor_track(rtwdev); 949 } 950 951 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev, 952 enum rtw89_phy_idx phy_idx, 953 u32 reg_base, u32 *val) 954 { 955 u32 cr; 956 957 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 958 return -EINVAL; 959 960 *val = rtw89_read32(rtwdev, cr); 961 return 0; 962 } 963 964 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev, 965 enum rtw89_phy_idx phy_idx, 966 u32 reg_base, u32 val) 967 { 968 u32 cr; 969 970 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 971 return -EINVAL; 972 973 rtw89_write32(rtwdev, cr, val); 974 return 0; 975 } 976 977 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev, 978 enum rtw89_phy_idx phy_idx, 979 u32 reg_base, u32 mask, u32 val) 980 { 981 u32 cr; 982 983 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 984 return -EINVAL; 985 986 rtw89_write32_mask(rtwdev, cr, mask, val); 987 return 0; 988 } 989 990 static inline void rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev *rtwdev, 991 bool enable) 992 { 993 const struct rtw89_chip_info *chip = rtwdev->chip; 994 995 if (enable) 996 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 997 B_AX_HCI_TXDMA_EN); 998 else 999 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1000 B_AX_HCI_TXDMA_EN); 1001 } 1002 1003 static inline void rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev *rtwdev, 1004 bool enable) 1005 { 1006 const struct rtw89_chip_info *chip = rtwdev->chip; 1007 1008 if (enable) 1009 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 1010 B_AX_HCI_RXDMA_EN); 1011 else 1012 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1013 B_AX_HCI_RXDMA_EN); 1014 } 1015 1016 static inline void rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev *rtwdev, 1017 bool enable) 1018 { 1019 const struct rtw89_chip_info *chip = rtwdev->chip; 1020 1021 if (enable) 1022 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 1023 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 1024 else 1025 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 1026 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 1027 } 1028 1029 static inline bool rtw89_mac_get_power_state(struct rtw89_dev *rtwdev) 1030 { 1031 u32 val; 1032 1033 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, 1034 B_AX_WLMAC_PWR_STE_MASK); 1035 1036 return !!val; 1037 } 1038 1039 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 1040 bool resume, u32 tx_time); 1041 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 1042 u32 *tx_time); 1043 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 1044 struct rtw89_sta *rtwsta, 1045 bool resume, u8 tx_retry); 1046 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 1047 struct rtw89_sta *rtwsta, u8 *tx_retry); 1048 1049 enum rtw89_mac_xtal_si_offset { 1050 XTAL0 = 0x0, 1051 XTAL3 = 0x3, 1052 XTAL_SI_XTAL_SC_XI = 0x04, 1053 #define XTAL_SC_XI_MASK GENMASK(7, 0) 1054 XTAL_SI_XTAL_SC_XO = 0x05, 1055 #define XTAL_SC_XO_MASK GENMASK(7, 0) 1056 XTAL_SI_PWR_CUT = 0x10, 1057 #define XTAL_SI_SMALL_PWR_CUT BIT(0) 1058 #define XTAL_SI_BIG_PWR_CUT BIT(1) 1059 XTAL_SI_XTAL_XMD_2 = 0x24, 1060 #define XTAL_SI_LDO_LPS GENMASK(6, 4) 1061 XTAL_SI_XTAL_XMD_4 = 0x26, 1062 #define XTAL_SI_LPS_CAP GENMASK(3, 0) 1063 XTAL_SI_CV = 0x41, 1064 XTAL_SI_LOW_ADDR = 0x62, 1065 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0) 1066 XTAL_SI_CTRL = 0x63, 1067 #define XTAL_SI_MODE_SEL_MASK GENMASK(7, 6) 1068 #define XTAL_SI_RDY BIT(5) 1069 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0) 1070 XTAL_SI_READ_VAL = 0x7A, 1071 XTAL_SI_WL_RFC_S0 = 0x80, 1072 #define XTAL_SI_RF00S_EN GENMASK(2, 0) 1073 #define XTAL_SI_RF00 BIT(0) 1074 XTAL_SI_WL_RFC_S1 = 0x81, 1075 #define XTAL_SI_RF10S_EN GENMASK(2, 0) 1076 #define XTAL_SI_RF10 BIT(0) 1077 XTAL_SI_ANAPAR_WL = 0x90, 1078 #define XTAL_SI_SRAM2RFC BIT(7) 1079 #define XTAL_SI_GND_SHDN_WL BIT(6) 1080 #define XTAL_SI_SHDN_WL BIT(5) 1081 #define XTAL_SI_RFC2RF BIT(4) 1082 #define XTAL_SI_OFF_EI BIT(3) 1083 #define XTAL_SI_OFF_WEI BIT(2) 1084 #define XTAL_SI_PON_EI BIT(1) 1085 #define XTAL_SI_PON_WEI BIT(0) 1086 XTAL_SI_SRAM_CTRL = 0xA1, 1087 #define XTAL_SI_SRAM_DIS BIT(1) 1088 #define FULL_BIT_MASK GENMASK(7, 0) 1089 }; 1090 1091 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask); 1092 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val); 1093 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 1094 u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd); 1095 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, 1096 struct rtw89_cpuio_ctrl *ctrl_para, bool wd); 1097 int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, 1098 enum rtw89_machdr_frame_type type, 1099 enum rtw89_mac_fwd_target fwd_target, u8 mac_idx); 1100 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow); 1101 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 1102 enum rtw89_mac_idx band); 1103 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow); 1104 1105 #endif 1106