1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_MAC_H__ 6 #define __RTW89_MAC_H__ 7 8 #include "core.h" 9 #include "reg.h" 10 11 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000 12 #define ADDR_CAM_ENT_SIZE 0x40 13 #define BSSID_CAM_ENT_SIZE 0x08 14 #define HFC_PAGE_UNIT 64 15 #define RPWM_TRY_CNT 3 16 17 enum rtw89_mac_hwmod_sel { 18 RTW89_DMAC_SEL = 0, 19 RTW89_CMAC_SEL = 1, 20 21 RTW89_MAC_INVALID, 22 }; 23 24 enum rtw89_mac_fwd_target { 25 RTW89_FWD_DONT_CARE = 0, 26 RTW89_FWD_TO_HOST = 1, 27 RTW89_FWD_TO_WLAN_CPU = 2 28 }; 29 30 enum rtw89_mac_wd_dma_intvl { 31 RTW89_MAC_WD_DMA_INTVL_0S, 32 RTW89_MAC_WD_DMA_INTVL_256NS, 33 RTW89_MAC_WD_DMA_INTVL_512NS, 34 RTW89_MAC_WD_DMA_INTVL_768NS, 35 RTW89_MAC_WD_DMA_INTVL_1US, 36 RTW89_MAC_WD_DMA_INTVL_1_5US, 37 RTW89_MAC_WD_DMA_INTVL_2US, 38 RTW89_MAC_WD_DMA_INTVL_4US, 39 RTW89_MAC_WD_DMA_INTVL_8US, 40 RTW89_MAC_WD_DMA_INTVL_16US, 41 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE 42 }; 43 44 enum rtw89_mac_multi_tag_num { 45 RTW89_MAC_TAG_NUM_1, 46 RTW89_MAC_TAG_NUM_2, 47 RTW89_MAC_TAG_NUM_3, 48 RTW89_MAC_TAG_NUM_4, 49 RTW89_MAC_TAG_NUM_5, 50 RTW89_MAC_TAG_NUM_6, 51 RTW89_MAC_TAG_NUM_7, 52 RTW89_MAC_TAG_NUM_8, 53 RTW89_MAC_TAG_NUM_DEF = 0xFE 54 }; 55 56 enum rtw89_mac_lbc_tmr { 57 RTW89_MAC_LBC_TMR_8US = 0, 58 RTW89_MAC_LBC_TMR_16US, 59 RTW89_MAC_LBC_TMR_32US, 60 RTW89_MAC_LBC_TMR_64US, 61 RTW89_MAC_LBC_TMR_128US, 62 RTW89_MAC_LBC_TMR_256US, 63 RTW89_MAC_LBC_TMR_512US, 64 RTW89_MAC_LBC_TMR_1MS, 65 RTW89_MAC_LBC_TMR_2MS, 66 RTW89_MAC_LBC_TMR_4MS, 67 RTW89_MAC_LBC_TMR_8MS, 68 RTW89_MAC_LBC_TMR_DEF = 0xFE 69 }; 70 71 enum rtw89_mac_cpuio_op_cmd_type { 72 CPUIO_OP_CMD_GET_1ST_PID = 0, 73 CPUIO_OP_CMD_GET_NEXT_PID = 1, 74 CPUIO_OP_CMD_ENQ_TO_TAIL = 4, 75 CPUIO_OP_CMD_ENQ_TO_HEAD = 5, 76 CPUIO_OP_CMD_DEQ = 8, 77 CPUIO_OP_CMD_DEQ_ENQ_ALL = 9, 78 CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12 79 }; 80 81 enum rtw89_mac_wde_dle_port_id { 82 WDE_DLE_PORT_ID_DISPATCH = 0, 83 WDE_DLE_PORT_ID_PKTIN = 1, 84 WDE_DLE_PORT_ID_CMAC0 = 3, 85 WDE_DLE_PORT_ID_CMAC1 = 4, 86 WDE_DLE_PORT_ID_CPU_IO = 6, 87 WDE_DLE_PORT_ID_WDRLS = 7, 88 WDE_DLE_PORT_ID_END = 8 89 }; 90 91 enum rtw89_mac_wde_dle_queid_wdrls { 92 WDE_DLE_QUEID_TXOK = 0, 93 WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1, 94 WDE_DLE_QUEID_DROP_LIFETIME_TO = 2, 95 WDE_DLE_QUEID_DROP_MACID_DROP = 3, 96 WDE_DLE_QUEID_NO_REPORT = 4 97 }; 98 99 enum rtw89_mac_ple_dle_port_id { 100 PLE_DLE_PORT_ID_DISPATCH = 0, 101 PLE_DLE_PORT_ID_MPDU = 1, 102 PLE_DLE_PORT_ID_SEC = 2, 103 PLE_DLE_PORT_ID_CMAC0 = 3, 104 PLE_DLE_PORT_ID_CMAC1 = 4, 105 PLE_DLE_PORT_ID_WDRLS = 5, 106 PLE_DLE_PORT_ID_CPU_IO = 6, 107 PLE_DLE_PORT_ID_PLRLS = 7, 108 PLE_DLE_PORT_ID_END = 8 109 }; 110 111 enum rtw89_mac_ple_dle_queid_plrls { 112 PLE_DLE_QUEID_NO_REPORT = 0x0 113 }; 114 115 enum rtw89_machdr_frame_type { 116 RTW89_MGNT = 0, 117 RTW89_CTRL = 1, 118 RTW89_DATA = 2, 119 }; 120 121 enum rtw89_mac_dle_dfi_type { 122 DLE_DFI_TYPE_FREEPG = 0, 123 DLE_DFI_TYPE_QUOTA = 1, 124 DLE_DFI_TYPE_PAGELLT = 2, 125 DLE_DFI_TYPE_PKTINFO = 3, 126 DLE_DFI_TYPE_PREPKTLLT = 4, 127 DLE_DFI_TYPE_NXTPKTLLT = 5, 128 DLE_DFI_TYPE_QLNKTBL = 6, 129 DLE_DFI_TYPE_QEMPTY = 7, 130 }; 131 132 enum rtw89_mac_dle_wde_quota_id { 133 WDE_QTAID_HOST_IF = 0, 134 WDE_QTAID_WLAN_CPU = 1, 135 WDE_QTAID_DATA_CPU = 2, 136 WDE_QTAID_PKTIN = 3, 137 WDE_QTAID_CPUIO = 4, 138 }; 139 140 enum rtw89_mac_dle_ple_quota_id { 141 PLE_QTAID_B0_TXPL = 0, 142 PLE_QTAID_B1_TXPL = 1, 143 PLE_QTAID_C2H = 2, 144 PLE_QTAID_H2C = 3, 145 PLE_QTAID_WLAN_CPU = 4, 146 PLE_QTAID_MPDU = 5, 147 PLE_QTAID_CMAC0_RX = 6, 148 PLE_QTAID_CMAC1_RX = 7, 149 PLE_QTAID_CMAC1_BBRPT = 8, 150 PLE_QTAID_WDRLS = 9, 151 PLE_QTAID_CPUIO = 10, 152 }; 153 154 enum rtw89_mac_dle_ctrl_type { 155 DLE_CTRL_TYPE_WDE = 0, 156 DLE_CTRL_TYPE_PLE = 1, 157 DLE_CTRL_TYPE_NUM = 2, 158 }; 159 160 enum rtw89_mac_ax_l0_to_l1_event { 161 MAC_AX_L0_TO_L1_CHIF_IDLE = 0, 162 MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1, 163 MAC_AX_L0_TO_L1_RLS_PKID = 2, 164 MAC_AX_L0_TO_L1_PTCL_IDLE = 3, 165 MAC_AX_L0_TO_L1_RX_QTA_LOST = 4, 166 MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5, 167 MAC_AX_L0_TO_L1_PCIE_STUCK = 6, 168 MAC_AX_L0_TO_L1_EVENT_MAX = 15, 169 }; 170 171 enum rtw89_mac_dbg_port_sel { 172 /* CMAC 0 related */ 173 RTW89_DBG_PORT_SEL_PTCL_C0 = 0, 174 RTW89_DBG_PORT_SEL_SCH_C0, 175 RTW89_DBG_PORT_SEL_TMAC_C0, 176 RTW89_DBG_PORT_SEL_RMAC_C0, 177 RTW89_DBG_PORT_SEL_RMACST_C0, 178 RTW89_DBG_PORT_SEL_RMAC_PLCP_C0, 179 RTW89_DBG_PORT_SEL_TRXPTCL_C0, 180 RTW89_DBG_PORT_SEL_TX_INFOL_C0, 181 RTW89_DBG_PORT_SEL_TX_INFOH_C0, 182 RTW89_DBG_PORT_SEL_TXTF_INFOL_C0, 183 RTW89_DBG_PORT_SEL_TXTF_INFOH_C0, 184 /* CMAC 1 related */ 185 RTW89_DBG_PORT_SEL_PTCL_C1, 186 RTW89_DBG_PORT_SEL_SCH_C1, 187 RTW89_DBG_PORT_SEL_TMAC_C1, 188 RTW89_DBG_PORT_SEL_RMAC_C1, 189 RTW89_DBG_PORT_SEL_RMACST_C1, 190 RTW89_DBG_PORT_SEL_RMAC_PLCP_C1, 191 RTW89_DBG_PORT_SEL_TRXPTCL_C1, 192 RTW89_DBG_PORT_SEL_TX_INFOL_C1, 193 RTW89_DBG_PORT_SEL_TX_INFOH_C1, 194 RTW89_DBG_PORT_SEL_TXTF_INFOL_C1, 195 RTW89_DBG_PORT_SEL_TXTF_INFOH_C1, 196 /* DLE related */ 197 RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG, 198 RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA, 199 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT, 200 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO, 201 RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT, 202 RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT, 203 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL, 204 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY, 205 RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG, 206 RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA, 207 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT, 208 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO, 209 RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT, 210 RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT, 211 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL, 212 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY, 213 RTW89_DBG_PORT_SEL_PKTINFO, 214 /* PCIE related */ 215 RTW89_DBG_PORT_SEL_PCIE_TXDMA, 216 RTW89_DBG_PORT_SEL_PCIE_RXDMA, 217 RTW89_DBG_PORT_SEL_PCIE_CVT, 218 RTW89_DBG_PORT_SEL_PCIE_CXPL, 219 RTW89_DBG_PORT_SEL_PCIE_IO, 220 RTW89_DBG_PORT_SEL_PCIE_MISC, 221 RTW89_DBG_PORT_SEL_PCIE_MISC2, 222 223 /* keep last */ 224 RTW89_DBG_PORT_SEL_LAST, 225 RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST, 226 RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST, 227 }; 228 229 /* SRAM mem dump */ 230 #define R_AX_INDIR_ACCESS_ENTRY 0x40000 231 232 #define AXIDMA_BASE_ADDR 0x18006000 233 #define STA_SCHED_BASE_ADDR 0x18808000 234 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000 235 #define SECURITY_CAM_BASE_ADDR 0x18814000 236 #define WOW_CAM_BASE_ADDR 0x18815000 237 #define CMAC_TBL_BASE_ADDR 0x18840000 238 #define ADDR_CAM_BASE_ADDR 0x18850000 239 #define BSSID_CAM_BASE_ADDR 0x18853000 240 #define BA_CAM_BASE_ADDR 0x18854000 241 #define BCN_IE_CAM0_BASE_ADDR 0x18855000 242 #define SHARED_BUF_BASE_ADDR 0x18700000 243 #define DMAC_TBL_BASE_ADDR 0x18800000 244 #define SHCUT_MACHDR_BASE_ADDR 0x18800800 245 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000 246 #define TXD_FIFO_0_BASE_ADDR 0x18856200 247 #define TXD_FIFO_1_BASE_ADDR 0x188A1080 248 #define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */ 249 #define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */ 250 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000 251 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000 252 #define CPU_LOCAL_BASE_ADDR 0x18003000 253 254 #define CCTL_INFO_SIZE 32 255 256 enum rtw89_mac_mem_sel { 257 RTW89_MAC_MEM_AXIDMA, 258 RTW89_MAC_MEM_SHARED_BUF, 259 RTW89_MAC_MEM_DMAC_TBL, 260 RTW89_MAC_MEM_SHCUT_MACHDR, 261 RTW89_MAC_MEM_STA_SCHED, 262 RTW89_MAC_MEM_RXPLD_FLTR_CAM, 263 RTW89_MAC_MEM_SECURITY_CAM, 264 RTW89_MAC_MEM_WOW_CAM, 265 RTW89_MAC_MEM_CMAC_TBL, 266 RTW89_MAC_MEM_ADDR_CAM, 267 RTW89_MAC_MEM_BA_CAM, 268 RTW89_MAC_MEM_BCN_IE_CAM0, 269 RTW89_MAC_MEM_BCN_IE_CAM1, 270 RTW89_MAC_MEM_TXD_FIFO_0, 271 RTW89_MAC_MEM_TXD_FIFO_1, 272 RTW89_MAC_MEM_TXDATA_FIFO_0, 273 RTW89_MAC_MEM_TXDATA_FIFO_1, 274 RTW89_MAC_MEM_CPU_LOCAL, 275 RTW89_MAC_MEM_BSSID_CAM, 276 RTW89_MAC_MEM_TXD_FIFO_0_V1, 277 RTW89_MAC_MEM_TXD_FIFO_1_V1, 278 279 /* keep last */ 280 RTW89_MAC_MEM_NUM, 281 }; 282 283 extern const u32 rtw89_mac_mem_base_addrs[]; 284 285 enum rtw89_rpwm_req_pwr_state { 286 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0, 287 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1, 288 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2, 289 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3, 290 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4, 291 RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5, 292 RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6, 293 RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7, 294 RTW89_MAC_RPWM_REQ_PWR_STATE_MAX, 295 }; 296 297 struct rtw89_pwr_cfg { 298 u16 addr; 299 u8 cv_msk; 300 u8 intf_msk; 301 u8 base:4; 302 u8 cmd:4; 303 u8 msk; 304 u8 val; 305 }; 306 307 enum rtw89_mac_c2h_ofld_func { 308 RTW89_MAC_C2H_FUNC_EFUSE_DUMP, 309 RTW89_MAC_C2H_FUNC_READ_RSP, 310 RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP, 311 RTW89_MAC_C2H_FUNC_BCN_RESEND, 312 RTW89_MAC_C2H_FUNC_MACID_PAUSE, 313 RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6, 314 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9, 315 RTW89_MAC_C2H_FUNC_OFLD_MAX, 316 }; 317 318 enum rtw89_mac_c2h_info_func { 319 RTW89_MAC_C2H_FUNC_REC_ACK, 320 RTW89_MAC_C2H_FUNC_DONE_ACK, 321 RTW89_MAC_C2H_FUNC_C2H_LOG, 322 RTW89_MAC_C2H_FUNC_BCN_CNT, 323 RTW89_MAC_C2H_FUNC_INFO_MAX, 324 }; 325 326 enum rtw89_mac_c2h_class { 327 RTW89_MAC_C2H_CLASS_INFO, 328 RTW89_MAC_C2H_CLASS_OFLD, 329 RTW89_MAC_C2H_CLASS_TWT, 330 RTW89_MAC_C2H_CLASS_WOW, 331 RTW89_MAC_C2H_CLASS_MCC, 332 RTW89_MAC_C2H_CLASS_FWDBG, 333 RTW89_MAC_C2H_CLASS_MAX, 334 }; 335 336 struct rtw89_mac_ax_coex { 337 #define RTW89_MAC_AX_COEX_RTK_MODE 0 338 #define RTW89_MAC_AX_COEX_CSR_MODE 1 339 u8 pta_mode; 340 #define RTW89_MAC_AX_COEX_INNER 0 341 #define RTW89_MAC_AX_COEX_OUTPUT 1 342 #define RTW89_MAC_AX_COEX_INPUT 2 343 u8 direction; 344 }; 345 346 struct rtw89_mac_ax_plt { 347 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0) 348 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1) 349 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2) 350 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3) 351 u8 band; 352 u8 tx; 353 u8 rx; 354 }; 355 356 enum rtw89_mac_bf_rrsc_rate { 357 RTW89_MAC_BF_RRSC_6M = 0, 358 RTW89_MAC_BF_RRSC_9M = 1, 359 RTW89_MAC_BF_RRSC_12M, 360 RTW89_MAC_BF_RRSC_18M, 361 RTW89_MAC_BF_RRSC_24M, 362 RTW89_MAC_BF_RRSC_36M, 363 RTW89_MAC_BF_RRSC_48M, 364 RTW89_MAC_BF_RRSC_54M, 365 RTW89_MAC_BF_RRSC_HT_MSC0, 366 RTW89_MAC_BF_RRSC_HT_MSC1, 367 RTW89_MAC_BF_RRSC_HT_MSC2, 368 RTW89_MAC_BF_RRSC_HT_MSC3, 369 RTW89_MAC_BF_RRSC_HT_MSC4, 370 RTW89_MAC_BF_RRSC_HT_MSC5, 371 RTW89_MAC_BF_RRSC_HT_MSC6, 372 RTW89_MAC_BF_RRSC_HT_MSC7, 373 RTW89_MAC_BF_RRSC_VHT_MSC0, 374 RTW89_MAC_BF_RRSC_VHT_MSC1, 375 RTW89_MAC_BF_RRSC_VHT_MSC2, 376 RTW89_MAC_BF_RRSC_VHT_MSC3, 377 RTW89_MAC_BF_RRSC_VHT_MSC4, 378 RTW89_MAC_BF_RRSC_VHT_MSC5, 379 RTW89_MAC_BF_RRSC_VHT_MSC6, 380 RTW89_MAC_BF_RRSC_VHT_MSC7, 381 RTW89_MAC_BF_RRSC_HE_MSC0, 382 RTW89_MAC_BF_RRSC_HE_MSC1, 383 RTW89_MAC_BF_RRSC_HE_MSC2, 384 RTW89_MAC_BF_RRSC_HE_MSC3, 385 RTW89_MAC_BF_RRSC_HE_MSC4, 386 RTW89_MAC_BF_RRSC_HE_MSC5, 387 RTW89_MAC_BF_RRSC_HE_MSC6, 388 RTW89_MAC_BF_RRSC_HE_MSC7 = 31, 389 RTW89_MAC_BF_RRSC_MAX = 32 390 }; 391 392 #define RTW89_R32_EA 0xEAEAEAEA 393 #define RTW89_R32_DEAD 0xDEADBEEF 394 #define MAC_REG_POOL_COUNT 10 395 #define ACCESS_CMAC(_addr) \ 396 ({typeof(_addr) __addr = (_addr); \ 397 __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; }) 398 399 #define PTCL_IDLE_POLL_CNT 10000 400 #define SW_CVR_DUR_US 8 401 #define SW_CVR_CNT 8 402 403 #define DLE_BOUND_UNIT (8 * 1024) 404 #define DLE_WAIT_CNT 2000 405 #define TRXCFG_WAIT_CNT 2000 406 407 #define RTW89_WDE_PG_64 64 408 #define RTW89_WDE_PG_128 128 409 #define RTW89_WDE_PG_256 256 410 411 #define S_AX_WDE_PAGE_SEL_64 0 412 #define S_AX_WDE_PAGE_SEL_128 1 413 #define S_AX_WDE_PAGE_SEL_256 2 414 415 #define RTW89_PLE_PG_64 64 416 #define RTW89_PLE_PG_128 128 417 #define RTW89_PLE_PG_256 256 418 419 #define S_AX_PLE_PAGE_SEL_64 0 420 #define S_AX_PLE_PAGE_SEL_128 1 421 #define S_AX_PLE_PAGE_SEL_256 2 422 423 #define B_CMAC0_MGQ_NORMAL BIT(2) 424 #define B_CMAC0_MGQ_NO_PWRSAV BIT(3) 425 #define B_CMAC0_CPUMGQ BIT(4) 426 #define B_CMAC1_MGQ_NORMAL BIT(10) 427 #define B_CMAC1_MGQ_NO_PWRSAV BIT(11) 428 #define B_CMAC1_CPUMGQ BIT(12) 429 430 #define QEMP_ACQ_GRP_MACID_NUM 8 431 #define QEMP_ACQ_GRP_QSEL_SH 4 432 #define QEMP_ACQ_GRP_QSEL_MASK 0xF 433 434 #define SDIO_LOCAL_BASE_ADDR 0x80000000 435 436 #define PWR_CMD_WRITE 0 437 #define PWR_CMD_POLL 1 438 #define PWR_CMD_DELAY 2 439 #define PWR_CMD_END 3 440 441 #define PWR_INTF_MSK_SDIO BIT(0) 442 #define PWR_INTF_MSK_USB BIT(1) 443 #define PWR_INTF_MSK_PCIE BIT(2) 444 #define PWR_INTF_MSK_ALL 0x7 445 446 #define PWR_BASE_MAC 0 447 #define PWR_BASE_USB 1 448 #define PWR_BASE_PCIE 2 449 #define PWR_BASE_SDIO 3 450 451 #define PWR_CV_MSK_A BIT(0) 452 #define PWR_CV_MSK_B BIT(1) 453 #define PWR_CV_MSK_C BIT(2) 454 #define PWR_CV_MSK_D BIT(3) 455 #define PWR_CV_MSK_E BIT(4) 456 #define PWR_CV_MSK_F BIT(5) 457 #define PWR_CV_MSK_G BIT(6) 458 #define PWR_CV_MSK_TEST BIT(7) 459 #define PWR_CV_MSK_ALL 0xFF 460 461 #define PWR_DELAY_US 0 462 #define PWR_DELAY_MS 1 463 464 /* STA scheduler */ 465 #define SS_MACID_SH 8 466 #define SS_TX_LEN_MSK 0x1FFFFF 467 #define SS_CTRL1_R_TX_LEN 5 468 #define SS_CTRL1_R_NEXT_LINK 20 469 #define SS_LINK_SIZE 256 470 471 /* MAC debug port */ 472 #define TMAC_DBG_SEL_C0 0xA5 473 #define RMAC_DBG_SEL_C0 0xA6 474 #define TRXPTCL_DBG_SEL_C0 0xA7 475 #define TMAC_DBG_SEL_C1 0xB5 476 #define RMAC_DBG_SEL_C1 0xB6 477 #define TRXPTCL_DBG_SEL_C1 0xB7 478 #define FW_PROG_CNTR_DBG_SEL 0xF2 479 #define PCIE_TXDMA_DBG_SEL 0x30 480 #define PCIE_RXDMA_DBG_SEL 0x31 481 #define PCIE_CVT_DBG_SEL 0x32 482 #define PCIE_CXPL_DBG_SEL 0x33 483 #define PCIE_IO_DBG_SEL 0x37 484 #define PCIE_MISC_DBG_SEL 0x38 485 #define PCIE_MISC2_DBG_SEL 0x00 486 #define MAC_DBG_SEL 1 487 #define RMAC_CMAC_DBG_SEL 1 488 489 /* TRXPTCL dbg port sel */ 490 #define TRXPTRL_DBG_SEL_TMAC 0 491 #define TRXPTRL_DBG_SEL_RMAC 1 492 493 struct rtw89_cpuio_ctrl { 494 u16 pkt_num; 495 u16 start_pktid; 496 u16 end_pktid; 497 u8 cmd_type; 498 u8 macid; 499 u8 src_pid; 500 u8 src_qid; 501 u8 dst_pid; 502 u8 dst_qid; 503 u16 pktid; 504 }; 505 506 struct rtw89_mac_dbg_port_info { 507 u32 sel_addr; 508 u8 sel_byte; 509 u32 sel_msk; 510 u32 srt; 511 u32 end; 512 u32 rd_addr; 513 u8 rd_byte; 514 u32 rd_msk; 515 }; 516 517 #define QLNKTBL_ADDR_INFO_SEL BIT(0) 518 #define QLNKTBL_ADDR_INFO_SEL_0 0 519 #define QLNKTBL_ADDR_INFO_SEL_1 1 520 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1) 521 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0) 522 523 struct rtw89_mac_dle_dfi_ctrl { 524 enum rtw89_mac_dle_ctrl_type type; 525 u32 target; 526 u32 addr; 527 u32 out_data; 528 }; 529 530 struct rtw89_mac_dle_dfi_quota { 531 enum rtw89_mac_dle_ctrl_type dle_type; 532 u32 qtaid; 533 u16 rsv_pgnum; 534 u16 use_pgnum; 535 }; 536 537 struct rtw89_mac_dle_dfi_qempty { 538 enum rtw89_mac_dle_ctrl_type dle_type; 539 u32 grpsel; 540 u32 qempty; 541 }; 542 543 enum rtw89_mac_error_scenario { 544 RTW89_WCPU_CPU_EXCEPTION = 2, 545 RTW89_WCPU_ASSERTION = 3, 546 }; 547 548 #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28) 549 550 /* Define DBG and recovery enum */ 551 enum mac_ax_err_info { 552 /* Get error info */ 553 554 /* L0 */ 555 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001, 556 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002, 557 MAC_AX_ERR_L0_RESET_DONE = 0x0003, 558 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010, 559 560 /* L1 */ 561 MAC_AX_ERR_L1_ERR_DMAC = 0x1000, 562 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001, 563 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002, 564 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010, 565 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011, 566 567 /* L2 */ 568 /* address hole (master) */ 569 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000, 570 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010, 571 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020, 572 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030, 573 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040, 574 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050, 575 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060, 576 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070, 577 578 /* AHB bridge timeout (master) */ 579 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100, 580 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110, 581 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120, 582 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130, 583 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140, 584 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150, 585 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160, 586 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170, 587 588 /* APB_SA bridge timeout (master + slave) */ 589 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200, 590 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201, 591 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202, 592 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203, 593 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204, 594 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205, 595 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206, 596 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207, 597 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208, 598 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209, 599 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A, 600 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210, 601 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211, 602 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212, 603 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213, 604 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214, 605 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215, 606 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216, 607 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218, 608 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219, 609 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A, 610 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220, 611 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221, 612 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222, 613 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223, 614 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224, 615 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225, 616 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226, 617 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227, 618 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228, 619 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229, 620 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A, 621 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230, 622 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231, 623 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232, 624 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233, 625 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234, 626 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235, 627 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236, 628 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237, 629 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238, 630 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239, 631 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A, 632 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240, 633 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241, 634 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242, 635 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243, 636 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244, 637 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245, 638 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246, 639 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247, 640 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248, 641 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249, 642 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A, 643 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250, 644 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251, 645 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252, 646 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253, 647 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254, 648 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255, 649 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256, 650 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257, 651 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258, 652 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259, 653 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A, 654 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260, 655 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261, 656 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262, 657 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263, 658 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264, 659 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265, 660 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266, 661 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267, 662 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268, 663 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269, 664 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A, 665 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270, 666 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271, 667 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272, 668 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273, 669 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274, 670 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275, 671 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276, 672 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277, 673 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278, 674 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279, 675 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A, 676 677 /* APB_BBRF bridge timeout (master) */ 678 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300, 679 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310, 680 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320, 681 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330, 682 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340, 683 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350, 684 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360, 685 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370, 686 MAC_AX_ERR_L2_RESET_DONE = 0x2400, 687 MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599, 688 MAC_AX_ERR_CPU_EXCEPTION = 0x3000, 689 MAC_AX_ERR_ASSERTION = 0x4000, 690 MAC_AX_GET_ERR_MAX, 691 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000, 692 693 /* set error info */ 694 MAC_AX_ERR_L1_DISABLE_EN = 0x0001, 695 MAC_AX_ERR_L1_RCVY_EN = 0x0002, 696 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003, 697 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004, 698 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010, 699 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011, 700 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012, 701 MAC_AX_ERR_L0_RCVY_EN = 0x0013, 702 MAC_AX_SET_ERR_MAX, 703 }; 704 705 struct rtw89_mac_size_set { 706 const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie; 707 const struct rtw89_dle_size wde_size0; 708 const struct rtw89_dle_size wde_size4; 709 const struct rtw89_dle_size wde_size6; 710 const struct rtw89_dle_size wde_size9; 711 const struct rtw89_dle_size wde_size18; 712 const struct rtw89_dle_size wde_size19; 713 const struct rtw89_dle_size ple_size0; 714 const struct rtw89_dle_size ple_size4; 715 const struct rtw89_dle_size ple_size6; 716 const struct rtw89_dle_size ple_size8; 717 const struct rtw89_dle_size ple_size18; 718 const struct rtw89_dle_size ple_size19; 719 const struct rtw89_wde_quota wde_qt0; 720 const struct rtw89_wde_quota wde_qt4; 721 const struct rtw89_wde_quota wde_qt6; 722 const struct rtw89_wde_quota wde_qt17; 723 const struct rtw89_wde_quota wde_qt18; 724 const struct rtw89_ple_quota ple_qt4; 725 const struct rtw89_ple_quota ple_qt5; 726 const struct rtw89_ple_quota ple_qt13; 727 const struct rtw89_ple_quota ple_qt18; 728 const struct rtw89_ple_quota ple_qt44; 729 const struct rtw89_ple_quota ple_qt45; 730 const struct rtw89_ple_quota ple_qt46; 731 const struct rtw89_ple_quota ple_qt47; 732 const struct rtw89_ple_quota ple_qt58; 733 const struct rtw89_ple_quota ple_qt_52a_wow; 734 }; 735 736 extern const struct rtw89_mac_size_set rtw89_mac_size; 737 738 static inline u32 rtw89_mac_reg_by_idx(u32 reg_base, u8 band) 739 { 740 return band == 0 ? reg_base : (reg_base + 0x2000); 741 } 742 743 static inline u32 rtw89_mac_reg_by_port(u32 base, u8 port, u8 mac_idx) 744 { 745 return rtw89_mac_reg_by_idx(base + port * 0x40, mac_idx); 746 } 747 748 static inline u32 749 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 750 u32 base, u32 mask) 751 { 752 u32 reg; 753 754 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 755 return rtw89_read32_mask(rtwdev, reg, mask); 756 } 757 758 static inline void 759 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base, 760 u32 data) 761 { 762 u32 reg; 763 764 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 765 rtw89_write32(rtwdev, reg, data); 766 } 767 768 static inline void 769 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 770 u32 base, u32 mask, u32 data) 771 { 772 u32 reg; 773 774 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 775 rtw89_write32_mask(rtwdev, reg, mask, data); 776 } 777 778 static inline void 779 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 780 u32 base, u32 mask, u16 data) 781 { 782 u32 reg; 783 784 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 785 rtw89_write16_mask(rtwdev, reg, mask, data); 786 } 787 788 static inline void 789 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 790 u32 base, u32 bit) 791 { 792 u32 reg; 793 794 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 795 rtw89_write32_clr(rtwdev, reg, bit); 796 } 797 798 static inline void 799 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 800 u32 base, u16 bit) 801 { 802 u32 reg; 803 804 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 805 rtw89_write16_clr(rtwdev, reg, bit); 806 } 807 808 static inline void 809 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 810 u32 base, u32 bit) 811 { 812 u32 reg; 813 814 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx); 815 rtw89_write32_set(rtwdev, reg, bit); 816 } 817 818 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev); 819 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev); 820 int rtw89_mac_init(struct rtw89_dev *rtwdev); 821 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band, 822 enum rtw89_mac_hwmod_sel sel); 823 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val); 824 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val); 825 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); 826 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 827 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 828 struct ieee80211_vif *vif); 829 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); 830 void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev); 831 int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw); 832 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev); 833 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev); 834 835 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev) 836 { 837 const struct rtw89_chip_info *chip = rtwdev->chip; 838 839 return chip->ops->enable_bb_rf(rtwdev); 840 } 841 842 static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev) 843 { 844 const struct rtw89_chip_info *chip = rtwdev->chip; 845 846 return chip->ops->disable_bb_rf(rtwdev); 847 } 848 849 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev); 850 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err); 851 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 852 u32 len, u8 class, u8 func); 853 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev); 854 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 855 u32 *tx_en, enum rtw89_sch_tx_sel sel); 856 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 857 u32 *tx_en, enum rtw89_sch_tx_sel sel); 858 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 859 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 860 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_ids, bool enable); 861 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx); 862 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop); 863 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex); 864 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 865 const struct rtw89_mac_ax_coex *coex); 866 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 867 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 868 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 869 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 870 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt); 871 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band); 872 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val); 873 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev); 874 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev); 875 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl); 876 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl); 877 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 878 enum rtw89_phy_idx phy_idx, 879 u32 reg_base, u32 *cr); 880 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter); 881 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev); 882 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 883 struct ieee80211_sta *sta); 884 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 885 struct ieee80211_sta *sta); 886 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 887 struct ieee80211_bss_conf *conf); 888 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 889 struct ieee80211_sta *sta, bool disconnect); 890 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev); 891 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 892 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 893 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 894 struct rtw89_vif *rtwvif, bool en); 895 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause); 896 897 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 898 { 899 if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags)) 900 return; 901 902 _rtw89_mac_bf_monitor_track(rtwdev); 903 } 904 905 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev, 906 enum rtw89_phy_idx phy_idx, 907 u32 reg_base, u32 *val) 908 { 909 u32 cr; 910 911 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 912 return -EINVAL; 913 914 *val = rtw89_read32(rtwdev, cr); 915 return 0; 916 } 917 918 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev, 919 enum rtw89_phy_idx phy_idx, 920 u32 reg_base, u32 val) 921 { 922 u32 cr; 923 924 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 925 return -EINVAL; 926 927 rtw89_write32(rtwdev, cr, val); 928 return 0; 929 } 930 931 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev, 932 enum rtw89_phy_idx phy_idx, 933 u32 reg_base, u32 mask, u32 val) 934 { 935 u32 cr; 936 937 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr)) 938 return -EINVAL; 939 940 rtw89_write32_mask(rtwdev, cr, mask, val); 941 return 0; 942 } 943 944 static inline void rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev *rtwdev, 945 bool enable) 946 { 947 const struct rtw89_chip_info *chip = rtwdev->chip; 948 949 if (enable) 950 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 951 B_AX_HCI_TXDMA_EN); 952 else 953 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 954 B_AX_HCI_TXDMA_EN); 955 } 956 957 static inline void rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev *rtwdev, 958 bool enable) 959 { 960 const struct rtw89_chip_info *chip = rtwdev->chip; 961 962 if (enable) 963 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 964 B_AX_HCI_RXDMA_EN); 965 else 966 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 967 B_AX_HCI_RXDMA_EN); 968 } 969 970 static inline void rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev *rtwdev, 971 bool enable) 972 { 973 const struct rtw89_chip_info *chip = rtwdev->chip; 974 975 if (enable) 976 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 977 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 978 else 979 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr, 980 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 981 } 982 983 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 984 bool resume, u32 tx_time); 985 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 986 u32 *tx_time); 987 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 988 struct rtw89_sta *rtwsta, 989 bool resume, u8 tx_retry); 990 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 991 struct rtw89_sta *rtwsta, u8 *tx_retry); 992 993 enum rtw89_mac_xtal_si_offset { 994 XTAL0 = 0x0, 995 XTAL3 = 0x3, 996 XTAL_SI_XTAL_SC_XI = 0x04, 997 #define XTAL_SC_XI_MASK GENMASK(7, 0) 998 XTAL_SI_XTAL_SC_XO = 0x05, 999 #define XTAL_SC_XO_MASK GENMASK(7, 0) 1000 XTAL_SI_PWR_CUT = 0x10, 1001 #define XTAL_SI_SMALL_PWR_CUT BIT(0) 1002 #define XTAL_SI_BIG_PWR_CUT BIT(1) 1003 XTAL_SI_XTAL_XMD_2 = 0x24, 1004 #define XTAL_SI_LDO_LPS GENMASK(6, 4) 1005 XTAL_SI_XTAL_XMD_4 = 0x26, 1006 #define XTAL_SI_LPS_CAP GENMASK(3, 0) 1007 XTAL_SI_CV = 0x41, 1008 XTAL_SI_LOW_ADDR = 0x62, 1009 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0) 1010 XTAL_SI_CTRL = 0x63, 1011 #define XTAL_SI_MODE_SEL_MASK GENMASK(7, 6) 1012 #define XTAL_SI_RDY BIT(5) 1013 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0) 1014 XTAL_SI_READ_VAL = 0x7A, 1015 XTAL_SI_WL_RFC_S0 = 0x80, 1016 #define XTAL_SI_RF00S_EN GENMASK(2, 0) 1017 #define XTAL_SI_RF00 BIT(0) 1018 XTAL_SI_WL_RFC_S1 = 0x81, 1019 #define XTAL_SI_RF10S_EN GENMASK(2, 0) 1020 #define XTAL_SI_RF10 BIT(0) 1021 XTAL_SI_ANAPAR_WL = 0x90, 1022 #define XTAL_SI_SRAM2RFC BIT(7) 1023 #define XTAL_SI_GND_SHDN_WL BIT(6) 1024 #define XTAL_SI_SHDN_WL BIT(5) 1025 #define XTAL_SI_RFC2RF BIT(4) 1026 #define XTAL_SI_OFF_EI BIT(3) 1027 #define XTAL_SI_OFF_WEI BIT(2) 1028 #define XTAL_SI_PON_EI BIT(1) 1029 #define XTAL_SI_PON_WEI BIT(0) 1030 XTAL_SI_SRAM_CTRL = 0xA1, 1031 #define XTAL_SI_SRAM_DIS BIT(1) 1032 #define FULL_BIT_MASK GENMASK(7, 0) 1033 }; 1034 1035 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask); 1036 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val); 1037 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 1038 u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd); 1039 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, 1040 struct rtw89_cpuio_ctrl *ctrl_para, bool wd); 1041 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow); 1042 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 1043 enum rtw89_mac_idx band); 1044 1045 #endif 1046