1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020  Realtek Corporation
3  */
4 
5 #ifndef __RTW89_MAC_H__
6 #define __RTW89_MAC_H__
7 
8 #include "core.h"
9 #include "reg.h"
10 
11 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000
12 #define ADDR_CAM_ENT_SIZE  0x40
13 #define BSSID_CAM_ENT_SIZE 0x08
14 #define HFC_PAGE_UNIT 64
15 #define RPWM_TRY_CNT 3
16 
17 enum rtw89_mac_hwmod_sel {
18 	RTW89_DMAC_SEL = 0,
19 	RTW89_CMAC_SEL = 1,
20 
21 	RTW89_MAC_INVALID,
22 };
23 
24 enum rtw89_mac_fwd_target {
25 	RTW89_FWD_DONT_CARE    = 0,
26 	RTW89_FWD_TO_HOST      = 1,
27 	RTW89_FWD_TO_WLAN_CPU  = 2
28 };
29 
30 enum rtw89_mac_wd_dma_intvl {
31 	RTW89_MAC_WD_DMA_INTVL_0S,
32 	RTW89_MAC_WD_DMA_INTVL_256NS,
33 	RTW89_MAC_WD_DMA_INTVL_512NS,
34 	RTW89_MAC_WD_DMA_INTVL_768NS,
35 	RTW89_MAC_WD_DMA_INTVL_1US,
36 	RTW89_MAC_WD_DMA_INTVL_1_5US,
37 	RTW89_MAC_WD_DMA_INTVL_2US,
38 	RTW89_MAC_WD_DMA_INTVL_4US,
39 	RTW89_MAC_WD_DMA_INTVL_8US,
40 	RTW89_MAC_WD_DMA_INTVL_16US,
41 	RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE
42 };
43 
44 enum rtw89_mac_multi_tag_num {
45 	RTW89_MAC_TAG_NUM_1,
46 	RTW89_MAC_TAG_NUM_2,
47 	RTW89_MAC_TAG_NUM_3,
48 	RTW89_MAC_TAG_NUM_4,
49 	RTW89_MAC_TAG_NUM_5,
50 	RTW89_MAC_TAG_NUM_6,
51 	RTW89_MAC_TAG_NUM_7,
52 	RTW89_MAC_TAG_NUM_8,
53 	RTW89_MAC_TAG_NUM_DEF = 0xFE
54 };
55 
56 enum rtw89_mac_lbc_tmr {
57 	RTW89_MAC_LBC_TMR_8US = 0,
58 	RTW89_MAC_LBC_TMR_16US,
59 	RTW89_MAC_LBC_TMR_32US,
60 	RTW89_MAC_LBC_TMR_64US,
61 	RTW89_MAC_LBC_TMR_128US,
62 	RTW89_MAC_LBC_TMR_256US,
63 	RTW89_MAC_LBC_TMR_512US,
64 	RTW89_MAC_LBC_TMR_1MS,
65 	RTW89_MAC_LBC_TMR_2MS,
66 	RTW89_MAC_LBC_TMR_4MS,
67 	RTW89_MAC_LBC_TMR_8MS,
68 	RTW89_MAC_LBC_TMR_DEF = 0xFE
69 };
70 
71 enum rtw89_mac_cpuio_op_cmd_type {
72 	CPUIO_OP_CMD_GET_1ST_PID = 0,
73 	CPUIO_OP_CMD_GET_NEXT_PID = 1,
74 	CPUIO_OP_CMD_ENQ_TO_TAIL = 4,
75 	CPUIO_OP_CMD_ENQ_TO_HEAD = 5,
76 	CPUIO_OP_CMD_DEQ = 8,
77 	CPUIO_OP_CMD_DEQ_ENQ_ALL = 9,
78 	CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12
79 };
80 
81 enum rtw89_mac_wde_dle_port_id {
82 	WDE_DLE_PORT_ID_DISPATCH = 0,
83 	WDE_DLE_PORT_ID_PKTIN = 1,
84 	WDE_DLE_PORT_ID_CMAC0 = 3,
85 	WDE_DLE_PORT_ID_CMAC1 = 4,
86 	WDE_DLE_PORT_ID_CPU_IO = 6,
87 	WDE_DLE_PORT_ID_WDRLS = 7,
88 	WDE_DLE_PORT_ID_END = 8
89 };
90 
91 enum rtw89_mac_wde_dle_queid_wdrls {
92 	WDE_DLE_QUEID_TXOK = 0,
93 	WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1,
94 	WDE_DLE_QUEID_DROP_LIFETIME_TO = 2,
95 	WDE_DLE_QUEID_DROP_MACID_DROP = 3,
96 	WDE_DLE_QUEID_NO_REPORT = 4
97 };
98 
99 enum rtw89_mac_ple_dle_port_id {
100 	PLE_DLE_PORT_ID_DISPATCH = 0,
101 	PLE_DLE_PORT_ID_MPDU = 1,
102 	PLE_DLE_PORT_ID_SEC = 2,
103 	PLE_DLE_PORT_ID_CMAC0 = 3,
104 	PLE_DLE_PORT_ID_CMAC1 = 4,
105 	PLE_DLE_PORT_ID_WDRLS = 5,
106 	PLE_DLE_PORT_ID_CPU_IO = 6,
107 	PLE_DLE_PORT_ID_PLRLS = 7,
108 	PLE_DLE_PORT_ID_END = 8
109 };
110 
111 enum rtw89_mac_ple_dle_queid_plrls {
112 	PLE_DLE_QUEID_NO_REPORT = 0x0
113 };
114 
115 enum rtw89_machdr_frame_type {
116 	RTW89_MGNT = 0,
117 	RTW89_CTRL = 1,
118 	RTW89_DATA = 2,
119 };
120 
121 enum rtw89_mac_dle_dfi_type {
122 	DLE_DFI_TYPE_FREEPG	= 0,
123 	DLE_DFI_TYPE_QUOTA	= 1,
124 	DLE_DFI_TYPE_PAGELLT	= 2,
125 	DLE_DFI_TYPE_PKTINFO	= 3,
126 	DLE_DFI_TYPE_PREPKTLLT	= 4,
127 	DLE_DFI_TYPE_NXTPKTLLT	= 5,
128 	DLE_DFI_TYPE_QLNKTBL	= 6,
129 	DLE_DFI_TYPE_QEMPTY	= 7,
130 };
131 
132 enum rtw89_mac_dle_wde_quota_id {
133 	WDE_QTAID_HOST_IF = 0,
134 	WDE_QTAID_WLAN_CPU = 1,
135 	WDE_QTAID_DATA_CPU = 2,
136 	WDE_QTAID_PKTIN = 3,
137 	WDE_QTAID_CPUIO = 4,
138 };
139 
140 enum rtw89_mac_dle_ple_quota_id {
141 	PLE_QTAID_B0_TXPL = 0,
142 	PLE_QTAID_B1_TXPL = 1,
143 	PLE_QTAID_C2H = 2,
144 	PLE_QTAID_H2C = 3,
145 	PLE_QTAID_WLAN_CPU = 4,
146 	PLE_QTAID_MPDU = 5,
147 	PLE_QTAID_CMAC0_RX = 6,
148 	PLE_QTAID_CMAC1_RX = 7,
149 	PLE_QTAID_CMAC1_BBRPT = 8,
150 	PLE_QTAID_WDRLS = 9,
151 	PLE_QTAID_CPUIO = 10,
152 };
153 
154 enum rtw89_mac_dle_ctrl_type {
155 	DLE_CTRL_TYPE_WDE = 0,
156 	DLE_CTRL_TYPE_PLE = 1,
157 	DLE_CTRL_TYPE_NUM = 2,
158 };
159 
160 enum rtw89_mac_ax_l0_to_l1_event {
161 	MAC_AX_L0_TO_L1_CHIF_IDLE = 0,
162 	MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1,
163 	MAC_AX_L0_TO_L1_RLS_PKID = 2,
164 	MAC_AX_L0_TO_L1_PTCL_IDLE = 3,
165 	MAC_AX_L0_TO_L1_RX_QTA_LOST = 4,
166 	MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5,
167 	MAC_AX_L0_TO_L1_PCIE_STUCK = 6,
168 	MAC_AX_L0_TO_L1_EVENT_MAX = 15,
169 };
170 
171 #define RTW89_PORT_OFFSET_TU_TO_32US(shift_tu) ((shift_tu) * 1024 / 32)
172 
173 enum rtw89_mac_dbg_port_sel {
174 	/* CMAC 0 related */
175 	RTW89_DBG_PORT_SEL_PTCL_C0 = 0,
176 	RTW89_DBG_PORT_SEL_SCH_C0,
177 	RTW89_DBG_PORT_SEL_TMAC_C0,
178 	RTW89_DBG_PORT_SEL_RMAC_C0,
179 	RTW89_DBG_PORT_SEL_RMACST_C0,
180 	RTW89_DBG_PORT_SEL_RMAC_PLCP_C0,
181 	RTW89_DBG_PORT_SEL_TRXPTCL_C0,
182 	RTW89_DBG_PORT_SEL_TX_INFOL_C0,
183 	RTW89_DBG_PORT_SEL_TX_INFOH_C0,
184 	RTW89_DBG_PORT_SEL_TXTF_INFOL_C0,
185 	RTW89_DBG_PORT_SEL_TXTF_INFOH_C0,
186 	/* CMAC 1 related */
187 	RTW89_DBG_PORT_SEL_PTCL_C1,
188 	RTW89_DBG_PORT_SEL_SCH_C1,
189 	RTW89_DBG_PORT_SEL_TMAC_C1,
190 	RTW89_DBG_PORT_SEL_RMAC_C1,
191 	RTW89_DBG_PORT_SEL_RMACST_C1,
192 	RTW89_DBG_PORT_SEL_RMAC_PLCP_C1,
193 	RTW89_DBG_PORT_SEL_TRXPTCL_C1,
194 	RTW89_DBG_PORT_SEL_TX_INFOL_C1,
195 	RTW89_DBG_PORT_SEL_TX_INFOH_C1,
196 	RTW89_DBG_PORT_SEL_TXTF_INFOL_C1,
197 	RTW89_DBG_PORT_SEL_TXTF_INFOH_C1,
198 	/* DLE related */
199 	RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG,
200 	RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA,
201 	RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT,
202 	RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO,
203 	RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT,
204 	RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT,
205 	RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL,
206 	RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY,
207 	RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG,
208 	RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA,
209 	RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT,
210 	RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO,
211 	RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT,
212 	RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT,
213 	RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL,
214 	RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY,
215 	RTW89_DBG_PORT_SEL_PKTINFO,
216 	/* DISPATCHER related */
217 	RTW89_DBG_PORT_SEL_DSPT_HDT_TX0,
218 	RTW89_DBG_PORT_SEL_DSPT_HDT_TX1,
219 	RTW89_DBG_PORT_SEL_DSPT_HDT_TX2,
220 	RTW89_DBG_PORT_SEL_DSPT_HDT_TX3,
221 	RTW89_DBG_PORT_SEL_DSPT_HDT_TX4,
222 	RTW89_DBG_PORT_SEL_DSPT_HDT_TX5,
223 	RTW89_DBG_PORT_SEL_DSPT_HDT_TX6,
224 	RTW89_DBG_PORT_SEL_DSPT_HDT_TX7,
225 	RTW89_DBG_PORT_SEL_DSPT_HDT_TX8,
226 	RTW89_DBG_PORT_SEL_DSPT_HDT_TX9,
227 	RTW89_DBG_PORT_SEL_DSPT_HDT_TXA,
228 	RTW89_DBG_PORT_SEL_DSPT_HDT_TXB,
229 	RTW89_DBG_PORT_SEL_DSPT_HDT_TXC,
230 	RTW89_DBG_PORT_SEL_DSPT_HDT_TXD,
231 	RTW89_DBG_PORT_SEL_DSPT_HDT_TXE,
232 	RTW89_DBG_PORT_SEL_DSPT_HDT_TXF,
233 	RTW89_DBG_PORT_SEL_DSPT_CDT_TX0,
234 	RTW89_DBG_PORT_SEL_DSPT_CDT_TX1,
235 	RTW89_DBG_PORT_SEL_DSPT_CDT_TX3,
236 	RTW89_DBG_PORT_SEL_DSPT_CDT_TX4,
237 	RTW89_DBG_PORT_SEL_DSPT_CDT_TX5,
238 	RTW89_DBG_PORT_SEL_DSPT_CDT_TX6,
239 	RTW89_DBG_PORT_SEL_DSPT_CDT_TX7,
240 	RTW89_DBG_PORT_SEL_DSPT_CDT_TX8,
241 	RTW89_DBG_PORT_SEL_DSPT_CDT_TX9,
242 	RTW89_DBG_PORT_SEL_DSPT_CDT_TXA,
243 	RTW89_DBG_PORT_SEL_DSPT_CDT_TXB,
244 	RTW89_DBG_PORT_SEL_DSPT_CDT_TXC,
245 	RTW89_DBG_PORT_SEL_DSPT_HDT_RX0,
246 	RTW89_DBG_PORT_SEL_DSPT_HDT_RX1,
247 	RTW89_DBG_PORT_SEL_DSPT_HDT_RX2,
248 	RTW89_DBG_PORT_SEL_DSPT_HDT_RX3,
249 	RTW89_DBG_PORT_SEL_DSPT_HDT_RX4,
250 	RTW89_DBG_PORT_SEL_DSPT_HDT_RX5,
251 	RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0,
252 	RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0,
253 	RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1,
254 	RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2,
255 	RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1,
256 	RTW89_DBG_PORT_SEL_DSPT_STF_CTRL,
257 	RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL,
258 	RTW89_DBG_PORT_SEL_DSPT_WDE_INTF,
259 	RTW89_DBG_PORT_SEL_DSPT_PLE_INTF,
260 	RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL,
261 	/* PCIE related */
262 	RTW89_DBG_PORT_SEL_PCIE_TXDMA,
263 	RTW89_DBG_PORT_SEL_PCIE_RXDMA,
264 	RTW89_DBG_PORT_SEL_PCIE_CVT,
265 	RTW89_DBG_PORT_SEL_PCIE_CXPL,
266 	RTW89_DBG_PORT_SEL_PCIE_IO,
267 	RTW89_DBG_PORT_SEL_PCIE_MISC,
268 	RTW89_DBG_PORT_SEL_PCIE_MISC2,
269 
270 	/* keep last */
271 	RTW89_DBG_PORT_SEL_LAST,
272 	RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST,
273 	RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST,
274 };
275 
276 /* SRAM mem dump */
277 #define R_AX_INDIR_ACCESS_ENTRY 0x40000
278 
279 #define	AXIDMA_BASE_ADDR		0x18006000
280 #define	STA_SCHED_BASE_ADDR		0x18808000
281 #define	RXPLD_FLTR_CAM_BASE_ADDR	0x18813000
282 #define	SECURITY_CAM_BASE_ADDR		0x18814000
283 #define	WOW_CAM_BASE_ADDR		0x18815000
284 #define	CMAC_TBL_BASE_ADDR		0x18840000
285 #define	ADDR_CAM_BASE_ADDR		0x18850000
286 #define	BSSID_CAM_BASE_ADDR		0x18853000
287 #define	BA_CAM_BASE_ADDR		0x18854000
288 #define	BCN_IE_CAM0_BASE_ADDR		0x18855000
289 #define	SHARED_BUF_BASE_ADDR		0x18700000
290 #define	DMAC_TBL_BASE_ADDR		0x18800000
291 #define	SHCUT_MACHDR_BASE_ADDR		0x18800800
292 #define	BCN_IE_CAM1_BASE_ADDR		0x188A0000
293 #define	TXD_FIFO_0_BASE_ADDR		0x18856200
294 #define	TXD_FIFO_1_BASE_ADDR		0x188A1080
295 #define	TXD_FIFO_0_BASE_ADDR_V1		0x18856400 /* for 8852C */
296 #define	TXD_FIFO_1_BASE_ADDR_V1		0x188A1080 /* for 8852C */
297 #define	TXDATA_FIFO_0_BASE_ADDR		0x18856000
298 #define	TXDATA_FIFO_1_BASE_ADDR		0x188A1000
299 #define	CPU_LOCAL_BASE_ADDR		0x18003000
300 
301 #define CCTL_INFO_SIZE		32
302 
303 enum rtw89_mac_mem_sel {
304 	RTW89_MAC_MEM_AXIDMA,
305 	RTW89_MAC_MEM_SHARED_BUF,
306 	RTW89_MAC_MEM_DMAC_TBL,
307 	RTW89_MAC_MEM_SHCUT_MACHDR,
308 	RTW89_MAC_MEM_STA_SCHED,
309 	RTW89_MAC_MEM_RXPLD_FLTR_CAM,
310 	RTW89_MAC_MEM_SECURITY_CAM,
311 	RTW89_MAC_MEM_WOW_CAM,
312 	RTW89_MAC_MEM_CMAC_TBL,
313 	RTW89_MAC_MEM_ADDR_CAM,
314 	RTW89_MAC_MEM_BA_CAM,
315 	RTW89_MAC_MEM_BCN_IE_CAM0,
316 	RTW89_MAC_MEM_BCN_IE_CAM1,
317 	RTW89_MAC_MEM_TXD_FIFO_0,
318 	RTW89_MAC_MEM_TXD_FIFO_1,
319 	RTW89_MAC_MEM_TXDATA_FIFO_0,
320 	RTW89_MAC_MEM_TXDATA_FIFO_1,
321 	RTW89_MAC_MEM_CPU_LOCAL,
322 	RTW89_MAC_MEM_BSSID_CAM,
323 	RTW89_MAC_MEM_TXD_FIFO_0_V1,
324 	RTW89_MAC_MEM_TXD_FIFO_1_V1,
325 
326 	/* keep last */
327 	RTW89_MAC_MEM_NUM,
328 };
329 
330 extern const u32 rtw89_mac_mem_base_addrs[];
331 
332 enum rtw89_rpwm_req_pwr_state {
333 	RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0,
334 	RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1,
335 	RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2,
336 	RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3,
337 	RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4,
338 	RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5,
339 	RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6,
340 	RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7,
341 	RTW89_MAC_RPWM_REQ_PWR_STATE_MAX,
342 };
343 
344 struct rtw89_pwr_cfg {
345 	u16 addr;
346 	u8 cv_msk;
347 	u8 intf_msk;
348 	u8 base:4;
349 	u8 cmd:4;
350 	u8 msk;
351 	u8 val;
352 };
353 
354 enum rtw89_mac_c2h_ofld_func {
355 	RTW89_MAC_C2H_FUNC_EFUSE_DUMP,
356 	RTW89_MAC_C2H_FUNC_READ_RSP,
357 	RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP,
358 	RTW89_MAC_C2H_FUNC_BCN_RESEND,
359 	RTW89_MAC_C2H_FUNC_MACID_PAUSE,
360 	RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6,
361 	RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9,
362 	RTW89_MAC_C2H_FUNC_OFLD_MAX,
363 };
364 
365 enum rtw89_mac_c2h_info_func {
366 	RTW89_MAC_C2H_FUNC_REC_ACK,
367 	RTW89_MAC_C2H_FUNC_DONE_ACK,
368 	RTW89_MAC_C2H_FUNC_C2H_LOG,
369 	RTW89_MAC_C2H_FUNC_BCN_CNT,
370 	RTW89_MAC_C2H_FUNC_INFO_MAX,
371 };
372 
373 enum rtw89_mac_c2h_mcc_func {
374 	RTW89_MAC_C2H_FUNC_MCC_RCV_ACK = 0,
375 	RTW89_MAC_C2H_FUNC_MCC_REQ_ACK = 1,
376 	RTW89_MAC_C2H_FUNC_MCC_TSF_RPT = 2,
377 	RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT = 3,
378 
379 	NUM_OF_RTW89_MAC_C2H_FUNC_MCC,
380 };
381 
382 enum rtw89_mac_c2h_class {
383 	RTW89_MAC_C2H_CLASS_INFO,
384 	RTW89_MAC_C2H_CLASS_OFLD,
385 	RTW89_MAC_C2H_CLASS_TWT,
386 	RTW89_MAC_C2H_CLASS_WOW,
387 	RTW89_MAC_C2H_CLASS_MCC,
388 	RTW89_MAC_C2H_CLASS_FWDBG,
389 	RTW89_MAC_C2H_CLASS_MAX,
390 };
391 
392 enum rtw89_mac_mcc_status {
393 	RTW89_MAC_MCC_ADD_ROLE_OK = 0,
394 	RTW89_MAC_MCC_START_GROUP_OK = 1,
395 	RTW89_MAC_MCC_STOP_GROUP_OK = 2,
396 	RTW89_MAC_MCC_DEL_GROUP_OK = 3,
397 	RTW89_MAC_MCC_RESET_GROUP_OK = 4,
398 	RTW89_MAC_MCC_SWITCH_CH_OK = 5,
399 	RTW89_MAC_MCC_TXNULL0_OK = 6,
400 	RTW89_MAC_MCC_TXNULL1_OK = 7,
401 
402 	RTW89_MAC_MCC_SWITCH_EARLY = 10,
403 	RTW89_MAC_MCC_TBTT = 11,
404 	RTW89_MAC_MCC_DURATION_START = 12,
405 	RTW89_MAC_MCC_DURATION_END = 13,
406 
407 	RTW89_MAC_MCC_ADD_ROLE_FAIL = 20,
408 	RTW89_MAC_MCC_START_GROUP_FAIL = 21,
409 	RTW89_MAC_MCC_STOP_GROUP_FAIL = 22,
410 	RTW89_MAC_MCC_DEL_GROUP_FAIL = 23,
411 	RTW89_MAC_MCC_RESET_GROUP_FAIL = 24,
412 	RTW89_MAC_MCC_SWITCH_CH_FAIL = 25,
413 	RTW89_MAC_MCC_TXNULL0_FAIL = 26,
414 	RTW89_MAC_MCC_TXNULL1_FAIL = 27,
415 };
416 
417 struct rtw89_mac_ax_coex {
418 #define RTW89_MAC_AX_COEX_RTK_MODE 0
419 #define RTW89_MAC_AX_COEX_CSR_MODE 1
420 	u8 pta_mode;
421 #define RTW89_MAC_AX_COEX_INNER 0
422 #define RTW89_MAC_AX_COEX_OUTPUT 1
423 #define RTW89_MAC_AX_COEX_INPUT 2
424 	u8 direction;
425 };
426 
427 struct rtw89_mac_ax_plt {
428 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0)
429 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1)
430 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2)
431 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3)
432 	u8 band;
433 	u8 tx;
434 	u8 rx;
435 };
436 
437 enum rtw89_mac_bf_rrsc_rate {
438 	RTW89_MAC_BF_RRSC_6M = 0,
439 	RTW89_MAC_BF_RRSC_9M = 1,
440 	RTW89_MAC_BF_RRSC_12M,
441 	RTW89_MAC_BF_RRSC_18M,
442 	RTW89_MAC_BF_RRSC_24M,
443 	RTW89_MAC_BF_RRSC_36M,
444 	RTW89_MAC_BF_RRSC_48M,
445 	RTW89_MAC_BF_RRSC_54M,
446 	RTW89_MAC_BF_RRSC_HT_MSC0,
447 	RTW89_MAC_BF_RRSC_HT_MSC1,
448 	RTW89_MAC_BF_RRSC_HT_MSC2,
449 	RTW89_MAC_BF_RRSC_HT_MSC3,
450 	RTW89_MAC_BF_RRSC_HT_MSC4,
451 	RTW89_MAC_BF_RRSC_HT_MSC5,
452 	RTW89_MAC_BF_RRSC_HT_MSC6,
453 	RTW89_MAC_BF_RRSC_HT_MSC7,
454 	RTW89_MAC_BF_RRSC_VHT_MSC0,
455 	RTW89_MAC_BF_RRSC_VHT_MSC1,
456 	RTW89_MAC_BF_RRSC_VHT_MSC2,
457 	RTW89_MAC_BF_RRSC_VHT_MSC3,
458 	RTW89_MAC_BF_RRSC_VHT_MSC4,
459 	RTW89_MAC_BF_RRSC_VHT_MSC5,
460 	RTW89_MAC_BF_RRSC_VHT_MSC6,
461 	RTW89_MAC_BF_RRSC_VHT_MSC7,
462 	RTW89_MAC_BF_RRSC_HE_MSC0,
463 	RTW89_MAC_BF_RRSC_HE_MSC1,
464 	RTW89_MAC_BF_RRSC_HE_MSC2,
465 	RTW89_MAC_BF_RRSC_HE_MSC3,
466 	RTW89_MAC_BF_RRSC_HE_MSC4,
467 	RTW89_MAC_BF_RRSC_HE_MSC5,
468 	RTW89_MAC_BF_RRSC_HE_MSC6,
469 	RTW89_MAC_BF_RRSC_HE_MSC7 = 31,
470 	RTW89_MAC_BF_RRSC_MAX = 32
471 };
472 
473 #define RTW89_R32_EA		0xEAEAEAEA
474 #define RTW89_R32_DEAD		0xDEADBEEF
475 #define MAC_REG_POOL_COUNT	10
476 #define ACCESS_CMAC(_addr) \
477 	({typeof(_addr) __addr = (_addr); \
478 	  __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; })
479 #define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000
480 
481 #define PTCL_IDLE_POLL_CNT	10000
482 #define SW_CVR_DUR_US	8
483 #define SW_CVR_CNT	8
484 
485 #define DLE_BOUND_UNIT (8 * 1024)
486 #define DLE_WAIT_CNT 2000
487 #define TRXCFG_WAIT_CNT	2000
488 
489 #define RTW89_WDE_PG_64		64
490 #define RTW89_WDE_PG_128	128
491 #define RTW89_WDE_PG_256	256
492 
493 #define S_AX_WDE_PAGE_SEL_64	0
494 #define S_AX_WDE_PAGE_SEL_128	1
495 #define S_AX_WDE_PAGE_SEL_256	2
496 
497 #define RTW89_PLE_PG_64		64
498 #define RTW89_PLE_PG_128	128
499 #define RTW89_PLE_PG_256	256
500 
501 #define S_AX_PLE_PAGE_SEL_64	0
502 #define S_AX_PLE_PAGE_SEL_128	1
503 #define S_AX_PLE_PAGE_SEL_256	2
504 
505 #define B_CMAC0_MGQ_NORMAL	BIT(2)
506 #define B_CMAC0_MGQ_NO_PWRSAV	BIT(3)
507 #define B_CMAC0_CPUMGQ		BIT(4)
508 #define B_CMAC1_MGQ_NORMAL	BIT(10)
509 #define B_CMAC1_MGQ_NO_PWRSAV	BIT(11)
510 #define B_CMAC1_CPUMGQ		BIT(12)
511 
512 #define QEMP_ACQ_GRP_MACID_NUM	8
513 #define QEMP_ACQ_GRP_QSEL_SH	4
514 #define QEMP_ACQ_GRP_QSEL_MASK	0xF
515 
516 #define SDIO_LOCAL_BASE_ADDR    0x80000000
517 
518 #define	PWR_CMD_WRITE		0
519 #define	PWR_CMD_POLL		1
520 #define	PWR_CMD_DELAY		2
521 #define	PWR_CMD_END		3
522 
523 #define	PWR_INTF_MSK_SDIO	BIT(0)
524 #define	PWR_INTF_MSK_USB	BIT(1)
525 #define	PWR_INTF_MSK_PCIE	BIT(2)
526 #define	PWR_INTF_MSK_ALL	0x7
527 
528 #define PWR_BASE_MAC		0
529 #define PWR_BASE_USB		1
530 #define PWR_BASE_PCIE		2
531 #define PWR_BASE_SDIO		3
532 
533 #define	PWR_CV_MSK_A		BIT(0)
534 #define	PWR_CV_MSK_B		BIT(1)
535 #define	PWR_CV_MSK_C		BIT(2)
536 #define	PWR_CV_MSK_D		BIT(3)
537 #define	PWR_CV_MSK_E		BIT(4)
538 #define	PWR_CV_MSK_F		BIT(5)
539 #define	PWR_CV_MSK_G		BIT(6)
540 #define	PWR_CV_MSK_TEST		BIT(7)
541 #define	PWR_CV_MSK_ALL		0xFF
542 
543 #define	PWR_DELAY_US		0
544 #define	PWR_DELAY_MS		1
545 
546 /* STA scheduler */
547 #define SS_MACID_SH		8
548 #define SS_TX_LEN_MSK		0x1FFFFF
549 #define SS_CTRL1_R_TX_LEN	5
550 #define SS_CTRL1_R_NEXT_LINK	20
551 #define SS_LINK_SIZE		256
552 
553 /* MAC debug port */
554 #define TMAC_DBG_SEL_C0 0xA5
555 #define RMAC_DBG_SEL_C0 0xA6
556 #define TRXPTCL_DBG_SEL_C0 0xA7
557 #define TMAC_DBG_SEL_C1 0xB5
558 #define RMAC_DBG_SEL_C1 0xB6
559 #define TRXPTCL_DBG_SEL_C1 0xB7
560 #define FW_PROG_CNTR_DBG_SEL 0xF2
561 #define PCIE_TXDMA_DBG_SEL 0x30
562 #define PCIE_RXDMA_DBG_SEL 0x31
563 #define PCIE_CVT_DBG_SEL 0x32
564 #define PCIE_CXPL_DBG_SEL 0x33
565 #define PCIE_IO_DBG_SEL 0x37
566 #define PCIE_MISC_DBG_SEL 0x38
567 #define PCIE_MISC2_DBG_SEL 0x00
568 #define MAC_DBG_SEL 1
569 #define RMAC_CMAC_DBG_SEL 1
570 
571 /* TRXPTCL dbg port sel */
572 #define TRXPTRL_DBG_SEL_TMAC 0
573 #define TRXPTRL_DBG_SEL_RMAC 1
574 
575 struct rtw89_cpuio_ctrl {
576 	u16 pkt_num;
577 	u16 start_pktid;
578 	u16 end_pktid;
579 	u8 cmd_type;
580 	u8 macid;
581 	u8 src_pid;
582 	u8 src_qid;
583 	u8 dst_pid;
584 	u8 dst_qid;
585 	u16 pktid;
586 };
587 
588 struct rtw89_mac_dbg_port_info {
589 	u32 sel_addr;
590 	u8 sel_byte;
591 	u32 sel_msk;
592 	u32 srt;
593 	u32 end;
594 	u32 rd_addr;
595 	u8 rd_byte;
596 	u32 rd_msk;
597 };
598 
599 #define QLNKTBL_ADDR_INFO_SEL BIT(0)
600 #define QLNKTBL_ADDR_INFO_SEL_0 0
601 #define QLNKTBL_ADDR_INFO_SEL_1 1
602 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1)
603 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0)
604 
605 struct rtw89_mac_dle_dfi_ctrl {
606 	enum rtw89_mac_dle_ctrl_type type;
607 	u32 target;
608 	u32 addr;
609 	u32 out_data;
610 };
611 
612 struct rtw89_mac_dle_dfi_quota {
613 	enum rtw89_mac_dle_ctrl_type dle_type;
614 	u32 qtaid;
615 	u16 rsv_pgnum;
616 	u16 use_pgnum;
617 };
618 
619 struct rtw89_mac_dle_dfi_qempty {
620 	enum rtw89_mac_dle_ctrl_type dle_type;
621 	u32 grpsel;
622 	u32 qempty;
623 };
624 
625 enum rtw89_mac_error_scenario {
626 	RTW89_RXI300_ERROR		= 1,
627 	RTW89_WCPU_CPU_EXCEPTION	= 2,
628 	RTW89_WCPU_ASSERTION		= 3,
629 };
630 
631 #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28)
632 
633 /* Define DBG and recovery enum */
634 enum mac_ax_err_info {
635 	/* Get error info */
636 
637 	/* L0 */
638 	MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001,
639 	MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002,
640 	MAC_AX_ERR_L0_RESET_DONE = 0x0003,
641 	MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010,
642 
643 	/* L1 */
644 	MAC_AX_ERR_L1_ERR_DMAC = 0x1000,
645 	MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001,
646 	MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002,
647 	MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010,
648 	MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011,
649 
650 	/* L2 */
651 	/* address hole (master) */
652 	MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000,
653 	MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010,
654 	MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020,
655 	MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030,
656 	MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040,
657 	MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050,
658 	MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060,
659 	MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070,
660 
661 	/* AHB bridge timeout (master) */
662 	MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100,
663 	MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110,
664 	MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120,
665 	MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130,
666 	MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140,
667 	MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150,
668 	MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160,
669 	MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170,
670 
671 	/* APB_SA bridge timeout (master + slave) */
672 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200,
673 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201,
674 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202,
675 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203,
676 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204,
677 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205,
678 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206,
679 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207,
680 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208,
681 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209,
682 	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A,
683 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210,
684 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211,
685 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212,
686 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213,
687 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214,
688 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215,
689 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216,
690 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218,
691 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219,
692 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A,
693 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220,
694 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221,
695 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222,
696 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223,
697 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224,
698 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225,
699 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226,
700 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227,
701 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228,
702 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229,
703 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A,
704 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230,
705 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231,
706 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232,
707 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233,
708 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234,
709 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235,
710 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236,
711 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237,
712 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238,
713 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239,
714 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A,
715 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240,
716 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241,
717 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242,
718 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243,
719 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244,
720 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245,
721 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246,
722 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247,
723 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248,
724 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249,
725 	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A,
726 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250,
727 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251,
728 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252,
729 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253,
730 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254,
731 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255,
732 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256,
733 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257,
734 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258,
735 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259,
736 	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A,
737 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260,
738 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261,
739 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262,
740 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263,
741 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264,
742 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265,
743 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266,
744 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267,
745 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268,
746 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269,
747 	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A,
748 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270,
749 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271,
750 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272,
751 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273,
752 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274,
753 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275,
754 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276,
755 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277,
756 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278,
757 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279,
758 	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A,
759 
760 	/* APB_BBRF bridge timeout (master) */
761 	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300,
762 	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310,
763 	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320,
764 	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330,
765 	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340,
766 	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350,
767 	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360,
768 	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370,
769 	MAC_AX_ERR_L2_RESET_DONE = 0x2400,
770 	MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599,
771 	MAC_AX_ERR_CPU_EXCEPTION = 0x3000,
772 	MAC_AX_ERR_ASSERTION = 0x4000,
773 	MAC_AX_ERR_RXI300 = 0x5000,
774 	MAC_AX_GET_ERR_MAX,
775 	MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000,
776 
777 	/* set error info */
778 	MAC_AX_ERR_L1_DISABLE_EN = 0x0001,
779 	MAC_AX_ERR_L1_RCVY_EN = 0x0002,
780 	MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003,
781 	MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004,
782 	MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010,
783 	MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011,
784 	MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012,
785 	MAC_AX_ERR_L0_RCVY_EN = 0x0013,
786 	MAC_AX_SET_ERR_MAX,
787 };
788 
789 struct rtw89_mac_size_set {
790 	const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie;
791 	const struct rtw89_dle_size wde_size0;
792 	const struct rtw89_dle_size wde_size4;
793 	const struct rtw89_dle_size wde_size6;
794 	const struct rtw89_dle_size wde_size9;
795 	const struct rtw89_dle_size wde_size18;
796 	const struct rtw89_dle_size wde_size19;
797 	const struct rtw89_dle_size ple_size0;
798 	const struct rtw89_dle_size ple_size4;
799 	const struct rtw89_dle_size ple_size6;
800 	const struct rtw89_dle_size ple_size8;
801 	const struct rtw89_dle_size ple_size18;
802 	const struct rtw89_dle_size ple_size19;
803 	const struct rtw89_wde_quota wde_qt0;
804 	const struct rtw89_wde_quota wde_qt4;
805 	const struct rtw89_wde_quota wde_qt6;
806 	const struct rtw89_wde_quota wde_qt17;
807 	const struct rtw89_wde_quota wde_qt18;
808 	const struct rtw89_ple_quota ple_qt4;
809 	const struct rtw89_ple_quota ple_qt5;
810 	const struct rtw89_ple_quota ple_qt13;
811 	const struct rtw89_ple_quota ple_qt18;
812 	const struct rtw89_ple_quota ple_qt44;
813 	const struct rtw89_ple_quota ple_qt45;
814 	const struct rtw89_ple_quota ple_qt46;
815 	const struct rtw89_ple_quota ple_qt47;
816 	const struct rtw89_ple_quota ple_qt58;
817 	const struct rtw89_ple_quota ple_qt_52a_wow;
818 };
819 
820 extern const struct rtw89_mac_size_set rtw89_mac_size;
821 
822 static inline u32 rtw89_mac_reg_by_idx(u32 reg_base, u8 band)
823 {
824 	return band == 0 ? reg_base : (reg_base + 0x2000);
825 }
826 
827 static inline u32 rtw89_mac_reg_by_port(u32 base, u8 port, u8 mac_idx)
828 {
829 	return rtw89_mac_reg_by_idx(base + port * 0x40, mac_idx);
830 }
831 
832 static inline u32
833 rtw89_read32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base)
834 {
835 	u32 reg;
836 
837 	reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
838 	return rtw89_read32(rtwdev, reg);
839 }
840 
841 static inline u32
842 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
843 		       u32 base, u32 mask)
844 {
845 	u32 reg;
846 
847 	reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
848 	return rtw89_read32_mask(rtwdev, reg, mask);
849 }
850 
851 static inline void
852 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base,
853 		   u32 data)
854 {
855 	u32 reg;
856 
857 	reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
858 	rtw89_write32(rtwdev, reg, data);
859 }
860 
861 static inline void
862 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
863 			u32 base, u32 mask, u32 data)
864 {
865 	u32 reg;
866 
867 	reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
868 	rtw89_write32_mask(rtwdev, reg, mask, data);
869 }
870 
871 static inline void
872 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
873 			u32 base, u32 mask, u16 data)
874 {
875 	u32 reg;
876 
877 	reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
878 	rtw89_write16_mask(rtwdev, reg, mask, data);
879 }
880 
881 static inline void
882 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
883 		       u32 base, u32 bit)
884 {
885 	u32 reg;
886 
887 	reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
888 	rtw89_write32_clr(rtwdev, reg, bit);
889 }
890 
891 static inline void
892 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
893 		       u32 base, u16 bit)
894 {
895 	u32 reg;
896 
897 	reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
898 	rtw89_write16_clr(rtwdev, reg, bit);
899 }
900 
901 static inline void
902 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
903 		       u32 base, u32 bit)
904 {
905 	u32 reg;
906 
907 	reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
908 	rtw89_write32_set(rtwdev, reg, bit);
909 }
910 
911 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev);
912 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev);
913 int rtw89_mac_init(struct rtw89_dev *rtwdev);
914 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band,
915 			   enum rtw89_mac_hwmod_sel sel);
916 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val);
917 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val);
918 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
919 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
920 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev,
921 			     struct rtw89_vif *rtwvif,
922 			     struct rtw89_vif *rtwvif_src,
923 			     u16 offset_tu);
924 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
925 			   u64 *tsf);
926 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev,
927 					struct ieee80211_vif *vif);
928 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
929 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
930 void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev);
931 int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw);
932 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev);
933 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev);
934 
935 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev)
936 {
937 	const struct rtw89_chip_info *chip = rtwdev->chip;
938 
939 	return chip->ops->enable_bb_rf(rtwdev);
940 }
941 
942 static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev)
943 {
944 	const struct rtw89_chip_info *chip = rtwdev->chip;
945 
946 	return chip->ops->disable_bb_rf(rtwdev);
947 }
948 
949 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev);
950 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err);
951 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func);
952 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
953 			  u32 len, u8 class, u8 func);
954 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev);
955 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
956 			  u32 *tx_en, enum rtw89_sch_tx_sel sel);
957 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
958 			     u32 *tx_en, enum rtw89_sch_tx_sel sel);
959 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
960 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
961 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_ids, bool enable);
962 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx);
963 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop);
964 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex);
965 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev,
966 			   const struct rtw89_mac_ax_coex *coex);
967 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
968 		      const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
969 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev,
970 			 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
971 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt);
972 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band);
973 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val);
974 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev);
975 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev);
976 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl);
977 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl);
978 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev,
979 			    enum rtw89_phy_idx phy_idx,
980 			    u32 reg_base, u32 *cr);
981 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter);
982 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev);
983 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
984 			struct ieee80211_sta *sta);
985 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
986 			   struct ieee80211_sta *sta);
987 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
988 				struct ieee80211_bss_conf *conf);
989 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev,
990 			       struct ieee80211_sta *sta, bool disconnect);
991 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev);
992 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
993 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
994 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
995 				 struct rtw89_vif *rtwvif, bool en);
996 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause);
997 
998 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)
999 {
1000 	if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags))
1001 		return;
1002 
1003 	_rtw89_mac_bf_monitor_track(rtwdev);
1004 }
1005 
1006 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev,
1007 					 enum rtw89_phy_idx phy_idx,
1008 					 u32 reg_base, u32 *val)
1009 {
1010 	u32 cr;
1011 
1012 	if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1013 		return -EINVAL;
1014 
1015 	*val = rtw89_read32(rtwdev, cr);
1016 	return 0;
1017 }
1018 
1019 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev,
1020 					  enum rtw89_phy_idx phy_idx,
1021 					  u32 reg_base, u32 val)
1022 {
1023 	u32 cr;
1024 
1025 	if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1026 		return -EINVAL;
1027 
1028 	rtw89_write32(rtwdev, cr, val);
1029 	return 0;
1030 }
1031 
1032 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev,
1033 					       enum rtw89_phy_idx phy_idx,
1034 					       u32 reg_base, u32 mask, u32 val)
1035 {
1036 	u32 cr;
1037 
1038 	if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1039 		return -EINVAL;
1040 
1041 	rtw89_write32_mask(rtwdev, cr, mask, val);
1042 	return 0;
1043 }
1044 
1045 static inline void rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev *rtwdev,
1046 					     bool enable)
1047 {
1048 	const struct rtw89_chip_info *chip = rtwdev->chip;
1049 
1050 	if (enable)
1051 		rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1052 				  B_AX_HCI_TXDMA_EN);
1053 	else
1054 		rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1055 				  B_AX_HCI_TXDMA_EN);
1056 }
1057 
1058 static inline void rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev *rtwdev,
1059 					     bool enable)
1060 {
1061 	const struct rtw89_chip_info *chip = rtwdev->chip;
1062 
1063 	if (enable)
1064 		rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1065 				  B_AX_HCI_RXDMA_EN);
1066 	else
1067 		rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1068 				  B_AX_HCI_RXDMA_EN);
1069 }
1070 
1071 static inline void rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev *rtwdev,
1072 					      bool enable)
1073 {
1074 	const struct rtw89_chip_info *chip = rtwdev->chip;
1075 
1076 	if (enable)
1077 		rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1078 				  B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
1079 	else
1080 		rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1081 				  B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
1082 }
1083 
1084 static inline bool rtw89_mac_get_power_state(struct rtw89_dev *rtwdev)
1085 {
1086 	u32 val;
1087 
1088 	val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE,
1089 				B_AX_WLMAC_PWR_STE_MASK);
1090 
1091 	return !!val;
1092 }
1093 
1094 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
1095 			  bool resume, u32 tx_time);
1096 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
1097 			  u32 *tx_time);
1098 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev,
1099 				 struct rtw89_sta *rtwsta,
1100 				 bool resume, u8 tx_retry);
1101 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
1102 				 struct rtw89_sta *rtwsta, u8 *tx_retry);
1103 
1104 enum rtw89_mac_xtal_si_offset {
1105 	XTAL0 = 0x0,
1106 	XTAL3 = 0x3,
1107 	XTAL_SI_XTAL_SC_XI = 0x04,
1108 #define XTAL_SC_XI_MASK		GENMASK(7, 0)
1109 	XTAL_SI_XTAL_SC_XO = 0x05,
1110 #define XTAL_SC_XO_MASK		GENMASK(7, 0)
1111 	XTAL_SI_PWR_CUT = 0x10,
1112 #define XTAL_SI_SMALL_PWR_CUT	BIT(0)
1113 #define XTAL_SI_BIG_PWR_CUT	BIT(1)
1114 	XTAL_SI_XTAL_XMD_2 = 0x24,
1115 #define XTAL_SI_LDO_LPS		GENMASK(6, 4)
1116 	XTAL_SI_XTAL_XMD_4 = 0x26,
1117 #define XTAL_SI_LPS_CAP		GENMASK(3, 0)
1118 	XTAL_SI_CV = 0x41,
1119 	XTAL_SI_LOW_ADDR = 0x62,
1120 #define XTAL_SI_LOW_ADDR_MASK	GENMASK(7, 0)
1121 	XTAL_SI_CTRL = 0x63,
1122 #define XTAL_SI_MODE_SEL_MASK	GENMASK(7, 6)
1123 #define XTAL_SI_RDY		BIT(5)
1124 #define XTAL_SI_HIGH_ADDR_MASK	GENMASK(2, 0)
1125 	XTAL_SI_READ_VAL = 0x7A,
1126 	XTAL_SI_WL_RFC_S0 = 0x80,
1127 #define XTAL_SI_RF00S_EN	GENMASK(2, 0)
1128 #define XTAL_SI_RF00		BIT(0)
1129 	XTAL_SI_WL_RFC_S1 = 0x81,
1130 #define XTAL_SI_RF10S_EN	GENMASK(2, 0)
1131 #define XTAL_SI_RF10		BIT(0)
1132 	XTAL_SI_ANAPAR_WL = 0x90,
1133 #define XTAL_SI_SRAM2RFC	BIT(7)
1134 #define XTAL_SI_GND_SHDN_WL	BIT(6)
1135 #define XTAL_SI_SHDN_WL		BIT(5)
1136 #define XTAL_SI_RFC2RF		BIT(4)
1137 #define XTAL_SI_OFF_EI		BIT(3)
1138 #define XTAL_SI_OFF_WEI		BIT(2)
1139 #define XTAL_SI_PON_EI		BIT(1)
1140 #define XTAL_SI_PON_WEI		BIT(0)
1141 	XTAL_SI_SRAM_CTRL = 0xA1,
1142 #define XTAL_SI_SRAM_DIS	BIT(1)
1143 #define FULL_BIT_MASK		GENMASK(7, 0)
1144 };
1145 
1146 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask);
1147 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val);
1148 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1149 u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd);
1150 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev,
1151 			struct rtw89_cpuio_ctrl *ctrl_para, bool wd);
1152 int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev,
1153 			   enum rtw89_machdr_frame_type type,
1154 			   enum rtw89_mac_fwd_target fwd_target, u8 mac_idx);
1155 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow);
1156 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,
1157 					enum rtw89_mac_idx band);
1158 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow);
1159 
1160 #endif
1161