1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "fw.h" 9 #include "mac.h" 10 #include "pci.h" 11 #include "ps.h" 12 #include "reg.h" 13 #include "util.h" 14 15 const u32 rtw89_mac_mem_base_addrs[RTW89_MAC_MEM_NUM] = { 16 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 17 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 18 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 19 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 20 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 21 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 22 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 23 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 24 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 25 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 26 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 28 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 29 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 30 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 31 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 32 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 33 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 34 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 35 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 36 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 37 }; 38 39 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 40 u32 val, enum rtw89_mac_mem_sel sel) 41 { 42 u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; 43 44 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); 45 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, val); 46 } 47 48 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 49 enum rtw89_mac_mem_sel sel) 50 { 51 u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; 52 53 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); 54 return rtw89_read32(rtwdev, R_AX_INDIR_ACCESS_ENTRY); 55 } 56 57 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, 58 enum rtw89_mac_hwmod_sel sel) 59 { 60 u32 val, r_val; 61 62 if (sel == RTW89_DMAC_SEL) { 63 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 64 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 65 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 66 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 67 val = B_AX_CMAC_EN; 68 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 69 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 70 val = B_AX_CMAC1_FEN; 71 } else { 72 return -EINVAL; 73 } 74 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 75 (val & r_val) != val) 76 return -EFAULT; 77 78 return 0; 79 } 80 81 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 82 { 83 u8 lte_ctrl; 84 int ret; 85 86 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 87 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 88 if (ret) 89 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 90 91 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 92 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 93 94 return ret; 95 } 96 97 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 98 { 99 u8 lte_ctrl; 100 int ret; 101 102 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 103 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 104 if (ret) 105 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 106 107 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 108 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 109 110 return ret; 111 } 112 113 static 114 int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 115 { 116 u32 ctrl_reg, data_reg, ctrl_data; 117 u32 val; 118 int ret; 119 120 switch (ctrl->type) { 121 case DLE_CTRL_TYPE_WDE: 122 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 123 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 124 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 125 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 126 B_AX_WDE_DFI_ACTIVE; 127 break; 128 case DLE_CTRL_TYPE_PLE: 129 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 130 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 131 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 132 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 133 B_AX_PLE_DFI_ACTIVE; 134 break; 135 default: 136 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 137 return -EINVAL; 138 } 139 140 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 141 142 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 143 1, 1000, false, rtwdev, ctrl_reg); 144 if (ret) { 145 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 146 ctrl_reg, ctrl_data); 147 return ret; 148 } 149 150 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 151 return 0; 152 } 153 154 static int dle_dfi_quota(struct rtw89_dev *rtwdev, 155 struct rtw89_mac_dle_dfi_quota *quota) 156 { 157 struct rtw89_mac_dle_dfi_ctrl ctrl; 158 int ret; 159 160 ctrl.type = quota->dle_type; 161 ctrl.target = DLE_DFI_TYPE_QUOTA; 162 ctrl.addr = quota->qtaid; 163 ret = dle_dfi_ctrl(rtwdev, &ctrl); 164 if (ret) { 165 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 166 return ret; 167 } 168 169 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 170 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 171 return 0; 172 } 173 174 static int dle_dfi_qempty(struct rtw89_dev *rtwdev, 175 struct rtw89_mac_dle_dfi_qempty *qempty) 176 { 177 struct rtw89_mac_dle_dfi_ctrl ctrl; 178 u32 ret; 179 180 ctrl.type = qempty->dle_type; 181 ctrl.target = DLE_DFI_TYPE_QEMPTY; 182 ctrl.addr = qempty->grpsel; 183 ret = dle_dfi_ctrl(rtwdev, &ctrl); 184 if (ret) { 185 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 186 return ret; 187 } 188 189 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 190 return 0; 191 } 192 193 static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev) 194 { 195 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 196 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 197 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 198 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 199 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 200 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 201 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 202 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 203 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 204 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 205 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 206 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 207 } 208 209 static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) 210 { 211 struct rtw89_mac_dle_dfi_qempty qempty; 212 struct rtw89_mac_dle_dfi_quota quota; 213 struct rtw89_mac_dle_dfi_ctrl ctrl; 214 u32 val, not_empty, i; 215 int ret; 216 217 qempty.dle_type = DLE_CTRL_TYPE_PLE; 218 qempty.grpsel = 0; 219 qempty.qempty = ~(u32)0; 220 ret = dle_dfi_qempty(rtwdev, &qempty); 221 if (ret) 222 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 223 else 224 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 225 226 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 227 if (!(not_empty & BIT(0))) 228 continue; 229 ctrl.type = DLE_CTRL_TYPE_PLE; 230 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 231 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 232 FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i); 233 ret = dle_dfi_ctrl(rtwdev, &ctrl); 234 if (ret) 235 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 236 else 237 rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i, 238 FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK, 239 ctrl.out_data)); 240 } 241 242 quota.dle_type = DLE_CTRL_TYPE_PLE; 243 quota.qtaid = 6; 244 ret = dle_dfi_quota(rtwdev, "a); 245 if (ret) 246 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 247 else 248 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 249 quota.rsv_pgnum, quota.use_pgnum); 250 251 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 252 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n", 253 FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val)); 254 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n", 255 FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val)); 256 257 dump_err_status_dispatcher(rtwdev); 258 } 259 260 static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 261 enum mac_ax_err_info err) 262 { 263 u32 dbg, event; 264 265 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 266 event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg); 267 268 switch (event) { 269 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 270 rtw89_info(rtwdev, "quota lost!\n"); 271 rtw89_mac_dump_qta_lost(rtwdev); 272 break; 273 default: 274 break; 275 } 276 } 277 278 static void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 279 { 280 const struct rtw89_chip_info *chip = rtwdev->chip; 281 u32 dmac_err; 282 int i, ret; 283 284 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 285 if (ret) { 286 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 287 return; 288 } 289 290 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 291 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 292 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 293 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 294 295 if (dmac_err) { 296 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 298 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 299 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 300 if (chip->chip_id == RTL8852C) { 301 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 302 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 303 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 304 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 305 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 306 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 307 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 308 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 309 } 310 } 311 312 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 313 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 314 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 315 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 316 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 317 if (chip->chip_id == RTL8852C) 318 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 319 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 320 else 321 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 322 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 323 } 324 325 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 326 if (chip->chip_id == RTL8852C) { 327 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 328 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 329 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 330 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 331 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 332 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 333 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 334 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 335 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 336 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 337 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 338 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 339 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 340 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 341 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 343 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 344 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 345 346 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 347 B_AX_DBG_SEL0, 0x8B); 348 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 349 B_AX_DBG_SEL1, 0x8B); 350 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 351 B_AX_SEL_0XC0_MASK, 1); 352 for (i = 0; i < 0x10; i++) { 353 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 354 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 355 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 356 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 357 } 358 } else { 359 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 360 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 361 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 362 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 363 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 364 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 365 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 366 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 367 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 368 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 369 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 370 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 371 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 372 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 373 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 374 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 375 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 376 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 377 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 378 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 379 } 380 } 381 382 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 383 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 384 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 385 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 386 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 387 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 388 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 389 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 390 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 391 } 392 393 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 394 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 395 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 396 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 397 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 398 } 399 400 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 401 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 402 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 403 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 404 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 405 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 406 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 407 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 408 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 409 } 410 411 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 412 if (chip->chip_id == RTL8852C) { 413 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 414 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 415 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 416 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 417 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 418 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 419 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 420 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 421 } else { 422 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 423 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 424 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 425 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 426 } 427 } 428 429 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 430 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 431 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 432 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 433 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 434 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 435 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 436 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 437 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 438 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 439 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 440 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 441 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 442 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 443 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 444 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 445 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 446 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 447 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 448 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 449 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 450 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 451 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 452 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 453 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 454 if (chip->chip_id == RTL8852C) { 455 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 456 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 457 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 458 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 459 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 460 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 461 } else { 462 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 463 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 464 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 465 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 466 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 467 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 468 } 469 } 470 471 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 472 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 473 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 474 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 475 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 476 } 477 478 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 479 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 480 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 481 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 482 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 483 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 484 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 485 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 486 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 487 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 488 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 489 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 490 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 491 } 492 493 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 494 if (chip->chip_id == RTL8852C) { 495 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 496 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 497 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 498 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 499 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 500 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 501 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 502 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 503 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 504 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 505 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 506 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 507 } else { 508 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 509 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 510 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 511 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 512 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 513 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 514 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 515 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 516 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 517 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 518 } 519 } 520 521 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 522 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 523 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 524 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 525 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 526 } 527 } 528 529 static void rtw89_mac_dump_cmac_err_status(struct rtw89_dev *rtwdev, 530 u8 band) 531 { 532 const struct rtw89_chip_info *chip = rtwdev->chip; 533 u32 offset = 0; 534 u32 cmac_err; 535 int ret; 536 537 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 538 if (ret) { 539 if (band) 540 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 541 else 542 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 543 return; 544 } 545 546 if (band) 547 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 548 549 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 550 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 551 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 552 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 553 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 554 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 555 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 556 557 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 558 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 559 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 560 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 561 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 562 } 563 564 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 565 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 566 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 567 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 568 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 569 } 570 571 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 572 if (chip->chip_id == RTL8852C) { 573 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 574 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 575 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 576 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 577 } else { 578 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 579 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 580 } 581 } 582 583 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 584 if (chip->chip_id == RTL8852C) { 585 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 586 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 587 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 588 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 589 } else { 590 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 591 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 592 } 593 } 594 595 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 596 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 597 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 598 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 599 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 600 } 601 602 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 603 if (chip->chip_id == RTL8852C) { 604 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 605 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 606 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 607 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 608 } else { 609 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 610 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 611 } 612 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 613 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 614 } 615 616 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 617 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 618 } 619 620 static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev, 621 enum mac_ax_err_info err) 622 { 623 if (err != MAC_AX_ERR_L1_ERR_DMAC && 624 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 625 err != MAC_AX_ERR_L0_ERR_CMAC0 && 626 err != MAC_AX_ERR_L0_ERR_CMAC1 && 627 err != MAC_AX_ERR_RXI300) 628 return; 629 630 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 631 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 632 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 633 634 rtw89_mac_dump_dmac_err_status(rtwdev); 635 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_0); 636 if (rtwdev->dbcc_en) 637 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_1); 638 639 rtwdev->hci.ops->dump_err_status(rtwdev); 640 641 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 642 rtw89_mac_dump_l0_to_l1(rtwdev, err); 643 644 rtw89_info(rtwdev, "<---\n"); 645 } 646 647 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 648 { 649 u32 err, err_scnr; 650 int ret; 651 652 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 653 false, rtwdev, R_AX_HALT_C2H_CTRL); 654 if (ret) { 655 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 656 return ret; 657 } 658 659 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 660 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 661 662 err_scnr = RTW89_ERROR_SCENARIO(err); 663 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 664 err = MAC_AX_ERR_CPU_EXCEPTION; 665 else if (err_scnr == RTW89_WCPU_ASSERTION) 666 err = MAC_AX_ERR_ASSERTION; 667 else if (err_scnr == RTW89_RXI300_ERROR) 668 err = MAC_AX_ERR_RXI300; 669 670 rtw89_fw_st_dbg_dump(rtwdev); 671 rtw89_mac_dump_err_status(rtwdev, err); 672 673 return err; 674 } 675 EXPORT_SYMBOL(rtw89_mac_get_err_status); 676 677 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 678 { 679 u32 halt; 680 int ret = 0; 681 682 if (err > MAC_AX_SET_ERR_MAX) { 683 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 684 return -EINVAL; 685 } 686 687 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 688 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 689 if (ret) { 690 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 691 return -EFAULT; 692 } 693 694 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 695 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 696 697 return 0; 698 } 699 EXPORT_SYMBOL(rtw89_mac_set_err_status); 700 701 static int hfc_reset_param(struct rtw89_dev *rtwdev) 702 { 703 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 704 struct rtw89_hfc_param_ini param_ini = {NULL}; 705 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 706 707 switch (rtwdev->hci.type) { 708 case RTW89_HCI_TYPE_PCIE: 709 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 710 param->en = 0; 711 break; 712 default: 713 return -EINVAL; 714 } 715 716 if (param_ini.pub_cfg) 717 param->pub_cfg = *param_ini.pub_cfg; 718 719 if (param_ini.prec_cfg) { 720 param->prec_cfg = *param_ini.prec_cfg; 721 rtwdev->hal.sw_amsdu_max_size = 722 param->prec_cfg.wp_ch07_prec * HFC_PAGE_UNIT; 723 } 724 725 if (param_ini.ch_cfg) 726 param->ch_cfg = param_ini.ch_cfg; 727 728 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 729 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 730 param->mode = param_ini.mode; 731 732 return 0; 733 } 734 735 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 736 { 737 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 738 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 739 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 740 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 741 742 if (ch >= RTW89_DMA_CH_NUM) 743 return -EINVAL; 744 745 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 746 ch_cfg[ch].max > pub_cfg->pub_max) 747 return -EINVAL; 748 if (ch_cfg[ch].grp >= grp_num) 749 return -EINVAL; 750 751 return 0; 752 } 753 754 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 755 { 756 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 757 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 758 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 759 760 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 761 if (rtwdev->chip->chip_id == RTL8852A) 762 return 0; 763 else 764 return -EFAULT; 765 } 766 767 return 0; 768 } 769 770 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 771 { 772 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 773 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 774 775 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 776 return -EFAULT; 777 778 return 0; 779 } 780 781 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 782 { 783 const struct rtw89_chip_info *chip = rtwdev->chip; 784 const struct rtw89_page_regs *regs = chip->page_regs; 785 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 786 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 787 int ret = 0; 788 u32 val = 0; 789 790 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 791 if (ret) 792 return ret; 793 794 ret = hfc_ch_cfg_chk(rtwdev, ch); 795 if (ret) 796 return ret; 797 798 if (ch > RTW89_DMA_B1HI) 799 return -EINVAL; 800 801 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 802 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 803 (cfg[ch].grp ? B_AX_GRP : 0); 804 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 805 806 return 0; 807 } 808 809 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 810 { 811 const struct rtw89_chip_info *chip = rtwdev->chip; 812 const struct rtw89_page_regs *regs = chip->page_regs; 813 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 814 struct rtw89_hfc_ch_info *info = param->ch_info; 815 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 816 u32 val; 817 u32 ret; 818 819 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 820 if (ret) 821 return ret; 822 823 if (ch > RTW89_DMA_H2C) 824 return -EINVAL; 825 826 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 827 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 828 if (ch < RTW89_DMA_H2C) 829 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 830 else 831 info[ch].used = cfg[ch].min - info[ch].aval; 832 833 return 0; 834 } 835 836 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 837 { 838 const struct rtw89_chip_info *chip = rtwdev->chip; 839 const struct rtw89_page_regs *regs = chip->page_regs; 840 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 841 u32 val; 842 int ret; 843 844 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 845 if (ret) 846 return ret; 847 848 ret = hfc_pub_cfg_chk(rtwdev); 849 if (ret) 850 return ret; 851 852 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 853 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 854 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 855 856 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 857 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 858 859 return 0; 860 } 861 862 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 863 { 864 const struct rtw89_chip_info *chip = rtwdev->chip; 865 const struct rtw89_page_regs *regs = chip->page_regs; 866 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 867 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 868 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 869 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 870 u32 val; 871 int ret; 872 873 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 874 if (ret) 875 return ret; 876 877 val = rtw89_read32(rtwdev, regs->pub_page_info1); 878 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 879 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 880 val = rtw89_read32(rtwdev, regs->pub_page_info3); 881 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 882 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 883 info->pub_aval = 884 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 885 B_AX_PUB_AVAL_PG_MASK); 886 info->wp_aval = 887 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 888 B_AX_WP_AVAL_PG_MASK); 889 890 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 891 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 892 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 893 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 894 prec_cfg->ch011_full_cond = 895 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 896 prec_cfg->h2c_full_cond = 897 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 898 prec_cfg->wp_ch07_full_cond = 899 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 900 prec_cfg->wp_ch811_full_cond = 901 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 902 903 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 904 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 905 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 906 907 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 908 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 909 910 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 911 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 912 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 913 914 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 915 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 916 917 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 918 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 919 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 920 921 ret = hfc_pub_info_chk(rtwdev); 922 if (param->en && ret) 923 return ret; 924 925 return 0; 926 } 927 928 static void hfc_h2c_cfg(struct rtw89_dev *rtwdev) 929 { 930 const struct rtw89_chip_info *chip = rtwdev->chip; 931 const struct rtw89_page_regs *regs = chip->page_regs; 932 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 933 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 934 u32 val; 935 936 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 937 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 938 939 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 940 B_AX_HCI_FC_CH12_FULL_COND_MASK, 941 prec_cfg->h2c_full_cond); 942 } 943 944 static void hfc_mix_cfg(struct rtw89_dev *rtwdev) 945 { 946 const struct rtw89_chip_info *chip = rtwdev->chip; 947 const struct rtw89_page_regs *regs = chip->page_regs; 948 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 949 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 950 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 951 u32 val; 952 953 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 954 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 955 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 956 957 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 958 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 959 960 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 961 B_AX_PREC_PAGE_WP_CH07_MASK) | 962 u32_encode_bits(prec_cfg->wp_ch811_prec, 963 B_AX_PREC_PAGE_WP_CH811_MASK); 964 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 965 966 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 967 param->mode, B_AX_HCI_FC_MODE_MASK); 968 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 969 B_AX_HCI_FC_WD_FULL_COND_MASK); 970 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 971 B_AX_HCI_FC_CH12_FULL_COND_MASK); 972 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 973 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 974 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 975 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 976 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 977 } 978 979 static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 980 { 981 const struct rtw89_chip_info *chip = rtwdev->chip; 982 const struct rtw89_page_regs *regs = chip->page_regs; 983 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 984 u32 val; 985 986 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 987 param->en = en; 988 param->h2c_en = h2c_en; 989 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 990 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 991 (val & ~B_AX_HCI_FC_CH12_EN); 992 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 993 } 994 995 static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 996 { 997 const struct rtw89_chip_info *chip = rtwdev->chip; 998 u32 dma_ch_mask = chip->dma_ch_mask; 999 u8 ch; 1000 u32 ret = 0; 1001 1002 if (reset) 1003 ret = hfc_reset_param(rtwdev); 1004 if (ret) 1005 return ret; 1006 1007 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1008 if (ret) 1009 return ret; 1010 1011 hfc_func_en(rtwdev, false, false); 1012 1013 if (!en && h2c_en) { 1014 hfc_h2c_cfg(rtwdev); 1015 hfc_func_en(rtwdev, en, h2c_en); 1016 return ret; 1017 } 1018 1019 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1020 if (dma_ch_mask & BIT(ch)) 1021 continue; 1022 ret = hfc_ch_ctrl(rtwdev, ch); 1023 if (ret) 1024 return ret; 1025 } 1026 1027 ret = hfc_pub_ctrl(rtwdev); 1028 if (ret) 1029 return ret; 1030 1031 hfc_mix_cfg(rtwdev); 1032 if (en || h2c_en) { 1033 hfc_func_en(rtwdev, en, h2c_en); 1034 udelay(10); 1035 } 1036 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1037 if (dma_ch_mask & BIT(ch)) 1038 continue; 1039 ret = hfc_upd_ch_info(rtwdev, ch); 1040 if (ret) 1041 return ret; 1042 } 1043 ret = hfc_upd_mix_info(rtwdev); 1044 1045 return ret; 1046 } 1047 1048 #define PWR_POLL_CNT 2000 1049 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1050 const struct rtw89_pwr_cfg *cfg) 1051 { 1052 u8 val = 0; 1053 int ret; 1054 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1055 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1056 1057 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1058 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1059 1060 if (!ret) 1061 return 0; 1062 1063 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1064 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1065 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1066 1067 return -EBUSY; 1068 } 1069 1070 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1071 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1072 { 1073 const struct rtw89_pwr_cfg *cur_cfg; 1074 u32 addr; 1075 u8 val; 1076 1077 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1078 if (!(cur_cfg->intf_msk & intf_msk) || 1079 !(cur_cfg->cv_msk & cv_msk)) 1080 continue; 1081 1082 switch (cur_cfg->cmd) { 1083 case PWR_CMD_WRITE: 1084 addr = cur_cfg->addr; 1085 1086 if (cur_cfg->base == PWR_BASE_SDIO) 1087 addr |= SDIO_LOCAL_BASE_ADDR; 1088 1089 val = rtw89_read8(rtwdev, addr); 1090 val &= ~(cur_cfg->msk); 1091 val |= (cur_cfg->val & cur_cfg->msk); 1092 1093 rtw89_write8(rtwdev, addr, val); 1094 break; 1095 case PWR_CMD_POLL: 1096 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1097 return -EBUSY; 1098 break; 1099 case PWR_CMD_DELAY: 1100 if (cur_cfg->val == PWR_DELAY_US) 1101 udelay(cur_cfg->addr); 1102 else 1103 fsleep(cur_cfg->addr * 1000); 1104 break; 1105 default: 1106 return -EINVAL; 1107 } 1108 } 1109 1110 return 0; 1111 } 1112 1113 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1114 const struct rtw89_pwr_cfg * const *cfg_seq) 1115 { 1116 int ret; 1117 1118 for (; *cfg_seq; cfg_seq++) { 1119 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1120 PWR_INTF_MSK_PCIE, *cfg_seq); 1121 if (ret) 1122 return -EBUSY; 1123 } 1124 1125 return 0; 1126 } 1127 1128 static enum rtw89_rpwm_req_pwr_state 1129 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1130 { 1131 enum rtw89_rpwm_req_pwr_state state; 1132 1133 switch (rtwdev->ps_mode) { 1134 case RTW89_PS_MODE_RFOFF: 1135 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1136 break; 1137 case RTW89_PS_MODE_CLK_GATED: 1138 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1139 break; 1140 case RTW89_PS_MODE_PWR_GATED: 1141 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1142 break; 1143 default: 1144 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1145 break; 1146 } 1147 return state; 1148 } 1149 1150 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1151 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1152 bool notify_wake) 1153 { 1154 u16 request; 1155 1156 spin_lock_bh(&rtwdev->rpwm_lock); 1157 1158 request = rtw89_read16(rtwdev, R_AX_RPWM); 1159 request ^= request | PS_RPWM_TOGGLE; 1160 request |= req_pwr_state; 1161 1162 if (notify_wake) { 1163 request |= PS_RPWM_NOTIFY_WAKE; 1164 } else { 1165 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1166 RPWM_SEQ_NUM_MAX; 1167 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1168 rtwdev->mac.rpwm_seq_num); 1169 1170 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1171 request |= PS_RPWM_ACK; 1172 } 1173 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1174 1175 spin_unlock_bh(&rtwdev->rpwm_lock); 1176 } 1177 1178 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1179 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1180 { 1181 bool request_deep_mode; 1182 bool in_deep_mode; 1183 u8 rpwm_req_num; 1184 u8 cpwm_rsp_seq; 1185 u8 cpwm_seq; 1186 u8 cpwm_status; 1187 1188 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1189 request_deep_mode = true; 1190 else 1191 request_deep_mode = false; 1192 1193 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1194 in_deep_mode = true; 1195 else 1196 in_deep_mode = false; 1197 1198 if (request_deep_mode != in_deep_mode) 1199 return -EPERM; 1200 1201 if (request_deep_mode) 1202 return 0; 1203 1204 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1205 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1206 PS_CPWM_RSP_SEQ_NUM); 1207 1208 if (rpwm_req_num != cpwm_rsp_seq) 1209 return -EPERM; 1210 1211 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1212 CPWM_SEQ_NUM_MAX; 1213 1214 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1215 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1216 return -EPERM; 1217 1218 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1219 if (cpwm_status != req_pwr_state) 1220 return -EPERM; 1221 1222 return 0; 1223 } 1224 1225 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1226 { 1227 enum rtw89_rpwm_req_pwr_state state; 1228 unsigned long delay = enter ? 10 : 150; 1229 int ret; 1230 int i; 1231 1232 if (enter) 1233 state = rtw89_mac_get_req_pwr_state(rtwdev); 1234 else 1235 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1236 1237 for (i = 0; i < RPWM_TRY_CNT; i++) { 1238 rtw89_mac_send_rpwm(rtwdev, state, false); 1239 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1240 !ret, delay, 15000, false, 1241 rtwdev, state); 1242 if (!ret) 1243 break; 1244 1245 if (i == RPWM_TRY_CNT - 1) 1246 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1247 enter ? "entering" : "leaving"); 1248 else 1249 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1250 "%d time firmware failed to ack for %s ps mode\n", 1251 i + 1, enter ? "entering" : "leaving"); 1252 } 1253 } 1254 1255 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1256 { 1257 enum rtw89_rpwm_req_pwr_state state; 1258 1259 state = rtw89_mac_get_req_pwr_state(rtwdev); 1260 rtw89_mac_send_rpwm(rtwdev, state, true); 1261 } 1262 1263 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1264 { 1265 #define PWR_ACT 1 1266 const struct rtw89_chip_info *chip = rtwdev->chip; 1267 const struct rtw89_pwr_cfg * const *cfg_seq; 1268 int (*cfg_func)(struct rtw89_dev *rtwdev); 1269 int ret; 1270 u8 val; 1271 1272 if (on) { 1273 cfg_seq = chip->pwr_on_seq; 1274 cfg_func = chip->ops->pwr_on_func; 1275 } else { 1276 cfg_seq = chip->pwr_off_seq; 1277 cfg_func = chip->ops->pwr_off_func; 1278 } 1279 1280 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1281 __rtw89_leave_ps_mode(rtwdev); 1282 1283 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1284 if (on && val == PWR_ACT) { 1285 rtw89_err(rtwdev, "MAC has already powered on\n"); 1286 return -EBUSY; 1287 } 1288 1289 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1290 if (ret) 1291 return ret; 1292 1293 if (on) { 1294 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1295 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1296 } else { 1297 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1298 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1299 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1300 rtw89_set_entity_state(rtwdev, false); 1301 } 1302 1303 return 0; 1304 #undef PWR_ACT 1305 } 1306 1307 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1308 { 1309 rtw89_mac_power_switch(rtwdev, false); 1310 } 1311 1312 static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1313 { 1314 u32 func_en = 0; 1315 u32 ck_en = 0; 1316 u32 c1pc_en = 0; 1317 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1318 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1319 1320 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1321 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1322 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1323 B_AX_CMAC_CRPRT; 1324 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1325 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1326 B_AX_RMAC_CKEN; 1327 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1328 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1329 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1330 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1331 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1332 1333 if (en) { 1334 if (mac_idx == RTW89_MAC_1) { 1335 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1336 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1337 B_AX_R_SYM_ISO_CMAC12PP); 1338 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1339 B_AX_CMAC1_FEN); 1340 } 1341 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1342 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1343 } else { 1344 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1345 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1346 if (mac_idx == RTW89_MAC_1) { 1347 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1348 B_AX_CMAC1_FEN); 1349 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1350 B_AX_R_SYM_ISO_CMAC12PP); 1351 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1352 } 1353 } 1354 1355 return 0; 1356 } 1357 1358 static int dmac_func_en(struct rtw89_dev *rtwdev) 1359 { 1360 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1361 u32 val32; 1362 1363 if (chip_id == RTL8852C) 1364 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1365 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1366 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1367 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1368 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1369 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1370 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1371 else 1372 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1373 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1374 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1375 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1376 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1377 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1378 B_AX_DMAC_CRPRT); 1379 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1380 1381 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1382 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1383 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1384 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1385 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1386 1387 return 0; 1388 } 1389 1390 static int chip_func_en(struct rtw89_dev *rtwdev) 1391 { 1392 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1393 1394 if (chip_id == RTL8852A || chip_id == RTL8852B) 1395 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1396 B_AX_OCP_L1_MASK); 1397 1398 return 0; 1399 } 1400 1401 static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev) 1402 { 1403 int ret; 1404 1405 ret = dmac_func_en(rtwdev); 1406 if (ret) 1407 return ret; 1408 1409 ret = cmac_func_en(rtwdev, 0, true); 1410 if (ret) 1411 return ret; 1412 1413 ret = chip_func_en(rtwdev); 1414 if (ret) 1415 return ret; 1416 1417 return ret; 1418 } 1419 1420 const struct rtw89_mac_size_set rtw89_mac_size = { 1421 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1422 /* PCIE 64 */ 1423 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1424 /* DLFW */ 1425 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1426 /* PCIE 64 */ 1427 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1428 /* DLFW */ 1429 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1430 /* 8852C DLFW */ 1431 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1432 /* 8852C PCIE SCC */ 1433 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1434 /* PCIE */ 1435 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1436 /* DLFW */ 1437 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1438 /* PCIE 64 */ 1439 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1440 /* DLFW */ 1441 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1442 /* 8852C DLFW */ 1443 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1444 /* 8852C PCIE SCC */ 1445 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1446 /* PCIE 64 */ 1447 .wde_qt0 = {3792, 196, 0, 107,}, 1448 /* DLFW */ 1449 .wde_qt4 = {0, 0, 0, 0,}, 1450 /* PCIE 64 */ 1451 .wde_qt6 = {448, 48, 0, 16,}, 1452 /* 8852C DLFW */ 1453 .wde_qt17 = {0, 0, 0, 0,}, 1454 /* 8852C PCIE SCC */ 1455 .wde_qt18 = {3228, 60, 0, 40,}, 1456 /* PCIE SCC */ 1457 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1458 /* PCIE SCC */ 1459 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1460 /* DLFW */ 1461 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1462 /* PCIE 64 */ 1463 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1464 /* DLFW 52C */ 1465 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1466 /* DLFW 52C */ 1467 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1468 /* 8852C PCIE SCC */ 1469 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1470 /* 8852C PCIE SCC */ 1471 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1472 /* PCIE 64 */ 1473 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1474 /* 8852A PCIE WOW */ 1475 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1476 /* 8852B PCIE WOW */ 1477 .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1478 }; 1479 EXPORT_SYMBOL(rtw89_mac_size); 1480 1481 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1482 enum rtw89_qta_mode mode) 1483 { 1484 struct rtw89_mac_info *mac = &rtwdev->mac; 1485 const struct rtw89_dle_mem *cfg; 1486 1487 cfg = &rtwdev->chip->dle_mem[mode]; 1488 if (!cfg) 1489 return NULL; 1490 1491 if (cfg->mode != mode) { 1492 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1493 return NULL; 1494 } 1495 1496 mac->dle_info.wde_pg_size = cfg->wde_size->pge_size; 1497 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1498 mac->dle_info.qta_mode = mode; 1499 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1500 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1501 1502 return cfg; 1503 } 1504 1505 static bool mac_is_txq_empty(struct rtw89_dev *rtwdev) 1506 { 1507 struct rtw89_mac_dle_dfi_qempty qempty; 1508 u32 qnum, qtmp, val32, msk32; 1509 int i, j, ret; 1510 1511 qnum = rtwdev->chip->wde_qempty_acq_num; 1512 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1513 1514 for (i = 0; i < qnum; i++) { 1515 qempty.grpsel = i; 1516 ret = dle_dfi_qempty(rtwdev, &qempty); 1517 if (ret) { 1518 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1519 return false; 1520 } 1521 qtmp = qempty.qempty; 1522 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1523 val32 = FIELD_GET(QEMP_ACQ_GRP_QSEL_MASK, qtmp); 1524 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1525 return false; 1526 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1527 } 1528 } 1529 1530 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_sel; 1531 ret = dle_dfi_qempty(rtwdev, &qempty); 1532 if (ret) { 1533 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1534 return false; 1535 } 1536 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1537 if ((qempty.qempty & msk32) != msk32) 1538 return false; 1539 1540 if (rtwdev->dbcc_en) { 1541 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1542 if ((qempty.qempty & msk32) != msk32) 1543 return false; 1544 } 1545 1546 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1547 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1548 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1549 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1550 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1551 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1552 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1553 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1554 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1555 1556 return (val32 & msk32) == msk32; 1557 } 1558 1559 static inline u32 dle_used_size(const struct rtw89_dle_size *wde, 1560 const struct rtw89_dle_size *ple) 1561 { 1562 return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1563 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1564 } 1565 1566 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 1567 enum rtw89_qta_mode mode) 1568 { 1569 u32 size = rtwdev->chip->fifo_size; 1570 1571 if (mode == RTW89_QTA_SCC) 1572 size -= rtwdev->chip->dle_scc_rsvd_size; 1573 1574 return size; 1575 } 1576 1577 static void dle_func_en(struct rtw89_dev *rtwdev, bool enable) 1578 { 1579 if (enable) 1580 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1581 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1582 else 1583 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1584 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1585 } 1586 1587 static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable) 1588 { 1589 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 1590 1591 if (enable) { 1592 if (rtwdev->chip->chip_id == RTL8851B) 1593 val |= B_AX_AXIDMA_CLK_EN; 1594 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 1595 } else { 1596 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 1597 } 1598 } 1599 1600 static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1601 { 1602 const struct rtw89_dle_size *size_cfg; 1603 u32 val; 1604 u8 bound = 0; 1605 1606 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1607 size_cfg = cfg->wde_size; 1608 1609 switch (size_cfg->pge_size) { 1610 default: 1611 case RTW89_WDE_PG_64: 1612 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1613 B_AX_WDE_PAGE_SEL_MASK); 1614 break; 1615 case RTW89_WDE_PG_128: 1616 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1617 B_AX_WDE_PAGE_SEL_MASK); 1618 break; 1619 case RTW89_WDE_PG_256: 1620 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1621 return -EINVAL; 1622 } 1623 1624 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1625 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1626 B_AX_WDE_FREE_PAGE_NUM_MASK); 1627 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1628 1629 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1630 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1631 * size_cfg->pge_size / DLE_BOUND_UNIT; 1632 size_cfg = cfg->ple_size; 1633 1634 switch (size_cfg->pge_size) { 1635 default: 1636 case RTW89_PLE_PG_64: 1637 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1638 return -EINVAL; 1639 case RTW89_PLE_PG_128: 1640 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1641 B_AX_PLE_PAGE_SEL_MASK); 1642 break; 1643 case RTW89_PLE_PG_256: 1644 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1645 B_AX_PLE_PAGE_SEL_MASK); 1646 break; 1647 } 1648 1649 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1650 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1651 B_AX_PLE_FREE_PAGE_NUM_MASK); 1652 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1653 1654 return 0; 1655 } 1656 1657 #define INVALID_QT_WCPU U16_MAX 1658 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1659 do { \ 1660 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1661 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1662 rtw89_write32(rtwdev, \ 1663 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1664 val); \ 1665 } while (0) 1666 #define SET_QUOTA(_x, _module, _idx) \ 1667 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1668 1669 static void wde_quota_cfg(struct rtw89_dev *rtwdev, 1670 const struct rtw89_wde_quota *min_cfg, 1671 const struct rtw89_wde_quota *max_cfg, 1672 u16 ext_wde_min_qt_wcpu) 1673 { 1674 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1675 ext_wde_min_qt_wcpu : min_cfg->wcpu; 1676 u32 val; 1677 1678 SET_QUOTA(hif, WDE, 0); 1679 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1680 SET_QUOTA(pkt_in, WDE, 3); 1681 SET_QUOTA(cpu_io, WDE, 4); 1682 } 1683 1684 static void ple_quota_cfg(struct rtw89_dev *rtwdev, 1685 const struct rtw89_ple_quota *min_cfg, 1686 const struct rtw89_ple_quota *max_cfg) 1687 { 1688 u32 val; 1689 1690 SET_QUOTA(cma0_tx, PLE, 0); 1691 SET_QUOTA(cma1_tx, PLE, 1); 1692 SET_QUOTA(c2h, PLE, 2); 1693 SET_QUOTA(h2c, PLE, 3); 1694 SET_QUOTA(wcpu, PLE, 4); 1695 SET_QUOTA(mpdu_proc, PLE, 5); 1696 SET_QUOTA(cma0_dma, PLE, 6); 1697 SET_QUOTA(cma1_dma, PLE, 7); 1698 SET_QUOTA(bb_rpt, PLE, 8); 1699 SET_QUOTA(wd_rel, PLE, 9); 1700 SET_QUOTA(cpu_io, PLE, 10); 1701 if (rtwdev->chip->chip_id == RTL8852C) 1702 SET_QUOTA(tx_rpt, PLE, 11); 1703 } 1704 1705 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 1706 { 1707 const struct rtw89_ple_quota *min_cfg, *max_cfg; 1708 const struct rtw89_dle_mem *cfg; 1709 u32 val; 1710 1711 if (rtwdev->chip->chip_id == RTL8852C) 1712 return 0; 1713 1714 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 1715 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 1716 return -EINVAL; 1717 } 1718 1719 if (wow) 1720 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 1721 else 1722 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 1723 if (!cfg) { 1724 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1725 return -EINVAL; 1726 } 1727 1728 min_cfg = cfg->ple_min_qt; 1729 max_cfg = cfg->ple_max_qt; 1730 SET_QUOTA(cma0_dma, PLE, 6); 1731 SET_QUOTA(cma1_dma, PLE, 7); 1732 1733 return 0; 1734 } 1735 #undef SET_QUOTA 1736 1737 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 1738 { 1739 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 1740 1741 if (enable) 1742 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 1743 else 1744 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 1745 } 1746 1747 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 1748 const struct rtw89_dle_mem *cfg, 1749 u16 ext_wde_min_qt_wcpu) 1750 { 1751 wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 1752 ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 1753 } 1754 1755 static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1756 enum rtw89_qta_mode ext_mode) 1757 { 1758 const struct rtw89_dle_mem *cfg, *ext_cfg; 1759 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 1760 int ret = 0; 1761 u32 ini; 1762 1763 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1764 if (ret) 1765 return ret; 1766 1767 cfg = get_dle_mem_cfg(rtwdev, mode); 1768 if (!cfg) { 1769 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1770 ret = -EINVAL; 1771 goto error; 1772 } 1773 1774 if (mode == RTW89_QTA_DLFW) { 1775 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 1776 if (!ext_cfg) { 1777 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 1778 ext_mode); 1779 ret = -EINVAL; 1780 goto error; 1781 } 1782 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 1783 } 1784 1785 if (dle_used_size(cfg->wde_size, cfg->ple_size) != 1786 dle_expected_used_size(rtwdev, mode)) { 1787 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 1788 ret = -EINVAL; 1789 goto error; 1790 } 1791 1792 dle_func_en(rtwdev, false); 1793 dle_clk_en(rtwdev, true); 1794 1795 ret = dle_mix_cfg(rtwdev, cfg); 1796 if (ret) { 1797 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 1798 goto error; 1799 } 1800 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 1801 1802 dle_func_en(rtwdev, true); 1803 1804 ret = read_poll_timeout(rtw89_read32, ini, 1805 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1806 2000, false, rtwdev, R_AX_WDE_INI_STATUS); 1807 if (ret) { 1808 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 1809 return ret; 1810 } 1811 1812 ret = read_poll_timeout(rtw89_read32, ini, 1813 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1814 2000, false, rtwdev, R_AX_PLE_INI_STATUS); 1815 if (ret) { 1816 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 1817 return ret; 1818 } 1819 1820 return 0; 1821 error: 1822 dle_func_en(rtwdev, false); 1823 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 1824 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 1825 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 1826 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 1827 1828 return ret; 1829 } 1830 1831 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1832 enum rtw89_qta_mode mode) 1833 { 1834 u32 reg, max_preld_size, min_rsvd_size; 1835 1836 max_preld_size = (mac_idx == RTW89_MAC_0 ? 1837 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 1838 reg = mac_idx == RTW89_MAC_0 ? 1839 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 1840 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 1841 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 1842 1843 min_rsvd_size = PRELD_AMSDU_SIZE; 1844 reg = mac_idx == RTW89_MAC_0 ? 1845 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 1846 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 1847 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 1848 1849 return 0; 1850 } 1851 1852 static bool is_qta_poh(struct rtw89_dev *rtwdev) 1853 { 1854 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 1855 } 1856 1857 static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1858 enum rtw89_qta_mode mode) 1859 { 1860 const struct rtw89_chip_info *chip = rtwdev->chip; 1861 1862 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 1863 chip->chip_id == RTL8851B || !is_qta_poh(rtwdev)) 1864 return 0; 1865 1866 return preload_init_set(rtwdev, mac_idx, mode); 1867 } 1868 1869 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 1870 { 1871 u32 msk32; 1872 u32 val32; 1873 1874 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 1875 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 1876 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 1877 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1878 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 1879 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 1880 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 1881 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 1882 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1883 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 1884 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1885 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1886 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 1887 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1888 1889 if ((val32 & msk32) == msk32) 1890 return true; 1891 1892 return false; 1893 } 1894 1895 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 1896 { 1897 const struct rtw89_chip_info *chip = rtwdev->chip; 1898 1899 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 1900 chip->chip_id == RTL8851B) 1901 return; 1902 1903 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 1904 SS2F_PATH_WLCPU); 1905 } 1906 1907 static int sta_sch_init(struct rtw89_dev *rtwdev) 1908 { 1909 u32 p_val; 1910 u8 val; 1911 int ret; 1912 1913 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1914 if (ret) 1915 return ret; 1916 1917 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 1918 val |= B_AX_SS_EN; 1919 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 1920 1921 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 1922 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 1923 if (ret) { 1924 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 1925 return ret; 1926 } 1927 1928 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 1929 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 1930 1931 _patch_ss2f_path(rtwdev); 1932 1933 return 0; 1934 } 1935 1936 static int mpdu_proc_init(struct rtw89_dev *rtwdev) 1937 { 1938 int ret; 1939 1940 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1941 if (ret) 1942 return ret; 1943 1944 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 1945 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 1946 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 1947 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 1948 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 1949 1950 return 0; 1951 } 1952 1953 static int sec_eng_init(struct rtw89_dev *rtwdev) 1954 { 1955 const struct rtw89_chip_info *chip = rtwdev->chip; 1956 u32 val = 0; 1957 int ret; 1958 1959 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1960 if (ret) 1961 return ret; 1962 1963 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 1964 /* init clock */ 1965 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 1966 /* init TX encryption */ 1967 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 1968 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 1969 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 1970 chip->chip_id == RTL8851B) 1971 val &= ~B_AX_TX_PARTIAL_MODE; 1972 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 1973 1974 /* init MIC ICV append */ 1975 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 1976 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 1977 1978 /* option init */ 1979 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 1980 1981 if (chip->chip_id == RTL8852C) 1982 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 1983 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 1984 1985 return 0; 1986 } 1987 1988 static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1989 { 1990 int ret; 1991 1992 ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 1993 if (ret) { 1994 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 1995 return ret; 1996 } 1997 1998 ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 1999 if (ret) { 2000 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2001 return ret; 2002 } 2003 2004 ret = hfc_init(rtwdev, true, true, true); 2005 if (ret) { 2006 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2007 return ret; 2008 } 2009 2010 ret = sta_sch_init(rtwdev); 2011 if (ret) { 2012 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2013 return ret; 2014 } 2015 2016 ret = mpdu_proc_init(rtwdev); 2017 if (ret) { 2018 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2019 return ret; 2020 } 2021 2022 ret = sec_eng_init(rtwdev); 2023 if (ret) { 2024 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2025 return ret; 2026 } 2027 2028 return ret; 2029 } 2030 2031 static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2032 { 2033 u32 val, reg; 2034 u16 p_val; 2035 int ret; 2036 2037 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2038 if (ret) 2039 return ret; 2040 2041 reg = rtw89_mac_reg_by_idx(R_AX_ADDR_CAM_CTRL, mac_idx); 2042 2043 val = rtw89_read32(rtwdev, reg); 2044 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2045 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2046 rtw89_write32(rtwdev, reg, val); 2047 2048 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2049 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2050 if (ret) { 2051 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2052 return ret; 2053 } 2054 2055 return 0; 2056 } 2057 2058 static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2059 { 2060 u32 ret; 2061 u32 reg; 2062 u32 val; 2063 2064 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2065 if (ret) 2066 return ret; 2067 2068 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_1, mac_idx); 2069 if (rtwdev->chip->chip_id == RTL8852C) 2070 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2071 SIFS_MACTXEN_T1_V1); 2072 else 2073 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2074 SIFS_MACTXEN_T1); 2075 2076 if (rtwdev->chip->chip_id == RTL8852B || rtwdev->chip->chip_id == RTL8851B) { 2077 reg = rtw89_mac_reg_by_idx(R_AX_SCH_EXT_CTRL, mac_idx); 2078 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2079 } 2080 2081 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CFG_0, mac_idx); 2082 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2083 2084 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_0, mac_idx); 2085 if (rtwdev->chip->chip_id == RTL8852C) { 2086 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2087 B_AX_TX_PARTIAL_MODE); 2088 if (!val) 2089 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2090 SCH_PREBKF_24US); 2091 } else { 2092 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2093 SCH_PREBKF_24US); 2094 } 2095 2096 return 0; 2097 } 2098 2099 int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, 2100 enum rtw89_machdr_frame_type type, 2101 enum rtw89_mac_fwd_target fwd_target, 2102 u8 mac_idx) 2103 { 2104 u32 reg; 2105 u32 val; 2106 2107 switch (fwd_target) { 2108 case RTW89_FWD_DONT_CARE: 2109 val = RX_FLTR_FRAME_DROP; 2110 break; 2111 case RTW89_FWD_TO_HOST: 2112 val = RX_FLTR_FRAME_TO_HOST; 2113 break; 2114 case RTW89_FWD_TO_WLAN_CPU: 2115 val = RX_FLTR_FRAME_TO_WLCPU; 2116 break; 2117 default: 2118 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2119 return -EINVAL; 2120 } 2121 2122 switch (type) { 2123 case RTW89_MGNT: 2124 reg = rtw89_mac_reg_by_idx(R_AX_MGNT_FLTR, mac_idx); 2125 break; 2126 case RTW89_CTRL: 2127 reg = rtw89_mac_reg_by_idx(R_AX_CTRL_FLTR, mac_idx); 2128 break; 2129 case RTW89_DATA: 2130 reg = rtw89_mac_reg_by_idx(R_AX_DATA_FLTR, mac_idx); 2131 break; 2132 default: 2133 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2134 return -EINVAL; 2135 } 2136 rtw89_write32(rtwdev, reg, val); 2137 2138 return 0; 2139 } 2140 2141 static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2142 { 2143 int ret, i; 2144 u32 mac_ftlr, plcp_ftlr; 2145 2146 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2147 if (ret) 2148 return ret; 2149 2150 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2151 ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST, 2152 mac_idx); 2153 if (ret) 2154 return ret; 2155 } 2156 mac_ftlr = rtwdev->hal.rx_fltr; 2157 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2158 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2159 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2160 B_AX_HE_SIGB_CRC_CHK; 2161 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx), 2162 mac_ftlr); 2163 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx), 2164 plcp_ftlr); 2165 2166 return 0; 2167 } 2168 2169 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2170 { 2171 u32 reg, val32; 2172 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2173 2174 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2175 B_AX_RSP_CHK_BASIC_NAV; 2176 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2177 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2178 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2179 2180 switch (rtwdev->chip->chip_id) { 2181 case RTL8852A: 2182 case RTL8852B: 2183 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 2184 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2185 rtw89_write32(rtwdev, reg, val32); 2186 2187 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2188 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2189 rtw89_write32(rtwdev, reg, val32); 2190 break; 2191 default: 2192 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 2193 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2194 rtw89_write32(rtwdev, reg, val32); 2195 2196 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2197 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2198 rtw89_write32(rtwdev, reg, val32); 2199 break; 2200 } 2201 } 2202 2203 static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2204 { 2205 u32 val, reg; 2206 int ret; 2207 2208 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2209 if (ret) 2210 return ret; 2211 2212 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CONTROL, mac_idx); 2213 val = rtw89_read32(rtwdev, reg); 2214 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2215 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2216 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2217 B_AX_CTN_CHK_INTRA_NAV | 2218 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2219 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2220 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2221 B_AX_CTN_CHK_CCA_P20); 2222 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2223 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2224 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2225 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2226 B_AX_SIFS_CHK_EDCCA); 2227 2228 rtw89_write32(rtwdev, reg, val); 2229 2230 _patch_dis_resp_chk(rtwdev, mac_idx); 2231 2232 return 0; 2233 } 2234 2235 static int nav_ctrl_init(struct rtw89_dev *rtwdev) 2236 { 2237 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2238 B_AX_WMAC_TF_UP_NAV_EN | 2239 B_AX_WMAC_NAV_UPPER_EN); 2240 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2241 2242 return 0; 2243 } 2244 2245 static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2246 { 2247 u32 reg; 2248 int ret; 2249 2250 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2251 if (ret) 2252 return ret; 2253 reg = rtw89_mac_reg_by_idx(R_AX_RX_SR_CTRL, mac_idx); 2254 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2255 2256 return 0; 2257 } 2258 2259 static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2260 { 2261 u32 reg; 2262 int ret; 2263 2264 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2265 if (ret) 2266 return ret; 2267 2268 reg = rtw89_mac_reg_by_idx(R_AX_MAC_LOOPBACK, mac_idx); 2269 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2270 2271 reg = rtw89_mac_reg_by_idx(R_AX_TCR0, mac_idx); 2272 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2273 2274 reg = rtw89_mac_reg_by_idx(R_AX_TXD_FIFO_CTRL, mac_idx); 2275 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2276 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2277 2278 return 0; 2279 } 2280 2281 static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2282 { 2283 const struct rtw89_chip_info *chip = rtwdev->chip; 2284 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2285 u32 reg, val, sifs; 2286 int ret; 2287 2288 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2289 if (ret) 2290 return ret; 2291 2292 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2293 val = rtw89_read32(rtwdev, reg); 2294 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2295 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2296 2297 switch (rtwdev->chip->chip_id) { 2298 case RTL8852A: 2299 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2300 break; 2301 case RTL8852B: 2302 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2303 break; 2304 default: 2305 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2306 break; 2307 } 2308 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2309 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2310 rtw89_write32(rtwdev, reg, val); 2311 2312 reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx); 2313 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2314 2315 reg = rtw89_mac_reg_by_idx(rrsr->ref_rate.addr, mac_idx); 2316 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2317 reg = rtw89_mac_reg_by_idx(rrsr->rsc.addr, mac_idx); 2318 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2319 2320 return 0; 2321 } 2322 2323 static void rst_bacam(struct rtw89_dev *rtwdev) 2324 { 2325 u32 val32; 2326 int ret; 2327 2328 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2329 S_AX_BACAM_RST_ALL); 2330 2331 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2332 1, 1000, false, 2333 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2334 if (ret) 2335 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2336 } 2337 2338 static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2339 { 2340 #define TRXCFG_RMAC_CCA_TO 32 2341 #define TRXCFG_RMAC_DATA_TO 15 2342 #define RX_MAX_LEN_UNIT 512 2343 #define PLD_RLS_MAX_PG 127 2344 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2345 int ret; 2346 u32 reg, rx_max_len, rx_qta; 2347 u16 val; 2348 2349 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2350 if (ret) 2351 return ret; 2352 2353 if (mac_idx == RTW89_MAC_0) 2354 rst_bacam(rtwdev); 2355 2356 reg = rtw89_mac_reg_by_idx(R_AX_RESPBA_CAM_CTRL, mac_idx); 2357 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2358 2359 reg = rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx); 2360 val = rtw89_read16(rtwdev, reg); 2361 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2362 B_AX_RX_DLK_DATA_TIME_MASK); 2363 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2364 B_AX_RX_DLK_CCA_TIME_MASK); 2365 rtw89_write16(rtwdev, reg, val); 2366 2367 reg = rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx); 2368 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2369 2370 reg = rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx); 2371 if (mac_idx == RTW89_MAC_0) 2372 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2373 else 2374 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2375 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2376 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2377 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2378 rx_max_len /= RX_MAX_LEN_UNIT; 2379 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2380 2381 if (rtwdev->chip->chip_id == RTL8852A && 2382 rtwdev->hal.cv == CHIP_CBV) { 2383 rtw89_write16_mask(rtwdev, 2384 rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx), 2385 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2386 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx), 2387 BIT(12)); 2388 } 2389 2390 reg = rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx); 2391 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2392 2393 return ret; 2394 } 2395 2396 static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2397 { 2398 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2399 u32 val, reg; 2400 int ret; 2401 2402 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2403 if (ret) 2404 return ret; 2405 2406 reg = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2407 val = rtw89_read32(rtwdev, reg); 2408 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2409 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2410 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2411 rtw89_write32(rtwdev, reg, val); 2412 2413 if (chip_id == RTL8852A || chip_id == RTL8852B) { 2414 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_RRSR1, mac_idx); 2415 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2416 } 2417 2418 return 0; 2419 } 2420 2421 static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2422 { 2423 const struct rtw89_dle_mem *cfg; 2424 2425 cfg = get_dle_mem_cfg(rtwdev, mode); 2426 if (!cfg) { 2427 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2428 return false; 2429 } 2430 2431 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2432 } 2433 2434 static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2435 { 2436 u32 val, reg; 2437 int ret; 2438 2439 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2440 if (ret) 2441 return ret; 2442 2443 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2444 reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); 2445 val = rtw89_read32(rtwdev, reg); 2446 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2447 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2448 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2449 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2450 val |= B_AX_HW_CTS2SELF_EN; 2451 rtw89_write32(rtwdev, reg, val); 2452 2453 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_FSM_MON, mac_idx); 2454 val = rtw89_read32(rtwdev, reg); 2455 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2456 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2457 rtw89_write32(rtwdev, reg, val); 2458 } 2459 2460 if (mac_idx == RTW89_MAC_0) { 2461 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2462 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2463 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2464 B_AX_PTCL_TRIGGER_SS_EN_0 | 2465 B_AX_PTCL_TRIGGER_SS_EN_1 | 2466 B_AX_PTCL_TRIGGER_SS_EN_UL); 2467 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2468 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2469 } else if (mac_idx == RTW89_MAC_1) { 2470 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2471 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2472 } 2473 2474 return 0; 2475 } 2476 2477 static int cmac_dma_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2478 { 2479 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2480 u32 reg; 2481 int ret; 2482 2483 if (chip_id != RTL8852A && chip_id != RTL8852B) 2484 return 0; 2485 2486 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2487 if (ret) 2488 return ret; 2489 2490 reg = rtw89_mac_reg_by_idx(R_AX_RXDMA_CTRL_0, mac_idx); 2491 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2492 2493 return 0; 2494 } 2495 2496 static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2497 { 2498 int ret; 2499 2500 ret = scheduler_init(rtwdev, mac_idx); 2501 if (ret) { 2502 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2503 return ret; 2504 } 2505 2506 ret = addr_cam_init(rtwdev, mac_idx); 2507 if (ret) { 2508 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2509 ret); 2510 return ret; 2511 } 2512 2513 ret = rx_fltr_init(rtwdev, mac_idx); 2514 if (ret) { 2515 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2516 ret); 2517 return ret; 2518 } 2519 2520 ret = cca_ctrl_init(rtwdev, mac_idx); 2521 if (ret) { 2522 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2523 ret); 2524 return ret; 2525 } 2526 2527 ret = nav_ctrl_init(rtwdev); 2528 if (ret) { 2529 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2530 ret); 2531 return ret; 2532 } 2533 2534 ret = spatial_reuse_init(rtwdev, mac_idx); 2535 if (ret) { 2536 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2537 mac_idx, ret); 2538 return ret; 2539 } 2540 2541 ret = tmac_init(rtwdev, mac_idx); 2542 if (ret) { 2543 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2544 return ret; 2545 } 2546 2547 ret = trxptcl_init(rtwdev, mac_idx); 2548 if (ret) { 2549 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2550 return ret; 2551 } 2552 2553 ret = rmac_init(rtwdev, mac_idx); 2554 if (ret) { 2555 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2556 return ret; 2557 } 2558 2559 ret = cmac_com_init(rtwdev, mac_idx); 2560 if (ret) { 2561 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2562 return ret; 2563 } 2564 2565 ret = ptcl_init(rtwdev, mac_idx); 2566 if (ret) { 2567 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2568 return ret; 2569 } 2570 2571 ret = cmac_dma_init(rtwdev, mac_idx); 2572 if (ret) { 2573 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2574 return ret; 2575 } 2576 2577 return ret; 2578 } 2579 2580 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2581 struct rtw89_mac_c2h_info *c2h_info) 2582 { 2583 struct rtw89_mac_h2c_info h2c_info = {0}; 2584 u32 ret; 2585 2586 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2587 h2c_info.content_len = 0; 2588 2589 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2590 if (ret) 2591 return ret; 2592 2593 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2594 return -EINVAL; 2595 2596 return 0; 2597 } 2598 2599 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2600 { 2601 struct rtw89_hal *hal = &rtwdev->hal; 2602 const struct rtw89_chip_info *chip = rtwdev->chip; 2603 struct rtw89_mac_c2h_info c2h_info = {0}; 2604 u8 tx_nss; 2605 u8 rx_nss; 2606 u8 tx_ant; 2607 u8 rx_ant; 2608 u32 ret; 2609 2610 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2611 if (ret) 2612 return ret; 2613 2614 tx_nss = RTW89_GET_C2H_PHYCAP_TX_NSS(c2h_info.c2hreg); 2615 rx_nss = RTW89_GET_C2H_PHYCAP_RX_NSS(c2h_info.c2hreg); 2616 tx_ant = RTW89_GET_C2H_PHYCAP_ANT_TX_NUM(c2h_info.c2hreg); 2617 rx_ant = RTW89_GET_C2H_PHYCAP_ANT_RX_NUM(c2h_info.c2hreg); 2618 2619 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2620 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2621 2622 if (tx_ant == 1) 2623 hal->antenna_tx = RF_B; 2624 if (rx_ant == 1) 2625 hal->antenna_rx = RF_B; 2626 2627 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2628 hal->antenna_tx = RF_B; 2629 hal->tx_path_diversity = true; 2630 } 2631 2632 rtw89_debug(rtwdev, RTW89_DBG_FW, 2633 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2634 hal->tx_nss, tx_nss, chip->tx_nss, 2635 hal->rx_nss, rx_nss, chip->rx_nss); 2636 rtw89_debug(rtwdev, RTW89_DBG_FW, 2637 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2638 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2639 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2640 2641 return 0; 2642 } 2643 2644 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2645 u16 tx_en_u16, u16 mask_u16) 2646 { 2647 u32 ret; 2648 struct rtw89_mac_c2h_info c2h_info = {0}; 2649 struct rtw89_mac_h2c_info h2c_info = {0}; 2650 struct rtw89_h2creg_sch_tx_en *h2creg = 2651 (struct rtw89_h2creg_sch_tx_en *)h2c_info.h2creg; 2652 2653 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2654 h2c_info.content_len = sizeof(*h2creg) - RTW89_H2CREG_HDR_LEN; 2655 h2creg->tx_en = tx_en_u16; 2656 h2creg->mask = mask_u16; 2657 h2creg->band = band; 2658 2659 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2660 if (ret) 2661 return ret; 2662 2663 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2664 return -EINVAL; 2665 2666 return 0; 2667 } 2668 2669 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2670 u16 tx_en, u16 tx_en_mask) 2671 { 2672 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx); 2673 u16 val; 2674 int ret; 2675 2676 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2677 if (ret) 2678 return ret; 2679 2680 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 2681 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 2682 tx_en, tx_en_mask); 2683 2684 val = rtw89_read16(rtwdev, reg); 2685 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2686 rtw89_write16(rtwdev, reg, val); 2687 2688 return 0; 2689 } 2690 2691 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2692 u32 tx_en, u32 tx_en_mask) 2693 { 2694 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx); 2695 u32 val; 2696 int ret; 2697 2698 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2699 if (ret) 2700 return ret; 2701 2702 val = rtw89_read32(rtwdev, reg); 2703 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2704 rtw89_write32(rtwdev, reg, val); 2705 2706 return 0; 2707 } 2708 2709 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 2710 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2711 { 2712 int ret; 2713 2714 *tx_en = rtw89_read16(rtwdev, 2715 rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx)); 2716 2717 switch (sel) { 2718 case RTW89_SCH_TX_SEL_ALL: 2719 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2720 B_AX_CTN_TXEN_ALL_MASK); 2721 if (ret) 2722 return ret; 2723 break; 2724 case RTW89_SCH_TX_SEL_HIQ: 2725 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2726 0, B_AX_CTN_TXEN_HGQ); 2727 if (ret) 2728 return ret; 2729 break; 2730 case RTW89_SCH_TX_SEL_MG0: 2731 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2732 0, B_AX_CTN_TXEN_MGQ); 2733 if (ret) 2734 return ret; 2735 break; 2736 case RTW89_SCH_TX_SEL_MACID: 2737 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2738 B_AX_CTN_TXEN_ALL_MASK); 2739 if (ret) 2740 return ret; 2741 break; 2742 default: 2743 return 0; 2744 } 2745 2746 return 0; 2747 } 2748 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 2749 2750 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2751 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2752 { 2753 int ret; 2754 2755 *tx_en = rtw89_read32(rtwdev, 2756 rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx)); 2757 2758 switch (sel) { 2759 case RTW89_SCH_TX_SEL_ALL: 2760 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2761 B_AX_CTN_TXEN_ALL_MASK_V1); 2762 if (ret) 2763 return ret; 2764 break; 2765 case RTW89_SCH_TX_SEL_HIQ: 2766 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2767 0, B_AX_CTN_TXEN_HGQ); 2768 if (ret) 2769 return ret; 2770 break; 2771 case RTW89_SCH_TX_SEL_MG0: 2772 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2773 0, B_AX_CTN_TXEN_MGQ); 2774 if (ret) 2775 return ret; 2776 break; 2777 case RTW89_SCH_TX_SEL_MACID: 2778 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2779 B_AX_CTN_TXEN_ALL_MASK_V1); 2780 if (ret) 2781 return ret; 2782 break; 2783 default: 2784 return 0; 2785 } 2786 2787 return 0; 2788 } 2789 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 2790 2791 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2792 { 2793 int ret; 2794 2795 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 2796 if (ret) 2797 return ret; 2798 2799 return 0; 2800 } 2801 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 2802 2803 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2804 { 2805 int ret; 2806 2807 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 2808 B_AX_CTN_TXEN_ALL_MASK_V1); 2809 if (ret) 2810 return ret; 2811 2812 return 0; 2813 } 2814 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 2815 2816 int rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 2817 { 2818 u32 val, reg; 2819 int ret; 2820 2821 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 2822 val = buf_len; 2823 val |= B_AX_WD_BUF_REQ_EXEC; 2824 rtw89_write32(rtwdev, reg, val); 2825 2826 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 2827 2828 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 2829 1, 2000, false, rtwdev, reg); 2830 if (ret) 2831 return ret; 2832 2833 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 2834 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 2835 return -ENOENT; 2836 2837 return 0; 2838 } 2839 2840 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, 2841 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 2842 { 2843 u32 val, cmd_type, reg; 2844 int ret; 2845 2846 cmd_type = ctrl_para->cmd_type; 2847 2848 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 2849 val = 0; 2850 val = u32_replace_bits(val, ctrl_para->start_pktid, 2851 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 2852 val = u32_replace_bits(val, ctrl_para->end_pktid, 2853 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 2854 rtw89_write32(rtwdev, reg, val); 2855 2856 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 2857 val = 0; 2858 val = u32_replace_bits(val, ctrl_para->src_pid, 2859 B_AX_CPUQ_OP_SRC_PID_MASK); 2860 val = u32_replace_bits(val, ctrl_para->src_qid, 2861 B_AX_CPUQ_OP_SRC_QID_MASK); 2862 val = u32_replace_bits(val, ctrl_para->dst_pid, 2863 B_AX_CPUQ_OP_DST_PID_MASK); 2864 val = u32_replace_bits(val, ctrl_para->dst_qid, 2865 B_AX_CPUQ_OP_DST_QID_MASK); 2866 rtw89_write32(rtwdev, reg, val); 2867 2868 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 2869 val = 0; 2870 val = u32_replace_bits(val, cmd_type, 2871 B_AX_CPUQ_OP_CMD_TYPE_MASK); 2872 val = u32_replace_bits(val, ctrl_para->macid, 2873 B_AX_CPUQ_OP_MACID_MASK); 2874 val = u32_replace_bits(val, ctrl_para->pkt_num, 2875 B_AX_CPUQ_OP_PKTNUM_MASK); 2876 val |= B_AX_WD_CPUQ_OP_EXEC; 2877 rtw89_write32(rtwdev, reg, val); 2878 2879 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 2880 2881 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 2882 1, 2000, false, rtwdev, reg); 2883 if (ret) 2884 return ret; 2885 2886 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 2887 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 2888 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 2889 2890 return 0; 2891 } 2892 2893 static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2894 { 2895 const struct rtw89_dle_mem *cfg; 2896 struct rtw89_cpuio_ctrl ctrl_para = {0}; 2897 u16 pkt_id; 2898 int ret; 2899 2900 cfg = get_dle_mem_cfg(rtwdev, mode); 2901 if (!cfg) { 2902 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2903 return -EINVAL; 2904 } 2905 2906 if (dle_used_size(cfg->wde_size, cfg->ple_size) != 2907 dle_expected_used_size(rtwdev, mode)) { 2908 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2909 return -EINVAL; 2910 } 2911 2912 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 2913 2914 ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, true, &pkt_id); 2915 if (ret) { 2916 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 2917 return ret; 2918 } 2919 2920 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2921 ctrl_para.start_pktid = pkt_id; 2922 ctrl_para.end_pktid = pkt_id; 2923 ctrl_para.pkt_num = 0; 2924 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 2925 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 2926 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true); 2927 if (ret) { 2928 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 2929 return -EFAULT; 2930 } 2931 2932 ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, false, &pkt_id); 2933 if (ret) { 2934 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 2935 return ret; 2936 } 2937 2938 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2939 ctrl_para.start_pktid = pkt_id; 2940 ctrl_para.end_pktid = pkt_id; 2941 ctrl_para.pkt_num = 0; 2942 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 2943 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 2944 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false); 2945 if (ret) { 2946 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 2947 return -EFAULT; 2948 } 2949 2950 return 0; 2951 } 2952 2953 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 2954 { 2955 int ret; 2956 u32 reg; 2957 u8 val; 2958 2959 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2960 if (ret) 2961 return ret; 2962 2963 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_TX_CTN_SEL, mac_idx); 2964 2965 ret = read_poll_timeout(rtw89_read8, val, 2966 (val & B_AX_PTCL_TX_ON_STAT) == 0, 2967 SW_CVR_DUR_US, 2968 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 2969 false, rtwdev, reg); 2970 if (ret) 2971 return ret; 2972 2973 return 0; 2974 } 2975 2976 static int band1_enable(struct rtw89_dev *rtwdev) 2977 { 2978 int ret, i; 2979 u32 sleep_bak[4] = {0}; 2980 u32 pause_bak[4] = {0}; 2981 u32 tx_en; 2982 2983 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 2984 if (ret) { 2985 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 2986 return ret; 2987 } 2988 2989 for (i = 0; i < 4; i++) { 2990 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 2991 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 2992 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 2993 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 2994 } 2995 2996 ret = band_idle_ck_b(rtwdev, 0); 2997 if (ret) { 2998 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 2999 return ret; 3000 } 3001 3002 ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode); 3003 if (ret) { 3004 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3005 return ret; 3006 } 3007 3008 for (i = 0; i < 4; i++) { 3009 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3010 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3011 } 3012 3013 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3014 if (ret) { 3015 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3016 return ret; 3017 } 3018 3019 ret = cmac_func_en(rtwdev, 1, true); 3020 if (ret) { 3021 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3022 return ret; 3023 } 3024 3025 ret = cmac_init(rtwdev, 1); 3026 if (ret) { 3027 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3028 return ret; 3029 } 3030 3031 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3032 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3033 3034 return 0; 3035 } 3036 3037 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3038 { 3039 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3040 3041 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3042 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3043 } 3044 3045 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3046 { 3047 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3048 3049 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3050 } 3051 3052 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3053 { 3054 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3055 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3056 3057 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3058 B_AX_TX_GET_ERRPKTID_INT_EN | 3059 B_AX_TX_NXT_ERRPKTID_INT_EN | 3060 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3061 B_AX_TX_OFFSET_ERR_INT_EN | 3062 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3063 if (chip_id == RTL8852C) 3064 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3065 B_AX_TX_ETH_TYPE_ERR_EN | 3066 B_AX_TX_LLC_PRE_ERR_EN | 3067 B_AX_TX_NW_TYPE_ERR_EN | 3068 B_AX_TX_KSRCH_ERR_EN); 3069 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3070 imr->mpdu_tx_imr_set); 3071 3072 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3073 B_AX_GETPKTID_ERR_INT_EN | 3074 B_AX_MHDRLEN_ERR_INT_EN | 3075 B_AX_RPT_ERR_INT_EN); 3076 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3077 imr->mpdu_rx_imr_set); 3078 } 3079 3080 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3081 { 3082 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3083 3084 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3085 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3086 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3087 B_AX_PLE_B_PKTID_ERR_INT_EN); 3088 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3089 imr->sta_sch_imr_set); 3090 } 3091 3092 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3093 { 3094 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3095 3096 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3097 imr->txpktctl_imr_b0_clr); 3098 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3099 imr->txpktctl_imr_b0_set); 3100 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3101 imr->txpktctl_imr_b1_clr); 3102 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3103 imr->txpktctl_imr_b1_set); 3104 } 3105 3106 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3107 { 3108 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3109 3110 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3111 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3112 } 3113 3114 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3115 { 3116 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3117 3118 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3119 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3120 } 3121 3122 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3123 { 3124 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3125 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3126 } 3127 3128 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3129 { 3130 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3131 3132 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3133 imr->host_disp_imr_clr); 3134 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3135 imr->host_disp_imr_set); 3136 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3137 imr->cpu_disp_imr_clr); 3138 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3139 imr->cpu_disp_imr_set); 3140 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3141 imr->other_disp_imr_clr); 3142 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3143 imr->other_disp_imr_set); 3144 } 3145 3146 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3147 { 3148 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3149 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3150 } 3151 3152 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3153 { 3154 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3155 3156 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3157 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3158 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3159 B_AX_BBRPT_CHINFO_IMR_CLR); 3160 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3161 imr->bbrpt_err_imr_set); 3162 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3163 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3164 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3165 } 3166 3167 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3168 { 3169 u32 reg; 3170 3171 reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx); 3172 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3173 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3174 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3175 } 3176 3177 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3178 { 3179 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3180 u32 reg; 3181 3182 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx); 3183 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3184 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3185 } 3186 3187 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3188 { 3189 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3190 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3191 u32 reg; 3192 3193 reg = rtw89_mac_reg_by_idx(imr->cdma_imr_0_reg, mac_idx); 3194 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3195 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3196 3197 if (chip_id == RTL8852C) { 3198 reg = rtw89_mac_reg_by_idx(imr->cdma_imr_1_reg, mac_idx); 3199 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3200 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3201 } 3202 } 3203 3204 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3205 { 3206 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3207 u32 reg; 3208 3209 reg = rtw89_mac_reg_by_idx(imr->phy_intf_imr_reg, mac_idx); 3210 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3211 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3212 } 3213 3214 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3215 { 3216 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3217 u32 reg; 3218 3219 reg = rtw89_mac_reg_by_idx(imr->rmac_imr_reg, mac_idx); 3220 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3221 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3222 } 3223 3224 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3225 { 3226 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3227 u32 reg; 3228 3229 reg = rtw89_mac_reg_by_idx(imr->tmac_imr_reg, mac_idx); 3230 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3231 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3232 } 3233 3234 static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, 3235 enum rtw89_mac_hwmod_sel sel) 3236 { 3237 int ret; 3238 3239 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3240 if (ret) { 3241 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3242 sel, mac_idx); 3243 return ret; 3244 } 3245 3246 if (sel == RTW89_DMAC_SEL) { 3247 rtw89_wdrls_imr_enable(rtwdev); 3248 rtw89_wsec_imr_enable(rtwdev); 3249 rtw89_mpdu_trx_imr_enable(rtwdev); 3250 rtw89_sta_sch_imr_enable(rtwdev); 3251 rtw89_txpktctl_imr_enable(rtwdev); 3252 rtw89_wde_imr_enable(rtwdev); 3253 rtw89_ple_imr_enable(rtwdev); 3254 rtw89_pktin_imr_enable(rtwdev); 3255 rtw89_dispatcher_imr_enable(rtwdev); 3256 rtw89_cpuio_imr_enable(rtwdev); 3257 rtw89_bbrpt_imr_enable(rtwdev); 3258 } else if (sel == RTW89_CMAC_SEL) { 3259 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3260 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3261 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3262 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3263 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3264 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3265 } else { 3266 return -EINVAL; 3267 } 3268 3269 return 0; 3270 } 3271 3272 static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en) 3273 { 3274 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3275 3276 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3277 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3278 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3279 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3280 if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta) 3281 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3282 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3283 } 3284 3285 static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) 3286 { 3287 int ret = 0; 3288 3289 if (enable) { 3290 ret = band1_enable(rtwdev); 3291 if (ret) { 3292 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3293 return ret; 3294 } 3295 3296 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3297 if (ret) { 3298 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3299 return ret; 3300 } 3301 } else { 3302 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3303 return -EINVAL; 3304 } 3305 3306 return 0; 3307 } 3308 3309 static int set_host_rpr(struct rtw89_dev *rtwdev) 3310 { 3311 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3312 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3313 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3314 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3315 B_AX_RLSRPT0_FLTR_MAP_MASK); 3316 } else { 3317 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3318 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3319 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3320 B_AX_RLSRPT0_FLTR_MAP_MASK); 3321 } 3322 3323 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3324 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3325 3326 return 0; 3327 } 3328 3329 static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) 3330 { 3331 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3332 int ret; 3333 3334 ret = dmac_init(rtwdev, 0); 3335 if (ret) { 3336 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3337 return ret; 3338 } 3339 3340 ret = cmac_init(rtwdev, 0); 3341 if (ret) { 3342 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3343 return ret; 3344 } 3345 3346 if (is_qta_dbcc(rtwdev, qta_mode)) { 3347 ret = rtw89_mac_dbcc_enable(rtwdev, true); 3348 if (ret) { 3349 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3350 return ret; 3351 } 3352 } 3353 3354 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3355 if (ret) { 3356 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3357 return ret; 3358 } 3359 3360 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3361 if (ret) { 3362 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3363 return ret; 3364 } 3365 3366 rtw89_mac_err_imr_ctrl(rtwdev, true); 3367 3368 ret = set_host_rpr(rtwdev); 3369 if (ret) { 3370 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3371 return ret; 3372 } 3373 3374 return 0; 3375 } 3376 3377 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3378 { 3379 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3380 u32 val32; 3381 3382 if (chip_id == RTL8852B || chip_id == RTL8851B) { 3383 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3384 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3385 return; 3386 } 3387 3388 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3389 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3390 3391 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3392 val32 |= B_AX_FS_WDT_INT; 3393 val32 &= ~B_AX_FS_WDT_INT_MSK; 3394 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3395 } 3396 3397 void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev) 3398 { 3399 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3400 3401 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3402 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3403 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3404 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3405 3406 rtw89_disable_fw_watchdog(rtwdev); 3407 3408 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3409 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3410 } 3411 3412 int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw) 3413 { 3414 u32 val; 3415 int ret; 3416 3417 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3418 return -EFAULT; 3419 3420 rtw89_write32(rtwdev, R_AX_UDM1, 0); 3421 rtw89_write32(rtwdev, R_AX_UDM2, 0); 3422 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3423 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3424 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3425 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3426 3427 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3428 3429 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3430 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3431 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3432 B_AX_WCPU_FWDL_STS_MASK); 3433 3434 if (dlfw) 3435 val |= B_AX_WCPU_FWDL_EN; 3436 3437 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3438 3439 if (rtwdev->chip->chip_id == RTL8852B) 3440 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 3441 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 3442 3443 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3444 boot_reason); 3445 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3446 3447 if (!dlfw) { 3448 mdelay(5); 3449 3450 ret = rtw89_fw_check_rdy(rtwdev); 3451 if (ret) 3452 return ret; 3453 } 3454 3455 return 0; 3456 } 3457 3458 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3459 { 3460 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3461 u32 val; 3462 int ret; 3463 3464 if (chip_id == RTL8852C) 3465 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3466 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3467 else 3468 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3469 B_AX_PKT_BUF_EN; 3470 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3471 3472 if (chip_id == RTL8851B) 3473 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 3474 else 3475 val = B_AX_DISPATCHER_CLK_EN; 3476 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3477 3478 if (chip_id != RTL8852C) 3479 goto dle; 3480 3481 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3482 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3483 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3484 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3485 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3486 3487 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3488 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3489 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3490 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3491 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3492 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3493 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3494 3495 dle: 3496 ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3497 if (ret) { 3498 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3499 return ret; 3500 } 3501 3502 ret = hfc_init(rtwdev, true, false, true); 3503 if (ret) { 3504 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3505 return ret; 3506 } 3507 3508 return ret; 3509 } 3510 3511 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3512 { 3513 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3514 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3515 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3516 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3517 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3518 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3519 3520 return 0; 3521 } 3522 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3523 3524 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3525 { 3526 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3527 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3528 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3529 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3530 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3531 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3532 3533 return 0; 3534 } 3535 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3536 3537 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev) 3538 { 3539 int ret; 3540 3541 ret = rtw89_mac_power_switch(rtwdev, true); 3542 if (ret) { 3543 rtw89_mac_power_switch(rtwdev, false); 3544 ret = rtw89_mac_power_switch(rtwdev, true); 3545 if (ret) 3546 return ret; 3547 } 3548 3549 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3550 3551 ret = rtw89_mac_dmac_pre_init(rtwdev); 3552 if (ret) 3553 return ret; 3554 3555 if (rtwdev->hci.ops->mac_pre_init) { 3556 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3557 if (ret) 3558 return ret; 3559 } 3560 3561 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL); 3562 if (ret) 3563 return ret; 3564 3565 return 0; 3566 } 3567 3568 int rtw89_mac_init(struct rtw89_dev *rtwdev) 3569 { 3570 int ret; 3571 3572 ret = rtw89_mac_partial_init(rtwdev); 3573 if (ret) 3574 goto fail; 3575 3576 ret = rtw89_chip_enable_bb_rf(rtwdev); 3577 if (ret) 3578 goto fail; 3579 3580 ret = rtw89_mac_sys_init(rtwdev); 3581 if (ret) 3582 goto fail; 3583 3584 ret = rtw89_mac_trx_init(rtwdev); 3585 if (ret) 3586 goto fail; 3587 3588 if (rtwdev->hci.ops->mac_post_init) { 3589 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3590 if (ret) 3591 goto fail; 3592 } 3593 3594 rtw89_fw_send_all_early_h2c(rtwdev); 3595 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3596 3597 return ret; 3598 fail: 3599 rtw89_mac_power_switch(rtwdev, false); 3600 3601 return ret; 3602 } 3603 3604 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3605 { 3606 u8 i; 3607 3608 for (i = 0; i < 4; i++) { 3609 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3610 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 3611 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 3612 } 3613 } 3614 3615 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3616 { 3617 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3618 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 3619 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 3620 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 3621 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 3622 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 3623 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 3624 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 3625 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 3626 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 3627 } 3628 3629 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 3630 { 3631 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 3632 u8 grp = macid >> 5; 3633 int ret; 3634 3635 /* If this is called by change_interface() in the case of P2P, it could 3636 * be power-off, so ignore this operation. 3637 */ 3638 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 3639 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3640 return 0; 3641 3642 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3643 if (ret) 3644 return ret; 3645 3646 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 3647 3648 return 0; 3649 } 3650 3651 static const struct rtw89_port_reg rtw_port_base = { 3652 .port_cfg = R_AX_PORT_CFG_P0, 3653 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 3654 .bcn_area = R_AX_BCN_AREA_P0, 3655 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 3656 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 3657 .tbtt_agg = R_AX_TBTT_AGG_P0, 3658 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 3659 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 3660 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 3661 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 3662 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 3663 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 3664 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 3665 .tsftr_l = R_AX_TSFTR_LOW_P0, 3666 .tsftr_h = R_AX_TSFTR_HIGH_P0 3667 }; 3668 3669 #define BCN_INTERVAL 100 3670 #define BCN_ERLY_DEF 160 3671 #define BCN_SETUP_DEF 2 3672 #define BCN_HOLD_DEF 200 3673 #define BCN_MASK_DEF 0 3674 #define TBTT_ERLY_DEF 5 3675 #define BCN_SET_UNIT 32 3676 #define BCN_ERLY_SET_DLY (10 * 2) 3677 3678 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 3679 struct rtw89_vif *rtwvif) 3680 { 3681 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3682 const struct rtw89_port_reg *p = &rtw_port_base; 3683 3684 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 3685 return; 3686 3687 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 3688 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 3689 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 3690 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 3691 3692 msleep(vif->bss_conf.beacon_int + 1); 3693 3694 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 3695 B_AX_BRK_SETUP); 3696 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 3697 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 3698 } 3699 3700 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 3701 struct rtw89_vif *rtwvif, bool en) 3702 { 3703 const struct rtw89_port_reg *p = &rtw_port_base; 3704 3705 if (en) 3706 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3707 else 3708 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3709 } 3710 3711 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 3712 struct rtw89_vif *rtwvif, bool en) 3713 { 3714 const struct rtw89_port_reg *p = &rtw_port_base; 3715 3716 if (en) 3717 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3718 else 3719 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3720 } 3721 3722 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 3723 struct rtw89_vif *rtwvif) 3724 { 3725 const struct rtw89_port_reg *p = &rtw_port_base; 3726 3727 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 3728 rtwvif->net_type); 3729 } 3730 3731 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 3732 struct rtw89_vif *rtwvif) 3733 { 3734 const struct rtw89_port_reg *p = &rtw_port_base; 3735 bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 3736 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 3737 3738 if (en) 3739 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 3740 else 3741 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 3742 } 3743 3744 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 3745 struct rtw89_vif *rtwvif) 3746 { 3747 const struct rtw89_port_reg *p = &rtw_port_base; 3748 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3749 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3750 u32 bit = B_AX_RX_BSSID_FIT_EN; 3751 3752 if (en) 3753 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 3754 else 3755 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 3756 } 3757 3758 static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 3759 struct rtw89_vif *rtwvif) 3760 { 3761 const struct rtw89_port_reg *p = &rtw_port_base; 3762 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3763 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3764 3765 if (en) 3766 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3767 else 3768 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3769 } 3770 3771 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 3772 struct rtw89_vif *rtwvif) 3773 { 3774 const struct rtw89_port_reg *p = &rtw_port_base; 3775 bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 3776 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3777 3778 if (en) 3779 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3780 else 3781 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3782 } 3783 3784 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 3785 struct rtw89_vif *rtwvif) 3786 { 3787 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3788 const struct rtw89_port_reg *p = &rtw_port_base; 3789 u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 3790 3791 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 3792 bcn_int); 3793 } 3794 3795 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 3796 struct rtw89_vif *rtwvif) 3797 { 3798 static const u32 hiq_win_addr[RTW89_PORT_NUM] = { 3799 R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 3800 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 3801 R_AX_PORT_HGQ_WINDOW_CFG + 3, 3802 }; 3803 u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 3804 u8 port = rtwvif->port; 3805 u32 reg; 3806 3807 reg = rtw89_mac_reg_by_idx(hiq_win_addr[port], rtwvif->mac_idx); 3808 rtw89_write8(rtwdev, reg, win); 3809 } 3810 3811 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 3812 struct rtw89_vif *rtwvif) 3813 { 3814 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3815 const struct rtw89_port_reg *p = &rtw_port_base; 3816 u32 addr; 3817 3818 addr = rtw89_mac_reg_by_idx(R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx); 3819 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 3820 3821 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 3822 vif->bss_conf.dtim_period); 3823 } 3824 3825 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 3826 struct rtw89_vif *rtwvif) 3827 { 3828 const struct rtw89_port_reg *p = &rtw_port_base; 3829 3830 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3831 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 3832 } 3833 3834 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 3835 struct rtw89_vif *rtwvif) 3836 { 3837 const struct rtw89_port_reg *p = &rtw_port_base; 3838 3839 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3840 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 3841 } 3842 3843 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 3844 struct rtw89_vif *rtwvif) 3845 { 3846 const struct rtw89_port_reg *p = &rtw_port_base; 3847 3848 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 3849 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 3850 } 3851 3852 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 3853 struct rtw89_vif *rtwvif) 3854 { 3855 const struct rtw89_port_reg *p = &rtw_port_base; 3856 3857 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 3858 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 3859 } 3860 3861 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 3862 struct rtw89_vif *rtwvif) 3863 { 3864 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3865 static const u32 masks[RTW89_PORT_NUM] = { 3866 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 3867 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 3868 B_AX_BSS_COLOB_AX_PORT_4_MASK, 3869 }; 3870 u8 port = rtwvif->port; 3871 u32 reg_base; 3872 u32 reg; 3873 u8 bss_color; 3874 3875 bss_color = vif->bss_conf.he_bss_color.color; 3876 reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0; 3877 reg = rtw89_mac_reg_by_idx(reg_base, rtwvif->mac_idx); 3878 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 3879 } 3880 3881 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 3882 struct rtw89_vif *rtwvif) 3883 { 3884 u8 port = rtwvif->port; 3885 u32 reg; 3886 3887 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 3888 return; 3889 3890 if (port == 0) { 3891 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_CTRL, rtwvif->mac_idx); 3892 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 3893 } 3894 } 3895 3896 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 3897 struct rtw89_vif *rtwvif) 3898 { 3899 u8 port = rtwvif->port; 3900 u32 reg; 3901 u32 val; 3902 3903 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_DROP_0, rtwvif->mac_idx); 3904 val = rtw89_read32(rtwdev, reg); 3905 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 3906 if (port == 0) 3907 val &= ~BIT(0); 3908 rtw89_write32(rtwdev, reg, val); 3909 } 3910 3911 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 3912 struct rtw89_vif *rtwvif, bool enable) 3913 { 3914 const struct rtw89_port_reg *p = &rtw_port_base; 3915 3916 if (enable) 3917 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, 3918 B_AX_PORT_FUNC_EN); 3919 else 3920 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, 3921 B_AX_PORT_FUNC_EN); 3922 } 3923 3924 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 3925 struct rtw89_vif *rtwvif) 3926 { 3927 const struct rtw89_port_reg *p = &rtw_port_base; 3928 3929 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 3930 BCN_ERLY_DEF); 3931 } 3932 3933 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 3934 struct rtw89_vif *rtwvif) 3935 { 3936 const struct rtw89_port_reg *p = &rtw_port_base; 3937 u16 val; 3938 3939 if (rtwdev->chip->chip_id != RTL8852C) 3940 return; 3941 3942 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 3943 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 3944 return; 3945 3946 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 3947 B_AX_TBTT_SHIFT_OFST_SIGN; 3948 3949 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift, 3950 B_AX_TBTT_SHIFT_OFST_MASK, val); 3951 } 3952 3953 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 3954 struct rtw89_vif *rtwvif, 3955 struct rtw89_vif *rtwvif_src, 3956 u16 offset_tu) 3957 { 3958 u32 val, reg; 3959 3960 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 3961 reg = rtw89_mac_reg_by_idx(R_AX_PORT0_TSF_SYNC + rtwvif->port * 4, 3962 rtwvif->mac_idx); 3963 3964 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 3965 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 3966 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 3967 } 3968 3969 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 3970 struct rtw89_vif *rtwvif, 3971 struct rtw89_vif *rtwvif_src, 3972 u8 offset, int *n_offset) 3973 { 3974 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src) 3975 return; 3976 3977 /* adjust offset randomly to avoid beacon conflict */ 3978 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 3979 rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src, 3980 (*n_offset) * offset); 3981 3982 (*n_offset)++; 3983 } 3984 3985 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 3986 { 3987 struct rtw89_vif *src = NULL, *tmp; 3988 u8 offset = 100, vif_aps = 0; 3989 int n_offset = 1; 3990 3991 rtw89_for_each_rtwvif(rtwdev, tmp) { 3992 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 3993 src = tmp; 3994 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 3995 vif_aps++; 3996 } 3997 3998 if (vif_aps == 0) 3999 return; 4000 4001 offset /= (vif_aps + 1); 4002 4003 rtw89_for_each_rtwvif(rtwdev, tmp) 4004 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset); 4005 } 4006 4007 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4008 { 4009 int ret; 4010 4011 ret = rtw89_mac_port_update(rtwdev, rtwvif); 4012 if (ret) 4013 return ret; 4014 4015 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 4016 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 4017 4018 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 4019 if (ret) 4020 return ret; 4021 4022 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 4023 if (ret) 4024 return ret; 4025 4026 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true); 4027 if (ret) 4028 return ret; 4029 4030 ret = rtw89_cam_init(rtwdev, rtwvif); 4031 if (ret) 4032 return ret; 4033 4034 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4035 if (ret) 4036 return ret; 4037 4038 ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif); 4039 if (ret) 4040 return ret; 4041 4042 return 0; 4043 } 4044 4045 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4046 { 4047 int ret; 4048 4049 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 4050 if (ret) 4051 return ret; 4052 4053 rtw89_cam_deinit(rtwdev, rtwvif); 4054 4055 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4056 if (ret) 4057 return ret; 4058 4059 return 0; 4060 } 4061 4062 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4063 { 4064 u8 port = rtwvif->port; 4065 4066 if (port >= RTW89_PORT_NUM) 4067 return -EINVAL; 4068 4069 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4070 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 4071 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 4072 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 4073 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 4074 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 4075 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); 4076 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif); 4077 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 4078 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 4079 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 4080 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 4081 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 4082 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 4083 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 4084 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 4085 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif); 4086 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 4087 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 4088 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true); 4089 rtw89_mac_port_tsf_resync_all(rtwdev); 4090 fsleep(BCN_ERLY_SET_DLY); 4091 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 4092 4093 return 0; 4094 } 4095 4096 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4097 u64 *tsf) 4098 { 4099 const struct rtw89_port_reg *p = &rtw_port_base; 4100 u32 tsf_low, tsf_high; 4101 int ret; 4102 4103 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL); 4104 if (ret) 4105 return ret; 4106 4107 tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l); 4108 tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h); 4109 *tsf = (u64)tsf_high << 32 | tsf_low; 4110 4111 return 0; 4112 } 4113 4114 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 4115 struct cfg80211_bss *bss, 4116 void *data) 4117 { 4118 const struct cfg80211_bss_ies *ies; 4119 const struct element *elem; 4120 bool *tolerated = data; 4121 4122 rcu_read_lock(); 4123 ies = rcu_dereference(bss->ies); 4124 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 4125 ies->len); 4126 4127 if (!elem || elem->datalen < 10 || 4128 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 4129 *tolerated = false; 4130 rcu_read_unlock(); 4131 } 4132 4133 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 4134 struct ieee80211_vif *vif) 4135 { 4136 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4137 struct ieee80211_hw *hw = rtwdev->hw; 4138 bool tolerated = true; 4139 u32 reg; 4140 4141 if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION) 4142 return; 4143 4144 if (!(vif->bss_conf.chandef.chan->flags & IEEE80211_CHAN_RADAR)) 4145 return; 4146 4147 cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chandef, 4148 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 4149 &tolerated); 4150 4151 reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx); 4152 if (tolerated) 4153 rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 4154 else 4155 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 4156 } 4157 4158 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4159 { 4160 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, false); 4161 } 4162 4163 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4164 { 4165 int ret; 4166 4167 rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 4168 RTW89_MAX_MAC_ID_NUM); 4169 if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 4170 return -ENOSPC; 4171 4172 ret = rtw89_mac_vif_init(rtwdev, rtwvif); 4173 if (ret) 4174 goto release_mac_id; 4175 4176 return 0; 4177 4178 release_mac_id: 4179 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4180 4181 return ret; 4182 } 4183 4184 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4185 { 4186 int ret; 4187 4188 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 4189 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4190 4191 return ret; 4192 } 4193 4194 static void 4195 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4196 { 4197 } 4198 4199 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 4200 { 4201 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 4202 4203 return band == op->band_type && channel == op->primary_channel; 4204 } 4205 4206 static void 4207 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4208 u32 len) 4209 { 4210 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 4211 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 4212 struct rtw89_chan new; 4213 u8 reason, status, tx_fail, band, actual_period; 4214 u32 last_chan = rtwdev->scan_info.last_chan_idx; 4215 u16 chan; 4216 int ret; 4217 4218 if (!rtwvif) 4219 return; 4220 4221 tx_fail = RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h->data); 4222 status = RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h->data); 4223 chan = RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h->data); 4224 reason = RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h->data); 4225 band = RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h->data); 4226 actual_period = RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h->data); 4227 4228 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 4229 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 4230 4231 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4232 "band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 4233 band, chan, reason, status, tx_fail, actual_period); 4234 4235 switch (reason) { 4236 case RTW89_SCAN_LEAVE_CH_NOTIFY: 4237 if (rtw89_is_op_chan(rtwdev, band, chan)) 4238 ieee80211_stop_queues(rtwdev->hw); 4239 return; 4240 case RTW89_SCAN_END_SCAN_NOTIFY: 4241 if (rtwvif && rtwvif->scan_req && 4242 last_chan < rtwvif->scan_req->n_channels) { 4243 ret = rtw89_hw_scan_offload(rtwdev, vif, true); 4244 if (ret) { 4245 rtw89_hw_scan_abort(rtwdev, vif); 4246 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 4247 } 4248 } else { 4249 rtw89_hw_scan_complete(rtwdev, vif, false); 4250 } 4251 break; 4252 case RTW89_SCAN_ENTER_CH_NOTIFY: 4253 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4254 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4255 &rtwdev->scan_info.op_chan); 4256 ieee80211_wake_queues(rtwdev->hw); 4257 } else { 4258 rtw89_chan_create(&new, chan, chan, band, 4259 RTW89_CHANNEL_WIDTH_20); 4260 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4261 &new); 4262 } 4263 break; 4264 default: 4265 return; 4266 } 4267 } 4268 4269 static void 4270 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4271 struct sk_buff *skb) 4272 { 4273 struct ieee80211_vif *vif = rtwvif_to_vif_safe(rtwvif); 4274 enum nl80211_cqm_rssi_threshold_event nl_event; 4275 const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 4276 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 4277 u8 type, event, mac_id; 4278 s8 sig; 4279 4280 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 4281 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 4282 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 4283 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 4284 4285 if (mac_id != rtwvif->mac_id) 4286 return; 4287 4288 rtw89_debug(rtwdev, RTW89_DBG_FW, 4289 "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 4290 mac_id, type, sig, event); 4291 4292 switch (type) { 4293 case RTW89_BCN_FLTR_BEACON_LOSS: 4294 if (!rtwdev->scanning && !rtwvif->offchan) 4295 ieee80211_connection_loss(vif); 4296 else 4297 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 4298 return; 4299 case RTW89_BCN_FLTR_NOTIFY: 4300 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4301 break; 4302 case RTW89_BCN_FLTR_RSSI: 4303 if (event == RTW89_BCN_FLTR_RSSI_LOW) 4304 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 4305 else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 4306 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4307 else 4308 return; 4309 break; 4310 default: 4311 return; 4312 } 4313 4314 ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 4315 } 4316 4317 static void 4318 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4319 u32 len) 4320 { 4321 struct rtw89_vif *rtwvif; 4322 4323 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4324 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif, c2h); 4325 } 4326 4327 static void 4328 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4329 { 4330 rtw89_debug(rtwdev, RTW89_DBG_FW, 4331 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 4332 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 4333 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 4334 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 4335 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 4336 } 4337 4338 static void 4339 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4340 { 4341 rtw89_debug(rtwdev, RTW89_DBG_FW, 4342 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 4343 RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h->data), 4344 RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h->data), 4345 RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h->data), 4346 RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h->data), 4347 RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h->data)); 4348 } 4349 4350 static void 4351 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4352 { 4353 rtw89_info(rtwdev, "%*s", RTW89_GET_C2H_LOG_LEN(len), 4354 RTW89_GET_C2H_LOG_SRT_PRT(c2h->data)); 4355 } 4356 4357 static void 4358 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4359 { 4360 } 4361 4362 static void 4363 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4364 u32 len) 4365 { 4366 } 4367 4368 static void 4369 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4370 u32 len) 4371 { 4372 } 4373 4374 static void 4375 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4376 { 4377 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 4378 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 4379 4380 switch (func) { 4381 case H2C_FUNC_ADD_MCC: 4382 case H2C_FUNC_START_MCC: 4383 case H2C_FUNC_STOP_MCC: 4384 case H2C_FUNC_DEL_MCC_GROUP: 4385 case H2C_FUNC_RESET_MCC_GROUP: 4386 case H2C_FUNC_MCC_REQ_TSF: 4387 case H2C_FUNC_MCC_MACID_BITMAP: 4388 case H2C_FUNC_MCC_SYNC: 4389 case H2C_FUNC_MCC_SET_DURATION: 4390 break; 4391 default: 4392 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4393 "invalid MCC C2H RCV ACK: func %d\n", func); 4394 return; 4395 } 4396 4397 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4398 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 4399 } 4400 4401 static void 4402 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4403 { 4404 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 4405 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 4406 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 4407 struct rtw89_completion_data data = {}; 4408 unsigned int cond; 4409 bool next = false; 4410 4411 switch (func) { 4412 case H2C_FUNC_MCC_REQ_TSF: 4413 next = true; 4414 break; 4415 case H2C_FUNC_MCC_MACID_BITMAP: 4416 case H2C_FUNC_MCC_SYNC: 4417 case H2C_FUNC_MCC_SET_DURATION: 4418 break; 4419 case H2C_FUNC_ADD_MCC: 4420 case H2C_FUNC_START_MCC: 4421 case H2C_FUNC_STOP_MCC: 4422 case H2C_FUNC_DEL_MCC_GROUP: 4423 case H2C_FUNC_RESET_MCC_GROUP: 4424 default: 4425 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4426 "invalid MCC C2H REQ ACK: func %d\n", func); 4427 return; 4428 } 4429 4430 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4431 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 4432 group, func, retcode); 4433 4434 if (!retcode && next) 4435 return; 4436 4437 data.err = !!retcode; 4438 cond = RTW89_MCC_WAIT_COND(group, func); 4439 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4440 } 4441 4442 static void 4443 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4444 { 4445 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 4446 struct rtw89_completion_data data = {}; 4447 struct rtw89_mac_mcc_tsf_rpt *rpt; 4448 unsigned int cond; 4449 4450 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 4451 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 4452 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 4453 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 4454 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 4455 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 4456 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 4457 4458 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4459 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 4460 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 4461 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 4462 4463 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 4464 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4465 } 4466 4467 static void 4468 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4469 { 4470 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 4471 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 4472 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 4473 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 4474 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 4475 struct rtw89_completion_data data = {}; 4476 unsigned int cond; 4477 bool rsp = true; 4478 bool err; 4479 u8 func; 4480 4481 switch (status) { 4482 case RTW89_MAC_MCC_ADD_ROLE_OK: 4483 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 4484 func = H2C_FUNC_ADD_MCC; 4485 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 4486 break; 4487 case RTW89_MAC_MCC_START_GROUP_OK: 4488 case RTW89_MAC_MCC_START_GROUP_FAIL: 4489 func = H2C_FUNC_START_MCC; 4490 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 4491 break; 4492 case RTW89_MAC_MCC_STOP_GROUP_OK: 4493 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 4494 func = H2C_FUNC_STOP_MCC; 4495 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 4496 break; 4497 case RTW89_MAC_MCC_DEL_GROUP_OK: 4498 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 4499 func = H2C_FUNC_DEL_MCC_GROUP; 4500 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 4501 break; 4502 case RTW89_MAC_MCC_RESET_GROUP_OK: 4503 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 4504 func = H2C_FUNC_RESET_MCC_GROUP; 4505 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 4506 break; 4507 case RTW89_MAC_MCC_SWITCH_CH_OK: 4508 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 4509 case RTW89_MAC_MCC_TXNULL0_OK: 4510 case RTW89_MAC_MCC_TXNULL0_FAIL: 4511 case RTW89_MAC_MCC_TXNULL1_OK: 4512 case RTW89_MAC_MCC_TXNULL1_FAIL: 4513 case RTW89_MAC_MCC_SWITCH_EARLY: 4514 case RTW89_MAC_MCC_TBTT: 4515 case RTW89_MAC_MCC_DURATION_START: 4516 case RTW89_MAC_MCC_DURATION_END: 4517 rsp = false; 4518 break; 4519 default: 4520 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4521 "invalid MCC C2H STS RPT: status %d\n", status); 4522 return; 4523 } 4524 4525 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4526 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 4527 group, macid, status, (u64)tsf_high << 32 | tsf_low); 4528 4529 if (!rsp) 4530 return; 4531 4532 data.err = err; 4533 cond = RTW89_MCC_WAIT_COND(group, func); 4534 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4535 } 4536 4537 static 4538 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 4539 struct sk_buff *c2h, u32 len) = { 4540 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 4541 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 4542 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 4543 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 4544 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 4545 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 4546 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 4547 [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 4548 }; 4549 4550 static 4551 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 4552 struct sk_buff *c2h, u32 len) = { 4553 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 4554 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 4555 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 4556 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 4557 }; 4558 4559 static 4560 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 4561 struct sk_buff *c2h, u32 len) = { 4562 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 4563 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 4564 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 4565 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 4566 }; 4567 4568 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func) 4569 { 4570 switch (class) { 4571 default: 4572 return false; 4573 case RTW89_MAC_C2H_CLASS_MCC: 4574 return true; 4575 } 4576 } 4577 4578 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4579 u32 len, u8 class, u8 func) 4580 { 4581 void (*handler)(struct rtw89_dev *rtwdev, 4582 struct sk_buff *c2h, u32 len) = NULL; 4583 4584 switch (class) { 4585 case RTW89_MAC_C2H_CLASS_INFO: 4586 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 4587 handler = rtw89_mac_c2h_info_handler[func]; 4588 break; 4589 case RTW89_MAC_C2H_CLASS_OFLD: 4590 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 4591 handler = rtw89_mac_c2h_ofld_handler[func]; 4592 break; 4593 case RTW89_MAC_C2H_CLASS_MCC: 4594 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 4595 handler = rtw89_mac_c2h_mcc_handler[func]; 4596 break; 4597 case RTW89_MAC_C2H_CLASS_FWDBG: 4598 return; 4599 default: 4600 rtw89_info(rtwdev, "c2h class %d not support\n", class); 4601 return; 4602 } 4603 if (!handler) { 4604 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 4605 func); 4606 return; 4607 } 4608 handler(rtwdev, skb, len); 4609 } 4610 4611 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 4612 enum rtw89_phy_idx phy_idx, 4613 u32 reg_base, u32 *cr) 4614 { 4615 const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; 4616 enum rtw89_qta_mode mode = dle_mem->mode; 4617 u32 addr = rtw89_mac_reg_by_idx(reg_base, phy_idx); 4618 4619 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) { 4620 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 4621 addr); 4622 goto error; 4623 } 4624 4625 if (addr >= CMAC1_START_ADDR && addr <= CMAC1_END_ADDR) 4626 if (mode == RTW89_QTA_SCC) { 4627 rtw89_err(rtwdev, 4628 "[TXPWR] addr=0x%x but hw not enable\n", 4629 addr); 4630 goto error; 4631 } 4632 4633 *cr = addr; 4634 return true; 4635 4636 error: 4637 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 4638 addr, phy_idx); 4639 4640 return false; 4641 } 4642 EXPORT_SYMBOL(rtw89_mac_get_txpwr_cr); 4643 4644 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 4645 { 4646 u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx); 4647 int ret; 4648 4649 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4650 if (ret) 4651 return ret; 4652 4653 if (!enable) { 4654 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 4655 return 0; 4656 } 4657 4658 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 4659 B_AX_APP_MAC_INFO_RPT | 4660 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 4661 B_AX_PPDU_STAT_RPT_CRC32); 4662 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 4663 RTW89_PRPT_DEST_HOST); 4664 4665 return 0; 4666 } 4667 EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status); 4668 4669 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 4670 { 4671 #define MAC_AX_TIME_TH_SH 5 4672 #define MAC_AX_LEN_TH_SH 4 4673 #define MAC_AX_TIME_TH_MAX 255 4674 #define MAC_AX_LEN_TH_MAX 255 4675 #define MAC_AX_TIME_TH_DEF 88 4676 #define MAC_AX_LEN_TH_DEF 4080 4677 struct ieee80211_hw *hw = rtwdev->hw; 4678 u32 rts_threshold = hw->wiphy->rts_threshold; 4679 u32 time_th, len_th; 4680 u32 reg; 4681 4682 if (rts_threshold == (u32)-1) { 4683 time_th = MAC_AX_TIME_TH_DEF; 4684 len_th = MAC_AX_LEN_TH_DEF; 4685 } else { 4686 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 4687 len_th = rts_threshold; 4688 } 4689 4690 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 4691 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 4692 4693 reg = rtw89_mac_reg_by_idx(R_AX_AGG_LEN_HT_0, mac_idx); 4694 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 4695 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 4696 } 4697 4698 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 4699 { 4700 bool empty; 4701 int ret; 4702 4703 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4704 return; 4705 4706 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 4707 10000, 200000, false, rtwdev); 4708 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 4709 rtw89_info(rtwdev, "timed out to flush queues\n"); 4710 } 4711 4712 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 4713 { 4714 u8 val; 4715 u16 val16; 4716 u32 val32; 4717 int ret; 4718 4719 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 4720 if (rtwdev->chip->chip_id != RTL8851B) 4721 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 4722 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 4723 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 4724 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 4725 if (rtwdev->chip->chip_id != RTL8851B) 4726 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 4727 4728 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 4729 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 4730 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 4731 4732 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 4733 if (ret) { 4734 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 4735 return ret; 4736 } 4737 val32 = val32 & B_AX_WL_RX_CTRL; 4738 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 4739 if (ret) { 4740 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 4741 return ret; 4742 } 4743 4744 switch (coex->pta_mode) { 4745 case RTW89_MAC_AX_COEX_RTK_MODE: 4746 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4747 val &= ~B_AX_BTMODE_MASK; 4748 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 4749 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4750 4751 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 4752 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 4753 4754 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 4755 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 4756 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 4757 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 4758 break; 4759 case RTW89_MAC_AX_COEX_CSR_MODE: 4760 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4761 val &= ~B_AX_BTMODE_MASK; 4762 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 4763 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4764 4765 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 4766 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 4767 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 4768 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 4769 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 4770 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 4771 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 4772 val16 |= B_AX_ENHANCED_BT; 4773 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 4774 4775 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 4776 break; 4777 default: 4778 return -EINVAL; 4779 } 4780 4781 switch (coex->direction) { 4782 case RTW89_MAC_AX_COEX_INNER: 4783 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4784 val = (val & ~BIT(2)) | BIT(1); 4785 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4786 break; 4787 case RTW89_MAC_AX_COEX_OUTPUT: 4788 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4789 val = val | BIT(1) | BIT(0); 4790 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4791 break; 4792 case RTW89_MAC_AX_COEX_INPUT: 4793 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4794 val = val & ~(BIT(2) | BIT(1)); 4795 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4796 break; 4797 default: 4798 return -EINVAL; 4799 } 4800 4801 return 0; 4802 } 4803 EXPORT_SYMBOL(rtw89_mac_coex_init); 4804 4805 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 4806 const struct rtw89_mac_ax_coex *coex) 4807 { 4808 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 4809 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 4810 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 4811 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 4812 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 4813 4814 switch (coex->pta_mode) { 4815 case RTW89_MAC_AX_COEX_RTK_MODE: 4816 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4817 MAC_AX_RTK_MODE); 4818 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 4819 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 4820 break; 4821 case RTW89_MAC_AX_COEX_CSR_MODE: 4822 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4823 MAC_AX_CSR_MODE); 4824 break; 4825 default: 4826 return -EINVAL; 4827 } 4828 4829 return 0; 4830 } 4831 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 4832 4833 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 4834 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4835 { 4836 u32 val = 0, ret; 4837 4838 if (gnt_cfg->band[0].gnt_bt) 4839 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 4840 4841 if (gnt_cfg->band[0].gnt_bt_sw_en) 4842 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 4843 4844 if (gnt_cfg->band[0].gnt_wl) 4845 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 4846 4847 if (gnt_cfg->band[0].gnt_wl_sw_en) 4848 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 4849 4850 if (gnt_cfg->band[1].gnt_bt) 4851 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 4852 4853 if (gnt_cfg->band[1].gnt_bt_sw_en) 4854 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 4855 4856 if (gnt_cfg->band[1].gnt_wl) 4857 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 4858 4859 if (gnt_cfg->band[1].gnt_wl_sw_en) 4860 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 4861 4862 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 4863 if (ret) { 4864 rtw89_err(rtwdev, "Write LTE fail!\n"); 4865 return ret; 4866 } 4867 4868 return 0; 4869 } 4870 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 4871 4872 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 4873 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4874 { 4875 u32 val = 0; 4876 4877 if (gnt_cfg->band[0].gnt_bt) 4878 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 4879 B_AX_GNT_BT_TX_VAL; 4880 else 4881 val |= B_AX_WL_ACT_VAL; 4882 4883 if (gnt_cfg->band[0].gnt_bt_sw_en) 4884 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 4885 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 4886 4887 if (gnt_cfg->band[0].gnt_wl) 4888 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 4889 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 4890 4891 if (gnt_cfg->band[0].gnt_wl_sw_en) 4892 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 4893 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 4894 4895 if (gnt_cfg->band[1].gnt_bt) 4896 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 4897 B_AX_GNT_BT_TX_VAL; 4898 else 4899 val |= B_AX_WL_ACT_VAL; 4900 4901 if (gnt_cfg->band[1].gnt_bt_sw_en) 4902 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 4903 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 4904 4905 if (gnt_cfg->band[1].gnt_wl) 4906 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 4907 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 4908 4909 if (gnt_cfg->band[1].gnt_wl_sw_en) 4910 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 4911 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 4912 4913 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 4914 4915 return 0; 4916 } 4917 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 4918 4919 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 4920 { 4921 u32 reg; 4922 u16 val; 4923 int ret; 4924 4925 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 4926 if (ret) 4927 return ret; 4928 4929 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, plt->band); 4930 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 4931 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 4932 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 4933 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 4934 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 4935 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 4936 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 4937 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 4938 B_AX_PLT_EN; 4939 rtw89_write16(rtwdev, reg, val); 4940 4941 return 0; 4942 } 4943 4944 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 4945 { 4946 u32 fw_sb; 4947 4948 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 4949 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 4950 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 4951 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4952 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 4953 else 4954 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 4955 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 4956 val = B_AX_TOGGLE | 4957 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 4958 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 4959 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 4960 fsleep(1000); /* avoid BT FW loss information */ 4961 } 4962 4963 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 4964 { 4965 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 4966 } 4967 4968 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 4969 { 4970 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 4971 4972 val = wl ? val | BIT(2) : val & ~BIT(2); 4973 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 4974 4975 return 0; 4976 } 4977 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 4978 4979 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 4980 { 4981 struct rtw89_btc *btc = &rtwdev->btc; 4982 struct rtw89_btc_dm *dm = &btc->dm; 4983 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 4984 int i; 4985 4986 if (wl) 4987 return 0; 4988 4989 for (i = 0; i < RTW89_PHY_MAX; i++) { 4990 g[i].gnt_bt_sw_en = 1; 4991 g[i].gnt_bt = 1; 4992 g[i].gnt_wl_sw_en = 1; 4993 g[i].gnt_wl = 0; 4994 } 4995 4996 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 4997 } 4998 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 4999 5000 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 5001 { 5002 const struct rtw89_chip_info *chip = rtwdev->chip; 5003 u8 val = 0; 5004 5005 if (chip->chip_id == RTL8852C) 5006 return false; 5007 else if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) 5008 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 5009 B_AX_LTE_MUX_CTRL_PATH >> 24); 5010 5011 return !!val; 5012 } 5013 5014 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 5015 { 5016 u32 reg; 5017 u16 cnt; 5018 5019 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, band); 5020 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 5021 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 5022 5023 return cnt; 5024 } 5025 5026 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 5027 bool keep) 5028 { 5029 u32 reg; 5030 5031 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 5032 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 5033 if (keep) { 5034 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5035 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5036 BFRP_RX_STANDBY_TIMER_KEEP); 5037 } else { 5038 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5039 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5040 BFRP_RX_STANDBY_TIMER_RELEASE); 5041 } 5042 } 5043 5044 static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 5045 { 5046 u32 reg; 5047 u32 mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 5048 B_AX_BFMEE_HE_NDPA_EN; 5049 5050 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 5051 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 5052 if (en) { 5053 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5054 rtw89_write32_set(rtwdev, reg, mask); 5055 } else { 5056 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5057 rtw89_write32_clr(rtwdev, reg, mask); 5058 } 5059 } 5060 5061 static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx) 5062 { 5063 u32 reg; 5064 u32 val32; 5065 int ret; 5066 5067 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5068 if (ret) 5069 return ret; 5070 5071 /* AP mode set tx gid to 63 */ 5072 /* STA mode set tx gid to 0(default) */ 5073 reg = rtw89_mac_reg_by_idx(R_AX_BFMER_CTRL_0, mac_idx); 5074 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 5075 5076 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 5077 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 5078 5079 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 5080 val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 5081 rtw89_write32(rtwdev, reg, val32); 5082 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 5083 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 5084 5085 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5086 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 5087 B_AX_BFMEE_USE_NSTS | 5088 B_AX_BFMEE_CSI_GID_SEL | 5089 B_AX_BFMEE_CSI_FORCE_RETE_EN); 5090 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 5091 rtw89_write32(rtwdev, reg, 5092 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 5093 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 5094 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 5095 5096 reg = rtw89_mac_reg_by_idx(R_AX_CSIRPT_OPTION, mac_idx); 5097 rtw89_write32_set(rtwdev, reg, 5098 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 5099 5100 return 0; 5101 } 5102 5103 static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, 5104 struct ieee80211_vif *vif, 5105 struct ieee80211_sta *sta) 5106 { 5107 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5108 u8 mac_idx = rtwvif->mac_idx; 5109 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 5110 u8 port_sel = rtwvif->port; 5111 u8 sound_dim = 3, t; 5112 u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 5113 u32 reg; 5114 u16 val; 5115 int ret; 5116 5117 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5118 if (ret) 5119 return ret; 5120 5121 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5122 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 5123 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 5124 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 5125 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 5126 phy_cap[5]); 5127 sound_dim = min(sound_dim, t); 5128 } 5129 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5130 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 5131 ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 5132 stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 5133 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 5134 sta->deflink.vht_cap.cap); 5135 sound_dim = min(sound_dim, t); 5136 } 5137 nc = min(nc, sound_dim); 5138 nr = min(nr, sound_dim); 5139 5140 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5141 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5142 5143 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 5144 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 5145 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 5146 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 5147 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 5148 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 5149 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 5150 5151 if (port_sel == 0) 5152 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5153 else 5154 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 5155 5156 rtw89_write16(rtwdev, reg, val); 5157 5158 return 0; 5159 } 5160 5161 static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev, 5162 struct ieee80211_vif *vif, 5163 struct ieee80211_sta *sta) 5164 { 5165 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5166 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 5167 u32 reg; 5168 u8 mac_idx = rtwvif->mac_idx; 5169 int ret; 5170 5171 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5172 if (ret) 5173 return ret; 5174 5175 if (sta->deflink.he_cap.has_he) { 5176 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 5177 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 5178 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 5179 } 5180 if (sta->deflink.vht_cap.vht_supported) { 5181 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 5182 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 5183 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 5184 } 5185 if (sta->deflink.ht_cap.ht_supported) { 5186 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 5187 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 5188 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 5189 } 5190 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5191 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5192 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 5193 rtw89_write32(rtwdev, 5194 rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 5195 rrsc); 5196 5197 return 0; 5198 } 5199 5200 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5201 struct ieee80211_sta *sta) 5202 { 5203 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5204 5205 if (rtw89_sta_has_beamformer_cap(sta)) { 5206 rtw89_debug(rtwdev, RTW89_DBG_BF, 5207 "initialize bfee for new association\n"); 5208 rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx); 5209 rtw89_mac_set_csi_para_reg(rtwdev, vif, sta); 5210 rtw89_mac_csi_rrsc(rtwdev, vif, sta); 5211 } 5212 } 5213 5214 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5215 struct ieee80211_sta *sta) 5216 { 5217 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5218 5219 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 5220 } 5221 5222 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5223 struct ieee80211_bss_conf *conf) 5224 { 5225 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5226 u8 mac_idx = rtwvif->mac_idx; 5227 __le32 *p; 5228 5229 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 5230 5231 p = (__le32 *)conf->mu_group.membership; 5232 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx), 5233 le32_to_cpu(p[0])); 5234 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx), 5235 le32_to_cpu(p[1])); 5236 5237 p = (__le32 *)conf->mu_group.position; 5238 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx), 5239 le32_to_cpu(p[0])); 5240 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx), 5241 le32_to_cpu(p[1])); 5242 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx), 5243 le32_to_cpu(p[2])); 5244 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx), 5245 le32_to_cpu(p[3])); 5246 } 5247 5248 struct rtw89_mac_bf_monitor_iter_data { 5249 struct rtw89_dev *rtwdev; 5250 struct ieee80211_sta *down_sta; 5251 int count; 5252 }; 5253 5254 static 5255 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 5256 { 5257 struct rtw89_mac_bf_monitor_iter_data *iter_data = 5258 (struct rtw89_mac_bf_monitor_iter_data *)data; 5259 struct ieee80211_sta *down_sta = iter_data->down_sta; 5260 int *count = &iter_data->count; 5261 5262 if (down_sta == sta) 5263 return; 5264 5265 if (rtw89_sta_has_beamformer_cap(sta)) 5266 (*count)++; 5267 } 5268 5269 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 5270 struct ieee80211_sta *sta, bool disconnect) 5271 { 5272 struct rtw89_mac_bf_monitor_iter_data data; 5273 5274 data.rtwdev = rtwdev; 5275 data.down_sta = disconnect ? sta : NULL; 5276 data.count = 0; 5277 ieee80211_iterate_stations_atomic(rtwdev->hw, 5278 rtw89_mac_bf_monitor_calc_iter, 5279 &data); 5280 5281 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 5282 if (data.count) 5283 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5284 else 5285 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5286 } 5287 5288 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 5289 { 5290 struct rtw89_traffic_stats *stats = &rtwdev->stats; 5291 struct rtw89_vif *rtwvif; 5292 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 5293 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5294 bool keep_timer = true; 5295 bool old_keep_timer; 5296 5297 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5298 5299 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 5300 keep_timer = false; 5301 5302 if (keep_timer != old_keep_timer) { 5303 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5304 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx, 5305 keep_timer); 5306 } 5307 5308 if (en == old) 5309 return; 5310 5311 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5312 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 5313 } 5314 5315 static int 5316 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5317 u32 tx_time) 5318 { 5319 #define MAC_AX_DFLT_TX_TIME 5280 5320 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5321 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 5322 u32 reg; 5323 int ret = 0; 5324 5325 if (rtwsta->cctl_tx_time) { 5326 rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 5327 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5328 } else { 5329 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5330 if (ret) { 5331 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 5332 return ret; 5333 } 5334 5335 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 5336 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 5337 max_tx_time >> 5); 5338 } 5339 5340 return ret; 5341 } 5342 5343 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5344 bool resume, u32 tx_time) 5345 { 5346 int ret = 0; 5347 5348 if (!resume) { 5349 rtwsta->cctl_tx_time = true; 5350 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5351 } else { 5352 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5353 rtwsta->cctl_tx_time = false; 5354 } 5355 5356 return ret; 5357 } 5358 5359 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5360 u32 *tx_time) 5361 { 5362 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5363 u32 reg; 5364 int ret = 0; 5365 5366 if (rtwsta->cctl_tx_time) { 5367 *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 5368 } else { 5369 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5370 if (ret) { 5371 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 5372 return ret; 5373 } 5374 5375 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 5376 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 5377 } 5378 5379 return ret; 5380 } 5381 5382 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 5383 struct rtw89_sta *rtwsta, 5384 bool resume, u8 tx_retry) 5385 { 5386 int ret = 0; 5387 5388 rtwsta->data_tx_cnt_lmt = tx_retry; 5389 5390 if (!resume) { 5391 rtwsta->cctl_tx_retry_limit = true; 5392 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5393 } else { 5394 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5395 rtwsta->cctl_tx_retry_limit = false; 5396 } 5397 5398 return ret; 5399 } 5400 5401 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 5402 struct rtw89_sta *rtwsta, u8 *tx_retry) 5403 { 5404 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5405 u32 reg; 5406 int ret = 0; 5407 5408 if (rtwsta->cctl_tx_retry_limit) { 5409 *tx_retry = rtwsta->data_tx_cnt_lmt; 5410 } else { 5411 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5412 if (ret) { 5413 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 5414 return ret; 5415 } 5416 5417 reg = rtw89_mac_reg_by_idx(R_AX_TXCNT, mac_idx); 5418 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 5419 } 5420 5421 return ret; 5422 } 5423 5424 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 5425 struct rtw89_vif *rtwvif, bool en) 5426 { 5427 u8 mac_idx = rtwvif->mac_idx; 5428 u16 set = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0; 5429 u32 reg; 5430 u32 ret; 5431 5432 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5433 if (ret) 5434 return ret; 5435 5436 reg = rtw89_mac_reg_by_idx(R_AX_MUEDCA_EN, mac_idx); 5437 if (en) 5438 rtw89_write16_set(rtwdev, reg, set); 5439 else 5440 rtw89_write16_clr(rtwdev, reg, set); 5441 5442 return 0; 5443 } 5444 5445 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 5446 { 5447 u32 val32; 5448 int ret; 5449 5450 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 5451 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 5452 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 5453 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 5454 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 5455 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 5456 5457 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 5458 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 5459 if (ret) { 5460 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 5461 offset, val, mask); 5462 return ret; 5463 } 5464 5465 return 0; 5466 } 5467 EXPORT_SYMBOL(rtw89_mac_write_xtal_si); 5468 5469 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 5470 { 5471 u32 val32; 5472 int ret; 5473 5474 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 5475 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 5476 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 5477 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 5478 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 5479 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 5480 5481 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 5482 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 5483 if (ret) { 5484 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 5485 return ret; 5486 } 5487 5488 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 5489 5490 return 0; 5491 } 5492 EXPORT_SYMBOL(rtw89_mac_read_xtal_si); 5493 5494 static 5495 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 5496 { 5497 static const enum rtw89_pkt_drop_sel sels[] = { 5498 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 5499 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 5500 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 5501 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 5502 }; 5503 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5504 struct rtw89_pkt_drop_params params = {0}; 5505 int i; 5506 5507 params.mac_band = RTW89_MAC_0; 5508 params.macid = rtwsta->mac_id; 5509 params.port = rtwvif->port; 5510 params.mbssid = 0; 5511 params.tf_trs = rtwvif->trigger; 5512 5513 for (i = 0; i < ARRAY_SIZE(sels); i++) { 5514 params.sel = sels[i]; 5515 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 5516 } 5517 } 5518 5519 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 5520 { 5521 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 5522 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5523 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 5524 struct rtw89_vif *target = data; 5525 5526 if (rtwvif != target) 5527 return; 5528 5529 rtw89_mac_pkt_drop_sta(rtwdev, rtwsta); 5530 } 5531 5532 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 5533 { 5534 ieee80211_iterate_stations_atomic(rtwdev->hw, 5535 rtw89_mac_pkt_drop_vif_iter, 5536 rtwvif); 5537 } 5538 5539 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 5540 enum rtw89_mac_idx band) 5541 { 5542 struct rtw89_pkt_drop_params params = {0}; 5543 bool empty; 5544 int i, ret = 0, try_cnt = 3; 5545 5546 params.mac_band = band; 5547 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 5548 5549 for (i = 0; i < try_cnt; i++) { 5550 ret = read_poll_timeout(mac_is_txq_empty, empty, empty, 50, 5551 50000, false, rtwdev); 5552 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 5553 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 5554 else 5555 return 0; 5556 } 5557 return ret; 5558 } 5559