1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "debug.h" 7 #include "fw.h" 8 #include "mac.h" 9 #include "ps.h" 10 #include "reg.h" 11 #include "util.h" 12 13 const u32 rtw89_mac_mem_base_addrs[RTW89_MAC_MEM_NUM] = { 14 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 15 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 16 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 17 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 18 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 19 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 20 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 21 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 22 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 23 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 24 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 25 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 26 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 27 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 28 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 29 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 30 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 31 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 32 }; 33 34 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 35 u32 val, enum rtw89_mac_mem_sel sel) 36 { 37 u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; 38 39 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); 40 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, val); 41 } 42 43 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 44 enum rtw89_mac_mem_sel sel) 45 { 46 u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; 47 48 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); 49 return rtw89_read32(rtwdev, R_AX_INDIR_ACCESS_ENTRY); 50 } 51 52 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, 53 enum rtw89_mac_hwmod_sel sel) 54 { 55 u32 val, r_val; 56 57 if (sel == RTW89_DMAC_SEL) { 58 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 59 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 60 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 61 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 62 val = B_AX_CMAC_EN; 63 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 64 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 65 val = B_AX_CMAC1_FEN; 66 } else { 67 return -EINVAL; 68 } 69 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 70 (val & r_val) != val) 71 return -EFAULT; 72 73 return 0; 74 } 75 76 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 77 { 78 u8 lte_ctrl; 79 int ret; 80 81 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 82 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 83 if (ret) 84 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 85 86 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 87 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 88 89 return ret; 90 } 91 92 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 93 { 94 u8 lte_ctrl; 95 int ret; 96 97 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 98 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 99 if (ret) 100 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 101 102 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 103 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 104 105 return ret; 106 } 107 108 static 109 int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 110 { 111 u32 ctrl_reg, data_reg, ctrl_data; 112 u32 val; 113 int ret; 114 115 switch (ctrl->type) { 116 case DLE_CTRL_TYPE_WDE: 117 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 118 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 119 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 120 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 121 B_AX_WDE_DFI_ACTIVE; 122 break; 123 case DLE_CTRL_TYPE_PLE: 124 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 125 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 126 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 127 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 128 B_AX_PLE_DFI_ACTIVE; 129 break; 130 default: 131 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 132 return -EINVAL; 133 } 134 135 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 136 137 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 138 1, 1000, false, rtwdev, ctrl_reg); 139 if (ret) { 140 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 141 ctrl_reg, ctrl_data); 142 return ret; 143 } 144 145 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 146 return 0; 147 } 148 149 static int dle_dfi_quota(struct rtw89_dev *rtwdev, 150 struct rtw89_mac_dle_dfi_quota *quota) 151 { 152 struct rtw89_mac_dle_dfi_ctrl ctrl; 153 int ret; 154 155 ctrl.type = quota->dle_type; 156 ctrl.target = DLE_DFI_TYPE_QUOTA; 157 ctrl.addr = quota->qtaid; 158 ret = dle_dfi_ctrl(rtwdev, &ctrl); 159 if (ret) { 160 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 161 return ret; 162 } 163 164 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 165 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 166 return 0; 167 } 168 169 static int dle_dfi_qempty(struct rtw89_dev *rtwdev, 170 struct rtw89_mac_dle_dfi_qempty *qempty) 171 { 172 struct rtw89_mac_dle_dfi_ctrl ctrl; 173 u32 ret; 174 175 ctrl.type = qempty->dle_type; 176 ctrl.target = DLE_DFI_TYPE_QEMPTY; 177 ctrl.addr = qempty->grpsel; 178 ret = dle_dfi_ctrl(rtwdev, &ctrl); 179 if (ret) { 180 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 181 return ret; 182 } 183 184 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 185 return 0; 186 } 187 188 static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev) 189 { 190 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 191 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 192 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 193 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 194 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 195 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 196 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 197 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 198 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 199 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 200 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 201 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 202 } 203 204 static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) 205 { 206 struct rtw89_mac_dle_dfi_qempty qempty; 207 struct rtw89_mac_dle_dfi_quota quota; 208 struct rtw89_mac_dle_dfi_ctrl ctrl; 209 u32 val, not_empty, i; 210 int ret; 211 212 qempty.dle_type = DLE_CTRL_TYPE_PLE; 213 qempty.grpsel = 0; 214 qempty.qempty = ~(u32)0; 215 ret = dle_dfi_qempty(rtwdev, &qempty); 216 if (ret) 217 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 218 else 219 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 220 221 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 222 if (!(not_empty & BIT(0))) 223 continue; 224 ctrl.type = DLE_CTRL_TYPE_PLE; 225 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 226 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 227 FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i); 228 ret = dle_dfi_ctrl(rtwdev, &ctrl); 229 if (ret) 230 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 231 else 232 rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i, 233 FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK, 234 ctrl.out_data)); 235 } 236 237 quota.dle_type = DLE_CTRL_TYPE_PLE; 238 quota.qtaid = 6; 239 ret = dle_dfi_quota(rtwdev, "a); 240 if (ret) 241 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 242 else 243 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 244 quota.rsv_pgnum, quota.use_pgnum); 245 246 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 247 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n", 248 FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val)); 249 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n", 250 FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val)); 251 252 dump_err_status_dispatcher(rtwdev); 253 } 254 255 static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 256 enum mac_ax_err_info err) 257 { 258 u32 dbg, event; 259 260 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 261 event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg); 262 263 switch (event) { 264 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 265 rtw89_info(rtwdev, "quota lost!\n"); 266 rtw89_mac_dump_qta_lost(rtwdev); 267 break; 268 default: 269 break; 270 } 271 } 272 273 static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev, 274 enum mac_ax_err_info err) 275 { 276 u32 dmac_err, cmac_err; 277 278 if (err != MAC_AX_ERR_L1_ERR_DMAC && 279 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 280 err != MAC_AX_ERR_L0_ERR_CMAC0 && 281 err != MAC_AX_ERR_L0_ERR_CMAC1) 282 return; 283 284 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 285 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 286 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 287 288 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR); 289 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR =0x%08x\n", cmac_err); 290 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 291 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR =0x%08x\n", dmac_err); 292 293 if (dmac_err) { 294 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG =0x%08x ", 295 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG)); 296 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG =0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG)); 298 } 299 300 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 301 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR =0x%08x ", 302 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 303 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR =0x%08x\n", 304 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 305 } 306 307 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 308 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR =0x%08x\n", 309 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 310 rtw89_info(rtwdev, "SEC_local_Register 0x9D00 =0x%08x\n", 311 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 312 rtw89_info(rtwdev, "SEC_local_Register 0x9D04 =0x%08x\n", 313 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 314 rtw89_info(rtwdev, "SEC_local_Register 0x9D10 =0x%08x\n", 315 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 316 rtw89_info(rtwdev, "SEC_local_Register 0x9D14 =0x%08x\n", 317 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 318 rtw89_info(rtwdev, "SEC_local_Register 0x9D18 =0x%08x\n", 319 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 320 rtw89_info(rtwdev, "SEC_local_Register 0x9D20 =0x%08x\n", 321 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 322 rtw89_info(rtwdev, "SEC_local_Register 0x9D24 =0x%08x\n", 323 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 324 rtw89_info(rtwdev, "SEC_local_Register 0x9D28 =0x%08x\n", 325 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 326 rtw89_info(rtwdev, "SEC_local_Register 0x9D2C =0x%08x\n", 327 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 328 } 329 330 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 331 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR =0x%08x ", 332 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 333 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR =0x%08x\n", 334 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 335 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR =0x%08x ", 336 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 337 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR =0x%08x\n", 338 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 339 } 340 341 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 342 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR =0x%08x ", 343 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 344 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR= 0x%08x\n", 345 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 346 } 347 348 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 349 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ", 350 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 351 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 352 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 353 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ", 354 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 355 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 356 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 357 dump_err_status_dispatcher(rtwdev); 358 } 359 360 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 361 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 362 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 363 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 364 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 365 } 366 367 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 368 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ", 369 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 370 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 371 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 372 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ", 373 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 374 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 375 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 376 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 377 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 378 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 379 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 380 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 381 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 382 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 383 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 384 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 385 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 386 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 387 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 388 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 389 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 390 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 391 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 392 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 393 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 394 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 395 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 396 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 397 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 398 dump_err_status_dispatcher(rtwdev); 399 } 400 401 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 402 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ", 403 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 404 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n", 405 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 406 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ", 407 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 408 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n", 409 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 410 } 411 412 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) 413 dump_err_status_dispatcher(rtwdev); 414 415 if (dmac_err & B_AX_DLE_CPUIO_ERR_FLAG) { 416 rtw89_info(rtwdev, "R_AX_CPUIO_ERR_IMR=0x%08x ", 417 rtw89_read32(rtwdev, R_AX_CPUIO_ERR_IMR)); 418 rtw89_info(rtwdev, "R_AX_CPUIO_ERR_ISR=0x%08x\n", 419 rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR)); 420 } 421 422 if (dmac_err & BIT(11)) { 423 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 424 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 425 } 426 427 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 428 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR=0x%08x ", 429 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR)); 430 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR=0x%04x\n", 431 rtw89_read16(rtwdev, R_AX_SCHEDULE_ERR_ISR)); 432 } 433 434 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 435 rtw89_info(rtwdev, "R_AX_PTCL_IMR0=0x%08x ", 436 rtw89_read32(rtwdev, R_AX_PTCL_IMR0)); 437 rtw89_info(rtwdev, "R_AX_PTCL_ISR0=0x%08x\n", 438 rtw89_read32(rtwdev, R_AX_PTCL_ISR0)); 439 } 440 441 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 442 rtw89_info(rtwdev, "R_AX_DLE_CTRL=0x%08x\n", 443 rtw89_read32(rtwdev, R_AX_DLE_CTRL)); 444 } 445 446 if (cmac_err & B_AX_PHYINTF_ERR_IND) { 447 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR=0x%08x\n", 448 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR)); 449 } 450 451 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 452 rtw89_info(rtwdev, "R_AX_TXPWR_IMR=0x%08x ", 453 rtw89_read32(rtwdev, R_AX_TXPWR_IMR)); 454 rtw89_info(rtwdev, "R_AX_TXPWR_ISR=0x%08x\n", 455 rtw89_read32(rtwdev, R_AX_TXPWR_ISR)); 456 } 457 458 if (cmac_err & B_AX_WMAC_RX_ERR_IND) { 459 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x ", 460 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL)); 461 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR=0x%08x\n", 462 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR)); 463 } 464 465 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 466 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR=0x%08x ", 467 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR)); 468 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x\n", 469 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL)); 470 } 471 472 rtwdev->hci.ops->dump_err_status(rtwdev); 473 474 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 475 rtw89_mac_dump_l0_to_l1(rtwdev, err); 476 477 rtw89_info(rtwdev, "<---\n"); 478 } 479 480 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 481 { 482 u32 err, err_scnr; 483 int ret; 484 485 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 486 false, rtwdev, R_AX_HALT_C2H_CTRL); 487 if (ret) { 488 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 489 return ret; 490 } 491 492 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 493 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 494 495 err_scnr = RTW89_ERROR_SCENARIO(err); 496 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 497 err = MAC_AX_ERR_CPU_EXCEPTION; 498 else if (err_scnr == RTW89_WCPU_ASSERTION) 499 err = MAC_AX_ERR_ASSERTION; 500 501 rtw89_fw_st_dbg_dump(rtwdev); 502 rtw89_mac_dump_err_status(rtwdev, err); 503 504 return err; 505 } 506 EXPORT_SYMBOL(rtw89_mac_get_err_status); 507 508 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 509 { 510 u32 halt; 511 int ret = 0; 512 513 if (err > MAC_AX_SET_ERR_MAX) { 514 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 515 return -EINVAL; 516 } 517 518 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 519 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 520 if (ret) { 521 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 522 return -EFAULT; 523 } 524 525 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 526 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 527 528 return 0; 529 } 530 EXPORT_SYMBOL(rtw89_mac_set_err_status); 531 532 static int hfc_reset_param(struct rtw89_dev *rtwdev) 533 { 534 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 535 struct rtw89_hfc_param_ini param_ini = {NULL}; 536 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 537 538 switch (rtwdev->hci.type) { 539 case RTW89_HCI_TYPE_PCIE: 540 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 541 param->en = 0; 542 break; 543 default: 544 return -EINVAL; 545 } 546 547 if (param_ini.pub_cfg) 548 param->pub_cfg = *param_ini.pub_cfg; 549 550 if (param_ini.prec_cfg) { 551 param->prec_cfg = *param_ini.prec_cfg; 552 rtwdev->hal.sw_amsdu_max_size = 553 param->prec_cfg.wp_ch07_prec * HFC_PAGE_UNIT; 554 } 555 556 if (param_ini.ch_cfg) 557 param->ch_cfg = param_ini.ch_cfg; 558 559 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 560 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 561 param->mode = param_ini.mode; 562 563 return 0; 564 } 565 566 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 567 { 568 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 569 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 570 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 571 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 572 573 if (ch >= RTW89_DMA_CH_NUM) 574 return -EINVAL; 575 576 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 577 ch_cfg[ch].max > pub_cfg->pub_max) 578 return -EINVAL; 579 if (ch_cfg[ch].grp >= grp_num) 580 return -EINVAL; 581 582 return 0; 583 } 584 585 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 586 { 587 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 588 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 589 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 590 591 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 592 if (rtwdev->chip->chip_id == RTL8852A) 593 return 0; 594 else 595 return -EFAULT; 596 } 597 598 return 0; 599 } 600 601 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 602 { 603 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 604 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 605 606 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 607 return -EFAULT; 608 609 return 0; 610 } 611 612 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 613 { 614 const struct rtw89_chip_info *chip = rtwdev->chip; 615 const struct rtw89_page_regs *regs = chip->page_regs; 616 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 617 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 618 int ret = 0; 619 u32 val = 0; 620 621 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 622 if (ret) 623 return ret; 624 625 ret = hfc_ch_cfg_chk(rtwdev, ch); 626 if (ret) 627 return ret; 628 629 if (ch > RTW89_DMA_B1HI) 630 return -EINVAL; 631 632 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 633 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 634 (cfg[ch].grp ? B_AX_GRP : 0); 635 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 636 637 return 0; 638 } 639 640 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 641 { 642 const struct rtw89_chip_info *chip = rtwdev->chip; 643 const struct rtw89_page_regs *regs = chip->page_regs; 644 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 645 struct rtw89_hfc_ch_info *info = param->ch_info; 646 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 647 u32 val; 648 u32 ret; 649 650 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 651 if (ret) 652 return ret; 653 654 if (ch > RTW89_DMA_H2C) 655 return -EINVAL; 656 657 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 658 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 659 if (ch < RTW89_DMA_H2C) 660 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 661 else 662 info[ch].used = cfg[ch].min - info[ch].aval; 663 664 return 0; 665 } 666 667 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 668 { 669 const struct rtw89_chip_info *chip = rtwdev->chip; 670 const struct rtw89_page_regs *regs = chip->page_regs; 671 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 672 u32 val; 673 int ret; 674 675 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 676 if (ret) 677 return ret; 678 679 ret = hfc_pub_cfg_chk(rtwdev); 680 if (ret) 681 return ret; 682 683 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 684 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 685 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 686 687 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 688 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 689 690 return 0; 691 } 692 693 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 694 { 695 const struct rtw89_chip_info *chip = rtwdev->chip; 696 const struct rtw89_page_regs *regs = chip->page_regs; 697 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 698 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 699 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 700 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 701 u32 val; 702 int ret; 703 704 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 705 if (ret) 706 return ret; 707 708 val = rtw89_read32(rtwdev, regs->pub_page_info1); 709 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 710 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 711 val = rtw89_read32(rtwdev, regs->pub_page_info3); 712 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 713 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 714 info->pub_aval = 715 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 716 B_AX_PUB_AVAL_PG_MASK); 717 info->wp_aval = 718 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 719 B_AX_WP_AVAL_PG_MASK); 720 721 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 722 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 723 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 724 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 725 prec_cfg->ch011_full_cond = 726 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 727 prec_cfg->h2c_full_cond = 728 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 729 prec_cfg->wp_ch07_full_cond = 730 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 731 prec_cfg->wp_ch811_full_cond = 732 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 733 734 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 735 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 736 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 737 738 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 739 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 740 741 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 742 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 743 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 744 745 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 746 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 747 748 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 749 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 750 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 751 752 ret = hfc_pub_info_chk(rtwdev); 753 if (param->en && ret) 754 return ret; 755 756 return 0; 757 } 758 759 static void hfc_h2c_cfg(struct rtw89_dev *rtwdev) 760 { 761 const struct rtw89_chip_info *chip = rtwdev->chip; 762 const struct rtw89_page_regs *regs = chip->page_regs; 763 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 764 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 765 u32 val; 766 767 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 768 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 769 770 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 771 B_AX_HCI_FC_CH12_FULL_COND_MASK, 772 prec_cfg->h2c_full_cond); 773 } 774 775 static void hfc_mix_cfg(struct rtw89_dev *rtwdev) 776 { 777 const struct rtw89_chip_info *chip = rtwdev->chip; 778 const struct rtw89_page_regs *regs = chip->page_regs; 779 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 780 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 781 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 782 u32 val; 783 784 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 785 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 786 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 787 788 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 789 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 790 791 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 792 B_AX_PREC_PAGE_WP_CH07_MASK) | 793 u32_encode_bits(prec_cfg->wp_ch811_prec, 794 B_AX_PREC_PAGE_WP_CH811_MASK); 795 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 796 797 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 798 param->mode, B_AX_HCI_FC_MODE_MASK); 799 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 800 B_AX_HCI_FC_WD_FULL_COND_MASK); 801 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 802 B_AX_HCI_FC_CH12_FULL_COND_MASK); 803 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 804 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 805 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 806 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 807 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 808 } 809 810 static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 811 { 812 const struct rtw89_chip_info *chip = rtwdev->chip; 813 const struct rtw89_page_regs *regs = chip->page_regs; 814 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 815 u32 val; 816 817 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 818 param->en = en; 819 param->h2c_en = h2c_en; 820 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 821 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 822 (val & ~B_AX_HCI_FC_CH12_EN); 823 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 824 } 825 826 static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 827 { 828 u8 ch; 829 u32 ret = 0; 830 831 if (reset) 832 ret = hfc_reset_param(rtwdev); 833 if (ret) 834 return ret; 835 836 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 837 if (ret) 838 return ret; 839 840 hfc_func_en(rtwdev, false, false); 841 842 if (!en && h2c_en) { 843 hfc_h2c_cfg(rtwdev); 844 hfc_func_en(rtwdev, en, h2c_en); 845 return ret; 846 } 847 848 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 849 ret = hfc_ch_ctrl(rtwdev, ch); 850 if (ret) 851 return ret; 852 } 853 854 ret = hfc_pub_ctrl(rtwdev); 855 if (ret) 856 return ret; 857 858 hfc_mix_cfg(rtwdev); 859 if (en || h2c_en) { 860 hfc_func_en(rtwdev, en, h2c_en); 861 udelay(10); 862 } 863 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 864 ret = hfc_upd_ch_info(rtwdev, ch); 865 if (ret) 866 return ret; 867 } 868 ret = hfc_upd_mix_info(rtwdev); 869 870 return ret; 871 } 872 873 #define PWR_POLL_CNT 2000 874 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 875 const struct rtw89_pwr_cfg *cfg) 876 { 877 u8 val = 0; 878 int ret; 879 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 880 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 881 882 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 883 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 884 885 if (!ret) 886 return 0; 887 888 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 889 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 890 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 891 892 return -EBUSY; 893 } 894 895 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 896 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 897 { 898 const struct rtw89_pwr_cfg *cur_cfg; 899 u32 addr; 900 u8 val; 901 902 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 903 if (!(cur_cfg->intf_msk & intf_msk) || 904 !(cur_cfg->cv_msk & cv_msk)) 905 continue; 906 907 switch (cur_cfg->cmd) { 908 case PWR_CMD_WRITE: 909 addr = cur_cfg->addr; 910 911 if (cur_cfg->base == PWR_BASE_SDIO) 912 addr |= SDIO_LOCAL_BASE_ADDR; 913 914 val = rtw89_read8(rtwdev, addr); 915 val &= ~(cur_cfg->msk); 916 val |= (cur_cfg->val & cur_cfg->msk); 917 918 rtw89_write8(rtwdev, addr, val); 919 break; 920 case PWR_CMD_POLL: 921 if (pwr_cmd_poll(rtwdev, cur_cfg)) 922 return -EBUSY; 923 break; 924 case PWR_CMD_DELAY: 925 if (cur_cfg->val == PWR_DELAY_US) 926 udelay(cur_cfg->addr); 927 else 928 fsleep(cur_cfg->addr * 1000); 929 break; 930 default: 931 return -EINVAL; 932 } 933 } 934 935 return 0; 936 } 937 938 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 939 const struct rtw89_pwr_cfg * const *cfg_seq) 940 { 941 int ret; 942 943 for (; *cfg_seq; cfg_seq++) { 944 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 945 PWR_INTF_MSK_PCIE, *cfg_seq); 946 if (ret) 947 return -EBUSY; 948 } 949 950 return 0; 951 } 952 953 static enum rtw89_rpwm_req_pwr_state 954 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 955 { 956 enum rtw89_rpwm_req_pwr_state state; 957 958 switch (rtwdev->ps_mode) { 959 case RTW89_PS_MODE_RFOFF: 960 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 961 break; 962 case RTW89_PS_MODE_CLK_GATED: 963 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 964 break; 965 case RTW89_PS_MODE_PWR_GATED: 966 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 967 break; 968 default: 969 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 970 break; 971 } 972 return state; 973 } 974 975 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 976 enum rtw89_rpwm_req_pwr_state req_pwr_state, 977 bool notify_wake) 978 { 979 u16 request; 980 981 spin_lock_bh(&rtwdev->rpwm_lock); 982 983 request = rtw89_read16(rtwdev, R_AX_RPWM); 984 request ^= request | PS_RPWM_TOGGLE; 985 request |= req_pwr_state; 986 987 if (notify_wake) { 988 request |= PS_RPWM_NOTIFY_WAKE; 989 } else { 990 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 991 RPWM_SEQ_NUM_MAX; 992 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 993 rtwdev->mac.rpwm_seq_num); 994 995 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 996 request |= PS_RPWM_ACK; 997 } 998 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 999 1000 spin_unlock_bh(&rtwdev->rpwm_lock); 1001 } 1002 1003 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1004 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1005 { 1006 bool request_deep_mode; 1007 bool in_deep_mode; 1008 u8 rpwm_req_num; 1009 u8 cpwm_rsp_seq; 1010 u8 cpwm_seq; 1011 u8 cpwm_status; 1012 1013 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1014 request_deep_mode = true; 1015 else 1016 request_deep_mode = false; 1017 1018 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1019 in_deep_mode = true; 1020 else 1021 in_deep_mode = false; 1022 1023 if (request_deep_mode != in_deep_mode) 1024 return -EPERM; 1025 1026 if (request_deep_mode) 1027 return 0; 1028 1029 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1030 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1031 PS_CPWM_RSP_SEQ_NUM); 1032 1033 if (rpwm_req_num != cpwm_rsp_seq) 1034 return -EPERM; 1035 1036 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1037 CPWM_SEQ_NUM_MAX; 1038 1039 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1040 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1041 return -EPERM; 1042 1043 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1044 if (cpwm_status != req_pwr_state) 1045 return -EPERM; 1046 1047 return 0; 1048 } 1049 1050 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1051 { 1052 enum rtw89_rpwm_req_pwr_state state; 1053 int ret; 1054 1055 if (enter) 1056 state = rtw89_mac_get_req_pwr_state(rtwdev); 1057 else 1058 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1059 1060 rtw89_mac_send_rpwm(rtwdev, state, false); 1061 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, !ret, 1062 1000, 15000, false, rtwdev, state); 1063 if (ret) 1064 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1065 enter ? "entering" : "leaving"); 1066 } 1067 1068 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1069 { 1070 enum rtw89_rpwm_req_pwr_state state; 1071 1072 state = rtw89_mac_get_req_pwr_state(rtwdev); 1073 rtw89_mac_send_rpwm(rtwdev, state, true); 1074 } 1075 1076 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1077 { 1078 #define PWR_ACT 1 1079 const struct rtw89_chip_info *chip = rtwdev->chip; 1080 const struct rtw89_pwr_cfg * const *cfg_seq; 1081 int (*cfg_func)(struct rtw89_dev *rtwdev); 1082 struct rtw89_hal *hal = &rtwdev->hal; 1083 int ret; 1084 u8 val; 1085 1086 if (on) { 1087 cfg_seq = chip->pwr_on_seq; 1088 cfg_func = chip->ops->pwr_on_func; 1089 } else { 1090 cfg_seq = chip->pwr_off_seq; 1091 cfg_func = chip->ops->pwr_off_func; 1092 } 1093 1094 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1095 __rtw89_leave_ps_mode(rtwdev); 1096 1097 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1098 if (on && val == PWR_ACT) { 1099 rtw89_err(rtwdev, "MAC has already powered on\n"); 1100 return -EBUSY; 1101 } 1102 1103 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1104 if (ret) 1105 return ret; 1106 1107 if (on) { 1108 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1109 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1110 } else { 1111 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1112 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1113 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1114 hal->current_channel = 0; 1115 } 1116 1117 return 0; 1118 #undef PWR_ACT 1119 } 1120 1121 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1122 { 1123 rtw89_mac_power_switch(rtwdev, false); 1124 } 1125 1126 static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1127 { 1128 u32 func_en = 0; 1129 u32 ck_en = 0; 1130 u32 c1pc_en = 0; 1131 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1132 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1133 1134 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1135 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1136 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1137 B_AX_CMAC_CRPRT; 1138 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1139 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1140 B_AX_RMAC_CKEN; 1141 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1142 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1143 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1144 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1145 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1146 1147 if (en) { 1148 if (mac_idx == RTW89_MAC_1) { 1149 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1150 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1151 B_AX_R_SYM_ISO_CMAC12PP); 1152 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1153 B_AX_CMAC1_FEN); 1154 } 1155 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1156 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1157 } else { 1158 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1159 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1160 if (mac_idx == RTW89_MAC_1) { 1161 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1162 B_AX_CMAC1_FEN); 1163 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1164 B_AX_R_SYM_ISO_CMAC12PP); 1165 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1166 } 1167 } 1168 1169 return 0; 1170 } 1171 1172 static int dmac_func_en(struct rtw89_dev *rtwdev) 1173 { 1174 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1175 u32 val32; 1176 1177 if (chip_id == RTL8852C) 1178 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1179 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1180 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1181 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1182 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1183 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1184 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1185 else 1186 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1187 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1188 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1189 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1190 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1191 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1192 B_AX_DMAC_CRPRT); 1193 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1194 1195 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1196 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1197 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1198 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1199 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1200 1201 return 0; 1202 } 1203 1204 static int chip_func_en(struct rtw89_dev *rtwdev) 1205 { 1206 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1207 1208 if (chip_id == RTL8852A) 1209 rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL0, 1210 B_AX_OCP_L1_MASK); 1211 1212 return 0; 1213 } 1214 1215 static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev) 1216 { 1217 int ret; 1218 1219 ret = dmac_func_en(rtwdev); 1220 if (ret) 1221 return ret; 1222 1223 ret = cmac_func_en(rtwdev, 0, true); 1224 if (ret) 1225 return ret; 1226 1227 ret = chip_func_en(rtwdev); 1228 if (ret) 1229 return ret; 1230 1231 return ret; 1232 } 1233 1234 const struct rtw89_mac_size_set rtw89_mac_size = { 1235 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1236 /* PCIE 64 */ 1237 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1238 /* DLFW */ 1239 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1240 /* 8852C DLFW */ 1241 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1242 /* 8852C PCIE SCC */ 1243 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1244 /* PCIE */ 1245 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1246 /* DLFW */ 1247 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1248 /* 8852C DLFW */ 1249 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1250 /* 8852C PCIE SCC */ 1251 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1252 /* PCIE 64 */ 1253 .wde_qt0 = {3792, 196, 0, 107,}, 1254 /* DLFW */ 1255 .wde_qt4 = {0, 0, 0, 0,}, 1256 /* 8852C DLFW */ 1257 .wde_qt17 = {0, 0, 0, 0,}, 1258 /* 8852C PCIE SCC */ 1259 .wde_qt18 = {3228, 60, 0, 40,}, 1260 /* PCIE SCC */ 1261 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1262 /* PCIE SCC */ 1263 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1264 /* DLFW */ 1265 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1266 /* DLFW 52C */ 1267 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1268 /* DLFW 52C */ 1269 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1270 /* 8852C PCIE SCC */ 1271 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1272 /* 8852C PCIE SCC */ 1273 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1274 }; 1275 EXPORT_SYMBOL(rtw89_mac_size); 1276 1277 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1278 enum rtw89_qta_mode mode) 1279 { 1280 struct rtw89_mac_info *mac = &rtwdev->mac; 1281 const struct rtw89_dle_mem *cfg; 1282 1283 cfg = &rtwdev->chip->dle_mem[mode]; 1284 if (!cfg) 1285 return NULL; 1286 1287 if (cfg->mode != mode) { 1288 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1289 return NULL; 1290 } 1291 1292 mac->dle_info.wde_pg_size = cfg->wde_size->pge_size; 1293 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1294 mac->dle_info.qta_mode = mode; 1295 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1296 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1297 1298 return cfg; 1299 } 1300 1301 static inline u32 dle_used_size(const struct rtw89_dle_size *wde, 1302 const struct rtw89_dle_size *ple) 1303 { 1304 return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1305 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1306 } 1307 1308 static void dle_func_en(struct rtw89_dev *rtwdev, bool enable) 1309 { 1310 if (enable) 1311 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1312 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1313 else 1314 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1315 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1316 } 1317 1318 static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable) 1319 { 1320 if (enable) 1321 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, 1322 B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); 1323 else 1324 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, 1325 B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); 1326 } 1327 1328 static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1329 { 1330 const struct rtw89_dle_size *size_cfg; 1331 u32 val; 1332 u8 bound = 0; 1333 1334 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1335 size_cfg = cfg->wde_size; 1336 1337 switch (size_cfg->pge_size) { 1338 default: 1339 case RTW89_WDE_PG_64: 1340 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1341 B_AX_WDE_PAGE_SEL_MASK); 1342 break; 1343 case RTW89_WDE_PG_128: 1344 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1345 B_AX_WDE_PAGE_SEL_MASK); 1346 break; 1347 case RTW89_WDE_PG_256: 1348 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1349 return -EINVAL; 1350 } 1351 1352 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1353 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1354 B_AX_WDE_FREE_PAGE_NUM_MASK); 1355 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1356 1357 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1358 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1359 * size_cfg->pge_size / DLE_BOUND_UNIT; 1360 size_cfg = cfg->ple_size; 1361 1362 switch (size_cfg->pge_size) { 1363 default: 1364 case RTW89_PLE_PG_64: 1365 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1366 return -EINVAL; 1367 case RTW89_PLE_PG_128: 1368 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1369 B_AX_PLE_PAGE_SEL_MASK); 1370 break; 1371 case RTW89_PLE_PG_256: 1372 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1373 B_AX_PLE_PAGE_SEL_MASK); 1374 break; 1375 } 1376 1377 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1378 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1379 B_AX_PLE_FREE_PAGE_NUM_MASK); 1380 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1381 1382 return 0; 1383 } 1384 1385 #define INVALID_QT_WCPU U16_MAX 1386 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1387 do { \ 1388 val = ((_min_x) & \ 1389 B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1390 (((_max_x) << 16) & \ 1391 B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1392 rtw89_write32(rtwdev, \ 1393 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1394 val); \ 1395 } while (0) 1396 #define SET_QUOTA(_x, _module, _idx) \ 1397 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1398 1399 static void wde_quota_cfg(struct rtw89_dev *rtwdev, 1400 const struct rtw89_wde_quota *min_cfg, 1401 const struct rtw89_wde_quota *max_cfg, 1402 u16 ext_wde_min_qt_wcpu) 1403 { 1404 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1405 ext_wde_min_qt_wcpu : min_cfg->wcpu; 1406 u32 val; 1407 1408 SET_QUOTA(hif, WDE, 0); 1409 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1410 SET_QUOTA(pkt_in, WDE, 3); 1411 SET_QUOTA(cpu_io, WDE, 4); 1412 } 1413 1414 static void ple_quota_cfg(struct rtw89_dev *rtwdev, 1415 const struct rtw89_ple_quota *min_cfg, 1416 const struct rtw89_ple_quota *max_cfg) 1417 { 1418 u32 val; 1419 1420 SET_QUOTA(cma0_tx, PLE, 0); 1421 SET_QUOTA(cma1_tx, PLE, 1); 1422 SET_QUOTA(c2h, PLE, 2); 1423 SET_QUOTA(h2c, PLE, 3); 1424 SET_QUOTA(wcpu, PLE, 4); 1425 SET_QUOTA(mpdu_proc, PLE, 5); 1426 SET_QUOTA(cma0_dma, PLE, 6); 1427 SET_QUOTA(cma1_dma, PLE, 7); 1428 SET_QUOTA(bb_rpt, PLE, 8); 1429 SET_QUOTA(wd_rel, PLE, 9); 1430 SET_QUOTA(cpu_io, PLE, 10); 1431 if (rtwdev->chip->chip_id == RTL8852C) 1432 SET_QUOTA(tx_rpt, PLE, 11); 1433 } 1434 1435 #undef SET_QUOTA 1436 1437 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 1438 const struct rtw89_dle_mem *cfg, 1439 u16 ext_wde_min_qt_wcpu) 1440 { 1441 wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 1442 ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 1443 } 1444 1445 static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1446 enum rtw89_qta_mode ext_mode) 1447 { 1448 const struct rtw89_dle_mem *cfg, *ext_cfg; 1449 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 1450 int ret = 0; 1451 u32 ini; 1452 1453 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1454 if (ret) 1455 return ret; 1456 1457 cfg = get_dle_mem_cfg(rtwdev, mode); 1458 if (!cfg) { 1459 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1460 ret = -EINVAL; 1461 goto error; 1462 } 1463 1464 if (mode == RTW89_QTA_DLFW) { 1465 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 1466 if (!ext_cfg) { 1467 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 1468 ext_mode); 1469 ret = -EINVAL; 1470 goto error; 1471 } 1472 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 1473 } 1474 1475 if (dle_used_size(cfg->wde_size, cfg->ple_size) != rtwdev->chip->fifo_size) { 1476 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 1477 ret = -EINVAL; 1478 goto error; 1479 } 1480 1481 dle_func_en(rtwdev, false); 1482 dle_clk_en(rtwdev, true); 1483 1484 ret = dle_mix_cfg(rtwdev, cfg); 1485 if (ret) { 1486 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 1487 goto error; 1488 } 1489 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 1490 1491 dle_func_en(rtwdev, true); 1492 1493 ret = read_poll_timeout(rtw89_read32, ini, 1494 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1495 2000, false, rtwdev, R_AX_WDE_INI_STATUS); 1496 if (ret) { 1497 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 1498 return ret; 1499 } 1500 1501 ret = read_poll_timeout(rtw89_read32, ini, 1502 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1503 2000, false, rtwdev, R_AX_PLE_INI_STATUS); 1504 if (ret) { 1505 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 1506 return ret; 1507 } 1508 1509 return 0; 1510 error: 1511 dle_func_en(rtwdev, false); 1512 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 1513 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 1514 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 1515 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 1516 1517 return ret; 1518 } 1519 1520 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1521 enum rtw89_qta_mode mode) 1522 { 1523 u32 reg, max_preld_size, min_rsvd_size; 1524 1525 max_preld_size = (mac_idx == RTW89_MAC_0 ? 1526 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 1527 reg = mac_idx == RTW89_MAC_0 ? 1528 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 1529 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 1530 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 1531 1532 min_rsvd_size = PRELD_AMSDU_SIZE; 1533 reg = mac_idx == RTW89_MAC_0 ? 1534 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 1535 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 1536 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 1537 1538 return 0; 1539 } 1540 1541 static bool is_qta_poh(struct rtw89_dev *rtwdev) 1542 { 1543 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 1544 } 1545 1546 static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1547 enum rtw89_qta_mode mode) 1548 { 1549 const struct rtw89_chip_info *chip = rtwdev->chip; 1550 1551 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || !is_qta_poh(rtwdev)) 1552 return 0; 1553 1554 return preload_init_set(rtwdev, mac_idx, mode); 1555 } 1556 1557 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 1558 { 1559 u32 msk32; 1560 u32 val32; 1561 1562 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 1563 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 1564 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 1565 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1566 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 1567 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 1568 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 1569 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 1570 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1571 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 1572 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1573 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1574 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 1575 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1576 1577 if ((val32 & msk32) == msk32) 1578 return true; 1579 1580 return false; 1581 } 1582 1583 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 1584 { 1585 const struct rtw89_chip_info *chip = rtwdev->chip; 1586 1587 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) 1588 return; 1589 1590 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 1591 SS2F_PATH_WLCPU); 1592 } 1593 1594 static int sta_sch_init(struct rtw89_dev *rtwdev) 1595 { 1596 u32 p_val; 1597 u8 val; 1598 int ret; 1599 1600 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1601 if (ret) 1602 return ret; 1603 1604 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 1605 val |= B_AX_SS_EN; 1606 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 1607 1608 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 1609 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 1610 if (ret) { 1611 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 1612 return ret; 1613 } 1614 1615 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 1616 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 1617 1618 _patch_ss2f_path(rtwdev); 1619 1620 return 0; 1621 } 1622 1623 static int mpdu_proc_init(struct rtw89_dev *rtwdev) 1624 { 1625 int ret; 1626 1627 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1628 if (ret) 1629 return ret; 1630 1631 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 1632 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 1633 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 1634 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 1635 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 1636 1637 return 0; 1638 } 1639 1640 static int sec_eng_init(struct rtw89_dev *rtwdev) 1641 { 1642 const struct rtw89_chip_info *chip = rtwdev->chip; 1643 u32 val = 0; 1644 int ret; 1645 1646 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1647 if (ret) 1648 return ret; 1649 1650 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 1651 /* init clock */ 1652 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 1653 /* init TX encryption */ 1654 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 1655 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 1656 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) 1657 val &= ~B_AX_TX_PARTIAL_MODE; 1658 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 1659 1660 /* init MIC ICV append */ 1661 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 1662 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 1663 1664 /* option init */ 1665 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 1666 1667 if (chip->chip_id == RTL8852C) 1668 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 1669 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 1670 1671 return 0; 1672 } 1673 1674 static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1675 { 1676 int ret; 1677 1678 ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 1679 if (ret) { 1680 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 1681 return ret; 1682 } 1683 1684 ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 1685 if (ret) { 1686 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 1687 return ret; 1688 } 1689 1690 ret = hfc_init(rtwdev, true, true, true); 1691 if (ret) { 1692 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 1693 return ret; 1694 } 1695 1696 ret = sta_sch_init(rtwdev); 1697 if (ret) { 1698 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 1699 return ret; 1700 } 1701 1702 ret = mpdu_proc_init(rtwdev); 1703 if (ret) { 1704 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 1705 return ret; 1706 } 1707 1708 ret = sec_eng_init(rtwdev); 1709 if (ret) { 1710 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 1711 return ret; 1712 } 1713 1714 return ret; 1715 } 1716 1717 static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1718 { 1719 u32 val, reg; 1720 u16 p_val; 1721 int ret; 1722 1723 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1724 if (ret) 1725 return ret; 1726 1727 reg = rtw89_mac_reg_by_idx(R_AX_ADDR_CAM_CTRL, mac_idx); 1728 1729 val = rtw89_read32(rtwdev, reg); 1730 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 1731 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 1732 rtw89_write32(rtwdev, reg, val); 1733 1734 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 1735 1, TRXCFG_WAIT_CNT, false, rtwdev, B_AX_ADDR_CAM_CLR); 1736 if (ret) { 1737 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 1738 return ret; 1739 } 1740 1741 return 0; 1742 } 1743 1744 static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1745 { 1746 u32 ret; 1747 u32 reg; 1748 1749 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1750 if (ret) 1751 return ret; 1752 1753 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_1, mac_idx); 1754 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, SIFS_MACTXEN_T1); 1755 1756 if (rtwdev->chip->chip_id == RTL8852B) { 1757 reg = rtw89_mac_reg_by_idx(R_AX_SCH_EXT_CTRL, mac_idx); 1758 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 1759 } 1760 1761 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CFG_0, mac_idx); 1762 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 1763 1764 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_0, mac_idx); 1765 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, SCH_PREBKF_24US); 1766 1767 return 0; 1768 } 1769 1770 static int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, 1771 enum rtw89_machdr_frame_type type, 1772 enum rtw89_mac_fwd_target fwd_target, 1773 u8 mac_idx) 1774 { 1775 u32 reg; 1776 u32 val; 1777 1778 switch (fwd_target) { 1779 case RTW89_FWD_DONT_CARE: 1780 val = RX_FLTR_FRAME_DROP; 1781 break; 1782 case RTW89_FWD_TO_HOST: 1783 val = RX_FLTR_FRAME_TO_HOST; 1784 break; 1785 case RTW89_FWD_TO_WLAN_CPU: 1786 val = RX_FLTR_FRAME_TO_WLCPU; 1787 break; 1788 default: 1789 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 1790 return -EINVAL; 1791 } 1792 1793 switch (type) { 1794 case RTW89_MGNT: 1795 reg = rtw89_mac_reg_by_idx(R_AX_MGNT_FLTR, mac_idx); 1796 break; 1797 case RTW89_CTRL: 1798 reg = rtw89_mac_reg_by_idx(R_AX_CTRL_FLTR, mac_idx); 1799 break; 1800 case RTW89_DATA: 1801 reg = rtw89_mac_reg_by_idx(R_AX_DATA_FLTR, mac_idx); 1802 break; 1803 default: 1804 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 1805 return -EINVAL; 1806 } 1807 rtw89_write32(rtwdev, reg, val); 1808 1809 return 0; 1810 } 1811 1812 static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1813 { 1814 int ret, i; 1815 u32 mac_ftlr, plcp_ftlr; 1816 1817 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1818 if (ret) 1819 return ret; 1820 1821 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 1822 ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST, 1823 mac_idx); 1824 if (ret) 1825 return ret; 1826 } 1827 mac_ftlr = rtwdev->hal.rx_fltr; 1828 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 1829 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 1830 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 1831 B_AX_HE_SIGB_CRC_CHK; 1832 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx), 1833 mac_ftlr); 1834 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx), 1835 plcp_ftlr); 1836 1837 return 0; 1838 } 1839 1840 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 1841 { 1842 u32 reg, val32; 1843 u32 b_rsp_chk_nav, b_rsp_chk_cca; 1844 1845 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 1846 B_AX_RSP_CHK_BASIC_NAV; 1847 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 1848 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 1849 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 1850 1851 switch (rtwdev->chip->chip_id) { 1852 case RTL8852A: 1853 case RTL8852B: 1854 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 1855 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 1856 rtw89_write32(rtwdev, reg, val32); 1857 1858 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 1859 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 1860 rtw89_write32(rtwdev, reg, val32); 1861 break; 1862 default: 1863 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 1864 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 1865 rtw89_write32(rtwdev, reg, val32); 1866 1867 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 1868 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 1869 rtw89_write32(rtwdev, reg, val32); 1870 break; 1871 } 1872 } 1873 1874 static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1875 { 1876 u32 val, reg; 1877 int ret; 1878 1879 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1880 if (ret) 1881 return ret; 1882 1883 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CONTROL, mac_idx); 1884 val = rtw89_read32(rtwdev, reg); 1885 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 1886 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 1887 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 1888 B_AX_CTN_CHK_INTRA_NAV | 1889 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 1890 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 1891 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 1892 B_AX_CTN_CHK_CCA_P20 | B_AX_SIFS_CHK_EDCCA); 1893 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 1894 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 1895 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 1896 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV); 1897 1898 rtw89_write32(rtwdev, reg, val); 1899 1900 _patch_dis_resp_chk(rtwdev, mac_idx); 1901 1902 return 0; 1903 } 1904 1905 static int nav_ctrl_init(struct rtw89_dev *rtwdev) 1906 { 1907 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 1908 B_AX_WMAC_TF_UP_NAV_EN | 1909 B_AX_WMAC_NAV_UPPER_EN); 1910 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_12MS); 1911 1912 return 0; 1913 } 1914 1915 static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1916 { 1917 u32 reg; 1918 int ret; 1919 1920 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1921 if (ret) 1922 return ret; 1923 reg = rtw89_mac_reg_by_idx(R_AX_RX_SR_CTRL, mac_idx); 1924 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 1925 1926 return 0; 1927 } 1928 1929 static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1930 { 1931 u32 reg; 1932 int ret; 1933 1934 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1935 if (ret) 1936 return ret; 1937 1938 reg = rtw89_mac_reg_by_idx(R_AX_MAC_LOOPBACK, mac_idx); 1939 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 1940 1941 reg = rtw89_mac_reg_by_idx(R_AX_TCR0, mac_idx); 1942 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 1943 1944 reg = rtw89_mac_reg_by_idx(R_AX_TXD_FIFO_CTRL, mac_idx); 1945 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 1946 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 1947 1948 return 0; 1949 } 1950 1951 static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1952 { 1953 u32 reg, val, sifs; 1954 int ret; 1955 1956 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1957 if (ret) 1958 return ret; 1959 1960 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 1961 val = rtw89_read32(rtwdev, reg); 1962 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 1963 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 1964 1965 switch (rtwdev->chip->chip_id) { 1966 case RTL8852A: 1967 sifs = WMAC_SPEC_SIFS_OFDM_52A; 1968 break; 1969 case RTL8852B: 1970 sifs = WMAC_SPEC_SIFS_OFDM_52B; 1971 break; 1972 default: 1973 sifs = WMAC_SPEC_SIFS_OFDM_52C; 1974 break; 1975 } 1976 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 1977 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 1978 rtw89_write32(rtwdev, reg, val); 1979 1980 reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx); 1981 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 1982 1983 return 0; 1984 } 1985 1986 static void rst_bacam(struct rtw89_dev *rtwdev) 1987 { 1988 u32 val32; 1989 int ret; 1990 1991 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 1992 S_AX_BACAM_RST_ALL); 1993 1994 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 1995 1, 1000, false, 1996 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 1997 if (ret) 1998 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 1999 } 2000 2001 static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2002 { 2003 #define TRXCFG_RMAC_CCA_TO 32 2004 #define TRXCFG_RMAC_DATA_TO 15 2005 #define RX_MAX_LEN_UNIT 512 2006 #define PLD_RLS_MAX_PG 127 2007 int ret; 2008 u32 reg, rx_max_len, rx_qta; 2009 u16 val; 2010 2011 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2012 if (ret) 2013 return ret; 2014 2015 if (mac_idx == RTW89_MAC_0) 2016 rst_bacam(rtwdev); 2017 2018 reg = rtw89_mac_reg_by_idx(R_AX_RESPBA_CAM_CTRL, mac_idx); 2019 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2020 2021 reg = rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx); 2022 val = rtw89_read16(rtwdev, reg); 2023 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2024 B_AX_RX_DLK_DATA_TIME_MASK); 2025 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2026 B_AX_RX_DLK_CCA_TIME_MASK); 2027 rtw89_write16(rtwdev, reg, val); 2028 2029 reg = rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx); 2030 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2031 2032 reg = rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx); 2033 if (mac_idx == RTW89_MAC_0) 2034 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2035 else 2036 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2037 rx_qta = rx_qta > PLD_RLS_MAX_PG ? PLD_RLS_MAX_PG : rx_qta; 2038 rx_max_len = (rx_qta - 1) * rtwdev->mac.dle_info.ple_pg_size / 2039 RX_MAX_LEN_UNIT; 2040 rx_max_len = rx_max_len > B_AX_RX_MPDU_MAX_LEN_SIZE ? 2041 B_AX_RX_MPDU_MAX_LEN_SIZE : rx_max_len; 2042 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2043 2044 if (rtwdev->chip->chip_id == RTL8852A && 2045 rtwdev->hal.cv == CHIP_CBV) { 2046 rtw89_write16_mask(rtwdev, 2047 rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx), 2048 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2049 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx), 2050 BIT(12)); 2051 } 2052 2053 reg = rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx); 2054 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2055 2056 return ret; 2057 } 2058 2059 static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2060 { 2061 u32 val, reg; 2062 int ret; 2063 2064 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2065 if (ret) 2066 return ret; 2067 2068 reg = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2069 val = rtw89_read32(rtwdev, reg); 2070 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2071 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2072 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2073 rtw89_write32(rtwdev, reg, val); 2074 2075 return 0; 2076 } 2077 2078 static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2079 { 2080 const struct rtw89_dle_mem *cfg; 2081 2082 cfg = get_dle_mem_cfg(rtwdev, mode); 2083 if (!cfg) { 2084 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2085 return false; 2086 } 2087 2088 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2089 } 2090 2091 static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2092 { 2093 u32 val, reg; 2094 int ret; 2095 2096 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2097 if (ret) 2098 return ret; 2099 2100 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2101 reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); 2102 val = rtw89_read32(rtwdev, reg); 2103 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2104 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2105 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2106 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2107 val |= B_AX_HW_CTS2SELF_EN; 2108 rtw89_write32(rtwdev, reg, val); 2109 2110 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_FSM_MON, mac_idx); 2111 val = rtw89_read32(rtwdev, reg); 2112 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2113 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2114 rtw89_write32(rtwdev, reg, val); 2115 } 2116 2117 if (mac_idx == RTW89_MAC_0) { 2118 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2119 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2120 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2121 B_AX_PTCL_TRIGGER_SS_EN_0 | 2122 B_AX_PTCL_TRIGGER_SS_EN_1 | 2123 B_AX_PTCL_TRIGGER_SS_EN_UL); 2124 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2125 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2126 } else if (mac_idx == RTW89_MAC_1) { 2127 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2128 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2129 } 2130 2131 return 0; 2132 } 2133 2134 static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2135 { 2136 int ret; 2137 2138 ret = scheduler_init(rtwdev, mac_idx); 2139 if (ret) { 2140 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2141 return ret; 2142 } 2143 2144 ret = addr_cam_init(rtwdev, mac_idx); 2145 if (ret) { 2146 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2147 ret); 2148 return ret; 2149 } 2150 2151 ret = rx_fltr_init(rtwdev, mac_idx); 2152 if (ret) { 2153 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2154 ret); 2155 return ret; 2156 } 2157 2158 ret = cca_ctrl_init(rtwdev, mac_idx); 2159 if (ret) { 2160 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2161 ret); 2162 return ret; 2163 } 2164 2165 ret = nav_ctrl_init(rtwdev); 2166 if (ret) { 2167 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2168 ret); 2169 return ret; 2170 } 2171 2172 ret = spatial_reuse_init(rtwdev, mac_idx); 2173 if (ret) { 2174 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2175 mac_idx, ret); 2176 return ret; 2177 } 2178 2179 ret = tmac_init(rtwdev, mac_idx); 2180 if (ret) { 2181 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2182 return ret; 2183 } 2184 2185 ret = trxptcl_init(rtwdev, mac_idx); 2186 if (ret) { 2187 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2188 return ret; 2189 } 2190 2191 ret = rmac_init(rtwdev, mac_idx); 2192 if (ret) { 2193 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2194 return ret; 2195 } 2196 2197 ret = cmac_com_init(rtwdev, mac_idx); 2198 if (ret) { 2199 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2200 return ret; 2201 } 2202 2203 ret = ptcl_init(rtwdev, mac_idx); 2204 if (ret) { 2205 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2206 return ret; 2207 } 2208 2209 return ret; 2210 } 2211 2212 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2213 struct rtw89_mac_c2h_info *c2h_info) 2214 { 2215 struct rtw89_mac_h2c_info h2c_info = {0}; 2216 u32 ret; 2217 2218 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2219 h2c_info.content_len = 0; 2220 2221 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2222 if (ret) 2223 return ret; 2224 2225 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2226 return -EINVAL; 2227 2228 return 0; 2229 } 2230 2231 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2232 { 2233 struct rtw89_hal *hal = &rtwdev->hal; 2234 const struct rtw89_chip_info *chip = rtwdev->chip; 2235 struct rtw89_mac_c2h_info c2h_info = {0}; 2236 struct rtw89_c2h_phy_cap *cap = 2237 (struct rtw89_c2h_phy_cap *)&c2h_info.c2hreg[0]; 2238 u32 ret; 2239 2240 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2241 if (ret) 2242 return ret; 2243 2244 hal->tx_nss = cap->tx_nss ? 2245 min_t(u8, cap->tx_nss, chip->tx_nss) : chip->tx_nss; 2246 hal->rx_nss = cap->rx_nss ? 2247 min_t(u8, cap->rx_nss, chip->rx_nss) : chip->rx_nss; 2248 2249 rtw89_debug(rtwdev, RTW89_DBG_FW, 2250 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2251 hal->tx_nss, cap->tx_nss, chip->tx_nss, 2252 hal->rx_nss, cap->rx_nss, chip->rx_nss); 2253 2254 return 0; 2255 } 2256 2257 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2258 u16 tx_en_u16, u16 mask_u16) 2259 { 2260 u32 ret; 2261 struct rtw89_mac_c2h_info c2h_info = {0}; 2262 struct rtw89_mac_h2c_info h2c_info = {0}; 2263 struct rtw89_h2creg_sch_tx_en *h2creg = 2264 (struct rtw89_h2creg_sch_tx_en *)h2c_info.h2creg; 2265 2266 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2267 h2c_info.content_len = sizeof(*h2creg) - RTW89_H2CREG_HDR_LEN; 2268 h2creg->tx_en = tx_en_u16; 2269 h2creg->mask = mask_u16; 2270 h2creg->band = band; 2271 2272 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2273 if (ret) 2274 return ret; 2275 2276 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2277 return -EINVAL; 2278 2279 return 0; 2280 } 2281 2282 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2283 u16 tx_en, u16 tx_en_mask) 2284 { 2285 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx); 2286 u16 val; 2287 int ret; 2288 2289 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2290 if (ret) 2291 return ret; 2292 2293 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 2294 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 2295 tx_en, tx_en_mask); 2296 2297 val = rtw89_read16(rtwdev, reg); 2298 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2299 rtw89_write16(rtwdev, reg, val); 2300 2301 return 0; 2302 } 2303 2304 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2305 u32 tx_en, u32 tx_en_mask) 2306 { 2307 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx); 2308 u32 val; 2309 int ret; 2310 2311 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2312 if (ret) 2313 return ret; 2314 2315 val = rtw89_read32(rtwdev, reg); 2316 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2317 rtw89_write32(rtwdev, reg, val); 2318 2319 return 0; 2320 } 2321 2322 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 2323 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2324 { 2325 int ret; 2326 2327 *tx_en = rtw89_read16(rtwdev, 2328 rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx)); 2329 2330 switch (sel) { 2331 case RTW89_SCH_TX_SEL_ALL: 2332 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2333 B_AX_CTN_TXEN_ALL_MASK); 2334 if (ret) 2335 return ret; 2336 break; 2337 case RTW89_SCH_TX_SEL_HIQ: 2338 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2339 0, B_AX_CTN_TXEN_HGQ); 2340 if (ret) 2341 return ret; 2342 break; 2343 case RTW89_SCH_TX_SEL_MG0: 2344 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2345 0, B_AX_CTN_TXEN_MGQ); 2346 if (ret) 2347 return ret; 2348 break; 2349 case RTW89_SCH_TX_SEL_MACID: 2350 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2351 B_AX_CTN_TXEN_ALL_MASK); 2352 if (ret) 2353 return ret; 2354 break; 2355 default: 2356 return 0; 2357 } 2358 2359 return 0; 2360 } 2361 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 2362 2363 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2364 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2365 { 2366 int ret; 2367 2368 *tx_en = rtw89_read32(rtwdev, 2369 rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx)); 2370 2371 switch (sel) { 2372 case RTW89_SCH_TX_SEL_ALL: 2373 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2374 B_AX_CTN_TXEN_ALL_MASK_V1); 2375 if (ret) 2376 return ret; 2377 break; 2378 case RTW89_SCH_TX_SEL_HIQ: 2379 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2380 0, B_AX_CTN_TXEN_HGQ); 2381 if (ret) 2382 return ret; 2383 break; 2384 case RTW89_SCH_TX_SEL_MG0: 2385 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2386 0, B_AX_CTN_TXEN_MGQ); 2387 if (ret) 2388 return ret; 2389 break; 2390 case RTW89_SCH_TX_SEL_MACID: 2391 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2392 B_AX_CTN_TXEN_ALL_MASK_V1); 2393 if (ret) 2394 return ret; 2395 break; 2396 default: 2397 return 0; 2398 } 2399 2400 return 0; 2401 } 2402 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 2403 2404 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2405 { 2406 int ret; 2407 2408 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 2409 if (ret) 2410 return ret; 2411 2412 return 0; 2413 } 2414 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 2415 2416 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2417 { 2418 int ret; 2419 2420 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 2421 B_AX_CTN_TXEN_ALL_MASK_V1); 2422 if (ret) 2423 return ret; 2424 2425 return 0; 2426 } 2427 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 2428 2429 static u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, 2430 bool wd) 2431 { 2432 u32 val, reg; 2433 int ret; 2434 2435 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 2436 val = buf_len; 2437 val |= B_AX_WD_BUF_REQ_EXEC; 2438 rtw89_write32(rtwdev, reg, val); 2439 2440 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 2441 2442 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 2443 1, 2000, false, rtwdev, reg); 2444 if (ret) 2445 return 0xffff; 2446 2447 return FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 2448 } 2449 2450 static int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, 2451 struct rtw89_cpuio_ctrl *ctrl_para, 2452 bool wd) 2453 { 2454 u32 val, cmd_type, reg; 2455 int ret; 2456 2457 cmd_type = ctrl_para->cmd_type; 2458 2459 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 2460 val = 0; 2461 val = u32_replace_bits(val, ctrl_para->start_pktid, 2462 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 2463 val = u32_replace_bits(val, ctrl_para->end_pktid, 2464 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 2465 rtw89_write32(rtwdev, reg, val); 2466 2467 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 2468 val = 0; 2469 val = u32_replace_bits(val, ctrl_para->src_pid, 2470 B_AX_CPUQ_OP_SRC_PID_MASK); 2471 val = u32_replace_bits(val, ctrl_para->src_qid, 2472 B_AX_CPUQ_OP_SRC_QID_MASK); 2473 val = u32_replace_bits(val, ctrl_para->dst_pid, 2474 B_AX_CPUQ_OP_DST_PID_MASK); 2475 val = u32_replace_bits(val, ctrl_para->dst_qid, 2476 B_AX_CPUQ_OP_DST_QID_MASK); 2477 rtw89_write32(rtwdev, reg, val); 2478 2479 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 2480 val = 0; 2481 val = u32_replace_bits(val, cmd_type, 2482 B_AX_CPUQ_OP_CMD_TYPE_MASK); 2483 val = u32_replace_bits(val, ctrl_para->macid, 2484 B_AX_CPUQ_OP_MACID_MASK); 2485 val = u32_replace_bits(val, ctrl_para->pkt_num, 2486 B_AX_CPUQ_OP_PKTNUM_MASK); 2487 val |= B_AX_WD_CPUQ_OP_EXEC; 2488 rtw89_write32(rtwdev, reg, val); 2489 2490 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 2491 2492 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 2493 1, 2000, false, rtwdev, reg); 2494 if (ret) 2495 return ret; 2496 2497 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 2498 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 2499 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 2500 2501 return 0; 2502 } 2503 2504 static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2505 { 2506 const struct rtw89_dle_mem *cfg; 2507 struct rtw89_cpuio_ctrl ctrl_para = {0}; 2508 u16 pkt_id; 2509 int ret; 2510 2511 cfg = get_dle_mem_cfg(rtwdev, mode); 2512 if (!cfg) { 2513 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2514 return -EINVAL; 2515 } 2516 2517 if (dle_used_size(cfg->wde_size, cfg->ple_size) != rtwdev->chip->fifo_size) { 2518 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2519 return -EINVAL; 2520 } 2521 2522 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 2523 2524 pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, true); 2525 if (pkt_id == 0xffff) { 2526 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 2527 return -ENOMEM; 2528 } 2529 2530 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2531 ctrl_para.start_pktid = pkt_id; 2532 ctrl_para.end_pktid = pkt_id; 2533 ctrl_para.pkt_num = 0; 2534 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 2535 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 2536 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true); 2537 if (ret) { 2538 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 2539 return -EFAULT; 2540 } 2541 2542 pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, false); 2543 if (pkt_id == 0xffff) { 2544 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 2545 return -ENOMEM; 2546 } 2547 2548 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2549 ctrl_para.start_pktid = pkt_id; 2550 ctrl_para.end_pktid = pkt_id; 2551 ctrl_para.pkt_num = 0; 2552 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 2553 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 2554 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false); 2555 if (ret) { 2556 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 2557 return -EFAULT; 2558 } 2559 2560 return 0; 2561 } 2562 2563 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 2564 { 2565 int ret; 2566 u32 reg; 2567 u8 val; 2568 2569 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2570 if (ret) 2571 return ret; 2572 2573 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_TX_CTN_SEL, mac_idx); 2574 2575 ret = read_poll_timeout(rtw89_read8, val, 2576 (val & B_AX_PTCL_TX_ON_STAT) == 0, 2577 SW_CVR_DUR_US, 2578 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 2579 false, rtwdev, reg); 2580 if (ret) 2581 return ret; 2582 2583 return 0; 2584 } 2585 2586 static int band1_enable(struct rtw89_dev *rtwdev) 2587 { 2588 int ret, i; 2589 u32 sleep_bak[4] = {0}; 2590 u32 pause_bak[4] = {0}; 2591 u32 tx_en; 2592 2593 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 2594 if (ret) { 2595 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 2596 return ret; 2597 } 2598 2599 for (i = 0; i < 4; i++) { 2600 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 2601 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 2602 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 2603 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 2604 } 2605 2606 ret = band_idle_ck_b(rtwdev, 0); 2607 if (ret) { 2608 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 2609 return ret; 2610 } 2611 2612 ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode); 2613 if (ret) { 2614 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 2615 return ret; 2616 } 2617 2618 for (i = 0; i < 4; i++) { 2619 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 2620 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 2621 } 2622 2623 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 2624 if (ret) { 2625 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 2626 return ret; 2627 } 2628 2629 ret = cmac_func_en(rtwdev, 1, true); 2630 if (ret) { 2631 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 2632 return ret; 2633 } 2634 2635 ret = cmac_init(rtwdev, 1); 2636 if (ret) { 2637 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 2638 return ret; 2639 } 2640 2641 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 2642 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 2643 2644 return 0; 2645 } 2646 2647 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 2648 { 2649 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2650 2651 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 2652 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 2653 } 2654 2655 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 2656 { 2657 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2658 2659 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 2660 } 2661 2662 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 2663 { 2664 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2665 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2666 2667 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 2668 B_AX_TX_GET_ERRPKTID_INT_EN | 2669 B_AX_TX_NXT_ERRPKTID_INT_EN | 2670 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 2671 B_AX_TX_OFFSET_ERR_INT_EN | 2672 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 2673 if (chip_id == RTL8852C) 2674 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 2675 B_AX_TX_ETH_TYPE_ERR_EN | 2676 B_AX_TX_LLC_PRE_ERR_EN | 2677 B_AX_TX_NW_TYPE_ERR_EN | 2678 B_AX_TX_KSRCH_ERR_EN); 2679 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 2680 imr->mpdu_tx_imr_set); 2681 2682 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 2683 B_AX_GETPKTID_ERR_INT_EN | 2684 B_AX_MHDRLEN_ERR_INT_EN | 2685 B_AX_RPT_ERR_INT_EN); 2686 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 2687 imr->mpdu_rx_imr_set); 2688 } 2689 2690 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 2691 { 2692 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2693 2694 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 2695 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 2696 B_AX_RPT_HANG_TIMEOUT_INT_EN | 2697 B_AX_PLE_B_PKTID_ERR_INT_EN); 2698 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 2699 imr->sta_sch_imr_set); 2700 } 2701 2702 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 2703 { 2704 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2705 2706 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 2707 imr->txpktctl_imr_b0_clr); 2708 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 2709 imr->txpktctl_imr_b0_set); 2710 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 2711 imr->txpktctl_imr_b1_clr); 2712 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 2713 imr->txpktctl_imr_b1_set); 2714 } 2715 2716 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 2717 { 2718 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2719 2720 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 2721 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 2722 } 2723 2724 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 2725 { 2726 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2727 2728 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 2729 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 2730 } 2731 2732 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 2733 { 2734 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 2735 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 2736 } 2737 2738 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 2739 { 2740 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2741 2742 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 2743 imr->host_disp_imr_clr); 2744 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 2745 imr->host_disp_imr_set); 2746 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 2747 imr->cpu_disp_imr_clr); 2748 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 2749 imr->cpu_disp_imr_set); 2750 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 2751 imr->other_disp_imr_clr); 2752 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 2753 imr->other_disp_imr_set); 2754 } 2755 2756 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 2757 { 2758 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 2759 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 2760 } 2761 2762 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 2763 { 2764 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2765 2766 rtw89_write32_set(rtwdev, R_AX_BBRPT_COM_ERR_IMR, 2767 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 2768 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 2769 B_AX_BBRPT_CHINFO_IMR_CLR); 2770 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 2771 imr->bbrpt_err_imr_set); 2772 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 2773 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 2774 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 2775 } 2776 2777 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 2778 { 2779 u32 reg; 2780 2781 reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx); 2782 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 2783 B_AX_FSM_TIMEOUT_ERR_INT_EN); 2784 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 2785 } 2786 2787 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 2788 { 2789 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2790 u32 reg; 2791 2792 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx); 2793 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 2794 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 2795 } 2796 2797 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 2798 { 2799 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2800 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2801 u32 reg; 2802 2803 reg = rtw89_mac_reg_by_idx(imr->cdma_imr_0_reg, mac_idx); 2804 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 2805 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 2806 2807 if (chip_id == RTL8852C) { 2808 reg = rtw89_mac_reg_by_idx(imr->cdma_imr_1_reg, mac_idx); 2809 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 2810 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 2811 } 2812 } 2813 2814 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 2815 { 2816 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2817 u32 reg; 2818 2819 reg = rtw89_mac_reg_by_idx(imr->phy_intf_imr_reg, mac_idx); 2820 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 2821 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 2822 } 2823 2824 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 2825 { 2826 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2827 u32 reg; 2828 2829 reg = rtw89_mac_reg_by_idx(imr->rmac_imr_reg, mac_idx); 2830 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 2831 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 2832 } 2833 2834 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 2835 { 2836 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2837 u32 reg; 2838 2839 reg = rtw89_mac_reg_by_idx(imr->tmac_imr_reg, mac_idx); 2840 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 2841 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 2842 } 2843 2844 static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, 2845 enum rtw89_mac_hwmod_sel sel) 2846 { 2847 int ret; 2848 2849 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 2850 if (ret) { 2851 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 2852 sel, mac_idx); 2853 return ret; 2854 } 2855 2856 if (sel == RTW89_DMAC_SEL) { 2857 rtw89_wdrls_imr_enable(rtwdev); 2858 rtw89_wsec_imr_enable(rtwdev); 2859 rtw89_mpdu_trx_imr_enable(rtwdev); 2860 rtw89_sta_sch_imr_enable(rtwdev); 2861 rtw89_txpktctl_imr_enable(rtwdev); 2862 rtw89_wde_imr_enable(rtwdev); 2863 rtw89_ple_imr_enable(rtwdev); 2864 rtw89_pktin_imr_enable(rtwdev); 2865 rtw89_dispatcher_imr_enable(rtwdev); 2866 rtw89_cpuio_imr_enable(rtwdev); 2867 rtw89_bbrpt_imr_enable(rtwdev); 2868 } else if (sel == RTW89_CMAC_SEL) { 2869 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 2870 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 2871 rtw89_cdma_imr_enable(rtwdev, mac_idx); 2872 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 2873 rtw89_rmac_imr_enable(rtwdev, mac_idx); 2874 rtw89_tmac_imr_enable(rtwdev, mac_idx); 2875 } else { 2876 return -EINVAL; 2877 } 2878 2879 return 0; 2880 } 2881 2882 static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en) 2883 { 2884 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2885 2886 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 2887 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 2888 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 2889 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 2890 if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta) 2891 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 2892 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 2893 } 2894 2895 static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) 2896 { 2897 int ret = 0; 2898 2899 if (enable) { 2900 ret = band1_enable(rtwdev); 2901 if (ret) { 2902 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 2903 return ret; 2904 } 2905 2906 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 2907 if (ret) { 2908 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 2909 return ret; 2910 } 2911 } else { 2912 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 2913 return -EINVAL; 2914 } 2915 2916 return 0; 2917 } 2918 2919 static int set_host_rpr(struct rtw89_dev *rtwdev) 2920 { 2921 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2922 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 2923 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 2924 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 2925 B_AX_RLSRPT0_FLTR_MAP_MASK); 2926 } else { 2927 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 2928 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 2929 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 2930 B_AX_RLSRPT0_FLTR_MAP_MASK); 2931 } 2932 2933 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 2934 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 2935 2936 return 0; 2937 } 2938 2939 static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) 2940 { 2941 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 2942 int ret; 2943 2944 ret = dmac_init(rtwdev, 0); 2945 if (ret) { 2946 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 2947 return ret; 2948 } 2949 2950 ret = cmac_init(rtwdev, 0); 2951 if (ret) { 2952 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 2953 return ret; 2954 } 2955 2956 if (is_qta_dbcc(rtwdev, qta_mode)) { 2957 ret = rtw89_mac_dbcc_enable(rtwdev, true); 2958 if (ret) { 2959 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 2960 return ret; 2961 } 2962 } 2963 2964 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2965 if (ret) { 2966 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 2967 return ret; 2968 } 2969 2970 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 2971 if (ret) { 2972 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 2973 return ret; 2974 } 2975 2976 rtw89_mac_err_imr_ctrl(rtwdev, true); 2977 2978 ret = set_host_rpr(rtwdev); 2979 if (ret) { 2980 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 2981 return ret; 2982 } 2983 2984 return 0; 2985 } 2986 2987 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 2988 { 2989 u32 val32; 2990 2991 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 2992 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 2993 2994 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 2995 val32 |= B_AX_FS_WDT_INT; 2996 val32 &= ~B_AX_FS_WDT_INT_MSK; 2997 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 2998 } 2999 3000 static void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev) 3001 { 3002 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3003 3004 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3005 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3006 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3007 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3008 3009 rtw89_disable_fw_watchdog(rtwdev); 3010 3011 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3012 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3013 } 3014 3015 static int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, 3016 bool dlfw) 3017 { 3018 u32 val; 3019 int ret; 3020 3021 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3022 return -EFAULT; 3023 3024 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3025 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3026 3027 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3028 3029 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3030 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3031 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3032 B_AX_WCPU_FWDL_STS_MASK); 3033 3034 if (dlfw) 3035 val |= B_AX_WCPU_FWDL_EN; 3036 3037 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3038 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3039 boot_reason); 3040 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3041 3042 if (!dlfw) { 3043 mdelay(5); 3044 3045 ret = rtw89_fw_check_rdy(rtwdev); 3046 if (ret) 3047 return ret; 3048 } 3049 3050 return 0; 3051 } 3052 3053 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3054 { 3055 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3056 u32 val; 3057 int ret; 3058 3059 if (chip_id == RTL8852C) 3060 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3061 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3062 else 3063 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3064 B_AX_PKT_BUF_EN; 3065 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3066 3067 val = B_AX_DISPATCHER_CLK_EN; 3068 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3069 3070 if (chip_id != RTL8852C) 3071 goto dle; 3072 3073 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3074 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3075 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3076 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3077 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3078 3079 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3080 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3081 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3082 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3083 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3084 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3085 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3086 3087 dle: 3088 ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3089 if (ret) { 3090 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3091 return ret; 3092 } 3093 3094 ret = hfc_init(rtwdev, true, false, true); 3095 if (ret) { 3096 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3097 return ret; 3098 } 3099 3100 return ret; 3101 } 3102 3103 static void rtw89_mac_hci_func_en(struct rtw89_dev *rtwdev) 3104 { 3105 const struct rtw89_chip_info *chip = rtwdev->chip; 3106 3107 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 3108 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 3109 } 3110 3111 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3112 { 3113 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3114 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3115 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3116 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3117 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3118 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3119 3120 return 0; 3121 } 3122 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3123 3124 void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3125 { 3126 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3127 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3128 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3129 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3130 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3131 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3132 } 3133 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3134 3135 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev) 3136 { 3137 int ret; 3138 3139 ret = rtw89_mac_power_switch(rtwdev, true); 3140 if (ret) { 3141 rtw89_mac_power_switch(rtwdev, false); 3142 ret = rtw89_mac_power_switch(rtwdev, true); 3143 if (ret) 3144 return ret; 3145 } 3146 3147 rtw89_mac_hci_func_en(rtwdev); 3148 3149 ret = rtw89_mac_dmac_pre_init(rtwdev); 3150 if (ret) 3151 return ret; 3152 3153 if (rtwdev->hci.ops->mac_pre_init) { 3154 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3155 if (ret) 3156 return ret; 3157 } 3158 3159 rtw89_mac_disable_cpu(rtwdev); 3160 ret = rtw89_mac_enable_cpu(rtwdev, 0, true); 3161 if (ret) 3162 return ret; 3163 3164 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL); 3165 if (ret) 3166 return ret; 3167 3168 return 0; 3169 } 3170 3171 int rtw89_mac_init(struct rtw89_dev *rtwdev) 3172 { 3173 int ret; 3174 3175 ret = rtw89_mac_partial_init(rtwdev); 3176 if (ret) 3177 goto fail; 3178 3179 ret = rtw89_chip_enable_bb_rf(rtwdev); 3180 if (ret) 3181 goto fail; 3182 3183 ret = rtw89_mac_sys_init(rtwdev); 3184 if (ret) 3185 goto fail; 3186 3187 ret = rtw89_mac_trx_init(rtwdev); 3188 if (ret) 3189 goto fail; 3190 3191 if (rtwdev->hci.ops->mac_post_init) { 3192 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3193 if (ret) 3194 goto fail; 3195 } 3196 3197 rtw89_fw_send_all_early_h2c(rtwdev); 3198 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3199 3200 return ret; 3201 fail: 3202 rtw89_mac_power_switch(rtwdev, false); 3203 3204 return ret; 3205 } 3206 3207 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3208 { 3209 u8 i; 3210 3211 for (i = 0; i < 4; i++) { 3212 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3213 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 3214 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 3215 } 3216 } 3217 3218 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3219 { 3220 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3221 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 3222 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 3223 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 3224 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 3225 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 3226 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 3227 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 3228 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 3229 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 3230 } 3231 3232 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 3233 { 3234 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 3235 u8 grp = macid >> 5; 3236 int ret; 3237 3238 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3239 if (ret) 3240 return ret; 3241 3242 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 3243 3244 return 0; 3245 } 3246 3247 static const struct rtw89_port_reg rtw_port_base = { 3248 .port_cfg = R_AX_PORT_CFG_P0, 3249 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 3250 .bcn_area = R_AX_BCN_AREA_P0, 3251 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 3252 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 3253 .tbtt_agg = R_AX_TBTT_AGG_P0, 3254 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 3255 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 3256 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 3257 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 3258 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 3259 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 3260 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 3261 .tsftr_l = R_AX_TSFTR_LOW_P0, 3262 .tsftr_h = R_AX_TSFTR_HIGH_P0 3263 }; 3264 3265 #define BCN_INTERVAL 100 3266 #define BCN_ERLY_DEF 160 3267 #define BCN_SETUP_DEF 2 3268 #define BCN_HOLD_DEF 200 3269 #define BCN_MASK_DEF 0 3270 #define TBTT_ERLY_DEF 5 3271 #define BCN_SET_UNIT 32 3272 #define BCN_ERLY_SET_DLY (10 * 2) 3273 3274 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 3275 struct rtw89_vif *rtwvif) 3276 { 3277 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3278 const struct rtw89_port_reg *p = &rtw_port_base; 3279 3280 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 3281 return; 3282 3283 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 3284 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 3285 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 3286 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 3287 3288 msleep(vif->bss_conf.beacon_int + 1); 3289 3290 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 3291 B_AX_BRK_SETUP); 3292 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 3293 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 3294 } 3295 3296 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 3297 struct rtw89_vif *rtwvif, bool en) 3298 { 3299 const struct rtw89_port_reg *p = &rtw_port_base; 3300 3301 if (en) 3302 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3303 else 3304 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3305 } 3306 3307 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 3308 struct rtw89_vif *rtwvif, bool en) 3309 { 3310 const struct rtw89_port_reg *p = &rtw_port_base; 3311 3312 if (en) 3313 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3314 else 3315 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3316 } 3317 3318 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 3319 struct rtw89_vif *rtwvif) 3320 { 3321 const struct rtw89_port_reg *p = &rtw_port_base; 3322 3323 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 3324 rtwvif->net_type); 3325 } 3326 3327 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 3328 struct rtw89_vif *rtwvif) 3329 { 3330 const struct rtw89_port_reg *p = &rtw_port_base; 3331 bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 3332 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 3333 3334 if (en) 3335 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 3336 else 3337 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 3338 } 3339 3340 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 3341 struct rtw89_vif *rtwvif) 3342 { 3343 const struct rtw89_port_reg *p = &rtw_port_base; 3344 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3345 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3346 u32 bit = B_AX_RX_BSSID_FIT_EN; 3347 3348 if (en) 3349 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 3350 else 3351 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 3352 } 3353 3354 static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 3355 struct rtw89_vif *rtwvif) 3356 { 3357 const struct rtw89_port_reg *p = &rtw_port_base; 3358 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3359 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3360 3361 if (en) 3362 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3363 else 3364 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3365 } 3366 3367 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 3368 struct rtw89_vif *rtwvif) 3369 { 3370 const struct rtw89_port_reg *p = &rtw_port_base; 3371 bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 3372 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3373 3374 if (en) 3375 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3376 else 3377 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3378 } 3379 3380 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 3381 struct rtw89_vif *rtwvif) 3382 { 3383 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3384 const struct rtw89_port_reg *p = &rtw_port_base; 3385 u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 3386 3387 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 3388 bcn_int); 3389 } 3390 3391 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 3392 struct rtw89_vif *rtwvif) 3393 { 3394 static const u32 hiq_win_addr[RTW89_PORT_NUM] = { 3395 R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 3396 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 3397 R_AX_PORT_HGQ_WINDOW_CFG + 3, 3398 }; 3399 u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 3400 u8 port = rtwvif->port; 3401 u32 reg; 3402 3403 reg = rtw89_mac_reg_by_idx(hiq_win_addr[port], rtwvif->mac_idx); 3404 rtw89_write8(rtwdev, reg, win); 3405 } 3406 3407 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 3408 struct rtw89_vif *rtwvif) 3409 { 3410 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3411 const struct rtw89_port_reg *p = &rtw_port_base; 3412 u32 addr; 3413 3414 addr = rtw89_mac_reg_by_idx(R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx); 3415 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 3416 3417 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 3418 vif->bss_conf.dtim_period); 3419 } 3420 3421 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 3422 struct rtw89_vif *rtwvif) 3423 { 3424 const struct rtw89_port_reg *p = &rtw_port_base; 3425 3426 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3427 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 3428 } 3429 3430 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 3431 struct rtw89_vif *rtwvif) 3432 { 3433 const struct rtw89_port_reg *p = &rtw_port_base; 3434 3435 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3436 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 3437 } 3438 3439 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 3440 struct rtw89_vif *rtwvif) 3441 { 3442 const struct rtw89_port_reg *p = &rtw_port_base; 3443 3444 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 3445 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 3446 } 3447 3448 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 3449 struct rtw89_vif *rtwvif) 3450 { 3451 const struct rtw89_port_reg *p = &rtw_port_base; 3452 3453 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 3454 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 3455 } 3456 3457 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 3458 struct rtw89_vif *rtwvif) 3459 { 3460 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3461 static const u32 masks[RTW89_PORT_NUM] = { 3462 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 3463 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 3464 B_AX_BSS_COLOB_AX_PORT_4_MASK, 3465 }; 3466 u8 port = rtwvif->port; 3467 u32 reg_base; 3468 u32 reg; 3469 u8 bss_color; 3470 3471 bss_color = vif->bss_conf.he_bss_color.color; 3472 reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0; 3473 reg = rtw89_mac_reg_by_idx(reg_base, rtwvif->mac_idx); 3474 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 3475 } 3476 3477 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 3478 struct rtw89_vif *rtwvif) 3479 { 3480 u8 port = rtwvif->port; 3481 u32 reg; 3482 3483 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 3484 return; 3485 3486 if (port == 0) { 3487 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_CTRL, rtwvif->mac_idx); 3488 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 3489 } 3490 } 3491 3492 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 3493 struct rtw89_vif *rtwvif) 3494 { 3495 u8 port = rtwvif->port; 3496 u32 reg; 3497 u32 val; 3498 3499 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_DROP_0, rtwvif->mac_idx); 3500 val = rtw89_read32(rtwdev, reg); 3501 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 3502 if (port == 0) 3503 val &= ~BIT(0); 3504 rtw89_write32(rtwdev, reg, val); 3505 } 3506 3507 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 3508 struct rtw89_vif *rtwvif) 3509 { 3510 const struct rtw89_port_reg *p = &rtw_port_base; 3511 3512 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN); 3513 } 3514 3515 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 3516 struct rtw89_vif *rtwvif) 3517 { 3518 const struct rtw89_port_reg *p = &rtw_port_base; 3519 3520 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 3521 BCN_ERLY_DEF); 3522 } 3523 3524 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3525 { 3526 int ret; 3527 3528 ret = rtw89_mac_port_update(rtwdev, rtwvif); 3529 if (ret) 3530 return ret; 3531 3532 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 3533 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 3534 3535 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 3536 if (ret) 3537 return ret; 3538 3539 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 3540 if (ret) 3541 return ret; 3542 3543 ret = rtw89_cam_init(rtwdev, rtwvif); 3544 if (ret) 3545 return ret; 3546 3547 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 3548 if (ret) 3549 return ret; 3550 3551 ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif); 3552 if (ret) 3553 return ret; 3554 3555 return 0; 3556 } 3557 3558 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3559 { 3560 int ret; 3561 3562 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 3563 if (ret) 3564 return ret; 3565 3566 rtw89_cam_deinit(rtwdev, rtwvif); 3567 3568 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 3569 if (ret) 3570 return ret; 3571 3572 return 0; 3573 } 3574 3575 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3576 { 3577 u8 port = rtwvif->port; 3578 3579 if (port >= RTW89_PORT_NUM) 3580 return -EINVAL; 3581 3582 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 3583 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 3584 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 3585 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 3586 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 3587 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 3588 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); 3589 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif); 3590 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 3591 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 3592 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 3593 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 3594 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 3595 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 3596 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 3597 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 3598 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 3599 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 3600 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif); 3601 fsleep(BCN_ERLY_SET_DLY); 3602 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 3603 3604 return 0; 3605 } 3606 3607 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3608 { 3609 int ret; 3610 3611 rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 3612 RTW89_MAX_MAC_ID_NUM); 3613 if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 3614 return -ENOSPC; 3615 3616 ret = rtw89_mac_vif_init(rtwdev, rtwvif); 3617 if (ret) 3618 goto release_mac_id; 3619 3620 return 0; 3621 3622 release_mac_id: 3623 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 3624 3625 return ret; 3626 } 3627 3628 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3629 { 3630 int ret; 3631 3632 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 3633 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 3634 3635 return ret; 3636 } 3637 3638 static void 3639 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3640 { 3641 } 3642 3643 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 3644 { 3645 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 3646 3647 return band == scan_info->op_band && channel == scan_info->op_pri_ch; 3648 } 3649 3650 static void 3651 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 3652 u32 len) 3653 { 3654 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 3655 struct rtw89_hal *hal = &rtwdev->hal; 3656 u8 reason, status, tx_fail, band; 3657 u16 chan; 3658 3659 tx_fail = RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h->data); 3660 status = RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h->data); 3661 chan = RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h->data); 3662 reason = RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h->data); 3663 band = RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h->data); 3664 3665 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 3666 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 3667 3668 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 3669 "band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d\n", 3670 band, chan, reason, status, tx_fail); 3671 3672 switch (reason) { 3673 case RTW89_SCAN_LEAVE_CH_NOTIFY: 3674 if (rtw89_is_op_chan(rtwdev, band, chan)) 3675 ieee80211_stop_queues(rtwdev->hw); 3676 return; 3677 case RTW89_SCAN_END_SCAN_NOTIFY: 3678 rtw89_hw_scan_complete(rtwdev, vif, false); 3679 break; 3680 case RTW89_SCAN_ENTER_CH_NOTIFY: 3681 if (rtw89_is_op_chan(rtwdev, band, chan)) 3682 ieee80211_wake_queues(rtwdev->hw); 3683 break; 3684 default: 3685 return; 3686 } 3687 3688 hal->prev_band_type = hal->current_band_type; 3689 hal->prev_primary_channel = hal->current_channel; 3690 hal->current_channel = chan; 3691 hal->current_band_type = band; 3692 } 3693 3694 static void 3695 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3696 { 3697 rtw89_debug(rtwdev, RTW89_DBG_FW, 3698 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 3699 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 3700 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 3701 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 3702 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 3703 } 3704 3705 static void 3706 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3707 { 3708 rtw89_debug(rtwdev, RTW89_DBG_FW, 3709 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 3710 RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h->data), 3711 RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h->data), 3712 RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h->data), 3713 RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h->data), 3714 RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h->data)); 3715 } 3716 3717 static void 3718 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3719 { 3720 rtw89_info(rtwdev, "%*s", RTW89_GET_C2H_LOG_LEN(len), 3721 RTW89_GET_C2H_LOG_SRT_PRT(c2h->data)); 3722 } 3723 3724 static void 3725 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3726 { 3727 } 3728 3729 static void 3730 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 3731 u32 len) 3732 { 3733 } 3734 3735 static 3736 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 3737 struct sk_buff *c2h, u32 len) = { 3738 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 3739 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 3740 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 3741 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 3742 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 3743 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 3744 }; 3745 3746 static 3747 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 3748 struct sk_buff *c2h, u32 len) = { 3749 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 3750 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 3751 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 3752 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 3753 }; 3754 3755 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 3756 u32 len, u8 class, u8 func) 3757 { 3758 void (*handler)(struct rtw89_dev *rtwdev, 3759 struct sk_buff *c2h, u32 len) = NULL; 3760 3761 switch (class) { 3762 case RTW89_MAC_C2H_CLASS_INFO: 3763 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 3764 handler = rtw89_mac_c2h_info_handler[func]; 3765 break; 3766 case RTW89_MAC_C2H_CLASS_OFLD: 3767 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 3768 handler = rtw89_mac_c2h_ofld_handler[func]; 3769 break; 3770 case RTW89_MAC_C2H_CLASS_FWDBG: 3771 return; 3772 default: 3773 rtw89_info(rtwdev, "c2h class %d not support\n", class); 3774 return; 3775 } 3776 if (!handler) { 3777 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 3778 func); 3779 return; 3780 } 3781 handler(rtwdev, skb, len); 3782 } 3783 3784 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 3785 enum rtw89_phy_idx phy_idx, 3786 u32 reg_base, u32 *cr) 3787 { 3788 const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; 3789 enum rtw89_qta_mode mode = dle_mem->mode; 3790 u32 addr = rtw89_mac_reg_by_idx(reg_base, phy_idx); 3791 3792 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) { 3793 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 3794 addr); 3795 goto error; 3796 } 3797 3798 if (addr >= CMAC1_START_ADDR && addr <= CMAC1_END_ADDR) 3799 if (mode == RTW89_QTA_SCC) { 3800 rtw89_err(rtwdev, 3801 "[TXPWR] addr=0x%x but hw not enable\n", 3802 addr); 3803 goto error; 3804 } 3805 3806 *cr = addr; 3807 return true; 3808 3809 error: 3810 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 3811 addr, phy_idx); 3812 3813 return false; 3814 } 3815 EXPORT_SYMBOL(rtw89_mac_get_txpwr_cr); 3816 3817 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 3818 { 3819 u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx); 3820 int ret = 0; 3821 3822 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3823 if (ret) 3824 return ret; 3825 3826 if (!enable) { 3827 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 3828 return ret; 3829 } 3830 3831 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 3832 B_AX_APP_MAC_INFO_RPT | 3833 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 3834 B_AX_PPDU_STAT_RPT_CRC32); 3835 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 3836 RTW89_PRPT_DEST_HOST); 3837 3838 return ret; 3839 } 3840 EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status); 3841 3842 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 3843 { 3844 #define MAC_AX_TIME_TH_SH 5 3845 #define MAC_AX_LEN_TH_SH 4 3846 #define MAC_AX_TIME_TH_MAX 255 3847 #define MAC_AX_LEN_TH_MAX 255 3848 #define MAC_AX_TIME_TH_DEF 88 3849 #define MAC_AX_LEN_TH_DEF 4080 3850 struct ieee80211_hw *hw = rtwdev->hw; 3851 u32 rts_threshold = hw->wiphy->rts_threshold; 3852 u32 time_th, len_th; 3853 u32 reg; 3854 3855 if (rts_threshold == (u32)-1) { 3856 time_th = MAC_AX_TIME_TH_DEF; 3857 len_th = MAC_AX_LEN_TH_DEF; 3858 } else { 3859 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 3860 len_th = rts_threshold; 3861 } 3862 3863 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 3864 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 3865 3866 reg = rtw89_mac_reg_by_idx(R_AX_AGG_LEN_HT_0, mac_idx); 3867 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 3868 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 3869 } 3870 3871 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 3872 { 3873 bool empty; 3874 int ret; 3875 3876 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3877 return; 3878 3879 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 3880 10000, 200000, false, rtwdev); 3881 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 3882 rtw89_info(rtwdev, "timed out to flush queues\n"); 3883 } 3884 3885 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 3886 { 3887 u8 val; 3888 u16 val16; 3889 u32 val32; 3890 int ret; 3891 3892 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 3893 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 3894 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 3895 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 3896 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 3897 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 3898 3899 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 3900 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 3901 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 3902 3903 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 3904 if (ret) { 3905 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 3906 return ret; 3907 } 3908 val32 = val32 & B_AX_WL_RX_CTRL; 3909 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 3910 if (ret) { 3911 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 3912 return ret; 3913 } 3914 3915 switch (coex->pta_mode) { 3916 case RTW89_MAC_AX_COEX_RTK_MODE: 3917 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 3918 val &= ~B_AX_BTMODE_MASK; 3919 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 3920 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 3921 3922 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 3923 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 3924 3925 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 3926 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 3927 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 3928 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 3929 break; 3930 case RTW89_MAC_AX_COEX_CSR_MODE: 3931 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 3932 val &= ~B_AX_BTMODE_MASK; 3933 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 3934 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 3935 3936 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 3937 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 3938 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 3939 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 3940 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 3941 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 3942 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 3943 val16 |= B_AX_ENHANCED_BT; 3944 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 3945 3946 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 3947 break; 3948 default: 3949 return -EINVAL; 3950 } 3951 3952 switch (coex->direction) { 3953 case RTW89_MAC_AX_COEX_INNER: 3954 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 3955 val = (val & ~BIT(2)) | BIT(1); 3956 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 3957 break; 3958 case RTW89_MAC_AX_COEX_OUTPUT: 3959 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 3960 val = val | BIT(1) | BIT(0); 3961 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 3962 break; 3963 case RTW89_MAC_AX_COEX_INPUT: 3964 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 3965 val = val & ~(BIT(2) | BIT(1)); 3966 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 3967 break; 3968 default: 3969 return -EINVAL; 3970 } 3971 3972 return 0; 3973 } 3974 EXPORT_SYMBOL(rtw89_mac_coex_init); 3975 3976 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 3977 const struct rtw89_mac_ax_coex *coex) 3978 { 3979 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 3980 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 3981 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 3982 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 3983 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 3984 3985 switch (coex->pta_mode) { 3986 case RTW89_MAC_AX_COEX_RTK_MODE: 3987 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 3988 MAC_AX_RTK_MODE); 3989 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 3990 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 3991 break; 3992 case RTW89_MAC_AX_COEX_CSR_MODE: 3993 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 3994 MAC_AX_CSR_MODE); 3995 break; 3996 default: 3997 return -EINVAL; 3998 } 3999 4000 return 0; 4001 } 4002 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 4003 4004 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 4005 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4006 { 4007 u32 val = 0, ret; 4008 4009 if (gnt_cfg->band[0].gnt_bt) 4010 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 4011 4012 if (gnt_cfg->band[0].gnt_bt_sw_en) 4013 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 4014 4015 if (gnt_cfg->band[0].gnt_wl) 4016 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 4017 4018 if (gnt_cfg->band[0].gnt_wl_sw_en) 4019 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 4020 4021 if (gnt_cfg->band[1].gnt_bt) 4022 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 4023 4024 if (gnt_cfg->band[1].gnt_bt_sw_en) 4025 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 4026 4027 if (gnt_cfg->band[1].gnt_wl) 4028 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 4029 4030 if (gnt_cfg->band[1].gnt_wl_sw_en) 4031 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 4032 4033 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 4034 if (ret) { 4035 rtw89_err(rtwdev, "Write LTE fail!\n"); 4036 return ret; 4037 } 4038 4039 return 0; 4040 } 4041 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 4042 4043 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 4044 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4045 { 4046 u32 val = 0; 4047 4048 if (gnt_cfg->band[0].gnt_bt) 4049 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 4050 B_AX_GNT_BT_TX_VAL; 4051 else 4052 val |= B_AX_WL_ACT_VAL; 4053 4054 if (gnt_cfg->band[0].gnt_bt_sw_en) 4055 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 4056 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 4057 4058 if (gnt_cfg->band[0].gnt_wl) 4059 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 4060 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 4061 4062 if (gnt_cfg->band[0].gnt_wl_sw_en) 4063 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 4064 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 4065 4066 if (gnt_cfg->band[1].gnt_bt) 4067 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 4068 B_AX_GNT_BT_TX_VAL; 4069 else 4070 val |= B_AX_WL_ACT_VAL; 4071 4072 if (gnt_cfg->band[1].gnt_bt_sw_en) 4073 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 4074 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 4075 4076 if (gnt_cfg->band[1].gnt_wl) 4077 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 4078 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 4079 4080 if (gnt_cfg->band[1].gnt_wl_sw_en) 4081 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 4082 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 4083 4084 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 4085 4086 return 0; 4087 } 4088 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 4089 4090 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 4091 { 4092 u32 reg; 4093 u16 val; 4094 int ret; 4095 4096 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 4097 if (ret) 4098 return ret; 4099 4100 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, plt->band); 4101 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 4102 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 4103 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 4104 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 4105 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 4106 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 4107 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 4108 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 4109 B_AX_PLT_EN; 4110 rtw89_write16(rtwdev, reg, val); 4111 4112 return 0; 4113 } 4114 4115 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 4116 { 4117 u32 fw_sb; 4118 4119 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 4120 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 4121 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 4122 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4123 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 4124 else 4125 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 4126 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 4127 val = B_AX_TOGGLE | 4128 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 4129 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 4130 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 4131 fsleep(1000); /* avoid BT FW loss information */ 4132 } 4133 4134 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 4135 { 4136 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 4137 } 4138 4139 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 4140 { 4141 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 4142 4143 val = wl ? val | BIT(2) : val & ~BIT(2); 4144 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 4145 4146 return 0; 4147 } 4148 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 4149 4150 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 4151 { 4152 struct rtw89_btc *btc = &rtwdev->btc; 4153 struct rtw89_btc_dm *dm = &btc->dm; 4154 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 4155 int i; 4156 4157 if (wl) 4158 return 0; 4159 4160 for (i = 0; i < RTW89_PHY_MAX; i++) { 4161 g[i].gnt_bt_sw_en = 1; 4162 g[i].gnt_bt = 1; 4163 g[i].gnt_wl_sw_en = 1; 4164 g[i].gnt_wl = 0; 4165 } 4166 4167 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 4168 } 4169 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 4170 4171 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 4172 { 4173 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 4174 4175 return FIELD_GET(B_AX_LTE_MUX_CTRL_PATH >> 24, val); 4176 } 4177 4178 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 4179 { 4180 u32 reg; 4181 u16 cnt; 4182 4183 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, band); 4184 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 4185 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 4186 4187 return cnt; 4188 } 4189 4190 static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 4191 { 4192 u32 reg; 4193 u32 mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 4194 B_AX_BFMEE_HE_NDPA_EN; 4195 4196 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 4197 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 4198 if (en) { 4199 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 4200 rtw89_write32_set(rtwdev, reg, mask); 4201 } else { 4202 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 4203 rtw89_write32_clr(rtwdev, reg, mask); 4204 } 4205 } 4206 4207 static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx) 4208 { 4209 u32 reg; 4210 u32 val32; 4211 int ret; 4212 4213 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4214 if (ret) 4215 return ret; 4216 4217 /* AP mode set tx gid to 63 */ 4218 /* STA mode set tx gid to 0(default) */ 4219 reg = rtw89_mac_reg_by_idx(R_AX_BFMER_CTRL_0, mac_idx); 4220 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 4221 4222 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 4223 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 4224 4225 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 4226 val32 = FIELD_PREP(B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, BFRP_RX_STANDBY_TIMER); 4227 val32 |= FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 4228 rtw89_write32(rtwdev, reg, val32); 4229 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 4230 4231 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 4232 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 4233 B_AX_BFMEE_USE_NSTS | 4234 B_AX_BFMEE_CSI_GID_SEL | 4235 B_AX_BFMEE_CSI_FORCE_RETE_EN); 4236 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 4237 rtw89_write32(rtwdev, reg, 4238 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 4239 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 4240 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 4241 4242 return 0; 4243 } 4244 4245 static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, 4246 struct ieee80211_vif *vif, 4247 struct ieee80211_sta *sta) 4248 { 4249 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4250 u8 mac_idx = rtwvif->mac_idx; 4251 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 4252 u8 port_sel = rtwvif->port; 4253 u8 sound_dim = 3, t; 4254 u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 4255 u32 reg; 4256 u16 val; 4257 int ret; 4258 4259 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4260 if (ret) 4261 return ret; 4262 4263 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 4264 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 4265 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 4266 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 4267 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 4268 phy_cap[5]); 4269 sound_dim = min(sound_dim, t); 4270 } 4271 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 4272 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 4273 ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 4274 stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 4275 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 4276 sta->deflink.vht_cap.cap); 4277 sound_dim = min(sound_dim, t); 4278 } 4279 nc = min(nc, sound_dim); 4280 nr = min(nr, sound_dim); 4281 4282 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 4283 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 4284 4285 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 4286 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 4287 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 4288 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 4289 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 4290 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 4291 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 4292 4293 if (port_sel == 0) 4294 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 4295 else 4296 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 4297 4298 rtw89_write16(rtwdev, reg, val); 4299 4300 return 0; 4301 } 4302 4303 static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev, 4304 struct ieee80211_vif *vif, 4305 struct ieee80211_sta *sta) 4306 { 4307 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4308 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 4309 u32 reg; 4310 u8 mac_idx = rtwvif->mac_idx; 4311 int ret; 4312 4313 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4314 if (ret) 4315 return ret; 4316 4317 if (sta->deflink.he_cap.has_he) { 4318 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 4319 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 4320 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 4321 } 4322 if (sta->deflink.vht_cap.vht_supported) { 4323 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 4324 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 4325 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 4326 } 4327 if (sta->deflink.ht_cap.ht_supported) { 4328 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 4329 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 4330 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 4331 } 4332 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 4333 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 4334 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 4335 rtw89_write32(rtwdev, 4336 rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 4337 rrsc); 4338 4339 return 0; 4340 } 4341 4342 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4343 struct ieee80211_sta *sta) 4344 { 4345 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4346 4347 if (rtw89_sta_has_beamformer_cap(sta)) { 4348 rtw89_debug(rtwdev, RTW89_DBG_BF, 4349 "initialize bfee for new association\n"); 4350 rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx); 4351 rtw89_mac_set_csi_para_reg(rtwdev, vif, sta); 4352 rtw89_mac_csi_rrsc(rtwdev, vif, sta); 4353 } 4354 } 4355 4356 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4357 struct ieee80211_sta *sta) 4358 { 4359 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4360 4361 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 4362 } 4363 4364 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4365 struct ieee80211_bss_conf *conf) 4366 { 4367 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4368 u8 mac_idx = rtwvif->mac_idx; 4369 __le32 *p; 4370 4371 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 4372 4373 p = (__le32 *)conf->mu_group.membership; 4374 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx), 4375 le32_to_cpu(p[0])); 4376 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx), 4377 le32_to_cpu(p[1])); 4378 4379 p = (__le32 *)conf->mu_group.position; 4380 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx), 4381 le32_to_cpu(p[0])); 4382 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx), 4383 le32_to_cpu(p[1])); 4384 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx), 4385 le32_to_cpu(p[2])); 4386 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx), 4387 le32_to_cpu(p[3])); 4388 } 4389 4390 struct rtw89_mac_bf_monitor_iter_data { 4391 struct rtw89_dev *rtwdev; 4392 struct ieee80211_sta *down_sta; 4393 int count; 4394 }; 4395 4396 static 4397 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 4398 { 4399 struct rtw89_mac_bf_monitor_iter_data *iter_data = 4400 (struct rtw89_mac_bf_monitor_iter_data *)data; 4401 struct ieee80211_sta *down_sta = iter_data->down_sta; 4402 int *count = &iter_data->count; 4403 4404 if (down_sta == sta) 4405 return; 4406 4407 if (rtw89_sta_has_beamformer_cap(sta)) 4408 (*count)++; 4409 } 4410 4411 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 4412 struct ieee80211_sta *sta, bool disconnect) 4413 { 4414 struct rtw89_mac_bf_monitor_iter_data data; 4415 4416 data.rtwdev = rtwdev; 4417 data.down_sta = disconnect ? sta : NULL; 4418 data.count = 0; 4419 ieee80211_iterate_stations_atomic(rtwdev->hw, 4420 rtw89_mac_bf_monitor_calc_iter, 4421 &data); 4422 4423 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 4424 if (data.count) 4425 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 4426 else 4427 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 4428 } 4429 4430 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 4431 { 4432 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4433 struct rtw89_vif *rtwvif; 4434 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 4435 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 4436 4437 if (en == old) 4438 return; 4439 4440 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4441 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 4442 } 4443 4444 static int 4445 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 4446 u32 tx_time) 4447 { 4448 #define MAC_AX_DFLT_TX_TIME 5280 4449 u8 mac_idx = rtwsta->rtwvif->mac_idx; 4450 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 4451 u32 reg; 4452 int ret = 0; 4453 4454 if (rtwsta->cctl_tx_time) { 4455 rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 4456 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 4457 } else { 4458 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4459 if (ret) { 4460 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 4461 return ret; 4462 } 4463 4464 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 4465 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 4466 max_tx_time >> 5); 4467 } 4468 4469 return ret; 4470 } 4471 4472 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 4473 bool resume, u32 tx_time) 4474 { 4475 int ret = 0; 4476 4477 if (!resume) { 4478 rtwsta->cctl_tx_time = true; 4479 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 4480 } else { 4481 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 4482 rtwsta->cctl_tx_time = false; 4483 } 4484 4485 return ret; 4486 } 4487 4488 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 4489 u32 *tx_time) 4490 { 4491 u8 mac_idx = rtwsta->rtwvif->mac_idx; 4492 u32 reg; 4493 int ret = 0; 4494 4495 if (rtwsta->cctl_tx_time) { 4496 *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 4497 } else { 4498 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4499 if (ret) { 4500 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 4501 return ret; 4502 } 4503 4504 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 4505 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 4506 } 4507 4508 return ret; 4509 } 4510 4511 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 4512 struct rtw89_sta *rtwsta, 4513 bool resume, u8 tx_retry) 4514 { 4515 int ret = 0; 4516 4517 rtwsta->data_tx_cnt_lmt = tx_retry; 4518 4519 if (!resume) { 4520 rtwsta->cctl_tx_retry_limit = true; 4521 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 4522 } else { 4523 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 4524 rtwsta->cctl_tx_retry_limit = false; 4525 } 4526 4527 return ret; 4528 } 4529 4530 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 4531 struct rtw89_sta *rtwsta, u8 *tx_retry) 4532 { 4533 u8 mac_idx = rtwsta->rtwvif->mac_idx; 4534 u32 reg; 4535 int ret = 0; 4536 4537 if (rtwsta->cctl_tx_retry_limit) { 4538 *tx_retry = rtwsta->data_tx_cnt_lmt; 4539 } else { 4540 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4541 if (ret) { 4542 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 4543 return ret; 4544 } 4545 4546 reg = rtw89_mac_reg_by_idx(R_AX_TXCNT, mac_idx); 4547 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 4548 } 4549 4550 return ret; 4551 } 4552 4553 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 4554 struct rtw89_vif *rtwvif, bool en) 4555 { 4556 u8 mac_idx = rtwvif->mac_idx; 4557 u16 set = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0; 4558 u32 reg; 4559 u32 ret; 4560 4561 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4562 if (ret) 4563 return ret; 4564 4565 reg = rtw89_mac_reg_by_idx(R_AX_MUEDCA_EN, mac_idx); 4566 if (en) 4567 rtw89_write16_set(rtwdev, reg, set); 4568 else 4569 rtw89_write16_clr(rtwdev, reg, set); 4570 4571 return 0; 4572 } 4573 4574 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 4575 { 4576 u32 val32; 4577 int ret; 4578 4579 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 4580 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 4581 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 4582 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 4583 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 4584 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 4585 4586 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 4587 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 4588 if (ret) { 4589 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 4590 offset, val, mask); 4591 return ret; 4592 } 4593 4594 return 0; 4595 } 4596 EXPORT_SYMBOL(rtw89_mac_write_xtal_si); 4597 4598 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 4599 { 4600 u32 val32; 4601 int ret; 4602 4603 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 4604 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 4605 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 4606 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 4607 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 4608 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 4609 4610 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 4611 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 4612 if (ret) { 4613 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 4614 return ret; 4615 } 4616 4617 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 4618 4619 return 0; 4620 } 4621