1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "debug.h" 7 #include "fw.h" 8 #include "mac.h" 9 #include "ps.h" 10 #include "reg.h" 11 #include "util.h" 12 13 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, 14 enum rtw89_mac_hwmod_sel sel) 15 { 16 u32 val, r_val; 17 18 if (sel == RTW89_DMAC_SEL) { 19 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 20 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 21 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 22 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 23 val = B_AX_CMAC_EN; 24 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 25 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 26 val = B_AX_CMAC1_FEN; 27 } else { 28 return -EINVAL; 29 } 30 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 31 (val & r_val) != val) 32 return -EFAULT; 33 34 return 0; 35 } 36 37 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 38 { 39 u8 lte_ctrl; 40 int ret; 41 42 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 43 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 44 if (ret) 45 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 46 47 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 48 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 49 50 return ret; 51 } 52 53 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 54 { 55 u8 lte_ctrl; 56 int ret; 57 58 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 59 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 60 if (ret) 61 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 62 63 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 64 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 65 66 return ret; 67 } 68 69 static 70 int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 71 { 72 u32 ctrl_reg, data_reg, ctrl_data; 73 u32 val; 74 int ret; 75 76 switch (ctrl->type) { 77 case DLE_CTRL_TYPE_WDE: 78 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 79 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 80 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 81 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 82 B_AX_WDE_DFI_ACTIVE; 83 break; 84 case DLE_CTRL_TYPE_PLE: 85 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 86 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 87 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 88 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 89 B_AX_PLE_DFI_ACTIVE; 90 break; 91 default: 92 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 93 return -EINVAL; 94 } 95 96 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 97 98 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 99 1, 1000, false, rtwdev, ctrl_reg); 100 if (ret) { 101 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 102 ctrl_reg, ctrl_data); 103 return ret; 104 } 105 106 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 107 return 0; 108 } 109 110 static int dle_dfi_quota(struct rtw89_dev *rtwdev, 111 struct rtw89_mac_dle_dfi_quota *quota) 112 { 113 struct rtw89_mac_dle_dfi_ctrl ctrl; 114 int ret; 115 116 ctrl.type = quota->dle_type; 117 ctrl.target = DLE_DFI_TYPE_QUOTA; 118 ctrl.addr = quota->qtaid; 119 ret = dle_dfi_ctrl(rtwdev, &ctrl); 120 if (ret) { 121 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 122 return ret; 123 } 124 125 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 126 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 127 return 0; 128 } 129 130 static int dle_dfi_qempty(struct rtw89_dev *rtwdev, 131 struct rtw89_mac_dle_dfi_qempty *qempty) 132 { 133 struct rtw89_mac_dle_dfi_ctrl ctrl; 134 u32 ret; 135 136 ctrl.type = qempty->dle_type; 137 ctrl.target = DLE_DFI_TYPE_QEMPTY; 138 ctrl.addr = qempty->grpsel; 139 ret = dle_dfi_ctrl(rtwdev, &ctrl); 140 if (ret) { 141 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 142 return ret; 143 } 144 145 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 146 return 0; 147 } 148 149 static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev) 150 { 151 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 152 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 153 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 154 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 155 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 156 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 157 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 158 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 159 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 160 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 161 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 162 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 163 } 164 165 static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) 166 { 167 struct rtw89_mac_dle_dfi_qempty qempty; 168 struct rtw89_mac_dle_dfi_quota quota; 169 struct rtw89_mac_dle_dfi_ctrl ctrl; 170 u32 val, not_empty, i; 171 int ret; 172 173 qempty.dle_type = DLE_CTRL_TYPE_PLE; 174 qempty.grpsel = 0; 175 qempty.qempty = ~(u32)0; 176 ret = dle_dfi_qempty(rtwdev, &qempty); 177 if (ret) 178 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 179 else 180 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 181 182 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 183 if (!(not_empty & BIT(0))) 184 continue; 185 ctrl.type = DLE_CTRL_TYPE_PLE; 186 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 187 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 188 FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i); 189 ret = dle_dfi_ctrl(rtwdev, &ctrl); 190 if (ret) 191 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 192 else 193 rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i, 194 FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK, 195 ctrl.out_data)); 196 } 197 198 quota.dle_type = DLE_CTRL_TYPE_PLE; 199 quota.qtaid = 6; 200 ret = dle_dfi_quota(rtwdev, "a); 201 if (ret) 202 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 203 else 204 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 205 quota.rsv_pgnum, quota.use_pgnum); 206 207 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 208 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n", 209 FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val)); 210 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n", 211 FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val)); 212 213 dump_err_status_dispatcher(rtwdev); 214 } 215 216 static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 217 enum mac_ax_err_info err) 218 { 219 u32 dbg, event; 220 221 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 222 event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg); 223 224 switch (event) { 225 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 226 rtw89_info(rtwdev, "quota lost!\n"); 227 rtw89_mac_dump_qta_lost(rtwdev); 228 break; 229 default: 230 break; 231 } 232 } 233 234 static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev, 235 enum mac_ax_err_info err) 236 { 237 u32 dmac_err, cmac_err; 238 239 if (err != MAC_AX_ERR_L1_ERR_DMAC && 240 err != MAC_AX_ERR_L0_PROMOTE_TO_L1) 241 return; 242 243 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 244 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 245 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 246 247 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR); 248 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR =0x%08x\n", cmac_err); 249 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 250 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR =0x%08x\n", dmac_err); 251 252 if (dmac_err) { 253 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG =0x%08x ", 254 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG)); 255 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG =0x%08x\n", 256 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG)); 257 } 258 259 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 260 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR =0x%08x ", 261 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 262 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR =0x%08x\n", 263 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 264 } 265 266 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 267 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR =0x%08x\n", 268 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 269 rtw89_info(rtwdev, "SEC_local_Register 0x9D00 =0x%08x\n", 270 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 271 rtw89_info(rtwdev, "SEC_local_Register 0x9D04 =0x%08x\n", 272 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 273 rtw89_info(rtwdev, "SEC_local_Register 0x9D10 =0x%08x\n", 274 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 275 rtw89_info(rtwdev, "SEC_local_Register 0x9D14 =0x%08x\n", 276 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 277 rtw89_info(rtwdev, "SEC_local_Register 0x9D18 =0x%08x\n", 278 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 279 rtw89_info(rtwdev, "SEC_local_Register 0x9D20 =0x%08x\n", 280 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 281 rtw89_info(rtwdev, "SEC_local_Register 0x9D24 =0x%08x\n", 282 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 283 rtw89_info(rtwdev, "SEC_local_Register 0x9D28 =0x%08x\n", 284 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 285 rtw89_info(rtwdev, "SEC_local_Register 0x9D2C =0x%08x\n", 286 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 287 } 288 289 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 290 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR =0x%08x ", 291 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 292 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR =0x%08x\n", 293 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 294 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR =0x%08x ", 295 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 296 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR =0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 298 } 299 300 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 301 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR =0x%08x ", 302 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 303 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR= 0x%08x\n", 304 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 305 } 306 307 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 308 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ", 309 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 310 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 311 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 312 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ", 313 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 314 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 315 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 316 dump_err_status_dispatcher(rtwdev); 317 } 318 319 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 320 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 321 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 322 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 323 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 324 } 325 326 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 327 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ", 328 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 329 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 330 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 331 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ", 332 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 333 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 334 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 335 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 336 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 337 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 338 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 339 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 340 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 341 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 343 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 344 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 345 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 346 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 347 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 348 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 349 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 350 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 351 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 352 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 353 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 354 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 355 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 356 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 357 dump_err_status_dispatcher(rtwdev); 358 } 359 360 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 361 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ", 362 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 363 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n", 364 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 365 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ", 366 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 367 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n", 368 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 369 } 370 371 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) 372 dump_err_status_dispatcher(rtwdev); 373 374 if (dmac_err & B_AX_DLE_CPUIO_ERR_FLAG) { 375 rtw89_info(rtwdev, "R_AX_CPUIO_ERR_IMR=0x%08x ", 376 rtw89_read32(rtwdev, R_AX_CPUIO_ERR_IMR)); 377 rtw89_info(rtwdev, "R_AX_CPUIO_ERR_ISR=0x%08x\n", 378 rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR)); 379 } 380 381 if (dmac_err & BIT(11)) { 382 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 383 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 384 } 385 386 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 387 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR=0x%08x ", 388 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR)); 389 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR=0x%04x\n", 390 rtw89_read16(rtwdev, R_AX_SCHEDULE_ERR_ISR)); 391 } 392 393 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 394 rtw89_info(rtwdev, "R_AX_PTCL_IMR0=0x%08x ", 395 rtw89_read32(rtwdev, R_AX_PTCL_IMR0)); 396 rtw89_info(rtwdev, "R_AX_PTCL_ISR0=0x%08x\n", 397 rtw89_read32(rtwdev, R_AX_PTCL_ISR0)); 398 } 399 400 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 401 rtw89_info(rtwdev, "R_AX_DLE_CTRL=0x%08x\n", 402 rtw89_read32(rtwdev, R_AX_DLE_CTRL)); 403 } 404 405 if (cmac_err & B_AX_PHYINTF_ERR_IND) { 406 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR=0x%08x\n", 407 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR)); 408 } 409 410 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 411 rtw89_info(rtwdev, "R_AX_TXPWR_IMR=0x%08x ", 412 rtw89_read32(rtwdev, R_AX_TXPWR_IMR)); 413 rtw89_info(rtwdev, "R_AX_TXPWR_ISR=0x%08x\n", 414 rtw89_read32(rtwdev, R_AX_TXPWR_ISR)); 415 } 416 417 if (cmac_err & B_AX_WMAC_RX_ERR_IND) { 418 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x ", 419 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL)); 420 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR=0x%08x\n", 421 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR)); 422 } 423 424 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 425 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR=0x%08x ", 426 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR)); 427 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x\n", 428 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL)); 429 } 430 431 rtwdev->hci.ops->dump_err_status(rtwdev); 432 433 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 434 rtw89_mac_dump_l0_to_l1(rtwdev, err); 435 436 rtw89_info(rtwdev, "<---\n"); 437 } 438 439 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 440 { 441 u32 err; 442 int ret; 443 444 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 445 false, rtwdev, R_AX_HALT_C2H_CTRL); 446 if (ret) { 447 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 448 return ret; 449 } 450 451 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 452 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 453 454 rtw89_fw_st_dbg_dump(rtwdev); 455 rtw89_mac_dump_err_status(rtwdev, err); 456 457 return err; 458 } 459 EXPORT_SYMBOL(rtw89_mac_get_err_status); 460 461 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 462 { 463 u32 halt; 464 int ret = 0; 465 466 if (err > MAC_AX_SET_ERR_MAX) { 467 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 468 return -EINVAL; 469 } 470 471 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 472 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 473 if (ret) { 474 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 475 return -EFAULT; 476 } 477 478 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 479 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 480 481 return 0; 482 } 483 EXPORT_SYMBOL(rtw89_mac_set_err_status); 484 485 const struct rtw89_hfc_prec_cfg rtw89_hfc_preccfg_pcie = { 486 2, 40, 0, 0, 1, 0, 0, 0 487 }; 488 EXPORT_SYMBOL(rtw89_hfc_preccfg_pcie); 489 490 static int hfc_reset_param(struct rtw89_dev *rtwdev) 491 { 492 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 493 struct rtw89_hfc_param_ini param_ini = {NULL}; 494 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 495 496 switch (rtwdev->hci.type) { 497 case RTW89_HCI_TYPE_PCIE: 498 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 499 param->en = 0; 500 break; 501 default: 502 return -EINVAL; 503 } 504 505 if (param_ini.pub_cfg) 506 param->pub_cfg = *param_ini.pub_cfg; 507 508 if (param_ini.prec_cfg) { 509 param->prec_cfg = *param_ini.prec_cfg; 510 rtwdev->hal.sw_amsdu_max_size = 511 param->prec_cfg.wp_ch07_prec * HFC_PAGE_UNIT; 512 } 513 514 if (param_ini.ch_cfg) 515 param->ch_cfg = param_ini.ch_cfg; 516 517 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 518 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 519 param->mode = param_ini.mode; 520 521 return 0; 522 } 523 524 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 525 { 526 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 527 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 528 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 529 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 530 531 if (ch >= RTW89_DMA_CH_NUM) 532 return -EINVAL; 533 534 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 535 ch_cfg[ch].max > pub_cfg->pub_max) 536 return -EINVAL; 537 if (ch_cfg[ch].grp >= grp_num) 538 return -EINVAL; 539 540 return 0; 541 } 542 543 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 544 { 545 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 546 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 547 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 548 549 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 550 if (rtwdev->chip->chip_id == RTL8852A) 551 return 0; 552 else 553 return -EFAULT; 554 } 555 556 return 0; 557 } 558 559 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 560 { 561 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 562 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 563 564 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 565 return -EFAULT; 566 567 return 0; 568 } 569 570 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 571 { 572 const struct rtw89_chip_info *chip = rtwdev->chip; 573 const struct rtw89_page_regs *regs = chip->page_regs; 574 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 575 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 576 int ret = 0; 577 u32 val = 0; 578 579 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 580 if (ret) 581 return ret; 582 583 ret = hfc_ch_cfg_chk(rtwdev, ch); 584 if (ret) 585 return ret; 586 587 if (ch > RTW89_DMA_B1HI) 588 return -EINVAL; 589 590 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 591 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 592 (cfg[ch].grp ? B_AX_GRP : 0); 593 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 594 595 return 0; 596 } 597 598 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 599 { 600 const struct rtw89_chip_info *chip = rtwdev->chip; 601 const struct rtw89_page_regs *regs = chip->page_regs; 602 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 603 struct rtw89_hfc_ch_info *info = param->ch_info; 604 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 605 u32 val; 606 u32 ret; 607 608 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 609 if (ret) 610 return ret; 611 612 if (ch > RTW89_DMA_H2C) 613 return -EINVAL; 614 615 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 616 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 617 if (ch < RTW89_DMA_H2C) 618 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 619 else 620 info[ch].used = cfg[ch].min - info[ch].aval; 621 622 return 0; 623 } 624 625 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 626 { 627 const struct rtw89_chip_info *chip = rtwdev->chip; 628 const struct rtw89_page_regs *regs = chip->page_regs; 629 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 630 u32 val; 631 int ret; 632 633 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 634 if (ret) 635 return ret; 636 637 ret = hfc_pub_cfg_chk(rtwdev); 638 if (ret) 639 return ret; 640 641 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 642 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 643 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 644 645 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 646 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 647 648 return 0; 649 } 650 651 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 652 { 653 const struct rtw89_chip_info *chip = rtwdev->chip; 654 const struct rtw89_page_regs *regs = chip->page_regs; 655 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 656 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 657 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 658 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 659 u32 val; 660 int ret; 661 662 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 663 if (ret) 664 return ret; 665 666 val = rtw89_read32(rtwdev, regs->pub_page_info1); 667 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 668 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 669 val = rtw89_read32(rtwdev, regs->pub_page_info3); 670 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 671 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 672 info->pub_aval = 673 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 674 B_AX_PUB_AVAL_PG_MASK); 675 info->wp_aval = 676 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 677 B_AX_WP_AVAL_PG_MASK); 678 679 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 680 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 681 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 682 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 683 prec_cfg->ch011_full_cond = 684 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 685 prec_cfg->h2c_full_cond = 686 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 687 prec_cfg->wp_ch07_full_cond = 688 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 689 prec_cfg->wp_ch811_full_cond = 690 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 691 692 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 693 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 694 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 695 696 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 697 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 698 699 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 700 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 701 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 702 703 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 704 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 705 706 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 707 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 708 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 709 710 ret = hfc_pub_info_chk(rtwdev); 711 if (param->en && ret) 712 return ret; 713 714 return 0; 715 } 716 717 static void hfc_h2c_cfg(struct rtw89_dev *rtwdev) 718 { 719 const struct rtw89_chip_info *chip = rtwdev->chip; 720 const struct rtw89_page_regs *regs = chip->page_regs; 721 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 722 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 723 u32 val; 724 725 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 726 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 727 728 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 729 B_AX_HCI_FC_CH12_FULL_COND_MASK, 730 prec_cfg->h2c_full_cond); 731 } 732 733 static void hfc_mix_cfg(struct rtw89_dev *rtwdev) 734 { 735 const struct rtw89_chip_info *chip = rtwdev->chip; 736 const struct rtw89_page_regs *regs = chip->page_regs; 737 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 738 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 739 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 740 u32 val; 741 742 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 743 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 744 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 745 746 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 747 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 748 749 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 750 B_AX_PREC_PAGE_WP_CH07_MASK) | 751 u32_encode_bits(prec_cfg->wp_ch811_prec, 752 B_AX_PREC_PAGE_WP_CH811_MASK); 753 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 754 755 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 756 param->mode, B_AX_HCI_FC_MODE_MASK); 757 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 758 B_AX_HCI_FC_WD_FULL_COND_MASK); 759 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 760 B_AX_HCI_FC_CH12_FULL_COND_MASK); 761 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 762 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 763 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 764 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 765 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 766 } 767 768 static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 769 { 770 const struct rtw89_chip_info *chip = rtwdev->chip; 771 const struct rtw89_page_regs *regs = chip->page_regs; 772 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 773 u32 val; 774 775 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 776 param->en = en; 777 param->h2c_en = h2c_en; 778 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 779 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 780 (val & ~B_AX_HCI_FC_CH12_EN); 781 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 782 } 783 784 static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 785 { 786 u8 ch; 787 u32 ret = 0; 788 789 if (reset) 790 ret = hfc_reset_param(rtwdev); 791 if (ret) 792 return ret; 793 794 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 795 if (ret) 796 return ret; 797 798 hfc_func_en(rtwdev, false, false); 799 800 if (!en && h2c_en) { 801 hfc_h2c_cfg(rtwdev); 802 hfc_func_en(rtwdev, en, h2c_en); 803 return ret; 804 } 805 806 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 807 ret = hfc_ch_ctrl(rtwdev, ch); 808 if (ret) 809 return ret; 810 } 811 812 ret = hfc_pub_ctrl(rtwdev); 813 if (ret) 814 return ret; 815 816 hfc_mix_cfg(rtwdev); 817 if (en || h2c_en) { 818 hfc_func_en(rtwdev, en, h2c_en); 819 udelay(10); 820 } 821 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 822 ret = hfc_upd_ch_info(rtwdev, ch); 823 if (ret) 824 return ret; 825 } 826 ret = hfc_upd_mix_info(rtwdev); 827 828 return ret; 829 } 830 831 #define PWR_POLL_CNT 2000 832 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 833 const struct rtw89_pwr_cfg *cfg) 834 { 835 u8 val = 0; 836 int ret; 837 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 838 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 839 840 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 841 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 842 843 if (!ret) 844 return 0; 845 846 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 847 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 848 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 849 850 return -EBUSY; 851 } 852 853 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 854 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 855 { 856 const struct rtw89_pwr_cfg *cur_cfg; 857 u32 addr; 858 u8 val; 859 860 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 861 if (!(cur_cfg->intf_msk & intf_msk) || 862 !(cur_cfg->cv_msk & cv_msk)) 863 continue; 864 865 switch (cur_cfg->cmd) { 866 case PWR_CMD_WRITE: 867 addr = cur_cfg->addr; 868 869 if (cur_cfg->base == PWR_BASE_SDIO) 870 addr |= SDIO_LOCAL_BASE_ADDR; 871 872 val = rtw89_read8(rtwdev, addr); 873 val &= ~(cur_cfg->msk); 874 val |= (cur_cfg->val & cur_cfg->msk); 875 876 rtw89_write8(rtwdev, addr, val); 877 break; 878 case PWR_CMD_POLL: 879 if (pwr_cmd_poll(rtwdev, cur_cfg)) 880 return -EBUSY; 881 break; 882 case PWR_CMD_DELAY: 883 if (cur_cfg->val == PWR_DELAY_US) 884 udelay(cur_cfg->addr); 885 else 886 fsleep(cur_cfg->addr * 1000); 887 break; 888 default: 889 return -EINVAL; 890 } 891 } 892 893 return 0; 894 } 895 896 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 897 const struct rtw89_pwr_cfg * const *cfg_seq) 898 { 899 int ret; 900 901 for (; *cfg_seq; cfg_seq++) { 902 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 903 PWR_INTF_MSK_PCIE, *cfg_seq); 904 if (ret) 905 return -EBUSY; 906 } 907 908 return 0; 909 } 910 911 static enum rtw89_rpwm_req_pwr_state 912 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 913 { 914 enum rtw89_rpwm_req_pwr_state state; 915 916 switch (rtwdev->ps_mode) { 917 case RTW89_PS_MODE_RFOFF: 918 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 919 break; 920 case RTW89_PS_MODE_CLK_GATED: 921 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 922 break; 923 case RTW89_PS_MODE_PWR_GATED: 924 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 925 break; 926 default: 927 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 928 break; 929 } 930 return state; 931 } 932 933 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 934 enum rtw89_rpwm_req_pwr_state req_pwr_state, 935 bool notify_wake) 936 { 937 u16 request; 938 939 spin_lock_bh(&rtwdev->rpwm_lock); 940 941 request = rtw89_read16(rtwdev, R_AX_RPWM); 942 request ^= request | PS_RPWM_TOGGLE; 943 request |= req_pwr_state; 944 945 if (notify_wake) { 946 request |= PS_RPWM_NOTIFY_WAKE; 947 } else { 948 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 949 RPWM_SEQ_NUM_MAX; 950 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 951 rtwdev->mac.rpwm_seq_num); 952 953 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 954 request |= PS_RPWM_ACK; 955 } 956 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 957 958 spin_unlock_bh(&rtwdev->rpwm_lock); 959 } 960 961 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 962 enum rtw89_rpwm_req_pwr_state req_pwr_state) 963 { 964 bool request_deep_mode; 965 bool in_deep_mode; 966 u8 rpwm_req_num; 967 u8 cpwm_rsp_seq; 968 u8 cpwm_seq; 969 u8 cpwm_status; 970 971 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 972 request_deep_mode = true; 973 else 974 request_deep_mode = false; 975 976 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 977 in_deep_mode = true; 978 else 979 in_deep_mode = false; 980 981 if (request_deep_mode != in_deep_mode) 982 return -EPERM; 983 984 if (request_deep_mode) 985 return 0; 986 987 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 988 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, R_AX_CPWM, 989 PS_CPWM_RSP_SEQ_NUM); 990 991 if (rpwm_req_num != cpwm_rsp_seq) 992 return -EPERM; 993 994 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 995 CPWM_SEQ_NUM_MAX; 996 997 cpwm_seq = rtw89_read16_mask(rtwdev, R_AX_CPWM, PS_CPWM_SEQ_NUM); 998 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 999 return -EPERM; 1000 1001 cpwm_status = rtw89_read16_mask(rtwdev, R_AX_CPWM, PS_CPWM_STATE); 1002 if (cpwm_status != req_pwr_state) 1003 return -EPERM; 1004 1005 return 0; 1006 } 1007 1008 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1009 { 1010 enum rtw89_rpwm_req_pwr_state state; 1011 int ret; 1012 1013 if (enter) 1014 state = rtw89_mac_get_req_pwr_state(rtwdev); 1015 else 1016 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1017 1018 rtw89_mac_send_rpwm(rtwdev, state, false); 1019 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, !ret, 1020 1000, 15000, false, rtwdev, state); 1021 if (ret) 1022 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1023 enter ? "entering" : "leaving"); 1024 } 1025 1026 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1027 { 1028 enum rtw89_rpwm_req_pwr_state state; 1029 1030 state = rtw89_mac_get_req_pwr_state(rtwdev); 1031 rtw89_mac_send_rpwm(rtwdev, state, true); 1032 } 1033 1034 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1035 { 1036 #define PWR_ACT 1 1037 const struct rtw89_chip_info *chip = rtwdev->chip; 1038 const struct rtw89_pwr_cfg * const *cfg_seq; 1039 int (*cfg_func)(struct rtw89_dev *rtwdev); 1040 struct rtw89_hal *hal = &rtwdev->hal; 1041 int ret; 1042 u8 val; 1043 1044 if (on) { 1045 cfg_seq = chip->pwr_on_seq; 1046 cfg_func = chip->ops->pwr_on_func; 1047 } else { 1048 cfg_seq = chip->pwr_off_seq; 1049 cfg_func = chip->ops->pwr_off_func; 1050 } 1051 1052 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1053 __rtw89_leave_ps_mode(rtwdev); 1054 1055 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1056 if (on && val == PWR_ACT) { 1057 rtw89_err(rtwdev, "MAC has already powered on\n"); 1058 return -EBUSY; 1059 } 1060 1061 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1062 if (ret) 1063 return ret; 1064 1065 if (on) { 1066 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1067 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1068 } else { 1069 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1070 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1071 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1072 hal->current_channel = 0; 1073 } 1074 1075 return 0; 1076 #undef PWR_ACT 1077 } 1078 1079 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1080 { 1081 rtw89_mac_power_switch(rtwdev, false); 1082 } 1083 1084 static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1085 { 1086 u32 func_en = 0; 1087 u32 ck_en = 0; 1088 u32 c1pc_en = 0; 1089 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1090 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1091 1092 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1093 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1094 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN; 1095 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1096 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1097 B_AX_RMAC_CKEN; 1098 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1099 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1100 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1101 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1102 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1103 1104 if (en) { 1105 if (mac_idx == RTW89_MAC_1) { 1106 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1107 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1108 B_AX_R_SYM_ISO_CMAC12PP); 1109 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1110 B_AX_CMAC1_FEN); 1111 } 1112 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1113 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1114 } else { 1115 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1116 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1117 if (mac_idx == RTW89_MAC_1) { 1118 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1119 B_AX_CMAC1_FEN); 1120 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1121 B_AX_R_SYM_ISO_CMAC12PP); 1122 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1123 } 1124 } 1125 1126 return 0; 1127 } 1128 1129 static int dmac_func_en(struct rtw89_dev *rtwdev) 1130 { 1131 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1132 u32 val32; 1133 1134 if (chip_id == RTL8852C) 1135 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1136 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1137 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1138 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1139 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1140 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1141 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1142 else 1143 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1144 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1145 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1146 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1147 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1148 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1149 B_AX_DMAC_CRPRT); 1150 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1151 1152 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1153 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1154 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1155 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1156 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1157 1158 return 0; 1159 } 1160 1161 static int chip_func_en(struct rtw89_dev *rtwdev) 1162 { 1163 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1164 1165 if (chip_id == RTL8852A) 1166 rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL0, 1167 B_AX_OCP_L1_MASK); 1168 1169 return 0; 1170 } 1171 1172 static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev) 1173 { 1174 int ret; 1175 1176 ret = dmac_func_en(rtwdev); 1177 if (ret) 1178 return ret; 1179 1180 ret = cmac_func_en(rtwdev, 0, true); 1181 if (ret) 1182 return ret; 1183 1184 ret = chip_func_en(rtwdev); 1185 if (ret) 1186 return ret; 1187 1188 return ret; 1189 } 1190 1191 /* PCIE 64 */ 1192 const struct rtw89_dle_size rtw89_wde_size0 = { 1193 RTW89_WDE_PG_64, 4095, 1, 1194 }; 1195 EXPORT_SYMBOL(rtw89_wde_size0); 1196 1197 /* DLFW */ 1198 const struct rtw89_dle_size rtw89_wde_size4 = { 1199 RTW89_WDE_PG_64, 0, 4096, 1200 }; 1201 EXPORT_SYMBOL(rtw89_wde_size4); 1202 1203 /* 8852C DLFW */ 1204 const struct rtw89_dle_size rtw89_wde_size18 = { 1205 RTW89_WDE_PG_64, 0, 2048, 1206 }; 1207 EXPORT_SYMBOL(rtw89_wde_size18); 1208 1209 /* 8852C PCIE SCC */ 1210 const struct rtw89_dle_size rtw89_wde_size19 = { 1211 RTW89_WDE_PG_64, 3328, 0, 1212 }; 1213 EXPORT_SYMBOL(rtw89_wde_size19); 1214 1215 /* PCIE */ 1216 const struct rtw89_dle_size rtw89_ple_size0 = { 1217 RTW89_PLE_PG_128, 1520, 16, 1218 }; 1219 EXPORT_SYMBOL(rtw89_ple_size0); 1220 1221 /* DLFW */ 1222 const struct rtw89_dle_size rtw89_ple_size4 = { 1223 RTW89_PLE_PG_128, 64, 1472, 1224 }; 1225 EXPORT_SYMBOL(rtw89_ple_size4); 1226 1227 /* 8852C DLFW */ 1228 const struct rtw89_dle_size rtw89_ple_size18 = { 1229 RTW89_PLE_PG_128, 2544, 16, 1230 }; 1231 EXPORT_SYMBOL(rtw89_ple_size18); 1232 1233 /* 8852C PCIE SCC */ 1234 const struct rtw89_dle_size rtw89_ple_size19 = { 1235 RTW89_PLE_PG_128, 1904, 16, 1236 }; 1237 EXPORT_SYMBOL(rtw89_ple_size19); 1238 1239 /* PCIE 64 */ 1240 const struct rtw89_wde_quota rtw89_wde_qt0 = { 1241 3792, 196, 0, 107, 1242 }; 1243 EXPORT_SYMBOL(rtw89_wde_qt0); 1244 1245 /* DLFW */ 1246 const struct rtw89_wde_quota rtw89_wde_qt4 = { 1247 0, 0, 0, 0, 1248 }; 1249 EXPORT_SYMBOL(rtw89_wde_qt4); 1250 1251 /* 8852C DLFW */ 1252 const struct rtw89_wde_quota rtw89_wde_qt17 = { 1253 0, 0, 0, 0, 1254 }; 1255 EXPORT_SYMBOL(rtw89_wde_qt17); 1256 1257 /* 8852C PCIE SCC */ 1258 const struct rtw89_wde_quota rtw89_wde_qt18 = { 1259 3228, 60, 0, 40, 1260 }; 1261 EXPORT_SYMBOL(rtw89_wde_qt18); 1262 1263 /* PCIE SCC */ 1264 const struct rtw89_ple_quota rtw89_ple_qt4 = { 1265 264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8, 1266 }; 1267 EXPORT_SYMBOL(rtw89_ple_qt4); 1268 1269 /* PCIE SCC */ 1270 const struct rtw89_ple_quota rtw89_ple_qt5 = { 1271 264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120, 1272 }; 1273 EXPORT_SYMBOL(rtw89_ple_qt5); 1274 1275 /* DLFW */ 1276 const struct rtw89_ple_quota rtw89_ple_qt13 = { 1277 0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0 1278 }; 1279 EXPORT_SYMBOL(rtw89_ple_qt13); 1280 1281 /* DLFW 52C */ 1282 const struct rtw89_ple_quota rtw89_ple_qt44 = { 1283 0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0, 1284 }; 1285 EXPORT_SYMBOL(rtw89_ple_qt44); 1286 1287 /* DLFW 52C */ 1288 const struct rtw89_ple_quota rtw89_ple_qt45 = { 1289 0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0, 1290 }; 1291 EXPORT_SYMBOL(rtw89_ple_qt45); 1292 1293 /* 8852C PCIE SCC */ 1294 const struct rtw89_ple_quota rtw89_ple_qt46 = { 1295 525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16, 1296 }; 1297 EXPORT_SYMBOL(rtw89_ple_qt46); 1298 1299 /* 8852C PCIE SCC */ 1300 const struct rtw89_ple_quota rtw89_ple_qt47 = { 1301 525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037, 1302 }; 1303 EXPORT_SYMBOL(rtw89_ple_qt47); 1304 1305 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1306 enum rtw89_qta_mode mode) 1307 { 1308 struct rtw89_mac_info *mac = &rtwdev->mac; 1309 const struct rtw89_dle_mem *cfg; 1310 1311 cfg = &rtwdev->chip->dle_mem[mode]; 1312 if (!cfg) 1313 return NULL; 1314 1315 if (cfg->mode != mode) { 1316 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1317 return NULL; 1318 } 1319 1320 mac->dle_info.wde_pg_size = cfg->wde_size->pge_size; 1321 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1322 mac->dle_info.qta_mode = mode; 1323 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1324 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1325 1326 return cfg; 1327 } 1328 1329 static inline u32 dle_used_size(const struct rtw89_dle_size *wde, 1330 const struct rtw89_dle_size *ple) 1331 { 1332 return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1333 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1334 } 1335 1336 static void dle_func_en(struct rtw89_dev *rtwdev, bool enable) 1337 { 1338 if (enable) 1339 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1340 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1341 else 1342 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1343 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1344 } 1345 1346 static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable) 1347 { 1348 if (enable) 1349 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, 1350 B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); 1351 else 1352 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, 1353 B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); 1354 } 1355 1356 static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1357 { 1358 const struct rtw89_dle_size *size_cfg; 1359 u32 val; 1360 u8 bound = 0; 1361 1362 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1363 size_cfg = cfg->wde_size; 1364 1365 switch (size_cfg->pge_size) { 1366 default: 1367 case RTW89_WDE_PG_64: 1368 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1369 B_AX_WDE_PAGE_SEL_MASK); 1370 break; 1371 case RTW89_WDE_PG_128: 1372 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1373 B_AX_WDE_PAGE_SEL_MASK); 1374 break; 1375 case RTW89_WDE_PG_256: 1376 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1377 return -EINVAL; 1378 } 1379 1380 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1381 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1382 B_AX_WDE_FREE_PAGE_NUM_MASK); 1383 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1384 1385 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1386 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1387 * size_cfg->pge_size / DLE_BOUND_UNIT; 1388 size_cfg = cfg->ple_size; 1389 1390 switch (size_cfg->pge_size) { 1391 default: 1392 case RTW89_PLE_PG_64: 1393 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1394 return -EINVAL; 1395 case RTW89_PLE_PG_128: 1396 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1397 B_AX_PLE_PAGE_SEL_MASK); 1398 break; 1399 case RTW89_PLE_PG_256: 1400 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1401 B_AX_PLE_PAGE_SEL_MASK); 1402 break; 1403 } 1404 1405 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1406 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1407 B_AX_PLE_FREE_PAGE_NUM_MASK); 1408 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1409 1410 return 0; 1411 } 1412 1413 #define INVALID_QT_WCPU U16_MAX 1414 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1415 do { \ 1416 val = ((_min_x) & \ 1417 B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1418 (((_max_x) << 16) & \ 1419 B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1420 rtw89_write32(rtwdev, \ 1421 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1422 val); \ 1423 } while (0) 1424 #define SET_QUOTA(_x, _module, _idx) \ 1425 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1426 1427 static void wde_quota_cfg(struct rtw89_dev *rtwdev, 1428 const struct rtw89_wde_quota *min_cfg, 1429 const struct rtw89_wde_quota *max_cfg, 1430 u16 ext_wde_min_qt_wcpu) 1431 { 1432 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1433 ext_wde_min_qt_wcpu : min_cfg->wcpu; 1434 u32 val; 1435 1436 SET_QUOTA(hif, WDE, 0); 1437 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1438 SET_QUOTA(pkt_in, WDE, 3); 1439 SET_QUOTA(cpu_io, WDE, 4); 1440 } 1441 1442 static void ple_quota_cfg(struct rtw89_dev *rtwdev, 1443 const struct rtw89_ple_quota *min_cfg, 1444 const struct rtw89_ple_quota *max_cfg) 1445 { 1446 u32 val; 1447 1448 SET_QUOTA(cma0_tx, PLE, 0); 1449 SET_QUOTA(cma1_tx, PLE, 1); 1450 SET_QUOTA(c2h, PLE, 2); 1451 SET_QUOTA(h2c, PLE, 3); 1452 SET_QUOTA(wcpu, PLE, 4); 1453 SET_QUOTA(mpdu_proc, PLE, 5); 1454 SET_QUOTA(cma0_dma, PLE, 6); 1455 SET_QUOTA(cma1_dma, PLE, 7); 1456 SET_QUOTA(bb_rpt, PLE, 8); 1457 SET_QUOTA(wd_rel, PLE, 9); 1458 SET_QUOTA(cpu_io, PLE, 10); 1459 if (rtwdev->chip->chip_id == RTL8852C) 1460 SET_QUOTA(tx_rpt, PLE, 11); 1461 } 1462 1463 #undef SET_QUOTA 1464 1465 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 1466 const struct rtw89_dle_mem *cfg, 1467 u16 ext_wde_min_qt_wcpu) 1468 { 1469 wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 1470 ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 1471 } 1472 1473 static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1474 enum rtw89_qta_mode ext_mode) 1475 { 1476 const struct rtw89_dle_mem *cfg, *ext_cfg; 1477 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 1478 int ret = 0; 1479 u32 ini; 1480 1481 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1482 if (ret) 1483 return ret; 1484 1485 cfg = get_dle_mem_cfg(rtwdev, mode); 1486 if (!cfg) { 1487 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1488 ret = -EINVAL; 1489 goto error; 1490 } 1491 1492 if (mode == RTW89_QTA_DLFW) { 1493 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 1494 if (!ext_cfg) { 1495 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 1496 ext_mode); 1497 ret = -EINVAL; 1498 goto error; 1499 } 1500 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 1501 } 1502 1503 if (dle_used_size(cfg->wde_size, cfg->ple_size) != rtwdev->chip->fifo_size) { 1504 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 1505 ret = -EINVAL; 1506 goto error; 1507 } 1508 1509 dle_func_en(rtwdev, false); 1510 dle_clk_en(rtwdev, true); 1511 1512 ret = dle_mix_cfg(rtwdev, cfg); 1513 if (ret) { 1514 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 1515 goto error; 1516 } 1517 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 1518 1519 dle_func_en(rtwdev, true); 1520 1521 ret = read_poll_timeout(rtw89_read32, ini, 1522 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1523 2000, false, rtwdev, R_AX_WDE_INI_STATUS); 1524 if (ret) { 1525 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 1526 return ret; 1527 } 1528 1529 ret = read_poll_timeout(rtw89_read32, ini, 1530 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1531 2000, false, rtwdev, R_AX_PLE_INI_STATUS); 1532 if (ret) { 1533 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 1534 return ret; 1535 } 1536 1537 return 0; 1538 error: 1539 dle_func_en(rtwdev, false); 1540 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 1541 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 1542 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 1543 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 1544 1545 return ret; 1546 } 1547 1548 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1549 enum rtw89_qta_mode mode) 1550 { 1551 u32 reg, max_preld_size, min_rsvd_size; 1552 1553 max_preld_size = (mac_idx == RTW89_MAC_0 ? 1554 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 1555 reg = mac_idx == RTW89_MAC_0 ? 1556 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 1557 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 1558 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 1559 1560 min_rsvd_size = PRELD_AMSDU_SIZE; 1561 reg = mac_idx == RTW89_MAC_0 ? 1562 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 1563 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 1564 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 1565 1566 return 0; 1567 } 1568 1569 static bool is_qta_poh(struct rtw89_dev *rtwdev) 1570 { 1571 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 1572 } 1573 1574 static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1575 enum rtw89_qta_mode mode) 1576 { 1577 const struct rtw89_chip_info *chip = rtwdev->chip; 1578 1579 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || !is_qta_poh(rtwdev)) 1580 return 0; 1581 1582 return preload_init_set(rtwdev, mac_idx, mode); 1583 } 1584 1585 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 1586 { 1587 u32 msk32; 1588 u32 val32; 1589 1590 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 1591 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 1592 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 1593 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1594 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 1595 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 1596 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 1597 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 1598 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1599 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 1600 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1601 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1602 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 1603 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1604 1605 if ((val32 & msk32) == msk32) 1606 return true; 1607 1608 return false; 1609 } 1610 1611 static int sta_sch_init(struct rtw89_dev *rtwdev) 1612 { 1613 u32 p_val; 1614 u8 val; 1615 int ret; 1616 1617 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1618 if (ret) 1619 return ret; 1620 1621 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 1622 val |= B_AX_SS_EN; 1623 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 1624 1625 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 1626 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 1627 if (ret) { 1628 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 1629 return ret; 1630 } 1631 1632 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 1633 1634 return 0; 1635 } 1636 1637 static int mpdu_proc_init(struct rtw89_dev *rtwdev) 1638 { 1639 int ret; 1640 1641 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1642 if (ret) 1643 return ret; 1644 1645 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 1646 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 1647 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 1648 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 1649 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 1650 1651 return 0; 1652 } 1653 1654 static int sec_eng_init(struct rtw89_dev *rtwdev) 1655 { 1656 u32 val = 0; 1657 int ret; 1658 1659 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1660 if (ret) 1661 return ret; 1662 1663 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 1664 /* init clock */ 1665 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 1666 /* init TX encryption */ 1667 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 1668 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 1669 val &= ~B_AX_TX_PARTIAL_MODE; 1670 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 1671 1672 /* init MIC ICV append */ 1673 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 1674 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 1675 1676 /* option init */ 1677 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 1678 1679 return 0; 1680 } 1681 1682 static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1683 { 1684 int ret; 1685 1686 ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 1687 if (ret) { 1688 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 1689 return ret; 1690 } 1691 1692 ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 1693 if (ret) { 1694 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 1695 return ret; 1696 } 1697 1698 ret = hfc_init(rtwdev, true, true, true); 1699 if (ret) { 1700 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 1701 return ret; 1702 } 1703 1704 ret = sta_sch_init(rtwdev); 1705 if (ret) { 1706 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 1707 return ret; 1708 } 1709 1710 ret = mpdu_proc_init(rtwdev); 1711 if (ret) { 1712 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 1713 return ret; 1714 } 1715 1716 ret = sec_eng_init(rtwdev); 1717 if (ret) { 1718 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 1719 return ret; 1720 } 1721 1722 return ret; 1723 } 1724 1725 static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1726 { 1727 u32 val, reg; 1728 u16 p_val; 1729 int ret; 1730 1731 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1732 if (ret) 1733 return ret; 1734 1735 reg = rtw89_mac_reg_by_idx(R_AX_ADDR_CAM_CTRL, mac_idx); 1736 1737 val = rtw89_read32(rtwdev, reg); 1738 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 1739 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 1740 rtw89_write32(rtwdev, reg, val); 1741 1742 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 1743 1, TRXCFG_WAIT_CNT, false, rtwdev, B_AX_ADDR_CAM_CLR); 1744 if (ret) { 1745 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 1746 return ret; 1747 } 1748 1749 return 0; 1750 } 1751 1752 static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1753 { 1754 u32 ret; 1755 u32 reg; 1756 1757 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1758 if (ret) 1759 return ret; 1760 1761 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_0, mac_idx); 1762 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, SCH_PREBKF_24US); 1763 1764 return 0; 1765 } 1766 1767 static int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, 1768 enum rtw89_machdr_frame_type type, 1769 enum rtw89_mac_fwd_target fwd_target, 1770 u8 mac_idx) 1771 { 1772 u32 reg; 1773 u32 val; 1774 1775 switch (fwd_target) { 1776 case RTW89_FWD_DONT_CARE: 1777 val = RX_FLTR_FRAME_DROP; 1778 break; 1779 case RTW89_FWD_TO_HOST: 1780 val = RX_FLTR_FRAME_TO_HOST; 1781 break; 1782 case RTW89_FWD_TO_WLAN_CPU: 1783 val = RX_FLTR_FRAME_TO_WLCPU; 1784 break; 1785 default: 1786 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 1787 return -EINVAL; 1788 } 1789 1790 switch (type) { 1791 case RTW89_MGNT: 1792 reg = rtw89_mac_reg_by_idx(R_AX_MGNT_FLTR, mac_idx); 1793 break; 1794 case RTW89_CTRL: 1795 reg = rtw89_mac_reg_by_idx(R_AX_CTRL_FLTR, mac_idx); 1796 break; 1797 case RTW89_DATA: 1798 reg = rtw89_mac_reg_by_idx(R_AX_DATA_FLTR, mac_idx); 1799 break; 1800 default: 1801 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 1802 return -EINVAL; 1803 } 1804 rtw89_write32(rtwdev, reg, val); 1805 1806 return 0; 1807 } 1808 1809 static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1810 { 1811 int ret, i; 1812 u32 mac_ftlr, plcp_ftlr; 1813 1814 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1815 if (ret) 1816 return ret; 1817 1818 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 1819 ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST, 1820 mac_idx); 1821 if (ret) 1822 return ret; 1823 } 1824 mac_ftlr = rtwdev->hal.rx_fltr; 1825 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 1826 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 1827 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 1828 B_AX_HE_SIGB_CRC_CHK; 1829 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx), 1830 mac_ftlr); 1831 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx), 1832 plcp_ftlr); 1833 1834 return 0; 1835 } 1836 1837 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 1838 { 1839 u32 reg, val32; 1840 u32 b_rsp_chk_nav, b_rsp_chk_cca; 1841 1842 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 1843 B_AX_RSP_CHK_BASIC_NAV; 1844 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 1845 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 1846 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 1847 1848 switch (rtwdev->chip->chip_id) { 1849 case RTL8852A: 1850 case RTL8852B: 1851 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 1852 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 1853 rtw89_write32(rtwdev, reg, val32); 1854 1855 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 1856 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 1857 rtw89_write32(rtwdev, reg, val32); 1858 break; 1859 default: 1860 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 1861 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 1862 rtw89_write32(rtwdev, reg, val32); 1863 1864 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 1865 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 1866 rtw89_write32(rtwdev, reg, val32); 1867 break; 1868 } 1869 } 1870 1871 static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1872 { 1873 u32 val, reg; 1874 int ret; 1875 1876 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1877 if (ret) 1878 return ret; 1879 1880 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CONTROL, mac_idx); 1881 val = rtw89_read32(rtwdev, reg); 1882 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 1883 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 1884 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 1885 B_AX_CTN_CHK_INTRA_NAV | 1886 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 1887 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 1888 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 1889 B_AX_CTN_CHK_CCA_P20 | B_AX_SIFS_CHK_EDCCA); 1890 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 1891 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 1892 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 1893 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV); 1894 1895 rtw89_write32(rtwdev, reg, val); 1896 1897 _patch_dis_resp_chk(rtwdev, mac_idx); 1898 1899 return 0; 1900 } 1901 1902 static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1903 { 1904 u32 reg; 1905 int ret; 1906 1907 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1908 if (ret) 1909 return ret; 1910 reg = rtw89_mac_reg_by_idx(R_AX_RX_SR_CTRL, mac_idx); 1911 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 1912 1913 return 0; 1914 } 1915 1916 static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1917 { 1918 u32 reg; 1919 int ret; 1920 1921 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1922 if (ret) 1923 return ret; 1924 1925 reg = rtw89_mac_reg_by_idx(R_AX_MAC_LOOPBACK, mac_idx); 1926 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 1927 1928 return 0; 1929 } 1930 1931 static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1932 { 1933 u32 reg, val, sifs; 1934 int ret; 1935 1936 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1937 if (ret) 1938 return ret; 1939 1940 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 1941 val = rtw89_read32(rtwdev, reg); 1942 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 1943 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 1944 1945 switch (rtwdev->chip->chip_id) { 1946 case RTL8852A: 1947 sifs = WMAC_SPEC_SIFS_OFDM_52A; 1948 break; 1949 case RTL8852B: 1950 sifs = WMAC_SPEC_SIFS_OFDM_52B; 1951 break; 1952 default: 1953 sifs = WMAC_SPEC_SIFS_OFDM_52C; 1954 break; 1955 } 1956 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 1957 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 1958 rtw89_write32(rtwdev, reg, val); 1959 1960 reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx); 1961 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 1962 1963 return 0; 1964 } 1965 1966 static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1967 { 1968 #define TRXCFG_RMAC_CCA_TO 32 1969 #define TRXCFG_RMAC_DATA_TO 15 1970 #define RX_MAX_LEN_UNIT 512 1971 #define PLD_RLS_MAX_PG 127 1972 int ret; 1973 u32 reg, rx_max_len, rx_qta; 1974 u16 val; 1975 1976 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1977 if (ret) 1978 return ret; 1979 1980 reg = rtw89_mac_reg_by_idx(R_AX_RESPBA_CAM_CTRL, mac_idx); 1981 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 1982 1983 reg = rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx); 1984 val = rtw89_read16(rtwdev, reg); 1985 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 1986 B_AX_RX_DLK_DATA_TIME_MASK); 1987 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 1988 B_AX_RX_DLK_CCA_TIME_MASK); 1989 rtw89_write16(rtwdev, reg, val); 1990 1991 reg = rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx); 1992 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 1993 1994 reg = rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx); 1995 if (mac_idx == RTW89_MAC_0) 1996 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 1997 else 1998 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 1999 rx_qta = rx_qta > PLD_RLS_MAX_PG ? PLD_RLS_MAX_PG : rx_qta; 2000 rx_max_len = (rx_qta - 1) * rtwdev->mac.dle_info.ple_pg_size / 2001 RX_MAX_LEN_UNIT; 2002 rx_max_len = rx_max_len > B_AX_RX_MPDU_MAX_LEN_SIZE ? 2003 B_AX_RX_MPDU_MAX_LEN_SIZE : rx_max_len; 2004 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2005 2006 if (rtwdev->chip->chip_id == RTL8852A && 2007 rtwdev->hal.cv == CHIP_CBV) { 2008 rtw89_write16_mask(rtwdev, 2009 rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx), 2010 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2011 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx), 2012 BIT(12)); 2013 } 2014 2015 reg = rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx); 2016 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2017 2018 return ret; 2019 } 2020 2021 static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2022 { 2023 u32 val, reg; 2024 int ret; 2025 2026 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2027 if (ret) 2028 return ret; 2029 2030 reg = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2031 val = rtw89_read32(rtwdev, reg); 2032 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2033 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2034 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2035 rtw89_write32(rtwdev, reg, val); 2036 2037 return 0; 2038 } 2039 2040 static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2041 { 2042 const struct rtw89_dle_mem *cfg; 2043 2044 cfg = get_dle_mem_cfg(rtwdev, mode); 2045 if (!cfg) { 2046 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2047 return false; 2048 } 2049 2050 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2051 } 2052 2053 static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2054 { 2055 u32 val, reg; 2056 int ret; 2057 2058 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2059 if (ret) 2060 return ret; 2061 2062 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2063 reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); 2064 val = rtw89_read32(rtwdev, reg); 2065 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2066 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2067 val |= B_AX_HW_CTS2SELF_EN; 2068 rtw89_write32(rtwdev, reg, val); 2069 2070 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_FSM_MON, mac_idx); 2071 val = rtw89_read32(rtwdev, reg); 2072 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2073 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2074 rtw89_write32(rtwdev, reg, val); 2075 } 2076 2077 reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); 2078 val = rtw89_read32(rtwdev, reg); 2079 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2080 val |= B_AX_HW_CTS2SELF_EN; 2081 rtw89_write32(rtwdev, reg, val); 2082 2083 return 0; 2084 } 2085 2086 static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2087 { 2088 int ret; 2089 2090 ret = scheduler_init(rtwdev, mac_idx); 2091 if (ret) { 2092 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2093 return ret; 2094 } 2095 2096 ret = addr_cam_init(rtwdev, mac_idx); 2097 if (ret) { 2098 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2099 ret); 2100 return ret; 2101 } 2102 2103 ret = rx_fltr_init(rtwdev, mac_idx); 2104 if (ret) { 2105 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2106 ret); 2107 return ret; 2108 } 2109 2110 ret = cca_ctrl_init(rtwdev, mac_idx); 2111 if (ret) { 2112 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2113 ret); 2114 return ret; 2115 } 2116 2117 ret = spatial_reuse_init(rtwdev, mac_idx); 2118 if (ret) { 2119 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2120 mac_idx, ret); 2121 return ret; 2122 } 2123 2124 ret = tmac_init(rtwdev, mac_idx); 2125 if (ret) { 2126 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2127 return ret; 2128 } 2129 2130 ret = trxptcl_init(rtwdev, mac_idx); 2131 if (ret) { 2132 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2133 return ret; 2134 } 2135 2136 ret = rmac_init(rtwdev, mac_idx); 2137 if (ret) { 2138 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2139 return ret; 2140 } 2141 2142 ret = cmac_com_init(rtwdev, mac_idx); 2143 if (ret) { 2144 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2145 return ret; 2146 } 2147 2148 ret = ptcl_init(rtwdev, mac_idx); 2149 if (ret) { 2150 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2151 return ret; 2152 } 2153 2154 return ret; 2155 } 2156 2157 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2158 struct rtw89_mac_c2h_info *c2h_info) 2159 { 2160 struct rtw89_mac_h2c_info h2c_info = {0}; 2161 u32 ret; 2162 2163 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2164 h2c_info.content_len = 0; 2165 2166 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2167 if (ret) 2168 return ret; 2169 2170 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2171 return -EINVAL; 2172 2173 return 0; 2174 } 2175 2176 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2177 { 2178 struct rtw89_hal *hal = &rtwdev->hal; 2179 const struct rtw89_chip_info *chip = rtwdev->chip; 2180 struct rtw89_mac_c2h_info c2h_info = {0}; 2181 struct rtw89_c2h_phy_cap *cap = 2182 (struct rtw89_c2h_phy_cap *)&c2h_info.c2hreg[0]; 2183 u32 ret; 2184 2185 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2186 if (ret) 2187 return ret; 2188 2189 hal->tx_nss = cap->tx_nss ? 2190 min_t(u8, cap->tx_nss, chip->tx_nss) : chip->tx_nss; 2191 hal->rx_nss = cap->rx_nss ? 2192 min_t(u8, cap->rx_nss, chip->rx_nss) : chip->rx_nss; 2193 2194 rtw89_debug(rtwdev, RTW89_DBG_FW, 2195 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2196 hal->tx_nss, cap->tx_nss, chip->tx_nss, 2197 hal->rx_nss, cap->rx_nss, chip->rx_nss); 2198 2199 return 0; 2200 } 2201 2202 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2203 u16 tx_en_u16, u16 mask_u16) 2204 { 2205 u32 ret; 2206 struct rtw89_mac_c2h_info c2h_info = {0}; 2207 struct rtw89_mac_h2c_info h2c_info = {0}; 2208 struct rtw89_h2creg_sch_tx_en *h2creg = 2209 (struct rtw89_h2creg_sch_tx_en *)h2c_info.h2creg; 2210 2211 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2212 h2c_info.content_len = sizeof(*h2creg) - RTW89_H2CREG_HDR_LEN; 2213 h2creg->tx_en = tx_en_u16; 2214 h2creg->mask = mask_u16; 2215 h2creg->band = band; 2216 2217 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2218 if (ret) 2219 return ret; 2220 2221 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2222 return -EINVAL; 2223 2224 return 0; 2225 } 2226 2227 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2228 u16 tx_en, u16 tx_en_mask) 2229 { 2230 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx); 2231 u16 val; 2232 int ret; 2233 2234 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2235 if (ret) 2236 return ret; 2237 2238 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 2239 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 2240 tx_en, tx_en_mask); 2241 2242 val = rtw89_read16(rtwdev, reg); 2243 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2244 rtw89_write16(rtwdev, reg, val); 2245 2246 return 0; 2247 } 2248 2249 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2250 u32 tx_en, u32 tx_en_mask) 2251 { 2252 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx); 2253 u32 val; 2254 int ret; 2255 2256 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2257 if (ret) 2258 return ret; 2259 2260 val = rtw89_read32(rtwdev, reg); 2261 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2262 rtw89_write32(rtwdev, reg, val); 2263 2264 return 0; 2265 } 2266 2267 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 2268 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2269 { 2270 int ret; 2271 2272 *tx_en = rtw89_read16(rtwdev, 2273 rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx)); 2274 2275 switch (sel) { 2276 case RTW89_SCH_TX_SEL_ALL: 2277 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2278 B_AX_CTN_TXEN_ALL_MASK); 2279 if (ret) 2280 return ret; 2281 break; 2282 case RTW89_SCH_TX_SEL_HIQ: 2283 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2284 0, B_AX_CTN_TXEN_HGQ); 2285 if (ret) 2286 return ret; 2287 break; 2288 case RTW89_SCH_TX_SEL_MG0: 2289 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2290 0, B_AX_CTN_TXEN_MGQ); 2291 if (ret) 2292 return ret; 2293 break; 2294 case RTW89_SCH_TX_SEL_MACID: 2295 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2296 B_AX_CTN_TXEN_ALL_MASK); 2297 if (ret) 2298 return ret; 2299 break; 2300 default: 2301 return 0; 2302 } 2303 2304 return 0; 2305 } 2306 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 2307 2308 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2309 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2310 { 2311 int ret; 2312 2313 *tx_en = rtw89_read32(rtwdev, 2314 rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx)); 2315 2316 switch (sel) { 2317 case RTW89_SCH_TX_SEL_ALL: 2318 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2319 B_AX_CTN_TXEN_ALL_MASK_V1); 2320 if (ret) 2321 return ret; 2322 break; 2323 case RTW89_SCH_TX_SEL_HIQ: 2324 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2325 0, B_AX_CTN_TXEN_HGQ); 2326 if (ret) 2327 return ret; 2328 break; 2329 case RTW89_SCH_TX_SEL_MG0: 2330 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2331 0, B_AX_CTN_TXEN_MGQ); 2332 if (ret) 2333 return ret; 2334 break; 2335 case RTW89_SCH_TX_SEL_MACID: 2336 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2337 B_AX_CTN_TXEN_ALL_MASK_V1); 2338 if (ret) 2339 return ret; 2340 break; 2341 default: 2342 return 0; 2343 } 2344 2345 return 0; 2346 } 2347 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 2348 2349 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2350 { 2351 int ret; 2352 2353 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 2354 if (ret) 2355 return ret; 2356 2357 return 0; 2358 } 2359 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 2360 2361 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2362 { 2363 int ret; 2364 2365 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 2366 B_AX_CTN_TXEN_ALL_MASK_V1); 2367 if (ret) 2368 return ret; 2369 2370 return 0; 2371 } 2372 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 2373 2374 static u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, 2375 bool wd) 2376 { 2377 u32 val, reg; 2378 int ret; 2379 2380 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 2381 val = buf_len; 2382 val |= B_AX_WD_BUF_REQ_EXEC; 2383 rtw89_write32(rtwdev, reg, val); 2384 2385 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 2386 2387 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 2388 1, 2000, false, rtwdev, reg); 2389 if (ret) 2390 return 0xffff; 2391 2392 return FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 2393 } 2394 2395 static int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, 2396 struct rtw89_cpuio_ctrl *ctrl_para, 2397 bool wd) 2398 { 2399 u32 val, cmd_type, reg; 2400 int ret; 2401 2402 cmd_type = ctrl_para->cmd_type; 2403 2404 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 2405 val = 0; 2406 val = u32_replace_bits(val, ctrl_para->start_pktid, 2407 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 2408 val = u32_replace_bits(val, ctrl_para->end_pktid, 2409 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 2410 rtw89_write32(rtwdev, reg, val); 2411 2412 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 2413 val = 0; 2414 val = u32_replace_bits(val, ctrl_para->src_pid, 2415 B_AX_CPUQ_OP_SRC_PID_MASK); 2416 val = u32_replace_bits(val, ctrl_para->src_qid, 2417 B_AX_CPUQ_OP_SRC_QID_MASK); 2418 val = u32_replace_bits(val, ctrl_para->dst_pid, 2419 B_AX_CPUQ_OP_DST_PID_MASK); 2420 val = u32_replace_bits(val, ctrl_para->dst_qid, 2421 B_AX_CPUQ_OP_DST_QID_MASK); 2422 rtw89_write32(rtwdev, reg, val); 2423 2424 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 2425 val = 0; 2426 val = u32_replace_bits(val, cmd_type, 2427 B_AX_CPUQ_OP_CMD_TYPE_MASK); 2428 val = u32_replace_bits(val, ctrl_para->macid, 2429 B_AX_CPUQ_OP_MACID_MASK); 2430 val = u32_replace_bits(val, ctrl_para->pkt_num, 2431 B_AX_CPUQ_OP_PKTNUM_MASK); 2432 val |= B_AX_WD_CPUQ_OP_EXEC; 2433 rtw89_write32(rtwdev, reg, val); 2434 2435 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 2436 2437 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 2438 1, 2000, false, rtwdev, reg); 2439 if (ret) 2440 return ret; 2441 2442 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 2443 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 2444 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 2445 2446 return 0; 2447 } 2448 2449 static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2450 { 2451 const struct rtw89_dle_mem *cfg; 2452 struct rtw89_cpuio_ctrl ctrl_para = {0}; 2453 u16 pkt_id; 2454 int ret; 2455 2456 cfg = get_dle_mem_cfg(rtwdev, mode); 2457 if (!cfg) { 2458 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2459 return -EINVAL; 2460 } 2461 2462 if (dle_used_size(cfg->wde_size, cfg->ple_size) != rtwdev->chip->fifo_size) { 2463 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2464 return -EINVAL; 2465 } 2466 2467 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 2468 2469 pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, true); 2470 if (pkt_id == 0xffff) { 2471 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 2472 return -ENOMEM; 2473 } 2474 2475 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2476 ctrl_para.start_pktid = pkt_id; 2477 ctrl_para.end_pktid = pkt_id; 2478 ctrl_para.pkt_num = 0; 2479 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 2480 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 2481 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true); 2482 if (ret) { 2483 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 2484 return -EFAULT; 2485 } 2486 2487 pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, false); 2488 if (pkt_id == 0xffff) { 2489 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 2490 return -ENOMEM; 2491 } 2492 2493 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2494 ctrl_para.start_pktid = pkt_id; 2495 ctrl_para.end_pktid = pkt_id; 2496 ctrl_para.pkt_num = 0; 2497 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 2498 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 2499 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false); 2500 if (ret) { 2501 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 2502 return -EFAULT; 2503 } 2504 2505 return 0; 2506 } 2507 2508 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 2509 { 2510 int ret; 2511 u32 reg; 2512 u8 val; 2513 2514 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2515 if (ret) 2516 return ret; 2517 2518 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_TX_CTN_SEL, mac_idx); 2519 2520 ret = read_poll_timeout(rtw89_read8, val, 2521 (val & B_AX_PTCL_TX_ON_STAT) == 0, 2522 SW_CVR_DUR_US, 2523 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 2524 false, rtwdev, reg); 2525 if (ret) 2526 return ret; 2527 2528 return 0; 2529 } 2530 2531 static int band1_enable(struct rtw89_dev *rtwdev) 2532 { 2533 int ret, i; 2534 u32 sleep_bak[4] = {0}; 2535 u32 pause_bak[4] = {0}; 2536 u32 tx_en; 2537 2538 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 2539 if (ret) { 2540 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 2541 return ret; 2542 } 2543 2544 for (i = 0; i < 4; i++) { 2545 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 2546 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 2547 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 2548 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 2549 } 2550 2551 ret = band_idle_ck_b(rtwdev, 0); 2552 if (ret) { 2553 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 2554 return ret; 2555 } 2556 2557 ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode); 2558 if (ret) { 2559 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 2560 return ret; 2561 } 2562 2563 for (i = 0; i < 4; i++) { 2564 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 2565 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 2566 } 2567 2568 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 2569 if (ret) { 2570 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 2571 return ret; 2572 } 2573 2574 ret = cmac_func_en(rtwdev, 1, true); 2575 if (ret) { 2576 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 2577 return ret; 2578 } 2579 2580 ret = cmac_init(rtwdev, 1); 2581 if (ret) { 2582 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 2583 return ret; 2584 } 2585 2586 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 2587 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 2588 2589 return 0; 2590 } 2591 2592 static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, 2593 enum rtw89_mac_hwmod_sel sel) 2594 { 2595 u32 reg, val; 2596 int ret; 2597 2598 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 2599 if (ret) { 2600 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 2601 sel, mac_idx); 2602 return ret; 2603 } 2604 2605 if (sel == RTW89_DMAC_SEL) { 2606 rtw89_write32_clr(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR, 2607 B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | 2608 B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN | 2609 B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN); 2610 rtw89_write32_clr(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1, 2611 B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | 2612 B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN); 2613 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 2614 B_AX_HDT_PKT_FAIL_DBG_INT_EN | 2615 B_AX_HDT_OFFSET_UNMATCH_INT_EN); 2616 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 2617 B_AX_CPU_SHIFT_EN_ERR_INT_EN); 2618 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, 2619 B_AX_PLE_GETNPG_STRPG_ERR_INT_EN); 2620 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, 2621 B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN); 2622 rtw89_write32_set(rtwdev, R_AX_HD0IMR, B_AX_WDT_PTFM_INT_EN); 2623 rtw89_write32_clr(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR, 2624 B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN); 2625 } else if (sel == RTW89_CMAC_SEL) { 2626 reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx); 2627 rtw89_write32_clr(rtwdev, reg, 2628 B_AX_SORT_NON_IDLE_ERR_INT_EN); 2629 2630 reg = rtw89_mac_reg_by_idx(R_AX_DLE_CTRL, mac_idx); 2631 rtw89_write32_clr(rtwdev, reg, 2632 B_AX_NO_RESERVE_PAGE_ERR_IMR | 2633 B_AX_RXDATA_FSM_HANG_ERROR_IMR); 2634 2635 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx); 2636 val = B_AX_F2PCMD_USER_ALLC_ERR_INT_EN | 2637 B_AX_TX_RECORD_PKTID_ERR_INT_EN | 2638 B_AX_FSM_TIMEOUT_ERR_INT_EN; 2639 rtw89_write32(rtwdev, reg, val); 2640 2641 reg = rtw89_mac_reg_by_idx(R_AX_PHYINFO_ERR_IMR, mac_idx); 2642 rtw89_write32_set(rtwdev, reg, 2643 B_AX_PHY_TXON_TIMEOUT_INT_EN | 2644 B_AX_CCK_CCA_TIMEOUT_INT_EN | 2645 B_AX_OFDM_CCA_TIMEOUT_INT_EN | 2646 B_AX_DATA_ON_TIMEOUT_INT_EN | 2647 B_AX_STS_ON_TIMEOUT_INT_EN | 2648 B_AX_CSI_ON_TIMEOUT_INT_EN); 2649 2650 reg = rtw89_mac_reg_by_idx(R_AX_RMAC_ERR_ISR, mac_idx); 2651 val = rtw89_read32(rtwdev, reg); 2652 val |= (B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN | 2653 B_AX_RMAC_RX_TIMEOUT_INT_EN | 2654 B_AX_RMAC_CSI_TIMEOUT_INT_EN); 2655 val &= ~(B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN | 2656 B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN | 2657 B_AX_RMAC_CCA_TIMEOUT_INT_EN | 2658 B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN); 2659 rtw89_write32(rtwdev, reg, val); 2660 } else { 2661 return -EINVAL; 2662 } 2663 2664 return 0; 2665 } 2666 2667 static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) 2668 { 2669 int ret = 0; 2670 2671 if (enable) { 2672 ret = band1_enable(rtwdev); 2673 if (ret) { 2674 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 2675 return ret; 2676 } 2677 2678 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 2679 if (ret) { 2680 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 2681 return ret; 2682 } 2683 } else { 2684 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 2685 return -EINVAL; 2686 } 2687 2688 return 0; 2689 } 2690 2691 static int set_host_rpr(struct rtw89_dev *rtwdev) 2692 { 2693 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2694 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 2695 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 2696 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 2697 B_AX_RLSRPT0_FLTR_MAP_MASK); 2698 } else { 2699 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 2700 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 2701 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 2702 B_AX_RLSRPT0_FLTR_MAP_MASK); 2703 } 2704 2705 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 2706 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 2707 2708 return 0; 2709 } 2710 2711 static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) 2712 { 2713 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 2714 int ret; 2715 2716 ret = dmac_init(rtwdev, 0); 2717 if (ret) { 2718 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 2719 return ret; 2720 } 2721 2722 ret = cmac_init(rtwdev, 0); 2723 if (ret) { 2724 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 2725 return ret; 2726 } 2727 2728 if (is_qta_dbcc(rtwdev, qta_mode)) { 2729 ret = rtw89_mac_dbcc_enable(rtwdev, true); 2730 if (ret) { 2731 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 2732 return ret; 2733 } 2734 } 2735 2736 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2737 if (ret) { 2738 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 2739 return ret; 2740 } 2741 2742 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 2743 if (ret) { 2744 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 2745 return ret; 2746 } 2747 2748 ret = set_host_rpr(rtwdev); 2749 if (ret) { 2750 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 2751 return ret; 2752 } 2753 2754 return 0; 2755 } 2756 2757 static void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev) 2758 { 2759 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 2760 2761 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 2762 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 2763 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 2764 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 2765 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 2766 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 2767 } 2768 2769 static int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, 2770 bool dlfw) 2771 { 2772 u32 val; 2773 int ret; 2774 2775 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 2776 return -EFAULT; 2777 2778 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 2779 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 2780 2781 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 2782 2783 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 2784 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 2785 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 2786 B_AX_WCPU_FWDL_STS_MASK); 2787 2788 if (dlfw) 2789 val |= B_AX_WCPU_FWDL_EN; 2790 2791 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 2792 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 2793 boot_reason); 2794 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 2795 2796 if (!dlfw) { 2797 mdelay(5); 2798 2799 ret = rtw89_fw_check_rdy(rtwdev); 2800 if (ret) 2801 return ret; 2802 } 2803 2804 return 0; 2805 } 2806 2807 static int rtw89_mac_fw_dl_pre_init(struct rtw89_dev *rtwdev) 2808 { 2809 u32 val; 2810 int ret; 2811 2812 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 2813 B_AX_PKT_BUF_EN; 2814 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 2815 2816 val = B_AX_DISPATCHER_CLK_EN; 2817 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 2818 2819 ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 2820 if (ret) { 2821 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 2822 return ret; 2823 } 2824 2825 ret = hfc_init(rtwdev, true, false, true); 2826 if (ret) { 2827 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 2828 return ret; 2829 } 2830 2831 return ret; 2832 } 2833 2834 static void rtw89_mac_hci_func_en(struct rtw89_dev *rtwdev) 2835 { 2836 const struct rtw89_chip_info *chip = rtwdev->chip; 2837 2838 rtw89_write32_set(rtwdev, chip->hci_func_en_addr, 2839 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN); 2840 } 2841 2842 void rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 2843 { 2844 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 2845 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2846 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 2847 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 2848 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 2849 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 2850 } 2851 2852 void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 2853 { 2854 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 2855 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2856 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 2857 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 2858 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 2859 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 2860 } 2861 2862 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev) 2863 { 2864 int ret; 2865 2866 ret = rtw89_mac_power_switch(rtwdev, true); 2867 if (ret) { 2868 rtw89_mac_power_switch(rtwdev, false); 2869 ret = rtw89_mac_power_switch(rtwdev, true); 2870 if (ret) 2871 return ret; 2872 } 2873 2874 rtw89_mac_hci_func_en(rtwdev); 2875 2876 if (rtwdev->hci.ops->mac_pre_init) { 2877 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 2878 if (ret) 2879 return ret; 2880 } 2881 2882 ret = rtw89_mac_fw_dl_pre_init(rtwdev); 2883 if (ret) 2884 return ret; 2885 2886 rtw89_mac_disable_cpu(rtwdev); 2887 ret = rtw89_mac_enable_cpu(rtwdev, 0, true); 2888 if (ret) 2889 return ret; 2890 2891 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL); 2892 if (ret) 2893 return ret; 2894 2895 return 0; 2896 } 2897 2898 int rtw89_mac_init(struct rtw89_dev *rtwdev) 2899 { 2900 int ret; 2901 2902 ret = rtw89_mac_partial_init(rtwdev); 2903 if (ret) 2904 goto fail; 2905 2906 rtw89_mac_enable_bb_rf(rtwdev); 2907 2908 ret = rtw89_mac_sys_init(rtwdev); 2909 if (ret) 2910 goto fail; 2911 2912 ret = rtw89_mac_trx_init(rtwdev); 2913 if (ret) 2914 goto fail; 2915 2916 if (rtwdev->hci.ops->mac_post_init) { 2917 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 2918 if (ret) 2919 goto fail; 2920 } 2921 2922 rtw89_fw_send_all_early_h2c(rtwdev); 2923 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 2924 2925 return ret; 2926 fail: 2927 rtw89_mac_power_switch(rtwdev, false); 2928 2929 return ret; 2930 } 2931 2932 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 2933 { 2934 u8 i; 2935 2936 for (i = 0; i < 4; i++) { 2937 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 2938 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 2939 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 2940 } 2941 } 2942 2943 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 2944 { 2945 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 2946 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 2947 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 2948 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 2949 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 2950 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 2951 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 2952 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 2953 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 2954 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 2955 } 2956 2957 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 2958 { 2959 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 2960 u8 grp = macid >> 5; 2961 int ret; 2962 2963 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 2964 if (ret) 2965 return ret; 2966 2967 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 2968 2969 return 0; 2970 } 2971 2972 static const struct rtw89_port_reg rtw_port_base = { 2973 .port_cfg = R_AX_PORT_CFG_P0, 2974 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 2975 .bcn_area = R_AX_BCN_AREA_P0, 2976 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 2977 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 2978 .tbtt_agg = R_AX_TBTT_AGG_P0, 2979 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 2980 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 2981 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 2982 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 2983 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 2984 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 2985 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 2986 .tsftr_l = R_AX_TSFTR_LOW_P0, 2987 .tsftr_h = R_AX_TSFTR_HIGH_P0 2988 }; 2989 2990 #define BCN_INTERVAL 100 2991 #define BCN_ERLY_DEF 160 2992 #define BCN_SETUP_DEF 2 2993 #define BCN_HOLD_DEF 200 2994 #define BCN_MASK_DEF 0 2995 #define TBTT_ERLY_DEF 5 2996 #define BCN_SET_UNIT 32 2997 #define BCN_ERLY_SET_DLY (10 * 2) 2998 2999 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 3000 struct rtw89_vif *rtwvif) 3001 { 3002 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3003 const struct rtw89_port_reg *p = &rtw_port_base; 3004 3005 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 3006 return; 3007 3008 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 3009 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 3010 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 3011 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 3012 3013 msleep(vif->bss_conf.beacon_int + 1); 3014 3015 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 3016 B_AX_BRK_SETUP); 3017 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 3018 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 3019 } 3020 3021 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 3022 struct rtw89_vif *rtwvif, bool en) 3023 { 3024 const struct rtw89_port_reg *p = &rtw_port_base; 3025 3026 if (en) 3027 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3028 else 3029 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3030 } 3031 3032 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 3033 struct rtw89_vif *rtwvif, bool en) 3034 { 3035 const struct rtw89_port_reg *p = &rtw_port_base; 3036 3037 if (en) 3038 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3039 else 3040 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3041 } 3042 3043 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 3044 struct rtw89_vif *rtwvif) 3045 { 3046 const struct rtw89_port_reg *p = &rtw_port_base; 3047 3048 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 3049 rtwvif->net_type); 3050 } 3051 3052 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 3053 struct rtw89_vif *rtwvif) 3054 { 3055 const struct rtw89_port_reg *p = &rtw_port_base; 3056 bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 3057 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 3058 3059 if (en) 3060 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 3061 else 3062 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 3063 } 3064 3065 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 3066 struct rtw89_vif *rtwvif) 3067 { 3068 const struct rtw89_port_reg *p = &rtw_port_base; 3069 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3070 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3071 u32 bit = B_AX_RX_BSSID_FIT_EN; 3072 3073 if (en) 3074 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 3075 else 3076 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 3077 } 3078 3079 static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 3080 struct rtw89_vif *rtwvif) 3081 { 3082 const struct rtw89_port_reg *p = &rtw_port_base; 3083 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3084 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3085 3086 if (en) 3087 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3088 else 3089 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3090 } 3091 3092 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 3093 struct rtw89_vif *rtwvif) 3094 { 3095 const struct rtw89_port_reg *p = &rtw_port_base; 3096 bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 3097 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3098 3099 if (en) 3100 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3101 else 3102 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3103 } 3104 3105 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 3106 struct rtw89_vif *rtwvif) 3107 { 3108 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3109 const struct rtw89_port_reg *p = &rtw_port_base; 3110 u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 3111 3112 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 3113 bcn_int); 3114 } 3115 3116 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 3117 struct rtw89_vif *rtwvif) 3118 { 3119 static const u32 hiq_win_addr[RTW89_PORT_NUM] = { 3120 R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 3121 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 3122 R_AX_PORT_HGQ_WINDOW_CFG + 3, 3123 }; 3124 u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 3125 u8 port = rtwvif->port; 3126 u32 reg; 3127 3128 reg = rtw89_mac_reg_by_idx(hiq_win_addr[port], rtwvif->mac_idx); 3129 rtw89_write8(rtwdev, reg, win); 3130 } 3131 3132 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 3133 struct rtw89_vif *rtwvif) 3134 { 3135 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3136 const struct rtw89_port_reg *p = &rtw_port_base; 3137 u32 addr; 3138 3139 addr = rtw89_mac_reg_by_idx(R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx); 3140 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 3141 3142 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 3143 vif->bss_conf.dtim_period); 3144 } 3145 3146 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 3147 struct rtw89_vif *rtwvif) 3148 { 3149 const struct rtw89_port_reg *p = &rtw_port_base; 3150 3151 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3152 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 3153 } 3154 3155 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 3156 struct rtw89_vif *rtwvif) 3157 { 3158 const struct rtw89_port_reg *p = &rtw_port_base; 3159 3160 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3161 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 3162 } 3163 3164 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 3165 struct rtw89_vif *rtwvif) 3166 { 3167 const struct rtw89_port_reg *p = &rtw_port_base; 3168 3169 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 3170 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 3171 } 3172 3173 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 3174 struct rtw89_vif *rtwvif) 3175 { 3176 const struct rtw89_port_reg *p = &rtw_port_base; 3177 3178 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 3179 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 3180 } 3181 3182 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 3183 struct rtw89_vif *rtwvif) 3184 { 3185 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3186 static const u32 masks[RTW89_PORT_NUM] = { 3187 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 3188 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 3189 B_AX_BSS_COLOB_AX_PORT_4_MASK, 3190 }; 3191 u8 port = rtwvif->port; 3192 u32 reg_base; 3193 u32 reg; 3194 u8 bss_color; 3195 3196 bss_color = vif->bss_conf.he_bss_color.color; 3197 reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0; 3198 reg = rtw89_mac_reg_by_idx(reg_base, rtwvif->mac_idx); 3199 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 3200 } 3201 3202 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 3203 struct rtw89_vif *rtwvif) 3204 { 3205 u8 port = rtwvif->port; 3206 u32 reg; 3207 3208 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 3209 return; 3210 3211 if (port == 0) { 3212 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_CTRL, rtwvif->mac_idx); 3213 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 3214 } 3215 } 3216 3217 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 3218 struct rtw89_vif *rtwvif) 3219 { 3220 u8 port = rtwvif->port; 3221 u32 reg; 3222 u32 val; 3223 3224 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_DROP_0, rtwvif->mac_idx); 3225 val = rtw89_read32(rtwdev, reg); 3226 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 3227 if (port == 0) 3228 val &= ~BIT(0); 3229 rtw89_write32(rtwdev, reg, val); 3230 } 3231 3232 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 3233 struct rtw89_vif *rtwvif) 3234 { 3235 const struct rtw89_port_reg *p = &rtw_port_base; 3236 3237 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN); 3238 } 3239 3240 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 3241 struct rtw89_vif *rtwvif) 3242 { 3243 const struct rtw89_port_reg *p = &rtw_port_base; 3244 3245 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 3246 BCN_ERLY_DEF); 3247 } 3248 3249 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3250 { 3251 int ret; 3252 3253 ret = rtw89_mac_port_update(rtwdev, rtwvif); 3254 if (ret) 3255 return ret; 3256 3257 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 3258 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 3259 3260 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 3261 if (ret) 3262 return ret; 3263 3264 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 3265 if (ret) 3266 return ret; 3267 3268 ret = rtw89_cam_init(rtwdev, rtwvif); 3269 if (ret) 3270 return ret; 3271 3272 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 3273 if (ret) 3274 return ret; 3275 3276 ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif); 3277 if (ret) 3278 return ret; 3279 3280 return 0; 3281 } 3282 3283 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3284 { 3285 int ret; 3286 3287 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 3288 if (ret) 3289 return ret; 3290 3291 rtw89_cam_deinit(rtwdev, rtwvif); 3292 3293 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 3294 if (ret) 3295 return ret; 3296 3297 return 0; 3298 } 3299 3300 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3301 { 3302 u8 port = rtwvif->port; 3303 3304 if (port >= RTW89_PORT_NUM) 3305 return -EINVAL; 3306 3307 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 3308 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 3309 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 3310 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 3311 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 3312 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 3313 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); 3314 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif); 3315 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 3316 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 3317 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 3318 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 3319 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 3320 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 3321 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 3322 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 3323 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 3324 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 3325 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif); 3326 fsleep(BCN_ERLY_SET_DLY); 3327 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 3328 3329 return 0; 3330 } 3331 3332 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3333 { 3334 int ret; 3335 3336 rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 3337 RTW89_MAX_MAC_ID_NUM); 3338 if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 3339 return -ENOSPC; 3340 3341 ret = rtw89_mac_vif_init(rtwdev, rtwvif); 3342 if (ret) 3343 goto release_mac_id; 3344 3345 return 0; 3346 3347 release_mac_id: 3348 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 3349 3350 return ret; 3351 } 3352 3353 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3354 { 3355 int ret; 3356 3357 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 3358 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 3359 3360 return ret; 3361 } 3362 3363 static void 3364 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3365 { 3366 } 3367 3368 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 3369 { 3370 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 3371 3372 return band == scan_info->op_band && channel == scan_info->op_pri_ch; 3373 } 3374 3375 static void 3376 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 3377 u32 len) 3378 { 3379 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 3380 struct rtw89_hal *hal = &rtwdev->hal; 3381 u8 reason, status, tx_fail, band; 3382 u16 chan; 3383 3384 tx_fail = RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h->data); 3385 status = RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h->data); 3386 chan = RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h->data); 3387 reason = RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h->data); 3388 band = RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h->data); 3389 3390 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 3391 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 3392 3393 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 3394 "band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d\n", 3395 band, chan, reason, status, tx_fail); 3396 3397 switch (reason) { 3398 case RTW89_SCAN_LEAVE_CH_NOTIFY: 3399 if (rtw89_is_op_chan(rtwdev, band, chan)) 3400 ieee80211_stop_queues(rtwdev->hw); 3401 return; 3402 case RTW89_SCAN_END_SCAN_NOTIFY: 3403 rtw89_hw_scan_complete(rtwdev, vif, false); 3404 break; 3405 case RTW89_SCAN_ENTER_CH_NOTIFY: 3406 if (rtw89_is_op_chan(rtwdev, band, chan)) 3407 ieee80211_wake_queues(rtwdev->hw); 3408 break; 3409 default: 3410 return; 3411 } 3412 3413 hal->prev_band_type = hal->current_band_type; 3414 hal->prev_primary_channel = hal->current_channel; 3415 hal->current_channel = chan; 3416 hal->current_band_type = band; 3417 } 3418 3419 static void 3420 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3421 { 3422 rtw89_debug(rtwdev, RTW89_DBG_FW, 3423 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 3424 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 3425 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 3426 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 3427 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 3428 } 3429 3430 static void 3431 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3432 { 3433 rtw89_debug(rtwdev, RTW89_DBG_FW, 3434 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 3435 RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h->data), 3436 RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h->data), 3437 RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h->data), 3438 RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h->data), 3439 RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h->data)); 3440 } 3441 3442 static void 3443 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3444 { 3445 rtw89_info(rtwdev, "%*s", RTW89_GET_C2H_LOG_LEN(len), 3446 RTW89_GET_C2H_LOG_SRT_PRT(c2h->data)); 3447 } 3448 3449 static void 3450 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3451 { 3452 } 3453 3454 static 3455 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 3456 struct sk_buff *c2h, u32 len) = { 3457 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 3458 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 3459 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = NULL, 3460 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 3461 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 3462 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 3463 }; 3464 3465 static 3466 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 3467 struct sk_buff *c2h, u32 len) = { 3468 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 3469 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 3470 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 3471 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 3472 }; 3473 3474 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 3475 u32 len, u8 class, u8 func) 3476 { 3477 void (*handler)(struct rtw89_dev *rtwdev, 3478 struct sk_buff *c2h, u32 len) = NULL; 3479 3480 switch (class) { 3481 case RTW89_MAC_C2H_CLASS_INFO: 3482 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 3483 handler = rtw89_mac_c2h_info_handler[func]; 3484 break; 3485 case RTW89_MAC_C2H_CLASS_OFLD: 3486 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 3487 handler = rtw89_mac_c2h_ofld_handler[func]; 3488 break; 3489 case RTW89_MAC_C2H_CLASS_FWDBG: 3490 return; 3491 default: 3492 rtw89_info(rtwdev, "c2h class %d not support\n", class); 3493 return; 3494 } 3495 if (!handler) { 3496 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 3497 func); 3498 return; 3499 } 3500 handler(rtwdev, skb, len); 3501 } 3502 3503 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 3504 enum rtw89_phy_idx phy_idx, 3505 u32 reg_base, u32 *cr) 3506 { 3507 const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; 3508 enum rtw89_qta_mode mode = dle_mem->mode; 3509 u32 addr = rtw89_mac_reg_by_idx(reg_base, phy_idx); 3510 3511 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) { 3512 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 3513 addr); 3514 goto error; 3515 } 3516 3517 if (addr >= CMAC1_START_ADDR && addr <= CMAC1_END_ADDR) 3518 if (mode == RTW89_QTA_SCC) { 3519 rtw89_err(rtwdev, 3520 "[TXPWR] addr=0x%x but hw not enable\n", 3521 addr); 3522 goto error; 3523 } 3524 3525 *cr = addr; 3526 return true; 3527 3528 error: 3529 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 3530 addr, phy_idx); 3531 3532 return false; 3533 } 3534 EXPORT_SYMBOL(rtw89_mac_get_txpwr_cr); 3535 3536 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 3537 { 3538 u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx); 3539 int ret = 0; 3540 3541 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3542 if (ret) 3543 return ret; 3544 3545 if (!enable) { 3546 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 3547 return ret; 3548 } 3549 3550 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 3551 B_AX_APP_MAC_INFO_RPT | 3552 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 3553 B_AX_PPDU_STAT_RPT_CRC32); 3554 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 3555 RTW89_PRPT_DEST_HOST); 3556 3557 return ret; 3558 } 3559 EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status); 3560 3561 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 3562 { 3563 #define MAC_AX_TIME_TH_SH 5 3564 #define MAC_AX_LEN_TH_SH 4 3565 #define MAC_AX_TIME_TH_MAX 255 3566 #define MAC_AX_LEN_TH_MAX 255 3567 #define MAC_AX_TIME_TH_DEF 88 3568 #define MAC_AX_LEN_TH_DEF 4080 3569 struct ieee80211_hw *hw = rtwdev->hw; 3570 u32 rts_threshold = hw->wiphy->rts_threshold; 3571 u32 time_th, len_th; 3572 u32 reg; 3573 3574 if (rts_threshold == (u32)-1) { 3575 time_th = MAC_AX_TIME_TH_DEF; 3576 len_th = MAC_AX_LEN_TH_DEF; 3577 } else { 3578 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 3579 len_th = rts_threshold; 3580 } 3581 3582 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 3583 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 3584 3585 reg = rtw89_mac_reg_by_idx(R_AX_AGG_LEN_HT_0, mac_idx); 3586 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 3587 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 3588 } 3589 3590 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 3591 { 3592 bool empty; 3593 int ret; 3594 3595 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3596 return; 3597 3598 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 3599 10000, 200000, false, rtwdev); 3600 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 3601 rtw89_info(rtwdev, "timed out to flush queues\n"); 3602 } 3603 3604 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 3605 { 3606 u8 val; 3607 u16 val16; 3608 u32 val32; 3609 int ret; 3610 3611 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 3612 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 3613 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 3614 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 3615 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 3616 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 3617 3618 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 3619 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 3620 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 3621 3622 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 3623 if (ret) { 3624 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 3625 return ret; 3626 } 3627 val32 = val32 & B_AX_WL_RX_CTRL; 3628 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 3629 if (ret) { 3630 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 3631 return ret; 3632 } 3633 3634 switch (coex->pta_mode) { 3635 case RTW89_MAC_AX_COEX_RTK_MODE: 3636 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 3637 val &= ~B_AX_BTMODE_MASK; 3638 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 3639 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 3640 3641 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 3642 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 3643 3644 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 3645 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 3646 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 3647 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 3648 break; 3649 case RTW89_MAC_AX_COEX_CSR_MODE: 3650 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 3651 val &= ~B_AX_BTMODE_MASK; 3652 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 3653 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 3654 3655 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 3656 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 3657 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 3658 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 3659 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 3660 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 3661 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 3662 val16 |= B_AX_ENHANCED_BT; 3663 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 3664 3665 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 3666 break; 3667 default: 3668 return -EINVAL; 3669 } 3670 3671 switch (coex->direction) { 3672 case RTW89_MAC_AX_COEX_INNER: 3673 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 3674 val = (val & ~BIT(2)) | BIT(1); 3675 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 3676 break; 3677 case RTW89_MAC_AX_COEX_OUTPUT: 3678 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 3679 val = val | BIT(1) | BIT(0); 3680 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 3681 break; 3682 case RTW89_MAC_AX_COEX_INPUT: 3683 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 3684 val = val & ~(BIT(2) | BIT(1)); 3685 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 3686 break; 3687 default: 3688 return -EINVAL; 3689 } 3690 3691 return 0; 3692 } 3693 EXPORT_SYMBOL(rtw89_mac_coex_init); 3694 3695 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 3696 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 3697 { 3698 u32 val = 0, ret; 3699 3700 if (gnt_cfg->band[0].gnt_bt) 3701 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 3702 3703 if (gnt_cfg->band[0].gnt_bt_sw_en) 3704 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 3705 3706 if (gnt_cfg->band[0].gnt_wl) 3707 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 3708 3709 if (gnt_cfg->band[0].gnt_wl_sw_en) 3710 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 3711 3712 if (gnt_cfg->band[1].gnt_bt) 3713 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 3714 3715 if (gnt_cfg->band[1].gnt_bt_sw_en) 3716 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 3717 3718 if (gnt_cfg->band[1].gnt_wl) 3719 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 3720 3721 if (gnt_cfg->band[1].gnt_wl_sw_en) 3722 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 3723 3724 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 3725 if (ret) { 3726 rtw89_err(rtwdev, "Write LTE fail!\n"); 3727 return ret; 3728 } 3729 3730 return 0; 3731 } 3732 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 3733 3734 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 3735 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 3736 { 3737 u32 val = 0; 3738 3739 if (gnt_cfg->band[0].gnt_bt) 3740 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 3741 B_AX_GNT_BT_TX_VAL; 3742 else 3743 val |= B_AX_WL_ACT_VAL; 3744 3745 if (gnt_cfg->band[0].gnt_bt_sw_en) 3746 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 3747 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 3748 3749 if (gnt_cfg->band[0].gnt_wl) 3750 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 3751 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 3752 3753 if (gnt_cfg->band[0].gnt_wl_sw_en) 3754 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 3755 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 3756 3757 if (gnt_cfg->band[1].gnt_bt) 3758 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 3759 B_AX_GNT_BT_TX_VAL; 3760 else 3761 val |= B_AX_WL_ACT_VAL; 3762 3763 if (gnt_cfg->band[1].gnt_bt_sw_en) 3764 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 3765 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 3766 3767 if (gnt_cfg->band[1].gnt_wl) 3768 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 3769 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 3770 3771 if (gnt_cfg->band[1].gnt_wl_sw_en) 3772 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 3773 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 3774 3775 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 3776 3777 return 0; 3778 } 3779 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 3780 3781 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 3782 { 3783 u32 reg; 3784 u16 val; 3785 int ret; 3786 3787 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 3788 if (ret) 3789 return ret; 3790 3791 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, plt->band); 3792 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 3793 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 3794 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 3795 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 3796 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 3797 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 3798 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 3799 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 3800 B_AX_PLT_EN; 3801 rtw89_write16(rtwdev, reg, val); 3802 3803 return 0; 3804 } 3805 3806 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 3807 { 3808 u32 fw_sb; 3809 3810 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 3811 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 3812 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 3813 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3814 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 3815 else 3816 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 3817 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 3818 val = B_AX_TOGGLE | 3819 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 3820 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 3821 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 3822 fsleep(1000); /* avoid BT FW loss information */ 3823 } 3824 3825 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 3826 { 3827 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 3828 } 3829 3830 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 3831 { 3832 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 3833 3834 val = wl ? val | BIT(2) : val & ~BIT(2); 3835 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 3836 3837 return 0; 3838 } 3839 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 3840 3841 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 3842 { 3843 struct rtw89_btc *btc = &rtwdev->btc; 3844 struct rtw89_btc_dm *dm = &btc->dm; 3845 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 3846 int i; 3847 3848 if (wl) 3849 return 0; 3850 3851 for (i = 0; i < RTW89_PHY_MAX; i++) { 3852 g[i].gnt_bt_sw_en = 1; 3853 g[i].gnt_bt = 1; 3854 g[i].gnt_wl_sw_en = 1; 3855 g[i].gnt_wl = 0; 3856 } 3857 3858 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 3859 } 3860 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 3861 3862 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 3863 { 3864 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 3865 3866 return FIELD_GET(B_AX_LTE_MUX_CTRL_PATH >> 24, val); 3867 } 3868 3869 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 3870 { 3871 u32 reg; 3872 u16 cnt; 3873 3874 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, band); 3875 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 3876 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 3877 3878 return cnt; 3879 } 3880 3881 static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 3882 { 3883 u32 reg; 3884 u32 mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 3885 B_AX_BFMEE_HE_NDPA_EN; 3886 3887 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 3888 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 3889 if (en) { 3890 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 3891 rtw89_write32_set(rtwdev, reg, mask); 3892 } else { 3893 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 3894 rtw89_write32_clr(rtwdev, reg, mask); 3895 } 3896 } 3897 3898 static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx) 3899 { 3900 u32 reg; 3901 u32 val32; 3902 int ret; 3903 3904 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3905 if (ret) 3906 return ret; 3907 3908 /* AP mode set tx gid to 63 */ 3909 /* STA mode set tx gid to 0(default) */ 3910 reg = rtw89_mac_reg_by_idx(R_AX_BFMER_CTRL_0, mac_idx); 3911 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 3912 3913 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 3914 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 3915 3916 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 3917 val32 = FIELD_PREP(B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, BFRP_RX_STANDBY_TIMER); 3918 val32 |= FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 3919 rtw89_write32(rtwdev, reg, val32); 3920 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 3921 3922 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 3923 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 3924 B_AX_BFMEE_USE_NSTS | 3925 B_AX_BFMEE_CSI_GID_SEL | 3926 B_AX_BFMEE_CSI_FORCE_RETE_EN); 3927 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 3928 rtw89_write32(rtwdev, reg, 3929 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 3930 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 3931 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 3932 3933 return 0; 3934 } 3935 3936 static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, 3937 struct ieee80211_vif *vif, 3938 struct ieee80211_sta *sta) 3939 { 3940 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3941 u8 mac_idx = rtwvif->mac_idx; 3942 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 3943 u8 port_sel = rtwvif->port; 3944 u8 sound_dim = 3, t; 3945 u8 *phy_cap = sta->he_cap.he_cap_elem.phy_cap_info; 3946 u32 reg; 3947 u16 val; 3948 int ret; 3949 3950 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3951 if (ret) 3952 return ret; 3953 3954 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 3955 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 3956 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 3957 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 3958 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 3959 phy_cap[5]); 3960 sound_dim = min(sound_dim, t); 3961 } 3962 if ((sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 3963 (sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 3964 ldpc_en &= !!(sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 3965 stbc_en &= !!(sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 3966 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 3967 sta->vht_cap.cap); 3968 sound_dim = min(sound_dim, t); 3969 } 3970 nc = min(nc, sound_dim); 3971 nr = min(nr, sound_dim); 3972 3973 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 3974 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 3975 3976 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 3977 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 3978 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 3979 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 3980 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 3981 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 3982 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 3983 3984 if (port_sel == 0) 3985 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 3986 else 3987 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 3988 3989 rtw89_write16(rtwdev, reg, val); 3990 3991 return 0; 3992 } 3993 3994 static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev, 3995 struct ieee80211_vif *vif, 3996 struct ieee80211_sta *sta) 3997 { 3998 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3999 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 4000 u32 reg; 4001 u8 mac_idx = rtwvif->mac_idx; 4002 int ret; 4003 4004 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4005 if (ret) 4006 return ret; 4007 4008 if (sta->he_cap.has_he) { 4009 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 4010 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 4011 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 4012 } 4013 if (sta->vht_cap.vht_supported) { 4014 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 4015 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 4016 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 4017 } 4018 if (sta->ht_cap.ht_supported) { 4019 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 4020 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 4021 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 4022 } 4023 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 4024 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 4025 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 4026 rtw89_write32(rtwdev, 4027 rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 4028 rrsc); 4029 4030 return 0; 4031 } 4032 4033 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4034 struct ieee80211_sta *sta) 4035 { 4036 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4037 4038 if (rtw89_sta_has_beamformer_cap(sta)) { 4039 rtw89_debug(rtwdev, RTW89_DBG_BF, 4040 "initialize bfee for new association\n"); 4041 rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx); 4042 rtw89_mac_set_csi_para_reg(rtwdev, vif, sta); 4043 rtw89_mac_csi_rrsc(rtwdev, vif, sta); 4044 } 4045 } 4046 4047 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4048 struct ieee80211_sta *sta) 4049 { 4050 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4051 4052 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 4053 } 4054 4055 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4056 struct ieee80211_bss_conf *conf) 4057 { 4058 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4059 u8 mac_idx = rtwvif->mac_idx; 4060 __le32 *p; 4061 4062 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 4063 4064 p = (__le32 *)conf->mu_group.membership; 4065 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx), 4066 le32_to_cpu(p[0])); 4067 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx), 4068 le32_to_cpu(p[1])); 4069 4070 p = (__le32 *)conf->mu_group.position; 4071 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx), 4072 le32_to_cpu(p[0])); 4073 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx), 4074 le32_to_cpu(p[1])); 4075 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx), 4076 le32_to_cpu(p[2])); 4077 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx), 4078 le32_to_cpu(p[3])); 4079 } 4080 4081 struct rtw89_mac_bf_monitor_iter_data { 4082 struct rtw89_dev *rtwdev; 4083 struct ieee80211_sta *down_sta; 4084 int count; 4085 }; 4086 4087 static 4088 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 4089 { 4090 struct rtw89_mac_bf_monitor_iter_data *iter_data = 4091 (struct rtw89_mac_bf_monitor_iter_data *)data; 4092 struct ieee80211_sta *down_sta = iter_data->down_sta; 4093 int *count = &iter_data->count; 4094 4095 if (down_sta == sta) 4096 return; 4097 4098 if (rtw89_sta_has_beamformer_cap(sta)) 4099 (*count)++; 4100 } 4101 4102 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 4103 struct ieee80211_sta *sta, bool disconnect) 4104 { 4105 struct rtw89_mac_bf_monitor_iter_data data; 4106 4107 data.rtwdev = rtwdev; 4108 data.down_sta = disconnect ? sta : NULL; 4109 data.count = 0; 4110 ieee80211_iterate_stations_atomic(rtwdev->hw, 4111 rtw89_mac_bf_monitor_calc_iter, 4112 &data); 4113 4114 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 4115 if (data.count) 4116 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 4117 else 4118 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 4119 } 4120 4121 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 4122 { 4123 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4124 struct rtw89_vif *rtwvif; 4125 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 4126 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 4127 4128 if (en == old) 4129 return; 4130 4131 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4132 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 4133 } 4134 4135 static int 4136 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 4137 u32 tx_time) 4138 { 4139 #define MAC_AX_DFLT_TX_TIME 5280 4140 u8 mac_idx = rtwsta->rtwvif->mac_idx; 4141 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 4142 u32 reg; 4143 int ret = 0; 4144 4145 if (rtwsta->cctl_tx_time) { 4146 rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 4147 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 4148 } else { 4149 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4150 if (ret) { 4151 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 4152 return ret; 4153 } 4154 4155 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 4156 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 4157 max_tx_time >> 5); 4158 } 4159 4160 return ret; 4161 } 4162 4163 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 4164 bool resume, u32 tx_time) 4165 { 4166 int ret = 0; 4167 4168 if (!resume) { 4169 rtwsta->cctl_tx_time = true; 4170 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 4171 } else { 4172 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 4173 rtwsta->cctl_tx_time = false; 4174 } 4175 4176 return ret; 4177 } 4178 4179 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 4180 u32 *tx_time) 4181 { 4182 u8 mac_idx = rtwsta->rtwvif->mac_idx; 4183 u32 reg; 4184 int ret = 0; 4185 4186 if (rtwsta->cctl_tx_time) { 4187 *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 4188 } else { 4189 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4190 if (ret) { 4191 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 4192 return ret; 4193 } 4194 4195 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 4196 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 4197 } 4198 4199 return ret; 4200 } 4201 4202 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 4203 struct rtw89_sta *rtwsta, 4204 bool resume, u8 tx_retry) 4205 { 4206 int ret = 0; 4207 4208 rtwsta->data_tx_cnt_lmt = tx_retry; 4209 4210 if (!resume) { 4211 rtwsta->cctl_tx_retry_limit = true; 4212 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 4213 } else { 4214 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 4215 rtwsta->cctl_tx_retry_limit = false; 4216 } 4217 4218 return ret; 4219 } 4220 4221 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 4222 struct rtw89_sta *rtwsta, u8 *tx_retry) 4223 { 4224 u8 mac_idx = rtwsta->rtwvif->mac_idx; 4225 u32 reg; 4226 int ret = 0; 4227 4228 if (rtwsta->cctl_tx_retry_limit) { 4229 *tx_retry = rtwsta->data_tx_cnt_lmt; 4230 } else { 4231 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4232 if (ret) { 4233 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 4234 return ret; 4235 } 4236 4237 reg = rtw89_mac_reg_by_idx(R_AX_TXCNT, mac_idx); 4238 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 4239 } 4240 4241 return ret; 4242 } 4243 4244 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 4245 struct rtw89_vif *rtwvif, bool en) 4246 { 4247 u8 mac_idx = rtwvif->mac_idx; 4248 u16 set = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0; 4249 u32 reg; 4250 u32 ret; 4251 4252 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4253 if (ret) 4254 return ret; 4255 4256 reg = rtw89_mac_reg_by_idx(R_AX_MUEDCA_EN, mac_idx); 4257 if (en) 4258 rtw89_write16_set(rtwdev, reg, set); 4259 else 4260 rtw89_write16_clr(rtwdev, reg, set); 4261 4262 return 0; 4263 } 4264 4265 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 4266 { 4267 u32 val32; 4268 int ret; 4269 4270 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 4271 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 4272 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 4273 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 4274 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 4275 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 4276 4277 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 4278 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 4279 if (ret) { 4280 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 4281 offset, val, mask); 4282 return ret; 4283 } 4284 4285 return 0; 4286 } 4287 EXPORT_SYMBOL(rtw89_mac_write_xtal_si); 4288 4289 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 4290 { 4291 u32 val32; 4292 int ret; 4293 4294 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 4295 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 4296 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 4297 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 4298 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 4299 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 4300 4301 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 4302 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 4303 if (ret) { 4304 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 4305 return ret; 4306 } 4307 4308 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 4309 4310 return 0; 4311 } 4312