1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "fw.h" 9 #include "mac.h" 10 #include "ps.h" 11 #include "reg.h" 12 #include "util.h" 13 14 const u32 rtw89_mac_mem_base_addrs[RTW89_MAC_MEM_NUM] = { 15 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 16 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 17 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 18 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 19 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 20 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 21 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 22 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 23 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 24 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 25 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 26 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 27 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 28 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 29 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 30 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 31 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 32 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 33 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 34 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 35 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 36 }; 37 38 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 39 u32 val, enum rtw89_mac_mem_sel sel) 40 { 41 u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; 42 43 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); 44 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, val); 45 } 46 47 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 48 enum rtw89_mac_mem_sel sel) 49 { 50 u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; 51 52 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); 53 return rtw89_read32(rtwdev, R_AX_INDIR_ACCESS_ENTRY); 54 } 55 56 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, 57 enum rtw89_mac_hwmod_sel sel) 58 { 59 u32 val, r_val; 60 61 if (sel == RTW89_DMAC_SEL) { 62 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 63 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 64 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 65 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 66 val = B_AX_CMAC_EN; 67 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 68 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 69 val = B_AX_CMAC1_FEN; 70 } else { 71 return -EINVAL; 72 } 73 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 74 (val & r_val) != val) 75 return -EFAULT; 76 77 return 0; 78 } 79 80 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 81 { 82 u8 lte_ctrl; 83 int ret; 84 85 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 86 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 87 if (ret) 88 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 89 90 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 91 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 92 93 return ret; 94 } 95 96 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 97 { 98 u8 lte_ctrl; 99 int ret; 100 101 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 102 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 103 if (ret) 104 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 105 106 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 107 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 108 109 return ret; 110 } 111 112 static 113 int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 114 { 115 u32 ctrl_reg, data_reg, ctrl_data; 116 u32 val; 117 int ret; 118 119 switch (ctrl->type) { 120 case DLE_CTRL_TYPE_WDE: 121 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 122 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 123 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 124 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 125 B_AX_WDE_DFI_ACTIVE; 126 break; 127 case DLE_CTRL_TYPE_PLE: 128 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 129 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 130 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 131 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 132 B_AX_PLE_DFI_ACTIVE; 133 break; 134 default: 135 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 136 return -EINVAL; 137 } 138 139 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 140 141 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 142 1, 1000, false, rtwdev, ctrl_reg); 143 if (ret) { 144 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 145 ctrl_reg, ctrl_data); 146 return ret; 147 } 148 149 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 150 return 0; 151 } 152 153 static int dle_dfi_quota(struct rtw89_dev *rtwdev, 154 struct rtw89_mac_dle_dfi_quota *quota) 155 { 156 struct rtw89_mac_dle_dfi_ctrl ctrl; 157 int ret; 158 159 ctrl.type = quota->dle_type; 160 ctrl.target = DLE_DFI_TYPE_QUOTA; 161 ctrl.addr = quota->qtaid; 162 ret = dle_dfi_ctrl(rtwdev, &ctrl); 163 if (ret) { 164 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 165 return ret; 166 } 167 168 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 169 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 170 return 0; 171 } 172 173 static int dle_dfi_qempty(struct rtw89_dev *rtwdev, 174 struct rtw89_mac_dle_dfi_qempty *qempty) 175 { 176 struct rtw89_mac_dle_dfi_ctrl ctrl; 177 u32 ret; 178 179 ctrl.type = qempty->dle_type; 180 ctrl.target = DLE_DFI_TYPE_QEMPTY; 181 ctrl.addr = qempty->grpsel; 182 ret = dle_dfi_ctrl(rtwdev, &ctrl); 183 if (ret) { 184 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 185 return ret; 186 } 187 188 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 189 return 0; 190 } 191 192 static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev) 193 { 194 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 195 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 196 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 197 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 198 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 199 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 200 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 201 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 202 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 203 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 204 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 205 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 206 } 207 208 static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) 209 { 210 struct rtw89_mac_dle_dfi_qempty qempty; 211 struct rtw89_mac_dle_dfi_quota quota; 212 struct rtw89_mac_dle_dfi_ctrl ctrl; 213 u32 val, not_empty, i; 214 int ret; 215 216 qempty.dle_type = DLE_CTRL_TYPE_PLE; 217 qempty.grpsel = 0; 218 qempty.qempty = ~(u32)0; 219 ret = dle_dfi_qempty(rtwdev, &qempty); 220 if (ret) 221 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 222 else 223 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 224 225 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 226 if (!(not_empty & BIT(0))) 227 continue; 228 ctrl.type = DLE_CTRL_TYPE_PLE; 229 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 230 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 231 FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i); 232 ret = dle_dfi_ctrl(rtwdev, &ctrl); 233 if (ret) 234 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 235 else 236 rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i, 237 FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK, 238 ctrl.out_data)); 239 } 240 241 quota.dle_type = DLE_CTRL_TYPE_PLE; 242 quota.qtaid = 6; 243 ret = dle_dfi_quota(rtwdev, "a); 244 if (ret) 245 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 246 else 247 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 248 quota.rsv_pgnum, quota.use_pgnum); 249 250 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 251 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n", 252 FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val)); 253 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n", 254 FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val)); 255 256 dump_err_status_dispatcher(rtwdev); 257 } 258 259 static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 260 enum mac_ax_err_info err) 261 { 262 u32 dbg, event; 263 264 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 265 event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg); 266 267 switch (event) { 268 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 269 rtw89_info(rtwdev, "quota lost!\n"); 270 rtw89_mac_dump_qta_lost(rtwdev); 271 break; 272 default: 273 break; 274 } 275 } 276 277 static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev, 278 enum mac_ax_err_info err) 279 { 280 u32 dmac_err, cmac_err; 281 282 if (err != MAC_AX_ERR_L1_ERR_DMAC && 283 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 284 err != MAC_AX_ERR_L0_ERR_CMAC0 && 285 err != MAC_AX_ERR_L0_ERR_CMAC1) 286 return; 287 288 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 289 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 290 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 291 292 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR); 293 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR =0x%08x\n", cmac_err); 294 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 295 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR =0x%08x\n", dmac_err); 296 297 if (dmac_err) { 298 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG =0x%08x ", 299 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG)); 300 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG =0x%08x\n", 301 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG)); 302 } 303 304 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 305 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR =0x%08x ", 306 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 307 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR =0x%08x\n", 308 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 309 } 310 311 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 312 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR =0x%08x\n", 313 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 314 rtw89_info(rtwdev, "SEC_local_Register 0x9D00 =0x%08x\n", 315 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 316 rtw89_info(rtwdev, "SEC_local_Register 0x9D04 =0x%08x\n", 317 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 318 rtw89_info(rtwdev, "SEC_local_Register 0x9D10 =0x%08x\n", 319 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 320 rtw89_info(rtwdev, "SEC_local_Register 0x9D14 =0x%08x\n", 321 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 322 rtw89_info(rtwdev, "SEC_local_Register 0x9D18 =0x%08x\n", 323 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 324 rtw89_info(rtwdev, "SEC_local_Register 0x9D20 =0x%08x\n", 325 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 326 rtw89_info(rtwdev, "SEC_local_Register 0x9D24 =0x%08x\n", 327 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 328 rtw89_info(rtwdev, "SEC_local_Register 0x9D28 =0x%08x\n", 329 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 330 rtw89_info(rtwdev, "SEC_local_Register 0x9D2C =0x%08x\n", 331 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 332 } 333 334 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 335 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR =0x%08x ", 336 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 337 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR =0x%08x\n", 338 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 339 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR =0x%08x ", 340 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 341 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR =0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 343 } 344 345 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 346 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR =0x%08x ", 347 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 348 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR= 0x%08x\n", 349 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 350 } 351 352 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 353 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ", 354 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 355 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 356 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 357 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ", 358 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 359 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 360 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 361 dump_err_status_dispatcher(rtwdev); 362 } 363 364 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 365 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 366 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 367 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 368 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 369 } 370 371 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 372 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ", 373 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 374 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 375 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 376 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ", 377 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 378 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 379 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 380 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 381 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 382 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 383 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 384 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 385 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 386 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 387 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 388 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 389 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 390 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 391 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 392 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 393 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 394 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 395 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 396 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 397 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 398 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 399 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 400 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 401 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 402 dump_err_status_dispatcher(rtwdev); 403 } 404 405 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 406 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ", 407 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 408 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n", 409 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 410 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ", 411 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 412 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n", 413 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 414 } 415 416 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) 417 dump_err_status_dispatcher(rtwdev); 418 419 if (dmac_err & B_AX_DLE_CPUIO_ERR_FLAG) { 420 rtw89_info(rtwdev, "R_AX_CPUIO_ERR_IMR=0x%08x ", 421 rtw89_read32(rtwdev, R_AX_CPUIO_ERR_IMR)); 422 rtw89_info(rtwdev, "R_AX_CPUIO_ERR_ISR=0x%08x\n", 423 rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR)); 424 } 425 426 if (dmac_err & BIT(11)) { 427 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 428 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 429 } 430 431 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 432 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR=0x%08x ", 433 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR)); 434 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR=0x%04x\n", 435 rtw89_read16(rtwdev, R_AX_SCHEDULE_ERR_ISR)); 436 } 437 438 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 439 rtw89_info(rtwdev, "R_AX_PTCL_IMR0=0x%08x ", 440 rtw89_read32(rtwdev, R_AX_PTCL_IMR0)); 441 rtw89_info(rtwdev, "R_AX_PTCL_ISR0=0x%08x\n", 442 rtw89_read32(rtwdev, R_AX_PTCL_ISR0)); 443 } 444 445 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 446 rtw89_info(rtwdev, "R_AX_DLE_CTRL=0x%08x\n", 447 rtw89_read32(rtwdev, R_AX_DLE_CTRL)); 448 } 449 450 if (cmac_err & B_AX_PHYINTF_ERR_IND) { 451 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR=0x%08x\n", 452 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR)); 453 } 454 455 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 456 rtw89_info(rtwdev, "R_AX_TXPWR_IMR=0x%08x ", 457 rtw89_read32(rtwdev, R_AX_TXPWR_IMR)); 458 rtw89_info(rtwdev, "R_AX_TXPWR_ISR=0x%08x\n", 459 rtw89_read32(rtwdev, R_AX_TXPWR_ISR)); 460 } 461 462 if (cmac_err & B_AX_WMAC_RX_ERR_IND) { 463 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x ", 464 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL)); 465 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR=0x%08x\n", 466 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR)); 467 } 468 469 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 470 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR=0x%08x ", 471 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR)); 472 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x\n", 473 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL)); 474 } 475 476 rtwdev->hci.ops->dump_err_status(rtwdev); 477 478 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 479 rtw89_mac_dump_l0_to_l1(rtwdev, err); 480 481 rtw89_info(rtwdev, "<---\n"); 482 } 483 484 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 485 { 486 u32 err, err_scnr; 487 int ret; 488 489 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 490 false, rtwdev, R_AX_HALT_C2H_CTRL); 491 if (ret) { 492 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 493 return ret; 494 } 495 496 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 497 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 498 499 err_scnr = RTW89_ERROR_SCENARIO(err); 500 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 501 err = MAC_AX_ERR_CPU_EXCEPTION; 502 else if (err_scnr == RTW89_WCPU_ASSERTION) 503 err = MAC_AX_ERR_ASSERTION; 504 505 rtw89_fw_st_dbg_dump(rtwdev); 506 rtw89_mac_dump_err_status(rtwdev, err); 507 508 return err; 509 } 510 EXPORT_SYMBOL(rtw89_mac_get_err_status); 511 512 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 513 { 514 u32 halt; 515 int ret = 0; 516 517 if (err > MAC_AX_SET_ERR_MAX) { 518 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 519 return -EINVAL; 520 } 521 522 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 523 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 524 if (ret) { 525 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 526 return -EFAULT; 527 } 528 529 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 530 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 531 532 return 0; 533 } 534 EXPORT_SYMBOL(rtw89_mac_set_err_status); 535 536 static int hfc_reset_param(struct rtw89_dev *rtwdev) 537 { 538 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 539 struct rtw89_hfc_param_ini param_ini = {NULL}; 540 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 541 542 switch (rtwdev->hci.type) { 543 case RTW89_HCI_TYPE_PCIE: 544 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 545 param->en = 0; 546 break; 547 default: 548 return -EINVAL; 549 } 550 551 if (param_ini.pub_cfg) 552 param->pub_cfg = *param_ini.pub_cfg; 553 554 if (param_ini.prec_cfg) { 555 param->prec_cfg = *param_ini.prec_cfg; 556 rtwdev->hal.sw_amsdu_max_size = 557 param->prec_cfg.wp_ch07_prec * HFC_PAGE_UNIT; 558 } 559 560 if (param_ini.ch_cfg) 561 param->ch_cfg = param_ini.ch_cfg; 562 563 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 564 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 565 param->mode = param_ini.mode; 566 567 return 0; 568 } 569 570 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 571 { 572 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 573 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 574 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 575 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 576 577 if (ch >= RTW89_DMA_CH_NUM) 578 return -EINVAL; 579 580 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 581 ch_cfg[ch].max > pub_cfg->pub_max) 582 return -EINVAL; 583 if (ch_cfg[ch].grp >= grp_num) 584 return -EINVAL; 585 586 return 0; 587 } 588 589 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 590 { 591 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 592 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 593 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 594 595 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 596 if (rtwdev->chip->chip_id == RTL8852A) 597 return 0; 598 else 599 return -EFAULT; 600 } 601 602 return 0; 603 } 604 605 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 606 { 607 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 608 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 609 610 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 611 return -EFAULT; 612 613 return 0; 614 } 615 616 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 617 { 618 const struct rtw89_chip_info *chip = rtwdev->chip; 619 const struct rtw89_page_regs *regs = chip->page_regs; 620 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 621 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 622 int ret = 0; 623 u32 val = 0; 624 625 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 626 if (ret) 627 return ret; 628 629 ret = hfc_ch_cfg_chk(rtwdev, ch); 630 if (ret) 631 return ret; 632 633 if (ch > RTW89_DMA_B1HI) 634 return -EINVAL; 635 636 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 637 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 638 (cfg[ch].grp ? B_AX_GRP : 0); 639 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 640 641 return 0; 642 } 643 644 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 645 { 646 const struct rtw89_chip_info *chip = rtwdev->chip; 647 const struct rtw89_page_regs *regs = chip->page_regs; 648 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 649 struct rtw89_hfc_ch_info *info = param->ch_info; 650 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 651 u32 val; 652 u32 ret; 653 654 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 655 if (ret) 656 return ret; 657 658 if (ch > RTW89_DMA_H2C) 659 return -EINVAL; 660 661 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 662 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 663 if (ch < RTW89_DMA_H2C) 664 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 665 else 666 info[ch].used = cfg[ch].min - info[ch].aval; 667 668 return 0; 669 } 670 671 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 672 { 673 const struct rtw89_chip_info *chip = rtwdev->chip; 674 const struct rtw89_page_regs *regs = chip->page_regs; 675 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 676 u32 val; 677 int ret; 678 679 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 680 if (ret) 681 return ret; 682 683 ret = hfc_pub_cfg_chk(rtwdev); 684 if (ret) 685 return ret; 686 687 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 688 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 689 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 690 691 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 692 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 693 694 return 0; 695 } 696 697 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 698 { 699 const struct rtw89_chip_info *chip = rtwdev->chip; 700 const struct rtw89_page_regs *regs = chip->page_regs; 701 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 702 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 703 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 704 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 705 u32 val; 706 int ret; 707 708 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 709 if (ret) 710 return ret; 711 712 val = rtw89_read32(rtwdev, regs->pub_page_info1); 713 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 714 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 715 val = rtw89_read32(rtwdev, regs->pub_page_info3); 716 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 717 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 718 info->pub_aval = 719 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 720 B_AX_PUB_AVAL_PG_MASK); 721 info->wp_aval = 722 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 723 B_AX_WP_AVAL_PG_MASK); 724 725 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 726 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 727 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 728 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 729 prec_cfg->ch011_full_cond = 730 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 731 prec_cfg->h2c_full_cond = 732 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 733 prec_cfg->wp_ch07_full_cond = 734 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 735 prec_cfg->wp_ch811_full_cond = 736 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 737 738 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 739 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 740 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 741 742 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 743 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 744 745 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 746 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 747 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 748 749 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 750 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 751 752 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 753 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 754 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 755 756 ret = hfc_pub_info_chk(rtwdev); 757 if (param->en && ret) 758 return ret; 759 760 return 0; 761 } 762 763 static void hfc_h2c_cfg(struct rtw89_dev *rtwdev) 764 { 765 const struct rtw89_chip_info *chip = rtwdev->chip; 766 const struct rtw89_page_regs *regs = chip->page_regs; 767 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 768 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 769 u32 val; 770 771 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 772 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 773 774 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 775 B_AX_HCI_FC_CH12_FULL_COND_MASK, 776 prec_cfg->h2c_full_cond); 777 } 778 779 static void hfc_mix_cfg(struct rtw89_dev *rtwdev) 780 { 781 const struct rtw89_chip_info *chip = rtwdev->chip; 782 const struct rtw89_page_regs *regs = chip->page_regs; 783 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 784 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 785 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 786 u32 val; 787 788 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 789 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 790 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 791 792 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 793 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 794 795 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 796 B_AX_PREC_PAGE_WP_CH07_MASK) | 797 u32_encode_bits(prec_cfg->wp_ch811_prec, 798 B_AX_PREC_PAGE_WP_CH811_MASK); 799 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 800 801 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 802 param->mode, B_AX_HCI_FC_MODE_MASK); 803 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 804 B_AX_HCI_FC_WD_FULL_COND_MASK); 805 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 806 B_AX_HCI_FC_CH12_FULL_COND_MASK); 807 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 808 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 809 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 810 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 811 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 812 } 813 814 static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 815 { 816 const struct rtw89_chip_info *chip = rtwdev->chip; 817 const struct rtw89_page_regs *regs = chip->page_regs; 818 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 819 u32 val; 820 821 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 822 param->en = en; 823 param->h2c_en = h2c_en; 824 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 825 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 826 (val & ~B_AX_HCI_FC_CH12_EN); 827 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 828 } 829 830 static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 831 { 832 const struct rtw89_chip_info *chip = rtwdev->chip; 833 u32 dma_ch_mask = chip->dma_ch_mask; 834 u8 ch; 835 u32 ret = 0; 836 837 if (reset) 838 ret = hfc_reset_param(rtwdev); 839 if (ret) 840 return ret; 841 842 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 843 if (ret) 844 return ret; 845 846 hfc_func_en(rtwdev, false, false); 847 848 if (!en && h2c_en) { 849 hfc_h2c_cfg(rtwdev); 850 hfc_func_en(rtwdev, en, h2c_en); 851 return ret; 852 } 853 854 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 855 if (dma_ch_mask & BIT(ch)) 856 continue; 857 ret = hfc_ch_ctrl(rtwdev, ch); 858 if (ret) 859 return ret; 860 } 861 862 ret = hfc_pub_ctrl(rtwdev); 863 if (ret) 864 return ret; 865 866 hfc_mix_cfg(rtwdev); 867 if (en || h2c_en) { 868 hfc_func_en(rtwdev, en, h2c_en); 869 udelay(10); 870 } 871 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 872 if (dma_ch_mask & BIT(ch)) 873 continue; 874 ret = hfc_upd_ch_info(rtwdev, ch); 875 if (ret) 876 return ret; 877 } 878 ret = hfc_upd_mix_info(rtwdev); 879 880 return ret; 881 } 882 883 #define PWR_POLL_CNT 2000 884 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 885 const struct rtw89_pwr_cfg *cfg) 886 { 887 u8 val = 0; 888 int ret; 889 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 890 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 891 892 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 893 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 894 895 if (!ret) 896 return 0; 897 898 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 899 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 900 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 901 902 return -EBUSY; 903 } 904 905 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 906 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 907 { 908 const struct rtw89_pwr_cfg *cur_cfg; 909 u32 addr; 910 u8 val; 911 912 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 913 if (!(cur_cfg->intf_msk & intf_msk) || 914 !(cur_cfg->cv_msk & cv_msk)) 915 continue; 916 917 switch (cur_cfg->cmd) { 918 case PWR_CMD_WRITE: 919 addr = cur_cfg->addr; 920 921 if (cur_cfg->base == PWR_BASE_SDIO) 922 addr |= SDIO_LOCAL_BASE_ADDR; 923 924 val = rtw89_read8(rtwdev, addr); 925 val &= ~(cur_cfg->msk); 926 val |= (cur_cfg->val & cur_cfg->msk); 927 928 rtw89_write8(rtwdev, addr, val); 929 break; 930 case PWR_CMD_POLL: 931 if (pwr_cmd_poll(rtwdev, cur_cfg)) 932 return -EBUSY; 933 break; 934 case PWR_CMD_DELAY: 935 if (cur_cfg->val == PWR_DELAY_US) 936 udelay(cur_cfg->addr); 937 else 938 fsleep(cur_cfg->addr * 1000); 939 break; 940 default: 941 return -EINVAL; 942 } 943 } 944 945 return 0; 946 } 947 948 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 949 const struct rtw89_pwr_cfg * const *cfg_seq) 950 { 951 int ret; 952 953 for (; *cfg_seq; cfg_seq++) { 954 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 955 PWR_INTF_MSK_PCIE, *cfg_seq); 956 if (ret) 957 return -EBUSY; 958 } 959 960 return 0; 961 } 962 963 static enum rtw89_rpwm_req_pwr_state 964 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 965 { 966 enum rtw89_rpwm_req_pwr_state state; 967 968 switch (rtwdev->ps_mode) { 969 case RTW89_PS_MODE_RFOFF: 970 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 971 break; 972 case RTW89_PS_MODE_CLK_GATED: 973 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 974 break; 975 case RTW89_PS_MODE_PWR_GATED: 976 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 977 break; 978 default: 979 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 980 break; 981 } 982 return state; 983 } 984 985 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 986 enum rtw89_rpwm_req_pwr_state req_pwr_state, 987 bool notify_wake) 988 { 989 u16 request; 990 991 spin_lock_bh(&rtwdev->rpwm_lock); 992 993 request = rtw89_read16(rtwdev, R_AX_RPWM); 994 request ^= request | PS_RPWM_TOGGLE; 995 request |= req_pwr_state; 996 997 if (notify_wake) { 998 request |= PS_RPWM_NOTIFY_WAKE; 999 } else { 1000 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1001 RPWM_SEQ_NUM_MAX; 1002 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1003 rtwdev->mac.rpwm_seq_num); 1004 1005 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1006 request |= PS_RPWM_ACK; 1007 } 1008 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1009 1010 spin_unlock_bh(&rtwdev->rpwm_lock); 1011 } 1012 1013 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1014 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1015 { 1016 bool request_deep_mode; 1017 bool in_deep_mode; 1018 u8 rpwm_req_num; 1019 u8 cpwm_rsp_seq; 1020 u8 cpwm_seq; 1021 u8 cpwm_status; 1022 1023 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1024 request_deep_mode = true; 1025 else 1026 request_deep_mode = false; 1027 1028 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1029 in_deep_mode = true; 1030 else 1031 in_deep_mode = false; 1032 1033 if (request_deep_mode != in_deep_mode) 1034 return -EPERM; 1035 1036 if (request_deep_mode) 1037 return 0; 1038 1039 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1040 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1041 PS_CPWM_RSP_SEQ_NUM); 1042 1043 if (rpwm_req_num != cpwm_rsp_seq) 1044 return -EPERM; 1045 1046 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1047 CPWM_SEQ_NUM_MAX; 1048 1049 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1050 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1051 return -EPERM; 1052 1053 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1054 if (cpwm_status != req_pwr_state) 1055 return -EPERM; 1056 1057 return 0; 1058 } 1059 1060 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1061 { 1062 enum rtw89_rpwm_req_pwr_state state; 1063 unsigned long delay = enter ? 10 : 150; 1064 int ret; 1065 int i; 1066 1067 if (enter) 1068 state = rtw89_mac_get_req_pwr_state(rtwdev); 1069 else 1070 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1071 1072 for (i = 0; i < RPWM_TRY_CNT; i++) { 1073 rtw89_mac_send_rpwm(rtwdev, state, false); 1074 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1075 !ret, delay, 15000, false, 1076 rtwdev, state); 1077 if (!ret) 1078 break; 1079 1080 if (i == RPWM_TRY_CNT - 1) 1081 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1082 enter ? "entering" : "leaving"); 1083 else 1084 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1085 "%d time firmware failed to ack for %s ps mode\n", 1086 i + 1, enter ? "entering" : "leaving"); 1087 } 1088 } 1089 1090 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1091 { 1092 enum rtw89_rpwm_req_pwr_state state; 1093 1094 state = rtw89_mac_get_req_pwr_state(rtwdev); 1095 rtw89_mac_send_rpwm(rtwdev, state, true); 1096 } 1097 1098 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1099 { 1100 #define PWR_ACT 1 1101 const struct rtw89_chip_info *chip = rtwdev->chip; 1102 const struct rtw89_pwr_cfg * const *cfg_seq; 1103 int (*cfg_func)(struct rtw89_dev *rtwdev); 1104 int ret; 1105 u8 val; 1106 1107 if (on) { 1108 cfg_seq = chip->pwr_on_seq; 1109 cfg_func = chip->ops->pwr_on_func; 1110 } else { 1111 cfg_seq = chip->pwr_off_seq; 1112 cfg_func = chip->ops->pwr_off_func; 1113 } 1114 1115 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1116 __rtw89_leave_ps_mode(rtwdev); 1117 1118 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1119 if (on && val == PWR_ACT) { 1120 rtw89_err(rtwdev, "MAC has already powered on\n"); 1121 return -EBUSY; 1122 } 1123 1124 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1125 if (ret) 1126 return ret; 1127 1128 if (on) { 1129 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1130 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1131 } else { 1132 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1133 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1134 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1135 rtw89_set_entity_state(rtwdev, false); 1136 } 1137 1138 return 0; 1139 #undef PWR_ACT 1140 } 1141 1142 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1143 { 1144 rtw89_mac_power_switch(rtwdev, false); 1145 } 1146 1147 static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1148 { 1149 u32 func_en = 0; 1150 u32 ck_en = 0; 1151 u32 c1pc_en = 0; 1152 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1153 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1154 1155 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1156 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1157 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1158 B_AX_CMAC_CRPRT; 1159 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1160 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1161 B_AX_RMAC_CKEN; 1162 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1163 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1164 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1165 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1166 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1167 1168 if (en) { 1169 if (mac_idx == RTW89_MAC_1) { 1170 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1171 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1172 B_AX_R_SYM_ISO_CMAC12PP); 1173 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1174 B_AX_CMAC1_FEN); 1175 } 1176 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1177 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1178 } else { 1179 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1180 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1181 if (mac_idx == RTW89_MAC_1) { 1182 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1183 B_AX_CMAC1_FEN); 1184 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1185 B_AX_R_SYM_ISO_CMAC12PP); 1186 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1187 } 1188 } 1189 1190 return 0; 1191 } 1192 1193 static int dmac_func_en(struct rtw89_dev *rtwdev) 1194 { 1195 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1196 u32 val32; 1197 1198 if (chip_id == RTL8852C) 1199 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1200 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1201 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1202 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1203 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1204 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1205 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1206 else 1207 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1208 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1209 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1210 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1211 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1212 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1213 B_AX_DMAC_CRPRT); 1214 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1215 1216 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1217 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1218 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1219 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1220 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1221 1222 return 0; 1223 } 1224 1225 static int chip_func_en(struct rtw89_dev *rtwdev) 1226 { 1227 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1228 1229 if (chip_id == RTL8852A || chip_id == RTL8852B) 1230 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1231 B_AX_OCP_L1_MASK); 1232 1233 return 0; 1234 } 1235 1236 static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev) 1237 { 1238 int ret; 1239 1240 ret = dmac_func_en(rtwdev); 1241 if (ret) 1242 return ret; 1243 1244 ret = cmac_func_en(rtwdev, 0, true); 1245 if (ret) 1246 return ret; 1247 1248 ret = chip_func_en(rtwdev); 1249 if (ret) 1250 return ret; 1251 1252 return ret; 1253 } 1254 1255 const struct rtw89_mac_size_set rtw89_mac_size = { 1256 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1257 /* PCIE 64 */ 1258 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1259 /* DLFW */ 1260 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1261 /* PCIE 64 */ 1262 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1263 /* DLFW */ 1264 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1265 /* 8852C DLFW */ 1266 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1267 /* 8852C PCIE SCC */ 1268 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1269 /* PCIE */ 1270 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1271 /* DLFW */ 1272 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1273 /* PCIE 64 */ 1274 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1275 /* DLFW */ 1276 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1277 /* 8852C DLFW */ 1278 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1279 /* 8852C PCIE SCC */ 1280 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1281 /* PCIE 64 */ 1282 .wde_qt0 = {3792, 196, 0, 107,}, 1283 /* DLFW */ 1284 .wde_qt4 = {0, 0, 0, 0,}, 1285 /* PCIE 64 */ 1286 .wde_qt6 = {448, 48, 0, 16,}, 1287 /* 8852C DLFW */ 1288 .wde_qt17 = {0, 0, 0, 0,}, 1289 /* 8852C PCIE SCC */ 1290 .wde_qt18 = {3228, 60, 0, 40,}, 1291 /* PCIE SCC */ 1292 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1293 /* PCIE SCC */ 1294 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1295 /* DLFW */ 1296 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1297 /* PCIE 64 */ 1298 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1299 /* DLFW 52C */ 1300 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1301 /* DLFW 52C */ 1302 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1303 /* 8852C PCIE SCC */ 1304 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1305 /* 8852C PCIE SCC */ 1306 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1307 /* PCIE 64 */ 1308 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1309 }; 1310 EXPORT_SYMBOL(rtw89_mac_size); 1311 1312 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1313 enum rtw89_qta_mode mode) 1314 { 1315 struct rtw89_mac_info *mac = &rtwdev->mac; 1316 const struct rtw89_dle_mem *cfg; 1317 1318 cfg = &rtwdev->chip->dle_mem[mode]; 1319 if (!cfg) 1320 return NULL; 1321 1322 if (cfg->mode != mode) { 1323 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1324 return NULL; 1325 } 1326 1327 mac->dle_info.wde_pg_size = cfg->wde_size->pge_size; 1328 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1329 mac->dle_info.qta_mode = mode; 1330 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1331 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1332 1333 return cfg; 1334 } 1335 1336 static inline u32 dle_used_size(const struct rtw89_dle_size *wde, 1337 const struct rtw89_dle_size *ple) 1338 { 1339 return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1340 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1341 } 1342 1343 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 1344 enum rtw89_qta_mode mode) 1345 { 1346 u32 size = rtwdev->chip->fifo_size; 1347 1348 if (mode == RTW89_QTA_SCC) 1349 size -= rtwdev->chip->dle_scc_rsvd_size; 1350 1351 return size; 1352 } 1353 1354 static void dle_func_en(struct rtw89_dev *rtwdev, bool enable) 1355 { 1356 if (enable) 1357 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1358 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1359 else 1360 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1361 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1362 } 1363 1364 static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable) 1365 { 1366 if (enable) 1367 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, 1368 B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); 1369 else 1370 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, 1371 B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); 1372 } 1373 1374 static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1375 { 1376 const struct rtw89_dle_size *size_cfg; 1377 u32 val; 1378 u8 bound = 0; 1379 1380 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1381 size_cfg = cfg->wde_size; 1382 1383 switch (size_cfg->pge_size) { 1384 default: 1385 case RTW89_WDE_PG_64: 1386 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1387 B_AX_WDE_PAGE_SEL_MASK); 1388 break; 1389 case RTW89_WDE_PG_128: 1390 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1391 B_AX_WDE_PAGE_SEL_MASK); 1392 break; 1393 case RTW89_WDE_PG_256: 1394 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1395 return -EINVAL; 1396 } 1397 1398 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1399 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1400 B_AX_WDE_FREE_PAGE_NUM_MASK); 1401 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1402 1403 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1404 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1405 * size_cfg->pge_size / DLE_BOUND_UNIT; 1406 size_cfg = cfg->ple_size; 1407 1408 switch (size_cfg->pge_size) { 1409 default: 1410 case RTW89_PLE_PG_64: 1411 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1412 return -EINVAL; 1413 case RTW89_PLE_PG_128: 1414 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1415 B_AX_PLE_PAGE_SEL_MASK); 1416 break; 1417 case RTW89_PLE_PG_256: 1418 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1419 B_AX_PLE_PAGE_SEL_MASK); 1420 break; 1421 } 1422 1423 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1424 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1425 B_AX_PLE_FREE_PAGE_NUM_MASK); 1426 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1427 1428 return 0; 1429 } 1430 1431 #define INVALID_QT_WCPU U16_MAX 1432 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1433 do { \ 1434 val = ((_min_x) & \ 1435 B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1436 (((_max_x) << 16) & \ 1437 B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1438 rtw89_write32(rtwdev, \ 1439 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1440 val); \ 1441 } while (0) 1442 #define SET_QUOTA(_x, _module, _idx) \ 1443 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1444 1445 static void wde_quota_cfg(struct rtw89_dev *rtwdev, 1446 const struct rtw89_wde_quota *min_cfg, 1447 const struct rtw89_wde_quota *max_cfg, 1448 u16 ext_wde_min_qt_wcpu) 1449 { 1450 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1451 ext_wde_min_qt_wcpu : min_cfg->wcpu; 1452 u32 val; 1453 1454 SET_QUOTA(hif, WDE, 0); 1455 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1456 SET_QUOTA(pkt_in, WDE, 3); 1457 SET_QUOTA(cpu_io, WDE, 4); 1458 } 1459 1460 static void ple_quota_cfg(struct rtw89_dev *rtwdev, 1461 const struct rtw89_ple_quota *min_cfg, 1462 const struct rtw89_ple_quota *max_cfg) 1463 { 1464 u32 val; 1465 1466 SET_QUOTA(cma0_tx, PLE, 0); 1467 SET_QUOTA(cma1_tx, PLE, 1); 1468 SET_QUOTA(c2h, PLE, 2); 1469 SET_QUOTA(h2c, PLE, 3); 1470 SET_QUOTA(wcpu, PLE, 4); 1471 SET_QUOTA(mpdu_proc, PLE, 5); 1472 SET_QUOTA(cma0_dma, PLE, 6); 1473 SET_QUOTA(cma1_dma, PLE, 7); 1474 SET_QUOTA(bb_rpt, PLE, 8); 1475 SET_QUOTA(wd_rel, PLE, 9); 1476 SET_QUOTA(cpu_io, PLE, 10); 1477 if (rtwdev->chip->chip_id == RTL8852C) 1478 SET_QUOTA(tx_rpt, PLE, 11); 1479 } 1480 1481 #undef SET_QUOTA 1482 1483 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 1484 const struct rtw89_dle_mem *cfg, 1485 u16 ext_wde_min_qt_wcpu) 1486 { 1487 wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 1488 ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 1489 } 1490 1491 static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1492 enum rtw89_qta_mode ext_mode) 1493 { 1494 const struct rtw89_dle_mem *cfg, *ext_cfg; 1495 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 1496 int ret = 0; 1497 u32 ini; 1498 1499 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1500 if (ret) 1501 return ret; 1502 1503 cfg = get_dle_mem_cfg(rtwdev, mode); 1504 if (!cfg) { 1505 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1506 ret = -EINVAL; 1507 goto error; 1508 } 1509 1510 if (mode == RTW89_QTA_DLFW) { 1511 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 1512 if (!ext_cfg) { 1513 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 1514 ext_mode); 1515 ret = -EINVAL; 1516 goto error; 1517 } 1518 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 1519 } 1520 1521 if (dle_used_size(cfg->wde_size, cfg->ple_size) != 1522 dle_expected_used_size(rtwdev, mode)) { 1523 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 1524 ret = -EINVAL; 1525 goto error; 1526 } 1527 1528 dle_func_en(rtwdev, false); 1529 dle_clk_en(rtwdev, true); 1530 1531 ret = dle_mix_cfg(rtwdev, cfg); 1532 if (ret) { 1533 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 1534 goto error; 1535 } 1536 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 1537 1538 dle_func_en(rtwdev, true); 1539 1540 ret = read_poll_timeout(rtw89_read32, ini, 1541 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1542 2000, false, rtwdev, R_AX_WDE_INI_STATUS); 1543 if (ret) { 1544 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 1545 return ret; 1546 } 1547 1548 ret = read_poll_timeout(rtw89_read32, ini, 1549 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1550 2000, false, rtwdev, R_AX_PLE_INI_STATUS); 1551 if (ret) { 1552 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 1553 return ret; 1554 } 1555 1556 return 0; 1557 error: 1558 dle_func_en(rtwdev, false); 1559 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 1560 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 1561 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 1562 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 1563 1564 return ret; 1565 } 1566 1567 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1568 enum rtw89_qta_mode mode) 1569 { 1570 u32 reg, max_preld_size, min_rsvd_size; 1571 1572 max_preld_size = (mac_idx == RTW89_MAC_0 ? 1573 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 1574 reg = mac_idx == RTW89_MAC_0 ? 1575 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 1576 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 1577 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 1578 1579 min_rsvd_size = PRELD_AMSDU_SIZE; 1580 reg = mac_idx == RTW89_MAC_0 ? 1581 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 1582 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 1583 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 1584 1585 return 0; 1586 } 1587 1588 static bool is_qta_poh(struct rtw89_dev *rtwdev) 1589 { 1590 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 1591 } 1592 1593 static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1594 enum rtw89_qta_mode mode) 1595 { 1596 const struct rtw89_chip_info *chip = rtwdev->chip; 1597 1598 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || !is_qta_poh(rtwdev)) 1599 return 0; 1600 1601 return preload_init_set(rtwdev, mac_idx, mode); 1602 } 1603 1604 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 1605 { 1606 u32 msk32; 1607 u32 val32; 1608 1609 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 1610 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 1611 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 1612 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1613 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 1614 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 1615 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 1616 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 1617 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1618 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 1619 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1620 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1621 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 1622 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1623 1624 if ((val32 & msk32) == msk32) 1625 return true; 1626 1627 return false; 1628 } 1629 1630 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 1631 { 1632 const struct rtw89_chip_info *chip = rtwdev->chip; 1633 1634 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) 1635 return; 1636 1637 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 1638 SS2F_PATH_WLCPU); 1639 } 1640 1641 static int sta_sch_init(struct rtw89_dev *rtwdev) 1642 { 1643 u32 p_val; 1644 u8 val; 1645 int ret; 1646 1647 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1648 if (ret) 1649 return ret; 1650 1651 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 1652 val |= B_AX_SS_EN; 1653 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 1654 1655 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 1656 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 1657 if (ret) { 1658 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 1659 return ret; 1660 } 1661 1662 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 1663 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 1664 1665 _patch_ss2f_path(rtwdev); 1666 1667 return 0; 1668 } 1669 1670 static int mpdu_proc_init(struct rtw89_dev *rtwdev) 1671 { 1672 int ret; 1673 1674 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1675 if (ret) 1676 return ret; 1677 1678 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 1679 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 1680 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 1681 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 1682 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 1683 1684 return 0; 1685 } 1686 1687 static int sec_eng_init(struct rtw89_dev *rtwdev) 1688 { 1689 const struct rtw89_chip_info *chip = rtwdev->chip; 1690 u32 val = 0; 1691 int ret; 1692 1693 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1694 if (ret) 1695 return ret; 1696 1697 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 1698 /* init clock */ 1699 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 1700 /* init TX encryption */ 1701 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 1702 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 1703 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) 1704 val &= ~B_AX_TX_PARTIAL_MODE; 1705 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 1706 1707 /* init MIC ICV append */ 1708 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 1709 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 1710 1711 /* option init */ 1712 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 1713 1714 if (chip->chip_id == RTL8852C) 1715 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 1716 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 1717 1718 return 0; 1719 } 1720 1721 static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1722 { 1723 int ret; 1724 1725 ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 1726 if (ret) { 1727 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 1728 return ret; 1729 } 1730 1731 ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 1732 if (ret) { 1733 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 1734 return ret; 1735 } 1736 1737 ret = hfc_init(rtwdev, true, true, true); 1738 if (ret) { 1739 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 1740 return ret; 1741 } 1742 1743 ret = sta_sch_init(rtwdev); 1744 if (ret) { 1745 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 1746 return ret; 1747 } 1748 1749 ret = mpdu_proc_init(rtwdev); 1750 if (ret) { 1751 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 1752 return ret; 1753 } 1754 1755 ret = sec_eng_init(rtwdev); 1756 if (ret) { 1757 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 1758 return ret; 1759 } 1760 1761 return ret; 1762 } 1763 1764 static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1765 { 1766 u32 val, reg; 1767 u16 p_val; 1768 int ret; 1769 1770 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1771 if (ret) 1772 return ret; 1773 1774 reg = rtw89_mac_reg_by_idx(R_AX_ADDR_CAM_CTRL, mac_idx); 1775 1776 val = rtw89_read32(rtwdev, reg); 1777 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 1778 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 1779 rtw89_write32(rtwdev, reg, val); 1780 1781 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 1782 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 1783 if (ret) { 1784 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 1785 return ret; 1786 } 1787 1788 return 0; 1789 } 1790 1791 static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1792 { 1793 u32 ret; 1794 u32 reg; 1795 u32 val; 1796 1797 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1798 if (ret) 1799 return ret; 1800 1801 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_1, mac_idx); 1802 if (rtwdev->chip->chip_id == RTL8852C) 1803 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 1804 SIFS_MACTXEN_T1_V1); 1805 else 1806 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 1807 SIFS_MACTXEN_T1); 1808 1809 if (rtwdev->chip->chip_id == RTL8852B) { 1810 reg = rtw89_mac_reg_by_idx(R_AX_SCH_EXT_CTRL, mac_idx); 1811 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 1812 } 1813 1814 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CFG_0, mac_idx); 1815 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 1816 1817 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_0, mac_idx); 1818 if (rtwdev->chip->chip_id == RTL8852C) { 1819 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 1820 B_AX_TX_PARTIAL_MODE); 1821 if (!val) 1822 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 1823 SCH_PREBKF_24US); 1824 } else { 1825 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 1826 SCH_PREBKF_24US); 1827 } 1828 1829 return 0; 1830 } 1831 1832 static int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, 1833 enum rtw89_machdr_frame_type type, 1834 enum rtw89_mac_fwd_target fwd_target, 1835 u8 mac_idx) 1836 { 1837 u32 reg; 1838 u32 val; 1839 1840 switch (fwd_target) { 1841 case RTW89_FWD_DONT_CARE: 1842 val = RX_FLTR_FRAME_DROP; 1843 break; 1844 case RTW89_FWD_TO_HOST: 1845 val = RX_FLTR_FRAME_TO_HOST; 1846 break; 1847 case RTW89_FWD_TO_WLAN_CPU: 1848 val = RX_FLTR_FRAME_TO_WLCPU; 1849 break; 1850 default: 1851 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 1852 return -EINVAL; 1853 } 1854 1855 switch (type) { 1856 case RTW89_MGNT: 1857 reg = rtw89_mac_reg_by_idx(R_AX_MGNT_FLTR, mac_idx); 1858 break; 1859 case RTW89_CTRL: 1860 reg = rtw89_mac_reg_by_idx(R_AX_CTRL_FLTR, mac_idx); 1861 break; 1862 case RTW89_DATA: 1863 reg = rtw89_mac_reg_by_idx(R_AX_DATA_FLTR, mac_idx); 1864 break; 1865 default: 1866 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 1867 return -EINVAL; 1868 } 1869 rtw89_write32(rtwdev, reg, val); 1870 1871 return 0; 1872 } 1873 1874 static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1875 { 1876 int ret, i; 1877 u32 mac_ftlr, plcp_ftlr; 1878 1879 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1880 if (ret) 1881 return ret; 1882 1883 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 1884 ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST, 1885 mac_idx); 1886 if (ret) 1887 return ret; 1888 } 1889 mac_ftlr = rtwdev->hal.rx_fltr; 1890 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 1891 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 1892 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 1893 B_AX_HE_SIGB_CRC_CHK; 1894 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx), 1895 mac_ftlr); 1896 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx), 1897 plcp_ftlr); 1898 1899 return 0; 1900 } 1901 1902 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 1903 { 1904 u32 reg, val32; 1905 u32 b_rsp_chk_nav, b_rsp_chk_cca; 1906 1907 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 1908 B_AX_RSP_CHK_BASIC_NAV; 1909 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 1910 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 1911 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 1912 1913 switch (rtwdev->chip->chip_id) { 1914 case RTL8852A: 1915 case RTL8852B: 1916 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 1917 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 1918 rtw89_write32(rtwdev, reg, val32); 1919 1920 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 1921 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 1922 rtw89_write32(rtwdev, reg, val32); 1923 break; 1924 default: 1925 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 1926 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 1927 rtw89_write32(rtwdev, reg, val32); 1928 1929 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 1930 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 1931 rtw89_write32(rtwdev, reg, val32); 1932 break; 1933 } 1934 } 1935 1936 static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1937 { 1938 u32 val, reg; 1939 int ret; 1940 1941 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1942 if (ret) 1943 return ret; 1944 1945 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CONTROL, mac_idx); 1946 val = rtw89_read32(rtwdev, reg); 1947 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 1948 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 1949 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 1950 B_AX_CTN_CHK_INTRA_NAV | 1951 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 1952 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 1953 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 1954 B_AX_CTN_CHK_CCA_P20); 1955 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 1956 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 1957 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 1958 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 1959 B_AX_SIFS_CHK_EDCCA); 1960 1961 rtw89_write32(rtwdev, reg, val); 1962 1963 _patch_dis_resp_chk(rtwdev, mac_idx); 1964 1965 return 0; 1966 } 1967 1968 static int nav_ctrl_init(struct rtw89_dev *rtwdev) 1969 { 1970 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 1971 B_AX_WMAC_TF_UP_NAV_EN | 1972 B_AX_WMAC_NAV_UPPER_EN); 1973 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 1974 1975 return 0; 1976 } 1977 1978 static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1979 { 1980 u32 reg; 1981 int ret; 1982 1983 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1984 if (ret) 1985 return ret; 1986 reg = rtw89_mac_reg_by_idx(R_AX_RX_SR_CTRL, mac_idx); 1987 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 1988 1989 return 0; 1990 } 1991 1992 static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1993 { 1994 u32 reg; 1995 int ret; 1996 1997 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 1998 if (ret) 1999 return ret; 2000 2001 reg = rtw89_mac_reg_by_idx(R_AX_MAC_LOOPBACK, mac_idx); 2002 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2003 2004 reg = rtw89_mac_reg_by_idx(R_AX_TCR0, mac_idx); 2005 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2006 2007 reg = rtw89_mac_reg_by_idx(R_AX_TXD_FIFO_CTRL, mac_idx); 2008 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2009 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2010 2011 return 0; 2012 } 2013 2014 static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2015 { 2016 const struct rtw89_chip_info *chip = rtwdev->chip; 2017 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2018 u32 reg, val, sifs; 2019 int ret; 2020 2021 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2022 if (ret) 2023 return ret; 2024 2025 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2026 val = rtw89_read32(rtwdev, reg); 2027 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2028 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2029 2030 switch (rtwdev->chip->chip_id) { 2031 case RTL8852A: 2032 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2033 break; 2034 case RTL8852B: 2035 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2036 break; 2037 default: 2038 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2039 break; 2040 } 2041 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2042 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2043 rtw89_write32(rtwdev, reg, val); 2044 2045 reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx); 2046 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2047 2048 reg = rtw89_mac_reg_by_idx(rrsr->ref_rate.addr, mac_idx); 2049 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2050 reg = rtw89_mac_reg_by_idx(rrsr->rsc.addr, mac_idx); 2051 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2052 2053 return 0; 2054 } 2055 2056 static void rst_bacam(struct rtw89_dev *rtwdev) 2057 { 2058 u32 val32; 2059 int ret; 2060 2061 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2062 S_AX_BACAM_RST_ALL); 2063 2064 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2065 1, 1000, false, 2066 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2067 if (ret) 2068 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2069 } 2070 2071 static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2072 { 2073 #define TRXCFG_RMAC_CCA_TO 32 2074 #define TRXCFG_RMAC_DATA_TO 15 2075 #define RX_MAX_LEN_UNIT 512 2076 #define PLD_RLS_MAX_PG 127 2077 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2078 int ret; 2079 u32 reg, rx_max_len, rx_qta; 2080 u16 val; 2081 2082 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2083 if (ret) 2084 return ret; 2085 2086 if (mac_idx == RTW89_MAC_0) 2087 rst_bacam(rtwdev); 2088 2089 reg = rtw89_mac_reg_by_idx(R_AX_RESPBA_CAM_CTRL, mac_idx); 2090 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2091 2092 reg = rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx); 2093 val = rtw89_read16(rtwdev, reg); 2094 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2095 B_AX_RX_DLK_DATA_TIME_MASK); 2096 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2097 B_AX_RX_DLK_CCA_TIME_MASK); 2098 rtw89_write16(rtwdev, reg, val); 2099 2100 reg = rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx); 2101 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2102 2103 reg = rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx); 2104 if (mac_idx == RTW89_MAC_0) 2105 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2106 else 2107 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2108 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2109 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2110 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2111 rx_max_len /= RX_MAX_LEN_UNIT; 2112 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2113 2114 if (rtwdev->chip->chip_id == RTL8852A && 2115 rtwdev->hal.cv == CHIP_CBV) { 2116 rtw89_write16_mask(rtwdev, 2117 rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx), 2118 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2119 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx), 2120 BIT(12)); 2121 } 2122 2123 reg = rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx); 2124 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2125 2126 return ret; 2127 } 2128 2129 static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2130 { 2131 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2132 u32 val, reg; 2133 int ret; 2134 2135 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2136 if (ret) 2137 return ret; 2138 2139 reg = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2140 val = rtw89_read32(rtwdev, reg); 2141 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2142 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2143 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2144 rtw89_write32(rtwdev, reg, val); 2145 2146 if (chip_id == RTL8852A || chip_id == RTL8852B) { 2147 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_RRSR1, mac_idx); 2148 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2149 } 2150 2151 return 0; 2152 } 2153 2154 static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2155 { 2156 const struct rtw89_dle_mem *cfg; 2157 2158 cfg = get_dle_mem_cfg(rtwdev, mode); 2159 if (!cfg) { 2160 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2161 return false; 2162 } 2163 2164 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2165 } 2166 2167 static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2168 { 2169 u32 val, reg; 2170 int ret; 2171 2172 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2173 if (ret) 2174 return ret; 2175 2176 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2177 reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); 2178 val = rtw89_read32(rtwdev, reg); 2179 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2180 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2181 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2182 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2183 val |= B_AX_HW_CTS2SELF_EN; 2184 rtw89_write32(rtwdev, reg, val); 2185 2186 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_FSM_MON, mac_idx); 2187 val = rtw89_read32(rtwdev, reg); 2188 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2189 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2190 rtw89_write32(rtwdev, reg, val); 2191 } 2192 2193 if (mac_idx == RTW89_MAC_0) { 2194 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2195 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2196 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2197 B_AX_PTCL_TRIGGER_SS_EN_0 | 2198 B_AX_PTCL_TRIGGER_SS_EN_1 | 2199 B_AX_PTCL_TRIGGER_SS_EN_UL); 2200 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2201 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2202 } else if (mac_idx == RTW89_MAC_1) { 2203 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2204 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2205 } 2206 2207 return 0; 2208 } 2209 2210 static int cmac_dma_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2211 { 2212 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2213 u32 reg; 2214 int ret; 2215 2216 if (chip_id != RTL8852A && chip_id != RTL8852B) 2217 return 0; 2218 2219 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2220 if (ret) 2221 return ret; 2222 2223 reg = rtw89_mac_reg_by_idx(R_AX_RXDMA_CTRL_0, mac_idx); 2224 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2225 2226 return 0; 2227 } 2228 2229 static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2230 { 2231 int ret; 2232 2233 ret = scheduler_init(rtwdev, mac_idx); 2234 if (ret) { 2235 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2236 return ret; 2237 } 2238 2239 ret = addr_cam_init(rtwdev, mac_idx); 2240 if (ret) { 2241 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2242 ret); 2243 return ret; 2244 } 2245 2246 ret = rx_fltr_init(rtwdev, mac_idx); 2247 if (ret) { 2248 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2249 ret); 2250 return ret; 2251 } 2252 2253 ret = cca_ctrl_init(rtwdev, mac_idx); 2254 if (ret) { 2255 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2256 ret); 2257 return ret; 2258 } 2259 2260 ret = nav_ctrl_init(rtwdev); 2261 if (ret) { 2262 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2263 ret); 2264 return ret; 2265 } 2266 2267 ret = spatial_reuse_init(rtwdev, mac_idx); 2268 if (ret) { 2269 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2270 mac_idx, ret); 2271 return ret; 2272 } 2273 2274 ret = tmac_init(rtwdev, mac_idx); 2275 if (ret) { 2276 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2277 return ret; 2278 } 2279 2280 ret = trxptcl_init(rtwdev, mac_idx); 2281 if (ret) { 2282 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2283 return ret; 2284 } 2285 2286 ret = rmac_init(rtwdev, mac_idx); 2287 if (ret) { 2288 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2289 return ret; 2290 } 2291 2292 ret = cmac_com_init(rtwdev, mac_idx); 2293 if (ret) { 2294 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2295 return ret; 2296 } 2297 2298 ret = ptcl_init(rtwdev, mac_idx); 2299 if (ret) { 2300 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2301 return ret; 2302 } 2303 2304 ret = cmac_dma_init(rtwdev, mac_idx); 2305 if (ret) { 2306 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2307 return ret; 2308 } 2309 2310 return ret; 2311 } 2312 2313 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2314 struct rtw89_mac_c2h_info *c2h_info) 2315 { 2316 struct rtw89_mac_h2c_info h2c_info = {0}; 2317 u32 ret; 2318 2319 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2320 h2c_info.content_len = 0; 2321 2322 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2323 if (ret) 2324 return ret; 2325 2326 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2327 return -EINVAL; 2328 2329 return 0; 2330 } 2331 2332 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2333 { 2334 struct rtw89_hal *hal = &rtwdev->hal; 2335 const struct rtw89_chip_info *chip = rtwdev->chip; 2336 struct rtw89_mac_c2h_info c2h_info = {0}; 2337 u8 tx_nss; 2338 u8 rx_nss; 2339 u8 tx_ant; 2340 u8 rx_ant; 2341 u32 ret; 2342 2343 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2344 if (ret) 2345 return ret; 2346 2347 tx_nss = RTW89_GET_C2H_PHYCAP_TX_NSS(c2h_info.c2hreg); 2348 rx_nss = RTW89_GET_C2H_PHYCAP_RX_NSS(c2h_info.c2hreg); 2349 tx_ant = RTW89_GET_C2H_PHYCAP_ANT_TX_NUM(c2h_info.c2hreg); 2350 rx_ant = RTW89_GET_C2H_PHYCAP_ANT_RX_NUM(c2h_info.c2hreg); 2351 2352 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2353 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2354 2355 if (tx_ant == 1) 2356 hal->antenna_tx = RF_B; 2357 if (rx_ant == 1) 2358 hal->antenna_rx = RF_B; 2359 2360 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2361 hal->antenna_tx = RF_B; 2362 hal->tx_path_diversity = true; 2363 } 2364 2365 rtw89_debug(rtwdev, RTW89_DBG_FW, 2366 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2367 hal->tx_nss, tx_nss, chip->tx_nss, 2368 hal->rx_nss, rx_nss, chip->rx_nss); 2369 rtw89_debug(rtwdev, RTW89_DBG_FW, 2370 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2371 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2372 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2373 2374 return 0; 2375 } 2376 2377 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2378 u16 tx_en_u16, u16 mask_u16) 2379 { 2380 u32 ret; 2381 struct rtw89_mac_c2h_info c2h_info = {0}; 2382 struct rtw89_mac_h2c_info h2c_info = {0}; 2383 struct rtw89_h2creg_sch_tx_en *h2creg = 2384 (struct rtw89_h2creg_sch_tx_en *)h2c_info.h2creg; 2385 2386 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2387 h2c_info.content_len = sizeof(*h2creg) - RTW89_H2CREG_HDR_LEN; 2388 h2creg->tx_en = tx_en_u16; 2389 h2creg->mask = mask_u16; 2390 h2creg->band = band; 2391 2392 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2393 if (ret) 2394 return ret; 2395 2396 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2397 return -EINVAL; 2398 2399 return 0; 2400 } 2401 2402 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2403 u16 tx_en, u16 tx_en_mask) 2404 { 2405 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx); 2406 u16 val; 2407 int ret; 2408 2409 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2410 if (ret) 2411 return ret; 2412 2413 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 2414 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 2415 tx_en, tx_en_mask); 2416 2417 val = rtw89_read16(rtwdev, reg); 2418 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2419 rtw89_write16(rtwdev, reg, val); 2420 2421 return 0; 2422 } 2423 2424 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2425 u32 tx_en, u32 tx_en_mask) 2426 { 2427 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx); 2428 u32 val; 2429 int ret; 2430 2431 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2432 if (ret) 2433 return ret; 2434 2435 val = rtw89_read32(rtwdev, reg); 2436 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2437 rtw89_write32(rtwdev, reg, val); 2438 2439 return 0; 2440 } 2441 2442 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 2443 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2444 { 2445 int ret; 2446 2447 *tx_en = rtw89_read16(rtwdev, 2448 rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx)); 2449 2450 switch (sel) { 2451 case RTW89_SCH_TX_SEL_ALL: 2452 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2453 B_AX_CTN_TXEN_ALL_MASK); 2454 if (ret) 2455 return ret; 2456 break; 2457 case RTW89_SCH_TX_SEL_HIQ: 2458 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2459 0, B_AX_CTN_TXEN_HGQ); 2460 if (ret) 2461 return ret; 2462 break; 2463 case RTW89_SCH_TX_SEL_MG0: 2464 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2465 0, B_AX_CTN_TXEN_MGQ); 2466 if (ret) 2467 return ret; 2468 break; 2469 case RTW89_SCH_TX_SEL_MACID: 2470 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2471 B_AX_CTN_TXEN_ALL_MASK); 2472 if (ret) 2473 return ret; 2474 break; 2475 default: 2476 return 0; 2477 } 2478 2479 return 0; 2480 } 2481 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 2482 2483 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2484 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2485 { 2486 int ret; 2487 2488 *tx_en = rtw89_read32(rtwdev, 2489 rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx)); 2490 2491 switch (sel) { 2492 case RTW89_SCH_TX_SEL_ALL: 2493 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2494 B_AX_CTN_TXEN_ALL_MASK_V1); 2495 if (ret) 2496 return ret; 2497 break; 2498 case RTW89_SCH_TX_SEL_HIQ: 2499 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2500 0, B_AX_CTN_TXEN_HGQ); 2501 if (ret) 2502 return ret; 2503 break; 2504 case RTW89_SCH_TX_SEL_MG0: 2505 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2506 0, B_AX_CTN_TXEN_MGQ); 2507 if (ret) 2508 return ret; 2509 break; 2510 case RTW89_SCH_TX_SEL_MACID: 2511 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2512 B_AX_CTN_TXEN_ALL_MASK_V1); 2513 if (ret) 2514 return ret; 2515 break; 2516 default: 2517 return 0; 2518 } 2519 2520 return 0; 2521 } 2522 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 2523 2524 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2525 { 2526 int ret; 2527 2528 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 2529 if (ret) 2530 return ret; 2531 2532 return 0; 2533 } 2534 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 2535 2536 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2537 { 2538 int ret; 2539 2540 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 2541 B_AX_CTN_TXEN_ALL_MASK_V1); 2542 if (ret) 2543 return ret; 2544 2545 return 0; 2546 } 2547 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 2548 2549 u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd) 2550 { 2551 u32 val, reg; 2552 int ret; 2553 2554 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 2555 val = buf_len; 2556 val |= B_AX_WD_BUF_REQ_EXEC; 2557 rtw89_write32(rtwdev, reg, val); 2558 2559 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 2560 2561 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 2562 1, 2000, false, rtwdev, reg); 2563 if (ret) 2564 return 0xffff; 2565 2566 return FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 2567 } 2568 2569 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, 2570 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 2571 { 2572 u32 val, cmd_type, reg; 2573 int ret; 2574 2575 cmd_type = ctrl_para->cmd_type; 2576 2577 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 2578 val = 0; 2579 val = u32_replace_bits(val, ctrl_para->start_pktid, 2580 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 2581 val = u32_replace_bits(val, ctrl_para->end_pktid, 2582 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 2583 rtw89_write32(rtwdev, reg, val); 2584 2585 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 2586 val = 0; 2587 val = u32_replace_bits(val, ctrl_para->src_pid, 2588 B_AX_CPUQ_OP_SRC_PID_MASK); 2589 val = u32_replace_bits(val, ctrl_para->src_qid, 2590 B_AX_CPUQ_OP_SRC_QID_MASK); 2591 val = u32_replace_bits(val, ctrl_para->dst_pid, 2592 B_AX_CPUQ_OP_DST_PID_MASK); 2593 val = u32_replace_bits(val, ctrl_para->dst_qid, 2594 B_AX_CPUQ_OP_DST_QID_MASK); 2595 rtw89_write32(rtwdev, reg, val); 2596 2597 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 2598 val = 0; 2599 val = u32_replace_bits(val, cmd_type, 2600 B_AX_CPUQ_OP_CMD_TYPE_MASK); 2601 val = u32_replace_bits(val, ctrl_para->macid, 2602 B_AX_CPUQ_OP_MACID_MASK); 2603 val = u32_replace_bits(val, ctrl_para->pkt_num, 2604 B_AX_CPUQ_OP_PKTNUM_MASK); 2605 val |= B_AX_WD_CPUQ_OP_EXEC; 2606 rtw89_write32(rtwdev, reg, val); 2607 2608 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 2609 2610 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 2611 1, 2000, false, rtwdev, reg); 2612 if (ret) 2613 return ret; 2614 2615 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 2616 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 2617 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 2618 2619 return 0; 2620 } 2621 2622 static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2623 { 2624 const struct rtw89_dle_mem *cfg; 2625 struct rtw89_cpuio_ctrl ctrl_para = {0}; 2626 u16 pkt_id; 2627 int ret; 2628 2629 cfg = get_dle_mem_cfg(rtwdev, mode); 2630 if (!cfg) { 2631 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2632 return -EINVAL; 2633 } 2634 2635 if (dle_used_size(cfg->wde_size, cfg->ple_size) != 2636 dle_expected_used_size(rtwdev, mode)) { 2637 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2638 return -EINVAL; 2639 } 2640 2641 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 2642 2643 pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, true); 2644 if (pkt_id == 0xffff) { 2645 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 2646 return -ENOMEM; 2647 } 2648 2649 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2650 ctrl_para.start_pktid = pkt_id; 2651 ctrl_para.end_pktid = pkt_id; 2652 ctrl_para.pkt_num = 0; 2653 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 2654 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 2655 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true); 2656 if (ret) { 2657 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 2658 return -EFAULT; 2659 } 2660 2661 pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, false); 2662 if (pkt_id == 0xffff) { 2663 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 2664 return -ENOMEM; 2665 } 2666 2667 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2668 ctrl_para.start_pktid = pkt_id; 2669 ctrl_para.end_pktid = pkt_id; 2670 ctrl_para.pkt_num = 0; 2671 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 2672 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 2673 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false); 2674 if (ret) { 2675 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 2676 return -EFAULT; 2677 } 2678 2679 return 0; 2680 } 2681 2682 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 2683 { 2684 int ret; 2685 u32 reg; 2686 u8 val; 2687 2688 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2689 if (ret) 2690 return ret; 2691 2692 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_TX_CTN_SEL, mac_idx); 2693 2694 ret = read_poll_timeout(rtw89_read8, val, 2695 (val & B_AX_PTCL_TX_ON_STAT) == 0, 2696 SW_CVR_DUR_US, 2697 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 2698 false, rtwdev, reg); 2699 if (ret) 2700 return ret; 2701 2702 return 0; 2703 } 2704 2705 static int band1_enable(struct rtw89_dev *rtwdev) 2706 { 2707 int ret, i; 2708 u32 sleep_bak[4] = {0}; 2709 u32 pause_bak[4] = {0}; 2710 u32 tx_en; 2711 2712 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 2713 if (ret) { 2714 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 2715 return ret; 2716 } 2717 2718 for (i = 0; i < 4; i++) { 2719 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 2720 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 2721 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 2722 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 2723 } 2724 2725 ret = band_idle_ck_b(rtwdev, 0); 2726 if (ret) { 2727 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 2728 return ret; 2729 } 2730 2731 ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode); 2732 if (ret) { 2733 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 2734 return ret; 2735 } 2736 2737 for (i = 0; i < 4; i++) { 2738 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 2739 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 2740 } 2741 2742 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 2743 if (ret) { 2744 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 2745 return ret; 2746 } 2747 2748 ret = cmac_func_en(rtwdev, 1, true); 2749 if (ret) { 2750 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 2751 return ret; 2752 } 2753 2754 ret = cmac_init(rtwdev, 1); 2755 if (ret) { 2756 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 2757 return ret; 2758 } 2759 2760 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 2761 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 2762 2763 return 0; 2764 } 2765 2766 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 2767 { 2768 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2769 2770 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 2771 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 2772 } 2773 2774 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 2775 { 2776 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2777 2778 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 2779 } 2780 2781 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 2782 { 2783 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2784 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2785 2786 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 2787 B_AX_TX_GET_ERRPKTID_INT_EN | 2788 B_AX_TX_NXT_ERRPKTID_INT_EN | 2789 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 2790 B_AX_TX_OFFSET_ERR_INT_EN | 2791 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 2792 if (chip_id == RTL8852C) 2793 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 2794 B_AX_TX_ETH_TYPE_ERR_EN | 2795 B_AX_TX_LLC_PRE_ERR_EN | 2796 B_AX_TX_NW_TYPE_ERR_EN | 2797 B_AX_TX_KSRCH_ERR_EN); 2798 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 2799 imr->mpdu_tx_imr_set); 2800 2801 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 2802 B_AX_GETPKTID_ERR_INT_EN | 2803 B_AX_MHDRLEN_ERR_INT_EN | 2804 B_AX_RPT_ERR_INT_EN); 2805 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 2806 imr->mpdu_rx_imr_set); 2807 } 2808 2809 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 2810 { 2811 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2812 2813 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 2814 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 2815 B_AX_RPT_HANG_TIMEOUT_INT_EN | 2816 B_AX_PLE_B_PKTID_ERR_INT_EN); 2817 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 2818 imr->sta_sch_imr_set); 2819 } 2820 2821 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 2822 { 2823 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2824 2825 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 2826 imr->txpktctl_imr_b0_clr); 2827 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 2828 imr->txpktctl_imr_b0_set); 2829 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 2830 imr->txpktctl_imr_b1_clr); 2831 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 2832 imr->txpktctl_imr_b1_set); 2833 } 2834 2835 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 2836 { 2837 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2838 2839 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 2840 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 2841 } 2842 2843 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 2844 { 2845 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2846 2847 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 2848 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 2849 } 2850 2851 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 2852 { 2853 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 2854 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 2855 } 2856 2857 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 2858 { 2859 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2860 2861 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 2862 imr->host_disp_imr_clr); 2863 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 2864 imr->host_disp_imr_set); 2865 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 2866 imr->cpu_disp_imr_clr); 2867 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 2868 imr->cpu_disp_imr_set); 2869 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 2870 imr->other_disp_imr_clr); 2871 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 2872 imr->other_disp_imr_set); 2873 } 2874 2875 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 2876 { 2877 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 2878 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 2879 } 2880 2881 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 2882 { 2883 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2884 2885 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 2886 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 2887 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 2888 B_AX_BBRPT_CHINFO_IMR_CLR); 2889 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 2890 imr->bbrpt_err_imr_set); 2891 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 2892 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 2893 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 2894 } 2895 2896 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 2897 { 2898 u32 reg; 2899 2900 reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx); 2901 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 2902 B_AX_FSM_TIMEOUT_ERR_INT_EN); 2903 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 2904 } 2905 2906 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 2907 { 2908 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2909 u32 reg; 2910 2911 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx); 2912 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 2913 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 2914 } 2915 2916 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 2917 { 2918 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2919 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2920 u32 reg; 2921 2922 reg = rtw89_mac_reg_by_idx(imr->cdma_imr_0_reg, mac_idx); 2923 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 2924 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 2925 2926 if (chip_id == RTL8852C) { 2927 reg = rtw89_mac_reg_by_idx(imr->cdma_imr_1_reg, mac_idx); 2928 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 2929 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 2930 } 2931 } 2932 2933 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 2934 { 2935 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2936 u32 reg; 2937 2938 reg = rtw89_mac_reg_by_idx(imr->phy_intf_imr_reg, mac_idx); 2939 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 2940 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 2941 } 2942 2943 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 2944 { 2945 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2946 u32 reg; 2947 2948 reg = rtw89_mac_reg_by_idx(imr->rmac_imr_reg, mac_idx); 2949 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 2950 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 2951 } 2952 2953 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 2954 { 2955 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 2956 u32 reg; 2957 2958 reg = rtw89_mac_reg_by_idx(imr->tmac_imr_reg, mac_idx); 2959 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 2960 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 2961 } 2962 2963 static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, 2964 enum rtw89_mac_hwmod_sel sel) 2965 { 2966 int ret; 2967 2968 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 2969 if (ret) { 2970 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 2971 sel, mac_idx); 2972 return ret; 2973 } 2974 2975 if (sel == RTW89_DMAC_SEL) { 2976 rtw89_wdrls_imr_enable(rtwdev); 2977 rtw89_wsec_imr_enable(rtwdev); 2978 rtw89_mpdu_trx_imr_enable(rtwdev); 2979 rtw89_sta_sch_imr_enable(rtwdev); 2980 rtw89_txpktctl_imr_enable(rtwdev); 2981 rtw89_wde_imr_enable(rtwdev); 2982 rtw89_ple_imr_enable(rtwdev); 2983 rtw89_pktin_imr_enable(rtwdev); 2984 rtw89_dispatcher_imr_enable(rtwdev); 2985 rtw89_cpuio_imr_enable(rtwdev); 2986 rtw89_bbrpt_imr_enable(rtwdev); 2987 } else if (sel == RTW89_CMAC_SEL) { 2988 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 2989 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 2990 rtw89_cdma_imr_enable(rtwdev, mac_idx); 2991 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 2992 rtw89_rmac_imr_enable(rtwdev, mac_idx); 2993 rtw89_tmac_imr_enable(rtwdev, mac_idx); 2994 } else { 2995 return -EINVAL; 2996 } 2997 2998 return 0; 2999 } 3000 3001 static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en) 3002 { 3003 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3004 3005 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3006 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3007 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3008 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3009 if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta) 3010 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3011 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3012 } 3013 3014 static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) 3015 { 3016 int ret = 0; 3017 3018 if (enable) { 3019 ret = band1_enable(rtwdev); 3020 if (ret) { 3021 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3022 return ret; 3023 } 3024 3025 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3026 if (ret) { 3027 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3028 return ret; 3029 } 3030 } else { 3031 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3032 return -EINVAL; 3033 } 3034 3035 return 0; 3036 } 3037 3038 static int set_host_rpr(struct rtw89_dev *rtwdev) 3039 { 3040 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3041 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3042 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3043 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3044 B_AX_RLSRPT0_FLTR_MAP_MASK); 3045 } else { 3046 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3047 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3048 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3049 B_AX_RLSRPT0_FLTR_MAP_MASK); 3050 } 3051 3052 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3053 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3054 3055 return 0; 3056 } 3057 3058 static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) 3059 { 3060 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3061 int ret; 3062 3063 ret = dmac_init(rtwdev, 0); 3064 if (ret) { 3065 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3066 return ret; 3067 } 3068 3069 ret = cmac_init(rtwdev, 0); 3070 if (ret) { 3071 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3072 return ret; 3073 } 3074 3075 if (is_qta_dbcc(rtwdev, qta_mode)) { 3076 ret = rtw89_mac_dbcc_enable(rtwdev, true); 3077 if (ret) { 3078 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3079 return ret; 3080 } 3081 } 3082 3083 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3084 if (ret) { 3085 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3086 return ret; 3087 } 3088 3089 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3090 if (ret) { 3091 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3092 return ret; 3093 } 3094 3095 rtw89_mac_err_imr_ctrl(rtwdev, true); 3096 3097 ret = set_host_rpr(rtwdev); 3098 if (ret) { 3099 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3100 return ret; 3101 } 3102 3103 return 0; 3104 } 3105 3106 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3107 { 3108 u32 val32; 3109 3110 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3111 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3112 3113 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3114 val32 |= B_AX_FS_WDT_INT; 3115 val32 &= ~B_AX_FS_WDT_INT_MSK; 3116 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3117 } 3118 3119 static void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev) 3120 { 3121 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3122 3123 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3124 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3125 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3126 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3127 3128 rtw89_disable_fw_watchdog(rtwdev); 3129 3130 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3131 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3132 } 3133 3134 static int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, 3135 bool dlfw) 3136 { 3137 u32 val; 3138 int ret; 3139 3140 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3141 return -EFAULT; 3142 3143 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3144 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3145 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3146 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3147 3148 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3149 3150 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3151 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3152 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3153 B_AX_WCPU_FWDL_STS_MASK); 3154 3155 if (dlfw) 3156 val |= B_AX_WCPU_FWDL_EN; 3157 3158 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3159 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3160 boot_reason); 3161 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3162 3163 if (!dlfw) { 3164 mdelay(5); 3165 3166 ret = rtw89_fw_check_rdy(rtwdev); 3167 if (ret) 3168 return ret; 3169 } 3170 3171 return 0; 3172 } 3173 3174 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3175 { 3176 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3177 u32 val; 3178 int ret; 3179 3180 if (chip_id == RTL8852C) 3181 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3182 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3183 else 3184 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3185 B_AX_PKT_BUF_EN; 3186 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3187 3188 val = B_AX_DISPATCHER_CLK_EN; 3189 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3190 3191 if (chip_id != RTL8852C) 3192 goto dle; 3193 3194 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3195 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3196 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3197 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3198 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3199 3200 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3201 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3202 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3203 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3204 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3205 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3206 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3207 3208 dle: 3209 ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3210 if (ret) { 3211 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3212 return ret; 3213 } 3214 3215 ret = hfc_init(rtwdev, true, false, true); 3216 if (ret) { 3217 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3218 return ret; 3219 } 3220 3221 return ret; 3222 } 3223 3224 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3225 { 3226 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3227 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3228 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3229 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3230 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3231 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3232 3233 return 0; 3234 } 3235 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3236 3237 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3238 { 3239 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3240 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3241 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3242 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3243 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3244 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3245 3246 return 0; 3247 } 3248 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3249 3250 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev) 3251 { 3252 int ret; 3253 3254 ret = rtw89_mac_power_switch(rtwdev, true); 3255 if (ret) { 3256 rtw89_mac_power_switch(rtwdev, false); 3257 ret = rtw89_mac_power_switch(rtwdev, true); 3258 if (ret) 3259 return ret; 3260 } 3261 3262 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3263 3264 ret = rtw89_mac_dmac_pre_init(rtwdev); 3265 if (ret) 3266 return ret; 3267 3268 if (rtwdev->hci.ops->mac_pre_init) { 3269 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3270 if (ret) 3271 return ret; 3272 } 3273 3274 rtw89_mac_disable_cpu(rtwdev); 3275 ret = rtw89_mac_enable_cpu(rtwdev, 0, true); 3276 if (ret) 3277 return ret; 3278 3279 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL); 3280 if (ret) 3281 return ret; 3282 3283 return 0; 3284 } 3285 3286 int rtw89_mac_init(struct rtw89_dev *rtwdev) 3287 { 3288 int ret; 3289 3290 ret = rtw89_mac_partial_init(rtwdev); 3291 if (ret) 3292 goto fail; 3293 3294 ret = rtw89_chip_enable_bb_rf(rtwdev); 3295 if (ret) 3296 goto fail; 3297 3298 ret = rtw89_mac_sys_init(rtwdev); 3299 if (ret) 3300 goto fail; 3301 3302 ret = rtw89_mac_trx_init(rtwdev); 3303 if (ret) 3304 goto fail; 3305 3306 if (rtwdev->hci.ops->mac_post_init) { 3307 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3308 if (ret) 3309 goto fail; 3310 } 3311 3312 rtw89_fw_send_all_early_h2c(rtwdev); 3313 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3314 3315 return ret; 3316 fail: 3317 rtw89_mac_power_switch(rtwdev, false); 3318 3319 return ret; 3320 } 3321 3322 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3323 { 3324 u8 i; 3325 3326 for (i = 0; i < 4; i++) { 3327 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3328 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 3329 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 3330 } 3331 } 3332 3333 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3334 { 3335 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3336 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 3337 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 3338 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 3339 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 3340 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 3341 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 3342 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 3343 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 3344 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 3345 } 3346 3347 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 3348 { 3349 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 3350 u8 grp = macid >> 5; 3351 int ret; 3352 3353 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3354 if (ret) 3355 return ret; 3356 3357 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 3358 3359 return 0; 3360 } 3361 3362 static const struct rtw89_port_reg rtw_port_base = { 3363 .port_cfg = R_AX_PORT_CFG_P0, 3364 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 3365 .bcn_area = R_AX_BCN_AREA_P0, 3366 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 3367 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 3368 .tbtt_agg = R_AX_TBTT_AGG_P0, 3369 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 3370 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 3371 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 3372 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 3373 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 3374 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 3375 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 3376 .tsftr_l = R_AX_TSFTR_LOW_P0, 3377 .tsftr_h = R_AX_TSFTR_HIGH_P0 3378 }; 3379 3380 #define BCN_INTERVAL 100 3381 #define BCN_ERLY_DEF 160 3382 #define BCN_SETUP_DEF 2 3383 #define BCN_HOLD_DEF 200 3384 #define BCN_MASK_DEF 0 3385 #define TBTT_ERLY_DEF 5 3386 #define BCN_SET_UNIT 32 3387 #define BCN_ERLY_SET_DLY (10 * 2) 3388 3389 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 3390 struct rtw89_vif *rtwvif) 3391 { 3392 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3393 const struct rtw89_port_reg *p = &rtw_port_base; 3394 3395 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 3396 return; 3397 3398 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 3399 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 3400 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 3401 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 3402 3403 msleep(vif->bss_conf.beacon_int + 1); 3404 3405 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 3406 B_AX_BRK_SETUP); 3407 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 3408 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 3409 } 3410 3411 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 3412 struct rtw89_vif *rtwvif, bool en) 3413 { 3414 const struct rtw89_port_reg *p = &rtw_port_base; 3415 3416 if (en) 3417 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3418 else 3419 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3420 } 3421 3422 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 3423 struct rtw89_vif *rtwvif, bool en) 3424 { 3425 const struct rtw89_port_reg *p = &rtw_port_base; 3426 3427 if (en) 3428 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3429 else 3430 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3431 } 3432 3433 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 3434 struct rtw89_vif *rtwvif) 3435 { 3436 const struct rtw89_port_reg *p = &rtw_port_base; 3437 3438 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 3439 rtwvif->net_type); 3440 } 3441 3442 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 3443 struct rtw89_vif *rtwvif) 3444 { 3445 const struct rtw89_port_reg *p = &rtw_port_base; 3446 bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 3447 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 3448 3449 if (en) 3450 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 3451 else 3452 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 3453 } 3454 3455 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 3456 struct rtw89_vif *rtwvif) 3457 { 3458 const struct rtw89_port_reg *p = &rtw_port_base; 3459 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3460 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3461 u32 bit = B_AX_RX_BSSID_FIT_EN; 3462 3463 if (en) 3464 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 3465 else 3466 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 3467 } 3468 3469 static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 3470 struct rtw89_vif *rtwvif) 3471 { 3472 const struct rtw89_port_reg *p = &rtw_port_base; 3473 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3474 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3475 3476 if (en) 3477 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3478 else 3479 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3480 } 3481 3482 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 3483 struct rtw89_vif *rtwvif) 3484 { 3485 const struct rtw89_port_reg *p = &rtw_port_base; 3486 bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 3487 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3488 3489 if (en) 3490 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3491 else 3492 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3493 } 3494 3495 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 3496 struct rtw89_vif *rtwvif) 3497 { 3498 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3499 const struct rtw89_port_reg *p = &rtw_port_base; 3500 u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 3501 3502 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 3503 bcn_int); 3504 } 3505 3506 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 3507 struct rtw89_vif *rtwvif) 3508 { 3509 static const u32 hiq_win_addr[RTW89_PORT_NUM] = { 3510 R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 3511 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 3512 R_AX_PORT_HGQ_WINDOW_CFG + 3, 3513 }; 3514 u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 3515 u8 port = rtwvif->port; 3516 u32 reg; 3517 3518 reg = rtw89_mac_reg_by_idx(hiq_win_addr[port], rtwvif->mac_idx); 3519 rtw89_write8(rtwdev, reg, win); 3520 } 3521 3522 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 3523 struct rtw89_vif *rtwvif) 3524 { 3525 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3526 const struct rtw89_port_reg *p = &rtw_port_base; 3527 u32 addr; 3528 3529 addr = rtw89_mac_reg_by_idx(R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx); 3530 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 3531 3532 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 3533 vif->bss_conf.dtim_period); 3534 } 3535 3536 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 3537 struct rtw89_vif *rtwvif) 3538 { 3539 const struct rtw89_port_reg *p = &rtw_port_base; 3540 3541 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3542 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 3543 } 3544 3545 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 3546 struct rtw89_vif *rtwvif) 3547 { 3548 const struct rtw89_port_reg *p = &rtw_port_base; 3549 3550 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3551 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 3552 } 3553 3554 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 3555 struct rtw89_vif *rtwvif) 3556 { 3557 const struct rtw89_port_reg *p = &rtw_port_base; 3558 3559 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 3560 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 3561 } 3562 3563 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 3564 struct rtw89_vif *rtwvif) 3565 { 3566 const struct rtw89_port_reg *p = &rtw_port_base; 3567 3568 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 3569 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 3570 } 3571 3572 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 3573 struct rtw89_vif *rtwvif) 3574 { 3575 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3576 static const u32 masks[RTW89_PORT_NUM] = { 3577 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 3578 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 3579 B_AX_BSS_COLOB_AX_PORT_4_MASK, 3580 }; 3581 u8 port = rtwvif->port; 3582 u32 reg_base; 3583 u32 reg; 3584 u8 bss_color; 3585 3586 bss_color = vif->bss_conf.he_bss_color.color; 3587 reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0; 3588 reg = rtw89_mac_reg_by_idx(reg_base, rtwvif->mac_idx); 3589 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 3590 } 3591 3592 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 3593 struct rtw89_vif *rtwvif) 3594 { 3595 u8 port = rtwvif->port; 3596 u32 reg; 3597 3598 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 3599 return; 3600 3601 if (port == 0) { 3602 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_CTRL, rtwvif->mac_idx); 3603 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 3604 } 3605 } 3606 3607 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 3608 struct rtw89_vif *rtwvif) 3609 { 3610 u8 port = rtwvif->port; 3611 u32 reg; 3612 u32 val; 3613 3614 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_DROP_0, rtwvif->mac_idx); 3615 val = rtw89_read32(rtwdev, reg); 3616 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 3617 if (port == 0) 3618 val &= ~BIT(0); 3619 rtw89_write32(rtwdev, reg, val); 3620 } 3621 3622 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 3623 struct rtw89_vif *rtwvif) 3624 { 3625 const struct rtw89_port_reg *p = &rtw_port_base; 3626 3627 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN); 3628 } 3629 3630 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 3631 struct rtw89_vif *rtwvif) 3632 { 3633 const struct rtw89_port_reg *p = &rtw_port_base; 3634 3635 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 3636 BCN_ERLY_DEF); 3637 } 3638 3639 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 3640 struct rtw89_vif *rtwvif) 3641 { 3642 const struct rtw89_port_reg *p = &rtw_port_base; 3643 u16 val; 3644 3645 if (rtwdev->chip->chip_id != RTL8852C) 3646 return; 3647 3648 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 3649 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 3650 return; 3651 3652 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 3653 B_AX_TBTT_SHIFT_OFST_SIGN; 3654 3655 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift, 3656 B_AX_TBTT_SHIFT_OFST_MASK, val); 3657 } 3658 3659 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3660 { 3661 int ret; 3662 3663 ret = rtw89_mac_port_update(rtwdev, rtwvif); 3664 if (ret) 3665 return ret; 3666 3667 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 3668 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 3669 3670 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 3671 if (ret) 3672 return ret; 3673 3674 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 3675 if (ret) 3676 return ret; 3677 3678 ret = rtw89_cam_init(rtwdev, rtwvif); 3679 if (ret) 3680 return ret; 3681 3682 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 3683 if (ret) 3684 return ret; 3685 3686 ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif); 3687 if (ret) 3688 return ret; 3689 3690 return 0; 3691 } 3692 3693 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3694 { 3695 int ret; 3696 3697 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 3698 if (ret) 3699 return ret; 3700 3701 rtw89_cam_deinit(rtwdev, rtwvif); 3702 3703 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 3704 if (ret) 3705 return ret; 3706 3707 return 0; 3708 } 3709 3710 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3711 { 3712 u8 port = rtwvif->port; 3713 3714 if (port >= RTW89_PORT_NUM) 3715 return -EINVAL; 3716 3717 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 3718 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 3719 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 3720 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 3721 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 3722 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 3723 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); 3724 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif); 3725 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 3726 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 3727 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 3728 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 3729 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 3730 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 3731 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 3732 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 3733 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif); 3734 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 3735 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 3736 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif); 3737 fsleep(BCN_ERLY_SET_DLY); 3738 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 3739 3740 return 0; 3741 } 3742 3743 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 3744 struct cfg80211_bss *bss, 3745 void *data) 3746 { 3747 const struct cfg80211_bss_ies *ies; 3748 const struct element *elem; 3749 bool *tolerated = data; 3750 3751 rcu_read_lock(); 3752 ies = rcu_dereference(bss->ies); 3753 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 3754 ies->len); 3755 3756 if (!elem || elem->datalen < 10 || 3757 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 3758 *tolerated = false; 3759 rcu_read_unlock(); 3760 } 3761 3762 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 3763 struct ieee80211_vif *vif) 3764 { 3765 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3766 struct ieee80211_hw *hw = rtwdev->hw; 3767 bool tolerated = true; 3768 u32 reg; 3769 3770 if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION) 3771 return; 3772 3773 if (!(vif->bss_conf.chandef.chan->flags & IEEE80211_CHAN_RADAR)) 3774 return; 3775 3776 cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chandef, 3777 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 3778 &tolerated); 3779 3780 reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx); 3781 if (tolerated) 3782 rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 3783 else 3784 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 3785 } 3786 3787 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3788 { 3789 int ret; 3790 3791 rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 3792 RTW89_MAX_MAC_ID_NUM); 3793 if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 3794 return -ENOSPC; 3795 3796 ret = rtw89_mac_vif_init(rtwdev, rtwvif); 3797 if (ret) 3798 goto release_mac_id; 3799 3800 return 0; 3801 3802 release_mac_id: 3803 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 3804 3805 return ret; 3806 } 3807 3808 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3809 { 3810 int ret; 3811 3812 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 3813 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 3814 3815 return ret; 3816 } 3817 3818 static void 3819 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3820 { 3821 } 3822 3823 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 3824 { 3825 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 3826 3827 return band == scan_info->op_band && channel == scan_info->op_pri_ch; 3828 } 3829 3830 static void 3831 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 3832 u32 len) 3833 { 3834 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 3835 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 3836 struct rtw89_chan new; 3837 u8 reason, status, tx_fail, band, actual_period; 3838 u32 last_chan = rtwdev->scan_info.last_chan_idx; 3839 u16 chan; 3840 int ret; 3841 3842 tx_fail = RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h->data); 3843 status = RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h->data); 3844 chan = RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h->data); 3845 reason = RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h->data); 3846 band = RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h->data); 3847 actual_period = RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h->data); 3848 3849 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 3850 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 3851 3852 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 3853 "band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 3854 band, chan, reason, status, tx_fail, actual_period); 3855 3856 switch (reason) { 3857 case RTW89_SCAN_LEAVE_CH_NOTIFY: 3858 if (rtw89_is_op_chan(rtwdev, band, chan)) 3859 ieee80211_stop_queues(rtwdev->hw); 3860 return; 3861 case RTW89_SCAN_END_SCAN_NOTIFY: 3862 if (rtwvif && rtwvif->scan_req && 3863 last_chan < rtwvif->scan_req->n_channels) { 3864 ret = rtw89_hw_scan_offload(rtwdev, vif, true); 3865 if (ret) { 3866 rtw89_hw_scan_abort(rtwdev, vif); 3867 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 3868 } 3869 } else { 3870 rtw89_hw_scan_complete(rtwdev, vif, false); 3871 } 3872 break; 3873 case RTW89_SCAN_ENTER_CH_NOTIFY: 3874 rtw89_chan_create(&new, chan, chan, band, RTW89_CHANNEL_WIDTH_20); 3875 rtw89_assign_entity_chan(rtwdev, RTW89_SUB_ENTITY_0, &new); 3876 if (rtw89_is_op_chan(rtwdev, band, chan)) { 3877 rtw89_store_op_chan(rtwdev, false); 3878 ieee80211_wake_queues(rtwdev->hw); 3879 } 3880 break; 3881 default: 3882 return; 3883 } 3884 } 3885 3886 static void 3887 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3888 { 3889 rtw89_debug(rtwdev, RTW89_DBG_FW, 3890 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 3891 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 3892 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 3893 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 3894 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 3895 } 3896 3897 static void 3898 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3899 { 3900 rtw89_debug(rtwdev, RTW89_DBG_FW, 3901 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 3902 RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h->data), 3903 RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h->data), 3904 RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h->data), 3905 RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h->data), 3906 RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h->data)); 3907 } 3908 3909 static void 3910 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3911 { 3912 rtw89_info(rtwdev, "%*s", RTW89_GET_C2H_LOG_LEN(len), 3913 RTW89_GET_C2H_LOG_SRT_PRT(c2h->data)); 3914 } 3915 3916 static void 3917 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3918 { 3919 } 3920 3921 static void 3922 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 3923 u32 len) 3924 { 3925 } 3926 3927 static void 3928 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 3929 u32 len) 3930 { 3931 } 3932 3933 static 3934 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 3935 struct sk_buff *c2h, u32 len) = { 3936 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 3937 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 3938 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 3939 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 3940 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 3941 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 3942 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 3943 }; 3944 3945 static 3946 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 3947 struct sk_buff *c2h, u32 len) = { 3948 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 3949 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 3950 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 3951 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 3952 }; 3953 3954 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 3955 u32 len, u8 class, u8 func) 3956 { 3957 void (*handler)(struct rtw89_dev *rtwdev, 3958 struct sk_buff *c2h, u32 len) = NULL; 3959 3960 switch (class) { 3961 case RTW89_MAC_C2H_CLASS_INFO: 3962 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 3963 handler = rtw89_mac_c2h_info_handler[func]; 3964 break; 3965 case RTW89_MAC_C2H_CLASS_OFLD: 3966 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 3967 handler = rtw89_mac_c2h_ofld_handler[func]; 3968 break; 3969 case RTW89_MAC_C2H_CLASS_FWDBG: 3970 return; 3971 default: 3972 rtw89_info(rtwdev, "c2h class %d not support\n", class); 3973 return; 3974 } 3975 if (!handler) { 3976 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 3977 func); 3978 return; 3979 } 3980 handler(rtwdev, skb, len); 3981 } 3982 3983 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 3984 enum rtw89_phy_idx phy_idx, 3985 u32 reg_base, u32 *cr) 3986 { 3987 const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; 3988 enum rtw89_qta_mode mode = dle_mem->mode; 3989 u32 addr = rtw89_mac_reg_by_idx(reg_base, phy_idx); 3990 3991 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) { 3992 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 3993 addr); 3994 goto error; 3995 } 3996 3997 if (addr >= CMAC1_START_ADDR && addr <= CMAC1_END_ADDR) 3998 if (mode == RTW89_QTA_SCC) { 3999 rtw89_err(rtwdev, 4000 "[TXPWR] addr=0x%x but hw not enable\n", 4001 addr); 4002 goto error; 4003 } 4004 4005 *cr = addr; 4006 return true; 4007 4008 error: 4009 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 4010 addr, phy_idx); 4011 4012 return false; 4013 } 4014 EXPORT_SYMBOL(rtw89_mac_get_txpwr_cr); 4015 4016 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 4017 { 4018 u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx); 4019 int ret = 0; 4020 4021 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4022 if (ret) 4023 return ret; 4024 4025 if (!enable) { 4026 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 4027 return ret; 4028 } 4029 4030 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 4031 B_AX_APP_MAC_INFO_RPT | 4032 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 4033 B_AX_PPDU_STAT_RPT_CRC32); 4034 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 4035 RTW89_PRPT_DEST_HOST); 4036 4037 return ret; 4038 } 4039 EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status); 4040 4041 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 4042 { 4043 #define MAC_AX_TIME_TH_SH 5 4044 #define MAC_AX_LEN_TH_SH 4 4045 #define MAC_AX_TIME_TH_MAX 255 4046 #define MAC_AX_LEN_TH_MAX 255 4047 #define MAC_AX_TIME_TH_DEF 88 4048 #define MAC_AX_LEN_TH_DEF 4080 4049 struct ieee80211_hw *hw = rtwdev->hw; 4050 u32 rts_threshold = hw->wiphy->rts_threshold; 4051 u32 time_th, len_th; 4052 u32 reg; 4053 4054 if (rts_threshold == (u32)-1) { 4055 time_th = MAC_AX_TIME_TH_DEF; 4056 len_th = MAC_AX_LEN_TH_DEF; 4057 } else { 4058 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 4059 len_th = rts_threshold; 4060 } 4061 4062 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 4063 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 4064 4065 reg = rtw89_mac_reg_by_idx(R_AX_AGG_LEN_HT_0, mac_idx); 4066 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 4067 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 4068 } 4069 4070 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 4071 { 4072 bool empty; 4073 int ret; 4074 4075 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4076 return; 4077 4078 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 4079 10000, 200000, false, rtwdev); 4080 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 4081 rtw89_info(rtwdev, "timed out to flush queues\n"); 4082 } 4083 4084 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 4085 { 4086 u8 val; 4087 u16 val16; 4088 u32 val32; 4089 int ret; 4090 4091 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 4092 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 4093 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 4094 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 4095 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 4096 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 4097 4098 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 4099 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 4100 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 4101 4102 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 4103 if (ret) { 4104 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 4105 return ret; 4106 } 4107 val32 = val32 & B_AX_WL_RX_CTRL; 4108 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 4109 if (ret) { 4110 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 4111 return ret; 4112 } 4113 4114 switch (coex->pta_mode) { 4115 case RTW89_MAC_AX_COEX_RTK_MODE: 4116 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4117 val &= ~B_AX_BTMODE_MASK; 4118 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 4119 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4120 4121 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 4122 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 4123 4124 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 4125 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 4126 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 4127 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 4128 break; 4129 case RTW89_MAC_AX_COEX_CSR_MODE: 4130 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4131 val &= ~B_AX_BTMODE_MASK; 4132 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 4133 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4134 4135 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 4136 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 4137 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 4138 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 4139 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 4140 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 4141 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 4142 val16 |= B_AX_ENHANCED_BT; 4143 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 4144 4145 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 4146 break; 4147 default: 4148 return -EINVAL; 4149 } 4150 4151 switch (coex->direction) { 4152 case RTW89_MAC_AX_COEX_INNER: 4153 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4154 val = (val & ~BIT(2)) | BIT(1); 4155 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4156 break; 4157 case RTW89_MAC_AX_COEX_OUTPUT: 4158 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4159 val = val | BIT(1) | BIT(0); 4160 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4161 break; 4162 case RTW89_MAC_AX_COEX_INPUT: 4163 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4164 val = val & ~(BIT(2) | BIT(1)); 4165 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4166 break; 4167 default: 4168 return -EINVAL; 4169 } 4170 4171 return 0; 4172 } 4173 EXPORT_SYMBOL(rtw89_mac_coex_init); 4174 4175 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 4176 const struct rtw89_mac_ax_coex *coex) 4177 { 4178 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 4179 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 4180 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 4181 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 4182 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 4183 4184 switch (coex->pta_mode) { 4185 case RTW89_MAC_AX_COEX_RTK_MODE: 4186 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4187 MAC_AX_RTK_MODE); 4188 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 4189 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 4190 break; 4191 case RTW89_MAC_AX_COEX_CSR_MODE: 4192 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4193 MAC_AX_CSR_MODE); 4194 break; 4195 default: 4196 return -EINVAL; 4197 } 4198 4199 return 0; 4200 } 4201 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 4202 4203 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 4204 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4205 { 4206 u32 val = 0, ret; 4207 4208 if (gnt_cfg->band[0].gnt_bt) 4209 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 4210 4211 if (gnt_cfg->band[0].gnt_bt_sw_en) 4212 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 4213 4214 if (gnt_cfg->band[0].gnt_wl) 4215 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 4216 4217 if (gnt_cfg->band[0].gnt_wl_sw_en) 4218 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 4219 4220 if (gnt_cfg->band[1].gnt_bt) 4221 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 4222 4223 if (gnt_cfg->band[1].gnt_bt_sw_en) 4224 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 4225 4226 if (gnt_cfg->band[1].gnt_wl) 4227 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 4228 4229 if (gnt_cfg->band[1].gnt_wl_sw_en) 4230 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 4231 4232 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 4233 if (ret) { 4234 rtw89_err(rtwdev, "Write LTE fail!\n"); 4235 return ret; 4236 } 4237 4238 return 0; 4239 } 4240 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 4241 4242 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 4243 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4244 { 4245 u32 val = 0; 4246 4247 if (gnt_cfg->band[0].gnt_bt) 4248 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 4249 B_AX_GNT_BT_TX_VAL; 4250 else 4251 val |= B_AX_WL_ACT_VAL; 4252 4253 if (gnt_cfg->band[0].gnt_bt_sw_en) 4254 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 4255 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 4256 4257 if (gnt_cfg->band[0].gnt_wl) 4258 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 4259 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 4260 4261 if (gnt_cfg->band[0].gnt_wl_sw_en) 4262 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 4263 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 4264 4265 if (gnt_cfg->band[1].gnt_bt) 4266 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 4267 B_AX_GNT_BT_TX_VAL; 4268 else 4269 val |= B_AX_WL_ACT_VAL; 4270 4271 if (gnt_cfg->band[1].gnt_bt_sw_en) 4272 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 4273 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 4274 4275 if (gnt_cfg->band[1].gnt_wl) 4276 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 4277 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 4278 4279 if (gnt_cfg->band[1].gnt_wl_sw_en) 4280 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 4281 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 4282 4283 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 4284 4285 return 0; 4286 } 4287 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 4288 4289 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 4290 { 4291 u32 reg; 4292 u16 val; 4293 int ret; 4294 4295 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 4296 if (ret) 4297 return ret; 4298 4299 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, plt->band); 4300 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 4301 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 4302 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 4303 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 4304 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 4305 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 4306 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 4307 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 4308 B_AX_PLT_EN; 4309 rtw89_write16(rtwdev, reg, val); 4310 4311 return 0; 4312 } 4313 4314 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 4315 { 4316 u32 fw_sb; 4317 4318 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 4319 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 4320 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 4321 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4322 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 4323 else 4324 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 4325 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 4326 val = B_AX_TOGGLE | 4327 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 4328 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 4329 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 4330 fsleep(1000); /* avoid BT FW loss information */ 4331 } 4332 4333 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 4334 { 4335 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 4336 } 4337 4338 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 4339 { 4340 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 4341 4342 val = wl ? val | BIT(2) : val & ~BIT(2); 4343 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 4344 4345 return 0; 4346 } 4347 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 4348 4349 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 4350 { 4351 struct rtw89_btc *btc = &rtwdev->btc; 4352 struct rtw89_btc_dm *dm = &btc->dm; 4353 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 4354 int i; 4355 4356 if (wl) 4357 return 0; 4358 4359 for (i = 0; i < RTW89_PHY_MAX; i++) { 4360 g[i].gnt_bt_sw_en = 1; 4361 g[i].gnt_bt = 1; 4362 g[i].gnt_wl_sw_en = 1; 4363 g[i].gnt_wl = 0; 4364 } 4365 4366 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 4367 } 4368 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 4369 4370 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 4371 { 4372 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 4373 4374 return FIELD_GET(B_AX_LTE_MUX_CTRL_PATH >> 24, val); 4375 } 4376 4377 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 4378 { 4379 u32 reg; 4380 u16 cnt; 4381 4382 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, band); 4383 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 4384 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 4385 4386 return cnt; 4387 } 4388 4389 static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 4390 { 4391 u32 reg; 4392 u32 mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 4393 B_AX_BFMEE_HE_NDPA_EN; 4394 4395 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 4396 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 4397 if (en) { 4398 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 4399 rtw89_write32_set(rtwdev, reg, mask); 4400 } else { 4401 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 4402 rtw89_write32_clr(rtwdev, reg, mask); 4403 } 4404 } 4405 4406 static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx) 4407 { 4408 u32 reg; 4409 u32 val32; 4410 int ret; 4411 4412 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4413 if (ret) 4414 return ret; 4415 4416 /* AP mode set tx gid to 63 */ 4417 /* STA mode set tx gid to 0(default) */ 4418 reg = rtw89_mac_reg_by_idx(R_AX_BFMER_CTRL_0, mac_idx); 4419 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 4420 4421 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 4422 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 4423 4424 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 4425 val32 = FIELD_PREP(B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, BFRP_RX_STANDBY_TIMER); 4426 val32 |= FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 4427 rtw89_write32(rtwdev, reg, val32); 4428 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 4429 4430 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 4431 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 4432 B_AX_BFMEE_USE_NSTS | 4433 B_AX_BFMEE_CSI_GID_SEL | 4434 B_AX_BFMEE_CSI_FORCE_RETE_EN); 4435 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 4436 rtw89_write32(rtwdev, reg, 4437 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 4438 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 4439 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 4440 4441 reg = rtw89_mac_reg_by_idx(R_AX_CSIRPT_OPTION, mac_idx); 4442 rtw89_write32_set(rtwdev, reg, 4443 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 4444 4445 return 0; 4446 } 4447 4448 static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, 4449 struct ieee80211_vif *vif, 4450 struct ieee80211_sta *sta) 4451 { 4452 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4453 u8 mac_idx = rtwvif->mac_idx; 4454 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 4455 u8 port_sel = rtwvif->port; 4456 u8 sound_dim = 3, t; 4457 u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 4458 u32 reg; 4459 u16 val; 4460 int ret; 4461 4462 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4463 if (ret) 4464 return ret; 4465 4466 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 4467 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 4468 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 4469 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 4470 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 4471 phy_cap[5]); 4472 sound_dim = min(sound_dim, t); 4473 } 4474 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 4475 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 4476 ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 4477 stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 4478 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 4479 sta->deflink.vht_cap.cap); 4480 sound_dim = min(sound_dim, t); 4481 } 4482 nc = min(nc, sound_dim); 4483 nr = min(nr, sound_dim); 4484 4485 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 4486 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 4487 4488 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 4489 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 4490 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 4491 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 4492 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 4493 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 4494 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 4495 4496 if (port_sel == 0) 4497 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 4498 else 4499 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 4500 4501 rtw89_write16(rtwdev, reg, val); 4502 4503 return 0; 4504 } 4505 4506 static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev, 4507 struct ieee80211_vif *vif, 4508 struct ieee80211_sta *sta) 4509 { 4510 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4511 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 4512 u32 reg; 4513 u8 mac_idx = rtwvif->mac_idx; 4514 int ret; 4515 4516 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4517 if (ret) 4518 return ret; 4519 4520 if (sta->deflink.he_cap.has_he) { 4521 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 4522 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 4523 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 4524 } 4525 if (sta->deflink.vht_cap.vht_supported) { 4526 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 4527 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 4528 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 4529 } 4530 if (sta->deflink.ht_cap.ht_supported) { 4531 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 4532 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 4533 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 4534 } 4535 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 4536 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 4537 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 4538 rtw89_write32(rtwdev, 4539 rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 4540 rrsc); 4541 4542 return 0; 4543 } 4544 4545 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4546 struct ieee80211_sta *sta) 4547 { 4548 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4549 4550 if (rtw89_sta_has_beamformer_cap(sta)) { 4551 rtw89_debug(rtwdev, RTW89_DBG_BF, 4552 "initialize bfee for new association\n"); 4553 rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx); 4554 rtw89_mac_set_csi_para_reg(rtwdev, vif, sta); 4555 rtw89_mac_csi_rrsc(rtwdev, vif, sta); 4556 } 4557 } 4558 4559 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4560 struct ieee80211_sta *sta) 4561 { 4562 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4563 4564 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 4565 } 4566 4567 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4568 struct ieee80211_bss_conf *conf) 4569 { 4570 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4571 u8 mac_idx = rtwvif->mac_idx; 4572 __le32 *p; 4573 4574 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 4575 4576 p = (__le32 *)conf->mu_group.membership; 4577 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx), 4578 le32_to_cpu(p[0])); 4579 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx), 4580 le32_to_cpu(p[1])); 4581 4582 p = (__le32 *)conf->mu_group.position; 4583 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx), 4584 le32_to_cpu(p[0])); 4585 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx), 4586 le32_to_cpu(p[1])); 4587 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx), 4588 le32_to_cpu(p[2])); 4589 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx), 4590 le32_to_cpu(p[3])); 4591 } 4592 4593 struct rtw89_mac_bf_monitor_iter_data { 4594 struct rtw89_dev *rtwdev; 4595 struct ieee80211_sta *down_sta; 4596 int count; 4597 }; 4598 4599 static 4600 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 4601 { 4602 struct rtw89_mac_bf_monitor_iter_data *iter_data = 4603 (struct rtw89_mac_bf_monitor_iter_data *)data; 4604 struct ieee80211_sta *down_sta = iter_data->down_sta; 4605 int *count = &iter_data->count; 4606 4607 if (down_sta == sta) 4608 return; 4609 4610 if (rtw89_sta_has_beamformer_cap(sta)) 4611 (*count)++; 4612 } 4613 4614 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 4615 struct ieee80211_sta *sta, bool disconnect) 4616 { 4617 struct rtw89_mac_bf_monitor_iter_data data; 4618 4619 data.rtwdev = rtwdev; 4620 data.down_sta = disconnect ? sta : NULL; 4621 data.count = 0; 4622 ieee80211_iterate_stations_atomic(rtwdev->hw, 4623 rtw89_mac_bf_monitor_calc_iter, 4624 &data); 4625 4626 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 4627 if (data.count) 4628 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 4629 else 4630 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 4631 } 4632 4633 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 4634 { 4635 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4636 struct rtw89_vif *rtwvif; 4637 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 4638 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 4639 4640 if (en == old) 4641 return; 4642 4643 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4644 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 4645 } 4646 4647 static int 4648 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 4649 u32 tx_time) 4650 { 4651 #define MAC_AX_DFLT_TX_TIME 5280 4652 u8 mac_idx = rtwsta->rtwvif->mac_idx; 4653 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 4654 u32 reg; 4655 int ret = 0; 4656 4657 if (rtwsta->cctl_tx_time) { 4658 rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 4659 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 4660 } else { 4661 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4662 if (ret) { 4663 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 4664 return ret; 4665 } 4666 4667 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 4668 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 4669 max_tx_time >> 5); 4670 } 4671 4672 return ret; 4673 } 4674 4675 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 4676 bool resume, u32 tx_time) 4677 { 4678 int ret = 0; 4679 4680 if (!resume) { 4681 rtwsta->cctl_tx_time = true; 4682 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 4683 } else { 4684 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 4685 rtwsta->cctl_tx_time = false; 4686 } 4687 4688 return ret; 4689 } 4690 4691 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 4692 u32 *tx_time) 4693 { 4694 u8 mac_idx = rtwsta->rtwvif->mac_idx; 4695 u32 reg; 4696 int ret = 0; 4697 4698 if (rtwsta->cctl_tx_time) { 4699 *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 4700 } else { 4701 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4702 if (ret) { 4703 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 4704 return ret; 4705 } 4706 4707 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 4708 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 4709 } 4710 4711 return ret; 4712 } 4713 4714 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 4715 struct rtw89_sta *rtwsta, 4716 bool resume, u8 tx_retry) 4717 { 4718 int ret = 0; 4719 4720 rtwsta->data_tx_cnt_lmt = tx_retry; 4721 4722 if (!resume) { 4723 rtwsta->cctl_tx_retry_limit = true; 4724 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 4725 } else { 4726 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 4727 rtwsta->cctl_tx_retry_limit = false; 4728 } 4729 4730 return ret; 4731 } 4732 4733 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 4734 struct rtw89_sta *rtwsta, u8 *tx_retry) 4735 { 4736 u8 mac_idx = rtwsta->rtwvif->mac_idx; 4737 u32 reg; 4738 int ret = 0; 4739 4740 if (rtwsta->cctl_tx_retry_limit) { 4741 *tx_retry = rtwsta->data_tx_cnt_lmt; 4742 } else { 4743 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4744 if (ret) { 4745 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 4746 return ret; 4747 } 4748 4749 reg = rtw89_mac_reg_by_idx(R_AX_TXCNT, mac_idx); 4750 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 4751 } 4752 4753 return ret; 4754 } 4755 4756 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 4757 struct rtw89_vif *rtwvif, bool en) 4758 { 4759 u8 mac_idx = rtwvif->mac_idx; 4760 u16 set = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0; 4761 u32 reg; 4762 u32 ret; 4763 4764 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4765 if (ret) 4766 return ret; 4767 4768 reg = rtw89_mac_reg_by_idx(R_AX_MUEDCA_EN, mac_idx); 4769 if (en) 4770 rtw89_write16_set(rtwdev, reg, set); 4771 else 4772 rtw89_write16_clr(rtwdev, reg, set); 4773 4774 return 0; 4775 } 4776 4777 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 4778 { 4779 u32 val32; 4780 int ret; 4781 4782 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 4783 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 4784 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 4785 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 4786 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 4787 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 4788 4789 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 4790 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 4791 if (ret) { 4792 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 4793 offset, val, mask); 4794 return ret; 4795 } 4796 4797 return 0; 4798 } 4799 EXPORT_SYMBOL(rtw89_mac_write_xtal_si); 4800 4801 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 4802 { 4803 u32 val32; 4804 int ret; 4805 4806 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 4807 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 4808 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 4809 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 4810 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 4811 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 4812 4813 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 4814 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 4815 if (ret) { 4816 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 4817 return ret; 4818 } 4819 4820 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 4821 4822 return 0; 4823 } 4824 EXPORT_SYMBOL(rtw89_mac_read_xtal_si); 4825 4826 static 4827 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 4828 { 4829 static const enum rtw89_pkt_drop_sel sels[] = { 4830 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4831 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4832 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4833 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4834 }; 4835 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 4836 struct rtw89_pkt_drop_params params = {0}; 4837 int i; 4838 4839 params.mac_band = RTW89_MAC_0; 4840 params.macid = rtwsta->mac_id; 4841 params.port = rtwvif->port; 4842 params.mbssid = 0; 4843 params.tf_trs = rtwvif->trigger; 4844 4845 for (i = 0; i < ARRAY_SIZE(sels); i++) { 4846 params.sel = sels[i]; 4847 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 4848 } 4849 } 4850 4851 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 4852 { 4853 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 4854 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 4855 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 4856 struct rtw89_vif *target = data; 4857 4858 if (rtwvif != target) 4859 return; 4860 4861 rtw89_mac_pkt_drop_sta(rtwdev, rtwsta); 4862 } 4863 4864 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4865 { 4866 ieee80211_iterate_stations_atomic(rtwdev->hw, 4867 rtw89_mac_pkt_drop_vif_iter, 4868 rtwvif); 4869 } 4870