1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "fw.h" 9 #include "mac.h" 10 #include "pci.h" 11 #include "ps.h" 12 #include "reg.h" 13 #include "util.h" 14 15 const u32 rtw89_mac_mem_base_addrs[RTW89_MAC_MEM_NUM] = { 16 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 17 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 18 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 19 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 20 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 21 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 22 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 23 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 24 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 25 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 26 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 28 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 29 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 30 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 31 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 32 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 33 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 34 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 35 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 36 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 37 }; 38 39 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 40 u32 val, enum rtw89_mac_mem_sel sel) 41 { 42 u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; 43 44 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); 45 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, val); 46 } 47 48 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 49 enum rtw89_mac_mem_sel sel) 50 { 51 u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; 52 53 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); 54 return rtw89_read32(rtwdev, R_AX_INDIR_ACCESS_ENTRY); 55 } 56 57 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, 58 enum rtw89_mac_hwmod_sel sel) 59 { 60 u32 val, r_val; 61 62 if (sel == RTW89_DMAC_SEL) { 63 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 64 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 65 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 66 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 67 val = B_AX_CMAC_EN; 68 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 69 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 70 val = B_AX_CMAC1_FEN; 71 } else { 72 return -EINVAL; 73 } 74 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 75 (val & r_val) != val) 76 return -EFAULT; 77 78 return 0; 79 } 80 81 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 82 { 83 u8 lte_ctrl; 84 int ret; 85 86 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 87 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 88 if (ret) 89 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 90 91 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 92 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 93 94 return ret; 95 } 96 97 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 98 { 99 u8 lte_ctrl; 100 int ret; 101 102 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 103 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 104 if (ret) 105 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 106 107 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 108 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 109 110 return ret; 111 } 112 113 static 114 int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 115 { 116 u32 ctrl_reg, data_reg, ctrl_data; 117 u32 val; 118 int ret; 119 120 switch (ctrl->type) { 121 case DLE_CTRL_TYPE_WDE: 122 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 123 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 124 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 125 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 126 B_AX_WDE_DFI_ACTIVE; 127 break; 128 case DLE_CTRL_TYPE_PLE: 129 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 130 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 131 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 132 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 133 B_AX_PLE_DFI_ACTIVE; 134 break; 135 default: 136 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 137 return -EINVAL; 138 } 139 140 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 141 142 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 143 1, 1000, false, rtwdev, ctrl_reg); 144 if (ret) { 145 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 146 ctrl_reg, ctrl_data); 147 return ret; 148 } 149 150 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 151 return 0; 152 } 153 154 static int dle_dfi_quota(struct rtw89_dev *rtwdev, 155 struct rtw89_mac_dle_dfi_quota *quota) 156 { 157 struct rtw89_mac_dle_dfi_ctrl ctrl; 158 int ret; 159 160 ctrl.type = quota->dle_type; 161 ctrl.target = DLE_DFI_TYPE_QUOTA; 162 ctrl.addr = quota->qtaid; 163 ret = dle_dfi_ctrl(rtwdev, &ctrl); 164 if (ret) { 165 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 166 return ret; 167 } 168 169 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 170 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 171 return 0; 172 } 173 174 static int dle_dfi_qempty(struct rtw89_dev *rtwdev, 175 struct rtw89_mac_dle_dfi_qempty *qempty) 176 { 177 struct rtw89_mac_dle_dfi_ctrl ctrl; 178 u32 ret; 179 180 ctrl.type = qempty->dle_type; 181 ctrl.target = DLE_DFI_TYPE_QEMPTY; 182 ctrl.addr = qempty->grpsel; 183 ret = dle_dfi_ctrl(rtwdev, &ctrl); 184 if (ret) { 185 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 186 return ret; 187 } 188 189 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 190 return 0; 191 } 192 193 static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev) 194 { 195 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 196 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 197 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 198 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 199 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 200 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 201 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 202 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 203 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 204 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 205 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 206 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 207 } 208 209 static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) 210 { 211 struct rtw89_mac_dle_dfi_qempty qempty; 212 struct rtw89_mac_dle_dfi_quota quota; 213 struct rtw89_mac_dle_dfi_ctrl ctrl; 214 u32 val, not_empty, i; 215 int ret; 216 217 qempty.dle_type = DLE_CTRL_TYPE_PLE; 218 qempty.grpsel = 0; 219 qempty.qempty = ~(u32)0; 220 ret = dle_dfi_qempty(rtwdev, &qempty); 221 if (ret) 222 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 223 else 224 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 225 226 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 227 if (!(not_empty & BIT(0))) 228 continue; 229 ctrl.type = DLE_CTRL_TYPE_PLE; 230 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 231 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 232 FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i); 233 ret = dle_dfi_ctrl(rtwdev, &ctrl); 234 if (ret) 235 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 236 else 237 rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i, 238 FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK, 239 ctrl.out_data)); 240 } 241 242 quota.dle_type = DLE_CTRL_TYPE_PLE; 243 quota.qtaid = 6; 244 ret = dle_dfi_quota(rtwdev, "a); 245 if (ret) 246 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 247 else 248 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 249 quota.rsv_pgnum, quota.use_pgnum); 250 251 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 252 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n", 253 FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val)); 254 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n", 255 FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val)); 256 257 dump_err_status_dispatcher(rtwdev); 258 } 259 260 static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 261 enum mac_ax_err_info err) 262 { 263 u32 dbg, event; 264 265 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 266 event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg); 267 268 switch (event) { 269 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 270 rtw89_info(rtwdev, "quota lost!\n"); 271 rtw89_mac_dump_qta_lost(rtwdev); 272 break; 273 default: 274 break; 275 } 276 } 277 278 static void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 279 { 280 const struct rtw89_chip_info *chip = rtwdev->chip; 281 u32 dmac_err; 282 int i, ret; 283 284 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 285 if (ret) { 286 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 287 return; 288 } 289 290 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 291 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 292 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 293 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 294 295 if (dmac_err) { 296 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 298 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 299 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 300 if (chip->chip_id == RTL8852C) { 301 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 302 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 303 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 304 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 305 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 306 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 307 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 308 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 309 } 310 } 311 312 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 313 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 314 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 315 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 316 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 317 if (chip->chip_id == RTL8852C) 318 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 319 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 320 else 321 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 322 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 323 } 324 325 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 326 if (chip->chip_id == RTL8852C) { 327 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 328 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 329 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 330 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 331 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 332 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 333 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 334 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 335 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 336 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 337 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 338 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 339 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 340 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 341 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 343 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 344 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 345 346 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 347 B_AX_DBG_SEL0, 0x8B); 348 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 349 B_AX_DBG_SEL1, 0x8B); 350 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 351 B_AX_SEL_0XC0_MASK, 1); 352 for (i = 0; i < 0x10; i++) { 353 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 354 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 355 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 356 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 357 } 358 } else { 359 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 360 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 361 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 362 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 363 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 364 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 365 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 366 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 367 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 368 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 369 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 370 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 371 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 372 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 373 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 374 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 375 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 376 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 377 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 378 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 379 } 380 } 381 382 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 383 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 384 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 385 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 386 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 387 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 388 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 389 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 390 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 391 } 392 393 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 394 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 395 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 396 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 397 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 398 } 399 400 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 401 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 402 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 403 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 404 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 405 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 406 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 407 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 408 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 409 } 410 411 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 412 if (chip->chip_id == RTL8852C) { 413 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 414 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 415 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 416 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 417 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 418 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 419 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 420 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 421 } else { 422 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 423 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 424 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 425 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 426 } 427 } 428 429 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 430 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 431 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 432 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 433 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 434 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 435 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 436 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 437 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 438 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 439 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 440 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 441 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 442 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 443 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 444 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 445 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 446 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 447 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 448 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 449 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 450 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 451 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 452 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 453 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 454 if (chip->chip_id == RTL8852C) { 455 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 456 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 457 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 458 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 459 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 460 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 461 } else { 462 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 463 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 464 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 465 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 466 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 467 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 468 } 469 } 470 471 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 472 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 473 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 474 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 475 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 476 } 477 478 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 479 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 480 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 481 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 482 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 483 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 484 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 485 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 486 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 487 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 488 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 489 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 490 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 491 } 492 493 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 494 if (chip->chip_id == RTL8852C) { 495 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 496 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 497 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 498 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 499 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 500 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 501 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 502 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 503 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 504 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 505 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 506 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 507 } else { 508 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 509 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 510 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 511 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 512 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 513 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 514 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 515 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 516 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 517 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 518 } 519 } 520 521 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 522 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 523 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 524 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 525 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 526 } 527 } 528 529 static void rtw89_mac_dump_cmac_err_status(struct rtw89_dev *rtwdev, 530 u8 band) 531 { 532 const struct rtw89_chip_info *chip = rtwdev->chip; 533 u32 offset = 0; 534 u32 cmac_err; 535 int ret; 536 537 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 538 if (ret) { 539 if (band) 540 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 541 else 542 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 543 return; 544 } 545 546 if (band) 547 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 548 549 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 550 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 551 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 552 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 553 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 554 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 555 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 556 557 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 558 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 559 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 560 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 561 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 562 } 563 564 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 565 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 566 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 567 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 568 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 569 } 570 571 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 572 if (chip->chip_id == RTL8852C) { 573 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 574 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 575 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 576 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 577 } else { 578 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 579 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 580 } 581 } 582 583 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 584 if (chip->chip_id == RTL8852C) { 585 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 586 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 587 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 588 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 589 } else { 590 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 591 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 592 } 593 } 594 595 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 596 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 597 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 598 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 599 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 600 } 601 602 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 603 if (chip->chip_id == RTL8852C) { 604 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 605 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 606 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 607 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 608 } else { 609 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 610 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 611 } 612 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 613 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 614 } 615 616 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 617 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 618 } 619 620 static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev, 621 enum mac_ax_err_info err) 622 { 623 if (err != MAC_AX_ERR_L1_ERR_DMAC && 624 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 625 err != MAC_AX_ERR_L0_ERR_CMAC0 && 626 err != MAC_AX_ERR_L0_ERR_CMAC1 && 627 err != MAC_AX_ERR_RXI300) 628 return; 629 630 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 631 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 632 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 633 634 rtw89_mac_dump_dmac_err_status(rtwdev); 635 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_0); 636 if (rtwdev->dbcc_en) 637 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_1); 638 639 rtwdev->hci.ops->dump_err_status(rtwdev); 640 641 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 642 rtw89_mac_dump_l0_to_l1(rtwdev, err); 643 644 rtw89_info(rtwdev, "<---\n"); 645 } 646 647 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 648 { 649 u32 err, err_scnr; 650 int ret; 651 652 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 653 false, rtwdev, R_AX_HALT_C2H_CTRL); 654 if (ret) { 655 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 656 return ret; 657 } 658 659 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 660 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 661 662 err_scnr = RTW89_ERROR_SCENARIO(err); 663 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 664 err = MAC_AX_ERR_CPU_EXCEPTION; 665 else if (err_scnr == RTW89_WCPU_ASSERTION) 666 err = MAC_AX_ERR_ASSERTION; 667 else if (err_scnr == RTW89_RXI300_ERROR) 668 err = MAC_AX_ERR_RXI300; 669 670 rtw89_fw_st_dbg_dump(rtwdev); 671 rtw89_mac_dump_err_status(rtwdev, err); 672 673 return err; 674 } 675 EXPORT_SYMBOL(rtw89_mac_get_err_status); 676 677 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 678 { 679 u32 halt; 680 int ret = 0; 681 682 if (err > MAC_AX_SET_ERR_MAX) { 683 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 684 return -EINVAL; 685 } 686 687 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 688 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 689 if (ret) { 690 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 691 return -EFAULT; 692 } 693 694 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 695 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 696 697 return 0; 698 } 699 EXPORT_SYMBOL(rtw89_mac_set_err_status); 700 701 static int hfc_reset_param(struct rtw89_dev *rtwdev) 702 { 703 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 704 struct rtw89_hfc_param_ini param_ini = {NULL}; 705 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 706 707 switch (rtwdev->hci.type) { 708 case RTW89_HCI_TYPE_PCIE: 709 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 710 param->en = 0; 711 break; 712 default: 713 return -EINVAL; 714 } 715 716 if (param_ini.pub_cfg) 717 param->pub_cfg = *param_ini.pub_cfg; 718 719 if (param_ini.prec_cfg) { 720 param->prec_cfg = *param_ini.prec_cfg; 721 rtwdev->hal.sw_amsdu_max_size = 722 param->prec_cfg.wp_ch07_prec * HFC_PAGE_UNIT; 723 } 724 725 if (param_ini.ch_cfg) 726 param->ch_cfg = param_ini.ch_cfg; 727 728 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 729 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 730 param->mode = param_ini.mode; 731 732 return 0; 733 } 734 735 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 736 { 737 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 738 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 739 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 740 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 741 742 if (ch >= RTW89_DMA_CH_NUM) 743 return -EINVAL; 744 745 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 746 ch_cfg[ch].max > pub_cfg->pub_max) 747 return -EINVAL; 748 if (ch_cfg[ch].grp >= grp_num) 749 return -EINVAL; 750 751 return 0; 752 } 753 754 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 755 { 756 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 757 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 758 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 759 760 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 761 if (rtwdev->chip->chip_id == RTL8852A) 762 return 0; 763 else 764 return -EFAULT; 765 } 766 767 return 0; 768 } 769 770 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 771 { 772 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 773 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 774 775 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 776 return -EFAULT; 777 778 return 0; 779 } 780 781 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 782 { 783 const struct rtw89_chip_info *chip = rtwdev->chip; 784 const struct rtw89_page_regs *regs = chip->page_regs; 785 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 786 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 787 int ret = 0; 788 u32 val = 0; 789 790 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 791 if (ret) 792 return ret; 793 794 ret = hfc_ch_cfg_chk(rtwdev, ch); 795 if (ret) 796 return ret; 797 798 if (ch > RTW89_DMA_B1HI) 799 return -EINVAL; 800 801 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 802 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 803 (cfg[ch].grp ? B_AX_GRP : 0); 804 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 805 806 return 0; 807 } 808 809 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 810 { 811 const struct rtw89_chip_info *chip = rtwdev->chip; 812 const struct rtw89_page_regs *regs = chip->page_regs; 813 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 814 struct rtw89_hfc_ch_info *info = param->ch_info; 815 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 816 u32 val; 817 u32 ret; 818 819 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 820 if (ret) 821 return ret; 822 823 if (ch > RTW89_DMA_H2C) 824 return -EINVAL; 825 826 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 827 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 828 if (ch < RTW89_DMA_H2C) 829 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 830 else 831 info[ch].used = cfg[ch].min - info[ch].aval; 832 833 return 0; 834 } 835 836 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 837 { 838 const struct rtw89_chip_info *chip = rtwdev->chip; 839 const struct rtw89_page_regs *regs = chip->page_regs; 840 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 841 u32 val; 842 int ret; 843 844 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 845 if (ret) 846 return ret; 847 848 ret = hfc_pub_cfg_chk(rtwdev); 849 if (ret) 850 return ret; 851 852 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 853 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 854 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 855 856 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 857 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 858 859 return 0; 860 } 861 862 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 863 { 864 const struct rtw89_chip_info *chip = rtwdev->chip; 865 const struct rtw89_page_regs *regs = chip->page_regs; 866 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 867 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 868 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 869 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 870 u32 val; 871 int ret; 872 873 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 874 if (ret) 875 return ret; 876 877 val = rtw89_read32(rtwdev, regs->pub_page_info1); 878 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 879 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 880 val = rtw89_read32(rtwdev, regs->pub_page_info3); 881 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 882 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 883 info->pub_aval = 884 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 885 B_AX_PUB_AVAL_PG_MASK); 886 info->wp_aval = 887 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 888 B_AX_WP_AVAL_PG_MASK); 889 890 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 891 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 892 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 893 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 894 prec_cfg->ch011_full_cond = 895 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 896 prec_cfg->h2c_full_cond = 897 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 898 prec_cfg->wp_ch07_full_cond = 899 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 900 prec_cfg->wp_ch811_full_cond = 901 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 902 903 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 904 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 905 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 906 907 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 908 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 909 910 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 911 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 912 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 913 914 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 915 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 916 917 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 918 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 919 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 920 921 ret = hfc_pub_info_chk(rtwdev); 922 if (param->en && ret) 923 return ret; 924 925 return 0; 926 } 927 928 static void hfc_h2c_cfg(struct rtw89_dev *rtwdev) 929 { 930 const struct rtw89_chip_info *chip = rtwdev->chip; 931 const struct rtw89_page_regs *regs = chip->page_regs; 932 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 933 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 934 u32 val; 935 936 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 937 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 938 939 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 940 B_AX_HCI_FC_CH12_FULL_COND_MASK, 941 prec_cfg->h2c_full_cond); 942 } 943 944 static void hfc_mix_cfg(struct rtw89_dev *rtwdev) 945 { 946 const struct rtw89_chip_info *chip = rtwdev->chip; 947 const struct rtw89_page_regs *regs = chip->page_regs; 948 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 949 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 950 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 951 u32 val; 952 953 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 954 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 955 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 956 957 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 958 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 959 960 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 961 B_AX_PREC_PAGE_WP_CH07_MASK) | 962 u32_encode_bits(prec_cfg->wp_ch811_prec, 963 B_AX_PREC_PAGE_WP_CH811_MASK); 964 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 965 966 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 967 param->mode, B_AX_HCI_FC_MODE_MASK); 968 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 969 B_AX_HCI_FC_WD_FULL_COND_MASK); 970 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 971 B_AX_HCI_FC_CH12_FULL_COND_MASK); 972 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 973 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 974 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 975 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 976 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 977 } 978 979 static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 980 { 981 const struct rtw89_chip_info *chip = rtwdev->chip; 982 const struct rtw89_page_regs *regs = chip->page_regs; 983 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 984 u32 val; 985 986 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 987 param->en = en; 988 param->h2c_en = h2c_en; 989 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 990 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 991 (val & ~B_AX_HCI_FC_CH12_EN); 992 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 993 } 994 995 static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 996 { 997 const struct rtw89_chip_info *chip = rtwdev->chip; 998 u32 dma_ch_mask = chip->dma_ch_mask; 999 u8 ch; 1000 u32 ret = 0; 1001 1002 if (reset) 1003 ret = hfc_reset_param(rtwdev); 1004 if (ret) 1005 return ret; 1006 1007 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1008 if (ret) 1009 return ret; 1010 1011 hfc_func_en(rtwdev, false, false); 1012 1013 if (!en && h2c_en) { 1014 hfc_h2c_cfg(rtwdev); 1015 hfc_func_en(rtwdev, en, h2c_en); 1016 return ret; 1017 } 1018 1019 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1020 if (dma_ch_mask & BIT(ch)) 1021 continue; 1022 ret = hfc_ch_ctrl(rtwdev, ch); 1023 if (ret) 1024 return ret; 1025 } 1026 1027 ret = hfc_pub_ctrl(rtwdev); 1028 if (ret) 1029 return ret; 1030 1031 hfc_mix_cfg(rtwdev); 1032 if (en || h2c_en) { 1033 hfc_func_en(rtwdev, en, h2c_en); 1034 udelay(10); 1035 } 1036 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1037 if (dma_ch_mask & BIT(ch)) 1038 continue; 1039 ret = hfc_upd_ch_info(rtwdev, ch); 1040 if (ret) 1041 return ret; 1042 } 1043 ret = hfc_upd_mix_info(rtwdev); 1044 1045 return ret; 1046 } 1047 1048 #define PWR_POLL_CNT 2000 1049 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1050 const struct rtw89_pwr_cfg *cfg) 1051 { 1052 u8 val = 0; 1053 int ret; 1054 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1055 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1056 1057 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1058 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1059 1060 if (!ret) 1061 return 0; 1062 1063 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1064 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1065 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1066 1067 return -EBUSY; 1068 } 1069 1070 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1071 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1072 { 1073 const struct rtw89_pwr_cfg *cur_cfg; 1074 u32 addr; 1075 u8 val; 1076 1077 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1078 if (!(cur_cfg->intf_msk & intf_msk) || 1079 !(cur_cfg->cv_msk & cv_msk)) 1080 continue; 1081 1082 switch (cur_cfg->cmd) { 1083 case PWR_CMD_WRITE: 1084 addr = cur_cfg->addr; 1085 1086 if (cur_cfg->base == PWR_BASE_SDIO) 1087 addr |= SDIO_LOCAL_BASE_ADDR; 1088 1089 val = rtw89_read8(rtwdev, addr); 1090 val &= ~(cur_cfg->msk); 1091 val |= (cur_cfg->val & cur_cfg->msk); 1092 1093 rtw89_write8(rtwdev, addr, val); 1094 break; 1095 case PWR_CMD_POLL: 1096 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1097 return -EBUSY; 1098 break; 1099 case PWR_CMD_DELAY: 1100 if (cur_cfg->val == PWR_DELAY_US) 1101 udelay(cur_cfg->addr); 1102 else 1103 fsleep(cur_cfg->addr * 1000); 1104 break; 1105 default: 1106 return -EINVAL; 1107 } 1108 } 1109 1110 return 0; 1111 } 1112 1113 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1114 const struct rtw89_pwr_cfg * const *cfg_seq) 1115 { 1116 int ret; 1117 1118 for (; *cfg_seq; cfg_seq++) { 1119 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1120 PWR_INTF_MSK_PCIE, *cfg_seq); 1121 if (ret) 1122 return -EBUSY; 1123 } 1124 1125 return 0; 1126 } 1127 1128 static enum rtw89_rpwm_req_pwr_state 1129 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1130 { 1131 enum rtw89_rpwm_req_pwr_state state; 1132 1133 switch (rtwdev->ps_mode) { 1134 case RTW89_PS_MODE_RFOFF: 1135 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1136 break; 1137 case RTW89_PS_MODE_CLK_GATED: 1138 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1139 break; 1140 case RTW89_PS_MODE_PWR_GATED: 1141 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1142 break; 1143 default: 1144 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1145 break; 1146 } 1147 return state; 1148 } 1149 1150 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1151 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1152 bool notify_wake) 1153 { 1154 u16 request; 1155 1156 spin_lock_bh(&rtwdev->rpwm_lock); 1157 1158 request = rtw89_read16(rtwdev, R_AX_RPWM); 1159 request ^= request | PS_RPWM_TOGGLE; 1160 request |= req_pwr_state; 1161 1162 if (notify_wake) { 1163 request |= PS_RPWM_NOTIFY_WAKE; 1164 } else { 1165 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1166 RPWM_SEQ_NUM_MAX; 1167 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1168 rtwdev->mac.rpwm_seq_num); 1169 1170 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1171 request |= PS_RPWM_ACK; 1172 } 1173 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1174 1175 spin_unlock_bh(&rtwdev->rpwm_lock); 1176 } 1177 1178 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1179 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1180 { 1181 bool request_deep_mode; 1182 bool in_deep_mode; 1183 u8 rpwm_req_num; 1184 u8 cpwm_rsp_seq; 1185 u8 cpwm_seq; 1186 u8 cpwm_status; 1187 1188 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1189 request_deep_mode = true; 1190 else 1191 request_deep_mode = false; 1192 1193 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1194 in_deep_mode = true; 1195 else 1196 in_deep_mode = false; 1197 1198 if (request_deep_mode != in_deep_mode) 1199 return -EPERM; 1200 1201 if (request_deep_mode) 1202 return 0; 1203 1204 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1205 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1206 PS_CPWM_RSP_SEQ_NUM); 1207 1208 if (rpwm_req_num != cpwm_rsp_seq) 1209 return -EPERM; 1210 1211 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1212 CPWM_SEQ_NUM_MAX; 1213 1214 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1215 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1216 return -EPERM; 1217 1218 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1219 if (cpwm_status != req_pwr_state) 1220 return -EPERM; 1221 1222 return 0; 1223 } 1224 1225 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1226 { 1227 enum rtw89_rpwm_req_pwr_state state; 1228 unsigned long delay = enter ? 10 : 150; 1229 int ret; 1230 int i; 1231 1232 if (enter) 1233 state = rtw89_mac_get_req_pwr_state(rtwdev); 1234 else 1235 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1236 1237 for (i = 0; i < RPWM_TRY_CNT; i++) { 1238 rtw89_mac_send_rpwm(rtwdev, state, false); 1239 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1240 !ret, delay, 15000, false, 1241 rtwdev, state); 1242 if (!ret) 1243 break; 1244 1245 if (i == RPWM_TRY_CNT - 1) 1246 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1247 enter ? "entering" : "leaving"); 1248 else 1249 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1250 "%d time firmware failed to ack for %s ps mode\n", 1251 i + 1, enter ? "entering" : "leaving"); 1252 } 1253 } 1254 1255 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1256 { 1257 enum rtw89_rpwm_req_pwr_state state; 1258 1259 state = rtw89_mac_get_req_pwr_state(rtwdev); 1260 rtw89_mac_send_rpwm(rtwdev, state, true); 1261 } 1262 1263 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1264 { 1265 #define PWR_ACT 1 1266 const struct rtw89_chip_info *chip = rtwdev->chip; 1267 const struct rtw89_pwr_cfg * const *cfg_seq; 1268 int (*cfg_func)(struct rtw89_dev *rtwdev); 1269 int ret; 1270 u8 val; 1271 1272 if (on) { 1273 cfg_seq = chip->pwr_on_seq; 1274 cfg_func = chip->ops->pwr_on_func; 1275 } else { 1276 cfg_seq = chip->pwr_off_seq; 1277 cfg_func = chip->ops->pwr_off_func; 1278 } 1279 1280 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1281 __rtw89_leave_ps_mode(rtwdev); 1282 1283 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1284 if (on && val == PWR_ACT) { 1285 rtw89_err(rtwdev, "MAC has already powered on\n"); 1286 return -EBUSY; 1287 } 1288 1289 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1290 if (ret) 1291 return ret; 1292 1293 if (on) { 1294 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1295 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1296 } else { 1297 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1298 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1299 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1300 rtw89_set_entity_state(rtwdev, false); 1301 } 1302 1303 return 0; 1304 #undef PWR_ACT 1305 } 1306 1307 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1308 { 1309 rtw89_mac_power_switch(rtwdev, false); 1310 } 1311 1312 static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1313 { 1314 u32 func_en = 0; 1315 u32 ck_en = 0; 1316 u32 c1pc_en = 0; 1317 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1318 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1319 1320 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1321 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1322 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1323 B_AX_CMAC_CRPRT; 1324 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1325 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1326 B_AX_RMAC_CKEN; 1327 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1328 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1329 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1330 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1331 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1332 1333 if (en) { 1334 if (mac_idx == RTW89_MAC_1) { 1335 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1336 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1337 B_AX_R_SYM_ISO_CMAC12PP); 1338 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1339 B_AX_CMAC1_FEN); 1340 } 1341 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1342 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1343 } else { 1344 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1345 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1346 if (mac_idx == RTW89_MAC_1) { 1347 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1348 B_AX_CMAC1_FEN); 1349 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1350 B_AX_R_SYM_ISO_CMAC12PP); 1351 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1352 } 1353 } 1354 1355 return 0; 1356 } 1357 1358 static int dmac_func_en(struct rtw89_dev *rtwdev) 1359 { 1360 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1361 u32 val32; 1362 1363 if (chip_id == RTL8852C) 1364 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1365 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1366 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1367 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1368 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1369 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1370 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1371 else 1372 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1373 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1374 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1375 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1376 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1377 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1378 B_AX_DMAC_CRPRT); 1379 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1380 1381 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1382 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1383 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1384 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1385 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1386 1387 return 0; 1388 } 1389 1390 static int chip_func_en(struct rtw89_dev *rtwdev) 1391 { 1392 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1393 1394 if (chip_id == RTL8852A || chip_id == RTL8852B) 1395 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1396 B_AX_OCP_L1_MASK); 1397 1398 return 0; 1399 } 1400 1401 static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev) 1402 { 1403 int ret; 1404 1405 ret = dmac_func_en(rtwdev); 1406 if (ret) 1407 return ret; 1408 1409 ret = cmac_func_en(rtwdev, 0, true); 1410 if (ret) 1411 return ret; 1412 1413 ret = chip_func_en(rtwdev); 1414 if (ret) 1415 return ret; 1416 1417 return ret; 1418 } 1419 1420 const struct rtw89_mac_size_set rtw89_mac_size = { 1421 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1422 /* PCIE 64 */ 1423 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1424 /* DLFW */ 1425 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1426 /* PCIE 64 */ 1427 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1428 /* DLFW */ 1429 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1430 /* 8852C DLFW */ 1431 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1432 /* 8852C PCIE SCC */ 1433 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1434 /* PCIE */ 1435 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1436 /* DLFW */ 1437 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1438 /* PCIE 64 */ 1439 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1440 /* DLFW */ 1441 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1442 /* 8852C DLFW */ 1443 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1444 /* 8852C PCIE SCC */ 1445 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1446 /* PCIE 64 */ 1447 .wde_qt0 = {3792, 196, 0, 107,}, 1448 /* DLFW */ 1449 .wde_qt4 = {0, 0, 0, 0,}, 1450 /* PCIE 64 */ 1451 .wde_qt6 = {448, 48, 0, 16,}, 1452 /* 8852C DLFW */ 1453 .wde_qt17 = {0, 0, 0, 0,}, 1454 /* 8852C PCIE SCC */ 1455 .wde_qt18 = {3228, 60, 0, 40,}, 1456 /* PCIE SCC */ 1457 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1458 /* PCIE SCC */ 1459 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1460 /* DLFW */ 1461 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1462 /* PCIE 64 */ 1463 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1464 /* DLFW 52C */ 1465 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1466 /* DLFW 52C */ 1467 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1468 /* 8852C PCIE SCC */ 1469 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1470 /* 8852C PCIE SCC */ 1471 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1472 /* PCIE 64 */ 1473 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1474 /* 8852A PCIE WOW */ 1475 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1476 }; 1477 EXPORT_SYMBOL(rtw89_mac_size); 1478 1479 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1480 enum rtw89_qta_mode mode) 1481 { 1482 struct rtw89_mac_info *mac = &rtwdev->mac; 1483 const struct rtw89_dle_mem *cfg; 1484 1485 cfg = &rtwdev->chip->dle_mem[mode]; 1486 if (!cfg) 1487 return NULL; 1488 1489 if (cfg->mode != mode) { 1490 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1491 return NULL; 1492 } 1493 1494 mac->dle_info.wde_pg_size = cfg->wde_size->pge_size; 1495 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1496 mac->dle_info.qta_mode = mode; 1497 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1498 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1499 1500 return cfg; 1501 } 1502 1503 static bool mac_is_txq_empty(struct rtw89_dev *rtwdev) 1504 { 1505 struct rtw89_mac_dle_dfi_qempty qempty; 1506 u32 qnum, qtmp, val32, msk32; 1507 int i, j, ret; 1508 1509 qnum = rtwdev->chip->wde_qempty_acq_num; 1510 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1511 1512 for (i = 0; i < qnum; i++) { 1513 qempty.grpsel = i; 1514 ret = dle_dfi_qempty(rtwdev, &qempty); 1515 if (ret) { 1516 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1517 return false; 1518 } 1519 qtmp = qempty.qempty; 1520 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1521 val32 = FIELD_GET(QEMP_ACQ_GRP_QSEL_MASK, qtmp); 1522 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1523 return false; 1524 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1525 } 1526 } 1527 1528 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_sel; 1529 ret = dle_dfi_qempty(rtwdev, &qempty); 1530 if (ret) { 1531 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1532 return false; 1533 } 1534 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1535 if ((qempty.qempty & msk32) != msk32) 1536 return false; 1537 1538 if (rtwdev->dbcc_en) { 1539 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1540 if ((qempty.qempty & msk32) != msk32) 1541 return false; 1542 } 1543 1544 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1545 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1546 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1547 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1548 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1549 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1550 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1551 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1552 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1553 1554 return (val32 & msk32) == msk32; 1555 } 1556 1557 static inline u32 dle_used_size(const struct rtw89_dle_size *wde, 1558 const struct rtw89_dle_size *ple) 1559 { 1560 return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1561 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1562 } 1563 1564 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 1565 enum rtw89_qta_mode mode) 1566 { 1567 u32 size = rtwdev->chip->fifo_size; 1568 1569 if (mode == RTW89_QTA_SCC) 1570 size -= rtwdev->chip->dle_scc_rsvd_size; 1571 1572 return size; 1573 } 1574 1575 static void dle_func_en(struct rtw89_dev *rtwdev, bool enable) 1576 { 1577 if (enable) 1578 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1579 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1580 else 1581 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1582 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1583 } 1584 1585 static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable) 1586 { 1587 if (enable) 1588 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, 1589 B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); 1590 else 1591 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, 1592 B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN); 1593 } 1594 1595 static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1596 { 1597 const struct rtw89_dle_size *size_cfg; 1598 u32 val; 1599 u8 bound = 0; 1600 1601 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1602 size_cfg = cfg->wde_size; 1603 1604 switch (size_cfg->pge_size) { 1605 default: 1606 case RTW89_WDE_PG_64: 1607 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1608 B_AX_WDE_PAGE_SEL_MASK); 1609 break; 1610 case RTW89_WDE_PG_128: 1611 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1612 B_AX_WDE_PAGE_SEL_MASK); 1613 break; 1614 case RTW89_WDE_PG_256: 1615 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1616 return -EINVAL; 1617 } 1618 1619 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1620 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1621 B_AX_WDE_FREE_PAGE_NUM_MASK); 1622 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1623 1624 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1625 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1626 * size_cfg->pge_size / DLE_BOUND_UNIT; 1627 size_cfg = cfg->ple_size; 1628 1629 switch (size_cfg->pge_size) { 1630 default: 1631 case RTW89_PLE_PG_64: 1632 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1633 return -EINVAL; 1634 case RTW89_PLE_PG_128: 1635 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1636 B_AX_PLE_PAGE_SEL_MASK); 1637 break; 1638 case RTW89_PLE_PG_256: 1639 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1640 B_AX_PLE_PAGE_SEL_MASK); 1641 break; 1642 } 1643 1644 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1645 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1646 B_AX_PLE_FREE_PAGE_NUM_MASK); 1647 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1648 1649 return 0; 1650 } 1651 1652 #define INVALID_QT_WCPU U16_MAX 1653 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1654 do { \ 1655 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1656 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1657 rtw89_write32(rtwdev, \ 1658 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1659 val); \ 1660 } while (0) 1661 #define SET_QUOTA(_x, _module, _idx) \ 1662 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1663 1664 static void wde_quota_cfg(struct rtw89_dev *rtwdev, 1665 const struct rtw89_wde_quota *min_cfg, 1666 const struct rtw89_wde_quota *max_cfg, 1667 u16 ext_wde_min_qt_wcpu) 1668 { 1669 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1670 ext_wde_min_qt_wcpu : min_cfg->wcpu; 1671 u32 val; 1672 1673 SET_QUOTA(hif, WDE, 0); 1674 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1675 SET_QUOTA(pkt_in, WDE, 3); 1676 SET_QUOTA(cpu_io, WDE, 4); 1677 } 1678 1679 static void ple_quota_cfg(struct rtw89_dev *rtwdev, 1680 const struct rtw89_ple_quota *min_cfg, 1681 const struct rtw89_ple_quota *max_cfg) 1682 { 1683 u32 val; 1684 1685 SET_QUOTA(cma0_tx, PLE, 0); 1686 SET_QUOTA(cma1_tx, PLE, 1); 1687 SET_QUOTA(c2h, PLE, 2); 1688 SET_QUOTA(h2c, PLE, 3); 1689 SET_QUOTA(wcpu, PLE, 4); 1690 SET_QUOTA(mpdu_proc, PLE, 5); 1691 SET_QUOTA(cma0_dma, PLE, 6); 1692 SET_QUOTA(cma1_dma, PLE, 7); 1693 SET_QUOTA(bb_rpt, PLE, 8); 1694 SET_QUOTA(wd_rel, PLE, 9); 1695 SET_QUOTA(cpu_io, PLE, 10); 1696 if (rtwdev->chip->chip_id == RTL8852C) 1697 SET_QUOTA(tx_rpt, PLE, 11); 1698 } 1699 1700 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 1701 { 1702 const struct rtw89_ple_quota *min_cfg, *max_cfg; 1703 const struct rtw89_dle_mem *cfg; 1704 u32 val; 1705 1706 if (rtwdev->chip->chip_id == RTL8852C) 1707 return 0; 1708 1709 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 1710 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 1711 return -EINVAL; 1712 } 1713 1714 if (wow) 1715 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 1716 else 1717 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 1718 if (!cfg) { 1719 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1720 return -EINVAL; 1721 } 1722 1723 min_cfg = cfg->ple_min_qt; 1724 max_cfg = cfg->ple_max_qt; 1725 SET_QUOTA(cma0_dma, PLE, 6); 1726 SET_QUOTA(cma1_dma, PLE, 7); 1727 1728 return 0; 1729 } 1730 #undef SET_QUOTA 1731 1732 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 1733 { 1734 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 1735 1736 if (enable) 1737 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 1738 else 1739 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 1740 } 1741 1742 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 1743 const struct rtw89_dle_mem *cfg, 1744 u16 ext_wde_min_qt_wcpu) 1745 { 1746 wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 1747 ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 1748 } 1749 1750 static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1751 enum rtw89_qta_mode ext_mode) 1752 { 1753 const struct rtw89_dle_mem *cfg, *ext_cfg; 1754 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 1755 int ret = 0; 1756 u32 ini; 1757 1758 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1759 if (ret) 1760 return ret; 1761 1762 cfg = get_dle_mem_cfg(rtwdev, mode); 1763 if (!cfg) { 1764 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1765 ret = -EINVAL; 1766 goto error; 1767 } 1768 1769 if (mode == RTW89_QTA_DLFW) { 1770 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 1771 if (!ext_cfg) { 1772 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 1773 ext_mode); 1774 ret = -EINVAL; 1775 goto error; 1776 } 1777 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 1778 } 1779 1780 if (dle_used_size(cfg->wde_size, cfg->ple_size) != 1781 dle_expected_used_size(rtwdev, mode)) { 1782 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 1783 ret = -EINVAL; 1784 goto error; 1785 } 1786 1787 dle_func_en(rtwdev, false); 1788 dle_clk_en(rtwdev, true); 1789 1790 ret = dle_mix_cfg(rtwdev, cfg); 1791 if (ret) { 1792 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 1793 goto error; 1794 } 1795 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 1796 1797 dle_func_en(rtwdev, true); 1798 1799 ret = read_poll_timeout(rtw89_read32, ini, 1800 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1801 2000, false, rtwdev, R_AX_WDE_INI_STATUS); 1802 if (ret) { 1803 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 1804 return ret; 1805 } 1806 1807 ret = read_poll_timeout(rtw89_read32, ini, 1808 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1809 2000, false, rtwdev, R_AX_PLE_INI_STATUS); 1810 if (ret) { 1811 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 1812 return ret; 1813 } 1814 1815 return 0; 1816 error: 1817 dle_func_en(rtwdev, false); 1818 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 1819 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 1820 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 1821 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 1822 1823 return ret; 1824 } 1825 1826 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1827 enum rtw89_qta_mode mode) 1828 { 1829 u32 reg, max_preld_size, min_rsvd_size; 1830 1831 max_preld_size = (mac_idx == RTW89_MAC_0 ? 1832 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 1833 reg = mac_idx == RTW89_MAC_0 ? 1834 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 1835 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 1836 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 1837 1838 min_rsvd_size = PRELD_AMSDU_SIZE; 1839 reg = mac_idx == RTW89_MAC_0 ? 1840 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 1841 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 1842 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 1843 1844 return 0; 1845 } 1846 1847 static bool is_qta_poh(struct rtw89_dev *rtwdev) 1848 { 1849 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 1850 } 1851 1852 static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1853 enum rtw89_qta_mode mode) 1854 { 1855 const struct rtw89_chip_info *chip = rtwdev->chip; 1856 1857 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || !is_qta_poh(rtwdev)) 1858 return 0; 1859 1860 return preload_init_set(rtwdev, mac_idx, mode); 1861 } 1862 1863 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 1864 { 1865 u32 msk32; 1866 u32 val32; 1867 1868 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 1869 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 1870 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 1871 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1872 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 1873 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 1874 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 1875 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 1876 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1877 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 1878 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1879 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1880 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 1881 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1882 1883 if ((val32 & msk32) == msk32) 1884 return true; 1885 1886 return false; 1887 } 1888 1889 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 1890 { 1891 const struct rtw89_chip_info *chip = rtwdev->chip; 1892 1893 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) 1894 return; 1895 1896 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 1897 SS2F_PATH_WLCPU); 1898 } 1899 1900 static int sta_sch_init(struct rtw89_dev *rtwdev) 1901 { 1902 u32 p_val; 1903 u8 val; 1904 int ret; 1905 1906 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1907 if (ret) 1908 return ret; 1909 1910 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 1911 val |= B_AX_SS_EN; 1912 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 1913 1914 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 1915 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 1916 if (ret) { 1917 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 1918 return ret; 1919 } 1920 1921 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 1922 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 1923 1924 _patch_ss2f_path(rtwdev); 1925 1926 return 0; 1927 } 1928 1929 static int mpdu_proc_init(struct rtw89_dev *rtwdev) 1930 { 1931 int ret; 1932 1933 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1934 if (ret) 1935 return ret; 1936 1937 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 1938 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 1939 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 1940 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 1941 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 1942 1943 return 0; 1944 } 1945 1946 static int sec_eng_init(struct rtw89_dev *rtwdev) 1947 { 1948 const struct rtw89_chip_info *chip = rtwdev->chip; 1949 u32 val = 0; 1950 int ret; 1951 1952 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1953 if (ret) 1954 return ret; 1955 1956 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 1957 /* init clock */ 1958 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 1959 /* init TX encryption */ 1960 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 1961 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 1962 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) 1963 val &= ~B_AX_TX_PARTIAL_MODE; 1964 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 1965 1966 /* init MIC ICV append */ 1967 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 1968 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 1969 1970 /* option init */ 1971 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 1972 1973 if (chip->chip_id == RTL8852C) 1974 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 1975 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 1976 1977 return 0; 1978 } 1979 1980 static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1981 { 1982 int ret; 1983 1984 ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 1985 if (ret) { 1986 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 1987 return ret; 1988 } 1989 1990 ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 1991 if (ret) { 1992 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 1993 return ret; 1994 } 1995 1996 ret = hfc_init(rtwdev, true, true, true); 1997 if (ret) { 1998 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 1999 return ret; 2000 } 2001 2002 ret = sta_sch_init(rtwdev); 2003 if (ret) { 2004 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2005 return ret; 2006 } 2007 2008 ret = mpdu_proc_init(rtwdev); 2009 if (ret) { 2010 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2011 return ret; 2012 } 2013 2014 ret = sec_eng_init(rtwdev); 2015 if (ret) { 2016 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2017 return ret; 2018 } 2019 2020 return ret; 2021 } 2022 2023 static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2024 { 2025 u32 val, reg; 2026 u16 p_val; 2027 int ret; 2028 2029 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2030 if (ret) 2031 return ret; 2032 2033 reg = rtw89_mac_reg_by_idx(R_AX_ADDR_CAM_CTRL, mac_idx); 2034 2035 val = rtw89_read32(rtwdev, reg); 2036 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2037 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2038 rtw89_write32(rtwdev, reg, val); 2039 2040 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2041 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2042 if (ret) { 2043 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2044 return ret; 2045 } 2046 2047 return 0; 2048 } 2049 2050 static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2051 { 2052 u32 ret; 2053 u32 reg; 2054 u32 val; 2055 2056 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2057 if (ret) 2058 return ret; 2059 2060 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_1, mac_idx); 2061 if (rtwdev->chip->chip_id == RTL8852C) 2062 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2063 SIFS_MACTXEN_T1_V1); 2064 else 2065 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2066 SIFS_MACTXEN_T1); 2067 2068 if (rtwdev->chip->chip_id == RTL8852B) { 2069 reg = rtw89_mac_reg_by_idx(R_AX_SCH_EXT_CTRL, mac_idx); 2070 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2071 } 2072 2073 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CFG_0, mac_idx); 2074 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2075 2076 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_0, mac_idx); 2077 if (rtwdev->chip->chip_id == RTL8852C) { 2078 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2079 B_AX_TX_PARTIAL_MODE); 2080 if (!val) 2081 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2082 SCH_PREBKF_24US); 2083 } else { 2084 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2085 SCH_PREBKF_24US); 2086 } 2087 2088 return 0; 2089 } 2090 2091 int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, 2092 enum rtw89_machdr_frame_type type, 2093 enum rtw89_mac_fwd_target fwd_target, 2094 u8 mac_idx) 2095 { 2096 u32 reg; 2097 u32 val; 2098 2099 switch (fwd_target) { 2100 case RTW89_FWD_DONT_CARE: 2101 val = RX_FLTR_FRAME_DROP; 2102 break; 2103 case RTW89_FWD_TO_HOST: 2104 val = RX_FLTR_FRAME_TO_HOST; 2105 break; 2106 case RTW89_FWD_TO_WLAN_CPU: 2107 val = RX_FLTR_FRAME_TO_WLCPU; 2108 break; 2109 default: 2110 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2111 return -EINVAL; 2112 } 2113 2114 switch (type) { 2115 case RTW89_MGNT: 2116 reg = rtw89_mac_reg_by_idx(R_AX_MGNT_FLTR, mac_idx); 2117 break; 2118 case RTW89_CTRL: 2119 reg = rtw89_mac_reg_by_idx(R_AX_CTRL_FLTR, mac_idx); 2120 break; 2121 case RTW89_DATA: 2122 reg = rtw89_mac_reg_by_idx(R_AX_DATA_FLTR, mac_idx); 2123 break; 2124 default: 2125 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2126 return -EINVAL; 2127 } 2128 rtw89_write32(rtwdev, reg, val); 2129 2130 return 0; 2131 } 2132 2133 static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2134 { 2135 int ret, i; 2136 u32 mac_ftlr, plcp_ftlr; 2137 2138 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2139 if (ret) 2140 return ret; 2141 2142 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2143 ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST, 2144 mac_idx); 2145 if (ret) 2146 return ret; 2147 } 2148 mac_ftlr = rtwdev->hal.rx_fltr; 2149 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2150 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2151 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2152 B_AX_HE_SIGB_CRC_CHK; 2153 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx), 2154 mac_ftlr); 2155 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx), 2156 plcp_ftlr); 2157 2158 return 0; 2159 } 2160 2161 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2162 { 2163 u32 reg, val32; 2164 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2165 2166 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2167 B_AX_RSP_CHK_BASIC_NAV; 2168 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2169 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2170 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2171 2172 switch (rtwdev->chip->chip_id) { 2173 case RTL8852A: 2174 case RTL8852B: 2175 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 2176 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2177 rtw89_write32(rtwdev, reg, val32); 2178 2179 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2180 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2181 rtw89_write32(rtwdev, reg, val32); 2182 break; 2183 default: 2184 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 2185 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2186 rtw89_write32(rtwdev, reg, val32); 2187 2188 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2189 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2190 rtw89_write32(rtwdev, reg, val32); 2191 break; 2192 } 2193 } 2194 2195 static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2196 { 2197 u32 val, reg; 2198 int ret; 2199 2200 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2201 if (ret) 2202 return ret; 2203 2204 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CONTROL, mac_idx); 2205 val = rtw89_read32(rtwdev, reg); 2206 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2207 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2208 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2209 B_AX_CTN_CHK_INTRA_NAV | 2210 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2211 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2212 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2213 B_AX_CTN_CHK_CCA_P20); 2214 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2215 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2216 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2217 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2218 B_AX_SIFS_CHK_EDCCA); 2219 2220 rtw89_write32(rtwdev, reg, val); 2221 2222 _patch_dis_resp_chk(rtwdev, mac_idx); 2223 2224 return 0; 2225 } 2226 2227 static int nav_ctrl_init(struct rtw89_dev *rtwdev) 2228 { 2229 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2230 B_AX_WMAC_TF_UP_NAV_EN | 2231 B_AX_WMAC_NAV_UPPER_EN); 2232 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2233 2234 return 0; 2235 } 2236 2237 static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2238 { 2239 u32 reg; 2240 int ret; 2241 2242 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2243 if (ret) 2244 return ret; 2245 reg = rtw89_mac_reg_by_idx(R_AX_RX_SR_CTRL, mac_idx); 2246 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2247 2248 return 0; 2249 } 2250 2251 static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2252 { 2253 u32 reg; 2254 int ret; 2255 2256 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2257 if (ret) 2258 return ret; 2259 2260 reg = rtw89_mac_reg_by_idx(R_AX_MAC_LOOPBACK, mac_idx); 2261 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2262 2263 reg = rtw89_mac_reg_by_idx(R_AX_TCR0, mac_idx); 2264 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2265 2266 reg = rtw89_mac_reg_by_idx(R_AX_TXD_FIFO_CTRL, mac_idx); 2267 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2268 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2269 2270 return 0; 2271 } 2272 2273 static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2274 { 2275 const struct rtw89_chip_info *chip = rtwdev->chip; 2276 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2277 u32 reg, val, sifs; 2278 int ret; 2279 2280 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2281 if (ret) 2282 return ret; 2283 2284 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2285 val = rtw89_read32(rtwdev, reg); 2286 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2287 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2288 2289 switch (rtwdev->chip->chip_id) { 2290 case RTL8852A: 2291 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2292 break; 2293 case RTL8852B: 2294 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2295 break; 2296 default: 2297 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2298 break; 2299 } 2300 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2301 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2302 rtw89_write32(rtwdev, reg, val); 2303 2304 reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx); 2305 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2306 2307 reg = rtw89_mac_reg_by_idx(rrsr->ref_rate.addr, mac_idx); 2308 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2309 reg = rtw89_mac_reg_by_idx(rrsr->rsc.addr, mac_idx); 2310 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2311 2312 return 0; 2313 } 2314 2315 static void rst_bacam(struct rtw89_dev *rtwdev) 2316 { 2317 u32 val32; 2318 int ret; 2319 2320 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2321 S_AX_BACAM_RST_ALL); 2322 2323 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2324 1, 1000, false, 2325 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2326 if (ret) 2327 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2328 } 2329 2330 static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2331 { 2332 #define TRXCFG_RMAC_CCA_TO 32 2333 #define TRXCFG_RMAC_DATA_TO 15 2334 #define RX_MAX_LEN_UNIT 512 2335 #define PLD_RLS_MAX_PG 127 2336 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2337 int ret; 2338 u32 reg, rx_max_len, rx_qta; 2339 u16 val; 2340 2341 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2342 if (ret) 2343 return ret; 2344 2345 if (mac_idx == RTW89_MAC_0) 2346 rst_bacam(rtwdev); 2347 2348 reg = rtw89_mac_reg_by_idx(R_AX_RESPBA_CAM_CTRL, mac_idx); 2349 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2350 2351 reg = rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx); 2352 val = rtw89_read16(rtwdev, reg); 2353 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2354 B_AX_RX_DLK_DATA_TIME_MASK); 2355 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2356 B_AX_RX_DLK_CCA_TIME_MASK); 2357 rtw89_write16(rtwdev, reg, val); 2358 2359 reg = rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx); 2360 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2361 2362 reg = rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx); 2363 if (mac_idx == RTW89_MAC_0) 2364 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2365 else 2366 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2367 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2368 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2369 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2370 rx_max_len /= RX_MAX_LEN_UNIT; 2371 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2372 2373 if (rtwdev->chip->chip_id == RTL8852A && 2374 rtwdev->hal.cv == CHIP_CBV) { 2375 rtw89_write16_mask(rtwdev, 2376 rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx), 2377 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2378 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx), 2379 BIT(12)); 2380 } 2381 2382 reg = rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx); 2383 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2384 2385 return ret; 2386 } 2387 2388 static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2389 { 2390 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2391 u32 val, reg; 2392 int ret; 2393 2394 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2395 if (ret) 2396 return ret; 2397 2398 reg = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2399 val = rtw89_read32(rtwdev, reg); 2400 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2401 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2402 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2403 rtw89_write32(rtwdev, reg, val); 2404 2405 if (chip_id == RTL8852A || chip_id == RTL8852B) { 2406 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_RRSR1, mac_idx); 2407 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2408 } 2409 2410 return 0; 2411 } 2412 2413 static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2414 { 2415 const struct rtw89_dle_mem *cfg; 2416 2417 cfg = get_dle_mem_cfg(rtwdev, mode); 2418 if (!cfg) { 2419 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2420 return false; 2421 } 2422 2423 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2424 } 2425 2426 static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2427 { 2428 u32 val, reg; 2429 int ret; 2430 2431 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2432 if (ret) 2433 return ret; 2434 2435 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2436 reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); 2437 val = rtw89_read32(rtwdev, reg); 2438 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2439 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2440 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2441 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2442 val |= B_AX_HW_CTS2SELF_EN; 2443 rtw89_write32(rtwdev, reg, val); 2444 2445 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_FSM_MON, mac_idx); 2446 val = rtw89_read32(rtwdev, reg); 2447 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2448 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2449 rtw89_write32(rtwdev, reg, val); 2450 } 2451 2452 if (mac_idx == RTW89_MAC_0) { 2453 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2454 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2455 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2456 B_AX_PTCL_TRIGGER_SS_EN_0 | 2457 B_AX_PTCL_TRIGGER_SS_EN_1 | 2458 B_AX_PTCL_TRIGGER_SS_EN_UL); 2459 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2460 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2461 } else if (mac_idx == RTW89_MAC_1) { 2462 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2463 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2464 } 2465 2466 return 0; 2467 } 2468 2469 static int cmac_dma_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2470 { 2471 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2472 u32 reg; 2473 int ret; 2474 2475 if (chip_id != RTL8852A && chip_id != RTL8852B) 2476 return 0; 2477 2478 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2479 if (ret) 2480 return ret; 2481 2482 reg = rtw89_mac_reg_by_idx(R_AX_RXDMA_CTRL_0, mac_idx); 2483 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2484 2485 return 0; 2486 } 2487 2488 static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2489 { 2490 int ret; 2491 2492 ret = scheduler_init(rtwdev, mac_idx); 2493 if (ret) { 2494 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2495 return ret; 2496 } 2497 2498 ret = addr_cam_init(rtwdev, mac_idx); 2499 if (ret) { 2500 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2501 ret); 2502 return ret; 2503 } 2504 2505 ret = rx_fltr_init(rtwdev, mac_idx); 2506 if (ret) { 2507 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2508 ret); 2509 return ret; 2510 } 2511 2512 ret = cca_ctrl_init(rtwdev, mac_idx); 2513 if (ret) { 2514 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2515 ret); 2516 return ret; 2517 } 2518 2519 ret = nav_ctrl_init(rtwdev); 2520 if (ret) { 2521 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2522 ret); 2523 return ret; 2524 } 2525 2526 ret = spatial_reuse_init(rtwdev, mac_idx); 2527 if (ret) { 2528 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2529 mac_idx, ret); 2530 return ret; 2531 } 2532 2533 ret = tmac_init(rtwdev, mac_idx); 2534 if (ret) { 2535 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2536 return ret; 2537 } 2538 2539 ret = trxptcl_init(rtwdev, mac_idx); 2540 if (ret) { 2541 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2542 return ret; 2543 } 2544 2545 ret = rmac_init(rtwdev, mac_idx); 2546 if (ret) { 2547 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2548 return ret; 2549 } 2550 2551 ret = cmac_com_init(rtwdev, mac_idx); 2552 if (ret) { 2553 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2554 return ret; 2555 } 2556 2557 ret = ptcl_init(rtwdev, mac_idx); 2558 if (ret) { 2559 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2560 return ret; 2561 } 2562 2563 ret = cmac_dma_init(rtwdev, mac_idx); 2564 if (ret) { 2565 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2566 return ret; 2567 } 2568 2569 return ret; 2570 } 2571 2572 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2573 struct rtw89_mac_c2h_info *c2h_info) 2574 { 2575 struct rtw89_mac_h2c_info h2c_info = {0}; 2576 u32 ret; 2577 2578 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2579 h2c_info.content_len = 0; 2580 2581 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2582 if (ret) 2583 return ret; 2584 2585 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2586 return -EINVAL; 2587 2588 return 0; 2589 } 2590 2591 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2592 { 2593 struct rtw89_hal *hal = &rtwdev->hal; 2594 const struct rtw89_chip_info *chip = rtwdev->chip; 2595 struct rtw89_mac_c2h_info c2h_info = {0}; 2596 u8 tx_nss; 2597 u8 rx_nss; 2598 u8 tx_ant; 2599 u8 rx_ant; 2600 u32 ret; 2601 2602 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2603 if (ret) 2604 return ret; 2605 2606 tx_nss = RTW89_GET_C2H_PHYCAP_TX_NSS(c2h_info.c2hreg); 2607 rx_nss = RTW89_GET_C2H_PHYCAP_RX_NSS(c2h_info.c2hreg); 2608 tx_ant = RTW89_GET_C2H_PHYCAP_ANT_TX_NUM(c2h_info.c2hreg); 2609 rx_ant = RTW89_GET_C2H_PHYCAP_ANT_RX_NUM(c2h_info.c2hreg); 2610 2611 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2612 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2613 2614 if (tx_ant == 1) 2615 hal->antenna_tx = RF_B; 2616 if (rx_ant == 1) 2617 hal->antenna_rx = RF_B; 2618 2619 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2620 hal->antenna_tx = RF_B; 2621 hal->tx_path_diversity = true; 2622 } 2623 2624 rtw89_debug(rtwdev, RTW89_DBG_FW, 2625 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2626 hal->tx_nss, tx_nss, chip->tx_nss, 2627 hal->rx_nss, rx_nss, chip->rx_nss); 2628 rtw89_debug(rtwdev, RTW89_DBG_FW, 2629 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2630 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2631 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2632 2633 return 0; 2634 } 2635 2636 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2637 u16 tx_en_u16, u16 mask_u16) 2638 { 2639 u32 ret; 2640 struct rtw89_mac_c2h_info c2h_info = {0}; 2641 struct rtw89_mac_h2c_info h2c_info = {0}; 2642 struct rtw89_h2creg_sch_tx_en *h2creg = 2643 (struct rtw89_h2creg_sch_tx_en *)h2c_info.h2creg; 2644 2645 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2646 h2c_info.content_len = sizeof(*h2creg) - RTW89_H2CREG_HDR_LEN; 2647 h2creg->tx_en = tx_en_u16; 2648 h2creg->mask = mask_u16; 2649 h2creg->band = band; 2650 2651 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2652 if (ret) 2653 return ret; 2654 2655 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2656 return -EINVAL; 2657 2658 return 0; 2659 } 2660 2661 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2662 u16 tx_en, u16 tx_en_mask) 2663 { 2664 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx); 2665 u16 val; 2666 int ret; 2667 2668 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2669 if (ret) 2670 return ret; 2671 2672 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 2673 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 2674 tx_en, tx_en_mask); 2675 2676 val = rtw89_read16(rtwdev, reg); 2677 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2678 rtw89_write16(rtwdev, reg, val); 2679 2680 return 0; 2681 } 2682 2683 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2684 u32 tx_en, u32 tx_en_mask) 2685 { 2686 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx); 2687 u32 val; 2688 int ret; 2689 2690 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2691 if (ret) 2692 return ret; 2693 2694 val = rtw89_read32(rtwdev, reg); 2695 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2696 rtw89_write32(rtwdev, reg, val); 2697 2698 return 0; 2699 } 2700 2701 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 2702 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2703 { 2704 int ret; 2705 2706 *tx_en = rtw89_read16(rtwdev, 2707 rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx)); 2708 2709 switch (sel) { 2710 case RTW89_SCH_TX_SEL_ALL: 2711 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2712 B_AX_CTN_TXEN_ALL_MASK); 2713 if (ret) 2714 return ret; 2715 break; 2716 case RTW89_SCH_TX_SEL_HIQ: 2717 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2718 0, B_AX_CTN_TXEN_HGQ); 2719 if (ret) 2720 return ret; 2721 break; 2722 case RTW89_SCH_TX_SEL_MG0: 2723 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2724 0, B_AX_CTN_TXEN_MGQ); 2725 if (ret) 2726 return ret; 2727 break; 2728 case RTW89_SCH_TX_SEL_MACID: 2729 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2730 B_AX_CTN_TXEN_ALL_MASK); 2731 if (ret) 2732 return ret; 2733 break; 2734 default: 2735 return 0; 2736 } 2737 2738 return 0; 2739 } 2740 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 2741 2742 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2743 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2744 { 2745 int ret; 2746 2747 *tx_en = rtw89_read32(rtwdev, 2748 rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx)); 2749 2750 switch (sel) { 2751 case RTW89_SCH_TX_SEL_ALL: 2752 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2753 B_AX_CTN_TXEN_ALL_MASK_V1); 2754 if (ret) 2755 return ret; 2756 break; 2757 case RTW89_SCH_TX_SEL_HIQ: 2758 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2759 0, B_AX_CTN_TXEN_HGQ); 2760 if (ret) 2761 return ret; 2762 break; 2763 case RTW89_SCH_TX_SEL_MG0: 2764 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2765 0, B_AX_CTN_TXEN_MGQ); 2766 if (ret) 2767 return ret; 2768 break; 2769 case RTW89_SCH_TX_SEL_MACID: 2770 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2771 B_AX_CTN_TXEN_ALL_MASK_V1); 2772 if (ret) 2773 return ret; 2774 break; 2775 default: 2776 return 0; 2777 } 2778 2779 return 0; 2780 } 2781 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 2782 2783 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2784 { 2785 int ret; 2786 2787 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 2788 if (ret) 2789 return ret; 2790 2791 return 0; 2792 } 2793 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 2794 2795 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2796 { 2797 int ret; 2798 2799 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 2800 B_AX_CTN_TXEN_ALL_MASK_V1); 2801 if (ret) 2802 return ret; 2803 2804 return 0; 2805 } 2806 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 2807 2808 u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd) 2809 { 2810 u32 val, reg; 2811 int ret; 2812 2813 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 2814 val = buf_len; 2815 val |= B_AX_WD_BUF_REQ_EXEC; 2816 rtw89_write32(rtwdev, reg, val); 2817 2818 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 2819 2820 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 2821 1, 2000, false, rtwdev, reg); 2822 if (ret) 2823 return 0xffff; 2824 2825 return FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 2826 } 2827 2828 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, 2829 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 2830 { 2831 u32 val, cmd_type, reg; 2832 int ret; 2833 2834 cmd_type = ctrl_para->cmd_type; 2835 2836 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 2837 val = 0; 2838 val = u32_replace_bits(val, ctrl_para->start_pktid, 2839 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 2840 val = u32_replace_bits(val, ctrl_para->end_pktid, 2841 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 2842 rtw89_write32(rtwdev, reg, val); 2843 2844 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 2845 val = 0; 2846 val = u32_replace_bits(val, ctrl_para->src_pid, 2847 B_AX_CPUQ_OP_SRC_PID_MASK); 2848 val = u32_replace_bits(val, ctrl_para->src_qid, 2849 B_AX_CPUQ_OP_SRC_QID_MASK); 2850 val = u32_replace_bits(val, ctrl_para->dst_pid, 2851 B_AX_CPUQ_OP_DST_PID_MASK); 2852 val = u32_replace_bits(val, ctrl_para->dst_qid, 2853 B_AX_CPUQ_OP_DST_QID_MASK); 2854 rtw89_write32(rtwdev, reg, val); 2855 2856 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 2857 val = 0; 2858 val = u32_replace_bits(val, cmd_type, 2859 B_AX_CPUQ_OP_CMD_TYPE_MASK); 2860 val = u32_replace_bits(val, ctrl_para->macid, 2861 B_AX_CPUQ_OP_MACID_MASK); 2862 val = u32_replace_bits(val, ctrl_para->pkt_num, 2863 B_AX_CPUQ_OP_PKTNUM_MASK); 2864 val |= B_AX_WD_CPUQ_OP_EXEC; 2865 rtw89_write32(rtwdev, reg, val); 2866 2867 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 2868 2869 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 2870 1, 2000, false, rtwdev, reg); 2871 if (ret) 2872 return ret; 2873 2874 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 2875 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 2876 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 2877 2878 return 0; 2879 } 2880 2881 static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2882 { 2883 const struct rtw89_dle_mem *cfg; 2884 struct rtw89_cpuio_ctrl ctrl_para = {0}; 2885 u16 pkt_id; 2886 int ret; 2887 2888 cfg = get_dle_mem_cfg(rtwdev, mode); 2889 if (!cfg) { 2890 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2891 return -EINVAL; 2892 } 2893 2894 if (dle_used_size(cfg->wde_size, cfg->ple_size) != 2895 dle_expected_used_size(rtwdev, mode)) { 2896 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2897 return -EINVAL; 2898 } 2899 2900 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 2901 2902 pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, true); 2903 if (pkt_id == 0xffff) { 2904 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 2905 return -ENOMEM; 2906 } 2907 2908 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2909 ctrl_para.start_pktid = pkt_id; 2910 ctrl_para.end_pktid = pkt_id; 2911 ctrl_para.pkt_num = 0; 2912 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 2913 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 2914 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true); 2915 if (ret) { 2916 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 2917 return -EFAULT; 2918 } 2919 2920 pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, false); 2921 if (pkt_id == 0xffff) { 2922 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 2923 return -ENOMEM; 2924 } 2925 2926 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2927 ctrl_para.start_pktid = pkt_id; 2928 ctrl_para.end_pktid = pkt_id; 2929 ctrl_para.pkt_num = 0; 2930 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 2931 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 2932 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false); 2933 if (ret) { 2934 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 2935 return -EFAULT; 2936 } 2937 2938 return 0; 2939 } 2940 2941 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 2942 { 2943 int ret; 2944 u32 reg; 2945 u8 val; 2946 2947 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2948 if (ret) 2949 return ret; 2950 2951 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_TX_CTN_SEL, mac_idx); 2952 2953 ret = read_poll_timeout(rtw89_read8, val, 2954 (val & B_AX_PTCL_TX_ON_STAT) == 0, 2955 SW_CVR_DUR_US, 2956 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 2957 false, rtwdev, reg); 2958 if (ret) 2959 return ret; 2960 2961 return 0; 2962 } 2963 2964 static int band1_enable(struct rtw89_dev *rtwdev) 2965 { 2966 int ret, i; 2967 u32 sleep_bak[4] = {0}; 2968 u32 pause_bak[4] = {0}; 2969 u32 tx_en; 2970 2971 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 2972 if (ret) { 2973 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 2974 return ret; 2975 } 2976 2977 for (i = 0; i < 4; i++) { 2978 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 2979 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 2980 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 2981 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 2982 } 2983 2984 ret = band_idle_ck_b(rtwdev, 0); 2985 if (ret) { 2986 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 2987 return ret; 2988 } 2989 2990 ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode); 2991 if (ret) { 2992 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 2993 return ret; 2994 } 2995 2996 for (i = 0; i < 4; i++) { 2997 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 2998 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 2999 } 3000 3001 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3002 if (ret) { 3003 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3004 return ret; 3005 } 3006 3007 ret = cmac_func_en(rtwdev, 1, true); 3008 if (ret) { 3009 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3010 return ret; 3011 } 3012 3013 ret = cmac_init(rtwdev, 1); 3014 if (ret) { 3015 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3016 return ret; 3017 } 3018 3019 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3020 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3021 3022 return 0; 3023 } 3024 3025 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3026 { 3027 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3028 3029 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3030 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3031 } 3032 3033 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3034 { 3035 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3036 3037 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3038 } 3039 3040 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3041 { 3042 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3043 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3044 3045 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3046 B_AX_TX_GET_ERRPKTID_INT_EN | 3047 B_AX_TX_NXT_ERRPKTID_INT_EN | 3048 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3049 B_AX_TX_OFFSET_ERR_INT_EN | 3050 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3051 if (chip_id == RTL8852C) 3052 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3053 B_AX_TX_ETH_TYPE_ERR_EN | 3054 B_AX_TX_LLC_PRE_ERR_EN | 3055 B_AX_TX_NW_TYPE_ERR_EN | 3056 B_AX_TX_KSRCH_ERR_EN); 3057 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3058 imr->mpdu_tx_imr_set); 3059 3060 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3061 B_AX_GETPKTID_ERR_INT_EN | 3062 B_AX_MHDRLEN_ERR_INT_EN | 3063 B_AX_RPT_ERR_INT_EN); 3064 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3065 imr->mpdu_rx_imr_set); 3066 } 3067 3068 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3069 { 3070 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3071 3072 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3073 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3074 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3075 B_AX_PLE_B_PKTID_ERR_INT_EN); 3076 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3077 imr->sta_sch_imr_set); 3078 } 3079 3080 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3081 { 3082 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3083 3084 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3085 imr->txpktctl_imr_b0_clr); 3086 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3087 imr->txpktctl_imr_b0_set); 3088 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3089 imr->txpktctl_imr_b1_clr); 3090 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3091 imr->txpktctl_imr_b1_set); 3092 } 3093 3094 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3095 { 3096 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3097 3098 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3099 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3100 } 3101 3102 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3103 { 3104 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3105 3106 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3107 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3108 } 3109 3110 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3111 { 3112 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3113 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3114 } 3115 3116 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3117 { 3118 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3119 3120 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3121 imr->host_disp_imr_clr); 3122 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3123 imr->host_disp_imr_set); 3124 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3125 imr->cpu_disp_imr_clr); 3126 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3127 imr->cpu_disp_imr_set); 3128 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3129 imr->other_disp_imr_clr); 3130 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3131 imr->other_disp_imr_set); 3132 } 3133 3134 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3135 { 3136 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3137 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3138 } 3139 3140 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3141 { 3142 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3143 3144 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3145 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3146 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3147 B_AX_BBRPT_CHINFO_IMR_CLR); 3148 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3149 imr->bbrpt_err_imr_set); 3150 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3151 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3152 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3153 } 3154 3155 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3156 { 3157 u32 reg; 3158 3159 reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx); 3160 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3161 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3162 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3163 } 3164 3165 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3166 { 3167 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3168 u32 reg; 3169 3170 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx); 3171 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3172 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3173 } 3174 3175 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3176 { 3177 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3178 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3179 u32 reg; 3180 3181 reg = rtw89_mac_reg_by_idx(imr->cdma_imr_0_reg, mac_idx); 3182 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3183 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3184 3185 if (chip_id == RTL8852C) { 3186 reg = rtw89_mac_reg_by_idx(imr->cdma_imr_1_reg, mac_idx); 3187 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3188 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3189 } 3190 } 3191 3192 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3193 { 3194 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3195 u32 reg; 3196 3197 reg = rtw89_mac_reg_by_idx(imr->phy_intf_imr_reg, mac_idx); 3198 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3199 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3200 } 3201 3202 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3203 { 3204 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3205 u32 reg; 3206 3207 reg = rtw89_mac_reg_by_idx(imr->rmac_imr_reg, mac_idx); 3208 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3209 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3210 } 3211 3212 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3213 { 3214 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3215 u32 reg; 3216 3217 reg = rtw89_mac_reg_by_idx(imr->tmac_imr_reg, mac_idx); 3218 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3219 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3220 } 3221 3222 static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, 3223 enum rtw89_mac_hwmod_sel sel) 3224 { 3225 int ret; 3226 3227 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3228 if (ret) { 3229 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3230 sel, mac_idx); 3231 return ret; 3232 } 3233 3234 if (sel == RTW89_DMAC_SEL) { 3235 rtw89_wdrls_imr_enable(rtwdev); 3236 rtw89_wsec_imr_enable(rtwdev); 3237 rtw89_mpdu_trx_imr_enable(rtwdev); 3238 rtw89_sta_sch_imr_enable(rtwdev); 3239 rtw89_txpktctl_imr_enable(rtwdev); 3240 rtw89_wde_imr_enable(rtwdev); 3241 rtw89_ple_imr_enable(rtwdev); 3242 rtw89_pktin_imr_enable(rtwdev); 3243 rtw89_dispatcher_imr_enable(rtwdev); 3244 rtw89_cpuio_imr_enable(rtwdev); 3245 rtw89_bbrpt_imr_enable(rtwdev); 3246 } else if (sel == RTW89_CMAC_SEL) { 3247 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3248 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3249 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3250 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3251 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3252 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3253 } else { 3254 return -EINVAL; 3255 } 3256 3257 return 0; 3258 } 3259 3260 static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en) 3261 { 3262 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3263 3264 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3265 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3266 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3267 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3268 if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta) 3269 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3270 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3271 } 3272 3273 static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) 3274 { 3275 int ret = 0; 3276 3277 if (enable) { 3278 ret = band1_enable(rtwdev); 3279 if (ret) { 3280 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3281 return ret; 3282 } 3283 3284 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3285 if (ret) { 3286 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3287 return ret; 3288 } 3289 } else { 3290 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3291 return -EINVAL; 3292 } 3293 3294 return 0; 3295 } 3296 3297 static int set_host_rpr(struct rtw89_dev *rtwdev) 3298 { 3299 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3300 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3301 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3302 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3303 B_AX_RLSRPT0_FLTR_MAP_MASK); 3304 } else { 3305 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3306 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3307 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3308 B_AX_RLSRPT0_FLTR_MAP_MASK); 3309 } 3310 3311 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3312 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3313 3314 return 0; 3315 } 3316 3317 static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) 3318 { 3319 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3320 int ret; 3321 3322 ret = dmac_init(rtwdev, 0); 3323 if (ret) { 3324 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3325 return ret; 3326 } 3327 3328 ret = cmac_init(rtwdev, 0); 3329 if (ret) { 3330 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3331 return ret; 3332 } 3333 3334 if (is_qta_dbcc(rtwdev, qta_mode)) { 3335 ret = rtw89_mac_dbcc_enable(rtwdev, true); 3336 if (ret) { 3337 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3338 return ret; 3339 } 3340 } 3341 3342 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3343 if (ret) { 3344 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3345 return ret; 3346 } 3347 3348 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3349 if (ret) { 3350 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3351 return ret; 3352 } 3353 3354 rtw89_mac_err_imr_ctrl(rtwdev, true); 3355 3356 ret = set_host_rpr(rtwdev); 3357 if (ret) { 3358 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3359 return ret; 3360 } 3361 3362 return 0; 3363 } 3364 3365 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3366 { 3367 u32 val32; 3368 3369 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3370 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3371 3372 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3373 val32 |= B_AX_FS_WDT_INT; 3374 val32 &= ~B_AX_FS_WDT_INT_MSK; 3375 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3376 } 3377 3378 void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev) 3379 { 3380 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3381 3382 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3383 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3384 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3385 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3386 3387 rtw89_disable_fw_watchdog(rtwdev); 3388 3389 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3390 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3391 } 3392 3393 int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw) 3394 { 3395 u32 val; 3396 int ret; 3397 3398 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3399 return -EFAULT; 3400 3401 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3402 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3403 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3404 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3405 3406 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3407 3408 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3409 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3410 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3411 B_AX_WCPU_FWDL_STS_MASK); 3412 3413 if (dlfw) 3414 val |= B_AX_WCPU_FWDL_EN; 3415 3416 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3417 3418 if (rtwdev->chip->chip_id == RTL8852B) 3419 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 3420 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 3421 3422 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3423 boot_reason); 3424 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3425 3426 if (!dlfw) { 3427 mdelay(5); 3428 3429 ret = rtw89_fw_check_rdy(rtwdev); 3430 if (ret) 3431 return ret; 3432 } 3433 3434 return 0; 3435 } 3436 3437 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3438 { 3439 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3440 u32 val; 3441 int ret; 3442 3443 if (chip_id == RTL8852C) 3444 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3445 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3446 else 3447 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3448 B_AX_PKT_BUF_EN; 3449 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3450 3451 val = B_AX_DISPATCHER_CLK_EN; 3452 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3453 3454 if (chip_id != RTL8852C) 3455 goto dle; 3456 3457 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3458 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3459 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3460 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3461 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3462 3463 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3464 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3465 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3466 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3467 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3468 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3469 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3470 3471 dle: 3472 ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3473 if (ret) { 3474 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3475 return ret; 3476 } 3477 3478 ret = hfc_init(rtwdev, true, false, true); 3479 if (ret) { 3480 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3481 return ret; 3482 } 3483 3484 return ret; 3485 } 3486 3487 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3488 { 3489 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3490 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3491 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3492 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3493 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3494 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3495 3496 return 0; 3497 } 3498 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3499 3500 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3501 { 3502 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3503 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3504 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3505 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3506 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3507 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3508 3509 return 0; 3510 } 3511 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3512 3513 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev) 3514 { 3515 int ret; 3516 3517 ret = rtw89_mac_power_switch(rtwdev, true); 3518 if (ret) { 3519 rtw89_mac_power_switch(rtwdev, false); 3520 ret = rtw89_mac_power_switch(rtwdev, true); 3521 if (ret) 3522 return ret; 3523 } 3524 3525 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3526 3527 ret = rtw89_mac_dmac_pre_init(rtwdev); 3528 if (ret) 3529 return ret; 3530 3531 if (rtwdev->hci.ops->mac_pre_init) { 3532 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3533 if (ret) 3534 return ret; 3535 } 3536 3537 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL); 3538 if (ret) 3539 return ret; 3540 3541 return 0; 3542 } 3543 3544 int rtw89_mac_init(struct rtw89_dev *rtwdev) 3545 { 3546 int ret; 3547 3548 ret = rtw89_mac_partial_init(rtwdev); 3549 if (ret) 3550 goto fail; 3551 3552 ret = rtw89_chip_enable_bb_rf(rtwdev); 3553 if (ret) 3554 goto fail; 3555 3556 ret = rtw89_mac_sys_init(rtwdev); 3557 if (ret) 3558 goto fail; 3559 3560 ret = rtw89_mac_trx_init(rtwdev); 3561 if (ret) 3562 goto fail; 3563 3564 if (rtwdev->hci.ops->mac_post_init) { 3565 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3566 if (ret) 3567 goto fail; 3568 } 3569 3570 rtw89_fw_send_all_early_h2c(rtwdev); 3571 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3572 3573 return ret; 3574 fail: 3575 rtw89_mac_power_switch(rtwdev, false); 3576 3577 return ret; 3578 } 3579 3580 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3581 { 3582 u8 i; 3583 3584 for (i = 0; i < 4; i++) { 3585 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3586 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 3587 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 3588 } 3589 } 3590 3591 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3592 { 3593 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3594 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 3595 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 3596 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 3597 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 3598 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 3599 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 3600 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 3601 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 3602 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 3603 } 3604 3605 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 3606 { 3607 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 3608 u8 grp = macid >> 5; 3609 int ret; 3610 3611 /* If this is called by change_interface() in the case of P2P, it could 3612 * be power-off, so ignore this operation. 3613 */ 3614 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 3615 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3616 return 0; 3617 3618 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3619 if (ret) 3620 return ret; 3621 3622 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 3623 3624 return 0; 3625 } 3626 3627 static const struct rtw89_port_reg rtw_port_base = { 3628 .port_cfg = R_AX_PORT_CFG_P0, 3629 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 3630 .bcn_area = R_AX_BCN_AREA_P0, 3631 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 3632 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 3633 .tbtt_agg = R_AX_TBTT_AGG_P0, 3634 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 3635 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 3636 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 3637 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 3638 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 3639 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 3640 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 3641 .tsftr_l = R_AX_TSFTR_LOW_P0, 3642 .tsftr_h = R_AX_TSFTR_HIGH_P0 3643 }; 3644 3645 #define BCN_INTERVAL 100 3646 #define BCN_ERLY_DEF 160 3647 #define BCN_SETUP_DEF 2 3648 #define BCN_HOLD_DEF 200 3649 #define BCN_MASK_DEF 0 3650 #define TBTT_ERLY_DEF 5 3651 #define BCN_SET_UNIT 32 3652 #define BCN_ERLY_SET_DLY (10 * 2) 3653 3654 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 3655 struct rtw89_vif *rtwvif) 3656 { 3657 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3658 const struct rtw89_port_reg *p = &rtw_port_base; 3659 3660 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 3661 return; 3662 3663 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 3664 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 3665 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 3666 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 3667 3668 msleep(vif->bss_conf.beacon_int + 1); 3669 3670 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 3671 B_AX_BRK_SETUP); 3672 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 3673 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 3674 } 3675 3676 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 3677 struct rtw89_vif *rtwvif, bool en) 3678 { 3679 const struct rtw89_port_reg *p = &rtw_port_base; 3680 3681 if (en) 3682 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3683 else 3684 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3685 } 3686 3687 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 3688 struct rtw89_vif *rtwvif, bool en) 3689 { 3690 const struct rtw89_port_reg *p = &rtw_port_base; 3691 3692 if (en) 3693 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3694 else 3695 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3696 } 3697 3698 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 3699 struct rtw89_vif *rtwvif) 3700 { 3701 const struct rtw89_port_reg *p = &rtw_port_base; 3702 3703 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 3704 rtwvif->net_type); 3705 } 3706 3707 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 3708 struct rtw89_vif *rtwvif) 3709 { 3710 const struct rtw89_port_reg *p = &rtw_port_base; 3711 bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 3712 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 3713 3714 if (en) 3715 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 3716 else 3717 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 3718 } 3719 3720 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 3721 struct rtw89_vif *rtwvif) 3722 { 3723 const struct rtw89_port_reg *p = &rtw_port_base; 3724 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3725 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3726 u32 bit = B_AX_RX_BSSID_FIT_EN; 3727 3728 if (en) 3729 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 3730 else 3731 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 3732 } 3733 3734 static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 3735 struct rtw89_vif *rtwvif) 3736 { 3737 const struct rtw89_port_reg *p = &rtw_port_base; 3738 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3739 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3740 3741 if (en) 3742 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3743 else 3744 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3745 } 3746 3747 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 3748 struct rtw89_vif *rtwvif) 3749 { 3750 const struct rtw89_port_reg *p = &rtw_port_base; 3751 bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 3752 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3753 3754 if (en) 3755 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3756 else 3757 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3758 } 3759 3760 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 3761 struct rtw89_vif *rtwvif) 3762 { 3763 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3764 const struct rtw89_port_reg *p = &rtw_port_base; 3765 u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 3766 3767 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 3768 bcn_int); 3769 } 3770 3771 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 3772 struct rtw89_vif *rtwvif) 3773 { 3774 static const u32 hiq_win_addr[RTW89_PORT_NUM] = { 3775 R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 3776 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 3777 R_AX_PORT_HGQ_WINDOW_CFG + 3, 3778 }; 3779 u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 3780 u8 port = rtwvif->port; 3781 u32 reg; 3782 3783 reg = rtw89_mac_reg_by_idx(hiq_win_addr[port], rtwvif->mac_idx); 3784 rtw89_write8(rtwdev, reg, win); 3785 } 3786 3787 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 3788 struct rtw89_vif *rtwvif) 3789 { 3790 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3791 const struct rtw89_port_reg *p = &rtw_port_base; 3792 u32 addr; 3793 3794 addr = rtw89_mac_reg_by_idx(R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx); 3795 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 3796 3797 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 3798 vif->bss_conf.dtim_period); 3799 } 3800 3801 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 3802 struct rtw89_vif *rtwvif) 3803 { 3804 const struct rtw89_port_reg *p = &rtw_port_base; 3805 3806 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3807 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 3808 } 3809 3810 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 3811 struct rtw89_vif *rtwvif) 3812 { 3813 const struct rtw89_port_reg *p = &rtw_port_base; 3814 3815 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3816 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 3817 } 3818 3819 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 3820 struct rtw89_vif *rtwvif) 3821 { 3822 const struct rtw89_port_reg *p = &rtw_port_base; 3823 3824 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 3825 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 3826 } 3827 3828 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 3829 struct rtw89_vif *rtwvif) 3830 { 3831 const struct rtw89_port_reg *p = &rtw_port_base; 3832 3833 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 3834 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 3835 } 3836 3837 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 3838 struct rtw89_vif *rtwvif) 3839 { 3840 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3841 static const u32 masks[RTW89_PORT_NUM] = { 3842 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 3843 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 3844 B_AX_BSS_COLOB_AX_PORT_4_MASK, 3845 }; 3846 u8 port = rtwvif->port; 3847 u32 reg_base; 3848 u32 reg; 3849 u8 bss_color; 3850 3851 bss_color = vif->bss_conf.he_bss_color.color; 3852 reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0; 3853 reg = rtw89_mac_reg_by_idx(reg_base, rtwvif->mac_idx); 3854 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 3855 } 3856 3857 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 3858 struct rtw89_vif *rtwvif) 3859 { 3860 u8 port = rtwvif->port; 3861 u32 reg; 3862 3863 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 3864 return; 3865 3866 if (port == 0) { 3867 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_CTRL, rtwvif->mac_idx); 3868 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 3869 } 3870 } 3871 3872 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 3873 struct rtw89_vif *rtwvif) 3874 { 3875 u8 port = rtwvif->port; 3876 u32 reg; 3877 u32 val; 3878 3879 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_DROP_0, rtwvif->mac_idx); 3880 val = rtw89_read32(rtwdev, reg); 3881 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 3882 if (port == 0) 3883 val &= ~BIT(0); 3884 rtw89_write32(rtwdev, reg, val); 3885 } 3886 3887 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 3888 struct rtw89_vif *rtwvif, bool enable) 3889 { 3890 const struct rtw89_port_reg *p = &rtw_port_base; 3891 3892 if (enable) 3893 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, 3894 B_AX_PORT_FUNC_EN); 3895 else 3896 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, 3897 B_AX_PORT_FUNC_EN); 3898 } 3899 3900 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 3901 struct rtw89_vif *rtwvif) 3902 { 3903 const struct rtw89_port_reg *p = &rtw_port_base; 3904 3905 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 3906 BCN_ERLY_DEF); 3907 } 3908 3909 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 3910 struct rtw89_vif *rtwvif) 3911 { 3912 const struct rtw89_port_reg *p = &rtw_port_base; 3913 u16 val; 3914 3915 if (rtwdev->chip->chip_id != RTL8852C) 3916 return; 3917 3918 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 3919 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 3920 return; 3921 3922 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 3923 B_AX_TBTT_SHIFT_OFST_SIGN; 3924 3925 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift, 3926 B_AX_TBTT_SHIFT_OFST_MASK, val); 3927 } 3928 3929 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 3930 struct rtw89_vif *rtwvif, 3931 struct rtw89_vif *rtwvif_src, 3932 u16 offset_tu) 3933 { 3934 u32 val, reg; 3935 3936 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 3937 reg = rtw89_mac_reg_by_idx(R_AX_PORT0_TSF_SYNC + rtwvif->port * 4, 3938 rtwvif->mac_idx); 3939 3940 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 3941 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 3942 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 3943 } 3944 3945 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 3946 struct rtw89_vif *rtwvif, 3947 struct rtw89_vif *rtwvif_src, 3948 u8 offset, int *n_offset) 3949 { 3950 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src) 3951 return; 3952 3953 /* adjust offset randomly to avoid beacon conflict */ 3954 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 3955 rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src, 3956 (*n_offset) * offset); 3957 3958 (*n_offset)++; 3959 } 3960 3961 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 3962 { 3963 struct rtw89_vif *src = NULL, *tmp; 3964 u8 offset = 100, vif_aps = 0; 3965 int n_offset = 1; 3966 3967 rtw89_for_each_rtwvif(rtwdev, tmp) { 3968 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 3969 src = tmp; 3970 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 3971 vif_aps++; 3972 } 3973 3974 if (vif_aps == 0) 3975 return; 3976 3977 offset /= (vif_aps + 1); 3978 3979 rtw89_for_each_rtwvif(rtwdev, tmp) 3980 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset); 3981 } 3982 3983 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3984 { 3985 int ret; 3986 3987 ret = rtw89_mac_port_update(rtwdev, rtwvif); 3988 if (ret) 3989 return ret; 3990 3991 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 3992 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 3993 3994 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 3995 if (ret) 3996 return ret; 3997 3998 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 3999 if (ret) 4000 return ret; 4001 4002 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true); 4003 if (ret) 4004 return ret; 4005 4006 ret = rtw89_cam_init(rtwdev, rtwvif); 4007 if (ret) 4008 return ret; 4009 4010 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4011 if (ret) 4012 return ret; 4013 4014 ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif); 4015 if (ret) 4016 return ret; 4017 4018 return 0; 4019 } 4020 4021 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4022 { 4023 int ret; 4024 4025 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 4026 if (ret) 4027 return ret; 4028 4029 rtw89_cam_deinit(rtwdev, rtwvif); 4030 4031 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4032 if (ret) 4033 return ret; 4034 4035 return 0; 4036 } 4037 4038 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4039 { 4040 u8 port = rtwvif->port; 4041 4042 if (port >= RTW89_PORT_NUM) 4043 return -EINVAL; 4044 4045 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4046 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 4047 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 4048 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 4049 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 4050 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 4051 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); 4052 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif); 4053 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 4054 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 4055 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 4056 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 4057 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 4058 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 4059 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 4060 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 4061 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif); 4062 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 4063 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 4064 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true); 4065 rtw89_mac_port_tsf_resync_all(rtwdev); 4066 fsleep(BCN_ERLY_SET_DLY); 4067 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 4068 4069 return 0; 4070 } 4071 4072 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4073 u64 *tsf) 4074 { 4075 const struct rtw89_port_reg *p = &rtw_port_base; 4076 u32 tsf_low, tsf_high; 4077 int ret; 4078 4079 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL); 4080 if (ret) 4081 return ret; 4082 4083 tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l); 4084 tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h); 4085 *tsf = (u64)tsf_high << 32 | tsf_low; 4086 4087 return 0; 4088 } 4089 4090 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 4091 struct cfg80211_bss *bss, 4092 void *data) 4093 { 4094 const struct cfg80211_bss_ies *ies; 4095 const struct element *elem; 4096 bool *tolerated = data; 4097 4098 rcu_read_lock(); 4099 ies = rcu_dereference(bss->ies); 4100 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 4101 ies->len); 4102 4103 if (!elem || elem->datalen < 10 || 4104 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 4105 *tolerated = false; 4106 rcu_read_unlock(); 4107 } 4108 4109 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 4110 struct ieee80211_vif *vif) 4111 { 4112 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4113 struct ieee80211_hw *hw = rtwdev->hw; 4114 bool tolerated = true; 4115 u32 reg; 4116 4117 if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION) 4118 return; 4119 4120 if (!(vif->bss_conf.chandef.chan->flags & IEEE80211_CHAN_RADAR)) 4121 return; 4122 4123 cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chandef, 4124 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 4125 &tolerated); 4126 4127 reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx); 4128 if (tolerated) 4129 rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 4130 else 4131 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 4132 } 4133 4134 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4135 { 4136 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, false); 4137 } 4138 4139 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4140 { 4141 int ret; 4142 4143 rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 4144 RTW89_MAX_MAC_ID_NUM); 4145 if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 4146 return -ENOSPC; 4147 4148 ret = rtw89_mac_vif_init(rtwdev, rtwvif); 4149 if (ret) 4150 goto release_mac_id; 4151 4152 return 0; 4153 4154 release_mac_id: 4155 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4156 4157 return ret; 4158 } 4159 4160 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4161 { 4162 int ret; 4163 4164 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 4165 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4166 4167 return ret; 4168 } 4169 4170 static void 4171 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4172 { 4173 } 4174 4175 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 4176 { 4177 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 4178 4179 return band == scan_info->op_band && channel == scan_info->op_pri_ch; 4180 } 4181 4182 static void 4183 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4184 u32 len) 4185 { 4186 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 4187 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 4188 struct rtw89_chan new; 4189 u8 reason, status, tx_fail, band, actual_period; 4190 u32 last_chan = rtwdev->scan_info.last_chan_idx; 4191 u16 chan; 4192 int ret; 4193 4194 tx_fail = RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h->data); 4195 status = RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h->data); 4196 chan = RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h->data); 4197 reason = RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h->data); 4198 band = RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h->data); 4199 actual_period = RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h->data); 4200 4201 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 4202 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 4203 4204 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4205 "band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 4206 band, chan, reason, status, tx_fail, actual_period); 4207 4208 switch (reason) { 4209 case RTW89_SCAN_LEAVE_CH_NOTIFY: 4210 if (rtw89_is_op_chan(rtwdev, band, chan)) 4211 ieee80211_stop_queues(rtwdev->hw); 4212 return; 4213 case RTW89_SCAN_END_SCAN_NOTIFY: 4214 if (rtwvif && rtwvif->scan_req && 4215 last_chan < rtwvif->scan_req->n_channels) { 4216 ret = rtw89_hw_scan_offload(rtwdev, vif, true); 4217 if (ret) { 4218 rtw89_hw_scan_abort(rtwdev, vif); 4219 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 4220 } 4221 } else { 4222 rtw89_hw_scan_complete(rtwdev, vif, false); 4223 } 4224 break; 4225 case RTW89_SCAN_ENTER_CH_NOTIFY: 4226 rtw89_chan_create(&new, chan, chan, band, RTW89_CHANNEL_WIDTH_20); 4227 rtw89_assign_entity_chan(rtwdev, RTW89_SUB_ENTITY_0, &new); 4228 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4229 rtw89_store_op_chan(rtwdev, false); 4230 ieee80211_wake_queues(rtwdev->hw); 4231 } 4232 break; 4233 default: 4234 return; 4235 } 4236 } 4237 4238 static void 4239 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4240 { 4241 rtw89_debug(rtwdev, RTW89_DBG_FW, 4242 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 4243 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 4244 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 4245 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 4246 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 4247 } 4248 4249 static void 4250 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4251 { 4252 rtw89_debug(rtwdev, RTW89_DBG_FW, 4253 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 4254 RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h->data), 4255 RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h->data), 4256 RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h->data), 4257 RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h->data), 4258 RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h->data)); 4259 } 4260 4261 static void 4262 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4263 { 4264 rtw89_info(rtwdev, "%*s", RTW89_GET_C2H_LOG_LEN(len), 4265 RTW89_GET_C2H_LOG_SRT_PRT(c2h->data)); 4266 } 4267 4268 static void 4269 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4270 { 4271 } 4272 4273 static void 4274 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4275 u32 len) 4276 { 4277 } 4278 4279 static void 4280 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4281 u32 len) 4282 { 4283 } 4284 4285 static void 4286 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4287 { 4288 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 4289 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 4290 4291 switch (func) { 4292 case H2C_FUNC_ADD_MCC: 4293 case H2C_FUNC_START_MCC: 4294 case H2C_FUNC_STOP_MCC: 4295 case H2C_FUNC_DEL_MCC_GROUP: 4296 case H2C_FUNC_RESET_MCC_GROUP: 4297 case H2C_FUNC_MCC_REQ_TSF: 4298 case H2C_FUNC_MCC_MACID_BITMAP: 4299 case H2C_FUNC_MCC_SYNC: 4300 case H2C_FUNC_MCC_SET_DURATION: 4301 break; 4302 default: 4303 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4304 "invalid MCC C2H RCV ACK: func %d\n", func); 4305 return; 4306 } 4307 4308 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4309 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 4310 } 4311 4312 static void 4313 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4314 { 4315 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 4316 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 4317 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 4318 struct rtw89_completion_data data = {}; 4319 unsigned int cond; 4320 bool next = false; 4321 4322 switch (func) { 4323 case H2C_FUNC_MCC_REQ_TSF: 4324 next = true; 4325 break; 4326 case H2C_FUNC_MCC_MACID_BITMAP: 4327 case H2C_FUNC_MCC_SYNC: 4328 case H2C_FUNC_MCC_SET_DURATION: 4329 break; 4330 case H2C_FUNC_ADD_MCC: 4331 case H2C_FUNC_START_MCC: 4332 case H2C_FUNC_STOP_MCC: 4333 case H2C_FUNC_DEL_MCC_GROUP: 4334 case H2C_FUNC_RESET_MCC_GROUP: 4335 default: 4336 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4337 "invalid MCC C2H REQ ACK: func %d\n", func); 4338 return; 4339 } 4340 4341 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4342 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 4343 group, func, retcode); 4344 4345 if (!retcode && next) 4346 return; 4347 4348 data.err = !!retcode; 4349 cond = RTW89_MCC_WAIT_COND(group, func); 4350 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4351 } 4352 4353 static void 4354 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4355 { 4356 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 4357 struct rtw89_completion_data data = {}; 4358 struct rtw89_mac_mcc_tsf_rpt *rpt; 4359 unsigned int cond; 4360 4361 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 4362 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 4363 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 4364 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 4365 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 4366 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 4367 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 4368 4369 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4370 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 4371 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 4372 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 4373 4374 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 4375 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4376 } 4377 4378 static void 4379 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4380 { 4381 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 4382 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 4383 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 4384 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 4385 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 4386 struct rtw89_completion_data data = {}; 4387 unsigned int cond; 4388 bool rsp = true; 4389 bool err; 4390 u8 func; 4391 4392 switch (status) { 4393 case RTW89_MAC_MCC_ADD_ROLE_OK: 4394 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 4395 func = H2C_FUNC_ADD_MCC; 4396 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 4397 break; 4398 case RTW89_MAC_MCC_START_GROUP_OK: 4399 case RTW89_MAC_MCC_START_GROUP_FAIL: 4400 func = H2C_FUNC_START_MCC; 4401 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 4402 break; 4403 case RTW89_MAC_MCC_STOP_GROUP_OK: 4404 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 4405 func = H2C_FUNC_STOP_MCC; 4406 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 4407 break; 4408 case RTW89_MAC_MCC_DEL_GROUP_OK: 4409 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 4410 func = H2C_FUNC_DEL_MCC_GROUP; 4411 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 4412 break; 4413 case RTW89_MAC_MCC_RESET_GROUP_OK: 4414 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 4415 func = H2C_FUNC_RESET_MCC_GROUP; 4416 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 4417 break; 4418 case RTW89_MAC_MCC_SWITCH_CH_OK: 4419 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 4420 case RTW89_MAC_MCC_TXNULL0_OK: 4421 case RTW89_MAC_MCC_TXNULL0_FAIL: 4422 case RTW89_MAC_MCC_TXNULL1_OK: 4423 case RTW89_MAC_MCC_TXNULL1_FAIL: 4424 case RTW89_MAC_MCC_SWITCH_EARLY: 4425 case RTW89_MAC_MCC_TBTT: 4426 case RTW89_MAC_MCC_DURATION_START: 4427 case RTW89_MAC_MCC_DURATION_END: 4428 rsp = false; 4429 break; 4430 default: 4431 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4432 "invalid MCC C2H STS RPT: status %d\n", status); 4433 return; 4434 } 4435 4436 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4437 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 4438 group, macid, status, (u64)tsf_high << 32 | tsf_low); 4439 4440 if (!rsp) 4441 return; 4442 4443 data.err = err; 4444 cond = RTW89_MCC_WAIT_COND(group, func); 4445 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4446 } 4447 4448 static 4449 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 4450 struct sk_buff *c2h, u32 len) = { 4451 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 4452 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 4453 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 4454 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 4455 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 4456 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 4457 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 4458 }; 4459 4460 static 4461 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 4462 struct sk_buff *c2h, u32 len) = { 4463 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 4464 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 4465 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 4466 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 4467 }; 4468 4469 static 4470 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 4471 struct sk_buff *c2h, u32 len) = { 4472 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 4473 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 4474 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 4475 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 4476 }; 4477 4478 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func) 4479 { 4480 switch (class) { 4481 default: 4482 return false; 4483 case RTW89_MAC_C2H_CLASS_MCC: 4484 return true; 4485 } 4486 } 4487 4488 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4489 u32 len, u8 class, u8 func) 4490 { 4491 void (*handler)(struct rtw89_dev *rtwdev, 4492 struct sk_buff *c2h, u32 len) = NULL; 4493 4494 switch (class) { 4495 case RTW89_MAC_C2H_CLASS_INFO: 4496 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 4497 handler = rtw89_mac_c2h_info_handler[func]; 4498 break; 4499 case RTW89_MAC_C2H_CLASS_OFLD: 4500 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 4501 handler = rtw89_mac_c2h_ofld_handler[func]; 4502 break; 4503 case RTW89_MAC_C2H_CLASS_MCC: 4504 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 4505 handler = rtw89_mac_c2h_mcc_handler[func]; 4506 break; 4507 case RTW89_MAC_C2H_CLASS_FWDBG: 4508 return; 4509 default: 4510 rtw89_info(rtwdev, "c2h class %d not support\n", class); 4511 return; 4512 } 4513 if (!handler) { 4514 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 4515 func); 4516 return; 4517 } 4518 handler(rtwdev, skb, len); 4519 } 4520 4521 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 4522 enum rtw89_phy_idx phy_idx, 4523 u32 reg_base, u32 *cr) 4524 { 4525 const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; 4526 enum rtw89_qta_mode mode = dle_mem->mode; 4527 u32 addr = rtw89_mac_reg_by_idx(reg_base, phy_idx); 4528 4529 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) { 4530 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 4531 addr); 4532 goto error; 4533 } 4534 4535 if (addr >= CMAC1_START_ADDR && addr <= CMAC1_END_ADDR) 4536 if (mode == RTW89_QTA_SCC) { 4537 rtw89_err(rtwdev, 4538 "[TXPWR] addr=0x%x but hw not enable\n", 4539 addr); 4540 goto error; 4541 } 4542 4543 *cr = addr; 4544 return true; 4545 4546 error: 4547 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 4548 addr, phy_idx); 4549 4550 return false; 4551 } 4552 EXPORT_SYMBOL(rtw89_mac_get_txpwr_cr); 4553 4554 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 4555 { 4556 u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx); 4557 int ret; 4558 4559 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4560 if (ret) 4561 return ret; 4562 4563 if (!enable) { 4564 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 4565 return 0; 4566 } 4567 4568 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 4569 B_AX_APP_MAC_INFO_RPT | 4570 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 4571 B_AX_PPDU_STAT_RPT_CRC32); 4572 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 4573 RTW89_PRPT_DEST_HOST); 4574 4575 return 0; 4576 } 4577 EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status); 4578 4579 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 4580 { 4581 #define MAC_AX_TIME_TH_SH 5 4582 #define MAC_AX_LEN_TH_SH 4 4583 #define MAC_AX_TIME_TH_MAX 255 4584 #define MAC_AX_LEN_TH_MAX 255 4585 #define MAC_AX_TIME_TH_DEF 88 4586 #define MAC_AX_LEN_TH_DEF 4080 4587 struct ieee80211_hw *hw = rtwdev->hw; 4588 u32 rts_threshold = hw->wiphy->rts_threshold; 4589 u32 time_th, len_th; 4590 u32 reg; 4591 4592 if (rts_threshold == (u32)-1) { 4593 time_th = MAC_AX_TIME_TH_DEF; 4594 len_th = MAC_AX_LEN_TH_DEF; 4595 } else { 4596 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 4597 len_th = rts_threshold; 4598 } 4599 4600 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 4601 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 4602 4603 reg = rtw89_mac_reg_by_idx(R_AX_AGG_LEN_HT_0, mac_idx); 4604 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 4605 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 4606 } 4607 4608 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 4609 { 4610 bool empty; 4611 int ret; 4612 4613 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4614 return; 4615 4616 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 4617 10000, 200000, false, rtwdev); 4618 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 4619 rtw89_info(rtwdev, "timed out to flush queues\n"); 4620 } 4621 4622 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 4623 { 4624 u8 val; 4625 u16 val16; 4626 u32 val32; 4627 int ret; 4628 4629 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 4630 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 4631 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 4632 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 4633 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 4634 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 4635 4636 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 4637 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 4638 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 4639 4640 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 4641 if (ret) { 4642 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 4643 return ret; 4644 } 4645 val32 = val32 & B_AX_WL_RX_CTRL; 4646 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 4647 if (ret) { 4648 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 4649 return ret; 4650 } 4651 4652 switch (coex->pta_mode) { 4653 case RTW89_MAC_AX_COEX_RTK_MODE: 4654 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4655 val &= ~B_AX_BTMODE_MASK; 4656 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 4657 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4658 4659 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 4660 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 4661 4662 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 4663 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 4664 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 4665 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 4666 break; 4667 case RTW89_MAC_AX_COEX_CSR_MODE: 4668 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4669 val &= ~B_AX_BTMODE_MASK; 4670 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 4671 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4672 4673 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 4674 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 4675 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 4676 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 4677 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 4678 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 4679 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 4680 val16 |= B_AX_ENHANCED_BT; 4681 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 4682 4683 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 4684 break; 4685 default: 4686 return -EINVAL; 4687 } 4688 4689 switch (coex->direction) { 4690 case RTW89_MAC_AX_COEX_INNER: 4691 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4692 val = (val & ~BIT(2)) | BIT(1); 4693 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4694 break; 4695 case RTW89_MAC_AX_COEX_OUTPUT: 4696 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4697 val = val | BIT(1) | BIT(0); 4698 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4699 break; 4700 case RTW89_MAC_AX_COEX_INPUT: 4701 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4702 val = val & ~(BIT(2) | BIT(1)); 4703 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4704 break; 4705 default: 4706 return -EINVAL; 4707 } 4708 4709 return 0; 4710 } 4711 EXPORT_SYMBOL(rtw89_mac_coex_init); 4712 4713 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 4714 const struct rtw89_mac_ax_coex *coex) 4715 { 4716 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 4717 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 4718 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 4719 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 4720 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 4721 4722 switch (coex->pta_mode) { 4723 case RTW89_MAC_AX_COEX_RTK_MODE: 4724 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4725 MAC_AX_RTK_MODE); 4726 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 4727 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 4728 break; 4729 case RTW89_MAC_AX_COEX_CSR_MODE: 4730 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4731 MAC_AX_CSR_MODE); 4732 break; 4733 default: 4734 return -EINVAL; 4735 } 4736 4737 return 0; 4738 } 4739 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 4740 4741 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 4742 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4743 { 4744 u32 val = 0, ret; 4745 4746 if (gnt_cfg->band[0].gnt_bt) 4747 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 4748 4749 if (gnt_cfg->band[0].gnt_bt_sw_en) 4750 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 4751 4752 if (gnt_cfg->band[0].gnt_wl) 4753 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 4754 4755 if (gnt_cfg->band[0].gnt_wl_sw_en) 4756 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 4757 4758 if (gnt_cfg->band[1].gnt_bt) 4759 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 4760 4761 if (gnt_cfg->band[1].gnt_bt_sw_en) 4762 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 4763 4764 if (gnt_cfg->band[1].gnt_wl) 4765 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 4766 4767 if (gnt_cfg->band[1].gnt_wl_sw_en) 4768 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 4769 4770 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 4771 if (ret) { 4772 rtw89_err(rtwdev, "Write LTE fail!\n"); 4773 return ret; 4774 } 4775 4776 return 0; 4777 } 4778 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 4779 4780 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 4781 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4782 { 4783 u32 val = 0; 4784 4785 if (gnt_cfg->band[0].gnt_bt) 4786 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 4787 B_AX_GNT_BT_TX_VAL; 4788 else 4789 val |= B_AX_WL_ACT_VAL; 4790 4791 if (gnt_cfg->band[0].gnt_bt_sw_en) 4792 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 4793 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 4794 4795 if (gnt_cfg->band[0].gnt_wl) 4796 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 4797 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 4798 4799 if (gnt_cfg->band[0].gnt_wl_sw_en) 4800 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 4801 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 4802 4803 if (gnt_cfg->band[1].gnt_bt) 4804 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 4805 B_AX_GNT_BT_TX_VAL; 4806 else 4807 val |= B_AX_WL_ACT_VAL; 4808 4809 if (gnt_cfg->band[1].gnt_bt_sw_en) 4810 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 4811 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 4812 4813 if (gnt_cfg->band[1].gnt_wl) 4814 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 4815 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 4816 4817 if (gnt_cfg->band[1].gnt_wl_sw_en) 4818 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 4819 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 4820 4821 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 4822 4823 return 0; 4824 } 4825 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 4826 4827 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 4828 { 4829 u32 reg; 4830 u16 val; 4831 int ret; 4832 4833 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 4834 if (ret) 4835 return ret; 4836 4837 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, plt->band); 4838 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 4839 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 4840 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 4841 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 4842 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 4843 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 4844 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 4845 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 4846 B_AX_PLT_EN; 4847 rtw89_write16(rtwdev, reg, val); 4848 4849 return 0; 4850 } 4851 4852 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 4853 { 4854 u32 fw_sb; 4855 4856 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 4857 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 4858 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 4859 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4860 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 4861 else 4862 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 4863 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 4864 val = B_AX_TOGGLE | 4865 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 4866 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 4867 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 4868 fsleep(1000); /* avoid BT FW loss information */ 4869 } 4870 4871 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 4872 { 4873 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 4874 } 4875 4876 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 4877 { 4878 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 4879 4880 val = wl ? val | BIT(2) : val & ~BIT(2); 4881 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 4882 4883 return 0; 4884 } 4885 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 4886 4887 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 4888 { 4889 struct rtw89_btc *btc = &rtwdev->btc; 4890 struct rtw89_btc_dm *dm = &btc->dm; 4891 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 4892 int i; 4893 4894 if (wl) 4895 return 0; 4896 4897 for (i = 0; i < RTW89_PHY_MAX; i++) { 4898 g[i].gnt_bt_sw_en = 1; 4899 g[i].gnt_bt = 1; 4900 g[i].gnt_wl_sw_en = 1; 4901 g[i].gnt_wl = 0; 4902 } 4903 4904 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 4905 } 4906 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 4907 4908 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 4909 { 4910 const struct rtw89_chip_info *chip = rtwdev->chip; 4911 u8 val = 0; 4912 4913 if (chip->chip_id == RTL8852C) 4914 return false; 4915 else if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) 4916 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 4917 B_AX_LTE_MUX_CTRL_PATH >> 24); 4918 4919 return !!val; 4920 } 4921 4922 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 4923 { 4924 u32 reg; 4925 u16 cnt; 4926 4927 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, band); 4928 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 4929 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 4930 4931 return cnt; 4932 } 4933 4934 static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 4935 { 4936 u32 reg; 4937 u32 mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 4938 B_AX_BFMEE_HE_NDPA_EN; 4939 4940 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 4941 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 4942 if (en) { 4943 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 4944 rtw89_write32_set(rtwdev, reg, mask); 4945 } else { 4946 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 4947 rtw89_write32_clr(rtwdev, reg, mask); 4948 } 4949 } 4950 4951 static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx) 4952 { 4953 u32 reg; 4954 u32 val32; 4955 int ret; 4956 4957 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4958 if (ret) 4959 return ret; 4960 4961 /* AP mode set tx gid to 63 */ 4962 /* STA mode set tx gid to 0(default) */ 4963 reg = rtw89_mac_reg_by_idx(R_AX_BFMER_CTRL_0, mac_idx); 4964 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 4965 4966 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 4967 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 4968 4969 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 4970 val32 = FIELD_PREP(B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, BFRP_RX_STANDBY_TIMER); 4971 val32 |= FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 4972 rtw89_write32(rtwdev, reg, val32); 4973 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 4974 4975 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 4976 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 4977 B_AX_BFMEE_USE_NSTS | 4978 B_AX_BFMEE_CSI_GID_SEL | 4979 B_AX_BFMEE_CSI_FORCE_RETE_EN); 4980 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 4981 rtw89_write32(rtwdev, reg, 4982 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 4983 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 4984 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 4985 4986 reg = rtw89_mac_reg_by_idx(R_AX_CSIRPT_OPTION, mac_idx); 4987 rtw89_write32_set(rtwdev, reg, 4988 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 4989 4990 return 0; 4991 } 4992 4993 static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, 4994 struct ieee80211_vif *vif, 4995 struct ieee80211_sta *sta) 4996 { 4997 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4998 u8 mac_idx = rtwvif->mac_idx; 4999 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 5000 u8 port_sel = rtwvif->port; 5001 u8 sound_dim = 3, t; 5002 u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 5003 u32 reg; 5004 u16 val; 5005 int ret; 5006 5007 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5008 if (ret) 5009 return ret; 5010 5011 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5012 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 5013 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 5014 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 5015 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 5016 phy_cap[5]); 5017 sound_dim = min(sound_dim, t); 5018 } 5019 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5020 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 5021 ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 5022 stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 5023 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 5024 sta->deflink.vht_cap.cap); 5025 sound_dim = min(sound_dim, t); 5026 } 5027 nc = min(nc, sound_dim); 5028 nr = min(nr, sound_dim); 5029 5030 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5031 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5032 5033 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 5034 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 5035 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 5036 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 5037 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 5038 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 5039 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 5040 5041 if (port_sel == 0) 5042 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5043 else 5044 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 5045 5046 rtw89_write16(rtwdev, reg, val); 5047 5048 return 0; 5049 } 5050 5051 static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev, 5052 struct ieee80211_vif *vif, 5053 struct ieee80211_sta *sta) 5054 { 5055 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5056 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 5057 u32 reg; 5058 u8 mac_idx = rtwvif->mac_idx; 5059 int ret; 5060 5061 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5062 if (ret) 5063 return ret; 5064 5065 if (sta->deflink.he_cap.has_he) { 5066 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 5067 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 5068 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 5069 } 5070 if (sta->deflink.vht_cap.vht_supported) { 5071 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 5072 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 5073 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 5074 } 5075 if (sta->deflink.ht_cap.ht_supported) { 5076 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 5077 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 5078 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 5079 } 5080 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5081 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5082 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 5083 rtw89_write32(rtwdev, 5084 rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 5085 rrsc); 5086 5087 return 0; 5088 } 5089 5090 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5091 struct ieee80211_sta *sta) 5092 { 5093 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5094 5095 if (rtw89_sta_has_beamformer_cap(sta)) { 5096 rtw89_debug(rtwdev, RTW89_DBG_BF, 5097 "initialize bfee for new association\n"); 5098 rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx); 5099 rtw89_mac_set_csi_para_reg(rtwdev, vif, sta); 5100 rtw89_mac_csi_rrsc(rtwdev, vif, sta); 5101 } 5102 } 5103 5104 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5105 struct ieee80211_sta *sta) 5106 { 5107 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5108 5109 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 5110 } 5111 5112 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5113 struct ieee80211_bss_conf *conf) 5114 { 5115 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5116 u8 mac_idx = rtwvif->mac_idx; 5117 __le32 *p; 5118 5119 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 5120 5121 p = (__le32 *)conf->mu_group.membership; 5122 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx), 5123 le32_to_cpu(p[0])); 5124 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx), 5125 le32_to_cpu(p[1])); 5126 5127 p = (__le32 *)conf->mu_group.position; 5128 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx), 5129 le32_to_cpu(p[0])); 5130 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx), 5131 le32_to_cpu(p[1])); 5132 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx), 5133 le32_to_cpu(p[2])); 5134 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx), 5135 le32_to_cpu(p[3])); 5136 } 5137 5138 struct rtw89_mac_bf_monitor_iter_data { 5139 struct rtw89_dev *rtwdev; 5140 struct ieee80211_sta *down_sta; 5141 int count; 5142 }; 5143 5144 static 5145 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 5146 { 5147 struct rtw89_mac_bf_monitor_iter_data *iter_data = 5148 (struct rtw89_mac_bf_monitor_iter_data *)data; 5149 struct ieee80211_sta *down_sta = iter_data->down_sta; 5150 int *count = &iter_data->count; 5151 5152 if (down_sta == sta) 5153 return; 5154 5155 if (rtw89_sta_has_beamformer_cap(sta)) 5156 (*count)++; 5157 } 5158 5159 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 5160 struct ieee80211_sta *sta, bool disconnect) 5161 { 5162 struct rtw89_mac_bf_monitor_iter_data data; 5163 5164 data.rtwdev = rtwdev; 5165 data.down_sta = disconnect ? sta : NULL; 5166 data.count = 0; 5167 ieee80211_iterate_stations_atomic(rtwdev->hw, 5168 rtw89_mac_bf_monitor_calc_iter, 5169 &data); 5170 5171 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 5172 if (data.count) 5173 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5174 else 5175 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5176 } 5177 5178 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 5179 { 5180 struct rtw89_traffic_stats *stats = &rtwdev->stats; 5181 struct rtw89_vif *rtwvif; 5182 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 5183 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5184 5185 if (en == old) 5186 return; 5187 5188 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5189 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 5190 } 5191 5192 static int 5193 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5194 u32 tx_time) 5195 { 5196 #define MAC_AX_DFLT_TX_TIME 5280 5197 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5198 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 5199 u32 reg; 5200 int ret = 0; 5201 5202 if (rtwsta->cctl_tx_time) { 5203 rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 5204 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5205 } else { 5206 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5207 if (ret) { 5208 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 5209 return ret; 5210 } 5211 5212 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 5213 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 5214 max_tx_time >> 5); 5215 } 5216 5217 return ret; 5218 } 5219 5220 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5221 bool resume, u32 tx_time) 5222 { 5223 int ret = 0; 5224 5225 if (!resume) { 5226 rtwsta->cctl_tx_time = true; 5227 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5228 } else { 5229 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5230 rtwsta->cctl_tx_time = false; 5231 } 5232 5233 return ret; 5234 } 5235 5236 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5237 u32 *tx_time) 5238 { 5239 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5240 u32 reg; 5241 int ret = 0; 5242 5243 if (rtwsta->cctl_tx_time) { 5244 *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 5245 } else { 5246 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5247 if (ret) { 5248 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 5249 return ret; 5250 } 5251 5252 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 5253 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 5254 } 5255 5256 return ret; 5257 } 5258 5259 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 5260 struct rtw89_sta *rtwsta, 5261 bool resume, u8 tx_retry) 5262 { 5263 int ret = 0; 5264 5265 rtwsta->data_tx_cnt_lmt = tx_retry; 5266 5267 if (!resume) { 5268 rtwsta->cctl_tx_retry_limit = true; 5269 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5270 } else { 5271 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5272 rtwsta->cctl_tx_retry_limit = false; 5273 } 5274 5275 return ret; 5276 } 5277 5278 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 5279 struct rtw89_sta *rtwsta, u8 *tx_retry) 5280 { 5281 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5282 u32 reg; 5283 int ret = 0; 5284 5285 if (rtwsta->cctl_tx_retry_limit) { 5286 *tx_retry = rtwsta->data_tx_cnt_lmt; 5287 } else { 5288 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5289 if (ret) { 5290 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 5291 return ret; 5292 } 5293 5294 reg = rtw89_mac_reg_by_idx(R_AX_TXCNT, mac_idx); 5295 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 5296 } 5297 5298 return ret; 5299 } 5300 5301 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 5302 struct rtw89_vif *rtwvif, bool en) 5303 { 5304 u8 mac_idx = rtwvif->mac_idx; 5305 u16 set = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0; 5306 u32 reg; 5307 u32 ret; 5308 5309 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5310 if (ret) 5311 return ret; 5312 5313 reg = rtw89_mac_reg_by_idx(R_AX_MUEDCA_EN, mac_idx); 5314 if (en) 5315 rtw89_write16_set(rtwdev, reg, set); 5316 else 5317 rtw89_write16_clr(rtwdev, reg, set); 5318 5319 return 0; 5320 } 5321 5322 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 5323 { 5324 u32 val32; 5325 int ret; 5326 5327 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 5328 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 5329 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 5330 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 5331 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 5332 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 5333 5334 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 5335 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 5336 if (ret) { 5337 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 5338 offset, val, mask); 5339 return ret; 5340 } 5341 5342 return 0; 5343 } 5344 EXPORT_SYMBOL(rtw89_mac_write_xtal_si); 5345 5346 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 5347 { 5348 u32 val32; 5349 int ret; 5350 5351 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 5352 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 5353 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 5354 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 5355 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 5356 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 5357 5358 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 5359 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 5360 if (ret) { 5361 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 5362 return ret; 5363 } 5364 5365 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 5366 5367 return 0; 5368 } 5369 EXPORT_SYMBOL(rtw89_mac_read_xtal_si); 5370 5371 static 5372 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 5373 { 5374 static const enum rtw89_pkt_drop_sel sels[] = { 5375 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 5376 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 5377 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 5378 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 5379 }; 5380 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5381 struct rtw89_pkt_drop_params params = {0}; 5382 int i; 5383 5384 params.mac_band = RTW89_MAC_0; 5385 params.macid = rtwsta->mac_id; 5386 params.port = rtwvif->port; 5387 params.mbssid = 0; 5388 params.tf_trs = rtwvif->trigger; 5389 5390 for (i = 0; i < ARRAY_SIZE(sels); i++) { 5391 params.sel = sels[i]; 5392 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 5393 } 5394 } 5395 5396 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 5397 { 5398 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 5399 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5400 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 5401 struct rtw89_vif *target = data; 5402 5403 if (rtwvif != target) 5404 return; 5405 5406 rtw89_mac_pkt_drop_sta(rtwdev, rtwsta); 5407 } 5408 5409 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 5410 { 5411 ieee80211_iterate_stations_atomic(rtwdev->hw, 5412 rtw89_mac_pkt_drop_vif_iter, 5413 rtwvif); 5414 } 5415 5416 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 5417 enum rtw89_mac_idx band) 5418 { 5419 struct rtw89_pkt_drop_params params = {0}; 5420 bool empty; 5421 int i, ret = 0, try_cnt = 3; 5422 5423 params.mac_band = band; 5424 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 5425 5426 for (i = 0; i < try_cnt; i++) { 5427 ret = read_poll_timeout(mac_is_txq_empty, empty, empty, 50, 5428 50000, false, rtwdev); 5429 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 5430 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 5431 else 5432 return 0; 5433 } 5434 return ret; 5435 } 5436