1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "fw.h" 9 #include "mac.h" 10 #include "pci.h" 11 #include "ps.h" 12 #include "reg.h" 13 #include "util.h" 14 15 const u32 rtw89_mac_mem_base_addrs[RTW89_MAC_MEM_NUM] = { 16 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 17 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 18 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 19 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 20 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 21 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 22 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 23 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 24 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 25 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 26 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 28 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 29 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 30 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 31 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 32 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 33 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 34 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 35 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 36 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 37 }; 38 39 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 40 u32 val, enum rtw89_mac_mem_sel sel) 41 { 42 u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; 43 44 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); 45 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, val); 46 } 47 48 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 49 enum rtw89_mac_mem_sel sel) 50 { 51 u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; 52 53 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); 54 return rtw89_read32(rtwdev, R_AX_INDIR_ACCESS_ENTRY); 55 } 56 57 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, 58 enum rtw89_mac_hwmod_sel sel) 59 { 60 u32 val, r_val; 61 62 if (sel == RTW89_DMAC_SEL) { 63 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 64 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 65 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 66 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 67 val = B_AX_CMAC_EN; 68 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 69 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 70 val = B_AX_CMAC1_FEN; 71 } else { 72 return -EINVAL; 73 } 74 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 75 (val & r_val) != val) 76 return -EFAULT; 77 78 return 0; 79 } 80 81 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 82 { 83 u8 lte_ctrl; 84 int ret; 85 86 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 87 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 88 if (ret) 89 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 90 91 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 92 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 93 94 return ret; 95 } 96 97 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 98 { 99 u8 lte_ctrl; 100 int ret; 101 102 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 103 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 104 if (ret) 105 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 106 107 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 108 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 109 110 return ret; 111 } 112 113 static 114 int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 115 { 116 u32 ctrl_reg, data_reg, ctrl_data; 117 u32 val; 118 int ret; 119 120 switch (ctrl->type) { 121 case DLE_CTRL_TYPE_WDE: 122 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 123 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 124 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 125 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 126 B_AX_WDE_DFI_ACTIVE; 127 break; 128 case DLE_CTRL_TYPE_PLE: 129 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 130 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 131 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 132 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 133 B_AX_PLE_DFI_ACTIVE; 134 break; 135 default: 136 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 137 return -EINVAL; 138 } 139 140 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 141 142 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 143 1, 1000, false, rtwdev, ctrl_reg); 144 if (ret) { 145 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 146 ctrl_reg, ctrl_data); 147 return ret; 148 } 149 150 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 151 return 0; 152 } 153 154 static int dle_dfi_quota(struct rtw89_dev *rtwdev, 155 struct rtw89_mac_dle_dfi_quota *quota) 156 { 157 struct rtw89_mac_dle_dfi_ctrl ctrl; 158 int ret; 159 160 ctrl.type = quota->dle_type; 161 ctrl.target = DLE_DFI_TYPE_QUOTA; 162 ctrl.addr = quota->qtaid; 163 ret = dle_dfi_ctrl(rtwdev, &ctrl); 164 if (ret) { 165 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 166 return ret; 167 } 168 169 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 170 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 171 return 0; 172 } 173 174 static int dle_dfi_qempty(struct rtw89_dev *rtwdev, 175 struct rtw89_mac_dle_dfi_qempty *qempty) 176 { 177 struct rtw89_mac_dle_dfi_ctrl ctrl; 178 u32 ret; 179 180 ctrl.type = qempty->dle_type; 181 ctrl.target = DLE_DFI_TYPE_QEMPTY; 182 ctrl.addr = qempty->grpsel; 183 ret = dle_dfi_ctrl(rtwdev, &ctrl); 184 if (ret) { 185 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 186 return ret; 187 } 188 189 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 190 return 0; 191 } 192 193 static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev) 194 { 195 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 196 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 197 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 198 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 199 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 200 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 201 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 202 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 203 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 204 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 205 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 206 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 207 } 208 209 static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) 210 { 211 struct rtw89_mac_dle_dfi_qempty qempty; 212 struct rtw89_mac_dle_dfi_quota quota; 213 struct rtw89_mac_dle_dfi_ctrl ctrl; 214 u32 val, not_empty, i; 215 int ret; 216 217 qempty.dle_type = DLE_CTRL_TYPE_PLE; 218 qempty.grpsel = 0; 219 qempty.qempty = ~(u32)0; 220 ret = dle_dfi_qempty(rtwdev, &qempty); 221 if (ret) 222 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 223 else 224 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 225 226 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 227 if (!(not_empty & BIT(0))) 228 continue; 229 ctrl.type = DLE_CTRL_TYPE_PLE; 230 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 231 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 232 FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i); 233 ret = dle_dfi_ctrl(rtwdev, &ctrl); 234 if (ret) 235 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 236 else 237 rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i, 238 FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK, 239 ctrl.out_data)); 240 } 241 242 quota.dle_type = DLE_CTRL_TYPE_PLE; 243 quota.qtaid = 6; 244 ret = dle_dfi_quota(rtwdev, "a); 245 if (ret) 246 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 247 else 248 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 249 quota.rsv_pgnum, quota.use_pgnum); 250 251 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 252 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n", 253 FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val)); 254 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n", 255 FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val)); 256 257 dump_err_status_dispatcher(rtwdev); 258 } 259 260 static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 261 enum mac_ax_err_info err) 262 { 263 u32 dbg, event; 264 265 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 266 event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg); 267 268 switch (event) { 269 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 270 rtw89_info(rtwdev, "quota lost!\n"); 271 rtw89_mac_dump_qta_lost(rtwdev); 272 break; 273 default: 274 break; 275 } 276 } 277 278 static void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 279 { 280 const struct rtw89_chip_info *chip = rtwdev->chip; 281 u32 dmac_err; 282 int i, ret; 283 284 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 285 if (ret) { 286 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 287 return; 288 } 289 290 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 291 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 292 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 293 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 294 295 if (dmac_err) { 296 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 298 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 299 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 300 if (chip->chip_id == RTL8852C) { 301 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 302 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 303 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 304 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 305 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 306 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 307 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 308 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 309 } 310 } 311 312 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 313 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 314 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 315 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 316 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 317 if (chip->chip_id == RTL8852C) 318 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 319 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 320 else 321 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 322 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 323 } 324 325 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 326 if (chip->chip_id == RTL8852C) { 327 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 328 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 329 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 330 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 331 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 332 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 333 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 334 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 335 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 336 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 337 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 338 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 339 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 340 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 341 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 343 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 344 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 345 346 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 347 B_AX_DBG_SEL0, 0x8B); 348 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 349 B_AX_DBG_SEL1, 0x8B); 350 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 351 B_AX_SEL_0XC0_MASK, 1); 352 for (i = 0; i < 0x10; i++) { 353 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 354 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 355 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 356 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 357 } 358 } else { 359 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 360 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 361 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 362 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 363 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 364 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 365 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 366 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 367 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 368 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 369 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 370 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 371 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 372 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 373 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 374 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 375 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 376 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 377 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 378 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 379 } 380 } 381 382 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 383 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 384 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 385 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 386 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 387 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 388 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 389 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 390 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 391 } 392 393 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 394 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 395 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 396 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 397 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 398 } 399 400 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 401 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 402 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 403 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 404 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 405 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 406 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 407 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 408 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 409 } 410 411 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 412 if (chip->chip_id == RTL8852C) { 413 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 414 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 415 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 416 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 417 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 418 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 419 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 420 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 421 } else { 422 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 423 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 424 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 425 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 426 } 427 } 428 429 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 430 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 431 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 432 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 433 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 434 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 435 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 436 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 437 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 438 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 439 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 440 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 441 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 442 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 443 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 444 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 445 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 446 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 447 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 448 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 449 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 450 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 451 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 452 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 453 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 454 if (chip->chip_id == RTL8852C) { 455 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 456 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 457 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 458 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 459 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 460 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 461 } else { 462 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 463 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 464 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 465 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 466 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 467 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 468 } 469 } 470 471 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 472 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 473 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 474 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 475 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 476 } 477 478 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 479 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 480 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 481 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 482 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 483 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 484 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 485 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 486 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 487 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 488 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 489 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 490 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 491 } 492 493 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 494 if (chip->chip_id == RTL8852C) { 495 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 496 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 497 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 498 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 499 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 500 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 501 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 502 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 503 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 504 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 505 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 506 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 507 } else { 508 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 509 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 510 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 511 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 512 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 513 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 514 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 515 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 516 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 517 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 518 } 519 } 520 521 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 522 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 523 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 524 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 525 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 526 } 527 } 528 529 static void rtw89_mac_dump_cmac_err_status(struct rtw89_dev *rtwdev, 530 u8 band) 531 { 532 const struct rtw89_chip_info *chip = rtwdev->chip; 533 u32 offset = 0; 534 u32 cmac_err; 535 int ret; 536 537 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 538 if (ret) { 539 if (band) 540 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 541 else 542 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 543 return; 544 } 545 546 if (band) 547 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 548 549 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 550 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 551 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 552 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 553 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 554 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 555 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 556 557 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 558 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 559 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 560 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 561 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 562 } 563 564 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 565 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 566 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 567 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 568 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 569 } 570 571 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 572 if (chip->chip_id == RTL8852C) { 573 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 574 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 575 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 576 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 577 } else { 578 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 579 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 580 } 581 } 582 583 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 584 if (chip->chip_id == RTL8852C) { 585 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 586 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 587 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 588 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 589 } else { 590 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 591 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 592 } 593 } 594 595 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 596 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 597 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 598 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 599 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 600 } 601 602 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 603 if (chip->chip_id == RTL8852C) { 604 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 605 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 606 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 607 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 608 } else { 609 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 610 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 611 } 612 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 613 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 614 } 615 616 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 617 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 618 } 619 620 static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev, 621 enum mac_ax_err_info err) 622 { 623 if (err != MAC_AX_ERR_L1_ERR_DMAC && 624 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 625 err != MAC_AX_ERR_L0_ERR_CMAC0 && 626 err != MAC_AX_ERR_L0_ERR_CMAC1 && 627 err != MAC_AX_ERR_RXI300) 628 return; 629 630 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 631 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 632 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 633 634 rtw89_mac_dump_dmac_err_status(rtwdev); 635 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_0); 636 if (rtwdev->dbcc_en) 637 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_1); 638 639 rtwdev->hci.ops->dump_err_status(rtwdev); 640 641 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 642 rtw89_mac_dump_l0_to_l1(rtwdev, err); 643 644 rtw89_info(rtwdev, "<---\n"); 645 } 646 647 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 648 { 649 u32 err, err_scnr; 650 int ret; 651 652 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 653 false, rtwdev, R_AX_HALT_C2H_CTRL); 654 if (ret) { 655 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 656 return ret; 657 } 658 659 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 660 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 661 662 err_scnr = RTW89_ERROR_SCENARIO(err); 663 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 664 err = MAC_AX_ERR_CPU_EXCEPTION; 665 else if (err_scnr == RTW89_WCPU_ASSERTION) 666 err = MAC_AX_ERR_ASSERTION; 667 else if (err_scnr == RTW89_RXI300_ERROR) 668 err = MAC_AX_ERR_RXI300; 669 670 rtw89_fw_st_dbg_dump(rtwdev); 671 rtw89_mac_dump_err_status(rtwdev, err); 672 673 return err; 674 } 675 EXPORT_SYMBOL(rtw89_mac_get_err_status); 676 677 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 678 { 679 u32 halt; 680 int ret = 0; 681 682 if (err > MAC_AX_SET_ERR_MAX) { 683 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 684 return -EINVAL; 685 } 686 687 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 688 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 689 if (ret) { 690 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 691 return -EFAULT; 692 } 693 694 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 695 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 696 697 return 0; 698 } 699 EXPORT_SYMBOL(rtw89_mac_set_err_status); 700 701 static int hfc_reset_param(struct rtw89_dev *rtwdev) 702 { 703 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 704 struct rtw89_hfc_param_ini param_ini = {NULL}; 705 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 706 707 switch (rtwdev->hci.type) { 708 case RTW89_HCI_TYPE_PCIE: 709 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 710 param->en = 0; 711 break; 712 default: 713 return -EINVAL; 714 } 715 716 if (param_ini.pub_cfg) 717 param->pub_cfg = *param_ini.pub_cfg; 718 719 if (param_ini.prec_cfg) { 720 param->prec_cfg = *param_ini.prec_cfg; 721 rtwdev->hal.sw_amsdu_max_size = 722 param->prec_cfg.wp_ch07_prec * HFC_PAGE_UNIT; 723 } 724 725 if (param_ini.ch_cfg) 726 param->ch_cfg = param_ini.ch_cfg; 727 728 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 729 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 730 param->mode = param_ini.mode; 731 732 return 0; 733 } 734 735 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 736 { 737 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 738 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 739 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 740 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 741 742 if (ch >= RTW89_DMA_CH_NUM) 743 return -EINVAL; 744 745 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 746 ch_cfg[ch].max > pub_cfg->pub_max) 747 return -EINVAL; 748 if (ch_cfg[ch].grp >= grp_num) 749 return -EINVAL; 750 751 return 0; 752 } 753 754 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 755 { 756 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 757 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 758 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 759 760 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 761 if (rtwdev->chip->chip_id == RTL8852A) 762 return 0; 763 else 764 return -EFAULT; 765 } 766 767 return 0; 768 } 769 770 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 771 { 772 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 773 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 774 775 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 776 return -EFAULT; 777 778 return 0; 779 } 780 781 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 782 { 783 const struct rtw89_chip_info *chip = rtwdev->chip; 784 const struct rtw89_page_regs *regs = chip->page_regs; 785 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 786 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 787 int ret = 0; 788 u32 val = 0; 789 790 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 791 if (ret) 792 return ret; 793 794 ret = hfc_ch_cfg_chk(rtwdev, ch); 795 if (ret) 796 return ret; 797 798 if (ch > RTW89_DMA_B1HI) 799 return -EINVAL; 800 801 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 802 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 803 (cfg[ch].grp ? B_AX_GRP : 0); 804 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 805 806 return 0; 807 } 808 809 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 810 { 811 const struct rtw89_chip_info *chip = rtwdev->chip; 812 const struct rtw89_page_regs *regs = chip->page_regs; 813 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 814 struct rtw89_hfc_ch_info *info = param->ch_info; 815 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 816 u32 val; 817 u32 ret; 818 819 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 820 if (ret) 821 return ret; 822 823 if (ch > RTW89_DMA_H2C) 824 return -EINVAL; 825 826 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 827 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 828 if (ch < RTW89_DMA_H2C) 829 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 830 else 831 info[ch].used = cfg[ch].min - info[ch].aval; 832 833 return 0; 834 } 835 836 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 837 { 838 const struct rtw89_chip_info *chip = rtwdev->chip; 839 const struct rtw89_page_regs *regs = chip->page_regs; 840 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 841 u32 val; 842 int ret; 843 844 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 845 if (ret) 846 return ret; 847 848 ret = hfc_pub_cfg_chk(rtwdev); 849 if (ret) 850 return ret; 851 852 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 853 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 854 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 855 856 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 857 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 858 859 return 0; 860 } 861 862 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 863 { 864 const struct rtw89_chip_info *chip = rtwdev->chip; 865 const struct rtw89_page_regs *regs = chip->page_regs; 866 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 867 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 868 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 869 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 870 u32 val; 871 int ret; 872 873 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 874 if (ret) 875 return ret; 876 877 val = rtw89_read32(rtwdev, regs->pub_page_info1); 878 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 879 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 880 val = rtw89_read32(rtwdev, regs->pub_page_info3); 881 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 882 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 883 info->pub_aval = 884 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 885 B_AX_PUB_AVAL_PG_MASK); 886 info->wp_aval = 887 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 888 B_AX_WP_AVAL_PG_MASK); 889 890 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 891 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 892 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 893 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 894 prec_cfg->ch011_full_cond = 895 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 896 prec_cfg->h2c_full_cond = 897 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 898 prec_cfg->wp_ch07_full_cond = 899 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 900 prec_cfg->wp_ch811_full_cond = 901 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 902 903 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 904 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 905 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 906 907 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 908 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 909 910 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 911 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 912 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 913 914 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 915 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 916 917 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 918 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 919 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 920 921 ret = hfc_pub_info_chk(rtwdev); 922 if (param->en && ret) 923 return ret; 924 925 return 0; 926 } 927 928 static void hfc_h2c_cfg(struct rtw89_dev *rtwdev) 929 { 930 const struct rtw89_chip_info *chip = rtwdev->chip; 931 const struct rtw89_page_regs *regs = chip->page_regs; 932 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 933 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 934 u32 val; 935 936 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 937 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 938 939 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 940 B_AX_HCI_FC_CH12_FULL_COND_MASK, 941 prec_cfg->h2c_full_cond); 942 } 943 944 static void hfc_mix_cfg(struct rtw89_dev *rtwdev) 945 { 946 const struct rtw89_chip_info *chip = rtwdev->chip; 947 const struct rtw89_page_regs *regs = chip->page_regs; 948 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 949 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 950 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 951 u32 val; 952 953 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 954 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 955 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 956 957 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 958 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 959 960 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 961 B_AX_PREC_PAGE_WP_CH07_MASK) | 962 u32_encode_bits(prec_cfg->wp_ch811_prec, 963 B_AX_PREC_PAGE_WP_CH811_MASK); 964 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 965 966 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 967 param->mode, B_AX_HCI_FC_MODE_MASK); 968 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 969 B_AX_HCI_FC_WD_FULL_COND_MASK); 970 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 971 B_AX_HCI_FC_CH12_FULL_COND_MASK); 972 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 973 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 974 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 975 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 976 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 977 } 978 979 static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 980 { 981 const struct rtw89_chip_info *chip = rtwdev->chip; 982 const struct rtw89_page_regs *regs = chip->page_regs; 983 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 984 u32 val; 985 986 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 987 param->en = en; 988 param->h2c_en = h2c_en; 989 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 990 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 991 (val & ~B_AX_HCI_FC_CH12_EN); 992 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 993 } 994 995 static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 996 { 997 const struct rtw89_chip_info *chip = rtwdev->chip; 998 u32 dma_ch_mask = chip->dma_ch_mask; 999 u8 ch; 1000 u32 ret = 0; 1001 1002 if (reset) 1003 ret = hfc_reset_param(rtwdev); 1004 if (ret) 1005 return ret; 1006 1007 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1008 if (ret) 1009 return ret; 1010 1011 hfc_func_en(rtwdev, false, false); 1012 1013 if (!en && h2c_en) { 1014 hfc_h2c_cfg(rtwdev); 1015 hfc_func_en(rtwdev, en, h2c_en); 1016 return ret; 1017 } 1018 1019 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1020 if (dma_ch_mask & BIT(ch)) 1021 continue; 1022 ret = hfc_ch_ctrl(rtwdev, ch); 1023 if (ret) 1024 return ret; 1025 } 1026 1027 ret = hfc_pub_ctrl(rtwdev); 1028 if (ret) 1029 return ret; 1030 1031 hfc_mix_cfg(rtwdev); 1032 if (en || h2c_en) { 1033 hfc_func_en(rtwdev, en, h2c_en); 1034 udelay(10); 1035 } 1036 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1037 if (dma_ch_mask & BIT(ch)) 1038 continue; 1039 ret = hfc_upd_ch_info(rtwdev, ch); 1040 if (ret) 1041 return ret; 1042 } 1043 ret = hfc_upd_mix_info(rtwdev); 1044 1045 return ret; 1046 } 1047 1048 #define PWR_POLL_CNT 2000 1049 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1050 const struct rtw89_pwr_cfg *cfg) 1051 { 1052 u8 val = 0; 1053 int ret; 1054 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1055 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1056 1057 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1058 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1059 1060 if (!ret) 1061 return 0; 1062 1063 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1064 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1065 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1066 1067 return -EBUSY; 1068 } 1069 1070 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1071 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1072 { 1073 const struct rtw89_pwr_cfg *cur_cfg; 1074 u32 addr; 1075 u8 val; 1076 1077 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1078 if (!(cur_cfg->intf_msk & intf_msk) || 1079 !(cur_cfg->cv_msk & cv_msk)) 1080 continue; 1081 1082 switch (cur_cfg->cmd) { 1083 case PWR_CMD_WRITE: 1084 addr = cur_cfg->addr; 1085 1086 if (cur_cfg->base == PWR_BASE_SDIO) 1087 addr |= SDIO_LOCAL_BASE_ADDR; 1088 1089 val = rtw89_read8(rtwdev, addr); 1090 val &= ~(cur_cfg->msk); 1091 val |= (cur_cfg->val & cur_cfg->msk); 1092 1093 rtw89_write8(rtwdev, addr, val); 1094 break; 1095 case PWR_CMD_POLL: 1096 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1097 return -EBUSY; 1098 break; 1099 case PWR_CMD_DELAY: 1100 if (cur_cfg->val == PWR_DELAY_US) 1101 udelay(cur_cfg->addr); 1102 else 1103 fsleep(cur_cfg->addr * 1000); 1104 break; 1105 default: 1106 return -EINVAL; 1107 } 1108 } 1109 1110 return 0; 1111 } 1112 1113 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1114 const struct rtw89_pwr_cfg * const *cfg_seq) 1115 { 1116 int ret; 1117 1118 for (; *cfg_seq; cfg_seq++) { 1119 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1120 PWR_INTF_MSK_PCIE, *cfg_seq); 1121 if (ret) 1122 return -EBUSY; 1123 } 1124 1125 return 0; 1126 } 1127 1128 static enum rtw89_rpwm_req_pwr_state 1129 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1130 { 1131 enum rtw89_rpwm_req_pwr_state state; 1132 1133 switch (rtwdev->ps_mode) { 1134 case RTW89_PS_MODE_RFOFF: 1135 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1136 break; 1137 case RTW89_PS_MODE_CLK_GATED: 1138 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1139 break; 1140 case RTW89_PS_MODE_PWR_GATED: 1141 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1142 break; 1143 default: 1144 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1145 break; 1146 } 1147 return state; 1148 } 1149 1150 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1151 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1152 bool notify_wake) 1153 { 1154 u16 request; 1155 1156 spin_lock_bh(&rtwdev->rpwm_lock); 1157 1158 request = rtw89_read16(rtwdev, R_AX_RPWM); 1159 request ^= request | PS_RPWM_TOGGLE; 1160 request |= req_pwr_state; 1161 1162 if (notify_wake) { 1163 request |= PS_RPWM_NOTIFY_WAKE; 1164 } else { 1165 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1166 RPWM_SEQ_NUM_MAX; 1167 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1168 rtwdev->mac.rpwm_seq_num); 1169 1170 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1171 request |= PS_RPWM_ACK; 1172 } 1173 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1174 1175 spin_unlock_bh(&rtwdev->rpwm_lock); 1176 } 1177 1178 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1179 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1180 { 1181 bool request_deep_mode; 1182 bool in_deep_mode; 1183 u8 rpwm_req_num; 1184 u8 cpwm_rsp_seq; 1185 u8 cpwm_seq; 1186 u8 cpwm_status; 1187 1188 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1189 request_deep_mode = true; 1190 else 1191 request_deep_mode = false; 1192 1193 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1194 in_deep_mode = true; 1195 else 1196 in_deep_mode = false; 1197 1198 if (request_deep_mode != in_deep_mode) 1199 return -EPERM; 1200 1201 if (request_deep_mode) 1202 return 0; 1203 1204 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1205 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1206 PS_CPWM_RSP_SEQ_NUM); 1207 1208 if (rpwm_req_num != cpwm_rsp_seq) 1209 return -EPERM; 1210 1211 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1212 CPWM_SEQ_NUM_MAX; 1213 1214 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1215 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1216 return -EPERM; 1217 1218 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1219 if (cpwm_status != req_pwr_state) 1220 return -EPERM; 1221 1222 return 0; 1223 } 1224 1225 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1226 { 1227 enum rtw89_rpwm_req_pwr_state state; 1228 unsigned long delay = enter ? 10 : 150; 1229 int ret; 1230 int i; 1231 1232 if (enter) 1233 state = rtw89_mac_get_req_pwr_state(rtwdev); 1234 else 1235 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1236 1237 for (i = 0; i < RPWM_TRY_CNT; i++) { 1238 rtw89_mac_send_rpwm(rtwdev, state, false); 1239 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1240 !ret, delay, 15000, false, 1241 rtwdev, state); 1242 if (!ret) 1243 break; 1244 1245 if (i == RPWM_TRY_CNT - 1) 1246 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1247 enter ? "entering" : "leaving"); 1248 else 1249 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1250 "%d time firmware failed to ack for %s ps mode\n", 1251 i + 1, enter ? "entering" : "leaving"); 1252 } 1253 } 1254 1255 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1256 { 1257 enum rtw89_rpwm_req_pwr_state state; 1258 1259 state = rtw89_mac_get_req_pwr_state(rtwdev); 1260 rtw89_mac_send_rpwm(rtwdev, state, true); 1261 } 1262 1263 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1264 { 1265 #define PWR_ACT 1 1266 const struct rtw89_chip_info *chip = rtwdev->chip; 1267 const struct rtw89_pwr_cfg * const *cfg_seq; 1268 int (*cfg_func)(struct rtw89_dev *rtwdev); 1269 int ret; 1270 u8 val; 1271 1272 if (on) { 1273 cfg_seq = chip->pwr_on_seq; 1274 cfg_func = chip->ops->pwr_on_func; 1275 } else { 1276 cfg_seq = chip->pwr_off_seq; 1277 cfg_func = chip->ops->pwr_off_func; 1278 } 1279 1280 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1281 __rtw89_leave_ps_mode(rtwdev); 1282 1283 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1284 if (on && val == PWR_ACT) { 1285 rtw89_err(rtwdev, "MAC has already powered on\n"); 1286 return -EBUSY; 1287 } 1288 1289 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1290 if (ret) 1291 return ret; 1292 1293 if (on) { 1294 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1295 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1296 } else { 1297 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1298 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1299 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1300 rtw89_set_entity_state(rtwdev, false); 1301 } 1302 1303 return 0; 1304 #undef PWR_ACT 1305 } 1306 1307 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1308 { 1309 rtw89_mac_power_switch(rtwdev, false); 1310 } 1311 1312 static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1313 { 1314 u32 func_en = 0; 1315 u32 ck_en = 0; 1316 u32 c1pc_en = 0; 1317 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1318 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1319 1320 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1321 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1322 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1323 B_AX_CMAC_CRPRT; 1324 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1325 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1326 B_AX_RMAC_CKEN; 1327 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1328 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1329 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1330 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1331 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1332 1333 if (en) { 1334 if (mac_idx == RTW89_MAC_1) { 1335 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1336 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1337 B_AX_R_SYM_ISO_CMAC12PP); 1338 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1339 B_AX_CMAC1_FEN); 1340 } 1341 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1342 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1343 } else { 1344 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1345 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1346 if (mac_idx == RTW89_MAC_1) { 1347 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1348 B_AX_CMAC1_FEN); 1349 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1350 B_AX_R_SYM_ISO_CMAC12PP); 1351 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1352 } 1353 } 1354 1355 return 0; 1356 } 1357 1358 static int dmac_func_en(struct rtw89_dev *rtwdev) 1359 { 1360 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1361 u32 val32; 1362 1363 if (chip_id == RTL8852C) 1364 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1365 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1366 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1367 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1368 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1369 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1370 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1371 else 1372 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1373 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1374 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1375 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1376 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1377 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1378 B_AX_DMAC_CRPRT); 1379 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1380 1381 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1382 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1383 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1384 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1385 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1386 1387 return 0; 1388 } 1389 1390 static int chip_func_en(struct rtw89_dev *rtwdev) 1391 { 1392 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1393 1394 if (chip_id == RTL8852A || chip_id == RTL8852B) 1395 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1396 B_AX_OCP_L1_MASK); 1397 1398 return 0; 1399 } 1400 1401 static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev) 1402 { 1403 int ret; 1404 1405 ret = dmac_func_en(rtwdev); 1406 if (ret) 1407 return ret; 1408 1409 ret = cmac_func_en(rtwdev, 0, true); 1410 if (ret) 1411 return ret; 1412 1413 ret = chip_func_en(rtwdev); 1414 if (ret) 1415 return ret; 1416 1417 return ret; 1418 } 1419 1420 const struct rtw89_mac_size_set rtw89_mac_size = { 1421 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1422 /* PCIE 64 */ 1423 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1424 /* DLFW */ 1425 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1426 /* PCIE 64 */ 1427 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1428 /* 8852B PCIE SCC */ 1429 .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1430 /* DLFW */ 1431 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1432 /* 8852C DLFW */ 1433 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1434 /* 8852C PCIE SCC */ 1435 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1436 /* PCIE */ 1437 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1438 /* DLFW */ 1439 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1440 /* PCIE 64 */ 1441 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1442 /* DLFW */ 1443 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1444 /* 8852C DLFW */ 1445 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1446 /* 8852C PCIE SCC */ 1447 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1448 /* PCIE 64 */ 1449 .wde_qt0 = {3792, 196, 0, 107,}, 1450 /* DLFW */ 1451 .wde_qt4 = {0, 0, 0, 0,}, 1452 /* PCIE 64 */ 1453 .wde_qt6 = {448, 48, 0, 16,}, 1454 /* 8852B PCIE SCC */ 1455 .wde_qt7 = {446, 48, 0, 16,}, 1456 /* 8852C DLFW */ 1457 .wde_qt17 = {0, 0, 0, 0,}, 1458 /* 8852C PCIE SCC */ 1459 .wde_qt18 = {3228, 60, 0, 40,}, 1460 /* PCIE SCC */ 1461 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1462 /* PCIE SCC */ 1463 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1464 /* DLFW */ 1465 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1466 /* PCIE 64 */ 1467 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1468 /* DLFW 52C */ 1469 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1470 /* DLFW 52C */ 1471 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1472 /* 8852C PCIE SCC */ 1473 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1474 /* 8852C PCIE SCC */ 1475 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1476 /* PCIE 64 */ 1477 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1478 /* 8852A PCIE WOW */ 1479 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1480 /* 8852B PCIE WOW */ 1481 .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1482 }; 1483 EXPORT_SYMBOL(rtw89_mac_size); 1484 1485 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1486 enum rtw89_qta_mode mode) 1487 { 1488 struct rtw89_mac_info *mac = &rtwdev->mac; 1489 const struct rtw89_dle_mem *cfg; 1490 1491 cfg = &rtwdev->chip->dle_mem[mode]; 1492 if (!cfg) 1493 return NULL; 1494 1495 if (cfg->mode != mode) { 1496 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1497 return NULL; 1498 } 1499 1500 mac->dle_info.wde_pg_size = cfg->wde_size->pge_size; 1501 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1502 mac->dle_info.qta_mode = mode; 1503 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1504 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1505 1506 return cfg; 1507 } 1508 1509 static bool mac_is_txq_empty(struct rtw89_dev *rtwdev) 1510 { 1511 struct rtw89_mac_dle_dfi_qempty qempty; 1512 u32 qnum, qtmp, val32, msk32; 1513 int i, j, ret; 1514 1515 qnum = rtwdev->chip->wde_qempty_acq_num; 1516 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1517 1518 for (i = 0; i < qnum; i++) { 1519 qempty.grpsel = i; 1520 ret = dle_dfi_qempty(rtwdev, &qempty); 1521 if (ret) { 1522 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1523 return false; 1524 } 1525 qtmp = qempty.qempty; 1526 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1527 val32 = FIELD_GET(QEMP_ACQ_GRP_QSEL_MASK, qtmp); 1528 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1529 return false; 1530 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1531 } 1532 } 1533 1534 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_sel; 1535 ret = dle_dfi_qempty(rtwdev, &qempty); 1536 if (ret) { 1537 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1538 return false; 1539 } 1540 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1541 if ((qempty.qempty & msk32) != msk32) 1542 return false; 1543 1544 if (rtwdev->dbcc_en) { 1545 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1546 if ((qempty.qempty & msk32) != msk32) 1547 return false; 1548 } 1549 1550 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1551 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1552 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1553 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1554 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1555 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1556 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1557 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1558 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1559 1560 return (val32 & msk32) == msk32; 1561 } 1562 1563 static inline u32 dle_used_size(const struct rtw89_dle_size *wde, 1564 const struct rtw89_dle_size *ple) 1565 { 1566 return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1567 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1568 } 1569 1570 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 1571 enum rtw89_qta_mode mode) 1572 { 1573 u32 size = rtwdev->chip->fifo_size; 1574 1575 if (mode == RTW89_QTA_SCC) 1576 size -= rtwdev->chip->dle_scc_rsvd_size; 1577 1578 return size; 1579 } 1580 1581 static void dle_func_en(struct rtw89_dev *rtwdev, bool enable) 1582 { 1583 if (enable) 1584 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1585 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1586 else 1587 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1588 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1589 } 1590 1591 static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable) 1592 { 1593 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 1594 1595 if (enable) { 1596 if (rtwdev->chip->chip_id == RTL8851B) 1597 val |= B_AX_AXIDMA_CLK_EN; 1598 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 1599 } else { 1600 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 1601 } 1602 } 1603 1604 static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1605 { 1606 const struct rtw89_dle_size *size_cfg; 1607 u32 val; 1608 u8 bound = 0; 1609 1610 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1611 size_cfg = cfg->wde_size; 1612 1613 switch (size_cfg->pge_size) { 1614 default: 1615 case RTW89_WDE_PG_64: 1616 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1617 B_AX_WDE_PAGE_SEL_MASK); 1618 break; 1619 case RTW89_WDE_PG_128: 1620 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1621 B_AX_WDE_PAGE_SEL_MASK); 1622 break; 1623 case RTW89_WDE_PG_256: 1624 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1625 return -EINVAL; 1626 } 1627 1628 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1629 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1630 B_AX_WDE_FREE_PAGE_NUM_MASK); 1631 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1632 1633 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1634 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1635 * size_cfg->pge_size / DLE_BOUND_UNIT; 1636 size_cfg = cfg->ple_size; 1637 1638 switch (size_cfg->pge_size) { 1639 default: 1640 case RTW89_PLE_PG_64: 1641 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1642 return -EINVAL; 1643 case RTW89_PLE_PG_128: 1644 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1645 B_AX_PLE_PAGE_SEL_MASK); 1646 break; 1647 case RTW89_PLE_PG_256: 1648 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1649 B_AX_PLE_PAGE_SEL_MASK); 1650 break; 1651 } 1652 1653 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1654 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1655 B_AX_PLE_FREE_PAGE_NUM_MASK); 1656 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1657 1658 return 0; 1659 } 1660 1661 #define INVALID_QT_WCPU U16_MAX 1662 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1663 do { \ 1664 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1665 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1666 rtw89_write32(rtwdev, \ 1667 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1668 val); \ 1669 } while (0) 1670 #define SET_QUOTA(_x, _module, _idx) \ 1671 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1672 1673 static void wde_quota_cfg(struct rtw89_dev *rtwdev, 1674 const struct rtw89_wde_quota *min_cfg, 1675 const struct rtw89_wde_quota *max_cfg, 1676 u16 ext_wde_min_qt_wcpu) 1677 { 1678 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1679 ext_wde_min_qt_wcpu : min_cfg->wcpu; 1680 u32 val; 1681 1682 SET_QUOTA(hif, WDE, 0); 1683 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1684 SET_QUOTA(pkt_in, WDE, 3); 1685 SET_QUOTA(cpu_io, WDE, 4); 1686 } 1687 1688 static void ple_quota_cfg(struct rtw89_dev *rtwdev, 1689 const struct rtw89_ple_quota *min_cfg, 1690 const struct rtw89_ple_quota *max_cfg) 1691 { 1692 u32 val; 1693 1694 SET_QUOTA(cma0_tx, PLE, 0); 1695 SET_QUOTA(cma1_tx, PLE, 1); 1696 SET_QUOTA(c2h, PLE, 2); 1697 SET_QUOTA(h2c, PLE, 3); 1698 SET_QUOTA(wcpu, PLE, 4); 1699 SET_QUOTA(mpdu_proc, PLE, 5); 1700 SET_QUOTA(cma0_dma, PLE, 6); 1701 SET_QUOTA(cma1_dma, PLE, 7); 1702 SET_QUOTA(bb_rpt, PLE, 8); 1703 SET_QUOTA(wd_rel, PLE, 9); 1704 SET_QUOTA(cpu_io, PLE, 10); 1705 if (rtwdev->chip->chip_id == RTL8852C) 1706 SET_QUOTA(tx_rpt, PLE, 11); 1707 } 1708 1709 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 1710 { 1711 const struct rtw89_ple_quota *min_cfg, *max_cfg; 1712 const struct rtw89_dle_mem *cfg; 1713 u32 val; 1714 1715 if (rtwdev->chip->chip_id == RTL8852C) 1716 return 0; 1717 1718 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 1719 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 1720 return -EINVAL; 1721 } 1722 1723 if (wow) 1724 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 1725 else 1726 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 1727 if (!cfg) { 1728 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1729 return -EINVAL; 1730 } 1731 1732 min_cfg = cfg->ple_min_qt; 1733 max_cfg = cfg->ple_max_qt; 1734 SET_QUOTA(cma0_dma, PLE, 6); 1735 SET_QUOTA(cma1_dma, PLE, 7); 1736 1737 return 0; 1738 } 1739 #undef SET_QUOTA 1740 1741 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 1742 { 1743 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 1744 1745 if (enable) 1746 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 1747 else 1748 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 1749 } 1750 1751 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 1752 const struct rtw89_dle_mem *cfg, 1753 u16 ext_wde_min_qt_wcpu) 1754 { 1755 wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 1756 ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 1757 } 1758 1759 static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1760 enum rtw89_qta_mode ext_mode) 1761 { 1762 const struct rtw89_dle_mem *cfg, *ext_cfg; 1763 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 1764 int ret = 0; 1765 u32 ini; 1766 1767 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1768 if (ret) 1769 return ret; 1770 1771 cfg = get_dle_mem_cfg(rtwdev, mode); 1772 if (!cfg) { 1773 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1774 ret = -EINVAL; 1775 goto error; 1776 } 1777 1778 if (mode == RTW89_QTA_DLFW) { 1779 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 1780 if (!ext_cfg) { 1781 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 1782 ext_mode); 1783 ret = -EINVAL; 1784 goto error; 1785 } 1786 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 1787 } 1788 1789 if (dle_used_size(cfg->wde_size, cfg->ple_size) != 1790 dle_expected_used_size(rtwdev, mode)) { 1791 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 1792 ret = -EINVAL; 1793 goto error; 1794 } 1795 1796 dle_func_en(rtwdev, false); 1797 dle_clk_en(rtwdev, true); 1798 1799 ret = dle_mix_cfg(rtwdev, cfg); 1800 if (ret) { 1801 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 1802 goto error; 1803 } 1804 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 1805 1806 dle_func_en(rtwdev, true); 1807 1808 ret = read_poll_timeout(rtw89_read32, ini, 1809 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1810 2000, false, rtwdev, R_AX_WDE_INI_STATUS); 1811 if (ret) { 1812 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 1813 return ret; 1814 } 1815 1816 ret = read_poll_timeout(rtw89_read32, ini, 1817 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1818 2000, false, rtwdev, R_AX_PLE_INI_STATUS); 1819 if (ret) { 1820 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 1821 return ret; 1822 } 1823 1824 return 0; 1825 error: 1826 dle_func_en(rtwdev, false); 1827 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 1828 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 1829 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 1830 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 1831 1832 return ret; 1833 } 1834 1835 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1836 enum rtw89_qta_mode mode) 1837 { 1838 u32 reg, max_preld_size, min_rsvd_size; 1839 1840 max_preld_size = (mac_idx == RTW89_MAC_0 ? 1841 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 1842 reg = mac_idx == RTW89_MAC_0 ? 1843 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 1844 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 1845 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 1846 1847 min_rsvd_size = PRELD_AMSDU_SIZE; 1848 reg = mac_idx == RTW89_MAC_0 ? 1849 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 1850 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 1851 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 1852 1853 return 0; 1854 } 1855 1856 static bool is_qta_poh(struct rtw89_dev *rtwdev) 1857 { 1858 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 1859 } 1860 1861 static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1862 enum rtw89_qta_mode mode) 1863 { 1864 const struct rtw89_chip_info *chip = rtwdev->chip; 1865 1866 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 1867 chip->chip_id == RTL8851B || !is_qta_poh(rtwdev)) 1868 return 0; 1869 1870 return preload_init_set(rtwdev, mac_idx, mode); 1871 } 1872 1873 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 1874 { 1875 u32 msk32; 1876 u32 val32; 1877 1878 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 1879 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 1880 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 1881 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1882 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 1883 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 1884 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 1885 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 1886 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1887 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 1888 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1889 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1890 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 1891 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1892 1893 if ((val32 & msk32) == msk32) 1894 return true; 1895 1896 return false; 1897 } 1898 1899 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 1900 { 1901 const struct rtw89_chip_info *chip = rtwdev->chip; 1902 1903 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 1904 chip->chip_id == RTL8851B) 1905 return; 1906 1907 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 1908 SS2F_PATH_WLCPU); 1909 } 1910 1911 static int sta_sch_init(struct rtw89_dev *rtwdev) 1912 { 1913 u32 p_val; 1914 u8 val; 1915 int ret; 1916 1917 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1918 if (ret) 1919 return ret; 1920 1921 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 1922 val |= B_AX_SS_EN; 1923 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 1924 1925 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 1926 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 1927 if (ret) { 1928 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 1929 return ret; 1930 } 1931 1932 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 1933 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 1934 1935 _patch_ss2f_path(rtwdev); 1936 1937 return 0; 1938 } 1939 1940 static int mpdu_proc_init(struct rtw89_dev *rtwdev) 1941 { 1942 int ret; 1943 1944 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1945 if (ret) 1946 return ret; 1947 1948 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 1949 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 1950 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 1951 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 1952 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 1953 1954 return 0; 1955 } 1956 1957 static int sec_eng_init(struct rtw89_dev *rtwdev) 1958 { 1959 const struct rtw89_chip_info *chip = rtwdev->chip; 1960 u32 val = 0; 1961 int ret; 1962 1963 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1964 if (ret) 1965 return ret; 1966 1967 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 1968 /* init clock */ 1969 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 1970 /* init TX encryption */ 1971 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 1972 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 1973 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 1974 chip->chip_id == RTL8851B) 1975 val &= ~B_AX_TX_PARTIAL_MODE; 1976 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 1977 1978 /* init MIC ICV append */ 1979 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 1980 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 1981 1982 /* option init */ 1983 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 1984 1985 if (chip->chip_id == RTL8852C) 1986 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 1987 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 1988 1989 return 0; 1990 } 1991 1992 static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 1993 { 1994 int ret; 1995 1996 ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 1997 if (ret) { 1998 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 1999 return ret; 2000 } 2001 2002 ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2003 if (ret) { 2004 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2005 return ret; 2006 } 2007 2008 ret = hfc_init(rtwdev, true, true, true); 2009 if (ret) { 2010 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2011 return ret; 2012 } 2013 2014 ret = sta_sch_init(rtwdev); 2015 if (ret) { 2016 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2017 return ret; 2018 } 2019 2020 ret = mpdu_proc_init(rtwdev); 2021 if (ret) { 2022 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2023 return ret; 2024 } 2025 2026 ret = sec_eng_init(rtwdev); 2027 if (ret) { 2028 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2029 return ret; 2030 } 2031 2032 return ret; 2033 } 2034 2035 static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2036 { 2037 u32 val, reg; 2038 u16 p_val; 2039 int ret; 2040 2041 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2042 if (ret) 2043 return ret; 2044 2045 reg = rtw89_mac_reg_by_idx(R_AX_ADDR_CAM_CTRL, mac_idx); 2046 2047 val = rtw89_read32(rtwdev, reg); 2048 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2049 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2050 rtw89_write32(rtwdev, reg, val); 2051 2052 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2053 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2054 if (ret) { 2055 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2056 return ret; 2057 } 2058 2059 return 0; 2060 } 2061 2062 static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2063 { 2064 u32 ret; 2065 u32 reg; 2066 u32 val; 2067 2068 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2069 if (ret) 2070 return ret; 2071 2072 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_1, mac_idx); 2073 if (rtwdev->chip->chip_id == RTL8852C) 2074 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2075 SIFS_MACTXEN_T1_V1); 2076 else 2077 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2078 SIFS_MACTXEN_T1); 2079 2080 if (rtwdev->chip->chip_id == RTL8852B || rtwdev->chip->chip_id == RTL8851B) { 2081 reg = rtw89_mac_reg_by_idx(R_AX_SCH_EXT_CTRL, mac_idx); 2082 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2083 } 2084 2085 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CFG_0, mac_idx); 2086 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2087 2088 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_0, mac_idx); 2089 if (rtwdev->chip->chip_id == RTL8852C) { 2090 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2091 B_AX_TX_PARTIAL_MODE); 2092 if (!val) 2093 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2094 SCH_PREBKF_24US); 2095 } else { 2096 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2097 SCH_PREBKF_24US); 2098 } 2099 2100 return 0; 2101 } 2102 2103 int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, 2104 enum rtw89_machdr_frame_type type, 2105 enum rtw89_mac_fwd_target fwd_target, 2106 u8 mac_idx) 2107 { 2108 u32 reg; 2109 u32 val; 2110 2111 switch (fwd_target) { 2112 case RTW89_FWD_DONT_CARE: 2113 val = RX_FLTR_FRAME_DROP; 2114 break; 2115 case RTW89_FWD_TO_HOST: 2116 val = RX_FLTR_FRAME_TO_HOST; 2117 break; 2118 case RTW89_FWD_TO_WLAN_CPU: 2119 val = RX_FLTR_FRAME_TO_WLCPU; 2120 break; 2121 default: 2122 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2123 return -EINVAL; 2124 } 2125 2126 switch (type) { 2127 case RTW89_MGNT: 2128 reg = rtw89_mac_reg_by_idx(R_AX_MGNT_FLTR, mac_idx); 2129 break; 2130 case RTW89_CTRL: 2131 reg = rtw89_mac_reg_by_idx(R_AX_CTRL_FLTR, mac_idx); 2132 break; 2133 case RTW89_DATA: 2134 reg = rtw89_mac_reg_by_idx(R_AX_DATA_FLTR, mac_idx); 2135 break; 2136 default: 2137 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2138 return -EINVAL; 2139 } 2140 rtw89_write32(rtwdev, reg, val); 2141 2142 return 0; 2143 } 2144 2145 static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2146 { 2147 int ret, i; 2148 u32 mac_ftlr, plcp_ftlr; 2149 2150 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2151 if (ret) 2152 return ret; 2153 2154 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2155 ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST, 2156 mac_idx); 2157 if (ret) 2158 return ret; 2159 } 2160 mac_ftlr = rtwdev->hal.rx_fltr; 2161 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2162 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2163 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2164 B_AX_HE_SIGB_CRC_CHK; 2165 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx), 2166 mac_ftlr); 2167 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx), 2168 plcp_ftlr); 2169 2170 return 0; 2171 } 2172 2173 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2174 { 2175 u32 reg, val32; 2176 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2177 2178 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2179 B_AX_RSP_CHK_BASIC_NAV; 2180 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2181 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2182 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2183 2184 switch (rtwdev->chip->chip_id) { 2185 case RTL8852A: 2186 case RTL8852B: 2187 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 2188 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2189 rtw89_write32(rtwdev, reg, val32); 2190 2191 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2192 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2193 rtw89_write32(rtwdev, reg, val32); 2194 break; 2195 default: 2196 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 2197 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2198 rtw89_write32(rtwdev, reg, val32); 2199 2200 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2201 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2202 rtw89_write32(rtwdev, reg, val32); 2203 break; 2204 } 2205 } 2206 2207 static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2208 { 2209 u32 val, reg; 2210 int ret; 2211 2212 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2213 if (ret) 2214 return ret; 2215 2216 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CONTROL, mac_idx); 2217 val = rtw89_read32(rtwdev, reg); 2218 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2219 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2220 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2221 B_AX_CTN_CHK_INTRA_NAV | 2222 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2223 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2224 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2225 B_AX_CTN_CHK_CCA_P20); 2226 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2227 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2228 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2229 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2230 B_AX_SIFS_CHK_EDCCA); 2231 2232 rtw89_write32(rtwdev, reg, val); 2233 2234 _patch_dis_resp_chk(rtwdev, mac_idx); 2235 2236 return 0; 2237 } 2238 2239 static int nav_ctrl_init(struct rtw89_dev *rtwdev) 2240 { 2241 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2242 B_AX_WMAC_TF_UP_NAV_EN | 2243 B_AX_WMAC_NAV_UPPER_EN); 2244 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2245 2246 return 0; 2247 } 2248 2249 static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2250 { 2251 u32 reg; 2252 int ret; 2253 2254 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2255 if (ret) 2256 return ret; 2257 reg = rtw89_mac_reg_by_idx(R_AX_RX_SR_CTRL, mac_idx); 2258 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2259 2260 return 0; 2261 } 2262 2263 static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2264 { 2265 u32 reg; 2266 int ret; 2267 2268 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2269 if (ret) 2270 return ret; 2271 2272 reg = rtw89_mac_reg_by_idx(R_AX_MAC_LOOPBACK, mac_idx); 2273 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2274 2275 reg = rtw89_mac_reg_by_idx(R_AX_TCR0, mac_idx); 2276 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2277 2278 reg = rtw89_mac_reg_by_idx(R_AX_TXD_FIFO_CTRL, mac_idx); 2279 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2280 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2281 2282 return 0; 2283 } 2284 2285 static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2286 { 2287 const struct rtw89_chip_info *chip = rtwdev->chip; 2288 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2289 u32 reg, val, sifs; 2290 int ret; 2291 2292 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2293 if (ret) 2294 return ret; 2295 2296 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2297 val = rtw89_read32(rtwdev, reg); 2298 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2299 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2300 2301 switch (rtwdev->chip->chip_id) { 2302 case RTL8852A: 2303 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2304 break; 2305 case RTL8852B: 2306 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2307 break; 2308 default: 2309 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2310 break; 2311 } 2312 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2313 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2314 rtw89_write32(rtwdev, reg, val); 2315 2316 reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx); 2317 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2318 2319 reg = rtw89_mac_reg_by_idx(rrsr->ref_rate.addr, mac_idx); 2320 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2321 reg = rtw89_mac_reg_by_idx(rrsr->rsc.addr, mac_idx); 2322 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2323 2324 return 0; 2325 } 2326 2327 static void rst_bacam(struct rtw89_dev *rtwdev) 2328 { 2329 u32 val32; 2330 int ret; 2331 2332 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2333 S_AX_BACAM_RST_ALL); 2334 2335 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2336 1, 1000, false, 2337 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2338 if (ret) 2339 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2340 } 2341 2342 static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2343 { 2344 #define TRXCFG_RMAC_CCA_TO 32 2345 #define TRXCFG_RMAC_DATA_TO 15 2346 #define RX_MAX_LEN_UNIT 512 2347 #define PLD_RLS_MAX_PG 127 2348 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2349 int ret; 2350 u32 reg, rx_max_len, rx_qta; 2351 u16 val; 2352 2353 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2354 if (ret) 2355 return ret; 2356 2357 if (mac_idx == RTW89_MAC_0) 2358 rst_bacam(rtwdev); 2359 2360 reg = rtw89_mac_reg_by_idx(R_AX_RESPBA_CAM_CTRL, mac_idx); 2361 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2362 2363 reg = rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx); 2364 val = rtw89_read16(rtwdev, reg); 2365 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2366 B_AX_RX_DLK_DATA_TIME_MASK); 2367 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2368 B_AX_RX_DLK_CCA_TIME_MASK); 2369 rtw89_write16(rtwdev, reg, val); 2370 2371 reg = rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx); 2372 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2373 2374 reg = rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx); 2375 if (mac_idx == RTW89_MAC_0) 2376 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2377 else 2378 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2379 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2380 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2381 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2382 rx_max_len /= RX_MAX_LEN_UNIT; 2383 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2384 2385 if (rtwdev->chip->chip_id == RTL8852A && 2386 rtwdev->hal.cv == CHIP_CBV) { 2387 rtw89_write16_mask(rtwdev, 2388 rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx), 2389 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2390 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx), 2391 BIT(12)); 2392 } 2393 2394 reg = rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx); 2395 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2396 2397 return ret; 2398 } 2399 2400 static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2401 { 2402 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2403 u32 val, reg; 2404 int ret; 2405 2406 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2407 if (ret) 2408 return ret; 2409 2410 reg = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2411 val = rtw89_read32(rtwdev, reg); 2412 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2413 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2414 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2415 rtw89_write32(rtwdev, reg, val); 2416 2417 if (chip_id == RTL8852A || chip_id == RTL8852B) { 2418 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_RRSR1, mac_idx); 2419 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2420 } 2421 2422 return 0; 2423 } 2424 2425 static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2426 { 2427 const struct rtw89_dle_mem *cfg; 2428 2429 cfg = get_dle_mem_cfg(rtwdev, mode); 2430 if (!cfg) { 2431 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2432 return false; 2433 } 2434 2435 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2436 } 2437 2438 static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2439 { 2440 u32 val, reg; 2441 int ret; 2442 2443 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2444 if (ret) 2445 return ret; 2446 2447 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2448 reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); 2449 val = rtw89_read32(rtwdev, reg); 2450 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2451 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2452 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2453 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2454 val |= B_AX_HW_CTS2SELF_EN; 2455 rtw89_write32(rtwdev, reg, val); 2456 2457 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_FSM_MON, mac_idx); 2458 val = rtw89_read32(rtwdev, reg); 2459 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2460 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2461 rtw89_write32(rtwdev, reg, val); 2462 } 2463 2464 if (mac_idx == RTW89_MAC_0) { 2465 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2466 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2467 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2468 B_AX_PTCL_TRIGGER_SS_EN_0 | 2469 B_AX_PTCL_TRIGGER_SS_EN_1 | 2470 B_AX_PTCL_TRIGGER_SS_EN_UL); 2471 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2472 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2473 } else if (mac_idx == RTW89_MAC_1) { 2474 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2475 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2476 } 2477 2478 return 0; 2479 } 2480 2481 static int cmac_dma_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2482 { 2483 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2484 u32 reg; 2485 int ret; 2486 2487 if (chip_id != RTL8852A && chip_id != RTL8852B) 2488 return 0; 2489 2490 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2491 if (ret) 2492 return ret; 2493 2494 reg = rtw89_mac_reg_by_idx(R_AX_RXDMA_CTRL_0, mac_idx); 2495 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2496 2497 return 0; 2498 } 2499 2500 static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2501 { 2502 int ret; 2503 2504 ret = scheduler_init(rtwdev, mac_idx); 2505 if (ret) { 2506 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2507 return ret; 2508 } 2509 2510 ret = addr_cam_init(rtwdev, mac_idx); 2511 if (ret) { 2512 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2513 ret); 2514 return ret; 2515 } 2516 2517 ret = rx_fltr_init(rtwdev, mac_idx); 2518 if (ret) { 2519 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2520 ret); 2521 return ret; 2522 } 2523 2524 ret = cca_ctrl_init(rtwdev, mac_idx); 2525 if (ret) { 2526 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2527 ret); 2528 return ret; 2529 } 2530 2531 ret = nav_ctrl_init(rtwdev); 2532 if (ret) { 2533 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2534 ret); 2535 return ret; 2536 } 2537 2538 ret = spatial_reuse_init(rtwdev, mac_idx); 2539 if (ret) { 2540 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2541 mac_idx, ret); 2542 return ret; 2543 } 2544 2545 ret = tmac_init(rtwdev, mac_idx); 2546 if (ret) { 2547 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2548 return ret; 2549 } 2550 2551 ret = trxptcl_init(rtwdev, mac_idx); 2552 if (ret) { 2553 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2554 return ret; 2555 } 2556 2557 ret = rmac_init(rtwdev, mac_idx); 2558 if (ret) { 2559 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2560 return ret; 2561 } 2562 2563 ret = cmac_com_init(rtwdev, mac_idx); 2564 if (ret) { 2565 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2566 return ret; 2567 } 2568 2569 ret = ptcl_init(rtwdev, mac_idx); 2570 if (ret) { 2571 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2572 return ret; 2573 } 2574 2575 ret = cmac_dma_init(rtwdev, mac_idx); 2576 if (ret) { 2577 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2578 return ret; 2579 } 2580 2581 return ret; 2582 } 2583 2584 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2585 struct rtw89_mac_c2h_info *c2h_info) 2586 { 2587 struct rtw89_mac_h2c_info h2c_info = {0}; 2588 u32 ret; 2589 2590 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2591 h2c_info.content_len = 0; 2592 2593 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2594 if (ret) 2595 return ret; 2596 2597 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2598 return -EINVAL; 2599 2600 return 0; 2601 } 2602 2603 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2604 { 2605 struct rtw89_hal *hal = &rtwdev->hal; 2606 const struct rtw89_chip_info *chip = rtwdev->chip; 2607 struct rtw89_mac_c2h_info c2h_info = {0}; 2608 u8 tx_nss; 2609 u8 rx_nss; 2610 u8 tx_ant; 2611 u8 rx_ant; 2612 u32 ret; 2613 2614 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2615 if (ret) 2616 return ret; 2617 2618 tx_nss = RTW89_GET_C2H_PHYCAP_TX_NSS(c2h_info.c2hreg); 2619 rx_nss = RTW89_GET_C2H_PHYCAP_RX_NSS(c2h_info.c2hreg); 2620 tx_ant = RTW89_GET_C2H_PHYCAP_ANT_TX_NUM(c2h_info.c2hreg); 2621 rx_ant = RTW89_GET_C2H_PHYCAP_ANT_RX_NUM(c2h_info.c2hreg); 2622 2623 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2624 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2625 2626 if (tx_ant == 1) 2627 hal->antenna_tx = RF_B; 2628 if (rx_ant == 1) 2629 hal->antenna_rx = RF_B; 2630 2631 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2632 hal->antenna_tx = RF_B; 2633 hal->tx_path_diversity = true; 2634 } 2635 2636 rtw89_debug(rtwdev, RTW89_DBG_FW, 2637 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2638 hal->tx_nss, tx_nss, chip->tx_nss, 2639 hal->rx_nss, rx_nss, chip->rx_nss); 2640 rtw89_debug(rtwdev, RTW89_DBG_FW, 2641 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2642 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2643 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2644 2645 return 0; 2646 } 2647 2648 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2649 u16 tx_en_u16, u16 mask_u16) 2650 { 2651 u32 ret; 2652 struct rtw89_mac_c2h_info c2h_info = {0}; 2653 struct rtw89_mac_h2c_info h2c_info = {0}; 2654 struct rtw89_h2creg_sch_tx_en *h2creg = 2655 (struct rtw89_h2creg_sch_tx_en *)h2c_info.h2creg; 2656 2657 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2658 h2c_info.content_len = sizeof(*h2creg) - RTW89_H2CREG_HDR_LEN; 2659 h2creg->tx_en = tx_en_u16; 2660 h2creg->mask = mask_u16; 2661 h2creg->band = band; 2662 2663 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2664 if (ret) 2665 return ret; 2666 2667 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2668 return -EINVAL; 2669 2670 return 0; 2671 } 2672 2673 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2674 u16 tx_en, u16 tx_en_mask) 2675 { 2676 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx); 2677 u16 val; 2678 int ret; 2679 2680 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2681 if (ret) 2682 return ret; 2683 2684 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 2685 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 2686 tx_en, tx_en_mask); 2687 2688 val = rtw89_read16(rtwdev, reg); 2689 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2690 rtw89_write16(rtwdev, reg, val); 2691 2692 return 0; 2693 } 2694 2695 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2696 u32 tx_en, u32 tx_en_mask) 2697 { 2698 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx); 2699 u32 val; 2700 int ret; 2701 2702 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2703 if (ret) 2704 return ret; 2705 2706 val = rtw89_read32(rtwdev, reg); 2707 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2708 rtw89_write32(rtwdev, reg, val); 2709 2710 return 0; 2711 } 2712 2713 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 2714 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2715 { 2716 int ret; 2717 2718 *tx_en = rtw89_read16(rtwdev, 2719 rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx)); 2720 2721 switch (sel) { 2722 case RTW89_SCH_TX_SEL_ALL: 2723 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2724 B_AX_CTN_TXEN_ALL_MASK); 2725 if (ret) 2726 return ret; 2727 break; 2728 case RTW89_SCH_TX_SEL_HIQ: 2729 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2730 0, B_AX_CTN_TXEN_HGQ); 2731 if (ret) 2732 return ret; 2733 break; 2734 case RTW89_SCH_TX_SEL_MG0: 2735 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2736 0, B_AX_CTN_TXEN_MGQ); 2737 if (ret) 2738 return ret; 2739 break; 2740 case RTW89_SCH_TX_SEL_MACID: 2741 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2742 B_AX_CTN_TXEN_ALL_MASK); 2743 if (ret) 2744 return ret; 2745 break; 2746 default: 2747 return 0; 2748 } 2749 2750 return 0; 2751 } 2752 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 2753 2754 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2755 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2756 { 2757 int ret; 2758 2759 *tx_en = rtw89_read32(rtwdev, 2760 rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx)); 2761 2762 switch (sel) { 2763 case RTW89_SCH_TX_SEL_ALL: 2764 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2765 B_AX_CTN_TXEN_ALL_MASK_V1); 2766 if (ret) 2767 return ret; 2768 break; 2769 case RTW89_SCH_TX_SEL_HIQ: 2770 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2771 0, B_AX_CTN_TXEN_HGQ); 2772 if (ret) 2773 return ret; 2774 break; 2775 case RTW89_SCH_TX_SEL_MG0: 2776 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2777 0, B_AX_CTN_TXEN_MGQ); 2778 if (ret) 2779 return ret; 2780 break; 2781 case RTW89_SCH_TX_SEL_MACID: 2782 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2783 B_AX_CTN_TXEN_ALL_MASK_V1); 2784 if (ret) 2785 return ret; 2786 break; 2787 default: 2788 return 0; 2789 } 2790 2791 return 0; 2792 } 2793 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 2794 2795 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2796 { 2797 int ret; 2798 2799 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 2800 if (ret) 2801 return ret; 2802 2803 return 0; 2804 } 2805 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 2806 2807 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2808 { 2809 int ret; 2810 2811 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 2812 B_AX_CTN_TXEN_ALL_MASK_V1); 2813 if (ret) 2814 return ret; 2815 2816 return 0; 2817 } 2818 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 2819 2820 int rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 2821 { 2822 u32 val, reg; 2823 int ret; 2824 2825 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 2826 val = buf_len; 2827 val |= B_AX_WD_BUF_REQ_EXEC; 2828 rtw89_write32(rtwdev, reg, val); 2829 2830 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 2831 2832 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 2833 1, 2000, false, rtwdev, reg); 2834 if (ret) 2835 return ret; 2836 2837 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 2838 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 2839 return -ENOENT; 2840 2841 return 0; 2842 } 2843 2844 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, 2845 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 2846 { 2847 u32 val, cmd_type, reg; 2848 int ret; 2849 2850 cmd_type = ctrl_para->cmd_type; 2851 2852 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 2853 val = 0; 2854 val = u32_replace_bits(val, ctrl_para->start_pktid, 2855 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 2856 val = u32_replace_bits(val, ctrl_para->end_pktid, 2857 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 2858 rtw89_write32(rtwdev, reg, val); 2859 2860 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 2861 val = 0; 2862 val = u32_replace_bits(val, ctrl_para->src_pid, 2863 B_AX_CPUQ_OP_SRC_PID_MASK); 2864 val = u32_replace_bits(val, ctrl_para->src_qid, 2865 B_AX_CPUQ_OP_SRC_QID_MASK); 2866 val = u32_replace_bits(val, ctrl_para->dst_pid, 2867 B_AX_CPUQ_OP_DST_PID_MASK); 2868 val = u32_replace_bits(val, ctrl_para->dst_qid, 2869 B_AX_CPUQ_OP_DST_QID_MASK); 2870 rtw89_write32(rtwdev, reg, val); 2871 2872 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 2873 val = 0; 2874 val = u32_replace_bits(val, cmd_type, 2875 B_AX_CPUQ_OP_CMD_TYPE_MASK); 2876 val = u32_replace_bits(val, ctrl_para->macid, 2877 B_AX_CPUQ_OP_MACID_MASK); 2878 val = u32_replace_bits(val, ctrl_para->pkt_num, 2879 B_AX_CPUQ_OP_PKTNUM_MASK); 2880 val |= B_AX_WD_CPUQ_OP_EXEC; 2881 rtw89_write32(rtwdev, reg, val); 2882 2883 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 2884 2885 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 2886 1, 2000, false, rtwdev, reg); 2887 if (ret) 2888 return ret; 2889 2890 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 2891 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 2892 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 2893 2894 return 0; 2895 } 2896 2897 static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2898 { 2899 const struct rtw89_dle_mem *cfg; 2900 struct rtw89_cpuio_ctrl ctrl_para = {0}; 2901 u16 pkt_id; 2902 int ret; 2903 2904 cfg = get_dle_mem_cfg(rtwdev, mode); 2905 if (!cfg) { 2906 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2907 return -EINVAL; 2908 } 2909 2910 if (dle_used_size(cfg->wde_size, cfg->ple_size) != 2911 dle_expected_used_size(rtwdev, mode)) { 2912 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2913 return -EINVAL; 2914 } 2915 2916 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 2917 2918 ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, true, &pkt_id); 2919 if (ret) { 2920 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 2921 return ret; 2922 } 2923 2924 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2925 ctrl_para.start_pktid = pkt_id; 2926 ctrl_para.end_pktid = pkt_id; 2927 ctrl_para.pkt_num = 0; 2928 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 2929 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 2930 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true); 2931 if (ret) { 2932 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 2933 return -EFAULT; 2934 } 2935 2936 ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, false, &pkt_id); 2937 if (ret) { 2938 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 2939 return ret; 2940 } 2941 2942 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2943 ctrl_para.start_pktid = pkt_id; 2944 ctrl_para.end_pktid = pkt_id; 2945 ctrl_para.pkt_num = 0; 2946 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 2947 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 2948 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false); 2949 if (ret) { 2950 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 2951 return -EFAULT; 2952 } 2953 2954 return 0; 2955 } 2956 2957 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 2958 { 2959 int ret; 2960 u32 reg; 2961 u8 val; 2962 2963 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2964 if (ret) 2965 return ret; 2966 2967 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_TX_CTN_SEL, mac_idx); 2968 2969 ret = read_poll_timeout(rtw89_read8, val, 2970 (val & B_AX_PTCL_TX_ON_STAT) == 0, 2971 SW_CVR_DUR_US, 2972 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 2973 false, rtwdev, reg); 2974 if (ret) 2975 return ret; 2976 2977 return 0; 2978 } 2979 2980 static int band1_enable(struct rtw89_dev *rtwdev) 2981 { 2982 int ret, i; 2983 u32 sleep_bak[4] = {0}; 2984 u32 pause_bak[4] = {0}; 2985 u32 tx_en; 2986 2987 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 2988 if (ret) { 2989 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 2990 return ret; 2991 } 2992 2993 for (i = 0; i < 4; i++) { 2994 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 2995 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 2996 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 2997 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 2998 } 2999 3000 ret = band_idle_ck_b(rtwdev, 0); 3001 if (ret) { 3002 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3003 return ret; 3004 } 3005 3006 ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode); 3007 if (ret) { 3008 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3009 return ret; 3010 } 3011 3012 for (i = 0; i < 4; i++) { 3013 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3014 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3015 } 3016 3017 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3018 if (ret) { 3019 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3020 return ret; 3021 } 3022 3023 ret = cmac_func_en(rtwdev, 1, true); 3024 if (ret) { 3025 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3026 return ret; 3027 } 3028 3029 ret = cmac_init(rtwdev, 1); 3030 if (ret) { 3031 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3032 return ret; 3033 } 3034 3035 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3036 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3037 3038 return 0; 3039 } 3040 3041 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3042 { 3043 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3044 3045 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3046 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3047 } 3048 3049 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3050 { 3051 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3052 3053 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3054 } 3055 3056 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3057 { 3058 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3059 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3060 3061 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3062 B_AX_TX_GET_ERRPKTID_INT_EN | 3063 B_AX_TX_NXT_ERRPKTID_INT_EN | 3064 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3065 B_AX_TX_OFFSET_ERR_INT_EN | 3066 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3067 if (chip_id == RTL8852C) 3068 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3069 B_AX_TX_ETH_TYPE_ERR_EN | 3070 B_AX_TX_LLC_PRE_ERR_EN | 3071 B_AX_TX_NW_TYPE_ERR_EN | 3072 B_AX_TX_KSRCH_ERR_EN); 3073 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3074 imr->mpdu_tx_imr_set); 3075 3076 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3077 B_AX_GETPKTID_ERR_INT_EN | 3078 B_AX_MHDRLEN_ERR_INT_EN | 3079 B_AX_RPT_ERR_INT_EN); 3080 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3081 imr->mpdu_rx_imr_set); 3082 } 3083 3084 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3085 { 3086 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3087 3088 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3089 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3090 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3091 B_AX_PLE_B_PKTID_ERR_INT_EN); 3092 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3093 imr->sta_sch_imr_set); 3094 } 3095 3096 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3097 { 3098 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3099 3100 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3101 imr->txpktctl_imr_b0_clr); 3102 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3103 imr->txpktctl_imr_b0_set); 3104 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3105 imr->txpktctl_imr_b1_clr); 3106 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3107 imr->txpktctl_imr_b1_set); 3108 } 3109 3110 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3111 { 3112 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3113 3114 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3115 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3116 } 3117 3118 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3119 { 3120 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3121 3122 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3123 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3124 } 3125 3126 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3127 { 3128 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3129 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3130 } 3131 3132 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3133 { 3134 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3135 3136 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3137 imr->host_disp_imr_clr); 3138 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3139 imr->host_disp_imr_set); 3140 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3141 imr->cpu_disp_imr_clr); 3142 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3143 imr->cpu_disp_imr_set); 3144 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3145 imr->other_disp_imr_clr); 3146 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3147 imr->other_disp_imr_set); 3148 } 3149 3150 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3151 { 3152 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3153 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3154 } 3155 3156 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3157 { 3158 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3159 3160 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3161 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3162 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3163 B_AX_BBRPT_CHINFO_IMR_CLR); 3164 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3165 imr->bbrpt_err_imr_set); 3166 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3167 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3168 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3169 } 3170 3171 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3172 { 3173 u32 reg; 3174 3175 reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx); 3176 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3177 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3178 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3179 } 3180 3181 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3182 { 3183 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3184 u32 reg; 3185 3186 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx); 3187 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3188 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3189 } 3190 3191 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3192 { 3193 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3194 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3195 u32 reg; 3196 3197 reg = rtw89_mac_reg_by_idx(imr->cdma_imr_0_reg, mac_idx); 3198 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3199 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3200 3201 if (chip_id == RTL8852C) { 3202 reg = rtw89_mac_reg_by_idx(imr->cdma_imr_1_reg, mac_idx); 3203 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3204 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3205 } 3206 } 3207 3208 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3209 { 3210 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3211 u32 reg; 3212 3213 reg = rtw89_mac_reg_by_idx(imr->phy_intf_imr_reg, mac_idx); 3214 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3215 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3216 } 3217 3218 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3219 { 3220 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3221 u32 reg; 3222 3223 reg = rtw89_mac_reg_by_idx(imr->rmac_imr_reg, mac_idx); 3224 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3225 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3226 } 3227 3228 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3229 { 3230 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3231 u32 reg; 3232 3233 reg = rtw89_mac_reg_by_idx(imr->tmac_imr_reg, mac_idx); 3234 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3235 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3236 } 3237 3238 static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, 3239 enum rtw89_mac_hwmod_sel sel) 3240 { 3241 int ret; 3242 3243 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3244 if (ret) { 3245 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3246 sel, mac_idx); 3247 return ret; 3248 } 3249 3250 if (sel == RTW89_DMAC_SEL) { 3251 rtw89_wdrls_imr_enable(rtwdev); 3252 rtw89_wsec_imr_enable(rtwdev); 3253 rtw89_mpdu_trx_imr_enable(rtwdev); 3254 rtw89_sta_sch_imr_enable(rtwdev); 3255 rtw89_txpktctl_imr_enable(rtwdev); 3256 rtw89_wde_imr_enable(rtwdev); 3257 rtw89_ple_imr_enable(rtwdev); 3258 rtw89_pktin_imr_enable(rtwdev); 3259 rtw89_dispatcher_imr_enable(rtwdev); 3260 rtw89_cpuio_imr_enable(rtwdev); 3261 rtw89_bbrpt_imr_enable(rtwdev); 3262 } else if (sel == RTW89_CMAC_SEL) { 3263 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3264 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3265 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3266 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3267 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3268 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3269 } else { 3270 return -EINVAL; 3271 } 3272 3273 return 0; 3274 } 3275 3276 static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en) 3277 { 3278 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3279 3280 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3281 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3282 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3283 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3284 if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta) 3285 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3286 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3287 } 3288 3289 static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) 3290 { 3291 int ret = 0; 3292 3293 if (enable) { 3294 ret = band1_enable(rtwdev); 3295 if (ret) { 3296 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3297 return ret; 3298 } 3299 3300 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3301 if (ret) { 3302 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3303 return ret; 3304 } 3305 } else { 3306 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3307 return -EINVAL; 3308 } 3309 3310 return 0; 3311 } 3312 3313 static int set_host_rpr(struct rtw89_dev *rtwdev) 3314 { 3315 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3316 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3317 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3318 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3319 B_AX_RLSRPT0_FLTR_MAP_MASK); 3320 } else { 3321 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3322 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3323 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3324 B_AX_RLSRPT0_FLTR_MAP_MASK); 3325 } 3326 3327 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3328 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3329 3330 return 0; 3331 } 3332 3333 static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) 3334 { 3335 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3336 int ret; 3337 3338 ret = dmac_init(rtwdev, 0); 3339 if (ret) { 3340 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3341 return ret; 3342 } 3343 3344 ret = cmac_init(rtwdev, 0); 3345 if (ret) { 3346 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3347 return ret; 3348 } 3349 3350 if (is_qta_dbcc(rtwdev, qta_mode)) { 3351 ret = rtw89_mac_dbcc_enable(rtwdev, true); 3352 if (ret) { 3353 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3354 return ret; 3355 } 3356 } 3357 3358 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3359 if (ret) { 3360 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3361 return ret; 3362 } 3363 3364 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3365 if (ret) { 3366 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3367 return ret; 3368 } 3369 3370 rtw89_mac_err_imr_ctrl(rtwdev, true); 3371 3372 ret = set_host_rpr(rtwdev); 3373 if (ret) { 3374 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3375 return ret; 3376 } 3377 3378 return 0; 3379 } 3380 3381 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3382 { 3383 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3384 u32 val32; 3385 3386 if (chip_id == RTL8852B || chip_id == RTL8851B) { 3387 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3388 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3389 return; 3390 } 3391 3392 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3393 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3394 3395 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3396 val32 |= B_AX_FS_WDT_INT; 3397 val32 &= ~B_AX_FS_WDT_INT_MSK; 3398 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3399 } 3400 3401 void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev) 3402 { 3403 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3404 3405 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3406 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3407 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3408 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3409 3410 rtw89_disable_fw_watchdog(rtwdev); 3411 3412 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3413 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3414 } 3415 3416 int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw) 3417 { 3418 u32 val; 3419 int ret; 3420 3421 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3422 return -EFAULT; 3423 3424 rtw89_write32(rtwdev, R_AX_UDM1, 0); 3425 rtw89_write32(rtwdev, R_AX_UDM2, 0); 3426 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3427 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3428 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3429 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3430 3431 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3432 3433 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3434 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3435 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3436 B_AX_WCPU_FWDL_STS_MASK); 3437 3438 if (dlfw) 3439 val |= B_AX_WCPU_FWDL_EN; 3440 3441 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3442 3443 if (rtwdev->chip->chip_id == RTL8852B) 3444 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 3445 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 3446 3447 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3448 boot_reason); 3449 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3450 3451 if (!dlfw) { 3452 mdelay(5); 3453 3454 ret = rtw89_fw_check_rdy(rtwdev); 3455 if (ret) 3456 return ret; 3457 } 3458 3459 return 0; 3460 } 3461 3462 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3463 { 3464 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3465 u32 val; 3466 int ret; 3467 3468 if (chip_id == RTL8852C) 3469 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3470 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3471 else 3472 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3473 B_AX_PKT_BUF_EN; 3474 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3475 3476 if (chip_id == RTL8851B) 3477 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 3478 else 3479 val = B_AX_DISPATCHER_CLK_EN; 3480 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3481 3482 if (chip_id != RTL8852C) 3483 goto dle; 3484 3485 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3486 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3487 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3488 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3489 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3490 3491 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3492 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3493 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3494 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3495 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3496 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3497 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3498 3499 dle: 3500 ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3501 if (ret) { 3502 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3503 return ret; 3504 } 3505 3506 ret = hfc_init(rtwdev, true, false, true); 3507 if (ret) { 3508 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3509 return ret; 3510 } 3511 3512 return ret; 3513 } 3514 3515 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3516 { 3517 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3518 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3519 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3520 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3521 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3522 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3523 3524 return 0; 3525 } 3526 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3527 3528 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3529 { 3530 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3531 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3532 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3533 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3534 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3535 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3536 3537 return 0; 3538 } 3539 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3540 3541 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev) 3542 { 3543 int ret; 3544 3545 ret = rtw89_mac_power_switch(rtwdev, true); 3546 if (ret) { 3547 rtw89_mac_power_switch(rtwdev, false); 3548 ret = rtw89_mac_power_switch(rtwdev, true); 3549 if (ret) 3550 return ret; 3551 } 3552 3553 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3554 3555 ret = rtw89_mac_dmac_pre_init(rtwdev); 3556 if (ret) 3557 return ret; 3558 3559 if (rtwdev->hci.ops->mac_pre_init) { 3560 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3561 if (ret) 3562 return ret; 3563 } 3564 3565 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL); 3566 if (ret) 3567 return ret; 3568 3569 return 0; 3570 } 3571 3572 int rtw89_mac_init(struct rtw89_dev *rtwdev) 3573 { 3574 int ret; 3575 3576 ret = rtw89_mac_partial_init(rtwdev); 3577 if (ret) 3578 goto fail; 3579 3580 ret = rtw89_chip_enable_bb_rf(rtwdev); 3581 if (ret) 3582 goto fail; 3583 3584 ret = rtw89_mac_sys_init(rtwdev); 3585 if (ret) 3586 goto fail; 3587 3588 ret = rtw89_mac_trx_init(rtwdev); 3589 if (ret) 3590 goto fail; 3591 3592 if (rtwdev->hci.ops->mac_post_init) { 3593 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3594 if (ret) 3595 goto fail; 3596 } 3597 3598 rtw89_fw_send_all_early_h2c(rtwdev); 3599 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3600 3601 return ret; 3602 fail: 3603 rtw89_mac_power_switch(rtwdev, false); 3604 3605 return ret; 3606 } 3607 3608 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3609 { 3610 u8 i; 3611 3612 for (i = 0; i < 4; i++) { 3613 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3614 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 3615 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 3616 } 3617 } 3618 3619 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3620 { 3621 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3622 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 3623 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 3624 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 3625 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 3626 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 3627 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 3628 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 3629 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 3630 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 3631 } 3632 3633 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 3634 { 3635 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 3636 u8 grp = macid >> 5; 3637 int ret; 3638 3639 /* If this is called by change_interface() in the case of P2P, it could 3640 * be power-off, so ignore this operation. 3641 */ 3642 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 3643 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3644 return 0; 3645 3646 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3647 if (ret) 3648 return ret; 3649 3650 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 3651 3652 return 0; 3653 } 3654 3655 static const struct rtw89_port_reg rtw_port_base = { 3656 .port_cfg = R_AX_PORT_CFG_P0, 3657 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 3658 .bcn_area = R_AX_BCN_AREA_P0, 3659 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 3660 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 3661 .tbtt_agg = R_AX_TBTT_AGG_P0, 3662 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 3663 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 3664 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 3665 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 3666 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 3667 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 3668 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 3669 .tsftr_l = R_AX_TSFTR_LOW_P0, 3670 .tsftr_h = R_AX_TSFTR_HIGH_P0 3671 }; 3672 3673 #define BCN_INTERVAL 100 3674 #define BCN_ERLY_DEF 160 3675 #define BCN_SETUP_DEF 2 3676 #define BCN_HOLD_DEF 200 3677 #define BCN_MASK_DEF 0 3678 #define TBTT_ERLY_DEF 5 3679 #define BCN_SET_UNIT 32 3680 #define BCN_ERLY_SET_DLY (10 * 2) 3681 3682 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 3683 struct rtw89_vif *rtwvif) 3684 { 3685 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3686 const struct rtw89_port_reg *p = &rtw_port_base; 3687 3688 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 3689 return; 3690 3691 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 3692 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 3693 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 3694 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 3695 3696 msleep(vif->bss_conf.beacon_int + 1); 3697 3698 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 3699 B_AX_BRK_SETUP); 3700 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 3701 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 3702 } 3703 3704 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 3705 struct rtw89_vif *rtwvif, bool en) 3706 { 3707 const struct rtw89_port_reg *p = &rtw_port_base; 3708 3709 if (en) 3710 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3711 else 3712 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3713 } 3714 3715 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 3716 struct rtw89_vif *rtwvif, bool en) 3717 { 3718 const struct rtw89_port_reg *p = &rtw_port_base; 3719 3720 if (en) 3721 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3722 else 3723 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3724 } 3725 3726 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 3727 struct rtw89_vif *rtwvif) 3728 { 3729 const struct rtw89_port_reg *p = &rtw_port_base; 3730 3731 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 3732 rtwvif->net_type); 3733 } 3734 3735 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 3736 struct rtw89_vif *rtwvif) 3737 { 3738 const struct rtw89_port_reg *p = &rtw_port_base; 3739 bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 3740 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 3741 3742 if (en) 3743 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 3744 else 3745 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 3746 } 3747 3748 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 3749 struct rtw89_vif *rtwvif) 3750 { 3751 const struct rtw89_port_reg *p = &rtw_port_base; 3752 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3753 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3754 u32 bit = B_AX_RX_BSSID_FIT_EN; 3755 3756 if (en) 3757 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 3758 else 3759 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 3760 } 3761 3762 static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 3763 struct rtw89_vif *rtwvif) 3764 { 3765 const struct rtw89_port_reg *p = &rtw_port_base; 3766 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3767 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3768 3769 if (en) 3770 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3771 else 3772 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3773 } 3774 3775 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 3776 struct rtw89_vif *rtwvif) 3777 { 3778 const struct rtw89_port_reg *p = &rtw_port_base; 3779 bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 3780 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3781 3782 if (en) 3783 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3784 else 3785 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3786 } 3787 3788 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 3789 struct rtw89_vif *rtwvif) 3790 { 3791 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3792 const struct rtw89_port_reg *p = &rtw_port_base; 3793 u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 3794 3795 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 3796 bcn_int); 3797 } 3798 3799 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 3800 struct rtw89_vif *rtwvif) 3801 { 3802 static const u32 hiq_win_addr[RTW89_PORT_NUM] = { 3803 R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 3804 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 3805 R_AX_PORT_HGQ_WINDOW_CFG + 3, 3806 }; 3807 u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 3808 u8 port = rtwvif->port; 3809 u32 reg; 3810 3811 reg = rtw89_mac_reg_by_idx(hiq_win_addr[port], rtwvif->mac_idx); 3812 rtw89_write8(rtwdev, reg, win); 3813 } 3814 3815 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 3816 struct rtw89_vif *rtwvif) 3817 { 3818 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3819 const struct rtw89_port_reg *p = &rtw_port_base; 3820 u32 addr; 3821 3822 addr = rtw89_mac_reg_by_idx(R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx); 3823 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 3824 3825 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 3826 vif->bss_conf.dtim_period); 3827 } 3828 3829 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 3830 struct rtw89_vif *rtwvif) 3831 { 3832 const struct rtw89_port_reg *p = &rtw_port_base; 3833 3834 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3835 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 3836 } 3837 3838 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 3839 struct rtw89_vif *rtwvif) 3840 { 3841 const struct rtw89_port_reg *p = &rtw_port_base; 3842 3843 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3844 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 3845 } 3846 3847 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 3848 struct rtw89_vif *rtwvif) 3849 { 3850 const struct rtw89_port_reg *p = &rtw_port_base; 3851 3852 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 3853 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 3854 } 3855 3856 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 3857 struct rtw89_vif *rtwvif) 3858 { 3859 const struct rtw89_port_reg *p = &rtw_port_base; 3860 3861 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 3862 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 3863 } 3864 3865 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 3866 struct rtw89_vif *rtwvif) 3867 { 3868 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3869 static const u32 masks[RTW89_PORT_NUM] = { 3870 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 3871 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 3872 B_AX_BSS_COLOB_AX_PORT_4_MASK, 3873 }; 3874 u8 port = rtwvif->port; 3875 u32 reg_base; 3876 u32 reg; 3877 u8 bss_color; 3878 3879 bss_color = vif->bss_conf.he_bss_color.color; 3880 reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0; 3881 reg = rtw89_mac_reg_by_idx(reg_base, rtwvif->mac_idx); 3882 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 3883 } 3884 3885 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 3886 struct rtw89_vif *rtwvif) 3887 { 3888 u8 port = rtwvif->port; 3889 u32 reg; 3890 3891 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 3892 return; 3893 3894 if (port == 0) { 3895 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_CTRL, rtwvif->mac_idx); 3896 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 3897 } 3898 } 3899 3900 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 3901 struct rtw89_vif *rtwvif) 3902 { 3903 u8 port = rtwvif->port; 3904 u32 reg; 3905 u32 val; 3906 3907 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_DROP_0, rtwvif->mac_idx); 3908 val = rtw89_read32(rtwdev, reg); 3909 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 3910 if (port == 0) 3911 val &= ~BIT(0); 3912 rtw89_write32(rtwdev, reg, val); 3913 } 3914 3915 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 3916 struct rtw89_vif *rtwvif, bool enable) 3917 { 3918 const struct rtw89_port_reg *p = &rtw_port_base; 3919 3920 if (enable) 3921 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, 3922 B_AX_PORT_FUNC_EN); 3923 else 3924 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, 3925 B_AX_PORT_FUNC_EN); 3926 } 3927 3928 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 3929 struct rtw89_vif *rtwvif) 3930 { 3931 const struct rtw89_port_reg *p = &rtw_port_base; 3932 3933 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 3934 BCN_ERLY_DEF); 3935 } 3936 3937 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 3938 struct rtw89_vif *rtwvif) 3939 { 3940 const struct rtw89_port_reg *p = &rtw_port_base; 3941 u16 val; 3942 3943 if (rtwdev->chip->chip_id != RTL8852C) 3944 return; 3945 3946 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 3947 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 3948 return; 3949 3950 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 3951 B_AX_TBTT_SHIFT_OFST_SIGN; 3952 3953 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift, 3954 B_AX_TBTT_SHIFT_OFST_MASK, val); 3955 } 3956 3957 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 3958 struct rtw89_vif *rtwvif, 3959 struct rtw89_vif *rtwvif_src, 3960 u16 offset_tu) 3961 { 3962 u32 val, reg; 3963 3964 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 3965 reg = rtw89_mac_reg_by_idx(R_AX_PORT0_TSF_SYNC + rtwvif->port * 4, 3966 rtwvif->mac_idx); 3967 3968 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 3969 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 3970 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 3971 } 3972 3973 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 3974 struct rtw89_vif *rtwvif, 3975 struct rtw89_vif *rtwvif_src, 3976 u8 offset, int *n_offset) 3977 { 3978 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src) 3979 return; 3980 3981 /* adjust offset randomly to avoid beacon conflict */ 3982 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 3983 rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src, 3984 (*n_offset) * offset); 3985 3986 (*n_offset)++; 3987 } 3988 3989 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 3990 { 3991 struct rtw89_vif *src = NULL, *tmp; 3992 u8 offset = 100, vif_aps = 0; 3993 int n_offset = 1; 3994 3995 rtw89_for_each_rtwvif(rtwdev, tmp) { 3996 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 3997 src = tmp; 3998 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 3999 vif_aps++; 4000 } 4001 4002 if (vif_aps == 0) 4003 return; 4004 4005 offset /= (vif_aps + 1); 4006 4007 rtw89_for_each_rtwvif(rtwdev, tmp) 4008 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset); 4009 } 4010 4011 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4012 { 4013 int ret; 4014 4015 ret = rtw89_mac_port_update(rtwdev, rtwvif); 4016 if (ret) 4017 return ret; 4018 4019 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 4020 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 4021 4022 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 4023 if (ret) 4024 return ret; 4025 4026 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 4027 if (ret) 4028 return ret; 4029 4030 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true); 4031 if (ret) 4032 return ret; 4033 4034 ret = rtw89_cam_init(rtwdev, rtwvif); 4035 if (ret) 4036 return ret; 4037 4038 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4039 if (ret) 4040 return ret; 4041 4042 ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif); 4043 if (ret) 4044 return ret; 4045 4046 return 0; 4047 } 4048 4049 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4050 { 4051 int ret; 4052 4053 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 4054 if (ret) 4055 return ret; 4056 4057 rtw89_cam_deinit(rtwdev, rtwvif); 4058 4059 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4060 if (ret) 4061 return ret; 4062 4063 return 0; 4064 } 4065 4066 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4067 { 4068 u8 port = rtwvif->port; 4069 4070 if (port >= RTW89_PORT_NUM) 4071 return -EINVAL; 4072 4073 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4074 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 4075 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 4076 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 4077 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 4078 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 4079 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); 4080 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif); 4081 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 4082 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 4083 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 4084 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 4085 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 4086 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 4087 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 4088 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 4089 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif); 4090 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 4091 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 4092 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true); 4093 rtw89_mac_port_tsf_resync_all(rtwdev); 4094 fsleep(BCN_ERLY_SET_DLY); 4095 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 4096 4097 return 0; 4098 } 4099 4100 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4101 u64 *tsf) 4102 { 4103 const struct rtw89_port_reg *p = &rtw_port_base; 4104 u32 tsf_low, tsf_high; 4105 int ret; 4106 4107 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL); 4108 if (ret) 4109 return ret; 4110 4111 tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l); 4112 tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h); 4113 *tsf = (u64)tsf_high << 32 | tsf_low; 4114 4115 return 0; 4116 } 4117 4118 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 4119 struct cfg80211_bss *bss, 4120 void *data) 4121 { 4122 const struct cfg80211_bss_ies *ies; 4123 const struct element *elem; 4124 bool *tolerated = data; 4125 4126 rcu_read_lock(); 4127 ies = rcu_dereference(bss->ies); 4128 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 4129 ies->len); 4130 4131 if (!elem || elem->datalen < 10 || 4132 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 4133 *tolerated = false; 4134 rcu_read_unlock(); 4135 } 4136 4137 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 4138 struct ieee80211_vif *vif) 4139 { 4140 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4141 struct ieee80211_hw *hw = rtwdev->hw; 4142 bool tolerated = true; 4143 u32 reg; 4144 4145 if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION) 4146 return; 4147 4148 if (!(vif->bss_conf.chandef.chan->flags & IEEE80211_CHAN_RADAR)) 4149 return; 4150 4151 cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chandef, 4152 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 4153 &tolerated); 4154 4155 reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx); 4156 if (tolerated) 4157 rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 4158 else 4159 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 4160 } 4161 4162 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4163 { 4164 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, false); 4165 } 4166 4167 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4168 { 4169 int ret; 4170 4171 rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 4172 RTW89_MAX_MAC_ID_NUM); 4173 if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 4174 return -ENOSPC; 4175 4176 ret = rtw89_mac_vif_init(rtwdev, rtwvif); 4177 if (ret) 4178 goto release_mac_id; 4179 4180 return 0; 4181 4182 release_mac_id: 4183 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4184 4185 return ret; 4186 } 4187 4188 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4189 { 4190 int ret; 4191 4192 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 4193 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4194 4195 return ret; 4196 } 4197 4198 static void 4199 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4200 { 4201 } 4202 4203 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 4204 { 4205 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 4206 4207 return band == op->band_type && channel == op->primary_channel; 4208 } 4209 4210 static void 4211 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4212 u32 len) 4213 { 4214 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 4215 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 4216 struct rtw89_chan new; 4217 u8 reason, status, tx_fail, band, actual_period; 4218 u32 last_chan = rtwdev->scan_info.last_chan_idx; 4219 u16 chan; 4220 int ret; 4221 4222 if (!rtwvif) 4223 return; 4224 4225 tx_fail = RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h->data); 4226 status = RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h->data); 4227 chan = RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h->data); 4228 reason = RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h->data); 4229 band = RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h->data); 4230 actual_period = RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h->data); 4231 4232 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 4233 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 4234 4235 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4236 "band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 4237 band, chan, reason, status, tx_fail, actual_period); 4238 4239 switch (reason) { 4240 case RTW89_SCAN_LEAVE_CH_NOTIFY: 4241 if (rtw89_is_op_chan(rtwdev, band, chan)) 4242 ieee80211_stop_queues(rtwdev->hw); 4243 return; 4244 case RTW89_SCAN_END_SCAN_NOTIFY: 4245 if (rtwvif && rtwvif->scan_req && 4246 last_chan < rtwvif->scan_req->n_channels) { 4247 ret = rtw89_hw_scan_offload(rtwdev, vif, true); 4248 if (ret) { 4249 rtw89_hw_scan_abort(rtwdev, vif); 4250 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 4251 } 4252 } else { 4253 rtw89_hw_scan_complete(rtwdev, vif, false); 4254 } 4255 break; 4256 case RTW89_SCAN_ENTER_CH_NOTIFY: 4257 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4258 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4259 &rtwdev->scan_info.op_chan); 4260 ieee80211_wake_queues(rtwdev->hw); 4261 } else { 4262 rtw89_chan_create(&new, chan, chan, band, 4263 RTW89_CHANNEL_WIDTH_20); 4264 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4265 &new); 4266 } 4267 break; 4268 default: 4269 return; 4270 } 4271 } 4272 4273 static void 4274 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4275 struct sk_buff *skb) 4276 { 4277 struct ieee80211_vif *vif = rtwvif_to_vif_safe(rtwvif); 4278 enum nl80211_cqm_rssi_threshold_event nl_event; 4279 const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 4280 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 4281 u8 type, event, mac_id; 4282 s8 sig; 4283 4284 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 4285 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 4286 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 4287 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 4288 4289 if (mac_id != rtwvif->mac_id) 4290 return; 4291 4292 rtw89_debug(rtwdev, RTW89_DBG_FW, 4293 "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 4294 mac_id, type, sig, event); 4295 4296 switch (type) { 4297 case RTW89_BCN_FLTR_BEACON_LOSS: 4298 if (!rtwdev->scanning && !rtwvif->offchan) 4299 ieee80211_connection_loss(vif); 4300 else 4301 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 4302 return; 4303 case RTW89_BCN_FLTR_NOTIFY: 4304 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4305 break; 4306 case RTW89_BCN_FLTR_RSSI: 4307 if (event == RTW89_BCN_FLTR_RSSI_LOW) 4308 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 4309 else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 4310 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4311 else 4312 return; 4313 break; 4314 default: 4315 return; 4316 } 4317 4318 ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 4319 } 4320 4321 static void 4322 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4323 u32 len) 4324 { 4325 struct rtw89_vif *rtwvif; 4326 4327 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4328 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif, c2h); 4329 } 4330 4331 static void 4332 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4333 { 4334 rtw89_debug(rtwdev, RTW89_DBG_FW, 4335 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 4336 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 4337 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 4338 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 4339 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 4340 } 4341 4342 static void 4343 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4344 { 4345 rtw89_debug(rtwdev, RTW89_DBG_FW, 4346 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 4347 RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h->data), 4348 RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h->data), 4349 RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h->data), 4350 RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h->data), 4351 RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h->data)); 4352 } 4353 4354 static void 4355 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4356 { 4357 rtw89_info(rtwdev, "%*s", RTW89_GET_C2H_LOG_LEN(len), 4358 RTW89_GET_C2H_LOG_SRT_PRT(c2h->data)); 4359 } 4360 4361 static void 4362 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4363 { 4364 } 4365 4366 static void 4367 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4368 u32 len) 4369 { 4370 } 4371 4372 static void 4373 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4374 u32 len) 4375 { 4376 } 4377 4378 static void 4379 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4380 { 4381 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 4382 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 4383 4384 switch (func) { 4385 case H2C_FUNC_ADD_MCC: 4386 case H2C_FUNC_START_MCC: 4387 case H2C_FUNC_STOP_MCC: 4388 case H2C_FUNC_DEL_MCC_GROUP: 4389 case H2C_FUNC_RESET_MCC_GROUP: 4390 case H2C_FUNC_MCC_REQ_TSF: 4391 case H2C_FUNC_MCC_MACID_BITMAP: 4392 case H2C_FUNC_MCC_SYNC: 4393 case H2C_FUNC_MCC_SET_DURATION: 4394 break; 4395 default: 4396 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4397 "invalid MCC C2H RCV ACK: func %d\n", func); 4398 return; 4399 } 4400 4401 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4402 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 4403 } 4404 4405 static void 4406 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4407 { 4408 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 4409 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 4410 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 4411 struct rtw89_completion_data data = {}; 4412 unsigned int cond; 4413 bool next = false; 4414 4415 switch (func) { 4416 case H2C_FUNC_MCC_REQ_TSF: 4417 next = true; 4418 break; 4419 case H2C_FUNC_MCC_MACID_BITMAP: 4420 case H2C_FUNC_MCC_SYNC: 4421 case H2C_FUNC_MCC_SET_DURATION: 4422 break; 4423 case H2C_FUNC_ADD_MCC: 4424 case H2C_FUNC_START_MCC: 4425 case H2C_FUNC_STOP_MCC: 4426 case H2C_FUNC_DEL_MCC_GROUP: 4427 case H2C_FUNC_RESET_MCC_GROUP: 4428 default: 4429 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4430 "invalid MCC C2H REQ ACK: func %d\n", func); 4431 return; 4432 } 4433 4434 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4435 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 4436 group, func, retcode); 4437 4438 if (!retcode && next) 4439 return; 4440 4441 data.err = !!retcode; 4442 cond = RTW89_MCC_WAIT_COND(group, func); 4443 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4444 } 4445 4446 static void 4447 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4448 { 4449 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 4450 struct rtw89_completion_data data = {}; 4451 struct rtw89_mac_mcc_tsf_rpt *rpt; 4452 unsigned int cond; 4453 4454 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 4455 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 4456 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 4457 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 4458 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 4459 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 4460 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 4461 4462 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4463 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 4464 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 4465 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 4466 4467 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 4468 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4469 } 4470 4471 static void 4472 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4473 { 4474 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 4475 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 4476 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 4477 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 4478 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 4479 struct rtw89_completion_data data = {}; 4480 unsigned int cond; 4481 bool rsp = true; 4482 bool err; 4483 u8 func; 4484 4485 switch (status) { 4486 case RTW89_MAC_MCC_ADD_ROLE_OK: 4487 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 4488 func = H2C_FUNC_ADD_MCC; 4489 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 4490 break; 4491 case RTW89_MAC_MCC_START_GROUP_OK: 4492 case RTW89_MAC_MCC_START_GROUP_FAIL: 4493 func = H2C_FUNC_START_MCC; 4494 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 4495 break; 4496 case RTW89_MAC_MCC_STOP_GROUP_OK: 4497 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 4498 func = H2C_FUNC_STOP_MCC; 4499 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 4500 break; 4501 case RTW89_MAC_MCC_DEL_GROUP_OK: 4502 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 4503 func = H2C_FUNC_DEL_MCC_GROUP; 4504 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 4505 break; 4506 case RTW89_MAC_MCC_RESET_GROUP_OK: 4507 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 4508 func = H2C_FUNC_RESET_MCC_GROUP; 4509 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 4510 break; 4511 case RTW89_MAC_MCC_SWITCH_CH_OK: 4512 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 4513 case RTW89_MAC_MCC_TXNULL0_OK: 4514 case RTW89_MAC_MCC_TXNULL0_FAIL: 4515 case RTW89_MAC_MCC_TXNULL1_OK: 4516 case RTW89_MAC_MCC_TXNULL1_FAIL: 4517 case RTW89_MAC_MCC_SWITCH_EARLY: 4518 case RTW89_MAC_MCC_TBTT: 4519 case RTW89_MAC_MCC_DURATION_START: 4520 case RTW89_MAC_MCC_DURATION_END: 4521 rsp = false; 4522 break; 4523 default: 4524 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4525 "invalid MCC C2H STS RPT: status %d\n", status); 4526 return; 4527 } 4528 4529 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4530 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 4531 group, macid, status, (u64)tsf_high << 32 | tsf_low); 4532 4533 if (!rsp) 4534 return; 4535 4536 data.err = err; 4537 cond = RTW89_MCC_WAIT_COND(group, func); 4538 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4539 } 4540 4541 static 4542 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 4543 struct sk_buff *c2h, u32 len) = { 4544 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 4545 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 4546 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 4547 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 4548 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 4549 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 4550 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 4551 [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 4552 }; 4553 4554 static 4555 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 4556 struct sk_buff *c2h, u32 len) = { 4557 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 4558 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 4559 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 4560 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 4561 }; 4562 4563 static 4564 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 4565 struct sk_buff *c2h, u32 len) = { 4566 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 4567 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 4568 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 4569 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 4570 }; 4571 4572 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func) 4573 { 4574 switch (class) { 4575 default: 4576 return false; 4577 case RTW89_MAC_C2H_CLASS_MCC: 4578 return true; 4579 } 4580 } 4581 4582 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4583 u32 len, u8 class, u8 func) 4584 { 4585 void (*handler)(struct rtw89_dev *rtwdev, 4586 struct sk_buff *c2h, u32 len) = NULL; 4587 4588 switch (class) { 4589 case RTW89_MAC_C2H_CLASS_INFO: 4590 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 4591 handler = rtw89_mac_c2h_info_handler[func]; 4592 break; 4593 case RTW89_MAC_C2H_CLASS_OFLD: 4594 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 4595 handler = rtw89_mac_c2h_ofld_handler[func]; 4596 break; 4597 case RTW89_MAC_C2H_CLASS_MCC: 4598 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 4599 handler = rtw89_mac_c2h_mcc_handler[func]; 4600 break; 4601 case RTW89_MAC_C2H_CLASS_FWDBG: 4602 return; 4603 default: 4604 rtw89_info(rtwdev, "c2h class %d not support\n", class); 4605 return; 4606 } 4607 if (!handler) { 4608 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 4609 func); 4610 return; 4611 } 4612 handler(rtwdev, skb, len); 4613 } 4614 4615 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 4616 enum rtw89_phy_idx phy_idx, 4617 u32 reg_base, u32 *cr) 4618 { 4619 const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; 4620 enum rtw89_qta_mode mode = dle_mem->mode; 4621 u32 addr = rtw89_mac_reg_by_idx(reg_base, phy_idx); 4622 4623 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) { 4624 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 4625 addr); 4626 goto error; 4627 } 4628 4629 if (addr >= CMAC1_START_ADDR && addr <= CMAC1_END_ADDR) 4630 if (mode == RTW89_QTA_SCC) { 4631 rtw89_err(rtwdev, 4632 "[TXPWR] addr=0x%x but hw not enable\n", 4633 addr); 4634 goto error; 4635 } 4636 4637 *cr = addr; 4638 return true; 4639 4640 error: 4641 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 4642 addr, phy_idx); 4643 4644 return false; 4645 } 4646 EXPORT_SYMBOL(rtw89_mac_get_txpwr_cr); 4647 4648 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 4649 { 4650 u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx); 4651 int ret; 4652 4653 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4654 if (ret) 4655 return ret; 4656 4657 if (!enable) { 4658 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 4659 return 0; 4660 } 4661 4662 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 4663 B_AX_APP_MAC_INFO_RPT | 4664 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 4665 B_AX_PPDU_STAT_RPT_CRC32); 4666 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 4667 RTW89_PRPT_DEST_HOST); 4668 4669 return 0; 4670 } 4671 EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status); 4672 4673 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 4674 { 4675 #define MAC_AX_TIME_TH_SH 5 4676 #define MAC_AX_LEN_TH_SH 4 4677 #define MAC_AX_TIME_TH_MAX 255 4678 #define MAC_AX_LEN_TH_MAX 255 4679 #define MAC_AX_TIME_TH_DEF 88 4680 #define MAC_AX_LEN_TH_DEF 4080 4681 struct ieee80211_hw *hw = rtwdev->hw; 4682 u32 rts_threshold = hw->wiphy->rts_threshold; 4683 u32 time_th, len_th; 4684 u32 reg; 4685 4686 if (rts_threshold == (u32)-1) { 4687 time_th = MAC_AX_TIME_TH_DEF; 4688 len_th = MAC_AX_LEN_TH_DEF; 4689 } else { 4690 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 4691 len_th = rts_threshold; 4692 } 4693 4694 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 4695 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 4696 4697 reg = rtw89_mac_reg_by_idx(R_AX_AGG_LEN_HT_0, mac_idx); 4698 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 4699 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 4700 } 4701 4702 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 4703 { 4704 bool empty; 4705 int ret; 4706 4707 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4708 return; 4709 4710 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 4711 10000, 200000, false, rtwdev); 4712 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 4713 rtw89_info(rtwdev, "timed out to flush queues\n"); 4714 } 4715 4716 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 4717 { 4718 u8 val; 4719 u16 val16; 4720 u32 val32; 4721 int ret; 4722 4723 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 4724 if (rtwdev->chip->chip_id != RTL8851B) 4725 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 4726 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 4727 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 4728 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 4729 if (rtwdev->chip->chip_id != RTL8851B) 4730 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 4731 4732 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 4733 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 4734 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 4735 4736 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 4737 if (ret) { 4738 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 4739 return ret; 4740 } 4741 val32 = val32 & B_AX_WL_RX_CTRL; 4742 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 4743 if (ret) { 4744 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 4745 return ret; 4746 } 4747 4748 switch (coex->pta_mode) { 4749 case RTW89_MAC_AX_COEX_RTK_MODE: 4750 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4751 val &= ~B_AX_BTMODE_MASK; 4752 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 4753 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4754 4755 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 4756 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 4757 4758 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 4759 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 4760 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 4761 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 4762 break; 4763 case RTW89_MAC_AX_COEX_CSR_MODE: 4764 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4765 val &= ~B_AX_BTMODE_MASK; 4766 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 4767 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4768 4769 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 4770 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 4771 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 4772 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 4773 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 4774 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 4775 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 4776 val16 |= B_AX_ENHANCED_BT; 4777 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 4778 4779 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 4780 break; 4781 default: 4782 return -EINVAL; 4783 } 4784 4785 switch (coex->direction) { 4786 case RTW89_MAC_AX_COEX_INNER: 4787 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4788 val = (val & ~BIT(2)) | BIT(1); 4789 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4790 break; 4791 case RTW89_MAC_AX_COEX_OUTPUT: 4792 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4793 val = val | BIT(1) | BIT(0); 4794 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4795 break; 4796 case RTW89_MAC_AX_COEX_INPUT: 4797 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4798 val = val & ~(BIT(2) | BIT(1)); 4799 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4800 break; 4801 default: 4802 return -EINVAL; 4803 } 4804 4805 return 0; 4806 } 4807 EXPORT_SYMBOL(rtw89_mac_coex_init); 4808 4809 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 4810 const struct rtw89_mac_ax_coex *coex) 4811 { 4812 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 4813 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 4814 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 4815 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 4816 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 4817 4818 switch (coex->pta_mode) { 4819 case RTW89_MAC_AX_COEX_RTK_MODE: 4820 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4821 MAC_AX_RTK_MODE); 4822 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 4823 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 4824 break; 4825 case RTW89_MAC_AX_COEX_CSR_MODE: 4826 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4827 MAC_AX_CSR_MODE); 4828 break; 4829 default: 4830 return -EINVAL; 4831 } 4832 4833 return 0; 4834 } 4835 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 4836 4837 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 4838 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4839 { 4840 u32 val = 0, ret; 4841 4842 if (gnt_cfg->band[0].gnt_bt) 4843 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 4844 4845 if (gnt_cfg->band[0].gnt_bt_sw_en) 4846 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 4847 4848 if (gnt_cfg->band[0].gnt_wl) 4849 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 4850 4851 if (gnt_cfg->band[0].gnt_wl_sw_en) 4852 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 4853 4854 if (gnt_cfg->band[1].gnt_bt) 4855 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 4856 4857 if (gnt_cfg->band[1].gnt_bt_sw_en) 4858 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 4859 4860 if (gnt_cfg->band[1].gnt_wl) 4861 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 4862 4863 if (gnt_cfg->band[1].gnt_wl_sw_en) 4864 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 4865 4866 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 4867 if (ret) { 4868 rtw89_err(rtwdev, "Write LTE fail!\n"); 4869 return ret; 4870 } 4871 4872 return 0; 4873 } 4874 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 4875 4876 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 4877 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4878 { 4879 u32 val = 0; 4880 4881 if (gnt_cfg->band[0].gnt_bt) 4882 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 4883 B_AX_GNT_BT_TX_VAL; 4884 else 4885 val |= B_AX_WL_ACT_VAL; 4886 4887 if (gnt_cfg->band[0].gnt_bt_sw_en) 4888 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 4889 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 4890 4891 if (gnt_cfg->band[0].gnt_wl) 4892 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 4893 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 4894 4895 if (gnt_cfg->band[0].gnt_wl_sw_en) 4896 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 4897 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 4898 4899 if (gnt_cfg->band[1].gnt_bt) 4900 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 4901 B_AX_GNT_BT_TX_VAL; 4902 else 4903 val |= B_AX_WL_ACT_VAL; 4904 4905 if (gnt_cfg->band[1].gnt_bt_sw_en) 4906 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 4907 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 4908 4909 if (gnt_cfg->band[1].gnt_wl) 4910 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 4911 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 4912 4913 if (gnt_cfg->band[1].gnt_wl_sw_en) 4914 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 4915 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 4916 4917 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 4918 4919 return 0; 4920 } 4921 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 4922 4923 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 4924 { 4925 u32 reg; 4926 u16 val; 4927 int ret; 4928 4929 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 4930 if (ret) 4931 return ret; 4932 4933 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, plt->band); 4934 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 4935 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 4936 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 4937 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 4938 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 4939 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 4940 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 4941 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 4942 B_AX_PLT_EN; 4943 rtw89_write16(rtwdev, reg, val); 4944 4945 return 0; 4946 } 4947 4948 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 4949 { 4950 u32 fw_sb; 4951 4952 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 4953 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 4954 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 4955 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4956 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 4957 else 4958 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 4959 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 4960 val = B_AX_TOGGLE | 4961 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 4962 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 4963 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 4964 fsleep(1000); /* avoid BT FW loss information */ 4965 } 4966 4967 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 4968 { 4969 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 4970 } 4971 4972 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 4973 { 4974 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 4975 4976 val = wl ? val | BIT(2) : val & ~BIT(2); 4977 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 4978 4979 return 0; 4980 } 4981 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 4982 4983 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 4984 { 4985 struct rtw89_btc *btc = &rtwdev->btc; 4986 struct rtw89_btc_dm *dm = &btc->dm; 4987 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 4988 int i; 4989 4990 if (wl) 4991 return 0; 4992 4993 for (i = 0; i < RTW89_PHY_MAX; i++) { 4994 g[i].gnt_bt_sw_en = 1; 4995 g[i].gnt_bt = 1; 4996 g[i].gnt_wl_sw_en = 1; 4997 g[i].gnt_wl = 0; 4998 } 4999 5000 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 5001 } 5002 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 5003 5004 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 5005 { 5006 const struct rtw89_chip_info *chip = rtwdev->chip; 5007 u8 val = 0; 5008 5009 if (chip->chip_id == RTL8852C) 5010 return false; 5011 else if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) 5012 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 5013 B_AX_LTE_MUX_CTRL_PATH >> 24); 5014 5015 return !!val; 5016 } 5017 5018 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 5019 { 5020 u32 reg; 5021 u16 cnt; 5022 5023 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, band); 5024 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 5025 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 5026 5027 return cnt; 5028 } 5029 5030 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 5031 bool keep) 5032 { 5033 u32 reg; 5034 5035 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 5036 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 5037 if (keep) { 5038 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5039 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5040 BFRP_RX_STANDBY_TIMER_KEEP); 5041 } else { 5042 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5043 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5044 BFRP_RX_STANDBY_TIMER_RELEASE); 5045 } 5046 } 5047 5048 static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 5049 { 5050 u32 reg; 5051 u32 mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 5052 B_AX_BFMEE_HE_NDPA_EN; 5053 5054 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 5055 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 5056 if (en) { 5057 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5058 rtw89_write32_set(rtwdev, reg, mask); 5059 } else { 5060 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5061 rtw89_write32_clr(rtwdev, reg, mask); 5062 } 5063 } 5064 5065 static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx) 5066 { 5067 u32 reg; 5068 u32 val32; 5069 int ret; 5070 5071 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5072 if (ret) 5073 return ret; 5074 5075 /* AP mode set tx gid to 63 */ 5076 /* STA mode set tx gid to 0(default) */ 5077 reg = rtw89_mac_reg_by_idx(R_AX_BFMER_CTRL_0, mac_idx); 5078 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 5079 5080 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 5081 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 5082 5083 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 5084 val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 5085 rtw89_write32(rtwdev, reg, val32); 5086 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 5087 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 5088 5089 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5090 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 5091 B_AX_BFMEE_USE_NSTS | 5092 B_AX_BFMEE_CSI_GID_SEL | 5093 B_AX_BFMEE_CSI_FORCE_RETE_EN); 5094 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 5095 rtw89_write32(rtwdev, reg, 5096 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 5097 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 5098 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 5099 5100 reg = rtw89_mac_reg_by_idx(R_AX_CSIRPT_OPTION, mac_idx); 5101 rtw89_write32_set(rtwdev, reg, 5102 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 5103 5104 return 0; 5105 } 5106 5107 static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, 5108 struct ieee80211_vif *vif, 5109 struct ieee80211_sta *sta) 5110 { 5111 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5112 u8 mac_idx = rtwvif->mac_idx; 5113 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 5114 u8 port_sel = rtwvif->port; 5115 u8 sound_dim = 3, t; 5116 u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 5117 u32 reg; 5118 u16 val; 5119 int ret; 5120 5121 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5122 if (ret) 5123 return ret; 5124 5125 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5126 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 5127 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 5128 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 5129 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 5130 phy_cap[5]); 5131 sound_dim = min(sound_dim, t); 5132 } 5133 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5134 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 5135 ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 5136 stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 5137 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 5138 sta->deflink.vht_cap.cap); 5139 sound_dim = min(sound_dim, t); 5140 } 5141 nc = min(nc, sound_dim); 5142 nr = min(nr, sound_dim); 5143 5144 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5145 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5146 5147 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 5148 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 5149 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 5150 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 5151 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 5152 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 5153 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 5154 5155 if (port_sel == 0) 5156 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5157 else 5158 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 5159 5160 rtw89_write16(rtwdev, reg, val); 5161 5162 return 0; 5163 } 5164 5165 static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev, 5166 struct ieee80211_vif *vif, 5167 struct ieee80211_sta *sta) 5168 { 5169 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5170 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 5171 u32 reg; 5172 u8 mac_idx = rtwvif->mac_idx; 5173 int ret; 5174 5175 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5176 if (ret) 5177 return ret; 5178 5179 if (sta->deflink.he_cap.has_he) { 5180 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 5181 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 5182 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 5183 } 5184 if (sta->deflink.vht_cap.vht_supported) { 5185 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 5186 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 5187 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 5188 } 5189 if (sta->deflink.ht_cap.ht_supported) { 5190 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 5191 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 5192 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 5193 } 5194 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5195 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5196 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 5197 rtw89_write32(rtwdev, 5198 rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 5199 rrsc); 5200 5201 return 0; 5202 } 5203 5204 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5205 struct ieee80211_sta *sta) 5206 { 5207 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5208 5209 if (rtw89_sta_has_beamformer_cap(sta)) { 5210 rtw89_debug(rtwdev, RTW89_DBG_BF, 5211 "initialize bfee for new association\n"); 5212 rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx); 5213 rtw89_mac_set_csi_para_reg(rtwdev, vif, sta); 5214 rtw89_mac_csi_rrsc(rtwdev, vif, sta); 5215 } 5216 } 5217 5218 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5219 struct ieee80211_sta *sta) 5220 { 5221 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5222 5223 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 5224 } 5225 5226 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5227 struct ieee80211_bss_conf *conf) 5228 { 5229 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5230 u8 mac_idx = rtwvif->mac_idx; 5231 __le32 *p; 5232 5233 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 5234 5235 p = (__le32 *)conf->mu_group.membership; 5236 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx), 5237 le32_to_cpu(p[0])); 5238 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx), 5239 le32_to_cpu(p[1])); 5240 5241 p = (__le32 *)conf->mu_group.position; 5242 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx), 5243 le32_to_cpu(p[0])); 5244 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx), 5245 le32_to_cpu(p[1])); 5246 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx), 5247 le32_to_cpu(p[2])); 5248 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx), 5249 le32_to_cpu(p[3])); 5250 } 5251 5252 struct rtw89_mac_bf_monitor_iter_data { 5253 struct rtw89_dev *rtwdev; 5254 struct ieee80211_sta *down_sta; 5255 int count; 5256 }; 5257 5258 static 5259 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 5260 { 5261 struct rtw89_mac_bf_monitor_iter_data *iter_data = 5262 (struct rtw89_mac_bf_monitor_iter_data *)data; 5263 struct ieee80211_sta *down_sta = iter_data->down_sta; 5264 int *count = &iter_data->count; 5265 5266 if (down_sta == sta) 5267 return; 5268 5269 if (rtw89_sta_has_beamformer_cap(sta)) 5270 (*count)++; 5271 } 5272 5273 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 5274 struct ieee80211_sta *sta, bool disconnect) 5275 { 5276 struct rtw89_mac_bf_monitor_iter_data data; 5277 5278 data.rtwdev = rtwdev; 5279 data.down_sta = disconnect ? sta : NULL; 5280 data.count = 0; 5281 ieee80211_iterate_stations_atomic(rtwdev->hw, 5282 rtw89_mac_bf_monitor_calc_iter, 5283 &data); 5284 5285 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 5286 if (data.count) 5287 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5288 else 5289 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5290 } 5291 5292 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 5293 { 5294 struct rtw89_traffic_stats *stats = &rtwdev->stats; 5295 struct rtw89_vif *rtwvif; 5296 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 5297 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5298 bool keep_timer = true; 5299 bool old_keep_timer; 5300 5301 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5302 5303 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 5304 keep_timer = false; 5305 5306 if (keep_timer != old_keep_timer) { 5307 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5308 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx, 5309 keep_timer); 5310 } 5311 5312 if (en == old) 5313 return; 5314 5315 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5316 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 5317 } 5318 5319 static int 5320 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5321 u32 tx_time) 5322 { 5323 #define MAC_AX_DFLT_TX_TIME 5280 5324 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5325 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 5326 u32 reg; 5327 int ret = 0; 5328 5329 if (rtwsta->cctl_tx_time) { 5330 rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 5331 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5332 } else { 5333 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5334 if (ret) { 5335 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 5336 return ret; 5337 } 5338 5339 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 5340 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 5341 max_tx_time >> 5); 5342 } 5343 5344 return ret; 5345 } 5346 5347 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5348 bool resume, u32 tx_time) 5349 { 5350 int ret = 0; 5351 5352 if (!resume) { 5353 rtwsta->cctl_tx_time = true; 5354 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5355 } else { 5356 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5357 rtwsta->cctl_tx_time = false; 5358 } 5359 5360 return ret; 5361 } 5362 5363 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5364 u32 *tx_time) 5365 { 5366 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5367 u32 reg; 5368 int ret = 0; 5369 5370 if (rtwsta->cctl_tx_time) { 5371 *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 5372 } else { 5373 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5374 if (ret) { 5375 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 5376 return ret; 5377 } 5378 5379 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 5380 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 5381 } 5382 5383 return ret; 5384 } 5385 5386 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 5387 struct rtw89_sta *rtwsta, 5388 bool resume, u8 tx_retry) 5389 { 5390 int ret = 0; 5391 5392 rtwsta->data_tx_cnt_lmt = tx_retry; 5393 5394 if (!resume) { 5395 rtwsta->cctl_tx_retry_limit = true; 5396 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5397 } else { 5398 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5399 rtwsta->cctl_tx_retry_limit = false; 5400 } 5401 5402 return ret; 5403 } 5404 5405 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 5406 struct rtw89_sta *rtwsta, u8 *tx_retry) 5407 { 5408 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5409 u32 reg; 5410 int ret = 0; 5411 5412 if (rtwsta->cctl_tx_retry_limit) { 5413 *tx_retry = rtwsta->data_tx_cnt_lmt; 5414 } else { 5415 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5416 if (ret) { 5417 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 5418 return ret; 5419 } 5420 5421 reg = rtw89_mac_reg_by_idx(R_AX_TXCNT, mac_idx); 5422 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 5423 } 5424 5425 return ret; 5426 } 5427 5428 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 5429 struct rtw89_vif *rtwvif, bool en) 5430 { 5431 u8 mac_idx = rtwvif->mac_idx; 5432 u16 set = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0; 5433 u32 reg; 5434 u32 ret; 5435 5436 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5437 if (ret) 5438 return ret; 5439 5440 reg = rtw89_mac_reg_by_idx(R_AX_MUEDCA_EN, mac_idx); 5441 if (en) 5442 rtw89_write16_set(rtwdev, reg, set); 5443 else 5444 rtw89_write16_clr(rtwdev, reg, set); 5445 5446 return 0; 5447 } 5448 5449 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 5450 { 5451 u32 val32; 5452 int ret; 5453 5454 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 5455 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 5456 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 5457 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 5458 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 5459 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 5460 5461 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 5462 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 5463 if (ret) { 5464 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 5465 offset, val, mask); 5466 return ret; 5467 } 5468 5469 return 0; 5470 } 5471 EXPORT_SYMBOL(rtw89_mac_write_xtal_si); 5472 5473 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 5474 { 5475 u32 val32; 5476 int ret; 5477 5478 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 5479 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 5480 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 5481 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 5482 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 5483 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 5484 5485 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 5486 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 5487 if (ret) { 5488 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 5489 return ret; 5490 } 5491 5492 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 5493 5494 return 0; 5495 } 5496 EXPORT_SYMBOL(rtw89_mac_read_xtal_si); 5497 5498 static 5499 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 5500 { 5501 static const enum rtw89_pkt_drop_sel sels[] = { 5502 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 5503 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 5504 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 5505 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 5506 }; 5507 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5508 struct rtw89_pkt_drop_params params = {0}; 5509 int i; 5510 5511 params.mac_band = RTW89_MAC_0; 5512 params.macid = rtwsta->mac_id; 5513 params.port = rtwvif->port; 5514 params.mbssid = 0; 5515 params.tf_trs = rtwvif->trigger; 5516 5517 for (i = 0; i < ARRAY_SIZE(sels); i++) { 5518 params.sel = sels[i]; 5519 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 5520 } 5521 } 5522 5523 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 5524 { 5525 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 5526 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5527 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 5528 struct rtw89_vif *target = data; 5529 5530 if (rtwvif != target) 5531 return; 5532 5533 rtw89_mac_pkt_drop_sta(rtwdev, rtwsta); 5534 } 5535 5536 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 5537 { 5538 ieee80211_iterate_stations_atomic(rtwdev->hw, 5539 rtw89_mac_pkt_drop_vif_iter, 5540 rtwvif); 5541 } 5542 5543 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 5544 enum rtw89_mac_idx band) 5545 { 5546 struct rtw89_pkt_drop_params params = {0}; 5547 bool empty; 5548 int i, ret = 0, try_cnt = 3; 5549 5550 params.mac_band = band; 5551 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 5552 5553 for (i = 0; i < try_cnt; i++) { 5554 ret = read_poll_timeout(mac_is_txq_empty, empty, empty, 50, 5555 50000, false, rtwdev); 5556 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 5557 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 5558 else 5559 return 0; 5560 } 5561 return ret; 5562 } 5563