1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "fw.h" 9 #include "mac.h" 10 #include "pci.h" 11 #include "ps.h" 12 #include "reg.h" 13 #include "util.h" 14 15 const u32 rtw89_mac_mem_base_addrs[RTW89_MAC_MEM_NUM] = { 16 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 17 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 18 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 19 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 20 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 21 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 22 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 23 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 24 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 25 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 26 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 28 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 29 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 30 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 31 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 32 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 33 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 34 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 35 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 36 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 37 }; 38 39 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 40 u32 val, enum rtw89_mac_mem_sel sel) 41 { 42 u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; 43 44 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); 45 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, val); 46 } 47 48 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 49 enum rtw89_mac_mem_sel sel) 50 { 51 u32 addr = rtw89_mac_mem_base_addrs[sel] + offset; 52 53 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr); 54 return rtw89_read32(rtwdev, R_AX_INDIR_ACCESS_ENTRY); 55 } 56 57 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx, 58 enum rtw89_mac_hwmod_sel sel) 59 { 60 u32 val, r_val; 61 62 if (sel == RTW89_DMAC_SEL) { 63 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 64 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 65 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 66 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 67 val = B_AX_CMAC_EN; 68 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 69 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 70 val = B_AX_CMAC1_FEN; 71 } else { 72 return -EINVAL; 73 } 74 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 75 (val & r_val) != val) 76 return -EFAULT; 77 78 return 0; 79 } 80 81 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 82 { 83 u8 lte_ctrl; 84 int ret; 85 86 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 87 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 88 if (ret) 89 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 90 91 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 92 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 93 94 return ret; 95 } 96 97 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 98 { 99 u8 lte_ctrl; 100 int ret; 101 102 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 103 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 104 if (ret) 105 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 106 107 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 108 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 109 110 return ret; 111 } 112 113 static 114 int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 115 { 116 u32 ctrl_reg, data_reg, ctrl_data; 117 u32 val; 118 int ret; 119 120 switch (ctrl->type) { 121 case DLE_CTRL_TYPE_WDE: 122 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 123 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 124 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 125 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 126 B_AX_WDE_DFI_ACTIVE; 127 break; 128 case DLE_CTRL_TYPE_PLE: 129 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 130 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 131 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 132 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 133 B_AX_PLE_DFI_ACTIVE; 134 break; 135 default: 136 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 137 return -EINVAL; 138 } 139 140 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 141 142 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 143 1, 1000, false, rtwdev, ctrl_reg); 144 if (ret) { 145 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 146 ctrl_reg, ctrl_data); 147 return ret; 148 } 149 150 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 151 return 0; 152 } 153 154 static int dle_dfi_quota(struct rtw89_dev *rtwdev, 155 struct rtw89_mac_dle_dfi_quota *quota) 156 { 157 struct rtw89_mac_dle_dfi_ctrl ctrl; 158 int ret; 159 160 ctrl.type = quota->dle_type; 161 ctrl.target = DLE_DFI_TYPE_QUOTA; 162 ctrl.addr = quota->qtaid; 163 ret = dle_dfi_ctrl(rtwdev, &ctrl); 164 if (ret) { 165 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 166 return ret; 167 } 168 169 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 170 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 171 return 0; 172 } 173 174 static int dle_dfi_qempty(struct rtw89_dev *rtwdev, 175 struct rtw89_mac_dle_dfi_qempty *qempty) 176 { 177 struct rtw89_mac_dle_dfi_ctrl ctrl; 178 u32 ret; 179 180 ctrl.type = qempty->dle_type; 181 ctrl.target = DLE_DFI_TYPE_QEMPTY; 182 ctrl.addr = qempty->grpsel; 183 ret = dle_dfi_ctrl(rtwdev, &ctrl); 184 if (ret) { 185 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret); 186 return ret; 187 } 188 189 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 190 return 0; 191 } 192 193 static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev) 194 { 195 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 196 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 197 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 198 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 199 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 200 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 201 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 202 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 203 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 204 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 205 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 206 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 207 } 208 209 static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev) 210 { 211 struct rtw89_mac_dle_dfi_qempty qempty; 212 struct rtw89_mac_dle_dfi_quota quota; 213 struct rtw89_mac_dle_dfi_ctrl ctrl; 214 u32 val, not_empty, i; 215 int ret; 216 217 qempty.dle_type = DLE_CTRL_TYPE_PLE; 218 qempty.grpsel = 0; 219 qempty.qempty = ~(u32)0; 220 ret = dle_dfi_qempty(rtwdev, &qempty); 221 if (ret) 222 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 223 else 224 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 225 226 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 227 if (!(not_empty & BIT(0))) 228 continue; 229 ctrl.type = DLE_CTRL_TYPE_PLE; 230 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 231 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 232 FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i); 233 ret = dle_dfi_ctrl(rtwdev, &ctrl); 234 if (ret) 235 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 236 else 237 rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i, 238 FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK, 239 ctrl.out_data)); 240 } 241 242 quota.dle_type = DLE_CTRL_TYPE_PLE; 243 quota.qtaid = 6; 244 ret = dle_dfi_quota(rtwdev, "a); 245 if (ret) 246 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 247 else 248 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 249 quota.rsv_pgnum, quota.use_pgnum); 250 251 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 252 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n", 253 FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val)); 254 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n", 255 FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val)); 256 257 dump_err_status_dispatcher(rtwdev); 258 } 259 260 static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 261 enum mac_ax_err_info err) 262 { 263 u32 dbg, event; 264 265 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 266 event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg); 267 268 switch (event) { 269 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 270 rtw89_info(rtwdev, "quota lost!\n"); 271 rtw89_mac_dump_qta_lost(rtwdev); 272 break; 273 default: 274 break; 275 } 276 } 277 278 static void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 279 { 280 const struct rtw89_chip_info *chip = rtwdev->chip; 281 u32 dmac_err; 282 int i, ret; 283 284 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 285 if (ret) { 286 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 287 return; 288 } 289 290 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 291 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 292 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 293 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 294 295 if (dmac_err) { 296 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 298 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 299 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 300 if (chip->chip_id == RTL8852C) { 301 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 302 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 303 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 304 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 305 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 306 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 307 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 308 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 309 } 310 } 311 312 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 313 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 314 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 315 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 316 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 317 if (chip->chip_id == RTL8852C) 318 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 319 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 320 else 321 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 322 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 323 } 324 325 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 326 if (chip->chip_id == RTL8852C) { 327 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 328 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 329 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 330 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 331 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 332 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 333 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 334 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 335 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 336 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 337 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 338 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 339 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 340 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 341 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 343 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 344 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 345 346 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 347 B_AX_DBG_SEL0, 0x8B); 348 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 349 B_AX_DBG_SEL1, 0x8B); 350 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 351 B_AX_SEL_0XC0_MASK, 1); 352 for (i = 0; i < 0x10; i++) { 353 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 354 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 355 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 356 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 357 } 358 } else { 359 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 360 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 361 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 362 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 363 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 364 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 365 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 366 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 367 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 368 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 369 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 370 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 371 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 372 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 373 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 374 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 375 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 376 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 377 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 378 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 379 } 380 } 381 382 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 383 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 384 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 385 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 386 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 387 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 388 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 389 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 390 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 391 } 392 393 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 394 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 395 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 396 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 397 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 398 } 399 400 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 401 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 402 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 403 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 404 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 405 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 406 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 407 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 408 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 409 } 410 411 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 412 if (chip->chip_id == RTL8852C) { 413 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 414 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 415 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 416 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 417 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 418 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 419 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 420 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 421 } else { 422 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 423 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 424 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 425 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 426 } 427 } 428 429 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 430 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 431 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 432 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 433 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 434 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 435 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 436 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 437 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 438 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 439 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 440 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 441 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 442 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 443 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 444 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 445 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 446 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 447 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 448 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 449 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 450 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 451 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 452 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 453 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 454 if (chip->chip_id == RTL8852C) { 455 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 456 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 457 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 458 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 459 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 460 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 461 } else { 462 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 463 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 464 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 465 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 466 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 467 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 468 } 469 } 470 471 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 472 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 473 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 474 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 475 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 476 } 477 478 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 479 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 480 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 481 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 482 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 483 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 484 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 485 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 486 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 487 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 488 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 489 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 490 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 491 } 492 493 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 494 if (chip->chip_id == RTL8852C) { 495 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 496 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 497 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 498 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 499 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 500 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 501 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 502 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 503 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 504 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 505 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 506 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 507 } else { 508 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 509 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 510 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 511 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 512 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 513 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 514 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 515 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 516 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 517 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 518 } 519 } 520 521 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 522 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 523 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 524 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 525 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 526 } 527 } 528 529 static void rtw89_mac_dump_cmac_err_status(struct rtw89_dev *rtwdev, 530 u8 band) 531 { 532 const struct rtw89_chip_info *chip = rtwdev->chip; 533 u32 offset = 0; 534 u32 cmac_err; 535 int ret; 536 537 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 538 if (ret) { 539 if (band) 540 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 541 else 542 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 543 return; 544 } 545 546 if (band) 547 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 548 549 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 550 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 551 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 552 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 553 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 554 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 555 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 556 557 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 558 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 559 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 560 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 561 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 562 } 563 564 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 565 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 566 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 567 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 568 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 569 } 570 571 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 572 if (chip->chip_id == RTL8852C) { 573 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 574 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 575 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 576 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 577 } else { 578 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 579 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 580 } 581 } 582 583 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 584 if (chip->chip_id == RTL8852C) { 585 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 586 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 587 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 588 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 589 } else { 590 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 591 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 592 } 593 } 594 595 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 596 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 597 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 598 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 599 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 600 } 601 602 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 603 if (chip->chip_id == RTL8852C) { 604 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 605 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 606 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 607 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 608 } else { 609 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 610 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 611 } 612 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 613 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 614 } 615 616 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 617 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 618 } 619 620 static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev, 621 enum mac_ax_err_info err) 622 { 623 if (err != MAC_AX_ERR_L1_ERR_DMAC && 624 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 625 err != MAC_AX_ERR_L0_ERR_CMAC0 && 626 err != MAC_AX_ERR_L0_ERR_CMAC1 && 627 err != MAC_AX_ERR_RXI300) 628 return; 629 630 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 631 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 632 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 633 634 rtw89_mac_dump_dmac_err_status(rtwdev); 635 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_0); 636 if (rtwdev->dbcc_en) 637 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_1); 638 639 rtwdev->hci.ops->dump_err_status(rtwdev); 640 641 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 642 rtw89_mac_dump_l0_to_l1(rtwdev, err); 643 644 rtw89_info(rtwdev, "<---\n"); 645 } 646 647 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 648 { 649 struct rtw89_ser *ser = &rtwdev->ser; 650 u32 dmac_err, imr, isr; 651 int ret; 652 653 if (rtwdev->chip->chip_id == RTL8852C) { 654 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 655 if (ret) 656 return true; 657 658 if (err == MAC_AX_ERR_L1_ERR_DMAC) { 659 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 660 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 661 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 662 663 if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 664 ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 665 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 666 return true; 667 } 668 } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 669 if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 670 return true; 671 } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 672 if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 673 return true; 674 } 675 } 676 677 return false; 678 } 679 680 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 681 { 682 u32 err, err_scnr; 683 int ret; 684 685 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 686 false, rtwdev, R_AX_HALT_C2H_CTRL); 687 if (ret) { 688 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 689 return ret; 690 } 691 692 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 693 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 694 695 err_scnr = RTW89_ERROR_SCENARIO(err); 696 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 697 err = MAC_AX_ERR_CPU_EXCEPTION; 698 else if (err_scnr == RTW89_WCPU_ASSERTION) 699 err = MAC_AX_ERR_ASSERTION; 700 else if (err_scnr == RTW89_RXI300_ERROR) 701 err = MAC_AX_ERR_RXI300; 702 703 if (rtw89_mac_suppress_log(rtwdev, err)) 704 return err; 705 706 rtw89_fw_st_dbg_dump(rtwdev); 707 rtw89_mac_dump_err_status(rtwdev, err); 708 709 return err; 710 } 711 EXPORT_SYMBOL(rtw89_mac_get_err_status); 712 713 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 714 { 715 struct rtw89_ser *ser = &rtwdev->ser; 716 u32 halt; 717 int ret = 0; 718 719 if (err > MAC_AX_SET_ERR_MAX) { 720 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 721 return -EINVAL; 722 } 723 724 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 725 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 726 if (ret) { 727 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 728 return -EFAULT; 729 } 730 731 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 732 733 if (ser->prehandle_l1 && 734 (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN)) 735 return 0; 736 737 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 738 739 return 0; 740 } 741 EXPORT_SYMBOL(rtw89_mac_set_err_status); 742 743 static int hfc_reset_param(struct rtw89_dev *rtwdev) 744 { 745 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 746 struct rtw89_hfc_param_ini param_ini = {NULL}; 747 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 748 749 switch (rtwdev->hci.type) { 750 case RTW89_HCI_TYPE_PCIE: 751 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 752 param->en = 0; 753 break; 754 default: 755 return -EINVAL; 756 } 757 758 if (param_ini.pub_cfg) 759 param->pub_cfg = *param_ini.pub_cfg; 760 761 if (param_ini.prec_cfg) { 762 param->prec_cfg = *param_ini.prec_cfg; 763 rtwdev->hal.sw_amsdu_max_size = 764 param->prec_cfg.wp_ch07_prec * HFC_PAGE_UNIT; 765 } 766 767 if (param_ini.ch_cfg) 768 param->ch_cfg = param_ini.ch_cfg; 769 770 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 771 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 772 param->mode = param_ini.mode; 773 774 return 0; 775 } 776 777 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 778 { 779 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 780 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 781 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 782 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 783 784 if (ch >= RTW89_DMA_CH_NUM) 785 return -EINVAL; 786 787 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 788 ch_cfg[ch].max > pub_cfg->pub_max) 789 return -EINVAL; 790 if (ch_cfg[ch].grp >= grp_num) 791 return -EINVAL; 792 793 return 0; 794 } 795 796 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 797 { 798 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 799 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 800 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 801 802 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 803 if (rtwdev->chip->chip_id == RTL8852A) 804 return 0; 805 else 806 return -EFAULT; 807 } 808 809 return 0; 810 } 811 812 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 813 { 814 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 815 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 816 817 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 818 return -EFAULT; 819 820 return 0; 821 } 822 823 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 824 { 825 const struct rtw89_chip_info *chip = rtwdev->chip; 826 const struct rtw89_page_regs *regs = chip->page_regs; 827 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 828 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 829 int ret = 0; 830 u32 val = 0; 831 832 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 833 if (ret) 834 return ret; 835 836 ret = hfc_ch_cfg_chk(rtwdev, ch); 837 if (ret) 838 return ret; 839 840 if (ch > RTW89_DMA_B1HI) 841 return -EINVAL; 842 843 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 844 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 845 (cfg[ch].grp ? B_AX_GRP : 0); 846 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 847 848 return 0; 849 } 850 851 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 852 { 853 const struct rtw89_chip_info *chip = rtwdev->chip; 854 const struct rtw89_page_regs *regs = chip->page_regs; 855 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 856 struct rtw89_hfc_ch_info *info = param->ch_info; 857 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 858 u32 val; 859 u32 ret; 860 861 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 862 if (ret) 863 return ret; 864 865 if (ch > RTW89_DMA_H2C) 866 return -EINVAL; 867 868 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 869 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 870 if (ch < RTW89_DMA_H2C) 871 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 872 else 873 info[ch].used = cfg[ch].min - info[ch].aval; 874 875 return 0; 876 } 877 878 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 879 { 880 const struct rtw89_chip_info *chip = rtwdev->chip; 881 const struct rtw89_page_regs *regs = chip->page_regs; 882 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 883 u32 val; 884 int ret; 885 886 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 887 if (ret) 888 return ret; 889 890 ret = hfc_pub_cfg_chk(rtwdev); 891 if (ret) 892 return ret; 893 894 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 895 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 896 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 897 898 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 899 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 900 901 return 0; 902 } 903 904 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 905 { 906 const struct rtw89_chip_info *chip = rtwdev->chip; 907 const struct rtw89_page_regs *regs = chip->page_regs; 908 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 909 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 910 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 911 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 912 u32 val; 913 int ret; 914 915 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 916 if (ret) 917 return ret; 918 919 val = rtw89_read32(rtwdev, regs->pub_page_info1); 920 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 921 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 922 val = rtw89_read32(rtwdev, regs->pub_page_info3); 923 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 924 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 925 info->pub_aval = 926 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 927 B_AX_PUB_AVAL_PG_MASK); 928 info->wp_aval = 929 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 930 B_AX_WP_AVAL_PG_MASK); 931 932 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 933 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 934 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 935 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 936 prec_cfg->ch011_full_cond = 937 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 938 prec_cfg->h2c_full_cond = 939 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 940 prec_cfg->wp_ch07_full_cond = 941 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 942 prec_cfg->wp_ch811_full_cond = 943 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 944 945 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 946 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 947 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 948 949 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 950 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 951 952 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 953 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 954 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 955 956 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 957 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 958 959 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 960 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 961 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 962 963 ret = hfc_pub_info_chk(rtwdev); 964 if (param->en && ret) 965 return ret; 966 967 return 0; 968 } 969 970 static void hfc_h2c_cfg(struct rtw89_dev *rtwdev) 971 { 972 const struct rtw89_chip_info *chip = rtwdev->chip; 973 const struct rtw89_page_regs *regs = chip->page_regs; 974 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 975 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 976 u32 val; 977 978 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 979 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 980 981 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 982 B_AX_HCI_FC_CH12_FULL_COND_MASK, 983 prec_cfg->h2c_full_cond); 984 } 985 986 static void hfc_mix_cfg(struct rtw89_dev *rtwdev) 987 { 988 const struct rtw89_chip_info *chip = rtwdev->chip; 989 const struct rtw89_page_regs *regs = chip->page_regs; 990 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 991 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 992 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 993 u32 val; 994 995 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 996 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 997 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 998 999 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 1000 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1001 1002 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1003 B_AX_PREC_PAGE_WP_CH07_MASK) | 1004 u32_encode_bits(prec_cfg->wp_ch811_prec, 1005 B_AX_PREC_PAGE_WP_CH811_MASK); 1006 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1007 1008 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1009 param->mode, B_AX_HCI_FC_MODE_MASK); 1010 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1011 B_AX_HCI_FC_WD_FULL_COND_MASK); 1012 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1013 B_AX_HCI_FC_CH12_FULL_COND_MASK); 1014 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1015 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1016 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1017 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1018 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1019 } 1020 1021 static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1022 { 1023 const struct rtw89_chip_info *chip = rtwdev->chip; 1024 const struct rtw89_page_regs *regs = chip->page_regs; 1025 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1026 u32 val; 1027 1028 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1029 param->en = en; 1030 param->h2c_en = h2c_en; 1031 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1032 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1033 (val & ~B_AX_HCI_FC_CH12_EN); 1034 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1035 } 1036 1037 static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1038 { 1039 const struct rtw89_chip_info *chip = rtwdev->chip; 1040 u32 dma_ch_mask = chip->dma_ch_mask; 1041 u8 ch; 1042 u32 ret = 0; 1043 1044 if (reset) 1045 ret = hfc_reset_param(rtwdev); 1046 if (ret) 1047 return ret; 1048 1049 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1050 if (ret) 1051 return ret; 1052 1053 hfc_func_en(rtwdev, false, false); 1054 1055 if (!en && h2c_en) { 1056 hfc_h2c_cfg(rtwdev); 1057 hfc_func_en(rtwdev, en, h2c_en); 1058 return ret; 1059 } 1060 1061 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1062 if (dma_ch_mask & BIT(ch)) 1063 continue; 1064 ret = hfc_ch_ctrl(rtwdev, ch); 1065 if (ret) 1066 return ret; 1067 } 1068 1069 ret = hfc_pub_ctrl(rtwdev); 1070 if (ret) 1071 return ret; 1072 1073 hfc_mix_cfg(rtwdev); 1074 if (en || h2c_en) { 1075 hfc_func_en(rtwdev, en, h2c_en); 1076 udelay(10); 1077 } 1078 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1079 if (dma_ch_mask & BIT(ch)) 1080 continue; 1081 ret = hfc_upd_ch_info(rtwdev, ch); 1082 if (ret) 1083 return ret; 1084 } 1085 ret = hfc_upd_mix_info(rtwdev); 1086 1087 return ret; 1088 } 1089 1090 #define PWR_POLL_CNT 2000 1091 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1092 const struct rtw89_pwr_cfg *cfg) 1093 { 1094 u8 val = 0; 1095 int ret; 1096 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1097 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1098 1099 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1100 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1101 1102 if (!ret) 1103 return 0; 1104 1105 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1106 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1107 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1108 1109 return -EBUSY; 1110 } 1111 1112 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1113 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1114 { 1115 const struct rtw89_pwr_cfg *cur_cfg; 1116 u32 addr; 1117 u8 val; 1118 1119 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1120 if (!(cur_cfg->intf_msk & intf_msk) || 1121 !(cur_cfg->cv_msk & cv_msk)) 1122 continue; 1123 1124 switch (cur_cfg->cmd) { 1125 case PWR_CMD_WRITE: 1126 addr = cur_cfg->addr; 1127 1128 if (cur_cfg->base == PWR_BASE_SDIO) 1129 addr |= SDIO_LOCAL_BASE_ADDR; 1130 1131 val = rtw89_read8(rtwdev, addr); 1132 val &= ~(cur_cfg->msk); 1133 val |= (cur_cfg->val & cur_cfg->msk); 1134 1135 rtw89_write8(rtwdev, addr, val); 1136 break; 1137 case PWR_CMD_POLL: 1138 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1139 return -EBUSY; 1140 break; 1141 case PWR_CMD_DELAY: 1142 if (cur_cfg->val == PWR_DELAY_US) 1143 udelay(cur_cfg->addr); 1144 else 1145 fsleep(cur_cfg->addr * 1000); 1146 break; 1147 default: 1148 return -EINVAL; 1149 } 1150 } 1151 1152 return 0; 1153 } 1154 1155 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1156 const struct rtw89_pwr_cfg * const *cfg_seq) 1157 { 1158 int ret; 1159 1160 for (; *cfg_seq; cfg_seq++) { 1161 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1162 PWR_INTF_MSK_PCIE, *cfg_seq); 1163 if (ret) 1164 return -EBUSY; 1165 } 1166 1167 return 0; 1168 } 1169 1170 static enum rtw89_rpwm_req_pwr_state 1171 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1172 { 1173 enum rtw89_rpwm_req_pwr_state state; 1174 1175 switch (rtwdev->ps_mode) { 1176 case RTW89_PS_MODE_RFOFF: 1177 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1178 break; 1179 case RTW89_PS_MODE_CLK_GATED: 1180 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1181 break; 1182 case RTW89_PS_MODE_PWR_GATED: 1183 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1184 break; 1185 default: 1186 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1187 break; 1188 } 1189 return state; 1190 } 1191 1192 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1193 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1194 bool notify_wake) 1195 { 1196 u16 request; 1197 1198 spin_lock_bh(&rtwdev->rpwm_lock); 1199 1200 request = rtw89_read16(rtwdev, R_AX_RPWM); 1201 request ^= request | PS_RPWM_TOGGLE; 1202 request |= req_pwr_state; 1203 1204 if (notify_wake) { 1205 request |= PS_RPWM_NOTIFY_WAKE; 1206 } else { 1207 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1208 RPWM_SEQ_NUM_MAX; 1209 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1210 rtwdev->mac.rpwm_seq_num); 1211 1212 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1213 request |= PS_RPWM_ACK; 1214 } 1215 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1216 1217 spin_unlock_bh(&rtwdev->rpwm_lock); 1218 } 1219 1220 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1221 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1222 { 1223 bool request_deep_mode; 1224 bool in_deep_mode; 1225 u8 rpwm_req_num; 1226 u8 cpwm_rsp_seq; 1227 u8 cpwm_seq; 1228 u8 cpwm_status; 1229 1230 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1231 request_deep_mode = true; 1232 else 1233 request_deep_mode = false; 1234 1235 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1236 in_deep_mode = true; 1237 else 1238 in_deep_mode = false; 1239 1240 if (request_deep_mode != in_deep_mode) 1241 return -EPERM; 1242 1243 if (request_deep_mode) 1244 return 0; 1245 1246 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1247 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1248 PS_CPWM_RSP_SEQ_NUM); 1249 1250 if (rpwm_req_num != cpwm_rsp_seq) 1251 return -EPERM; 1252 1253 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1254 CPWM_SEQ_NUM_MAX; 1255 1256 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1257 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1258 return -EPERM; 1259 1260 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1261 if (cpwm_status != req_pwr_state) 1262 return -EPERM; 1263 1264 return 0; 1265 } 1266 1267 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1268 { 1269 enum rtw89_rpwm_req_pwr_state state; 1270 unsigned long delay = enter ? 10 : 150; 1271 int ret; 1272 int i; 1273 1274 if (enter) 1275 state = rtw89_mac_get_req_pwr_state(rtwdev); 1276 else 1277 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1278 1279 for (i = 0; i < RPWM_TRY_CNT; i++) { 1280 rtw89_mac_send_rpwm(rtwdev, state, false); 1281 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1282 !ret, delay, 15000, false, 1283 rtwdev, state); 1284 if (!ret) 1285 break; 1286 1287 if (i == RPWM_TRY_CNT - 1) 1288 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1289 enter ? "entering" : "leaving"); 1290 else 1291 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1292 "%d time firmware failed to ack for %s ps mode\n", 1293 i + 1, enter ? "entering" : "leaving"); 1294 } 1295 } 1296 1297 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1298 { 1299 enum rtw89_rpwm_req_pwr_state state; 1300 1301 state = rtw89_mac_get_req_pwr_state(rtwdev); 1302 rtw89_mac_send_rpwm(rtwdev, state, true); 1303 } 1304 1305 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1306 { 1307 #define PWR_ACT 1 1308 const struct rtw89_chip_info *chip = rtwdev->chip; 1309 const struct rtw89_pwr_cfg * const *cfg_seq; 1310 int (*cfg_func)(struct rtw89_dev *rtwdev); 1311 int ret; 1312 u8 val; 1313 1314 if (on) { 1315 cfg_seq = chip->pwr_on_seq; 1316 cfg_func = chip->ops->pwr_on_func; 1317 } else { 1318 cfg_seq = chip->pwr_off_seq; 1319 cfg_func = chip->ops->pwr_off_func; 1320 } 1321 1322 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1323 __rtw89_leave_ps_mode(rtwdev); 1324 1325 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1326 if (on && val == PWR_ACT) { 1327 rtw89_err(rtwdev, "MAC has already powered on\n"); 1328 return -EBUSY; 1329 } 1330 1331 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1332 if (ret) 1333 return ret; 1334 1335 if (on) { 1336 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1337 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1338 } else { 1339 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1340 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1341 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1342 rtw89_set_entity_state(rtwdev, false); 1343 } 1344 1345 return 0; 1346 #undef PWR_ACT 1347 } 1348 1349 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1350 { 1351 rtw89_mac_power_switch(rtwdev, false); 1352 } 1353 1354 static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1355 { 1356 u32 func_en = 0; 1357 u32 ck_en = 0; 1358 u32 c1pc_en = 0; 1359 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1360 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1361 1362 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1363 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1364 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1365 B_AX_CMAC_CRPRT; 1366 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1367 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1368 B_AX_RMAC_CKEN; 1369 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1370 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1371 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1372 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1373 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1374 1375 if (en) { 1376 if (mac_idx == RTW89_MAC_1) { 1377 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1378 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1379 B_AX_R_SYM_ISO_CMAC12PP); 1380 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1381 B_AX_CMAC1_FEN); 1382 } 1383 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1384 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1385 } else { 1386 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1387 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1388 if (mac_idx == RTW89_MAC_1) { 1389 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1390 B_AX_CMAC1_FEN); 1391 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1392 B_AX_R_SYM_ISO_CMAC12PP); 1393 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1394 } 1395 } 1396 1397 return 0; 1398 } 1399 1400 static int dmac_func_en(struct rtw89_dev *rtwdev) 1401 { 1402 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1403 u32 val32; 1404 1405 if (chip_id == RTL8852C) 1406 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1407 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1408 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1409 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1410 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1411 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1412 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1413 else 1414 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1415 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1416 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1417 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1418 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1419 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1420 B_AX_DMAC_CRPRT); 1421 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1422 1423 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1424 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1425 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1426 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1427 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1428 1429 return 0; 1430 } 1431 1432 static int chip_func_en(struct rtw89_dev *rtwdev) 1433 { 1434 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1435 1436 if (chip_id == RTL8852A || chip_id == RTL8852B) 1437 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1438 B_AX_OCP_L1_MASK); 1439 1440 return 0; 1441 } 1442 1443 static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev) 1444 { 1445 int ret; 1446 1447 ret = dmac_func_en(rtwdev); 1448 if (ret) 1449 return ret; 1450 1451 ret = cmac_func_en(rtwdev, 0, true); 1452 if (ret) 1453 return ret; 1454 1455 ret = chip_func_en(rtwdev); 1456 if (ret) 1457 return ret; 1458 1459 return ret; 1460 } 1461 1462 const struct rtw89_mac_size_set rtw89_mac_size = { 1463 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1464 /* PCIE 64 */ 1465 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1466 /* DLFW */ 1467 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1468 /* PCIE 64 */ 1469 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1470 /* 8852B PCIE SCC */ 1471 .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1472 /* DLFW */ 1473 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1474 /* 8852C DLFW */ 1475 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1476 /* 8852C PCIE SCC */ 1477 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1478 /* PCIE */ 1479 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1480 /* DLFW */ 1481 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1482 /* PCIE 64 */ 1483 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1484 /* DLFW */ 1485 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1486 /* 8852C DLFW */ 1487 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1488 /* 8852C PCIE SCC */ 1489 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1490 /* PCIE 64 */ 1491 .wde_qt0 = {3792, 196, 0, 107,}, 1492 /* DLFW */ 1493 .wde_qt4 = {0, 0, 0, 0,}, 1494 /* PCIE 64 */ 1495 .wde_qt6 = {448, 48, 0, 16,}, 1496 /* 8852B PCIE SCC */ 1497 .wde_qt7 = {446, 48, 0, 16,}, 1498 /* 8852C DLFW */ 1499 .wde_qt17 = {0, 0, 0, 0,}, 1500 /* 8852C PCIE SCC */ 1501 .wde_qt18 = {3228, 60, 0, 40,}, 1502 /* PCIE SCC */ 1503 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1504 /* PCIE SCC */ 1505 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1506 /* DLFW */ 1507 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1508 /* PCIE 64 */ 1509 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1510 /* DLFW 52C */ 1511 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1512 /* DLFW 52C */ 1513 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1514 /* 8852C PCIE SCC */ 1515 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1516 /* 8852C PCIE SCC */ 1517 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1518 /* PCIE 64 */ 1519 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1520 /* 8852A PCIE WOW */ 1521 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1522 /* 8852B PCIE WOW */ 1523 .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1524 /* 8851B PCIE WOW */ 1525 .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1526 }; 1527 EXPORT_SYMBOL(rtw89_mac_size); 1528 1529 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1530 enum rtw89_qta_mode mode) 1531 { 1532 struct rtw89_mac_info *mac = &rtwdev->mac; 1533 const struct rtw89_dle_mem *cfg; 1534 1535 cfg = &rtwdev->chip->dle_mem[mode]; 1536 if (!cfg) 1537 return NULL; 1538 1539 if (cfg->mode != mode) { 1540 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1541 return NULL; 1542 } 1543 1544 mac->dle_info.wde_pg_size = cfg->wde_size->pge_size; 1545 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1546 mac->dle_info.qta_mode = mode; 1547 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1548 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1549 1550 return cfg; 1551 } 1552 1553 static bool mac_is_txq_empty(struct rtw89_dev *rtwdev) 1554 { 1555 struct rtw89_mac_dle_dfi_qempty qempty; 1556 u32 qnum, qtmp, val32, msk32; 1557 int i, j, ret; 1558 1559 qnum = rtwdev->chip->wde_qempty_acq_num; 1560 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1561 1562 for (i = 0; i < qnum; i++) { 1563 qempty.grpsel = i; 1564 ret = dle_dfi_qempty(rtwdev, &qempty); 1565 if (ret) { 1566 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1567 return false; 1568 } 1569 qtmp = qempty.qempty; 1570 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1571 val32 = FIELD_GET(QEMP_ACQ_GRP_QSEL_MASK, qtmp); 1572 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1573 return false; 1574 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1575 } 1576 } 1577 1578 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_sel; 1579 ret = dle_dfi_qempty(rtwdev, &qempty); 1580 if (ret) { 1581 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1582 return false; 1583 } 1584 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1585 if ((qempty.qempty & msk32) != msk32) 1586 return false; 1587 1588 if (rtwdev->dbcc_en) { 1589 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1590 if ((qempty.qempty & msk32) != msk32) 1591 return false; 1592 } 1593 1594 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1595 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1596 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1597 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1598 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1599 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1600 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1601 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1602 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1603 1604 return (val32 & msk32) == msk32; 1605 } 1606 1607 static inline u32 dle_used_size(const struct rtw89_dle_size *wde, 1608 const struct rtw89_dle_size *ple) 1609 { 1610 return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1611 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1612 } 1613 1614 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 1615 enum rtw89_qta_mode mode) 1616 { 1617 u32 size = rtwdev->chip->fifo_size; 1618 1619 if (mode == RTW89_QTA_SCC) 1620 size -= rtwdev->chip->dle_scc_rsvd_size; 1621 1622 return size; 1623 } 1624 1625 static void dle_func_en(struct rtw89_dev *rtwdev, bool enable) 1626 { 1627 if (enable) 1628 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1629 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1630 else 1631 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1632 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1633 } 1634 1635 static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable) 1636 { 1637 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 1638 1639 if (enable) { 1640 if (rtwdev->chip->chip_id == RTL8851B) 1641 val |= B_AX_AXIDMA_CLK_EN; 1642 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 1643 } else { 1644 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 1645 } 1646 } 1647 1648 static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1649 { 1650 const struct rtw89_dle_size *size_cfg; 1651 u32 val; 1652 u8 bound = 0; 1653 1654 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1655 size_cfg = cfg->wde_size; 1656 1657 switch (size_cfg->pge_size) { 1658 default: 1659 case RTW89_WDE_PG_64: 1660 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1661 B_AX_WDE_PAGE_SEL_MASK); 1662 break; 1663 case RTW89_WDE_PG_128: 1664 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1665 B_AX_WDE_PAGE_SEL_MASK); 1666 break; 1667 case RTW89_WDE_PG_256: 1668 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1669 return -EINVAL; 1670 } 1671 1672 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1673 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1674 B_AX_WDE_FREE_PAGE_NUM_MASK); 1675 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1676 1677 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1678 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1679 * size_cfg->pge_size / DLE_BOUND_UNIT; 1680 size_cfg = cfg->ple_size; 1681 1682 switch (size_cfg->pge_size) { 1683 default: 1684 case RTW89_PLE_PG_64: 1685 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1686 return -EINVAL; 1687 case RTW89_PLE_PG_128: 1688 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1689 B_AX_PLE_PAGE_SEL_MASK); 1690 break; 1691 case RTW89_PLE_PG_256: 1692 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1693 B_AX_PLE_PAGE_SEL_MASK); 1694 break; 1695 } 1696 1697 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1698 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1699 B_AX_PLE_FREE_PAGE_NUM_MASK); 1700 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1701 1702 return 0; 1703 } 1704 1705 #define INVALID_QT_WCPU U16_MAX 1706 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1707 do { \ 1708 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1709 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1710 rtw89_write32(rtwdev, \ 1711 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1712 val); \ 1713 } while (0) 1714 #define SET_QUOTA(_x, _module, _idx) \ 1715 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1716 1717 static void wde_quota_cfg(struct rtw89_dev *rtwdev, 1718 const struct rtw89_wde_quota *min_cfg, 1719 const struct rtw89_wde_quota *max_cfg, 1720 u16 ext_wde_min_qt_wcpu) 1721 { 1722 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1723 ext_wde_min_qt_wcpu : min_cfg->wcpu; 1724 u32 val; 1725 1726 SET_QUOTA(hif, WDE, 0); 1727 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1728 SET_QUOTA(pkt_in, WDE, 3); 1729 SET_QUOTA(cpu_io, WDE, 4); 1730 } 1731 1732 static void ple_quota_cfg(struct rtw89_dev *rtwdev, 1733 const struct rtw89_ple_quota *min_cfg, 1734 const struct rtw89_ple_quota *max_cfg) 1735 { 1736 u32 val; 1737 1738 SET_QUOTA(cma0_tx, PLE, 0); 1739 SET_QUOTA(cma1_tx, PLE, 1); 1740 SET_QUOTA(c2h, PLE, 2); 1741 SET_QUOTA(h2c, PLE, 3); 1742 SET_QUOTA(wcpu, PLE, 4); 1743 SET_QUOTA(mpdu_proc, PLE, 5); 1744 SET_QUOTA(cma0_dma, PLE, 6); 1745 SET_QUOTA(cma1_dma, PLE, 7); 1746 SET_QUOTA(bb_rpt, PLE, 8); 1747 SET_QUOTA(wd_rel, PLE, 9); 1748 SET_QUOTA(cpu_io, PLE, 10); 1749 if (rtwdev->chip->chip_id == RTL8852C) 1750 SET_QUOTA(tx_rpt, PLE, 11); 1751 } 1752 1753 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 1754 { 1755 const struct rtw89_ple_quota *min_cfg, *max_cfg; 1756 const struct rtw89_dle_mem *cfg; 1757 u32 val; 1758 1759 if (rtwdev->chip->chip_id == RTL8852C) 1760 return 0; 1761 1762 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 1763 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 1764 return -EINVAL; 1765 } 1766 1767 if (wow) 1768 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 1769 else 1770 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 1771 if (!cfg) { 1772 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1773 return -EINVAL; 1774 } 1775 1776 min_cfg = cfg->ple_min_qt; 1777 max_cfg = cfg->ple_max_qt; 1778 SET_QUOTA(cma0_dma, PLE, 6); 1779 SET_QUOTA(cma1_dma, PLE, 7); 1780 1781 return 0; 1782 } 1783 #undef SET_QUOTA 1784 1785 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 1786 { 1787 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 1788 1789 if (enable) 1790 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 1791 else 1792 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 1793 } 1794 1795 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 1796 const struct rtw89_dle_mem *cfg, 1797 u16 ext_wde_min_qt_wcpu) 1798 { 1799 wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 1800 ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 1801 } 1802 1803 static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 1804 enum rtw89_qta_mode ext_mode) 1805 { 1806 const struct rtw89_dle_mem *cfg, *ext_cfg; 1807 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 1808 int ret = 0; 1809 u32 ini; 1810 1811 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1812 if (ret) 1813 return ret; 1814 1815 cfg = get_dle_mem_cfg(rtwdev, mode); 1816 if (!cfg) { 1817 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 1818 ret = -EINVAL; 1819 goto error; 1820 } 1821 1822 if (mode == RTW89_QTA_DLFW) { 1823 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 1824 if (!ext_cfg) { 1825 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 1826 ext_mode); 1827 ret = -EINVAL; 1828 goto error; 1829 } 1830 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 1831 } 1832 1833 if (dle_used_size(cfg->wde_size, cfg->ple_size) != 1834 dle_expected_used_size(rtwdev, mode)) { 1835 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 1836 ret = -EINVAL; 1837 goto error; 1838 } 1839 1840 dle_func_en(rtwdev, false); 1841 dle_clk_en(rtwdev, true); 1842 1843 ret = dle_mix_cfg(rtwdev, cfg); 1844 if (ret) { 1845 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 1846 goto error; 1847 } 1848 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 1849 1850 dle_func_en(rtwdev, true); 1851 1852 ret = read_poll_timeout(rtw89_read32, ini, 1853 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1854 2000, false, rtwdev, R_AX_WDE_INI_STATUS); 1855 if (ret) { 1856 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 1857 return ret; 1858 } 1859 1860 ret = read_poll_timeout(rtw89_read32, ini, 1861 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1, 1862 2000, false, rtwdev, R_AX_PLE_INI_STATUS); 1863 if (ret) { 1864 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 1865 return ret; 1866 } 1867 1868 return 0; 1869 error: 1870 dle_func_en(rtwdev, false); 1871 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 1872 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 1873 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 1874 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 1875 1876 return ret; 1877 } 1878 1879 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1880 enum rtw89_qta_mode mode) 1881 { 1882 u32 reg, max_preld_size, min_rsvd_size; 1883 1884 max_preld_size = (mac_idx == RTW89_MAC_0 ? 1885 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 1886 reg = mac_idx == RTW89_MAC_0 ? 1887 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 1888 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 1889 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 1890 1891 min_rsvd_size = PRELD_AMSDU_SIZE; 1892 reg = mac_idx == RTW89_MAC_0 ? 1893 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 1894 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 1895 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 1896 1897 return 0; 1898 } 1899 1900 static bool is_qta_poh(struct rtw89_dev *rtwdev) 1901 { 1902 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 1903 } 1904 1905 static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 1906 enum rtw89_qta_mode mode) 1907 { 1908 const struct rtw89_chip_info *chip = rtwdev->chip; 1909 1910 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 1911 chip->chip_id == RTL8851B || !is_qta_poh(rtwdev)) 1912 return 0; 1913 1914 return preload_init_set(rtwdev, mac_idx, mode); 1915 } 1916 1917 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 1918 { 1919 u32 msk32; 1920 u32 val32; 1921 1922 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 1923 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 1924 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 1925 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1926 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 1927 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 1928 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 1929 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 1930 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1931 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 1932 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1933 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1934 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 1935 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1936 1937 if ((val32 & msk32) == msk32) 1938 return true; 1939 1940 return false; 1941 } 1942 1943 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 1944 { 1945 const struct rtw89_chip_info *chip = rtwdev->chip; 1946 1947 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 1948 chip->chip_id == RTL8851B) 1949 return; 1950 1951 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 1952 SS2F_PATH_WLCPU); 1953 } 1954 1955 static int sta_sch_init(struct rtw89_dev *rtwdev) 1956 { 1957 u32 p_val; 1958 u8 val; 1959 int ret; 1960 1961 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1962 if (ret) 1963 return ret; 1964 1965 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 1966 val |= B_AX_SS_EN; 1967 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 1968 1969 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 1970 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 1971 if (ret) { 1972 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 1973 return ret; 1974 } 1975 1976 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 1977 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 1978 1979 _patch_ss2f_path(rtwdev); 1980 1981 return 0; 1982 } 1983 1984 static int mpdu_proc_init(struct rtw89_dev *rtwdev) 1985 { 1986 int ret; 1987 1988 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1989 if (ret) 1990 return ret; 1991 1992 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 1993 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 1994 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 1995 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 1996 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 1997 1998 return 0; 1999 } 2000 2001 static int sec_eng_init(struct rtw89_dev *rtwdev) 2002 { 2003 const struct rtw89_chip_info *chip = rtwdev->chip; 2004 u32 val = 0; 2005 int ret; 2006 2007 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2008 if (ret) 2009 return ret; 2010 2011 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2012 /* init clock */ 2013 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2014 /* init TX encryption */ 2015 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2016 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 2017 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2018 chip->chip_id == RTL8851B) 2019 val &= ~B_AX_TX_PARTIAL_MODE; 2020 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2021 2022 /* init MIC ICV append */ 2023 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2024 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2025 2026 /* option init */ 2027 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2028 2029 if (chip->chip_id == RTL8852C) 2030 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2031 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2032 2033 return 0; 2034 } 2035 2036 static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2037 { 2038 int ret; 2039 2040 ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2041 if (ret) { 2042 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2043 return ret; 2044 } 2045 2046 ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2047 if (ret) { 2048 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2049 return ret; 2050 } 2051 2052 ret = hfc_init(rtwdev, true, true, true); 2053 if (ret) { 2054 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2055 return ret; 2056 } 2057 2058 ret = sta_sch_init(rtwdev); 2059 if (ret) { 2060 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2061 return ret; 2062 } 2063 2064 ret = mpdu_proc_init(rtwdev); 2065 if (ret) { 2066 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2067 return ret; 2068 } 2069 2070 ret = sec_eng_init(rtwdev); 2071 if (ret) { 2072 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2073 return ret; 2074 } 2075 2076 return ret; 2077 } 2078 2079 static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2080 { 2081 u32 val, reg; 2082 u16 p_val; 2083 int ret; 2084 2085 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2086 if (ret) 2087 return ret; 2088 2089 reg = rtw89_mac_reg_by_idx(R_AX_ADDR_CAM_CTRL, mac_idx); 2090 2091 val = rtw89_read32(rtwdev, reg); 2092 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2093 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2094 rtw89_write32(rtwdev, reg, val); 2095 2096 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2097 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2098 if (ret) { 2099 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2100 return ret; 2101 } 2102 2103 return 0; 2104 } 2105 2106 static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2107 { 2108 u32 ret; 2109 u32 reg; 2110 u32 val; 2111 2112 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2113 if (ret) 2114 return ret; 2115 2116 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_1, mac_idx); 2117 if (rtwdev->chip->chip_id == RTL8852C) 2118 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2119 SIFS_MACTXEN_T1_V1); 2120 else 2121 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2122 SIFS_MACTXEN_T1); 2123 2124 if (rtwdev->chip->chip_id == RTL8852B || rtwdev->chip->chip_id == RTL8851B) { 2125 reg = rtw89_mac_reg_by_idx(R_AX_SCH_EXT_CTRL, mac_idx); 2126 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2127 } 2128 2129 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CFG_0, mac_idx); 2130 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2131 2132 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_0, mac_idx); 2133 if (rtwdev->chip->chip_id == RTL8852C) { 2134 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2135 B_AX_TX_PARTIAL_MODE); 2136 if (!val) 2137 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2138 SCH_PREBKF_24US); 2139 } else { 2140 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2141 SCH_PREBKF_24US); 2142 } 2143 2144 return 0; 2145 } 2146 2147 int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev, 2148 enum rtw89_machdr_frame_type type, 2149 enum rtw89_mac_fwd_target fwd_target, 2150 u8 mac_idx) 2151 { 2152 u32 reg; 2153 u32 val; 2154 2155 switch (fwd_target) { 2156 case RTW89_FWD_DONT_CARE: 2157 val = RX_FLTR_FRAME_DROP; 2158 break; 2159 case RTW89_FWD_TO_HOST: 2160 val = RX_FLTR_FRAME_TO_HOST; 2161 break; 2162 case RTW89_FWD_TO_WLAN_CPU: 2163 val = RX_FLTR_FRAME_TO_WLCPU; 2164 break; 2165 default: 2166 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2167 return -EINVAL; 2168 } 2169 2170 switch (type) { 2171 case RTW89_MGNT: 2172 reg = rtw89_mac_reg_by_idx(R_AX_MGNT_FLTR, mac_idx); 2173 break; 2174 case RTW89_CTRL: 2175 reg = rtw89_mac_reg_by_idx(R_AX_CTRL_FLTR, mac_idx); 2176 break; 2177 case RTW89_DATA: 2178 reg = rtw89_mac_reg_by_idx(R_AX_DATA_FLTR, mac_idx); 2179 break; 2180 default: 2181 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2182 return -EINVAL; 2183 } 2184 rtw89_write32(rtwdev, reg, val); 2185 2186 return 0; 2187 } 2188 2189 static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2190 { 2191 int ret, i; 2192 u32 mac_ftlr, plcp_ftlr; 2193 2194 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2195 if (ret) 2196 return ret; 2197 2198 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2199 ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST, 2200 mac_idx); 2201 if (ret) 2202 return ret; 2203 } 2204 mac_ftlr = rtwdev->hal.rx_fltr; 2205 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2206 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2207 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2208 B_AX_HE_SIGB_CRC_CHK; 2209 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx), 2210 mac_ftlr); 2211 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx), 2212 plcp_ftlr); 2213 2214 return 0; 2215 } 2216 2217 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2218 { 2219 u32 reg, val32; 2220 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2221 2222 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2223 B_AX_RSP_CHK_BASIC_NAV; 2224 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2225 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2226 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2227 2228 switch (rtwdev->chip->chip_id) { 2229 case RTL8852A: 2230 case RTL8852B: 2231 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 2232 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2233 rtw89_write32(rtwdev, reg, val32); 2234 2235 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2236 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2237 rtw89_write32(rtwdev, reg, val32); 2238 break; 2239 default: 2240 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx); 2241 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2242 rtw89_write32(rtwdev, reg, val32); 2243 2244 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2245 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2246 rtw89_write32(rtwdev, reg, val32); 2247 break; 2248 } 2249 } 2250 2251 static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2252 { 2253 u32 val, reg; 2254 int ret; 2255 2256 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2257 if (ret) 2258 return ret; 2259 2260 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CONTROL, mac_idx); 2261 val = rtw89_read32(rtwdev, reg); 2262 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2263 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2264 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2265 B_AX_CTN_CHK_INTRA_NAV | 2266 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2267 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2268 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2269 B_AX_CTN_CHK_CCA_P20); 2270 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2271 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2272 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2273 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2274 B_AX_SIFS_CHK_EDCCA); 2275 2276 rtw89_write32(rtwdev, reg, val); 2277 2278 _patch_dis_resp_chk(rtwdev, mac_idx); 2279 2280 return 0; 2281 } 2282 2283 static int nav_ctrl_init(struct rtw89_dev *rtwdev) 2284 { 2285 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2286 B_AX_WMAC_TF_UP_NAV_EN | 2287 B_AX_WMAC_NAV_UPPER_EN); 2288 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2289 2290 return 0; 2291 } 2292 2293 static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2294 { 2295 u32 reg; 2296 int ret; 2297 2298 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2299 if (ret) 2300 return ret; 2301 reg = rtw89_mac_reg_by_idx(R_AX_RX_SR_CTRL, mac_idx); 2302 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2303 2304 return 0; 2305 } 2306 2307 static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2308 { 2309 u32 reg; 2310 int ret; 2311 2312 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2313 if (ret) 2314 return ret; 2315 2316 reg = rtw89_mac_reg_by_idx(R_AX_MAC_LOOPBACK, mac_idx); 2317 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2318 2319 reg = rtw89_mac_reg_by_idx(R_AX_TCR0, mac_idx); 2320 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2321 2322 reg = rtw89_mac_reg_by_idx(R_AX_TXD_FIFO_CTRL, mac_idx); 2323 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2324 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2325 2326 return 0; 2327 } 2328 2329 static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2330 { 2331 const struct rtw89_chip_info *chip = rtwdev->chip; 2332 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2333 u32 reg, val, sifs; 2334 int ret; 2335 2336 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2337 if (ret) 2338 return ret; 2339 2340 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx); 2341 val = rtw89_read32(rtwdev, reg); 2342 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2343 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2344 2345 switch (rtwdev->chip->chip_id) { 2346 case RTL8852A: 2347 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2348 break; 2349 case RTL8852B: 2350 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2351 break; 2352 default: 2353 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2354 break; 2355 } 2356 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2357 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2358 rtw89_write32(rtwdev, reg, val); 2359 2360 reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx); 2361 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2362 2363 reg = rtw89_mac_reg_by_idx(rrsr->ref_rate.addr, mac_idx); 2364 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2365 reg = rtw89_mac_reg_by_idx(rrsr->rsc.addr, mac_idx); 2366 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2367 2368 return 0; 2369 } 2370 2371 static void rst_bacam(struct rtw89_dev *rtwdev) 2372 { 2373 u32 val32; 2374 int ret; 2375 2376 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2377 S_AX_BACAM_RST_ALL); 2378 2379 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2380 1, 1000, false, 2381 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2382 if (ret) 2383 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2384 } 2385 2386 static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2387 { 2388 #define TRXCFG_RMAC_CCA_TO 32 2389 #define TRXCFG_RMAC_DATA_TO 15 2390 #define RX_MAX_LEN_UNIT 512 2391 #define PLD_RLS_MAX_PG 127 2392 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2393 int ret; 2394 u32 reg, rx_max_len, rx_qta; 2395 u16 val; 2396 2397 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2398 if (ret) 2399 return ret; 2400 2401 if (mac_idx == RTW89_MAC_0) 2402 rst_bacam(rtwdev); 2403 2404 reg = rtw89_mac_reg_by_idx(R_AX_RESPBA_CAM_CTRL, mac_idx); 2405 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2406 2407 reg = rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx); 2408 val = rtw89_read16(rtwdev, reg); 2409 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2410 B_AX_RX_DLK_DATA_TIME_MASK); 2411 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2412 B_AX_RX_DLK_CCA_TIME_MASK); 2413 rtw89_write16(rtwdev, reg, val); 2414 2415 reg = rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx); 2416 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2417 2418 reg = rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx); 2419 if (mac_idx == RTW89_MAC_0) 2420 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2421 else 2422 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2423 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2424 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2425 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2426 rx_max_len /= RX_MAX_LEN_UNIT; 2427 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2428 2429 if (rtwdev->chip->chip_id == RTL8852A && 2430 rtwdev->hal.cv == CHIP_CBV) { 2431 rtw89_write16_mask(rtwdev, 2432 rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx), 2433 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2434 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx), 2435 BIT(12)); 2436 } 2437 2438 reg = rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx); 2439 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2440 2441 return ret; 2442 } 2443 2444 static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2445 { 2446 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2447 u32 val, reg; 2448 int ret; 2449 2450 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2451 if (ret) 2452 return ret; 2453 2454 reg = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2455 val = rtw89_read32(rtwdev, reg); 2456 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2457 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2458 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2459 rtw89_write32(rtwdev, reg, val); 2460 2461 if (chip_id == RTL8852A || chip_id == RTL8852B) { 2462 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_RRSR1, mac_idx); 2463 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2464 } 2465 2466 return 0; 2467 } 2468 2469 static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2470 { 2471 const struct rtw89_dle_mem *cfg; 2472 2473 cfg = get_dle_mem_cfg(rtwdev, mode); 2474 if (!cfg) { 2475 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2476 return false; 2477 } 2478 2479 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2480 } 2481 2482 static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2483 { 2484 u32 val, reg; 2485 int ret; 2486 2487 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2488 if (ret) 2489 return ret; 2490 2491 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2492 reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx); 2493 val = rtw89_read32(rtwdev, reg); 2494 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2495 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2496 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2497 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2498 val |= B_AX_HW_CTS2SELF_EN; 2499 rtw89_write32(rtwdev, reg, val); 2500 2501 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_FSM_MON, mac_idx); 2502 val = rtw89_read32(rtwdev, reg); 2503 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2504 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2505 rtw89_write32(rtwdev, reg, val); 2506 } 2507 2508 if (mac_idx == RTW89_MAC_0) { 2509 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2510 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2511 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2512 B_AX_PTCL_TRIGGER_SS_EN_0 | 2513 B_AX_PTCL_TRIGGER_SS_EN_1 | 2514 B_AX_PTCL_TRIGGER_SS_EN_UL); 2515 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2516 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2517 } else if (mac_idx == RTW89_MAC_1) { 2518 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2519 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2520 } 2521 2522 return 0; 2523 } 2524 2525 static int cmac_dma_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2526 { 2527 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2528 u32 reg; 2529 int ret; 2530 2531 if (chip_id != RTL8852A && chip_id != RTL8852B) 2532 return 0; 2533 2534 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2535 if (ret) 2536 return ret; 2537 2538 reg = rtw89_mac_reg_by_idx(R_AX_RXDMA_CTRL_0, mac_idx); 2539 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2540 2541 return 0; 2542 } 2543 2544 static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx) 2545 { 2546 int ret; 2547 2548 ret = scheduler_init(rtwdev, mac_idx); 2549 if (ret) { 2550 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2551 return ret; 2552 } 2553 2554 ret = addr_cam_init(rtwdev, mac_idx); 2555 if (ret) { 2556 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2557 ret); 2558 return ret; 2559 } 2560 2561 ret = rx_fltr_init(rtwdev, mac_idx); 2562 if (ret) { 2563 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2564 ret); 2565 return ret; 2566 } 2567 2568 ret = cca_ctrl_init(rtwdev, mac_idx); 2569 if (ret) { 2570 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2571 ret); 2572 return ret; 2573 } 2574 2575 ret = nav_ctrl_init(rtwdev); 2576 if (ret) { 2577 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2578 ret); 2579 return ret; 2580 } 2581 2582 ret = spatial_reuse_init(rtwdev, mac_idx); 2583 if (ret) { 2584 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2585 mac_idx, ret); 2586 return ret; 2587 } 2588 2589 ret = tmac_init(rtwdev, mac_idx); 2590 if (ret) { 2591 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2592 return ret; 2593 } 2594 2595 ret = trxptcl_init(rtwdev, mac_idx); 2596 if (ret) { 2597 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2598 return ret; 2599 } 2600 2601 ret = rmac_init(rtwdev, mac_idx); 2602 if (ret) { 2603 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2604 return ret; 2605 } 2606 2607 ret = cmac_com_init(rtwdev, mac_idx); 2608 if (ret) { 2609 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2610 return ret; 2611 } 2612 2613 ret = ptcl_init(rtwdev, mac_idx); 2614 if (ret) { 2615 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2616 return ret; 2617 } 2618 2619 ret = cmac_dma_init(rtwdev, mac_idx); 2620 if (ret) { 2621 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2622 return ret; 2623 } 2624 2625 return ret; 2626 } 2627 2628 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2629 struct rtw89_mac_c2h_info *c2h_info) 2630 { 2631 struct rtw89_mac_h2c_info h2c_info = {0}; 2632 u32 ret; 2633 2634 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2635 h2c_info.content_len = 0; 2636 2637 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2638 if (ret) 2639 return ret; 2640 2641 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2642 return -EINVAL; 2643 2644 return 0; 2645 } 2646 2647 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2648 { 2649 struct rtw89_efuse *efuse = &rtwdev->efuse; 2650 struct rtw89_hal *hal = &rtwdev->hal; 2651 const struct rtw89_chip_info *chip = rtwdev->chip; 2652 struct rtw89_mac_c2h_info c2h_info = {0}; 2653 const struct rtw89_c2hreg_phycap *phycap; 2654 u8 tx_nss; 2655 u8 rx_nss; 2656 u8 tx_ant; 2657 u8 rx_ant; 2658 u32 ret; 2659 2660 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2661 if (ret) 2662 return ret; 2663 2664 phycap = &c2h_info.u.phycap; 2665 2666 tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS); 2667 rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS); 2668 tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); 2669 rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); 2670 2671 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2672 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2673 2674 if (tx_ant == 1) 2675 hal->antenna_tx = RF_B; 2676 if (rx_ant == 1) 2677 hal->antenna_rx = RF_B; 2678 2679 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2680 hal->antenna_tx = RF_B; 2681 hal->tx_path_diversity = true; 2682 } 2683 2684 if (chip->rf_path_num == 1) { 2685 hal->antenna_tx = RF_A; 2686 hal->antenna_rx = RF_A; 2687 if ((efuse->rfe_type % 3) == 2) 2688 hal->ant_diversity = true; 2689 } 2690 2691 rtw89_debug(rtwdev, RTW89_DBG_FW, 2692 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2693 hal->tx_nss, tx_nss, chip->tx_nss, 2694 hal->rx_nss, rx_nss, chip->rx_nss); 2695 rtw89_debug(rtwdev, RTW89_DBG_FW, 2696 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2697 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2698 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2699 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 2700 2701 return 0; 2702 } 2703 2704 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2705 u16 tx_en_u16, u16 mask_u16) 2706 { 2707 u32 ret; 2708 struct rtw89_mac_c2h_info c2h_info = {0}; 2709 struct rtw89_mac_h2c_info h2c_info = {0}; 2710 struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 2711 2712 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2713 h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; 2714 2715 u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN); 2716 u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK); 2717 u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND); 2718 2719 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2720 if (ret) 2721 return ret; 2722 2723 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2724 return -EINVAL; 2725 2726 return 0; 2727 } 2728 2729 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 2730 u16 tx_en, u16 tx_en_mask) 2731 { 2732 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx); 2733 u16 val; 2734 int ret; 2735 2736 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2737 if (ret) 2738 return ret; 2739 2740 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 2741 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 2742 tx_en, tx_en_mask); 2743 2744 val = rtw89_read16(rtwdev, reg); 2745 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2746 rtw89_write16(rtwdev, reg, val); 2747 2748 return 0; 2749 } 2750 2751 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2752 u32 tx_en, u32 tx_en_mask) 2753 { 2754 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx); 2755 u32 val; 2756 int ret; 2757 2758 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2759 if (ret) 2760 return ret; 2761 2762 val = rtw89_read32(rtwdev, reg); 2763 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 2764 rtw89_write32(rtwdev, reg, val); 2765 2766 return 0; 2767 } 2768 2769 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 2770 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2771 { 2772 int ret; 2773 2774 *tx_en = rtw89_read16(rtwdev, 2775 rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx)); 2776 2777 switch (sel) { 2778 case RTW89_SCH_TX_SEL_ALL: 2779 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2780 B_AX_CTN_TXEN_ALL_MASK); 2781 if (ret) 2782 return ret; 2783 break; 2784 case RTW89_SCH_TX_SEL_HIQ: 2785 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2786 0, B_AX_CTN_TXEN_HGQ); 2787 if (ret) 2788 return ret; 2789 break; 2790 case RTW89_SCH_TX_SEL_MG0: 2791 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 2792 0, B_AX_CTN_TXEN_MGQ); 2793 if (ret) 2794 return ret; 2795 break; 2796 case RTW89_SCH_TX_SEL_MACID: 2797 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 2798 B_AX_CTN_TXEN_ALL_MASK); 2799 if (ret) 2800 return ret; 2801 break; 2802 default: 2803 return 0; 2804 } 2805 2806 return 0; 2807 } 2808 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 2809 2810 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 2811 u32 *tx_en, enum rtw89_sch_tx_sel sel) 2812 { 2813 int ret; 2814 2815 *tx_en = rtw89_read32(rtwdev, 2816 rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx)); 2817 2818 switch (sel) { 2819 case RTW89_SCH_TX_SEL_ALL: 2820 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2821 B_AX_CTN_TXEN_ALL_MASK_V1); 2822 if (ret) 2823 return ret; 2824 break; 2825 case RTW89_SCH_TX_SEL_HIQ: 2826 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2827 0, B_AX_CTN_TXEN_HGQ); 2828 if (ret) 2829 return ret; 2830 break; 2831 case RTW89_SCH_TX_SEL_MG0: 2832 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 2833 0, B_AX_CTN_TXEN_MGQ); 2834 if (ret) 2835 return ret; 2836 break; 2837 case RTW89_SCH_TX_SEL_MACID: 2838 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 2839 B_AX_CTN_TXEN_ALL_MASK_V1); 2840 if (ret) 2841 return ret; 2842 break; 2843 default: 2844 return 0; 2845 } 2846 2847 return 0; 2848 } 2849 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 2850 2851 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2852 { 2853 int ret; 2854 2855 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 2856 if (ret) 2857 return ret; 2858 2859 return 0; 2860 } 2861 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 2862 2863 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 2864 { 2865 int ret; 2866 2867 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 2868 B_AX_CTN_TXEN_ALL_MASK_V1); 2869 if (ret) 2870 return ret; 2871 2872 return 0; 2873 } 2874 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 2875 2876 int rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 2877 { 2878 u32 val, reg; 2879 int ret; 2880 2881 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 2882 val = buf_len; 2883 val |= B_AX_WD_BUF_REQ_EXEC; 2884 rtw89_write32(rtwdev, reg, val); 2885 2886 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 2887 2888 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 2889 1, 2000, false, rtwdev, reg); 2890 if (ret) 2891 return ret; 2892 2893 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 2894 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 2895 return -ENOENT; 2896 2897 return 0; 2898 } 2899 2900 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev, 2901 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 2902 { 2903 u32 val, cmd_type, reg; 2904 int ret; 2905 2906 cmd_type = ctrl_para->cmd_type; 2907 2908 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 2909 val = 0; 2910 val = u32_replace_bits(val, ctrl_para->start_pktid, 2911 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 2912 val = u32_replace_bits(val, ctrl_para->end_pktid, 2913 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 2914 rtw89_write32(rtwdev, reg, val); 2915 2916 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 2917 val = 0; 2918 val = u32_replace_bits(val, ctrl_para->src_pid, 2919 B_AX_CPUQ_OP_SRC_PID_MASK); 2920 val = u32_replace_bits(val, ctrl_para->src_qid, 2921 B_AX_CPUQ_OP_SRC_QID_MASK); 2922 val = u32_replace_bits(val, ctrl_para->dst_pid, 2923 B_AX_CPUQ_OP_DST_PID_MASK); 2924 val = u32_replace_bits(val, ctrl_para->dst_qid, 2925 B_AX_CPUQ_OP_DST_QID_MASK); 2926 rtw89_write32(rtwdev, reg, val); 2927 2928 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 2929 val = 0; 2930 val = u32_replace_bits(val, cmd_type, 2931 B_AX_CPUQ_OP_CMD_TYPE_MASK); 2932 val = u32_replace_bits(val, ctrl_para->macid, 2933 B_AX_CPUQ_OP_MACID_MASK); 2934 val = u32_replace_bits(val, ctrl_para->pkt_num, 2935 B_AX_CPUQ_OP_PKTNUM_MASK); 2936 val |= B_AX_WD_CPUQ_OP_EXEC; 2937 rtw89_write32(rtwdev, reg, val); 2938 2939 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 2940 2941 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 2942 1, 2000, false, rtwdev, reg); 2943 if (ret) 2944 return ret; 2945 2946 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 2947 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 2948 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 2949 2950 return 0; 2951 } 2952 2953 static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2954 { 2955 const struct rtw89_dle_mem *cfg; 2956 struct rtw89_cpuio_ctrl ctrl_para = {0}; 2957 u16 pkt_id; 2958 int ret; 2959 2960 cfg = get_dle_mem_cfg(rtwdev, mode); 2961 if (!cfg) { 2962 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2963 return -EINVAL; 2964 } 2965 2966 if (dle_used_size(cfg->wde_size, cfg->ple_size) != 2967 dle_expected_used_size(rtwdev, mode)) { 2968 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2969 return -EINVAL; 2970 } 2971 2972 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 2973 2974 ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, true, &pkt_id); 2975 if (ret) { 2976 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 2977 return ret; 2978 } 2979 2980 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2981 ctrl_para.start_pktid = pkt_id; 2982 ctrl_para.end_pktid = pkt_id; 2983 ctrl_para.pkt_num = 0; 2984 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 2985 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 2986 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true); 2987 if (ret) { 2988 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 2989 return -EFAULT; 2990 } 2991 2992 ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, false, &pkt_id); 2993 if (ret) { 2994 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 2995 return ret; 2996 } 2997 2998 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2999 ctrl_para.start_pktid = pkt_id; 3000 ctrl_para.end_pktid = pkt_id; 3001 ctrl_para.pkt_num = 0; 3002 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 3003 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 3004 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false); 3005 if (ret) { 3006 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3007 return -EFAULT; 3008 } 3009 3010 return 0; 3011 } 3012 3013 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3014 { 3015 int ret; 3016 u32 reg; 3017 u8 val; 3018 3019 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3020 if (ret) 3021 return ret; 3022 3023 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_TX_CTN_SEL, mac_idx); 3024 3025 ret = read_poll_timeout(rtw89_read8, val, 3026 (val & B_AX_PTCL_TX_ON_STAT) == 0, 3027 SW_CVR_DUR_US, 3028 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3029 false, rtwdev, reg); 3030 if (ret) 3031 return ret; 3032 3033 return 0; 3034 } 3035 3036 static int band1_enable(struct rtw89_dev *rtwdev) 3037 { 3038 int ret, i; 3039 u32 sleep_bak[4] = {0}; 3040 u32 pause_bak[4] = {0}; 3041 u32 tx_en; 3042 3043 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3044 if (ret) { 3045 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3046 return ret; 3047 } 3048 3049 for (i = 0; i < 4; i++) { 3050 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3051 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3052 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3053 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3054 } 3055 3056 ret = band_idle_ck_b(rtwdev, 0); 3057 if (ret) { 3058 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3059 return ret; 3060 } 3061 3062 ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode); 3063 if (ret) { 3064 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3065 return ret; 3066 } 3067 3068 for (i = 0; i < 4; i++) { 3069 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3070 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3071 } 3072 3073 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3074 if (ret) { 3075 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3076 return ret; 3077 } 3078 3079 ret = cmac_func_en(rtwdev, 1, true); 3080 if (ret) { 3081 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3082 return ret; 3083 } 3084 3085 ret = cmac_init(rtwdev, 1); 3086 if (ret) { 3087 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3088 return ret; 3089 } 3090 3091 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3092 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3093 3094 return 0; 3095 } 3096 3097 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3098 { 3099 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3100 3101 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3102 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3103 } 3104 3105 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3106 { 3107 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3108 3109 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3110 } 3111 3112 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3113 { 3114 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3115 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3116 3117 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3118 B_AX_TX_GET_ERRPKTID_INT_EN | 3119 B_AX_TX_NXT_ERRPKTID_INT_EN | 3120 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3121 B_AX_TX_OFFSET_ERR_INT_EN | 3122 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3123 if (chip_id == RTL8852C) 3124 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3125 B_AX_TX_ETH_TYPE_ERR_EN | 3126 B_AX_TX_LLC_PRE_ERR_EN | 3127 B_AX_TX_NW_TYPE_ERR_EN | 3128 B_AX_TX_KSRCH_ERR_EN); 3129 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3130 imr->mpdu_tx_imr_set); 3131 3132 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3133 B_AX_GETPKTID_ERR_INT_EN | 3134 B_AX_MHDRLEN_ERR_INT_EN | 3135 B_AX_RPT_ERR_INT_EN); 3136 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3137 imr->mpdu_rx_imr_set); 3138 } 3139 3140 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3141 { 3142 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3143 3144 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3145 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3146 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3147 B_AX_PLE_B_PKTID_ERR_INT_EN); 3148 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3149 imr->sta_sch_imr_set); 3150 } 3151 3152 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3153 { 3154 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3155 3156 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3157 imr->txpktctl_imr_b0_clr); 3158 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3159 imr->txpktctl_imr_b0_set); 3160 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3161 imr->txpktctl_imr_b1_clr); 3162 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3163 imr->txpktctl_imr_b1_set); 3164 } 3165 3166 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3167 { 3168 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3169 3170 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3171 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3172 } 3173 3174 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3175 { 3176 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3177 3178 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3179 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3180 } 3181 3182 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3183 { 3184 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3185 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3186 } 3187 3188 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3189 { 3190 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3191 3192 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3193 imr->host_disp_imr_clr); 3194 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3195 imr->host_disp_imr_set); 3196 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3197 imr->cpu_disp_imr_clr); 3198 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3199 imr->cpu_disp_imr_set); 3200 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3201 imr->other_disp_imr_clr); 3202 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3203 imr->other_disp_imr_set); 3204 } 3205 3206 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3207 { 3208 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3209 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3210 } 3211 3212 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3213 { 3214 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3215 3216 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3217 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3218 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3219 B_AX_BBRPT_CHINFO_IMR_CLR); 3220 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3221 imr->bbrpt_err_imr_set); 3222 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3223 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3224 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3225 } 3226 3227 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3228 { 3229 u32 reg; 3230 3231 reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx); 3232 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3233 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3234 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3235 } 3236 3237 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3238 { 3239 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3240 u32 reg; 3241 3242 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx); 3243 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3244 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3245 } 3246 3247 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3248 { 3249 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3250 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3251 u32 reg; 3252 3253 reg = rtw89_mac_reg_by_idx(imr->cdma_imr_0_reg, mac_idx); 3254 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3255 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3256 3257 if (chip_id == RTL8852C) { 3258 reg = rtw89_mac_reg_by_idx(imr->cdma_imr_1_reg, mac_idx); 3259 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3260 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3261 } 3262 } 3263 3264 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3265 { 3266 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3267 u32 reg; 3268 3269 reg = rtw89_mac_reg_by_idx(imr->phy_intf_imr_reg, mac_idx); 3270 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3271 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3272 } 3273 3274 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3275 { 3276 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3277 u32 reg; 3278 3279 reg = rtw89_mac_reg_by_idx(imr->rmac_imr_reg, mac_idx); 3280 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3281 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3282 } 3283 3284 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3285 { 3286 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3287 u32 reg; 3288 3289 reg = rtw89_mac_reg_by_idx(imr->tmac_imr_reg, mac_idx); 3290 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3291 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3292 } 3293 3294 static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx, 3295 enum rtw89_mac_hwmod_sel sel) 3296 { 3297 int ret; 3298 3299 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3300 if (ret) { 3301 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3302 sel, mac_idx); 3303 return ret; 3304 } 3305 3306 if (sel == RTW89_DMAC_SEL) { 3307 rtw89_wdrls_imr_enable(rtwdev); 3308 rtw89_wsec_imr_enable(rtwdev); 3309 rtw89_mpdu_trx_imr_enable(rtwdev); 3310 rtw89_sta_sch_imr_enable(rtwdev); 3311 rtw89_txpktctl_imr_enable(rtwdev); 3312 rtw89_wde_imr_enable(rtwdev); 3313 rtw89_ple_imr_enable(rtwdev); 3314 rtw89_pktin_imr_enable(rtwdev); 3315 rtw89_dispatcher_imr_enable(rtwdev); 3316 rtw89_cpuio_imr_enable(rtwdev); 3317 rtw89_bbrpt_imr_enable(rtwdev); 3318 } else if (sel == RTW89_CMAC_SEL) { 3319 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3320 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3321 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3322 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3323 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3324 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3325 } else { 3326 return -EINVAL; 3327 } 3328 3329 return 0; 3330 } 3331 3332 static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en) 3333 { 3334 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3335 3336 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3337 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3338 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3339 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3340 if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta) 3341 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3342 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3343 } 3344 3345 static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable) 3346 { 3347 int ret = 0; 3348 3349 if (enable) { 3350 ret = band1_enable(rtwdev); 3351 if (ret) { 3352 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3353 return ret; 3354 } 3355 3356 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3357 if (ret) { 3358 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3359 return ret; 3360 } 3361 } else { 3362 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3363 return -EINVAL; 3364 } 3365 3366 return 0; 3367 } 3368 3369 static int set_host_rpr(struct rtw89_dev *rtwdev) 3370 { 3371 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3372 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3373 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3374 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3375 B_AX_RLSRPT0_FLTR_MAP_MASK); 3376 } else { 3377 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3378 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3379 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3380 B_AX_RLSRPT0_FLTR_MAP_MASK); 3381 } 3382 3383 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3384 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3385 3386 return 0; 3387 } 3388 3389 static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev) 3390 { 3391 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3392 int ret; 3393 3394 ret = dmac_init(rtwdev, 0); 3395 if (ret) { 3396 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3397 return ret; 3398 } 3399 3400 ret = cmac_init(rtwdev, 0); 3401 if (ret) { 3402 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3403 return ret; 3404 } 3405 3406 if (is_qta_dbcc(rtwdev, qta_mode)) { 3407 ret = rtw89_mac_dbcc_enable(rtwdev, true); 3408 if (ret) { 3409 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3410 return ret; 3411 } 3412 } 3413 3414 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3415 if (ret) { 3416 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3417 return ret; 3418 } 3419 3420 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3421 if (ret) { 3422 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3423 return ret; 3424 } 3425 3426 rtw89_mac_err_imr_ctrl(rtwdev, true); 3427 3428 ret = set_host_rpr(rtwdev); 3429 if (ret) { 3430 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3431 return ret; 3432 } 3433 3434 return 0; 3435 } 3436 3437 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3438 { 3439 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3440 u32 val32; 3441 3442 if (chip_id == RTL8852B || chip_id == RTL8851B) { 3443 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3444 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3445 return; 3446 } 3447 3448 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3449 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3450 3451 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3452 val32 |= B_AX_FS_WDT_INT; 3453 val32 &= ~B_AX_FS_WDT_INT_MSK; 3454 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3455 } 3456 3457 void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev) 3458 { 3459 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3460 3461 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3462 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3463 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3464 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3465 3466 rtw89_disable_fw_watchdog(rtwdev); 3467 3468 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3469 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3470 } 3471 3472 int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw) 3473 { 3474 u32 val; 3475 int ret; 3476 3477 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3478 return -EFAULT; 3479 3480 rtw89_write32(rtwdev, R_AX_UDM1, 0); 3481 rtw89_write32(rtwdev, R_AX_UDM2, 0); 3482 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3483 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3484 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3485 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3486 3487 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3488 3489 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3490 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3491 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3492 B_AX_WCPU_FWDL_STS_MASK); 3493 3494 if (dlfw) 3495 val |= B_AX_WCPU_FWDL_EN; 3496 3497 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3498 3499 if (rtwdev->chip->chip_id == RTL8852B) 3500 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 3501 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 3502 3503 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3504 boot_reason); 3505 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3506 3507 if (!dlfw) { 3508 mdelay(5); 3509 3510 ret = rtw89_fw_check_rdy(rtwdev); 3511 if (ret) 3512 return ret; 3513 } 3514 3515 return 0; 3516 } 3517 3518 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3519 { 3520 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3521 u32 val; 3522 int ret; 3523 3524 if (chip_id == RTL8852C) 3525 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3526 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3527 else 3528 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3529 B_AX_PKT_BUF_EN; 3530 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3531 3532 if (chip_id == RTL8851B) 3533 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 3534 else 3535 val = B_AX_DISPATCHER_CLK_EN; 3536 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3537 3538 if (chip_id != RTL8852C) 3539 goto dle; 3540 3541 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3542 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3543 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3544 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3545 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3546 3547 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3548 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3549 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3550 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3551 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3552 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3553 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3554 3555 dle: 3556 ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3557 if (ret) { 3558 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3559 return ret; 3560 } 3561 3562 ret = hfc_init(rtwdev, true, false, true); 3563 if (ret) { 3564 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3565 return ret; 3566 } 3567 3568 return ret; 3569 } 3570 3571 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3572 { 3573 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3574 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3575 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3576 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3577 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3578 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3579 3580 return 0; 3581 } 3582 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3583 3584 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3585 { 3586 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3587 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3588 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3589 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3590 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3591 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3592 3593 return 0; 3594 } 3595 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3596 3597 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev) 3598 { 3599 int ret; 3600 3601 ret = rtw89_mac_power_switch(rtwdev, true); 3602 if (ret) { 3603 rtw89_mac_power_switch(rtwdev, false); 3604 ret = rtw89_mac_power_switch(rtwdev, true); 3605 if (ret) 3606 return ret; 3607 } 3608 3609 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3610 3611 ret = rtw89_mac_dmac_pre_init(rtwdev); 3612 if (ret) 3613 return ret; 3614 3615 if (rtwdev->hci.ops->mac_pre_init) { 3616 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3617 if (ret) 3618 return ret; 3619 } 3620 3621 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL); 3622 if (ret) 3623 return ret; 3624 3625 return 0; 3626 } 3627 3628 int rtw89_mac_init(struct rtw89_dev *rtwdev) 3629 { 3630 int ret; 3631 3632 ret = rtw89_mac_partial_init(rtwdev); 3633 if (ret) 3634 goto fail; 3635 3636 ret = rtw89_chip_enable_bb_rf(rtwdev); 3637 if (ret) 3638 goto fail; 3639 3640 ret = rtw89_mac_sys_init(rtwdev); 3641 if (ret) 3642 goto fail; 3643 3644 ret = rtw89_mac_trx_init(rtwdev); 3645 if (ret) 3646 goto fail; 3647 3648 if (rtwdev->hci.ops->mac_post_init) { 3649 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3650 if (ret) 3651 goto fail; 3652 } 3653 3654 rtw89_fw_send_all_early_h2c(rtwdev); 3655 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3656 3657 return ret; 3658 fail: 3659 rtw89_mac_power_switch(rtwdev, false); 3660 3661 return ret; 3662 } 3663 3664 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3665 { 3666 u8 i; 3667 3668 for (i = 0; i < 4; i++) { 3669 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3670 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 3671 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 3672 } 3673 } 3674 3675 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3676 { 3677 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 3678 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 3679 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 3680 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 3681 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 3682 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 3683 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 3684 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 3685 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 3686 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 3687 } 3688 3689 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 3690 { 3691 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 3692 u8 grp = macid >> 5; 3693 int ret; 3694 3695 /* If this is called by change_interface() in the case of P2P, it could 3696 * be power-off, so ignore this operation. 3697 */ 3698 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 3699 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3700 return 0; 3701 3702 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3703 if (ret) 3704 return ret; 3705 3706 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 3707 3708 return 0; 3709 } 3710 3711 static const struct rtw89_port_reg rtw_port_base = { 3712 .port_cfg = R_AX_PORT_CFG_P0, 3713 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 3714 .bcn_area = R_AX_BCN_AREA_P0, 3715 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 3716 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 3717 .tbtt_agg = R_AX_TBTT_AGG_P0, 3718 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 3719 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 3720 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 3721 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 3722 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 3723 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 3724 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 3725 .tsftr_l = R_AX_TSFTR_LOW_P0, 3726 .tsftr_h = R_AX_TSFTR_HIGH_P0 3727 }; 3728 3729 #define BCN_INTERVAL 100 3730 #define BCN_ERLY_DEF 160 3731 #define BCN_SETUP_DEF 2 3732 #define BCN_HOLD_DEF 200 3733 #define BCN_MASK_DEF 0 3734 #define TBTT_ERLY_DEF 5 3735 #define BCN_SET_UNIT 32 3736 #define BCN_ERLY_SET_DLY (10 * 2) 3737 3738 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 3739 struct rtw89_vif *rtwvif) 3740 { 3741 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3742 const struct rtw89_port_reg *p = &rtw_port_base; 3743 3744 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 3745 return; 3746 3747 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 3748 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 3749 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 3750 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 3751 3752 msleep(vif->bss_conf.beacon_int + 1); 3753 3754 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 3755 B_AX_BRK_SETUP); 3756 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 3757 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 3758 } 3759 3760 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 3761 struct rtw89_vif *rtwvif, bool en) 3762 { 3763 const struct rtw89_port_reg *p = &rtw_port_base; 3764 3765 if (en) 3766 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3767 else 3768 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 3769 } 3770 3771 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 3772 struct rtw89_vif *rtwvif, bool en) 3773 { 3774 const struct rtw89_port_reg *p = &rtw_port_base; 3775 3776 if (en) 3777 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3778 else 3779 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 3780 } 3781 3782 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 3783 struct rtw89_vif *rtwvif) 3784 { 3785 const struct rtw89_port_reg *p = &rtw_port_base; 3786 3787 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 3788 rtwvif->net_type); 3789 } 3790 3791 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 3792 struct rtw89_vif *rtwvif) 3793 { 3794 const struct rtw89_port_reg *p = &rtw_port_base; 3795 bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 3796 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 3797 3798 if (en) 3799 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 3800 else 3801 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 3802 } 3803 3804 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 3805 struct rtw89_vif *rtwvif) 3806 { 3807 const struct rtw89_port_reg *p = &rtw_port_base; 3808 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3809 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3810 u32 bit = B_AX_RX_BSSID_FIT_EN; 3811 3812 if (en) 3813 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 3814 else 3815 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 3816 } 3817 3818 static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 3819 struct rtw89_vif *rtwvif) 3820 { 3821 const struct rtw89_port_reg *p = &rtw_port_base; 3822 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 3823 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3824 3825 if (en) 3826 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3827 else 3828 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 3829 } 3830 3831 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 3832 struct rtw89_vif *rtwvif) 3833 { 3834 const struct rtw89_port_reg *p = &rtw_port_base; 3835 bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 3836 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 3837 3838 if (en) 3839 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3840 else 3841 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 3842 } 3843 3844 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 3845 struct rtw89_vif *rtwvif) 3846 { 3847 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3848 const struct rtw89_port_reg *p = &rtw_port_base; 3849 u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 3850 3851 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 3852 bcn_int); 3853 } 3854 3855 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 3856 struct rtw89_vif *rtwvif) 3857 { 3858 static const u32 hiq_win_addr[RTW89_PORT_NUM] = { 3859 R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 3860 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 3861 R_AX_PORT_HGQ_WINDOW_CFG + 3, 3862 }; 3863 u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 3864 u8 port = rtwvif->port; 3865 u32 reg; 3866 3867 reg = rtw89_mac_reg_by_idx(hiq_win_addr[port], rtwvif->mac_idx); 3868 rtw89_write8(rtwdev, reg, win); 3869 } 3870 3871 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 3872 struct rtw89_vif *rtwvif) 3873 { 3874 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3875 const struct rtw89_port_reg *p = &rtw_port_base; 3876 u32 addr; 3877 3878 addr = rtw89_mac_reg_by_idx(R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx); 3879 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 3880 3881 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 3882 vif->bss_conf.dtim_period); 3883 } 3884 3885 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 3886 struct rtw89_vif *rtwvif) 3887 { 3888 const struct rtw89_port_reg *p = &rtw_port_base; 3889 3890 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3891 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 3892 } 3893 3894 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 3895 struct rtw89_vif *rtwvif) 3896 { 3897 const struct rtw89_port_reg *p = &rtw_port_base; 3898 3899 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 3900 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 3901 } 3902 3903 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 3904 struct rtw89_vif *rtwvif) 3905 { 3906 const struct rtw89_port_reg *p = &rtw_port_base; 3907 3908 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 3909 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 3910 } 3911 3912 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 3913 struct rtw89_vif *rtwvif) 3914 { 3915 const struct rtw89_port_reg *p = &rtw_port_base; 3916 3917 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 3918 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 3919 } 3920 3921 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 3922 struct rtw89_vif *rtwvif) 3923 { 3924 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3925 static const u32 masks[RTW89_PORT_NUM] = { 3926 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 3927 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 3928 B_AX_BSS_COLOB_AX_PORT_4_MASK, 3929 }; 3930 u8 port = rtwvif->port; 3931 u32 reg_base; 3932 u32 reg; 3933 u8 bss_color; 3934 3935 bss_color = vif->bss_conf.he_bss_color.color; 3936 reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0; 3937 reg = rtw89_mac_reg_by_idx(reg_base, rtwvif->mac_idx); 3938 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 3939 } 3940 3941 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 3942 struct rtw89_vif *rtwvif) 3943 { 3944 u8 port = rtwvif->port; 3945 u32 reg; 3946 3947 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 3948 return; 3949 3950 if (port == 0) { 3951 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_CTRL, rtwvif->mac_idx); 3952 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 3953 } 3954 } 3955 3956 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 3957 struct rtw89_vif *rtwvif) 3958 { 3959 u8 port = rtwvif->port; 3960 u32 reg; 3961 u32 val; 3962 3963 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_DROP_0, rtwvif->mac_idx); 3964 val = rtw89_read32(rtwdev, reg); 3965 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 3966 if (port == 0) 3967 val &= ~BIT(0); 3968 rtw89_write32(rtwdev, reg, val); 3969 } 3970 3971 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 3972 struct rtw89_vif *rtwvif, bool enable) 3973 { 3974 const struct rtw89_port_reg *p = &rtw_port_base; 3975 3976 if (enable) 3977 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, 3978 B_AX_PORT_FUNC_EN); 3979 else 3980 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, 3981 B_AX_PORT_FUNC_EN); 3982 } 3983 3984 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 3985 struct rtw89_vif *rtwvif) 3986 { 3987 const struct rtw89_port_reg *p = &rtw_port_base; 3988 3989 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 3990 BCN_ERLY_DEF); 3991 } 3992 3993 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 3994 struct rtw89_vif *rtwvif) 3995 { 3996 const struct rtw89_port_reg *p = &rtw_port_base; 3997 u16 val; 3998 3999 if (rtwdev->chip->chip_id != RTL8852C) 4000 return; 4001 4002 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 4003 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 4004 return; 4005 4006 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 4007 B_AX_TBTT_SHIFT_OFST_SIGN; 4008 4009 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift, 4010 B_AX_TBTT_SHIFT_OFST_MASK, val); 4011 } 4012 4013 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4014 struct rtw89_vif *rtwvif, 4015 struct rtw89_vif *rtwvif_src, 4016 u16 offset_tu) 4017 { 4018 u32 val, reg; 4019 4020 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 4021 reg = rtw89_mac_reg_by_idx(R_AX_PORT0_TSF_SYNC + rtwvif->port * 4, 4022 rtwvif->mac_idx); 4023 4024 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 4025 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 4026 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 4027 } 4028 4029 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 4030 struct rtw89_vif *rtwvif, 4031 struct rtw89_vif *rtwvif_src, 4032 u8 offset, int *n_offset) 4033 { 4034 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src) 4035 return; 4036 4037 /* adjust offset randomly to avoid beacon conflict */ 4038 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 4039 rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src, 4040 (*n_offset) * offset); 4041 4042 (*n_offset)++; 4043 } 4044 4045 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 4046 { 4047 struct rtw89_vif *src = NULL, *tmp; 4048 u8 offset = 100, vif_aps = 0; 4049 int n_offset = 1; 4050 4051 rtw89_for_each_rtwvif(rtwdev, tmp) { 4052 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4053 src = tmp; 4054 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4055 vif_aps++; 4056 } 4057 4058 if (vif_aps == 0) 4059 return; 4060 4061 offset /= (vif_aps + 1); 4062 4063 rtw89_for_each_rtwvif(rtwdev, tmp) 4064 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset); 4065 } 4066 4067 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4068 { 4069 int ret; 4070 4071 ret = rtw89_mac_port_update(rtwdev, rtwvif); 4072 if (ret) 4073 return ret; 4074 4075 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 4076 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 4077 4078 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 4079 if (ret) 4080 return ret; 4081 4082 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 4083 if (ret) 4084 return ret; 4085 4086 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true); 4087 if (ret) 4088 return ret; 4089 4090 ret = rtw89_cam_init(rtwdev, rtwvif); 4091 if (ret) 4092 return ret; 4093 4094 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4095 if (ret) 4096 return ret; 4097 4098 ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif); 4099 if (ret) 4100 return ret; 4101 4102 return 0; 4103 } 4104 4105 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4106 { 4107 int ret; 4108 4109 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 4110 if (ret) 4111 return ret; 4112 4113 rtw89_cam_deinit(rtwdev, rtwvif); 4114 4115 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4116 if (ret) 4117 return ret; 4118 4119 return 0; 4120 } 4121 4122 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4123 { 4124 u8 port = rtwvif->port; 4125 4126 if (port >= RTW89_PORT_NUM) 4127 return -EINVAL; 4128 4129 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4130 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 4131 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 4132 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 4133 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 4134 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 4135 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif); 4136 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif); 4137 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 4138 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 4139 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 4140 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 4141 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 4142 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 4143 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 4144 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 4145 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif); 4146 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 4147 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 4148 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true); 4149 rtw89_mac_port_tsf_resync_all(rtwdev); 4150 fsleep(BCN_ERLY_SET_DLY); 4151 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 4152 4153 return 0; 4154 } 4155 4156 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4157 u64 *tsf) 4158 { 4159 const struct rtw89_port_reg *p = &rtw_port_base; 4160 u32 tsf_low, tsf_high; 4161 int ret; 4162 4163 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL); 4164 if (ret) 4165 return ret; 4166 4167 tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l); 4168 tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h); 4169 *tsf = (u64)tsf_high << 32 | tsf_low; 4170 4171 return 0; 4172 } 4173 4174 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 4175 struct cfg80211_bss *bss, 4176 void *data) 4177 { 4178 const struct cfg80211_bss_ies *ies; 4179 const struct element *elem; 4180 bool *tolerated = data; 4181 4182 rcu_read_lock(); 4183 ies = rcu_dereference(bss->ies); 4184 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 4185 ies->len); 4186 4187 if (!elem || elem->datalen < 10 || 4188 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 4189 *tolerated = false; 4190 rcu_read_unlock(); 4191 } 4192 4193 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 4194 struct ieee80211_vif *vif) 4195 { 4196 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4197 struct ieee80211_hw *hw = rtwdev->hw; 4198 bool tolerated = true; 4199 u32 reg; 4200 4201 if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION) 4202 return; 4203 4204 if (!(vif->bss_conf.chandef.chan->flags & IEEE80211_CHAN_RADAR)) 4205 return; 4206 4207 cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chandef, 4208 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 4209 &tolerated); 4210 4211 reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx); 4212 if (tolerated) 4213 rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 4214 else 4215 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS); 4216 } 4217 4218 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4219 { 4220 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, false); 4221 } 4222 4223 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4224 { 4225 int ret; 4226 4227 rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 4228 RTW89_MAX_MAC_ID_NUM); 4229 if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 4230 return -ENOSPC; 4231 4232 ret = rtw89_mac_vif_init(rtwdev, rtwvif); 4233 if (ret) 4234 goto release_mac_id; 4235 4236 return 0; 4237 4238 release_mac_id: 4239 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4240 4241 return ret; 4242 } 4243 4244 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4245 { 4246 int ret; 4247 4248 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 4249 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id); 4250 4251 return ret; 4252 } 4253 4254 static void 4255 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4256 { 4257 } 4258 4259 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 4260 { 4261 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 4262 4263 return band == op->band_type && channel == op->primary_channel; 4264 } 4265 4266 static void 4267 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4268 u32 len) 4269 { 4270 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 4271 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 4272 struct rtw89_chan new; 4273 u8 reason, status, tx_fail, band, actual_period; 4274 u32 last_chan = rtwdev->scan_info.last_chan_idx; 4275 u16 chan; 4276 int ret; 4277 4278 if (!rtwvif) 4279 return; 4280 4281 tx_fail = RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h->data); 4282 status = RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h->data); 4283 chan = RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h->data); 4284 reason = RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h->data); 4285 band = RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h->data); 4286 actual_period = RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h->data); 4287 4288 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 4289 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 4290 4291 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4292 "band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 4293 band, chan, reason, status, tx_fail, actual_period); 4294 4295 switch (reason) { 4296 case RTW89_SCAN_LEAVE_CH_NOTIFY: 4297 if (rtw89_is_op_chan(rtwdev, band, chan)) 4298 ieee80211_stop_queues(rtwdev->hw); 4299 return; 4300 case RTW89_SCAN_END_SCAN_NOTIFY: 4301 if (rtwvif && rtwvif->scan_req && 4302 last_chan < rtwvif->scan_req->n_channels) { 4303 ret = rtw89_hw_scan_offload(rtwdev, vif, true); 4304 if (ret) { 4305 rtw89_hw_scan_abort(rtwdev, vif); 4306 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 4307 } 4308 } else { 4309 rtw89_hw_scan_complete(rtwdev, vif, false); 4310 } 4311 break; 4312 case RTW89_SCAN_ENTER_CH_NOTIFY: 4313 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4314 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4315 &rtwdev->scan_info.op_chan); 4316 ieee80211_wake_queues(rtwdev->hw); 4317 } else { 4318 rtw89_chan_create(&new, chan, chan, band, 4319 RTW89_CHANNEL_WIDTH_20); 4320 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx, 4321 &new); 4322 } 4323 break; 4324 default: 4325 return; 4326 } 4327 } 4328 4329 static void 4330 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4331 struct sk_buff *skb) 4332 { 4333 struct ieee80211_vif *vif = rtwvif_to_vif_safe(rtwvif); 4334 enum nl80211_cqm_rssi_threshold_event nl_event; 4335 const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 4336 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 4337 u8 type, event, mac_id; 4338 s8 sig; 4339 4340 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 4341 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 4342 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 4343 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 4344 4345 if (mac_id != rtwvif->mac_id) 4346 return; 4347 4348 rtw89_debug(rtwdev, RTW89_DBG_FW, 4349 "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 4350 mac_id, type, sig, event); 4351 4352 switch (type) { 4353 case RTW89_BCN_FLTR_BEACON_LOSS: 4354 if (!rtwdev->scanning && !rtwvif->offchan) 4355 ieee80211_connection_loss(vif); 4356 else 4357 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 4358 return; 4359 case RTW89_BCN_FLTR_NOTIFY: 4360 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4361 break; 4362 case RTW89_BCN_FLTR_RSSI: 4363 if (event == RTW89_BCN_FLTR_RSSI_LOW) 4364 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 4365 else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 4366 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4367 else 4368 return; 4369 break; 4370 default: 4371 return; 4372 } 4373 4374 ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 4375 } 4376 4377 static void 4378 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4379 u32 len) 4380 { 4381 struct rtw89_vif *rtwvif; 4382 4383 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4384 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif, c2h); 4385 } 4386 4387 static void 4388 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4389 { 4390 /* N.B. This will run in interrupt context. */ 4391 4392 rtw89_debug(rtwdev, RTW89_DBG_FW, 4393 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 4394 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 4395 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 4396 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 4397 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 4398 } 4399 4400 static void 4401 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 4402 { 4403 /* N.B. This will run in interrupt context. */ 4404 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 4405 const struct rtw89_c2h_done_ack *c2h = 4406 (const struct rtw89_c2h_done_ack *)skb_c2h->data; 4407 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 4408 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 4409 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 4410 u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 4411 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 4412 struct rtw89_completion_data data = {}; 4413 unsigned int cond; 4414 4415 rtw89_debug(rtwdev, RTW89_DBG_FW, 4416 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 4417 h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 4418 4419 if (h2c_cat != H2C_CAT_MAC) 4420 return; 4421 4422 switch (h2c_class) { 4423 default: 4424 return; 4425 case H2C_CL_MAC_FW_OFLD: 4426 switch (h2c_func) { 4427 default: 4428 return; 4429 case H2C_FUNC_ADD_SCANOFLD_CH: 4430 case H2C_FUNC_SCANOFLD: 4431 cond = RTW89_FW_OFLD_WAIT_COND(0, h2c_func); 4432 break; 4433 } 4434 4435 data.err = !!h2c_return; 4436 rtw89_complete_cond(fw_ofld_wait, cond, &data); 4437 return; 4438 } 4439 } 4440 4441 static void 4442 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4443 { 4444 rtw89_info(rtwdev, "%*s", RTW89_GET_C2H_LOG_LEN(len), 4445 RTW89_GET_C2H_LOG_SRT_PRT(c2h->data)); 4446 } 4447 4448 static void 4449 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4450 { 4451 } 4452 4453 static void 4454 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 4455 u32 len) 4456 { 4457 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 4458 const struct rtw89_c2h_pkt_ofld_rsp *c2h = 4459 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 4460 u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 4461 u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 4462 u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 4463 struct rtw89_completion_data data = {}; 4464 unsigned int cond; 4465 4466 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", 4467 pkt_id, pkt_op, pkt_len); 4468 4469 data.err = !pkt_len; 4470 cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 4471 4472 rtw89_complete_cond(wait, cond, &data); 4473 } 4474 4475 static void 4476 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4477 u32 len) 4478 { 4479 } 4480 4481 static void 4482 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4483 { 4484 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 4485 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 4486 4487 switch (func) { 4488 case H2C_FUNC_ADD_MCC: 4489 case H2C_FUNC_START_MCC: 4490 case H2C_FUNC_STOP_MCC: 4491 case H2C_FUNC_DEL_MCC_GROUP: 4492 case H2C_FUNC_RESET_MCC_GROUP: 4493 case H2C_FUNC_MCC_REQ_TSF: 4494 case H2C_FUNC_MCC_MACID_BITMAP: 4495 case H2C_FUNC_MCC_SYNC: 4496 case H2C_FUNC_MCC_SET_DURATION: 4497 break; 4498 default: 4499 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4500 "invalid MCC C2H RCV ACK: func %d\n", func); 4501 return; 4502 } 4503 4504 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4505 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 4506 } 4507 4508 static void 4509 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4510 { 4511 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 4512 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 4513 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 4514 struct rtw89_completion_data data = {}; 4515 unsigned int cond; 4516 bool next = false; 4517 4518 switch (func) { 4519 case H2C_FUNC_MCC_REQ_TSF: 4520 next = true; 4521 break; 4522 case H2C_FUNC_MCC_MACID_BITMAP: 4523 case H2C_FUNC_MCC_SYNC: 4524 case H2C_FUNC_MCC_SET_DURATION: 4525 break; 4526 case H2C_FUNC_ADD_MCC: 4527 case H2C_FUNC_START_MCC: 4528 case H2C_FUNC_STOP_MCC: 4529 case H2C_FUNC_DEL_MCC_GROUP: 4530 case H2C_FUNC_RESET_MCC_GROUP: 4531 default: 4532 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4533 "invalid MCC C2H REQ ACK: func %d\n", func); 4534 return; 4535 } 4536 4537 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4538 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 4539 group, func, retcode); 4540 4541 if (!retcode && next) 4542 return; 4543 4544 data.err = !!retcode; 4545 cond = RTW89_MCC_WAIT_COND(group, func); 4546 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4547 } 4548 4549 static void 4550 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4551 { 4552 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 4553 struct rtw89_completion_data data = {}; 4554 struct rtw89_mac_mcc_tsf_rpt *rpt; 4555 unsigned int cond; 4556 4557 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 4558 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 4559 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 4560 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 4561 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 4562 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 4563 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 4564 4565 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4566 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 4567 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 4568 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 4569 4570 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 4571 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4572 } 4573 4574 static void 4575 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4576 { 4577 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 4578 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 4579 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 4580 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 4581 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 4582 struct rtw89_completion_data data = {}; 4583 unsigned int cond; 4584 bool rsp = true; 4585 bool err; 4586 u8 func; 4587 4588 switch (status) { 4589 case RTW89_MAC_MCC_ADD_ROLE_OK: 4590 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 4591 func = H2C_FUNC_ADD_MCC; 4592 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 4593 break; 4594 case RTW89_MAC_MCC_START_GROUP_OK: 4595 case RTW89_MAC_MCC_START_GROUP_FAIL: 4596 func = H2C_FUNC_START_MCC; 4597 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 4598 break; 4599 case RTW89_MAC_MCC_STOP_GROUP_OK: 4600 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 4601 func = H2C_FUNC_STOP_MCC; 4602 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 4603 break; 4604 case RTW89_MAC_MCC_DEL_GROUP_OK: 4605 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 4606 func = H2C_FUNC_DEL_MCC_GROUP; 4607 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 4608 break; 4609 case RTW89_MAC_MCC_RESET_GROUP_OK: 4610 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 4611 func = H2C_FUNC_RESET_MCC_GROUP; 4612 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 4613 break; 4614 case RTW89_MAC_MCC_SWITCH_CH_OK: 4615 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 4616 case RTW89_MAC_MCC_TXNULL0_OK: 4617 case RTW89_MAC_MCC_TXNULL0_FAIL: 4618 case RTW89_MAC_MCC_TXNULL1_OK: 4619 case RTW89_MAC_MCC_TXNULL1_FAIL: 4620 case RTW89_MAC_MCC_SWITCH_EARLY: 4621 case RTW89_MAC_MCC_TBTT: 4622 case RTW89_MAC_MCC_DURATION_START: 4623 case RTW89_MAC_MCC_DURATION_END: 4624 rsp = false; 4625 break; 4626 default: 4627 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4628 "invalid MCC C2H STS RPT: status %d\n", status); 4629 return; 4630 } 4631 4632 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 4633 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 4634 group, macid, status, (u64)tsf_high << 32 | tsf_low); 4635 4636 if (!rsp) 4637 return; 4638 4639 data.err = err; 4640 cond = RTW89_MCC_WAIT_COND(group, func); 4641 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 4642 } 4643 4644 static 4645 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 4646 struct sk_buff *c2h, u32 len) = { 4647 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 4648 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 4649 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 4650 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 4651 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 4652 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 4653 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 4654 [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 4655 }; 4656 4657 static 4658 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 4659 struct sk_buff *c2h, u32 len) = { 4660 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 4661 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 4662 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 4663 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 4664 }; 4665 4666 static 4667 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 4668 struct sk_buff *c2h, u32 len) = { 4669 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 4670 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 4671 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 4672 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 4673 }; 4674 4675 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func) 4676 { 4677 switch (class) { 4678 default: 4679 return false; 4680 case RTW89_MAC_C2H_CLASS_INFO: 4681 switch (func) { 4682 default: 4683 return false; 4684 case RTW89_MAC_C2H_FUNC_REC_ACK: 4685 case RTW89_MAC_C2H_FUNC_DONE_ACK: 4686 return true; 4687 } 4688 case RTW89_MAC_C2H_CLASS_OFLD: 4689 switch (func) { 4690 default: 4691 return false; 4692 case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 4693 return true; 4694 } 4695 case RTW89_MAC_C2H_CLASS_MCC: 4696 return true; 4697 } 4698 } 4699 4700 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4701 u32 len, u8 class, u8 func) 4702 { 4703 void (*handler)(struct rtw89_dev *rtwdev, 4704 struct sk_buff *c2h, u32 len) = NULL; 4705 4706 switch (class) { 4707 case RTW89_MAC_C2H_CLASS_INFO: 4708 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 4709 handler = rtw89_mac_c2h_info_handler[func]; 4710 break; 4711 case RTW89_MAC_C2H_CLASS_OFLD: 4712 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 4713 handler = rtw89_mac_c2h_ofld_handler[func]; 4714 break; 4715 case RTW89_MAC_C2H_CLASS_MCC: 4716 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 4717 handler = rtw89_mac_c2h_mcc_handler[func]; 4718 break; 4719 case RTW89_MAC_C2H_CLASS_FWDBG: 4720 return; 4721 default: 4722 rtw89_info(rtwdev, "c2h class %d not support\n", class); 4723 return; 4724 } 4725 if (!handler) { 4726 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 4727 func); 4728 return; 4729 } 4730 handler(rtwdev, skb, len); 4731 } 4732 4733 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev, 4734 enum rtw89_phy_idx phy_idx, 4735 u32 reg_base, u32 *cr) 4736 { 4737 const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem; 4738 enum rtw89_qta_mode mode = dle_mem->mode; 4739 u32 addr = rtw89_mac_reg_by_idx(reg_base, phy_idx); 4740 4741 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) { 4742 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 4743 addr); 4744 goto error; 4745 } 4746 4747 if (addr >= CMAC1_START_ADDR && addr <= CMAC1_END_ADDR) 4748 if (mode == RTW89_QTA_SCC) { 4749 rtw89_err(rtwdev, 4750 "[TXPWR] addr=0x%x but hw not enable\n", 4751 addr); 4752 goto error; 4753 } 4754 4755 *cr = addr; 4756 return true; 4757 4758 error: 4759 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 4760 addr, phy_idx); 4761 4762 return false; 4763 } 4764 EXPORT_SYMBOL(rtw89_mac_get_txpwr_cr); 4765 4766 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 4767 { 4768 u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx); 4769 int ret; 4770 4771 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 4772 if (ret) 4773 return ret; 4774 4775 if (!enable) { 4776 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 4777 return 0; 4778 } 4779 4780 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 4781 B_AX_APP_MAC_INFO_RPT | 4782 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 4783 B_AX_PPDU_STAT_RPT_CRC32); 4784 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 4785 RTW89_PRPT_DEST_HOST); 4786 4787 return 0; 4788 } 4789 EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status); 4790 4791 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 4792 { 4793 #define MAC_AX_TIME_TH_SH 5 4794 #define MAC_AX_LEN_TH_SH 4 4795 #define MAC_AX_TIME_TH_MAX 255 4796 #define MAC_AX_LEN_TH_MAX 255 4797 #define MAC_AX_TIME_TH_DEF 88 4798 #define MAC_AX_LEN_TH_DEF 4080 4799 struct ieee80211_hw *hw = rtwdev->hw; 4800 u32 rts_threshold = hw->wiphy->rts_threshold; 4801 u32 time_th, len_th; 4802 u32 reg; 4803 4804 if (rts_threshold == (u32)-1) { 4805 time_th = MAC_AX_TIME_TH_DEF; 4806 len_th = MAC_AX_LEN_TH_DEF; 4807 } else { 4808 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 4809 len_th = rts_threshold; 4810 } 4811 4812 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 4813 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 4814 4815 reg = rtw89_mac_reg_by_idx(R_AX_AGG_LEN_HT_0, mac_idx); 4816 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 4817 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 4818 } 4819 4820 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 4821 { 4822 bool empty; 4823 int ret; 4824 4825 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4826 return; 4827 4828 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 4829 10000, 200000, false, rtwdev); 4830 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 4831 rtw89_info(rtwdev, "timed out to flush queues\n"); 4832 } 4833 4834 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 4835 { 4836 u8 val; 4837 u16 val16; 4838 u32 val32; 4839 int ret; 4840 4841 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 4842 if (rtwdev->chip->chip_id != RTL8851B) 4843 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 4844 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 4845 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 4846 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 4847 if (rtwdev->chip->chip_id != RTL8851B) 4848 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 4849 4850 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 4851 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 4852 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 4853 4854 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 4855 if (ret) { 4856 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 4857 return ret; 4858 } 4859 val32 = val32 & B_AX_WL_RX_CTRL; 4860 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 4861 if (ret) { 4862 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 4863 return ret; 4864 } 4865 4866 switch (coex->pta_mode) { 4867 case RTW89_MAC_AX_COEX_RTK_MODE: 4868 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4869 val &= ~B_AX_BTMODE_MASK; 4870 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 4871 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4872 4873 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 4874 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 4875 4876 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 4877 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 4878 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 4879 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 4880 break; 4881 case RTW89_MAC_AX_COEX_CSR_MODE: 4882 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 4883 val &= ~B_AX_BTMODE_MASK; 4884 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 4885 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 4886 4887 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 4888 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 4889 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 4890 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 4891 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 4892 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 4893 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 4894 val16 |= B_AX_ENHANCED_BT; 4895 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 4896 4897 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 4898 break; 4899 default: 4900 return -EINVAL; 4901 } 4902 4903 switch (coex->direction) { 4904 case RTW89_MAC_AX_COEX_INNER: 4905 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4906 val = (val & ~BIT(2)) | BIT(1); 4907 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4908 break; 4909 case RTW89_MAC_AX_COEX_OUTPUT: 4910 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4911 val = val | BIT(1) | BIT(0); 4912 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4913 break; 4914 case RTW89_MAC_AX_COEX_INPUT: 4915 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 4916 val = val & ~(BIT(2) | BIT(1)); 4917 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 4918 break; 4919 default: 4920 return -EINVAL; 4921 } 4922 4923 return 0; 4924 } 4925 EXPORT_SYMBOL(rtw89_mac_coex_init); 4926 4927 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 4928 const struct rtw89_mac_ax_coex *coex) 4929 { 4930 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 4931 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 4932 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 4933 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 4934 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 4935 4936 switch (coex->pta_mode) { 4937 case RTW89_MAC_AX_COEX_RTK_MODE: 4938 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4939 MAC_AX_RTK_MODE); 4940 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 4941 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 4942 break; 4943 case RTW89_MAC_AX_COEX_CSR_MODE: 4944 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 4945 MAC_AX_CSR_MODE); 4946 break; 4947 default: 4948 return -EINVAL; 4949 } 4950 4951 return 0; 4952 } 4953 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 4954 4955 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 4956 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4957 { 4958 u32 val = 0, ret; 4959 4960 if (gnt_cfg->band[0].gnt_bt) 4961 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 4962 4963 if (gnt_cfg->band[0].gnt_bt_sw_en) 4964 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 4965 4966 if (gnt_cfg->band[0].gnt_wl) 4967 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 4968 4969 if (gnt_cfg->band[0].gnt_wl_sw_en) 4970 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 4971 4972 if (gnt_cfg->band[1].gnt_bt) 4973 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 4974 4975 if (gnt_cfg->band[1].gnt_bt_sw_en) 4976 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 4977 4978 if (gnt_cfg->band[1].gnt_wl) 4979 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 4980 4981 if (gnt_cfg->band[1].gnt_wl_sw_en) 4982 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 4983 4984 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 4985 if (ret) { 4986 rtw89_err(rtwdev, "Write LTE fail!\n"); 4987 return ret; 4988 } 4989 4990 return 0; 4991 } 4992 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 4993 4994 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 4995 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4996 { 4997 u32 val = 0; 4998 4999 if (gnt_cfg->band[0].gnt_bt) 5000 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 5001 B_AX_GNT_BT_TX_VAL; 5002 else 5003 val |= B_AX_WL_ACT_VAL; 5004 5005 if (gnt_cfg->band[0].gnt_bt_sw_en) 5006 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5007 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5008 5009 if (gnt_cfg->band[0].gnt_wl) 5010 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 5011 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5012 5013 if (gnt_cfg->band[0].gnt_wl_sw_en) 5014 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5015 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5016 5017 if (gnt_cfg->band[1].gnt_bt) 5018 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 5019 B_AX_GNT_BT_TX_VAL; 5020 else 5021 val |= B_AX_WL_ACT_VAL; 5022 5023 if (gnt_cfg->band[1].gnt_bt_sw_en) 5024 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5025 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5026 5027 if (gnt_cfg->band[1].gnt_wl) 5028 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 5029 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5030 5031 if (gnt_cfg->band[1].gnt_wl_sw_en) 5032 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5033 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5034 5035 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 5036 5037 return 0; 5038 } 5039 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 5040 5041 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 5042 { 5043 u32 reg; 5044 u16 val; 5045 int ret; 5046 5047 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 5048 if (ret) 5049 return ret; 5050 5051 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, plt->band); 5052 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 5053 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 5054 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 5055 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 5056 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 5057 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 5058 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 5059 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 5060 B_AX_PLT_EN; 5061 rtw89_write16(rtwdev, reg, val); 5062 5063 return 0; 5064 } 5065 5066 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 5067 { 5068 u32 fw_sb; 5069 5070 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5071 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 5072 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 5073 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5074 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 5075 else 5076 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 5077 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 5078 val = B_AX_TOGGLE | 5079 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 5080 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 5081 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 5082 fsleep(1000); /* avoid BT FW loss information */ 5083 } 5084 5085 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 5086 { 5087 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5088 } 5089 5090 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5091 { 5092 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 5093 5094 val = wl ? val | BIT(2) : val & ~BIT(2); 5095 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 5096 5097 return 0; 5098 } 5099 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 5100 5101 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 5102 { 5103 struct rtw89_btc *btc = &rtwdev->btc; 5104 struct rtw89_btc_dm *dm = &btc->dm; 5105 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 5106 int i; 5107 5108 if (wl) 5109 return 0; 5110 5111 for (i = 0; i < RTW89_PHY_MAX; i++) { 5112 g[i].gnt_bt_sw_en = 1; 5113 g[i].gnt_bt = 1; 5114 g[i].gnt_wl_sw_en = 1; 5115 g[i].gnt_wl = 0; 5116 } 5117 5118 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 5119 } 5120 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 5121 5122 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 5123 { 5124 const struct rtw89_chip_info *chip = rtwdev->chip; 5125 u8 val = 0; 5126 5127 if (chip->chip_id == RTL8852C) 5128 return false; 5129 else if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) 5130 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 5131 B_AX_LTE_MUX_CTRL_PATH >> 24); 5132 5133 return !!val; 5134 } 5135 5136 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) 5137 { 5138 u32 reg; 5139 u16 cnt; 5140 5141 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, band); 5142 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 5143 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 5144 5145 return cnt; 5146 } 5147 5148 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 5149 bool keep) 5150 { 5151 u32 reg; 5152 5153 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 5154 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 5155 if (keep) { 5156 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5157 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5158 BFRP_RX_STANDBY_TIMER_KEEP); 5159 } else { 5160 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5161 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5162 BFRP_RX_STANDBY_TIMER_RELEASE); 5163 } 5164 } 5165 5166 static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 5167 { 5168 u32 reg; 5169 u32 mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 5170 B_AX_BFMEE_HE_NDPA_EN; 5171 5172 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 5173 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 5174 if (en) { 5175 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5176 rtw89_write32_set(rtwdev, reg, mask); 5177 } else { 5178 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5179 rtw89_write32_clr(rtwdev, reg, mask); 5180 } 5181 } 5182 5183 static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx) 5184 { 5185 u32 reg; 5186 u32 val32; 5187 int ret; 5188 5189 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5190 if (ret) 5191 return ret; 5192 5193 /* AP mode set tx gid to 63 */ 5194 /* STA mode set tx gid to 0(default) */ 5195 reg = rtw89_mac_reg_by_idx(R_AX_BFMER_CTRL_0, mac_idx); 5196 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 5197 5198 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 5199 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 5200 5201 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx); 5202 val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 5203 rtw89_write32(rtwdev, reg, val32); 5204 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 5205 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 5206 5207 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5208 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 5209 B_AX_BFMEE_USE_NSTS | 5210 B_AX_BFMEE_CSI_GID_SEL | 5211 B_AX_BFMEE_CSI_FORCE_RETE_EN); 5212 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 5213 rtw89_write32(rtwdev, reg, 5214 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 5215 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 5216 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 5217 5218 reg = rtw89_mac_reg_by_idx(R_AX_CSIRPT_OPTION, mac_idx); 5219 rtw89_write32_set(rtwdev, reg, 5220 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 5221 5222 return 0; 5223 } 5224 5225 static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev, 5226 struct ieee80211_vif *vif, 5227 struct ieee80211_sta *sta) 5228 { 5229 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5230 u8 mac_idx = rtwvif->mac_idx; 5231 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 5232 u8 port_sel = rtwvif->port; 5233 u8 sound_dim = 3, t; 5234 u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 5235 u32 reg; 5236 u16 val; 5237 int ret; 5238 5239 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5240 if (ret) 5241 return ret; 5242 5243 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5244 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 5245 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 5246 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 5247 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 5248 phy_cap[5]); 5249 sound_dim = min(sound_dim, t); 5250 } 5251 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5252 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 5253 ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 5254 stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 5255 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 5256 sta->deflink.vht_cap.cap); 5257 sound_dim = min(sound_dim, t); 5258 } 5259 nc = min(nc, sound_dim); 5260 nr = min(nr, sound_dim); 5261 5262 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5263 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5264 5265 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 5266 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 5267 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 5268 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 5269 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 5270 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 5271 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 5272 5273 if (port_sel == 0) 5274 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5275 else 5276 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 5277 5278 rtw89_write16(rtwdev, reg, val); 5279 5280 return 0; 5281 } 5282 5283 static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev, 5284 struct ieee80211_vif *vif, 5285 struct ieee80211_sta *sta) 5286 { 5287 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5288 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 5289 u32 reg; 5290 u8 mac_idx = rtwvif->mac_idx; 5291 int ret; 5292 5293 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5294 if (ret) 5295 return ret; 5296 5297 if (sta->deflink.he_cap.has_he) { 5298 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 5299 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 5300 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 5301 } 5302 if (sta->deflink.vht_cap.vht_supported) { 5303 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 5304 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 5305 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 5306 } 5307 if (sta->deflink.ht_cap.ht_supported) { 5308 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 5309 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 5310 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 5311 } 5312 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5313 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5314 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 5315 rtw89_write32(rtwdev, 5316 rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 5317 rrsc); 5318 5319 return 0; 5320 } 5321 5322 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5323 struct ieee80211_sta *sta) 5324 { 5325 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5326 5327 if (rtw89_sta_has_beamformer_cap(sta)) { 5328 rtw89_debug(rtwdev, RTW89_DBG_BF, 5329 "initialize bfee for new association\n"); 5330 rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx); 5331 rtw89_mac_set_csi_para_reg(rtwdev, vif, sta); 5332 rtw89_mac_csi_rrsc(rtwdev, vif, sta); 5333 } 5334 } 5335 5336 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5337 struct ieee80211_sta *sta) 5338 { 5339 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5340 5341 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 5342 } 5343 5344 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5345 struct ieee80211_bss_conf *conf) 5346 { 5347 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5348 u8 mac_idx = rtwvif->mac_idx; 5349 __le32 *p; 5350 5351 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 5352 5353 p = (__le32 *)conf->mu_group.membership; 5354 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx), 5355 le32_to_cpu(p[0])); 5356 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx), 5357 le32_to_cpu(p[1])); 5358 5359 p = (__le32 *)conf->mu_group.position; 5360 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx), 5361 le32_to_cpu(p[0])); 5362 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx), 5363 le32_to_cpu(p[1])); 5364 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx), 5365 le32_to_cpu(p[2])); 5366 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx), 5367 le32_to_cpu(p[3])); 5368 } 5369 5370 struct rtw89_mac_bf_monitor_iter_data { 5371 struct rtw89_dev *rtwdev; 5372 struct ieee80211_sta *down_sta; 5373 int count; 5374 }; 5375 5376 static 5377 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 5378 { 5379 struct rtw89_mac_bf_monitor_iter_data *iter_data = 5380 (struct rtw89_mac_bf_monitor_iter_data *)data; 5381 struct ieee80211_sta *down_sta = iter_data->down_sta; 5382 int *count = &iter_data->count; 5383 5384 if (down_sta == sta) 5385 return; 5386 5387 if (rtw89_sta_has_beamformer_cap(sta)) 5388 (*count)++; 5389 } 5390 5391 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 5392 struct ieee80211_sta *sta, bool disconnect) 5393 { 5394 struct rtw89_mac_bf_monitor_iter_data data; 5395 5396 data.rtwdev = rtwdev; 5397 data.down_sta = disconnect ? sta : NULL; 5398 data.count = 0; 5399 ieee80211_iterate_stations_atomic(rtwdev->hw, 5400 rtw89_mac_bf_monitor_calc_iter, 5401 &data); 5402 5403 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 5404 if (data.count) 5405 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5406 else 5407 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 5408 } 5409 5410 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 5411 { 5412 struct rtw89_traffic_stats *stats = &rtwdev->stats; 5413 struct rtw89_vif *rtwvif; 5414 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 5415 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5416 bool keep_timer = true; 5417 bool old_keep_timer; 5418 5419 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5420 5421 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 5422 keep_timer = false; 5423 5424 if (keep_timer != old_keep_timer) { 5425 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5426 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx, 5427 keep_timer); 5428 } 5429 5430 if (en == old) 5431 return; 5432 5433 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5434 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 5435 } 5436 5437 static int 5438 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5439 u32 tx_time) 5440 { 5441 #define MAC_AX_DFLT_TX_TIME 5280 5442 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5443 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 5444 u32 reg; 5445 int ret = 0; 5446 5447 if (rtwsta->cctl_tx_time) { 5448 rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 5449 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5450 } else { 5451 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5452 if (ret) { 5453 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 5454 return ret; 5455 } 5456 5457 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 5458 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 5459 max_tx_time >> 5); 5460 } 5461 5462 return ret; 5463 } 5464 5465 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5466 bool resume, u32 tx_time) 5467 { 5468 int ret = 0; 5469 5470 if (!resume) { 5471 rtwsta->cctl_tx_time = true; 5472 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5473 } else { 5474 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 5475 rtwsta->cctl_tx_time = false; 5476 } 5477 5478 return ret; 5479 } 5480 5481 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 5482 u32 *tx_time) 5483 { 5484 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5485 u32 reg; 5486 int ret = 0; 5487 5488 if (rtwsta->cctl_tx_time) { 5489 *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 5490 } else { 5491 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5492 if (ret) { 5493 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 5494 return ret; 5495 } 5496 5497 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx); 5498 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 5499 } 5500 5501 return ret; 5502 } 5503 5504 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 5505 struct rtw89_sta *rtwsta, 5506 bool resume, u8 tx_retry) 5507 { 5508 int ret = 0; 5509 5510 rtwsta->data_tx_cnt_lmt = tx_retry; 5511 5512 if (!resume) { 5513 rtwsta->cctl_tx_retry_limit = true; 5514 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5515 } else { 5516 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 5517 rtwsta->cctl_tx_retry_limit = false; 5518 } 5519 5520 return ret; 5521 } 5522 5523 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 5524 struct rtw89_sta *rtwsta, u8 *tx_retry) 5525 { 5526 u8 mac_idx = rtwsta->rtwvif->mac_idx; 5527 u32 reg; 5528 int ret = 0; 5529 5530 if (rtwsta->cctl_tx_retry_limit) { 5531 *tx_retry = rtwsta->data_tx_cnt_lmt; 5532 } else { 5533 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5534 if (ret) { 5535 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 5536 return ret; 5537 } 5538 5539 reg = rtw89_mac_reg_by_idx(R_AX_TXCNT, mac_idx); 5540 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 5541 } 5542 5543 return ret; 5544 } 5545 5546 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 5547 struct rtw89_vif *rtwvif, bool en) 5548 { 5549 u8 mac_idx = rtwvif->mac_idx; 5550 u16 set = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0; 5551 u32 reg; 5552 u32 ret; 5553 5554 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5555 if (ret) 5556 return ret; 5557 5558 reg = rtw89_mac_reg_by_idx(R_AX_MUEDCA_EN, mac_idx); 5559 if (en) 5560 rtw89_write16_set(rtwdev, reg, set); 5561 else 5562 rtw89_write16_clr(rtwdev, reg, set); 5563 5564 return 0; 5565 } 5566 5567 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 5568 { 5569 u32 val32; 5570 int ret; 5571 5572 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 5573 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 5574 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 5575 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 5576 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 5577 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 5578 5579 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 5580 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 5581 if (ret) { 5582 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 5583 offset, val, mask); 5584 return ret; 5585 } 5586 5587 return 0; 5588 } 5589 EXPORT_SYMBOL(rtw89_mac_write_xtal_si); 5590 5591 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 5592 { 5593 u32 val32; 5594 int ret; 5595 5596 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 5597 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 5598 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 5599 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 5600 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 5601 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 5602 5603 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 5604 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 5605 if (ret) { 5606 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 5607 return ret; 5608 } 5609 5610 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 5611 5612 return 0; 5613 } 5614 EXPORT_SYMBOL(rtw89_mac_read_xtal_si); 5615 5616 static 5617 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 5618 { 5619 static const enum rtw89_pkt_drop_sel sels[] = { 5620 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 5621 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 5622 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 5623 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 5624 }; 5625 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5626 struct rtw89_pkt_drop_params params = {0}; 5627 int i; 5628 5629 params.mac_band = RTW89_MAC_0; 5630 params.macid = rtwsta->mac_id; 5631 params.port = rtwvif->port; 5632 params.mbssid = 0; 5633 params.tf_trs = rtwvif->trigger; 5634 5635 for (i = 0; i < ARRAY_SIZE(sels); i++) { 5636 params.sel = sels[i]; 5637 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 5638 } 5639 } 5640 5641 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 5642 { 5643 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 5644 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5645 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 5646 struct rtw89_vif *target = data; 5647 5648 if (rtwvif != target) 5649 return; 5650 5651 rtw89_mac_pkt_drop_sta(rtwdev, rtwsta); 5652 } 5653 5654 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 5655 { 5656 ieee80211_iterate_stations_atomic(rtwdev->hw, 5657 rtw89_mac_pkt_drop_vif_iter, 5658 rtwvif); 5659 } 5660 5661 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 5662 enum rtw89_mac_idx band) 5663 { 5664 struct rtw89_pkt_drop_params params = {0}; 5665 bool empty; 5666 int i, ret = 0, try_cnt = 3; 5667 5668 params.mac_band = band; 5669 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 5670 5671 for (i = 0; i < try_cnt; i++) { 5672 ret = read_poll_timeout(mac_is_txq_empty, empty, empty, 50, 5673 50000, false, rtwdev); 5674 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 5675 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 5676 else 5677 return 0; 5678 } 5679 return ret; 5680 } 5681