1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020  Realtek Corporation
3  */
4 
5 #ifndef __RTW89_FW_H__
6 #define __RTW89_FW_H__
7 
8 #include "core.h"
9 
10 enum rtw89_fw_dl_status {
11 	RTW89_FWDL_INITIAL_STATE = 0,
12 	RTW89_FWDL_FWDL_ONGOING = 1,
13 	RTW89_FWDL_CHECKSUM_FAIL = 2,
14 	RTW89_FWDL_SECURITY_FAIL = 3,
15 	RTW89_FWDL_CV_NOT_MATCH = 4,
16 	RTW89_FWDL_RSVD0 = 5,
17 	RTW89_FWDL_WCPU_FWDL_RDY = 6,
18 	RTW89_FWDL_WCPU_FW_INIT_RDY = 7
19 };
20 
21 #define RTW89_GET_C2H_HDR_FUNC(info) \
22 	u32_get_bits(info, GENMASK(6, 0))
23 #define RTW89_GET_C2H_HDR_LEN(info) \
24 	u32_get_bits(info, GENMASK(11, 8))
25 
26 #define RTW89_SET_H2CREG_HDR_FUNC(info, val) \
27 	u32p_replace_bits(info, val, GENMASK(6, 0))
28 #define RTW89_SET_H2CREG_HDR_LEN(info, val) \
29 	u32p_replace_bits(info, val, GENMASK(11, 8))
30 
31 #define RTW89_H2CREG_MAX 4
32 #define RTW89_C2HREG_MAX 4
33 #define RTW89_C2HREG_HDR_LEN 2
34 #define RTW89_H2CREG_HDR_LEN 2
35 #define RTW89_C2H_TIMEOUT 1000000
36 struct rtw89_mac_c2h_info {
37 	u8 id;
38 	u8 content_len;
39 	u32 c2hreg[RTW89_C2HREG_MAX];
40 };
41 
42 struct rtw89_mac_h2c_info {
43 	u8 id;
44 	u8 content_len;
45 	u32 h2creg[RTW89_H2CREG_MAX];
46 };
47 
48 enum rtw89_mac_h2c_type {
49 	RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0,
50 	RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD,
51 	RTW89_FWCMD_H2CREG_FUNC_FWERR,
52 	RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE,
53 	RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM,
54 	RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN
55 };
56 
57 enum rtw89_mac_c2h_type {
58 	RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0,
59 	RTW89_FWCMD_C2HREG_FUNC_ERR_RPT,
60 	RTW89_FWCMD_C2HREG_FUNC_ERR_MSG,
61 	RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,
62 	RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,
63 	RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF
64 };
65 
66 #define RTW89_GET_C2H_PHYCAP_FUNC(info) \
67 	u32_get_bits(*((const u32 *)(info)), GENMASK(6, 0))
68 #define RTW89_GET_C2H_PHYCAP_ACK(info) \
69 	u32_get_bits(*((const u32 *)(info)), BIT(7))
70 #define RTW89_GET_C2H_PHYCAP_LEN(info) \
71 	u32_get_bits(*((const u32 *)(info)), GENMASK(11, 8))
72 #define RTW89_GET_C2H_PHYCAP_SEQ(info) \
73 	u32_get_bits(*((const u32 *)(info)), GENMASK(15, 12))
74 #define RTW89_GET_C2H_PHYCAP_RX_NSS(info) \
75 	u32_get_bits(*((const u32 *)(info)), GENMASK(23, 16))
76 #define RTW89_GET_C2H_PHYCAP_BW(info) \
77 	u32_get_bits(*((const u32 *)(info)), GENMASK(31, 24))
78 #define RTW89_GET_C2H_PHYCAP_TX_NSS(info) \
79 	u32_get_bits(*((const u32 *)(info) + 1), GENMASK(7, 0))
80 #define RTW89_GET_C2H_PHYCAP_PROT(info) \
81 	u32_get_bits(*((const u32 *)(info) + 1), GENMASK(15, 8))
82 #define RTW89_GET_C2H_PHYCAP_NIC(info) \
83 	u32_get_bits(*((const u32 *)(info) + 1), GENMASK(23, 16))
84 #define RTW89_GET_C2H_PHYCAP_WL_FUNC(info) \
85 	u32_get_bits(*((const u32 *)(info) + 1), GENMASK(31, 24))
86 #define RTW89_GET_C2H_PHYCAP_HW_TYPE(info) \
87 	u32_get_bits(*((const u32 *)(info) + 2), GENMASK(7, 0))
88 #define RTW89_GET_C2H_PHYCAP_ANT_TX_NUM(info) \
89 	u32_get_bits(*((const u32 *)(info) + 3), GENMASK(15, 8))
90 #define RTW89_GET_C2H_PHYCAP_ANT_RX_NUM(info) \
91 	u32_get_bits(*((const u32 *)(info) + 3), GENMASK(23, 16))
92 
93 enum rtw89_fw_c2h_category {
94 	RTW89_C2H_CAT_TEST,
95 	RTW89_C2H_CAT_MAC,
96 	RTW89_C2H_CAT_OUTSRC,
97 };
98 
99 enum rtw89_fw_log_level {
100 	RTW89_FW_LOG_LEVEL_OFF,
101 	RTW89_FW_LOG_LEVEL_CRT,
102 	RTW89_FW_LOG_LEVEL_SER,
103 	RTW89_FW_LOG_LEVEL_WARN,
104 	RTW89_FW_LOG_LEVEL_LOUD,
105 	RTW89_FW_LOG_LEVEL_TR,
106 };
107 
108 enum rtw89_fw_log_path {
109 	RTW89_FW_LOG_LEVEL_UART,
110 	RTW89_FW_LOG_LEVEL_C2H,
111 	RTW89_FW_LOG_LEVEL_SNI,
112 };
113 
114 enum rtw89_fw_log_comp {
115 	RTW89_FW_LOG_COMP_VER,
116 	RTW89_FW_LOG_COMP_INIT,
117 	RTW89_FW_LOG_COMP_TASK,
118 	RTW89_FW_LOG_COMP_CNS,
119 	RTW89_FW_LOG_COMP_H2C,
120 	RTW89_FW_LOG_COMP_C2H,
121 	RTW89_FW_LOG_COMP_TX,
122 	RTW89_FW_LOG_COMP_RX,
123 	RTW89_FW_LOG_COMP_IPSEC,
124 	RTW89_FW_LOG_COMP_TIMER,
125 	RTW89_FW_LOG_COMP_DBGPKT,
126 	RTW89_FW_LOG_COMP_PS,
127 	RTW89_FW_LOG_COMP_ERROR,
128 	RTW89_FW_LOG_COMP_WOWLAN,
129 	RTW89_FW_LOG_COMP_SECURE_BOOT,
130 	RTW89_FW_LOG_COMP_BTC,
131 	RTW89_FW_LOG_COMP_BB,
132 	RTW89_FW_LOG_COMP_TWT,
133 	RTW89_FW_LOG_COMP_RF,
134 	RTW89_FW_LOG_COMP_MCC = 20,
135 };
136 
137 enum rtw89_pkt_offload_op {
138 	RTW89_PKT_OFLD_OP_ADD,
139 	RTW89_PKT_OFLD_OP_DEL,
140 	RTW89_PKT_OFLD_OP_READ,
141 };
142 
143 enum rtw89_scanofld_notify_reason {
144 	RTW89_SCAN_DWELL_NOTIFY,
145 	RTW89_SCAN_PRE_TX_NOTIFY,
146 	RTW89_SCAN_POST_TX_NOTIFY,
147 	RTW89_SCAN_ENTER_CH_NOTIFY,
148 	RTW89_SCAN_LEAVE_CH_NOTIFY,
149 	RTW89_SCAN_END_SCAN_NOTIFY,
150 };
151 
152 enum rtw89_chan_type {
153 	RTW89_CHAN_OPERATE = 0,
154 	RTW89_CHAN_ACTIVE,
155 	RTW89_CHAN_DFS,
156 };
157 
158 enum rtw89_p2pps_action {
159 	RTW89_P2P_ACT_INIT = 0,
160 	RTW89_P2P_ACT_UPDATE = 1,
161 	RTW89_P2P_ACT_REMOVE = 2,
162 	RTW89_P2P_ACT_TERMINATE = 3,
163 };
164 
165 enum rtw89_bcn_fltr_offload_mode {
166 	RTW89_BCN_FLTR_OFFLOAD_MODE_0 = 0,
167 	RTW89_BCN_FLTR_OFFLOAD_MODE_1,
168 	RTW89_BCN_FLTR_OFFLOAD_MODE_2,
169 	RTW89_BCN_FLTR_OFFLOAD_MODE_3,
170 
171 	RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT = RTW89_BCN_FLTR_OFFLOAD_MODE_0,
172 };
173 
174 enum rtw89_bcn_fltr_type {
175 	RTW89_BCN_FLTR_BEACON_LOSS,
176 	RTW89_BCN_FLTR_RSSI,
177 	RTW89_BCN_FLTR_NOTIFY,
178 };
179 
180 enum rtw89_bcn_fltr_rssi_event {
181 	RTW89_BCN_FLTR_RSSI_NOT_CHANGED,
182 	RTW89_BCN_FLTR_RSSI_HIGH,
183 	RTW89_BCN_FLTR_RSSI_LOW,
184 };
185 
186 #define FWDL_SECTION_MAX_NUM 10
187 #define FWDL_SECTION_CHKSUM_LEN	8
188 #define FWDL_SECTION_PER_PKT_LEN 2020
189 
190 struct rtw89_fw_hdr_section_info {
191 	u8 redl;
192 	const u8 *addr;
193 	u32 len;
194 	u32 dladdr;
195 	u32 mssc;
196 	u8 type;
197 };
198 
199 struct rtw89_fw_bin_info {
200 	u8 section_num;
201 	u32 hdr_len;
202 	bool dynamic_hdr_en;
203 	u32 dynamic_hdr_len;
204 	struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];
205 };
206 
207 struct rtw89_fw_macid_pause_grp {
208 	__le32 pause_grp[4];
209 	__le32 mask_grp[4];
210 } __packed;
211 
212 struct rtw89_h2creg_sch_tx_en {
213 	u8 func:7;
214 	u8 ack:1;
215 	u8 total_len:4;
216 	u8 seq_num:4;
217 	u16 tx_en:16;
218 	u16 mask:16;
219 	u8 band:1;
220 	u16 rsvd:15;
221 } __packed;
222 
223 #define RTW89_H2C_MAX_SIZE 2048
224 #define RTW89_CHANNEL_TIME 45
225 #define RTW89_CHANNEL_TIME_6G 20
226 #define RTW89_DFS_CHAN_TIME 105
227 #define RTW89_OFF_CHAN_TIME 100
228 #define RTW89_DWELL_TIME 20
229 #define RTW89_DWELL_TIME_6G 10
230 #define RTW89_SCAN_WIDTH 0
231 #define RTW89_SCANOFLD_MAX_SSID 8
232 #define RTW89_SCANOFLD_MAX_IE_LEN 512
233 #define RTW89_SCANOFLD_PKT_NONE 0xFF
234 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F
235 #define RTW89_MAC_CHINFO_SIZE 24
236 #define RTW89_SCAN_LIST_GUARD 4
237 #define RTW89_SCAN_LIST_LIMIT \
238 		((RTW89_H2C_MAX_SIZE / RTW89_MAC_CHINFO_SIZE) - RTW89_SCAN_LIST_GUARD)
239 
240 #define RTW89_BCN_LOSS_CNT 10
241 
242 struct rtw89_mac_chinfo {
243 	u8 period;
244 	u8 dwell_time;
245 	u8 central_ch;
246 	u8 pri_ch;
247 	u8 bw:3;
248 	u8 notify_action:5;
249 	u8 num_pkt:4;
250 	u8 tx_pkt:1;
251 	u8 pause_data:1;
252 	u8 ch_band:2;
253 	u8 probe_id;
254 	u8 dfs_ch:1;
255 	u8 tx_null:1;
256 	u8 rand_seq_num:1;
257 	u8 cfg_tx_pwr:1;
258 	u8 rsvd0: 4;
259 	u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
260 	u16 tx_pwr_idx;
261 	u8 rsvd1;
262 	struct list_head list;
263 	bool is_psc;
264 };
265 
266 struct rtw89_scan_option {
267 	bool enable;
268 	bool target_ch_mode;
269 };
270 
271 struct rtw89_pktofld_info {
272 	struct list_head list;
273 	u8 id;
274 
275 	/* Below fields are for 6 GHz RNR use only */
276 	u8 ssid[IEEE80211_MAX_SSID_LEN];
277 	u8 ssid_len;
278 	u8 bssid[ETH_ALEN];
279 	u16 channel_6ghz;
280 };
281 
282 static inline void RTW89_SET_FWCMD_RA_IS_DIS(void *cmd, u32 val)
283 {
284 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(0));
285 }
286 
287 static inline void RTW89_SET_FWCMD_RA_MODE(void *cmd, u32 val)
288 {
289 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(5, 1));
290 }
291 
292 static inline void RTW89_SET_FWCMD_RA_BW_CAP(void *cmd, u32 val)
293 {
294 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 6));
295 }
296 
297 static inline void RTW89_SET_FWCMD_RA_MACID(void *cmd, u32 val)
298 {
299 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
300 }
301 
302 static inline void RTW89_SET_FWCMD_RA_DCM(void *cmd, u32 val)
303 {
304 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(16));
305 }
306 
307 static inline void RTW89_SET_FWCMD_RA_ER(void *cmd, u32 val)
308 {
309 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(17));
310 }
311 
312 static inline void RTW89_SET_FWCMD_RA_INIT_RATE_LV(void *cmd, u32 val)
313 {
314 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(19, 18));
315 }
316 
317 static inline void RTW89_SET_FWCMD_RA_UPD_ALL(void *cmd, u32 val)
318 {
319 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(20));
320 }
321 
322 static inline void RTW89_SET_FWCMD_RA_SGI(void *cmd, u32 val)
323 {
324 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(21));
325 }
326 
327 static inline void RTW89_SET_FWCMD_RA_LDPC(void *cmd, u32 val)
328 {
329 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(22));
330 }
331 
332 static inline void RTW89_SET_FWCMD_RA_STBC(void *cmd, u32 val)
333 {
334 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(23));
335 }
336 
337 static inline void RTW89_SET_FWCMD_RA_SS_NUM(void *cmd, u32 val)
338 {
339 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(26, 24));
340 }
341 
342 static inline void RTW89_SET_FWCMD_RA_GILTF(void *cmd, u32 val)
343 {
344 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(29, 27));
345 }
346 
347 static inline void RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(void *cmd, u32 val)
348 {
349 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(30));
350 }
351 
352 static inline void RTW89_SET_FWCMD_RA_UPD_MASK(void *cmd, u32 val)
353 {
354 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(31));
355 }
356 
357 static inline void RTW89_SET_FWCMD_RA_MASK_0(void *cmd, u32 val)
358 {
359 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(7, 0));
360 }
361 
362 static inline void RTW89_SET_FWCMD_RA_MASK_1(void *cmd, u32 val)
363 {
364 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(15, 8));
365 }
366 
367 static inline void RTW89_SET_FWCMD_RA_MASK_2(void *cmd, u32 val)
368 {
369 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(23, 16));
370 }
371 
372 static inline void RTW89_SET_FWCMD_RA_MASK_3(void *cmd, u32 val)
373 {
374 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 24));
375 }
376 
377 static inline void RTW89_SET_FWCMD_RA_MASK_4(void *cmd, u32 val)
378 {
379 	le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(7, 0));
380 }
381 
382 static inline void RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(void *cmd, u32 val)
383 {
384 	le32p_replace_bits((__le32 *)(cmd) + 0x02, val, BIT(31));
385 }
386 
387 static inline void RTW89_SET_FWCMD_RA_BAND_NUM(void *cmd, u32 val)
388 {
389 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(7, 0));
390 }
391 
392 static inline void RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(void *cmd, u32 val)
393 {
394 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(8));
395 }
396 
397 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(void *cmd, u32 val)
398 {
399 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(9));
400 }
401 
402 static inline void RTW89_SET_FWCMD_RA_CR_TBL_SEL(void *cmd, u32 val)
403 {
404 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(10));
405 }
406 
407 static inline void RTW89_SET_FWCMD_RA_FIX_GILTF_EN(void *cmd, u32 val)
408 {
409 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(11));
410 }
411 
412 static inline void RTW89_SET_FWCMD_RA_FIX_GILTF(void *cmd, u32 val)
413 {
414 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(14, 12));
415 }
416 
417 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(void *cmd, u32 val)
418 {
419 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(23, 16));
420 }
421 
422 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(void *cmd, u32 val)
423 {
424 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(25, 24));
425 }
426 
427 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(void *cmd, u32 val)
428 {
429 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(28, 26));
430 }
431 
432 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_BW(void *cmd, u32 val)
433 {
434 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 29));
435 }
436 
437 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)
438 {
439 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));
440 }
441 
442 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val)
443 {
444 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
445 }
446 
447 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val)
448 {
449 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16));
450 }
451 
452 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val)
453 {
454 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0));
455 }
456 
457 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val)
458 {
459 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4));
460 }
461 
462 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val)
463 {
464 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5));
465 }
466 
467 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val)
468 {
469 	le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0));
470 }
471 
472 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val)
473 {
474 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0));
475 }
476 
477 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val)
478 {
479 	le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0));
480 }
481 
482 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val)
483 {
484 	le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0));
485 }
486 
487 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val)
488 {
489 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0));
490 }
491 
492 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val)
493 {
494 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3));
495 }
496 
497 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val)
498 {
499 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4));
500 }
501 
502 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val)
503 {
504 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5));
505 }
506 
507 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val)
508 {
509 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0));
510 }
511 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)
512 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)
513 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)
514 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)
515 
516 #define FWDL_SECURITY_SECTION_TYPE 9
517 #define FWDL_SECURITY_SIGLEN 512
518 
519 #define GET_FWSECTION_HDR_DL_ADDR(fwhdr)	\
520 	le32_get_bits(*((const __le32 *)(fwhdr)), GENMASK(31, 0))
521 #define GET_FWSECTION_HDR_SECTIONTYPE(fwhdr)	\
522 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(27, 24))
523 #define GET_FWSECTION_HDR_SEC_SIZE(fwhdr)	\
524 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 0))
525 #define GET_FWSECTION_HDR_CHECKSUM(fwhdr)	\
526 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(28))
527 #define GET_FWSECTION_HDR_REDL(fwhdr)	\
528 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(29))
529 #define GET_FWSECTION_HDR_MSSC(fwhdr)	\
530 	le32_get_bits(*((const __le32 *)(fwhdr) + 2), GENMASK(31, 0))
531 
532 #define GET_FW_HDR_MAJOR_VERSION(fwhdr)	\
533 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(7, 0))
534 #define GET_FW_HDR_MINOR_VERSION(fwhdr)	\
535 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(15, 8))
536 #define GET_FW_HDR_SUBVERSION(fwhdr)	\
537 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 16))
538 #define GET_FW_HDR_SUBINDEX(fwhdr)	\
539 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(31, 24))
540 #define GET_FW_HDR_LEN(fwhdr)	\
541 	le32_get_bits(*((const __le32 *)(fwhdr) + 3), GENMASK(23, 16))
542 #define GET_FW_HDR_MONTH(fwhdr)		\
543 	le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(7, 0))
544 #define GET_FW_HDR_DATE(fwhdr)		\
545 	le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(15, 8))
546 #define GET_FW_HDR_HOUR(fwhdr)		\
547 	le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(23, 16))
548 #define GET_FW_HDR_MIN(fwhdr)		\
549 	le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(31, 24))
550 #define GET_FW_HDR_YEAR(fwhdr)		\
551 	le32_get_bits(*((const __le32 *)(fwhdr) + 5), GENMASK(31, 0))
552 #define GET_FW_HDR_SEC_NUM(fwhdr)	\
553 	le32_get_bits(*((const __le32 *)(fwhdr) + 6), GENMASK(15, 8))
554 #define GET_FW_HDR_DYN_HDR(fwhdr)	\
555 	le32_get_bits(*((const __le32 *)(fwhdr) + 7), BIT(16))
556 #define GET_FW_HDR_CMD_VERSERION(fwhdr)	\
557 	le32_get_bits(*((const __le32 *)(fwhdr) + 7), GENMASK(31, 24))
558 
559 #define GET_FW_DYNHDR_LEN(fwdynhdr)	\
560 	le32_get_bits(*((const __le32 *)(fwdynhdr)), GENMASK(31, 0))
561 #define GET_FW_DYNHDR_COUNT(fwdynhdr)	\
562 	le32_get_bits(*((const __le32 *)(fwdynhdr) + 1), GENMASK(31, 0))
563 
564 static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val)
565 {
566 	le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0));
567 }
568 
569 static inline void SET_CTRL_INFO_MACID(void *table, u32 val)
570 {
571 	le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
572 }
573 
574 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val)
575 {
576 	le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
577 }
578 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)
579 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val)
580 {
581 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0));
582 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE,
583 			   GENMASK(8, 0));
584 }
585 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
586 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val)
587 {
588 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9));
589 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP,
590 			   BIT(9));
591 }
592 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0)
593 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val)
594 {
595 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10));
596 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW,
597 			   GENMASK(11, 10));
598 }
599 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0)
600 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val)
601 {
602 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12));
603 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF,
604 			   GENMASK(14, 12));
605 }
606 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
607 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val)
608 {
609 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
610 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX,
611 			   BIT(15));
612 }
613 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0)
614 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val)
615 {
616 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16));
617 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL,
618 			   GENMASK(19, 16));
619 }
620 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
621 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val)
622 {
623 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20));
624 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN,
625 			   BIT(20));
626 }
627 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
628 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val)
629 {
630 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21));
631 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN,
632 			   BIT(21));
633 }
634 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
635 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val)
636 {
637 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22));
638 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN,
639 			   BIT(22));
640 }
641 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
642 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val)
643 {
644 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23));
645 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN,
646 			   BIT(23));
647 }
648 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
649 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val)
650 {
651 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25));
652 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB,
653 			   BIT(25));
654 }
655 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
656 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val)
657 {
658 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26));
659 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB,
660 			   BIT(26));
661 }
662 #define SET_CMC_TBL_MASK_TRYRATE BIT(0)
663 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val)
664 {
665 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27));
666 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE,
667 			   BIT(27));
668 }
669 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0)
670 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val)
671 {
672 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28));
673 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY,
674 			   GENMASK(31, 28));
675 }
676 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)
677 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val)
678 {
679 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0));
680 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE,
681 			   GENMASK(8, 0));
682 }
683 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
684 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val)
685 {
686 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9));
687 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL,
688 			   BIT(9));
689 }
690 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
691 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val)
692 {
693 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10));
694 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL,
695 			   BIT(10));
696 }
697 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
698 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val)
699 {
700 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11));
701 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL,
702 			   BIT(11));
703 }
704 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0)
705 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val)
706 {
707 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12));
708 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT,
709 			   GENMASK(15, 12));
710 }
711 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)
712 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val)
713 {
714 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16));
715 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE,
716 			   GENMASK(24, 16));
717 }
718 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
719 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val)
720 {
721 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27));
722 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC,
723 			   BIT(27));
724 }
725 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0)
726 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val)
727 {
728 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28));
729 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE,
730 			   GENMASK(31, 28));
731 }
732 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0)
733 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val)
734 {
735 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0));
736 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT,
737 			   GENMASK(5, 0));
738 }
739 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
740 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val)
741 {
742 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6));
743 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL,
744 			   BIT(6));
745 }
746 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
747 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val)
748 {
749 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7));
750 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL,
751 			   BIT(7));
752 }
753 #define SET_CMC_TBL_MASK_RTS_EN BIT(0)
754 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val)
755 {
756 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8));
757 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN,
758 			   BIT(8));
759 }
760 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
761 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val)
762 {
763 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9));
764 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN,
765 			   BIT(9));
766 }
767 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0)
768 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val)
769 {
770 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10));
771 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS,
772 			   GENMASK(11, 10));
773 }
774 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
775 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val)
776 {
777 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12));
778 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN,
779 			   BIT(12));
780 }
781 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0)
782 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val)
783 {
784 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13));
785 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE,
786 			   GENMASK(14, 13));
787 }
788 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0)
789 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val)
790 {
791 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16));
792 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN,
793 			   GENMASK(26, 16));
794 }
795 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
796 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val)
797 {
798 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
799 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS,
800 			   BIT(27));
801 }
802 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0)
803 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val)
804 {
805 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28));
806 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME,
807 			   GENMASK(31, 28));
808 }
809 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)
810 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val)
811 {
812 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0));
813 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM,
814 			   GENMASK(7, 0));
815 }
816 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0)
817 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val)
818 {
819 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8));
820 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP,
821 			   GENMASK(9, 8));
822 }
823 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0)
824 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val)
825 {
826 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16));
827 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL,
828 			   GENMASK(18, 16));
829 }
830 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0)
831 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val)
832 {
833 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19));
834 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL,
835 			   GENMASK(21, 19));
836 }
837 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0)
838 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val)
839 {
840 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22));
841 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL,
842 			   GENMASK(24, 22));
843 }
844 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0)
845 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val)
846 {
847 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25));
848 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL,
849 			   GENMASK(27, 25));
850 }
851 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0)
852 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val)
853 {
854 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28));
855 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE,
856 			   GENMASK(31, 28));
857 }
858 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0)
859 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val)
860 {
861 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0));
862 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID,
863 			   GENMASK(2, 0));
864 }
865 #define SET_CMC_TBL_MASK_BMC BIT(0)
866 static inline void SET_CMC_TBL_BMC(void *table, u32 val)
867 {
868 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3));
869 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC,
870 			   BIT(3));
871 }
872 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0)
873 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val)
874 {
875 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4));
876 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID,
877 			   GENMASK(7, 4));
878 }
879 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
880 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val)
881 {
882 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
883 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR,
884 			   BIT(8));
885 }
886 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0)
887 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val)
888 {
889 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9));
890 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE,
891 			   GENMASK(11, 9));
892 }
893 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
894 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val)
895 {
896 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12));
897 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM,
898 			   BIT(12));
899 }
900 #define SET_CMC_TBL_MASK_DATA_ER BIT(0)
901 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val)
902 {
903 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13));
904 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER,
905 			   BIT(13));
906 }
907 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
908 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val)
909 {
910 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14));
911 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC,
912 			   BIT(14));
913 }
914 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
915 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val)
916 {
917 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
918 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC,
919 			   BIT(15));
920 }
921 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
922 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val)
923 {
924 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16));
925 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR,
926 			   BIT(16));
927 }
928 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
929 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val)
930 {
931 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17));
932 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH,
933 			   BIT(17));
934 }
935 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
936 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val)
937 {
938 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18));
939 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR,
940 			   BIT(18));
941 }
942 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
943 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val)
944 {
945 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19));
946 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS,
947 			   BIT(19));
948 }
949 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
950 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val)
951 {
952 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20));
953 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER,
954 			   BIT(20));
955 }
956 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
957 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val)
958 {
959 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21));
960 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN,
961 			   BIT(21));
962 }
963 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
964 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val)
965 {
966 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27));
967 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD,
968 			   BIT(27));
969 }
970 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0)
971 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val)
972 {
973 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28));
974 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT,
975 			   GENMASK(31, 28));
976 }
977 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)
978 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val)
979 {
980 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0));
981 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE,
982 			   GENMASK(8, 0));
983 }
984 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
985 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val)
986 {
987 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12));
988 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT,
989 			   BIT(12));
990 }
991 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
992 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val)
993 {
994 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13));
995 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT,
996 			   BIT(13));
997 }
998 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0)
999 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val)
1000 {
1001 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16));
1002 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN,
1003 			   GENMASK(19, 16));
1004 }
1005 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0)
1006 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val)
1007 {
1008 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20));
1009 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A,
1010 			   GENMASK(21, 20));
1011 }
1012 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0)
1013 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val)
1014 {
1015 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22));
1016 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B,
1017 			   GENMASK(23, 22));
1018 }
1019 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0)
1020 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val)
1021 {
1022 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24));
1023 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C,
1024 			   GENMASK(25, 24));
1025 }
1026 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0)
1027 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val)
1028 {
1029 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26));
1030 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D,
1031 			   GENMASK(27, 26));
1032 }
1033 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
1034 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val)
1035 {
1036 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28));
1037 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A,
1038 			   BIT(28));
1039 }
1040 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
1041 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val)
1042 {
1043 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29));
1044 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B,
1045 			   BIT(29));
1046 }
1047 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
1048 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val)
1049 {
1050 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30));
1051 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C,
1052 			   BIT(30));
1053 }
1054 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
1055 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val)
1056 {
1057 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31));
1058 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D,
1059 			   BIT(31));
1060 }
1061 
1062 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0)
1063 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val)
1064 {
1065 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0));
1066 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1067 			   GENMASK(1, 0));
1068 }
1069 
1070 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val)
1071 {
1072 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2));
1073 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1074 			   GENMASK(3, 2));
1075 }
1076 
1077 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val)
1078 {
1079 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4));
1080 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1081 			   GENMASK(5, 4));
1082 }
1083 
1084 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val)
1085 {
1086 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6));
1087 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1088 			   GENMASK(7, 6));
1089 }
1090 
1091 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)
1092 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val)
1093 {
1094 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1095 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX,
1096 			   GENMASK(7, 0));
1097 }
1098 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)
1099 static inline void SET_CMC_TBL_PAID(void *table, u32 val)
1100 {
1101 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8));
1102 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID,
1103 			   GENMASK(16, 8));
1104 }
1105 #define SET_CMC_TBL_MASK_ULDL BIT(0)
1106 static inline void SET_CMC_TBL_ULDL(void *table, u32 val)
1107 {
1108 	le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17));
1109 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL,
1110 			   BIT(17));
1111 }
1112 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0)
1113 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val)
1114 {
1115 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18));
1116 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL,
1117 			   GENMASK(19, 18));
1118 }
1119 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val)
1120 {
1121 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20));
1122 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1123 			   GENMASK(21, 20));
1124 }
1125 
1126 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val)
1127 {
1128 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22));
1129 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1130 			   GENMASK(23, 22));
1131 }
1132 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0)
1133 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val)
1134 {
1135 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24));
1136 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE,
1137 			   GENMASK(27, 24));
1138 }
1139 
1140 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val)
1141 {
1142 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30));
1143 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1144 			   GENMASK(31, 30));
1145 }
1146 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0)
1147 static inline void SET_CMC_TBL_NC(void *table, u32 val)
1148 {
1149 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0));
1150 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC,
1151 			   GENMASK(2, 0));
1152 }
1153 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0)
1154 static inline void SET_CMC_TBL_NR(void *table, u32 val)
1155 {
1156 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3));
1157 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR,
1158 			   GENMASK(5, 3));
1159 }
1160 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0)
1161 static inline void SET_CMC_TBL_NG(void *table, u32 val)
1162 {
1163 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6));
1164 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG,
1165 			   GENMASK(7, 6));
1166 }
1167 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0)
1168 static inline void SET_CMC_TBL_CB(void *table, u32 val)
1169 {
1170 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8));
1171 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB,
1172 			   GENMASK(9, 8));
1173 }
1174 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0)
1175 static inline void SET_CMC_TBL_CS(void *table, u32 val)
1176 {
1177 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10));
1178 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS,
1179 			   GENMASK(11, 10));
1180 }
1181 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
1182 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val)
1183 {
1184 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12));
1185 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN,
1186 			   BIT(12));
1187 }
1188 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
1189 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val)
1190 {
1191 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13));
1192 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN,
1193 			   BIT(13));
1194 }
1195 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
1196 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val)
1197 {
1198 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14));
1199 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN,
1200 			   BIT(14));
1201 }
1202 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
1203 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val)
1204 {
1205 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15));
1206 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN,
1207 			   BIT(15));
1208 }
1209 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)
1210 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val)
1211 {
1212 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16));
1213 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE,
1214 			   GENMASK(24, 16));
1215 }
1216 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0)
1217 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val)
1218 {
1219 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25));
1220 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF,
1221 			   GENMASK(27, 25));
1222 }
1223 
1224 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val)
1225 {
1226 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28));
1227 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1228 			   GENMASK(29, 28));
1229 }
1230 
1231 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0)
1232 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val)
1233 {
1234 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30));
1235 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW,
1236 			   GENMASK(31, 30));
1237 }
1238 
1239 static inline void SET_DCTL_MACID_V1(void *table, u32 val)
1240 {
1241 	le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
1242 }
1243 
1244 static inline void SET_DCTL_OPERATION_V1(void *table, u32 val)
1245 {
1246 	le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
1247 }
1248 
1249 #define SET_DCTL_MASK_QOS_FIELD_V1 GENMASK(7, 0)
1250 static inline void SET_DCTL_QOS_FIELD_V1(void *table, u32 val)
1251 {
1252 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(7, 0));
1253 	le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_FIELD_V1,
1254 			   GENMASK(7, 0));
1255 }
1256 
1257 #define SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID GENMASK(6, 0)
1258 static inline void SET_DCTL_HW_EXSEQ_MACID_V1(void *table, u32 val)
1259 {
1260 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 8));
1261 	le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID,
1262 			   GENMASK(14, 8));
1263 }
1264 
1265 #define SET_DCTL_MASK_QOS_DATA BIT(0)
1266 static inline void SET_DCTL_QOS_DATA_V1(void *table, u32 val)
1267 {
1268 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
1269 	le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_DATA,
1270 			   BIT(15));
1271 }
1272 
1273 #define SET_DCTL_MASK_AES_IV_L GENMASK(15, 0)
1274 static inline void SET_DCTL_AES_IV_L_V1(void *table, u32 val)
1275 {
1276 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 16));
1277 	le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_AES_IV_L,
1278 			   GENMASK(31, 16));
1279 }
1280 
1281 #define SET_DCTL_MASK_AES_IV_H GENMASK(31, 0)
1282 static inline void SET_DCTL_AES_IV_H_V1(void *table, u32 val)
1283 {
1284 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 0));
1285 	le32p_replace_bits((__le32 *)(table) + 10, SET_DCTL_MASK_AES_IV_H,
1286 			   GENMASK(31, 0));
1287 }
1288 
1289 #define SET_DCTL_MASK_SEQ0 GENMASK(11, 0)
1290 static inline void SET_DCTL_SEQ0_V1(void *table, u32 val)
1291 {
1292 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 0));
1293 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ0,
1294 			   GENMASK(11, 0));
1295 }
1296 
1297 #define SET_DCTL_MASK_SEQ1 GENMASK(11, 0)
1298 static inline void SET_DCTL_SEQ1_V1(void *table, u32 val)
1299 {
1300 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(23, 12));
1301 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ1,
1302 			   GENMASK(23, 12));
1303 }
1304 
1305 #define SET_DCTL_MASK_AMSDU_MAX_LEN GENMASK(2, 0)
1306 static inline void SET_DCTL_AMSDU_MAX_LEN_V1(void *table, u32 val)
1307 {
1308 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 24));
1309 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_AMSDU_MAX_LEN,
1310 			   GENMASK(26, 24));
1311 }
1312 
1313 #define SET_DCTL_MASK_STA_AMSDU_EN BIT(0)
1314 static inline void SET_DCTL_STA_AMSDU_EN_V1(void *table, u32 val)
1315 {
1316 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
1317 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_STA_AMSDU_EN,
1318 			   BIT(27));
1319 }
1320 
1321 #define SET_DCTL_MASK_CHKSUM_OFLD_EN BIT(0)
1322 static inline void SET_DCTL_CHKSUM_OFLD_EN_V1(void *table, u32 val)
1323 {
1324 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(28));
1325 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_CHKSUM_OFLD_EN,
1326 			   BIT(28));
1327 }
1328 
1329 #define SET_DCTL_MASK_WITH_LLC BIT(0)
1330 static inline void SET_DCTL_WITH_LLC_V1(void *table, u32 val)
1331 {
1332 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(29));
1333 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_WITH_LLC,
1334 			   BIT(29));
1335 }
1336 
1337 #define SET_DCTL_MASK_SEQ2 GENMASK(11, 0)
1338 static inline void SET_DCTL_SEQ2_V1(void *table, u32 val)
1339 {
1340 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(11, 0));
1341 	le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ2,
1342 			   GENMASK(11, 0));
1343 }
1344 
1345 #define SET_DCTL_MASK_SEQ3 GENMASK(11, 0)
1346 static inline void SET_DCTL_SEQ3_V1(void *table, u32 val)
1347 {
1348 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(23, 12));
1349 	le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ3,
1350 			   GENMASK(23, 12));
1351 }
1352 
1353 #define SET_DCTL_MASK_TGT_IND GENMASK(3, 0)
1354 static inline void SET_DCTL_TGT_IND_V1(void *table, u32 val)
1355 {
1356 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 24));
1357 	le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND,
1358 			   GENMASK(27, 24));
1359 }
1360 
1361 #define SET_DCTL_MASK_TGT_IND_EN BIT(0)
1362 static inline void SET_DCTL_TGT_IND_EN_V1(void *table, u32 val)
1363 {
1364 	le32p_replace_bits((__le32 *)(table) + 4, val, BIT(28));
1365 	le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND_EN,
1366 			   BIT(28));
1367 }
1368 
1369 #define SET_DCTL_MASK_HTC_LB GENMASK(2, 0)
1370 static inline void SET_DCTL_HTC_LB_V1(void *table, u32 val)
1371 {
1372 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 29));
1373 	le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_HTC_LB,
1374 			   GENMASK(31, 29));
1375 }
1376 
1377 #define SET_DCTL_MASK_MHDR_LEN GENMASK(4, 0)
1378 static inline void SET_DCTL_MHDR_LEN_V1(void *table, u32 val)
1379 {
1380 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(4, 0));
1381 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_MHDR_LEN,
1382 			   GENMASK(4, 0));
1383 }
1384 
1385 #define SET_DCTL_MASK_VLAN_TAG_VALID BIT(0)
1386 static inline void SET_DCTL_VLAN_TAG_VALID_V1(void *table, u32 val)
1387 {
1388 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(5));
1389 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_VALID,
1390 			   BIT(5));
1391 }
1392 
1393 #define SET_DCTL_MASK_VLAN_TAG_SEL GENMASK(1, 0)
1394 static inline void SET_DCTL_VLAN_TAG_SEL_V1(void *table, u32 val)
1395 {
1396 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 6));
1397 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_SEL,
1398 			   GENMASK(7, 6));
1399 }
1400 
1401 #define SET_DCTL_MASK_HTC_ORDER BIT(0)
1402 static inline void SET_DCTL_HTC_ORDER_V1(void *table, u32 val)
1403 {
1404 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
1405 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_HTC_ORDER,
1406 			   BIT(8));
1407 }
1408 
1409 #define SET_DCTL_MASK_SEC_KEY_ID GENMASK(1, 0)
1410 static inline void SET_DCTL_SEC_KEY_ID_V1(void *table, u32 val)
1411 {
1412 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(10, 9));
1413 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_KEY_ID,
1414 			   GENMASK(10, 9));
1415 }
1416 
1417 #define SET_DCTL_MASK_WAPI BIT(0)
1418 static inline void SET_DCTL_WAPI_V1(void *table, u32 val)
1419 {
1420 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
1421 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_WAPI,
1422 			   BIT(15));
1423 }
1424 
1425 #define SET_DCTL_MASK_SEC_ENT_MODE GENMASK(1, 0)
1426 static inline void SET_DCTL_SEC_ENT_MODE_V1(void *table, u32 val)
1427 {
1428 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(17, 16));
1429 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENT_MODE,
1430 			   GENMASK(17, 16));
1431 }
1432 
1433 #define SET_DCTL_MASK_SEC_ENTX_KEYID GENMASK(1, 0)
1434 static inline void SET_DCTL_SEC_ENT0_KEYID_V1(void *table, u32 val)
1435 {
1436 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(19, 18));
1437 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1438 			   GENMASK(19, 18));
1439 }
1440 
1441 static inline void SET_DCTL_SEC_ENT1_KEYID_V1(void *table, u32 val)
1442 {
1443 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(21, 20));
1444 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1445 			   GENMASK(21, 20));
1446 }
1447 
1448 static inline void SET_DCTL_SEC_ENT2_KEYID_V1(void *table, u32 val)
1449 {
1450 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(23, 22));
1451 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1452 			   GENMASK(23, 22));
1453 }
1454 
1455 static inline void SET_DCTL_SEC_ENT3_KEYID_V1(void *table, u32 val)
1456 {
1457 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(25, 24));
1458 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1459 			   GENMASK(25, 24));
1460 }
1461 
1462 static inline void SET_DCTL_SEC_ENT4_KEYID_V1(void *table, u32 val)
1463 {
1464 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(27, 26));
1465 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1466 			   GENMASK(27, 26));
1467 }
1468 
1469 static inline void SET_DCTL_SEC_ENT5_KEYID_V1(void *table, u32 val)
1470 {
1471 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(29, 28));
1472 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1473 			   GENMASK(29, 28));
1474 }
1475 
1476 static inline void SET_DCTL_SEC_ENT6_KEYID_V1(void *table, u32 val)
1477 {
1478 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 30));
1479 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1480 			   GENMASK(31, 30));
1481 }
1482 
1483 #define SET_DCTL_MASK_SEC_ENT_VALID GENMASK(7, 0)
1484 static inline void SET_DCTL_SEC_ENT_VALID_V1(void *table, u32 val)
1485 {
1486 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(7, 0));
1487 	le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENT_VALID,
1488 			   GENMASK(7, 0));
1489 }
1490 
1491 #define SET_DCTL_MASK_SEC_ENTX GENMASK(7, 0)
1492 static inline void SET_DCTL_SEC_ENT0_V1(void *table, u32 val)
1493 {
1494 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(15, 8));
1495 	le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1496 			   GENMASK(15, 8));
1497 }
1498 
1499 static inline void SET_DCTL_SEC_ENT1_V1(void *table, u32 val)
1500 {
1501 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 16));
1502 	le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1503 			   GENMASK(23, 16));
1504 }
1505 
1506 static inline void SET_DCTL_SEC_ENT2_V1(void *table, u32 val)
1507 {
1508 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(31, 24));
1509 	le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1510 			   GENMASK(31, 24));
1511 }
1512 
1513 static inline void SET_DCTL_SEC_ENT3_V1(void *table, u32 val)
1514 {
1515 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1516 	le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1517 			   GENMASK(7, 0));
1518 }
1519 
1520 static inline void SET_DCTL_SEC_ENT4_V1(void *table, u32 val)
1521 {
1522 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(15, 8));
1523 	le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1524 			   GENMASK(15, 8));
1525 }
1526 
1527 static inline void SET_DCTL_SEC_ENT5_V1(void *table, u32 val)
1528 {
1529 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 16));
1530 	le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1531 			   GENMASK(23, 16));
1532 }
1533 
1534 static inline void SET_DCTL_SEC_ENT6_V1(void *table, u32 val)
1535 {
1536 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 24));
1537 	le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1538 			   GENMASK(31, 24));
1539 }
1540 
1541 static inline void SET_BCN_UPD_PORT(void *h2c, u32 val)
1542 {
1543 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1544 }
1545 
1546 static inline void SET_BCN_UPD_MBSSID(void *h2c, u32 val)
1547 {
1548 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1549 }
1550 
1551 static inline void SET_BCN_UPD_BAND(void *h2c, u32 val)
1552 {
1553 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1554 }
1555 
1556 static inline void SET_BCN_UPD_GRP_IE_OFST(void *h2c, u32 val)
1557 {
1558 	le32p_replace_bits((__le32 *)h2c, (val - 24) | BIT(7), GENMASK(31, 24));
1559 }
1560 
1561 static inline void SET_BCN_UPD_MACID(void *h2c, u32 val)
1562 {
1563 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1564 }
1565 
1566 static inline void SET_BCN_UPD_SSN_SEL(void *h2c, u32 val)
1567 {
1568 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(9, 8));
1569 }
1570 
1571 static inline void SET_BCN_UPD_SSN_MODE(void *h2c, u32 val)
1572 {
1573 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(11, 10));
1574 }
1575 
1576 static inline void SET_BCN_UPD_RATE(void *h2c, u32 val)
1577 {
1578 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(20, 12));
1579 }
1580 
1581 static inline void SET_BCN_UPD_TXPWR(void *h2c, u32 val)
1582 {
1583 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(23, 21));
1584 }
1585 
1586 static inline void SET_BCN_UPD_TXINFO_CTRL_EN(void *h2c, u32 val)
1587 {
1588 	le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(0));
1589 }
1590 
1591 static inline void SET_BCN_UPD_NTX_PATH_EN(void *h2c, u32 val)
1592 {
1593 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(4, 1));
1594 }
1595 
1596 static inline void SET_BCN_UPD_PATH_MAP_A(void *h2c, u32 val)
1597 {
1598 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(6, 5));
1599 }
1600 
1601 static inline void SET_BCN_UPD_PATH_MAP_B(void *h2c, u32 val)
1602 {
1603 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(8, 7));
1604 }
1605 
1606 static inline void SET_BCN_UPD_PATH_MAP_C(void *h2c, u32 val)
1607 {
1608 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(10, 9));
1609 }
1610 
1611 static inline void SET_BCN_UPD_PATH_MAP_D(void *h2c, u32 val)
1612 {
1613 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(12, 11));
1614 }
1615 
1616 static inline void SET_BCN_UPD_PATH_ANTSEL_A(void *h2c, u32 val)
1617 {
1618 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  BIT(13));
1619 }
1620 
1621 static inline void SET_BCN_UPD_PATH_ANTSEL_B(void *h2c, u32 val)
1622 {
1623 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  BIT(14));
1624 }
1625 
1626 static inline void SET_BCN_UPD_PATH_ANTSEL_C(void *h2c, u32 val)
1627 {
1628 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  BIT(15));
1629 }
1630 
1631 static inline void SET_BCN_UPD_PATH_ANTSEL_D(void *h2c, u32 val)
1632 {
1633 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  BIT(16));
1634 }
1635 
1636 static inline void SET_BCN_UPD_CSA_OFST(void *h2c, u32 val)
1637 {
1638 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(31, 17));
1639 }
1640 
1641 static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val)
1642 {
1643 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1644 }
1645 
1646 static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val)
1647 {
1648 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8));
1649 }
1650 
1651 static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val)
1652 {
1653 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10));
1654 }
1655 
1656 static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val)
1657 {
1658 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13));
1659 }
1660 
1661 static inline void SET_JOININFO_MACID(void *h2c, u32 val)
1662 {
1663 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1664 }
1665 
1666 static inline void SET_JOININFO_OP(void *h2c, u32 val)
1667 {
1668 	le32p_replace_bits((__le32 *)h2c, val, BIT(8));
1669 }
1670 
1671 static inline void SET_JOININFO_BAND(void *h2c, u32 val)
1672 {
1673 	le32p_replace_bits((__le32 *)h2c, val, BIT(9));
1674 }
1675 
1676 static inline void SET_JOININFO_WMM(void *h2c, u32 val)
1677 {
1678 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10));
1679 }
1680 
1681 static inline void SET_JOININFO_TGR(void *h2c, u32 val)
1682 {
1683 	le32p_replace_bits((__le32 *)h2c, val, BIT(12));
1684 }
1685 
1686 static inline void SET_JOININFO_ISHESTA(void *h2c, u32 val)
1687 {
1688 	le32p_replace_bits((__le32 *)h2c, val, BIT(13));
1689 }
1690 
1691 static inline void SET_JOININFO_DLBW(void *h2c, u32 val)
1692 {
1693 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14));
1694 }
1695 
1696 static inline void SET_JOININFO_TF_MAC_PAD(void *h2c, u32 val)
1697 {
1698 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16));
1699 }
1700 
1701 static inline void SET_JOININFO_DL_T_PE(void *h2c, u32 val)
1702 {
1703 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18));
1704 }
1705 
1706 static inline void SET_JOININFO_PORT_ID(void *h2c, u32 val)
1707 {
1708 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21));
1709 }
1710 
1711 static inline void SET_JOININFO_NET_TYPE(void *h2c, u32 val)
1712 {
1713 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24));
1714 }
1715 
1716 static inline void SET_JOININFO_WIFI_ROLE(void *h2c, u32 val)
1717 {
1718 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26));
1719 }
1720 
1721 static inline void SET_JOININFO_SELF_ROLE(void *h2c, u32 val)
1722 {
1723 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30));
1724 }
1725 
1726 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val)
1727 {
1728 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1729 }
1730 
1731 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val)
1732 {
1733 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1734 }
1735 
1736 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val)
1737 {
1738 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1739 }
1740 
1741 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val)
1742 {
1743 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1744 }
1745 
1746 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val)
1747 {
1748 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1749 }
1750 
1751 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val)
1752 {
1753 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1754 }
1755 
1756 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val)
1757 {
1758 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1759 }
1760 
1761 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val)
1762 {
1763 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1764 }
1765 
1766 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val)
1767 {
1768 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
1769 }
1770 
1771 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val)
1772 {
1773 	le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0));
1774 }
1775 
1776 static inline void SET_BA_CAM_VALID(void *h2c, u32 val)
1777 {
1778 	le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1779 }
1780 
1781 static inline void SET_BA_CAM_INIT_REQ(void *h2c, u32 val)
1782 {
1783 	le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1784 }
1785 
1786 static inline void SET_BA_CAM_ENTRY_IDX(void *h2c, u32 val)
1787 {
1788 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2));
1789 }
1790 
1791 static inline void SET_BA_CAM_TID(void *h2c, u32 val)
1792 {
1793 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4));
1794 }
1795 
1796 static inline void SET_BA_CAM_MACID(void *h2c, u32 val)
1797 {
1798 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1799 }
1800 
1801 static inline void SET_BA_CAM_BMAP_SIZE(void *h2c, u32 val)
1802 {
1803 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1804 }
1805 
1806 static inline void SET_BA_CAM_SSN(void *h2c, u32 val)
1807 {
1808 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20));
1809 }
1810 
1811 static inline void SET_BA_CAM_UID(void *h2c, u32 val)
1812 {
1813 	le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(7, 0));
1814 }
1815 
1816 static inline void SET_BA_CAM_STD_EN(void *h2c, u32 val)
1817 {
1818 	le32p_replace_bits((__le32 *)h2c + 1, val, BIT(8));
1819 }
1820 
1821 static inline void SET_BA_CAM_BAND(void *h2c, u32 val)
1822 {
1823 	le32p_replace_bits((__le32 *)h2c + 1, val, BIT(9));
1824 }
1825 
1826 static inline void SET_BA_CAM_ENTRY_IDX_V1(void *h2c, u32 val)
1827 {
1828 	le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 28));
1829 }
1830 
1831 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val)
1832 {
1833 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1834 }
1835 
1836 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val)
1837 {
1838 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1839 }
1840 
1841 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val)
1842 {
1843 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1844 }
1845 
1846 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val)
1847 {
1848 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20));
1849 }
1850 
1851 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val)
1852 {
1853 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1854 }
1855 
1856 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val)
1857 {
1858 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0));
1859 }
1860 
1861 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val)
1862 {
1863 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1));
1864 }
1865 
1866 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val)
1867 {
1868 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2));
1869 }
1870 
1871 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val)
1872 {
1873 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3));
1874 }
1875 
1876 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val)
1877 {
1878 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1879 }
1880 
1881 static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val)
1882 {
1883 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0));
1884 }
1885 
1886 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val)
1887 {
1888 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
1889 }
1890 
1891 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val)
1892 {
1893 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
1894 }
1895 
1896 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val)
1897 {
1898 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
1899 }
1900 
1901 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val)
1902 {
1903 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
1904 }
1905 
1906 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val)
1907 {
1908 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0));
1909 }
1910 
1911 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val)
1912 {
1913 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8));
1914 }
1915 
1916 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val)
1917 {
1918 	le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
1919 }
1920 
1921 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val)
1922 {
1923 	le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
1924 }
1925 
1926 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val)
1927 {
1928 	le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
1929 }
1930 
1931 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val)
1932 {
1933 	le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0));
1934 }
1935 
1936 static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val)
1937 {
1938 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0));
1939 }
1940 
1941 static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val)
1942 {
1943 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1944 }
1945 
1946 static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val)
1947 {
1948 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16));
1949 }
1950 
1951 static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val)
1952 {
1953 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1954 }
1955 
1956 static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val)
1957 {
1958 	le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1959 }
1960 
1961 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val)
1962 {
1963 	le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1964 }
1965 
1966 static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val)
1967 {
1968 	le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1969 }
1970 
1971 static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val)
1972 {
1973 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1974 }
1975 
1976 static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val)
1977 {
1978 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1979 }
1980 
1981 static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val)
1982 {
1983 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1984 }
1985 
1986 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val)
1987 {
1988 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1989 }
1990 
1991 static inline void RTW89_SET_WOW_GLOBAL_ENABLE(void *h2c, u32 val)
1992 {
1993 	le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1994 }
1995 
1996 static inline void RTW89_SET_WOW_GLOBAL_DROP_ALL_PKT(void *h2c, u32 val)
1997 {
1998 	le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1999 }
2000 
2001 static inline void RTW89_SET_WOW_GLOBAL_RX_PARSE_AFTER_WAKE(void *h2c, u32 val)
2002 {
2003 	le32p_replace_bits((__le32 *)h2c, val, BIT(2));
2004 }
2005 
2006 static inline void RTW89_SET_WOW_GLOBAL_WAKE_BAR_PULLED(void *h2c, u32 val)
2007 {
2008 	le32p_replace_bits((__le32 *)h2c, val, BIT(3));
2009 }
2010 
2011 static inline void RTW89_SET_WOW_GLOBAL_MAC_ID(void *h2c, u32 val)
2012 {
2013 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
2014 }
2015 
2016 static inline void RTW89_SET_WOW_GLOBAL_PAIRWISE_SEC_ALGO(void *h2c, u32 val)
2017 {
2018 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
2019 }
2020 
2021 static inline void RTW89_SET_WOW_GLOBAL_GROUP_SEC_ALGO(void *h2c, u32 val)
2022 {
2023 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
2024 }
2025 
2026 static inline void RTW89_SET_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT(void *h2c, u32 val)
2027 {
2028 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
2029 }
2030 
2031 static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val)
2032 {
2033 	le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2034 }
2035 
2036 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val)
2037 {
2038 	le32p_replace_bits((__le32 *)h2c, val, BIT(1));
2039 }
2040 
2041 static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val)
2042 {
2043 	le32p_replace_bits((__le32 *)h2c, val, BIT(2));
2044 }
2045 
2046 static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val)
2047 {
2048 	le32p_replace_bits((__le32 *)h2c, val, BIT(3));
2049 }
2050 
2051 static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val)
2052 {
2053 	le32p_replace_bits((__le32 *)h2c, val, BIT(4));
2054 }
2055 
2056 static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val)
2057 {
2058 	le32p_replace_bits((__le32 *)h2c, val, BIT(5));
2059 }
2060 
2061 static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val)
2062 {
2063 	le32p_replace_bits((__le32 *)h2c, val, BIT(6));
2064 }
2065 
2066 static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val)
2067 {
2068 	le32p_replace_bits((__le32 *)h2c, val, BIT(7));
2069 }
2070 
2071 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val)
2072 {
2073 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
2074 }
2075 
2076 static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val)
2077 {
2078 	le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2079 }
2080 
2081 static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val)
2082 {
2083 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1));
2084 }
2085 
2086 static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val)
2087 {
2088 	le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0));
2089 }
2090 
2091 static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val)
2092 {
2093 	le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0));
2094 }
2095 
2096 static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val)
2097 {
2098 	le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0));
2099 }
2100 
2101 static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val)
2102 {
2103 	le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0));
2104 }
2105 
2106 static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val)
2107 {
2108 	le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0));
2109 }
2110 
2111 static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val)
2112 {
2113 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22));
2114 }
2115 
2116 static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val)
2117 {
2118 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23));
2119 }
2120 
2121 static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val)
2122 {
2123 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24));
2124 }
2125 
2126 static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val)
2127 {
2128 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25));
2129 }
2130 
2131 static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val)
2132 {
2133 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26));
2134 }
2135 
2136 static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val)
2137 {
2138 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31));
2139 }
2140 
2141 enum rtw89_btc_btf_h2c_class {
2142 	BTFC_SET = 0x10,
2143 	BTFC_GET = 0x11,
2144 	BTFC_FW_EVENT = 0x12,
2145 };
2146 
2147 enum rtw89_btc_btf_set {
2148 	SET_REPORT_EN = 0x0,
2149 	SET_SLOT_TABLE,
2150 	SET_MREG_TABLE,
2151 	SET_CX_POLICY,
2152 	SET_GPIO_DBG,
2153 	SET_DRV_INFO,
2154 	SET_DRV_EVENT,
2155 	SET_BT_WREG_ADDR,
2156 	SET_BT_WREG_VAL,
2157 	SET_BT_RREG_ADDR,
2158 	SET_BT_WL_CH_INFO,
2159 	SET_BT_INFO_REPORT,
2160 	SET_BT_IGNORE_WLAN_ACT,
2161 	SET_BT_TX_PWR,
2162 	SET_BT_LNA_CONSTRAIN,
2163 	SET_BT_GOLDEN_RX_RANGE,
2164 	SET_BT_PSD_REPORT,
2165 	SET_H2C_TEST,
2166 	SET_MAX1,
2167 };
2168 
2169 enum rtw89_btc_cxdrvinfo {
2170 	CXDRVINFO_INIT = 0,
2171 	CXDRVINFO_ROLE,
2172 	CXDRVINFO_DBCC,
2173 	CXDRVINFO_SMAP,
2174 	CXDRVINFO_RFK,
2175 	CXDRVINFO_RUN,
2176 	CXDRVINFO_CTRL,
2177 	CXDRVINFO_SCAN,
2178 	CXDRVINFO_TRX,  /* WL traffic to WL fw */
2179 	CXDRVINFO_MAX,
2180 };
2181 
2182 enum rtw89_scan_mode {
2183 	RTW89_SCAN_IMMEDIATE,
2184 };
2185 
2186 enum rtw89_scan_type {
2187 	RTW89_SCAN_ONCE,
2188 };
2189 
2190 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val)
2191 {
2192 	u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0));
2193 }
2194 
2195 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val)
2196 {
2197 	u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0));
2198 }
2199 
2200 struct rtw89_h2c_cxhdr {
2201 	u8 type;
2202 	u8 len;
2203 } __packed;
2204 
2205 #define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr)
2206 
2207 struct rtw89_h2c_cxinit {
2208 	struct rtw89_h2c_cxhdr hdr;
2209 	u8 ant_type;
2210 	u8 ant_num;
2211 	u8 ant_iso;
2212 	u8 ant_info;
2213 	u8 mod_rfe;
2214 	u8 mod_cv;
2215 	u8 mod_info;
2216 	u8 mod_adie_kt;
2217 	u8 wl_gch;
2218 	u8 info;
2219 	u8 rsvd;
2220 	u8 rsvd1;
2221 } __packed;
2222 
2223 #define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0)
2224 #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1)
2225 #define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2)
2226 #define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4)
2227 
2228 #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0)
2229 #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1)
2230 #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2)
2231 #define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3)
2232 
2233 #define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0)
2234 #define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1)
2235 #define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2)
2236 #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3)
2237 #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4)
2238 
2239 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val)
2240 {
2241 	u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0));
2242 }
2243 
2244 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val)
2245 {
2246 	u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0));
2247 }
2248 
2249 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val)
2250 {
2251 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0));
2252 }
2253 
2254 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val)
2255 {
2256 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1));
2257 }
2258 
2259 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val)
2260 {
2261 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2));
2262 }
2263 
2264 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val)
2265 {
2266 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3));
2267 }
2268 
2269 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val)
2270 {
2271 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4));
2272 }
2273 
2274 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val)
2275 {
2276 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5));
2277 }
2278 
2279 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val)
2280 {
2281 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6));
2282 }
2283 
2284 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val)
2285 {
2286 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7));
2287 }
2288 
2289 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val)
2290 {
2291 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8));
2292 }
2293 
2294 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val)
2295 {
2296 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9));
2297 }
2298 
2299 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val)
2300 {
2301 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10));
2302 }
2303 
2304 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val)
2305 {
2306 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11));
2307 }
2308 
2309 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset)
2310 {
2311 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2312 }
2313 
2314 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset)
2315 {
2316 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2317 }
2318 
2319 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset)
2320 {
2321 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2322 }
2323 
2324 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset)
2325 {
2326 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2327 }
2328 
2329 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset)
2330 {
2331 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2332 }
2333 
2334 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset)
2335 {
2336 	u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2337 }
2338 
2339 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset)
2340 {
2341 	u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2342 }
2343 
2344 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset)
2345 {
2346 	u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2347 }
2348 
2349 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset)
2350 {
2351 	u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2352 }
2353 
2354 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset)
2355 {
2356 	le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0));
2357 }
2358 
2359 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset)
2360 {
2361 	le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0));
2362 }
2363 
2364 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset)
2365 {
2366 	le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0));
2367 }
2368 
2369 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset)
2370 {
2371 	le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0));
2372 }
2373 
2374 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset)
2375 {
2376 	le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0));
2377 }
2378 
2379 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset)
2380 {
2381 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2382 }
2383 
2384 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset)
2385 {
2386 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2387 }
2388 
2389 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset)
2390 {
2391 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2392 }
2393 
2394 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset)
2395 {
2396 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2397 }
2398 
2399 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset)
2400 {
2401 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2402 }
2403 
2404 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset)
2405 {
2406 	u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2407 }
2408 
2409 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset)
2410 {
2411 	u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2412 }
2413 
2414 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset)
2415 {
2416 	u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2417 }
2418 
2419 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset)
2420 {
2421 	u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2422 }
2423 
2424 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset)
2425 {
2426 	le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0));
2427 }
2428 
2429 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset)
2430 {
2431 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0));
2432 }
2433 
2434 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset)
2435 {
2436 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0));
2437 }
2438 
2439 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset)
2440 {
2441 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0));
2442 }
2443 
2444 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset)
2445 {
2446 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1));
2447 }
2448 
2449 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset)
2450 {
2451 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2));
2452 }
2453 
2454 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset)
2455 {
2456 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4));
2457 }
2458 
2459 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val)
2460 {
2461 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0));
2462 }
2463 
2464 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val)
2465 {
2466 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1));
2467 }
2468 
2469 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val)
2470 {
2471 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2));
2472 }
2473 
2474 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val)
2475 {
2476 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3));
2477 }
2478 
2479 static inline void RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val)
2480 {
2481 	u8p_replace_bits((u8 *)cmd + 2, val, GENMASK(7, 0));
2482 }
2483 
2484 static inline void RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val)
2485 {
2486 	u8p_replace_bits((u8 *)cmd + 3, val, GENMASK(7, 0));
2487 }
2488 
2489 static inline void RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val)
2490 {
2491 	u8p_replace_bits((u8 *)cmd + 4, val, GENMASK(7, 0));
2492 }
2493 
2494 static inline void RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val)
2495 {
2496 	u8p_replace_bits((u8 *)cmd + 5, val, GENMASK(7, 0));
2497 }
2498 
2499 static inline void RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val)
2500 {
2501 	u8p_replace_bits((u8 *)cmd + 6, val, GENMASK(7, 0));
2502 }
2503 
2504 static inline void RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val)
2505 {
2506 	u8p_replace_bits((u8 *)cmd + 7, val, GENMASK(7, 0));
2507 }
2508 
2509 static inline void RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val)
2510 {
2511 	u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0));
2512 }
2513 
2514 static inline void RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val)
2515 {
2516 	u8p_replace_bits((u8 *)cmd + 9, val, GENMASK(7, 0));
2517 }
2518 
2519 static inline void RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val)
2520 {
2521 	u8p_replace_bits((u8 *)cmd + 10, val, GENMASK(7, 0));
2522 }
2523 
2524 static inline void RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val)
2525 {
2526 	u8p_replace_bits((u8 *)cmd + 11, val, GENMASK(7, 0));
2527 }
2528 
2529 static inline void RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val)
2530 {
2531 	u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0));
2532 }
2533 
2534 static inline void RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val)
2535 {
2536 	u8p_replace_bits((u8 *)cmd + 13, val, GENMASK(7, 0));
2537 }
2538 
2539 static inline void RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val)
2540 {
2541 	le16p_replace_bits((__le16 *)((u8 *)cmd + 14), val, GENMASK(15, 0));
2542 }
2543 
2544 static inline void RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val)
2545 {
2546 	le16p_replace_bits((__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0));
2547 }
2548 
2549 static inline void RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val)
2550 {
2551 	le32p_replace_bits((__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0));
2552 }
2553 
2554 static inline void RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val)
2555 {
2556 	le32p_replace_bits((__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0));
2557 }
2558 
2559 static inline void RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val)
2560 {
2561 	le32p_replace_bits((__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0));
2562 }
2563 
2564 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val)
2565 {
2566 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0));
2567 }
2568 
2569 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val)
2570 {
2571 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2));
2572 }
2573 
2574 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val)
2575 {
2576 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6));
2577 }
2578 
2579 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val)
2580 {
2581 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8));
2582 }
2583 
2584 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val)
2585 {
2586 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10));
2587 }
2588 
2589 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val)
2590 {
2591 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2592 }
2593 
2594 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val)
2595 {
2596 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8));
2597 }
2598 
2599 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val)
2600 {
2601 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16));
2602 }
2603 
2604 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_NUM(void *cmd, u32 val)
2605 {
2606 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2607 }
2608 
2609 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_SIZE(void *cmd, u32 val)
2610 {
2611 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8));
2612 }
2613 
2614 static inline void RTW89_SET_FWCMD_CHINFO_PERIOD(void *cmd, u32 val)
2615 {
2616 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2617 }
2618 
2619 static inline void RTW89_SET_FWCMD_CHINFO_DWELL(void *cmd, u32 val)
2620 {
2621 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8));
2622 }
2623 
2624 static inline void RTW89_SET_FWCMD_CHINFO_CENTER_CH(void *cmd, u32 val)
2625 {
2626 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 16));
2627 }
2628 
2629 static inline void RTW89_SET_FWCMD_CHINFO_PRI_CH(void *cmd, u32 val)
2630 {
2631 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 24));
2632 }
2633 
2634 static inline void RTW89_SET_FWCMD_CHINFO_BW(void *cmd, u32 val)
2635 {
2636 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(2, 0));
2637 }
2638 
2639 static inline void RTW89_SET_FWCMD_CHINFO_ACTION(void *cmd, u32 val)
2640 {
2641 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 3));
2642 }
2643 
2644 static inline void RTW89_SET_FWCMD_CHINFO_NUM_PKT(void *cmd, u32 val)
2645 {
2646 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(11, 8));
2647 }
2648 
2649 static inline void RTW89_SET_FWCMD_CHINFO_TX(void *cmd, u32 val)
2650 {
2651 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(12));
2652 }
2653 
2654 static inline void RTW89_SET_FWCMD_CHINFO_PAUSE_DATA(void *cmd, u32 val)
2655 {
2656 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(13));
2657 }
2658 
2659 static inline void RTW89_SET_FWCMD_CHINFO_BAND(void *cmd, u32 val)
2660 {
2661 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 14));
2662 }
2663 
2664 static inline void RTW89_SET_FWCMD_CHINFO_PKT_ID(void *cmd, u32 val)
2665 {
2666 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16));
2667 }
2668 
2669 static inline void RTW89_SET_FWCMD_CHINFO_DFS(void *cmd, u32 val)
2670 {
2671 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(24));
2672 }
2673 
2674 static inline void RTW89_SET_FWCMD_CHINFO_TX_NULL(void *cmd, u32 val)
2675 {
2676 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(25));
2677 }
2678 
2679 static inline void RTW89_SET_FWCMD_CHINFO_RANDOM(void *cmd, u32 val)
2680 {
2681 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(26));
2682 }
2683 
2684 static inline void RTW89_SET_FWCMD_CHINFO_CFG_TX(void *cmd, u32 val)
2685 {
2686 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(27));
2687 }
2688 
2689 static inline void RTW89_SET_FWCMD_CHINFO_PKT0(void *cmd, u32 val)
2690 {
2691 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(7, 0));
2692 }
2693 
2694 static inline void RTW89_SET_FWCMD_CHINFO_PKT1(void *cmd, u32 val)
2695 {
2696 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 8));
2697 }
2698 
2699 static inline void RTW89_SET_FWCMD_CHINFO_PKT2(void *cmd, u32 val)
2700 {
2701 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16));
2702 }
2703 
2704 static inline void RTW89_SET_FWCMD_CHINFO_PKT3(void *cmd, u32 val)
2705 {
2706 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(31, 24));
2707 }
2708 
2709 static inline void RTW89_SET_FWCMD_CHINFO_PKT4(void *cmd, u32 val)
2710 {
2711 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(7, 0));
2712 }
2713 
2714 static inline void RTW89_SET_FWCMD_CHINFO_PKT5(void *cmd, u32 val)
2715 {
2716 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(15, 8));
2717 }
2718 
2719 static inline void RTW89_SET_FWCMD_CHINFO_PKT6(void *cmd, u32 val)
2720 {
2721 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(23, 16));
2722 }
2723 
2724 static inline void RTW89_SET_FWCMD_CHINFO_PKT7(void *cmd, u32 val)
2725 {
2726 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 24));
2727 }
2728 
2729 static inline void RTW89_SET_FWCMD_CHINFO_POWER_IDX(void *cmd, u32 val)
2730 {
2731 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(15, 0));
2732 }
2733 
2734 struct rtw89_h2c_scanofld {
2735 	__le32 w0;
2736 	__le32 w1;
2737 	__le32 w2;
2738 	__le32 tsf_high;
2739 	__le32 tsf_low;
2740 	__le32 w5;
2741 	__le32 w6;
2742 } __packed;
2743 
2744 #define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0)
2745 #define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8)
2746 #define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16)
2747 #define RTW89_H2C_SCANOFLD_W0_BAND BIT(19)
2748 #define RTW89_H2C_SCANOFLD_W0_OPERATION GENMASK(21, 20)
2749 #define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND GENMASK(23, 22)
2750 #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0)
2751 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1)
2752 #define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2)
2753 #define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE GENMASK(4, 3)
2754 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5)
2755 #define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8)
2756 #define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16)
2757 #define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24)
2758 #define RTW89_H2C_SCANOFLD_W2_NORM_PD GENMASK(15, 0)
2759 #define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16)
2760 
2761 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val)
2762 {
2763 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2764 }
2765 
2766 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val)
2767 {
2768 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8));
2769 }
2770 
2771 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val)
2772 {
2773 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12));
2774 }
2775 
2776 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val)
2777 {
2778 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16));
2779 }
2780 
2781 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val)
2782 {
2783 	le32p_replace_bits((__le32 *)cmd, val, BIT(20));
2784 }
2785 
2786 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val)
2787 {
2788 	le32p_replace_bits((__le32 *)cmd, val, BIT(21));
2789 }
2790 
2791 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val)
2792 {
2793 	*((__le32 *)cmd + 1) = val;
2794 }
2795 
2796 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val)
2797 {
2798 	*((__le32 *)cmd + 2) = val;
2799 }
2800 
2801 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val)
2802 {
2803 	*((__le32 *)cmd + 3) = val;
2804 }
2805 
2806 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val)
2807 {
2808 	le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0));
2809 }
2810 
2811 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val)
2812 {
2813 	u8 ctwnd;
2814 
2815 	if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT))
2816 		return;
2817 	ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val);
2818 	le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8));
2819 }
2820 
2821 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val)
2822 {
2823 	le32p_replace_bits((__le32 *)cmd, val, BIT(0));
2824 }
2825 
2826 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val)
2827 {
2828 	le32p_replace_bits((__le32 *)cmd, val, BIT(1));
2829 }
2830 
2831 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val)
2832 {
2833 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2));
2834 }
2835 
2836 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val)
2837 {
2838 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16));
2839 }
2840 
2841 enum rtw89_fw_mcc_c2h_rpt_cfg {
2842 	RTW89_FW_MCC_C2H_RPT_OFF	= 0,
2843 	RTW89_FW_MCC_C2H_RPT_FAIL_ONLY	= 1,
2844 	RTW89_FW_MCC_C2H_RPT_ALL	= 2,
2845 };
2846 
2847 struct rtw89_fw_mcc_add_req {
2848 	u8 macid;
2849 	u8 central_ch_seg0;
2850 	u8 central_ch_seg1;
2851 	u8 primary_ch;
2852 	enum rtw89_bandwidth bandwidth: 4;
2853 	u32 group: 2;
2854 	u32 c2h_rpt: 2;
2855 	u32 dis_tx_null: 1;
2856 	u32 dis_sw_retry: 1;
2857 	u32 in_curr_ch: 1;
2858 	u32 sw_retry_count: 3;
2859 	u32 tx_null_early: 4;
2860 	u32 btc_in_2g: 1;
2861 	u32 pta_en: 1;
2862 	u32 rfk_by_pass: 1;
2863 	u32 ch_band_type: 2;
2864 	u32 rsvd0: 9;
2865 	u32 duration;
2866 	u8 courtesy_en;
2867 	u8 courtesy_num;
2868 	u8 courtesy_target;
2869 	u8 rsvd1;
2870 };
2871 
2872 static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val)
2873 {
2874 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2875 }
2876 
2877 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val)
2878 {
2879 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
2880 }
2881 
2882 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val)
2883 {
2884 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
2885 }
2886 
2887 static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val)
2888 {
2889 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
2890 }
2891 
2892 static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val)
2893 {
2894 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0));
2895 }
2896 
2897 static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val)
2898 {
2899 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4));
2900 }
2901 
2902 static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val)
2903 {
2904 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6));
2905 }
2906 
2907 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val)
2908 {
2909 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8));
2910 }
2911 
2912 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val)
2913 {
2914 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9));
2915 }
2916 
2917 static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val)
2918 {
2919 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10));
2920 }
2921 
2922 static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val)
2923 {
2924 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11));
2925 }
2926 
2927 static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val)
2928 {
2929 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14));
2930 }
2931 
2932 static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val)
2933 {
2934 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18));
2935 }
2936 
2937 static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val)
2938 {
2939 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19));
2940 }
2941 
2942 static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val)
2943 {
2944 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20));
2945 }
2946 
2947 static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val)
2948 {
2949 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21));
2950 }
2951 
2952 static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val)
2953 {
2954 	le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
2955 }
2956 
2957 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val)
2958 {
2959 	le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0));
2960 }
2961 
2962 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val)
2963 {
2964 	le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8));
2965 }
2966 
2967 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val)
2968 {
2969 	le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16));
2970 }
2971 
2972 struct rtw89_fw_mcc_start_req {
2973 	u32 group: 2;
2974 	u32 btc_in_group: 1;
2975 	u32 old_group_action: 2;
2976 	u32 old_group: 2;
2977 	u32 rsvd0: 9;
2978 	u32 notify_cnt: 3;
2979 	u32 rsvd1: 2;
2980 	u32 notify_rxdbg_en: 1;
2981 	u32 rsvd2: 2;
2982 	u32 macid: 8;
2983 	u32 tsf_low;
2984 	u32 tsf_high;
2985 };
2986 
2987 static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val)
2988 {
2989 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
2990 }
2991 
2992 static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val)
2993 {
2994 	le32p_replace_bits((__le32 *)cmd, val, BIT(2));
2995 }
2996 
2997 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val)
2998 {
2999 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3));
3000 }
3001 
3002 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val)
3003 {
3004 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5));
3005 }
3006 
3007 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val)
3008 {
3009 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16));
3010 }
3011 
3012 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val)
3013 {
3014 	le32p_replace_bits((__le32 *)cmd, val, BIT(21));
3015 }
3016 
3017 static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val)
3018 {
3019 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3020 }
3021 
3022 static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val)
3023 {
3024 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3025 }
3026 
3027 static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val)
3028 {
3029 	le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3030 }
3031 
3032 static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val)
3033 {
3034 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
3035 }
3036 
3037 static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val)
3038 {
3039 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8));
3040 }
3041 
3042 static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val)
3043 {
3044 	le32p_replace_bits((__le32 *)cmd, val, BIT(10));
3045 }
3046 
3047 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val)
3048 {
3049 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3050 }
3051 
3052 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val)
3053 {
3054 	le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3055 }
3056 
3057 static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val)
3058 {
3059 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3060 }
3061 
3062 struct rtw89_fw_mcc_tsf_req {
3063 	u8 group: 2;
3064 	u8 rsvd0: 6;
3065 	u8 macid_x;
3066 	u8 macid_y;
3067 	u8 rsvd1;
3068 };
3069 
3070 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val)
3071 {
3072 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3073 }
3074 
3075 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val)
3076 {
3077 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3078 }
3079 
3080 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val)
3081 {
3082 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3083 }
3084 
3085 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val)
3086 {
3087 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3088 }
3089 
3090 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val)
3091 {
3092 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3093 }
3094 
3095 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val)
3096 {
3097 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3098 }
3099 
3100 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd,
3101 							   u8 *bitmap, u8 len)
3102 {
3103 	memcpy((__le32 *)cmd + 1, bitmap, len);
3104 }
3105 
3106 static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val)
3107 {
3108 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3109 }
3110 
3111 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val)
3112 {
3113 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3114 }
3115 
3116 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val)
3117 {
3118 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3119 }
3120 
3121 static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val)
3122 {
3123 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3124 }
3125 
3126 struct rtw89_fw_mcc_duration {
3127 	u32 group: 2;
3128 	u32 btc_in_group: 1;
3129 	u32 rsvd0: 5;
3130 	u32 start_macid: 8;
3131 	u32 macid_x: 8;
3132 	u32 macid_y: 8;
3133 	u32 start_tsf_low;
3134 	u32 start_tsf_high;
3135 	u32 duration_x;
3136 	u32 duration_y;
3137 };
3138 
3139 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val)
3140 {
3141 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3142 }
3143 
3144 static
3145 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val)
3146 {
3147 	le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3148 }
3149 
3150 static
3151 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val)
3152 {
3153 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3154 }
3155 
3156 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val)
3157 {
3158 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3159 }
3160 
3161 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val)
3162 {
3163 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3164 }
3165 
3166 static
3167 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val)
3168 {
3169 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3170 }
3171 
3172 static
3173 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val)
3174 {
3175 	le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3176 }
3177 
3178 static
3179 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val)
3180 {
3181 	le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
3182 }
3183 
3184 static
3185 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val)
3186 {
3187 	le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
3188 }
3189 
3190 #define RTW89_C2H_HEADER_LEN 8
3191 
3192 #define RTW89_GET_C2H_CATEGORY(c2h) \
3193 	le32_get_bits(*((const __le32 *)c2h), GENMASK(1, 0))
3194 #define RTW89_GET_C2H_CLASS(c2h) \
3195 	le32_get_bits(*((const __le32 *)c2h), GENMASK(7, 2))
3196 #define RTW89_GET_C2H_FUNC(c2h) \
3197 	le32_get_bits(*((const __le32 *)c2h), GENMASK(15, 8))
3198 #define RTW89_GET_C2H_LEN(c2h) \
3199 	le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(13, 0))
3200 
3201 struct rtw89_fw_c2h_attr {
3202 	u8 category;
3203 	u8 class;
3204 	u8 func;
3205 	u16 len;
3206 };
3207 
3208 static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb)
3209 {
3210 	static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
3211 
3212 	return (struct rtw89_fw_c2h_attr *)skb->cb;
3213 }
3214 
3215 #define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2)
3216 #define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN)
3217 
3218 #define RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h) \
3219 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3220 #define RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h) \
3221 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3222 #define RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h) \
3223 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3224 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h) \
3225 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
3226 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h) \
3227 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24))
3228 
3229 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \
3230 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3231 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \
3232 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3233 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \
3234 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3235 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \
3236 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
3237 
3238 struct rtw89_c2h_mac_bcnfltr_rpt {
3239 	__le32 w0;
3240 	__le32 w1;
3241 	__le32 w2;
3242 } __packed;
3243 
3244 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0)
3245 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8)
3246 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10)
3247 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16)
3248 
3249 #define RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h) \
3250 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 0))
3251 #define RTW89_GET_PHY_C2H_RA_RPT_RETRY_RATIO(c2h) \
3252 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
3253 #define RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h) \
3254 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(6, 0))
3255 #define RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h) \
3256 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(9, 8))
3257 #define RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h) \
3258 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(12, 10))
3259 #define RTW89_GET_PHY_C2H_RA_RPT_BW(c2h) \
3260 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(14, 13))
3261 
3262 /* VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
3263  * HT-new: [6:5]: NA, [4:0]: MCS
3264  */
3265 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
3266 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
3267 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
3268 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
3269 				    FIELD_PREP(GENMASK(2, 0), mcs))
3270 
3271 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \
3272 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3273 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \
3274 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))
3275 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \
3276 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))
3277 
3278 #define RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h) \
3279 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3280 #define RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h) \
3281 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(19, 16))
3282 #define RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h) \
3283 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 20))
3284 #define RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h) \
3285 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24))
3286 #define RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h) \
3287 	le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(3, 0))
3288 #define RTW89_GET_MAC_C2H_SCANOFLD_AIR_DENSITY(c2h) \
3289 	le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(7, 4))
3290 #define RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h) \
3291 	le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(25, 24))
3292 
3293 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \
3294 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3295 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \
3296 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3297 
3298 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \
3299 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3300 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \
3301 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3302 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \
3303 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3304 
3305 struct rtw89_mac_mcc_tsf_rpt {
3306 	u32 macid_x;
3307 	u32 macid_y;
3308 	u32 tsf_x_low;
3309 	u32 tsf_x_high;
3310 	u32 tsf_y_low;
3311 	u32 tsf_y_high;
3312 };
3313 
3314 static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3315 
3316 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \
3317 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3318 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \
3319 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3320 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \
3321 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16))
3322 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \
3323 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3324 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \
3325 	le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3326 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \
3327 	le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0))
3328 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \
3329 	le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0))
3330 
3331 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \
3332 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0))
3333 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \
3334 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6))
3335 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \
3336 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3337 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \
3338 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3339 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \
3340 	le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3341 
3342 struct rtw89_h2c_bcnfltr {
3343 	__le32 w0;
3344 } __packed;
3345 
3346 #define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0)
3347 #define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1)
3348 #define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2)
3349 #define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3)
3350 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT GENMASK(11, 8)
3351 #define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12)
3352 #define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16)
3353 #define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24)
3354 
3355 struct rtw89_h2c_ofld_rssi {
3356 	__le32 w0;
3357 	__le32 w1;
3358 } __packed;
3359 
3360 #define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0)
3361 #define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8)
3362 #define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0)
3363 
3364 struct rtw89_h2c_ofld {
3365 	__le32 w0;
3366 } __packed;
3367 
3368 #define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0)
3369 #define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8)
3370 #define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18)
3371 
3372 #define RTW89_FW_HDR_SIZE 32
3373 #define RTW89_FW_SECTION_HDR_SIZE 16
3374 
3375 #define RTW89_MFW_SIG	0xFF
3376 
3377 struct rtw89_mfw_info {
3378 	u8 cv;
3379 	u8 type; /* enum rtw89_fw_type */
3380 	u8 mp;
3381 	u8 rsvd;
3382 	__le32 shift;
3383 	__le32 size;
3384 	u8 rsvd2[4];
3385 } __packed;
3386 
3387 struct rtw89_mfw_hdr {
3388 	u8 sig;	/* RTW89_MFW_SIG */
3389 	u8 fw_nr;
3390 	u8 rsvd0[2];
3391 	struct {
3392 		u8 major;
3393 		u8 minor;
3394 		u8 sub;
3395 		u8 idx;
3396 	} ver;
3397 	u8 rsvd1[8];
3398 	struct rtw89_mfw_info info[];
3399 } __packed;
3400 
3401 struct fwcmd_hdr {
3402 	__le32 hdr0;
3403 	__le32 hdr1;
3404 };
3405 
3406 union rtw89_compat_fw_hdr {
3407 	struct rtw89_mfw_hdr mfw_hdr;
3408 	u8 fw_hdr[RTW89_FW_HDR_SIZE];
3409 };
3410 
3411 static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf)
3412 {
3413 	const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf;
3414 
3415 	if (compat->mfw_hdr.sig == RTW89_MFW_SIG)
3416 		return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr);
3417 	else
3418 		return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr);
3419 }
3420 
3421 static inline void rtw89_fw_get_filename(char *buf, size_t size,
3422 					 const char *fw_basename, int fw_format)
3423 {
3424 	if (fw_format <= 0)
3425 		snprintf(buf, size, "%s.bin", fw_basename);
3426 	else
3427 		snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format);
3428 }
3429 
3430 #define RTW89_H2C_RF_PAGE_SIZE 500
3431 #define RTW89_H2C_RF_PAGE_NUM 3
3432 struct rtw89_fw_h2c_rf_reg_info {
3433 	enum rtw89_rf_path rf_path;
3434 	__le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE];
3435 	u16 curr_idx;
3436 };
3437 
3438 #define H2C_SEC_CAM_LEN			24
3439 
3440 #define H2C_HEADER_LEN			8
3441 #define H2C_HDR_CAT			GENMASK(1, 0)
3442 #define H2C_HDR_CLASS			GENMASK(7, 2)
3443 #define H2C_HDR_FUNC			GENMASK(15, 8)
3444 #define H2C_HDR_DEL_TYPE		GENMASK(19, 16)
3445 #define H2C_HDR_H2C_SEQ			GENMASK(31, 24)
3446 #define H2C_HDR_TOTAL_LEN		GENMASK(13, 0)
3447 #define H2C_HDR_REC_ACK			BIT(14)
3448 #define H2C_HDR_DONE_ACK		BIT(15)
3449 
3450 #define FWCMD_TYPE_H2C			0
3451 
3452 #define H2C_CAT_TEST		0x0
3453 
3454 /* CLASS 5 - FW STATUS TEST */
3455 #define H2C_CL_FW_STATUS_TEST		0x5
3456 #define H2C_FUNC_CPU_EXCEPTION		0x1
3457 
3458 #define H2C_CAT_MAC		0x1
3459 
3460 /* CLASS 0 - FW INFO */
3461 #define H2C_CL_FW_INFO			0x0
3462 #define H2C_FUNC_LOG_CFG		0x0
3463 #define H2C_FUNC_MAC_GENERAL_PKT	0x1
3464 
3465 /* CLASS 1 - WOW */
3466 #define H2C_CL_MAC_WOW			0x1
3467 #define H2C_FUNC_KEEP_ALIVE		0x0
3468 #define H2C_FUNC_DISCONNECT_DETECT	0x1
3469 #define H2C_FUNC_WOW_GLOBAL		0x2
3470 #define H2C_FUNC_WAKEUP_CTRL		0x8
3471 #define H2C_FUNC_WOW_CAM_UPD		0xC
3472 
3473 /* CLASS 2 - PS */
3474 #define H2C_CL_MAC_PS			0x2
3475 #define H2C_FUNC_MAC_LPS_PARM		0x0
3476 #define H2C_FUNC_P2P_ACT		0x1
3477 
3478 /* CLASS 3 - FW download */
3479 #define H2C_CL_MAC_FWDL		0x3
3480 #define H2C_FUNC_MAC_FWHDR_DL		0x0
3481 
3482 /* CLASS 5 - Frame Exchange */
3483 #define H2C_CL_MAC_FR_EXCHG		0x5
3484 #define H2C_FUNC_MAC_CCTLINFO_UD	0x2
3485 #define H2C_FUNC_MAC_BCN_UPD		0x5
3486 #define H2C_FUNC_MAC_DCTLINFO_UD_V1	0x9
3487 #define H2C_FUNC_MAC_CCTLINFO_UD_V1	0xa
3488 
3489 /* CLASS 6 - Address CAM */
3490 #define H2C_CL_MAC_ADDR_CAM_UPDATE	0x6
3491 #define H2C_FUNC_MAC_ADDR_CAM_UPD	0x0
3492 
3493 /* CLASS 8 - Media Status Report */
3494 #define H2C_CL_MAC_MEDIA_RPT		0x8
3495 #define H2C_FUNC_MAC_JOININFO		0x0
3496 #define H2C_FUNC_MAC_FWROLE_MAINTAIN	0x4
3497 
3498 /* CLASS 9 - FW offload */
3499 #define H2C_CL_MAC_FW_OFLD		0x9
3500 #define H2C_FUNC_PACKET_OFLD		0x1
3501 #define H2C_FUNC_MAC_MACID_PAUSE	0x8
3502 #define H2C_FUNC_USR_EDCA		0xF
3503 #define H2C_FUNC_TSF32_TOGL		0x10
3504 #define H2C_FUNC_OFLD_CFG		0x14
3505 #define H2C_FUNC_ADD_SCANOFLD_CH	0x16
3506 #define H2C_FUNC_SCANOFLD		0x17
3507 #define H2C_FUNC_PKT_DROP		0x1b
3508 #define H2C_FUNC_CFG_BCNFLTR		0x1e
3509 #define H2C_FUNC_OFLD_RSSI		0x1f
3510 #define H2C_FUNC_OFLD_TP		0x20
3511 
3512 /* CLASS 10 - Security CAM */
3513 #define H2C_CL_MAC_SEC_CAM		0xa
3514 #define H2C_FUNC_MAC_SEC_UPD		0x1
3515 
3516 /* CLASS 12 - BA CAM */
3517 #define H2C_CL_BA_CAM			0xc
3518 #define H2C_FUNC_MAC_BA_CAM		0x0
3519 
3520 /* CLASS 14 - MCC */
3521 #define H2C_CL_MCC			0xe
3522 enum rtw89_mcc_h2c_func {
3523 	H2C_FUNC_ADD_MCC		= 0x0,
3524 	H2C_FUNC_START_MCC		= 0x1,
3525 	H2C_FUNC_STOP_MCC		= 0x2,
3526 	H2C_FUNC_DEL_MCC_GROUP		= 0x3,
3527 	H2C_FUNC_RESET_MCC_GROUP	= 0x4,
3528 	H2C_FUNC_MCC_REQ_TSF		= 0x5,
3529 	H2C_FUNC_MCC_MACID_BITMAP	= 0x6,
3530 	H2C_FUNC_MCC_SYNC		= 0x7,
3531 	H2C_FUNC_MCC_SET_DURATION	= 0x8,
3532 
3533 	NUM_OF_RTW89_MCC_H2C_FUNC,
3534 };
3535 
3536 #define RTW89_MCC_WAIT_COND(group, func) \
3537 	((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func))
3538 
3539 #define H2C_CAT_OUTSRC			0x2
3540 
3541 #define H2C_CL_OUTSRC_RA		0x1
3542 #define H2C_FUNC_OUTSRC_RA_MACIDCFG	0x0
3543 
3544 #define H2C_CL_OUTSRC_RF_REG_A		0x8
3545 #define H2C_CL_OUTSRC_RF_REG_B		0x9
3546 #define H2C_CL_OUTSRC_RF_FW_NOTIFY	0xa
3547 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH	0x2
3548 
3549 struct rtw89_fw_h2c_rf_get_mccch {
3550 	__le32 ch_0;
3551 	__le32 ch_1;
3552 	__le32 band_0;
3553 	__le32 band_1;
3554 	__le32 current_channel;
3555 	__le32 current_band_type;
3556 } __packed;
3557 
3558 #define RTW89_FW_RSVD_PLE_SIZE 0x800
3559 
3560 #define RTW89_WCPU_BASE_MASK GENMASK(27, 0)
3561 
3562 #define RTW89_FW_BACKTRACE_INFO_SIZE 8
3563 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \
3564 	((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0)
3565 
3566 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */
3567 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE
3568 
3569 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev);
3570 int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
3571 const struct firmware *
3572 rtw89_early_fw_feature_recognize(struct device *device,
3573 				 const struct rtw89_chip_info *chip,
3574 				 struct rtw89_fw_info *early_fw,
3575 				 int *used_fw_format);
3576 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type);
3577 void rtw89_load_firmware_work(struct work_struct *work);
3578 void rtw89_unload_firmware(struct rtw89_dev *rtwdev);
3579 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev);
3580 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb,
3581 			   u8 type, u8 cat, u8 class, u8 func,
3582 			   bool rack, bool dack, u32 len);
3583 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
3584 				  struct rtw89_vif *rtwvif);
3585 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
3586 				struct ieee80211_vif *vif,
3587 				struct ieee80211_sta *sta);
3588 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
3589 				 struct rtw89_sta *rtwsta);
3590 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev,
3591 				 struct rtw89_sta *rtwsta);
3592 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev,
3593 			       struct rtw89_vif *rtwvif);
3594 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif,
3595 		     struct rtw89_sta *rtwsta, const u8 *scan_mac_addr);
3596 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev,
3597 				 struct rtw89_vif *rtwvif,
3598 				 struct rtw89_sta *rtwsta);
3599 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h);
3600 void rtw89_fw_c2h_work(struct work_struct *work);
3601 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev,
3602 			       struct rtw89_vif *rtwvif,
3603 			       struct rtw89_sta *rtwsta,
3604 			       enum rtw89_upd_mode upd_mode);
3605 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3606 			   struct rtw89_sta *rtwsta, bool dis_conn);
3607 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp,
3608 			     bool pause);
3609 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3610 			  u8 ac, u32 val);
3611 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev);
3612 int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev,
3613 				  struct ieee80211_vif *vif,
3614 				  bool connect);
3615 int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev,
3616 			      struct rtw89_rx_phy_ppdu *phy_ppdu);
3617 int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
3618 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi);
3619 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev);
3620 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev);
3621 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev);
3622 int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev);
3623 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev);
3624 int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev);
3625 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev);
3626 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id);
3627 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
3628 				 struct sk_buff *skb_ofld);
3629 int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int len,
3630 				   struct list_head *chan_list);
3631 int rtw89_fw_h2c_scan_offload(struct rtw89_dev *rtwdev,
3632 			      struct rtw89_scan_option *opt,
3633 			      struct rtw89_vif *vif);
3634 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
3635 			struct rtw89_fw_h2c_rf_reg_info *info,
3636 			u16 len, u8 page);
3637 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev);
3638 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
3639 			      u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
3640 			      bool rack, bool dack);
3641 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len);
3642 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev);
3643 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
3644 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3645 			     u8 macid);
3646 void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev,
3647 					   struct rtw89_vif *rtwvif, bool notify_fw);
3648 void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw);
3649 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
3650 			bool valid, struct ieee80211_ampdu_params *params);
3651 void rtw89_fw_h2c_init_ba_cam_v1(struct rtw89_dev *rtwdev);
3652 
3653 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,
3654 			  struct rtw89_lps_parm *lps_param);
3655 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len);
3656 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len);
3657 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev,
3658 		     struct rtw89_mac_h2c_info *h2c_info,
3659 		     struct rtw89_mac_c2h_info *c2h_info);
3660 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable);
3661 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev);
3662 void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3663 			 struct ieee80211_scan_request *req);
3664 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3665 			    bool aborted);
3666 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3667 			  bool enable);
3668 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
3669 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev);
3670 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev,
3671 			  const struct rtw89_pkt_drop_params *params);
3672 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3673 			 struct ieee80211_p2p_noa_desc *desc,
3674 			 u8 act, u8 noa_id);
3675 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3676 			      bool en);
3677 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3678 			    bool enable);
3679 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
3680 				 struct rtw89_vif *rtwvif, bool enable);
3681 int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3682 			    bool enable);
3683 int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
3684 				   struct rtw89_vif *rtwvif, bool enable);
3685 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3686 			    bool enable);
3687 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
3688 				 struct rtw89_vif *rtwvif, bool enable);
3689 int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
3690 			    struct rtw89_wow_cam_info *cam_info);
3691 int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
3692 			 const struct rtw89_fw_mcc_add_req *p);
3693 int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
3694 			   const struct rtw89_fw_mcc_start_req *p);
3695 int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
3696 			  bool prev_groups);
3697 int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
3698 			       bool prev_groups);
3699 int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group);
3700 int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
3701 			     const struct rtw89_fw_mcc_tsf_req *req,
3702 			     struct rtw89_mac_mcc_tsf_rpt *rpt);
3703 int rtw89_fw_h2c_mcc_macid_bitamp(struct rtw89_dev *rtwdev, u8 group, u8 macid,
3704 				  u8 *bitmap);
3705 int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
3706 			  u8 target, u8 offset);
3707 int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
3708 				  const struct rtw89_fw_mcc_duration *p);
3709 
3710 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
3711 {
3712 	const struct rtw89_chip_info *chip = rtwdev->chip;
3713 
3714 	if (chip->bacam_v1)
3715 		rtw89_fw_h2c_init_ba_cam_v1(rtwdev);
3716 }
3717 
3718 #endif
3719