1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_FW_H__ 6 #define __RTW89_FW_H__ 7 8 #include "core.h" 9 10 enum rtw89_fw_dl_status { 11 RTW89_FWDL_INITIAL_STATE = 0, 12 RTW89_FWDL_FWDL_ONGOING = 1, 13 RTW89_FWDL_CHECKSUM_FAIL = 2, 14 RTW89_FWDL_SECURITY_FAIL = 3, 15 RTW89_FWDL_CV_NOT_MATCH = 4, 16 RTW89_FWDL_RSVD0 = 5, 17 RTW89_FWDL_WCPU_FWDL_RDY = 6, 18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7 19 }; 20 21 #define RTW89_GET_C2H_HDR_FUNC(info) \ 22 u32_get_bits(info, GENMASK(6, 0)) 23 #define RTW89_GET_C2H_HDR_LEN(info) \ 24 u32_get_bits(info, GENMASK(11, 8)) 25 26 #define RTW89_SET_H2CREG_HDR_FUNC(info, val) \ 27 u32p_replace_bits(info, val, GENMASK(6, 0)) 28 #define RTW89_SET_H2CREG_HDR_LEN(info, val) \ 29 u32p_replace_bits(info, val, GENMASK(11, 8)) 30 31 #define RTW89_H2CREG_MAX 4 32 #define RTW89_C2HREG_MAX 4 33 #define RTW89_C2HREG_HDR_LEN 2 34 #define RTW89_H2CREG_HDR_LEN 2 35 #define RTW89_C2H_TIMEOUT 1000000 36 struct rtw89_mac_c2h_info { 37 u8 id; 38 u8 content_len; 39 u32 c2hreg[RTW89_C2HREG_MAX]; 40 }; 41 42 struct rtw89_mac_h2c_info { 43 u8 id; 44 u8 content_len; 45 u32 h2creg[RTW89_H2CREG_MAX]; 46 }; 47 48 enum rtw89_mac_h2c_type { 49 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0, 50 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD, 51 RTW89_FWCMD_H2CREG_FUNC_FWERR, 52 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE, 53 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM, 54 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN 55 }; 56 57 enum rtw89_mac_c2h_type { 58 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0, 59 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT, 60 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG, 61 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP, 62 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT, 63 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF 64 }; 65 66 #define RTW89_GET_C2H_PHYCAP_FUNC(info) \ 67 u32_get_bits(*((const u32 *)(info)), GENMASK(6, 0)) 68 #define RTW89_GET_C2H_PHYCAP_ACK(info) \ 69 u32_get_bits(*((const u32 *)(info)), BIT(7)) 70 #define RTW89_GET_C2H_PHYCAP_LEN(info) \ 71 u32_get_bits(*((const u32 *)(info)), GENMASK(11, 8)) 72 #define RTW89_GET_C2H_PHYCAP_SEQ(info) \ 73 u32_get_bits(*((const u32 *)(info)), GENMASK(15, 12)) 74 #define RTW89_GET_C2H_PHYCAP_RX_NSS(info) \ 75 u32_get_bits(*((const u32 *)(info)), GENMASK(23, 16)) 76 #define RTW89_GET_C2H_PHYCAP_BW(info) \ 77 u32_get_bits(*((const u32 *)(info)), GENMASK(31, 24)) 78 #define RTW89_GET_C2H_PHYCAP_TX_NSS(info) \ 79 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(7, 0)) 80 #define RTW89_GET_C2H_PHYCAP_PROT(info) \ 81 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(15, 8)) 82 #define RTW89_GET_C2H_PHYCAP_NIC(info) \ 83 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(23, 16)) 84 #define RTW89_GET_C2H_PHYCAP_WL_FUNC(info) \ 85 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(31, 24)) 86 #define RTW89_GET_C2H_PHYCAP_HW_TYPE(info) \ 87 u32_get_bits(*((const u32 *)(info) + 2), GENMASK(7, 0)) 88 #define RTW89_GET_C2H_PHYCAP_ANT_TX_NUM(info) \ 89 u32_get_bits(*((const u32 *)(info) + 3), GENMASK(15, 8)) 90 #define RTW89_GET_C2H_PHYCAP_ANT_RX_NUM(info) \ 91 u32_get_bits(*((const u32 *)(info) + 3), GENMASK(23, 16)) 92 93 enum rtw89_fw_c2h_category { 94 RTW89_C2H_CAT_TEST, 95 RTW89_C2H_CAT_MAC, 96 RTW89_C2H_CAT_OUTSRC, 97 }; 98 99 enum rtw89_fw_log_level { 100 RTW89_FW_LOG_LEVEL_OFF, 101 RTW89_FW_LOG_LEVEL_CRT, 102 RTW89_FW_LOG_LEVEL_SER, 103 RTW89_FW_LOG_LEVEL_WARN, 104 RTW89_FW_LOG_LEVEL_LOUD, 105 RTW89_FW_LOG_LEVEL_TR, 106 }; 107 108 enum rtw89_fw_log_path { 109 RTW89_FW_LOG_LEVEL_UART, 110 RTW89_FW_LOG_LEVEL_C2H, 111 RTW89_FW_LOG_LEVEL_SNI, 112 }; 113 114 enum rtw89_fw_log_comp { 115 RTW89_FW_LOG_COMP_VER, 116 RTW89_FW_LOG_COMP_INIT, 117 RTW89_FW_LOG_COMP_TASK, 118 RTW89_FW_LOG_COMP_CNS, 119 RTW89_FW_LOG_COMP_H2C, 120 RTW89_FW_LOG_COMP_C2H, 121 RTW89_FW_LOG_COMP_TX, 122 RTW89_FW_LOG_COMP_RX, 123 RTW89_FW_LOG_COMP_IPSEC, 124 RTW89_FW_LOG_COMP_TIMER, 125 RTW89_FW_LOG_COMP_DBGPKT, 126 RTW89_FW_LOG_COMP_PS, 127 RTW89_FW_LOG_COMP_ERROR, 128 RTW89_FW_LOG_COMP_WOWLAN, 129 RTW89_FW_LOG_COMP_SECURE_BOOT, 130 RTW89_FW_LOG_COMP_BTC, 131 RTW89_FW_LOG_COMP_BB, 132 RTW89_FW_LOG_COMP_TWT, 133 RTW89_FW_LOG_COMP_RF, 134 RTW89_FW_LOG_COMP_MCC = 20, 135 }; 136 137 enum rtw89_pkt_offload_op { 138 RTW89_PKT_OFLD_OP_ADD, 139 RTW89_PKT_OFLD_OP_DEL, 140 RTW89_PKT_OFLD_OP_READ, 141 }; 142 143 enum rtw89_scanofld_notify_reason { 144 RTW89_SCAN_DWELL_NOTIFY, 145 RTW89_SCAN_PRE_TX_NOTIFY, 146 RTW89_SCAN_POST_TX_NOTIFY, 147 RTW89_SCAN_ENTER_CH_NOTIFY, 148 RTW89_SCAN_LEAVE_CH_NOTIFY, 149 RTW89_SCAN_END_SCAN_NOTIFY, 150 }; 151 152 enum rtw89_chan_type { 153 RTW89_CHAN_OPERATE = 0, 154 RTW89_CHAN_ACTIVE, 155 RTW89_CHAN_DFS, 156 }; 157 158 enum rtw89_p2pps_action { 159 RTW89_P2P_ACT_INIT = 0, 160 RTW89_P2P_ACT_UPDATE = 1, 161 RTW89_P2P_ACT_REMOVE = 2, 162 RTW89_P2P_ACT_TERMINATE = 3, 163 }; 164 165 #define FWDL_SECTION_MAX_NUM 10 166 #define FWDL_SECTION_CHKSUM_LEN 8 167 #define FWDL_SECTION_PER_PKT_LEN 2020 168 169 struct rtw89_fw_hdr_section_info { 170 u8 redl; 171 const u8 *addr; 172 u32 len; 173 u32 dladdr; 174 u32 mssc; 175 u8 type; 176 }; 177 178 struct rtw89_fw_bin_info { 179 u8 section_num; 180 u32 hdr_len; 181 bool dynamic_hdr_en; 182 u32 dynamic_hdr_len; 183 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM]; 184 }; 185 186 struct rtw89_fw_macid_pause_grp { 187 __le32 pause_grp[4]; 188 __le32 mask_grp[4]; 189 } __packed; 190 191 struct rtw89_h2creg_sch_tx_en { 192 u8 func:7; 193 u8 ack:1; 194 u8 total_len:4; 195 u8 seq_num:4; 196 u16 tx_en:16; 197 u16 mask:16; 198 u8 band:1; 199 u16 rsvd:15; 200 } __packed; 201 202 #define RTW89_H2C_MAX_SIZE 2048 203 #define RTW89_CHANNEL_TIME 45 204 #define RTW89_CHANNEL_TIME_6G 20 205 #define RTW89_DFS_CHAN_TIME 105 206 #define RTW89_OFF_CHAN_TIME 100 207 #define RTW89_DWELL_TIME 20 208 #define RTW89_DWELL_TIME_6G 10 209 #define RTW89_SCAN_WIDTH 0 210 #define RTW89_SCANOFLD_MAX_SSID 8 211 #define RTW89_SCANOFLD_MAX_IE_LEN 512 212 #define RTW89_SCANOFLD_PKT_NONE 0xFF 213 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F 214 #define RTW89_MAC_CHINFO_SIZE 24 215 #define RTW89_SCAN_LIST_GUARD 4 216 #define RTW89_SCAN_LIST_LIMIT \ 217 ((RTW89_H2C_MAX_SIZE / RTW89_MAC_CHINFO_SIZE) - RTW89_SCAN_LIST_GUARD) 218 219 struct rtw89_mac_chinfo { 220 u8 period; 221 u8 dwell_time; 222 u8 central_ch; 223 u8 pri_ch; 224 u8 bw:3; 225 u8 notify_action:5; 226 u8 num_pkt:4; 227 u8 tx_pkt:1; 228 u8 pause_data:1; 229 u8 ch_band:2; 230 u8 probe_id; 231 u8 dfs_ch:1; 232 u8 tx_null:1; 233 u8 rand_seq_num:1; 234 u8 cfg_tx_pwr:1; 235 u8 rsvd0: 4; 236 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID]; 237 u16 tx_pwr_idx; 238 u8 rsvd1; 239 struct list_head list; 240 }; 241 242 struct rtw89_scan_option { 243 bool enable; 244 bool target_ch_mode; 245 }; 246 247 struct rtw89_pktofld_info { 248 struct list_head list; 249 u8 id; 250 }; 251 252 static inline void RTW89_SET_FWCMD_RA_IS_DIS(void *cmd, u32 val) 253 { 254 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(0)); 255 } 256 257 static inline void RTW89_SET_FWCMD_RA_MODE(void *cmd, u32 val) 258 { 259 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(5, 1)); 260 } 261 262 static inline void RTW89_SET_FWCMD_RA_BW_CAP(void *cmd, u32 val) 263 { 264 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 6)); 265 } 266 267 static inline void RTW89_SET_FWCMD_RA_MACID(void *cmd, u32 val) 268 { 269 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); 270 } 271 272 static inline void RTW89_SET_FWCMD_RA_DCM(void *cmd, u32 val) 273 { 274 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(16)); 275 } 276 277 static inline void RTW89_SET_FWCMD_RA_ER(void *cmd, u32 val) 278 { 279 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(17)); 280 } 281 282 static inline void RTW89_SET_FWCMD_RA_INIT_RATE_LV(void *cmd, u32 val) 283 { 284 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(19, 18)); 285 } 286 287 static inline void RTW89_SET_FWCMD_RA_UPD_ALL(void *cmd, u32 val) 288 { 289 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(20)); 290 } 291 292 static inline void RTW89_SET_FWCMD_RA_SGI(void *cmd, u32 val) 293 { 294 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(21)); 295 } 296 297 static inline void RTW89_SET_FWCMD_RA_LDPC(void *cmd, u32 val) 298 { 299 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(22)); 300 } 301 302 static inline void RTW89_SET_FWCMD_RA_STBC(void *cmd, u32 val) 303 { 304 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(23)); 305 } 306 307 static inline void RTW89_SET_FWCMD_RA_SS_NUM(void *cmd, u32 val) 308 { 309 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(26, 24)); 310 } 311 312 static inline void RTW89_SET_FWCMD_RA_GILTF(void *cmd, u32 val) 313 { 314 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(29, 27)); 315 } 316 317 static inline void RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(void *cmd, u32 val) 318 { 319 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(30)); 320 } 321 322 static inline void RTW89_SET_FWCMD_RA_UPD_MASK(void *cmd, u32 val) 323 { 324 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(31)); 325 } 326 327 static inline void RTW89_SET_FWCMD_RA_MASK_0(void *cmd, u32 val) 328 { 329 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(7, 0)); 330 } 331 332 static inline void RTW89_SET_FWCMD_RA_MASK_1(void *cmd, u32 val) 333 { 334 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(15, 8)); 335 } 336 337 static inline void RTW89_SET_FWCMD_RA_MASK_2(void *cmd, u32 val) 338 { 339 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(23, 16)); 340 } 341 342 static inline void RTW89_SET_FWCMD_RA_MASK_3(void *cmd, u32 val) 343 { 344 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 24)); 345 } 346 347 static inline void RTW89_SET_FWCMD_RA_MASK_4(void *cmd, u32 val) 348 { 349 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(7, 0)); 350 } 351 352 static inline void RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(void *cmd, u32 val) 353 { 354 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, BIT(31)); 355 } 356 357 static inline void RTW89_SET_FWCMD_RA_BAND_NUM(void *cmd, u32 val) 358 { 359 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(7, 0)); 360 } 361 362 static inline void RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(void *cmd, u32 val) 363 { 364 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(8)); 365 } 366 367 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(void *cmd, u32 val) 368 { 369 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(9)); 370 } 371 372 static inline void RTW89_SET_FWCMD_RA_CR_TBL_SEL(void *cmd, u32 val) 373 { 374 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(10)); 375 } 376 377 static inline void RTW89_SET_FWCMD_RA_FIX_GILTF_EN(void *cmd, u32 val) 378 { 379 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(11)); 380 } 381 382 static inline void RTW89_SET_FWCMD_RA_FIX_GILTF(void *cmd, u32 val) 383 { 384 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(14, 12)); 385 } 386 387 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(void *cmd, u32 val) 388 { 389 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(23, 16)); 390 } 391 392 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(void *cmd, u32 val) 393 { 394 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(25, 24)); 395 } 396 397 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(void *cmd, u32 val) 398 { 399 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(28, 26)); 400 } 401 402 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_BW(void *cmd, u32 val) 403 { 404 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 29)); 405 } 406 407 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val) 408 { 409 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)); 410 } 411 412 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val) 413 { 414 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); 415 } 416 417 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val) 418 { 419 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)); 420 } 421 422 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val) 423 { 424 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0)); 425 } 426 427 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val) 428 { 429 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4)); 430 } 431 432 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val) 433 { 434 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5)); 435 } 436 437 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val) 438 { 439 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0)); 440 } 441 442 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val) 443 { 444 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0)); 445 } 446 447 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val) 448 { 449 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0)); 450 } 451 452 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val) 453 { 454 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0)); 455 } 456 457 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val) 458 { 459 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0)); 460 } 461 462 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val) 463 { 464 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3)); 465 } 466 467 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val) 468 { 469 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4)); 470 } 471 472 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val) 473 { 474 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5)); 475 } 476 477 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val) 478 { 479 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0)); 480 } 481 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16) 482 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12) 483 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8) 484 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0) 485 486 #define FWDL_SECURITY_SECTION_TYPE 9 487 #define FWDL_SECURITY_SIGLEN 512 488 489 #define GET_FWSECTION_HDR_DL_ADDR(fwhdr) \ 490 le32_get_bits(*((const __le32 *)(fwhdr)), GENMASK(31, 0)) 491 #define GET_FWSECTION_HDR_SECTIONTYPE(fwhdr) \ 492 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(27, 24)) 493 #define GET_FWSECTION_HDR_SEC_SIZE(fwhdr) \ 494 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 0)) 495 #define GET_FWSECTION_HDR_CHECKSUM(fwhdr) \ 496 le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(28)) 497 #define GET_FWSECTION_HDR_REDL(fwhdr) \ 498 le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(29)) 499 #define GET_FWSECTION_HDR_MSSC(fwhdr) \ 500 le32_get_bits(*((const __le32 *)(fwhdr) + 2), GENMASK(31, 0)) 501 502 #define GET_FW_HDR_MAJOR_VERSION(fwhdr) \ 503 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(7, 0)) 504 #define GET_FW_HDR_MINOR_VERSION(fwhdr) \ 505 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(15, 8)) 506 #define GET_FW_HDR_SUBVERSION(fwhdr) \ 507 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 16)) 508 #define GET_FW_HDR_SUBINDEX(fwhdr) \ 509 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(31, 24)) 510 #define GET_FW_HDR_LEN(fwhdr) \ 511 le32_get_bits(*((const __le32 *)(fwhdr) + 3), GENMASK(23, 16)) 512 #define GET_FW_HDR_MONTH(fwhdr) \ 513 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(7, 0)) 514 #define GET_FW_HDR_DATE(fwhdr) \ 515 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(15, 8)) 516 #define GET_FW_HDR_HOUR(fwhdr) \ 517 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(23, 16)) 518 #define GET_FW_HDR_MIN(fwhdr) \ 519 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(31, 24)) 520 #define GET_FW_HDR_YEAR(fwhdr) \ 521 le32_get_bits(*((const __le32 *)(fwhdr) + 5), GENMASK(31, 0)) 522 #define GET_FW_HDR_SEC_NUM(fwhdr) \ 523 le32_get_bits(*((const __le32 *)(fwhdr) + 6), GENMASK(15, 8)) 524 #define GET_FW_HDR_DYN_HDR(fwhdr) \ 525 le32_get_bits(*((const __le32 *)(fwhdr) + 7), BIT(16)) 526 #define GET_FW_HDR_CMD_VERSERION(fwhdr) \ 527 le32_get_bits(*((const __le32 *)(fwhdr) + 7), GENMASK(31, 24)) 528 529 #define GET_FW_DYNHDR_LEN(fwdynhdr) \ 530 le32_get_bits(*((const __le32 *)(fwdynhdr)), GENMASK(31, 0)) 531 #define GET_FW_DYNHDR_COUNT(fwdynhdr) \ 532 le32_get_bits(*((const __le32 *)(fwdynhdr) + 1), GENMASK(31, 0)) 533 534 static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val) 535 { 536 le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0)); 537 } 538 539 static inline void SET_CTRL_INFO_MACID(void *table, u32 val) 540 { 541 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)); 542 } 543 544 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val) 545 { 546 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); 547 } 548 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0) 549 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val) 550 { 551 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0)); 552 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE, 553 GENMASK(8, 0)); 554 } 555 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0) 556 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val) 557 { 558 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9)); 559 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP, 560 BIT(9)); 561 } 562 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0) 563 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val) 564 { 565 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10)); 566 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW, 567 GENMASK(11, 10)); 568 } 569 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0) 570 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val) 571 { 572 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12)); 573 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF, 574 GENMASK(14, 12)); 575 } 576 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0) 577 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val) 578 { 579 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); 580 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX, 581 BIT(15)); 582 } 583 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0) 584 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val) 585 { 586 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16)); 587 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL, 588 GENMASK(19, 16)); 589 } 590 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0) 591 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val) 592 { 593 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20)); 594 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN, 595 BIT(20)); 596 } 597 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0) 598 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val) 599 { 600 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21)); 601 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN, 602 BIT(21)); 603 } 604 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0) 605 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val) 606 { 607 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22)); 608 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN, 609 BIT(22)); 610 } 611 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0) 612 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val) 613 { 614 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23)); 615 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN, 616 BIT(23)); 617 } 618 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0) 619 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val) 620 { 621 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25)); 622 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB, 623 BIT(25)); 624 } 625 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0) 626 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val) 627 { 628 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26)); 629 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB, 630 BIT(26)); 631 } 632 #define SET_CMC_TBL_MASK_TRYRATE BIT(0) 633 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val) 634 { 635 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27)); 636 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE, 637 BIT(27)); 638 } 639 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0) 640 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val) 641 { 642 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28)); 643 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY, 644 GENMASK(31, 28)); 645 } 646 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0) 647 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val) 648 { 649 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0)); 650 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE, 651 GENMASK(8, 0)); 652 } 653 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0) 654 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val) 655 { 656 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9)); 657 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL, 658 BIT(9)); 659 } 660 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0) 661 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val) 662 { 663 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10)); 664 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL, 665 BIT(10)); 666 } 667 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0) 668 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val) 669 { 670 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11)); 671 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL, 672 BIT(11)); 673 } 674 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0) 675 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val) 676 { 677 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12)); 678 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT, 679 GENMASK(15, 12)); 680 } 681 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0) 682 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val) 683 { 684 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16)); 685 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE, 686 GENMASK(24, 16)); 687 } 688 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0) 689 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val) 690 { 691 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27)); 692 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC, 693 BIT(27)); 694 } 695 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0) 696 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val) 697 { 698 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28)); 699 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE, 700 GENMASK(31, 28)); 701 } 702 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0) 703 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val) 704 { 705 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0)); 706 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT, 707 GENMASK(5, 0)); 708 } 709 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0) 710 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val) 711 { 712 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6)); 713 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL, 714 BIT(6)); 715 } 716 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0) 717 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val) 718 { 719 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7)); 720 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL, 721 BIT(7)); 722 } 723 #define SET_CMC_TBL_MASK_RTS_EN BIT(0) 724 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val) 725 { 726 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8)); 727 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN, 728 BIT(8)); 729 } 730 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0) 731 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val) 732 { 733 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9)); 734 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN, 735 BIT(9)); 736 } 737 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0) 738 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val) 739 { 740 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10)); 741 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS, 742 GENMASK(11, 10)); 743 } 744 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0) 745 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val) 746 { 747 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12)); 748 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN, 749 BIT(12)); 750 } 751 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0) 752 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val) 753 { 754 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13)); 755 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE, 756 GENMASK(14, 13)); 757 } 758 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0) 759 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val) 760 { 761 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16)); 762 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN, 763 GENMASK(26, 16)); 764 } 765 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0) 766 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val) 767 { 768 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); 769 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS, 770 BIT(27)); 771 } 772 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0) 773 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val) 774 { 775 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28)); 776 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME, 777 GENMASK(31, 28)); 778 } 779 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0) 780 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val) 781 { 782 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0)); 783 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM, 784 GENMASK(7, 0)); 785 } 786 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0) 787 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val) 788 { 789 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8)); 790 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP, 791 GENMASK(9, 8)); 792 } 793 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0) 794 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val) 795 { 796 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16)); 797 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL, 798 GENMASK(18, 16)); 799 } 800 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0) 801 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val) 802 { 803 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19)); 804 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL, 805 GENMASK(21, 19)); 806 } 807 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0) 808 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val) 809 { 810 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22)); 811 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL, 812 GENMASK(24, 22)); 813 } 814 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0) 815 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val) 816 { 817 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25)); 818 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL, 819 GENMASK(27, 25)); 820 } 821 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0) 822 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val) 823 { 824 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28)); 825 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE, 826 GENMASK(31, 28)); 827 } 828 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0) 829 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val) 830 { 831 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0)); 832 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID, 833 GENMASK(2, 0)); 834 } 835 #define SET_CMC_TBL_MASK_BMC BIT(0) 836 static inline void SET_CMC_TBL_BMC(void *table, u32 val) 837 { 838 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3)); 839 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC, 840 BIT(3)); 841 } 842 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0) 843 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val) 844 { 845 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4)); 846 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID, 847 GENMASK(7, 4)); 848 } 849 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0) 850 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val) 851 { 852 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); 853 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR, 854 BIT(8)); 855 } 856 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0) 857 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val) 858 { 859 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9)); 860 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE, 861 GENMASK(11, 9)); 862 } 863 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0) 864 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val) 865 { 866 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12)); 867 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM, 868 BIT(12)); 869 } 870 #define SET_CMC_TBL_MASK_DATA_ER BIT(0) 871 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val) 872 { 873 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13)); 874 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER, 875 BIT(13)); 876 } 877 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0) 878 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val) 879 { 880 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14)); 881 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC, 882 BIT(14)); 883 } 884 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0) 885 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val) 886 { 887 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); 888 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC, 889 BIT(15)); 890 } 891 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0) 892 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val) 893 { 894 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16)); 895 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR, 896 BIT(16)); 897 } 898 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0) 899 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val) 900 { 901 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17)); 902 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH, 903 BIT(17)); 904 } 905 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0) 906 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val) 907 { 908 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18)); 909 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR, 910 BIT(18)); 911 } 912 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0) 913 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val) 914 { 915 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19)); 916 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS, 917 BIT(19)); 918 } 919 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0) 920 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val) 921 { 922 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20)); 923 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER, 924 BIT(20)); 925 } 926 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0) 927 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val) 928 { 929 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21)); 930 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN, 931 BIT(21)); 932 } 933 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0) 934 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val) 935 { 936 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27)); 937 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD, 938 BIT(27)); 939 } 940 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0) 941 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val) 942 { 943 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28)); 944 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT, 945 GENMASK(31, 28)); 946 } 947 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0) 948 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val) 949 { 950 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0)); 951 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE, 952 GENMASK(8, 0)); 953 } 954 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0) 955 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val) 956 { 957 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12)); 958 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT, 959 BIT(12)); 960 } 961 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0) 962 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val) 963 { 964 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13)); 965 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT, 966 BIT(13)); 967 } 968 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0) 969 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val) 970 { 971 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16)); 972 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN, 973 GENMASK(19, 16)); 974 } 975 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0) 976 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val) 977 { 978 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20)); 979 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A, 980 GENMASK(21, 20)); 981 } 982 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0) 983 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val) 984 { 985 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22)); 986 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B, 987 GENMASK(23, 22)); 988 } 989 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0) 990 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val) 991 { 992 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24)); 993 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C, 994 GENMASK(25, 24)); 995 } 996 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0) 997 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val) 998 { 999 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26)); 1000 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D, 1001 GENMASK(27, 26)); 1002 } 1003 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0) 1004 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val) 1005 { 1006 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28)); 1007 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A, 1008 BIT(28)); 1009 } 1010 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0) 1011 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val) 1012 { 1013 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29)); 1014 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B, 1015 BIT(29)); 1016 } 1017 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0) 1018 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val) 1019 { 1020 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30)); 1021 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C, 1022 BIT(30)); 1023 } 1024 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0) 1025 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val) 1026 { 1027 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31)); 1028 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D, 1029 BIT(31)); 1030 } 1031 1032 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0) 1033 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val) 1034 { 1035 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0)); 1036 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1037 GENMASK(1, 0)); 1038 } 1039 1040 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val) 1041 { 1042 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2)); 1043 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1044 GENMASK(3, 2)); 1045 } 1046 1047 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val) 1048 { 1049 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4)); 1050 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1051 GENMASK(5, 4)); 1052 } 1053 1054 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val) 1055 { 1056 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6)); 1057 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1058 GENMASK(7, 6)); 1059 } 1060 1061 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0) 1062 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val) 1063 { 1064 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); 1065 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX, 1066 GENMASK(7, 0)); 1067 } 1068 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0) 1069 static inline void SET_CMC_TBL_PAID(void *table, u32 val) 1070 { 1071 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8)); 1072 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID, 1073 GENMASK(16, 8)); 1074 } 1075 #define SET_CMC_TBL_MASK_ULDL BIT(0) 1076 static inline void SET_CMC_TBL_ULDL(void *table, u32 val) 1077 { 1078 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17)); 1079 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL, 1080 BIT(17)); 1081 } 1082 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0) 1083 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val) 1084 { 1085 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18)); 1086 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL, 1087 GENMASK(19, 18)); 1088 } 1089 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val) 1090 { 1091 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20)); 1092 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1093 GENMASK(21, 20)); 1094 } 1095 1096 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val) 1097 { 1098 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22)); 1099 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1100 GENMASK(23, 22)); 1101 } 1102 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0) 1103 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val) 1104 { 1105 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24)); 1106 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE, 1107 GENMASK(27, 24)); 1108 } 1109 1110 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val) 1111 { 1112 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30)); 1113 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1114 GENMASK(31, 30)); 1115 } 1116 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0) 1117 static inline void SET_CMC_TBL_NC(void *table, u32 val) 1118 { 1119 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0)); 1120 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC, 1121 GENMASK(2, 0)); 1122 } 1123 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0) 1124 static inline void SET_CMC_TBL_NR(void *table, u32 val) 1125 { 1126 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3)); 1127 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR, 1128 GENMASK(5, 3)); 1129 } 1130 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0) 1131 static inline void SET_CMC_TBL_NG(void *table, u32 val) 1132 { 1133 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6)); 1134 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG, 1135 GENMASK(7, 6)); 1136 } 1137 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0) 1138 static inline void SET_CMC_TBL_CB(void *table, u32 val) 1139 { 1140 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8)); 1141 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB, 1142 GENMASK(9, 8)); 1143 } 1144 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0) 1145 static inline void SET_CMC_TBL_CS(void *table, u32 val) 1146 { 1147 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10)); 1148 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS, 1149 GENMASK(11, 10)); 1150 } 1151 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0) 1152 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val) 1153 { 1154 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12)); 1155 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN, 1156 BIT(12)); 1157 } 1158 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0) 1159 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val) 1160 { 1161 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13)); 1162 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN, 1163 BIT(13)); 1164 } 1165 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0) 1166 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val) 1167 { 1168 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14)); 1169 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN, 1170 BIT(14)); 1171 } 1172 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0) 1173 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val) 1174 { 1175 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15)); 1176 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN, 1177 BIT(15)); 1178 } 1179 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0) 1180 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val) 1181 { 1182 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16)); 1183 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE, 1184 GENMASK(24, 16)); 1185 } 1186 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0) 1187 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val) 1188 { 1189 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25)); 1190 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF, 1191 GENMASK(27, 25)); 1192 } 1193 1194 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val) 1195 { 1196 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28)); 1197 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1198 GENMASK(29, 28)); 1199 } 1200 1201 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0) 1202 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val) 1203 { 1204 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30)); 1205 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW, 1206 GENMASK(31, 30)); 1207 } 1208 1209 static inline void SET_DCTL_MACID_V1(void *table, u32 val) 1210 { 1211 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)); 1212 } 1213 1214 static inline void SET_DCTL_OPERATION_V1(void *table, u32 val) 1215 { 1216 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); 1217 } 1218 1219 #define SET_DCTL_MASK_QOS_FIELD_V1 GENMASK(7, 0) 1220 static inline void SET_DCTL_QOS_FIELD_V1(void *table, u32 val) 1221 { 1222 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(7, 0)); 1223 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_FIELD_V1, 1224 GENMASK(7, 0)); 1225 } 1226 1227 #define SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID GENMASK(6, 0) 1228 static inline void SET_DCTL_HW_EXSEQ_MACID_V1(void *table, u32 val) 1229 { 1230 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 8)); 1231 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID, 1232 GENMASK(14, 8)); 1233 } 1234 1235 #define SET_DCTL_MASK_QOS_DATA BIT(0) 1236 static inline void SET_DCTL_QOS_DATA_V1(void *table, u32 val) 1237 { 1238 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); 1239 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_DATA, 1240 BIT(15)); 1241 } 1242 1243 #define SET_DCTL_MASK_AES_IV_L GENMASK(15, 0) 1244 static inline void SET_DCTL_AES_IV_L_V1(void *table, u32 val) 1245 { 1246 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 16)); 1247 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_AES_IV_L, 1248 GENMASK(31, 16)); 1249 } 1250 1251 #define SET_DCTL_MASK_AES_IV_H GENMASK(31, 0) 1252 static inline void SET_DCTL_AES_IV_H_V1(void *table, u32 val) 1253 { 1254 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 0)); 1255 le32p_replace_bits((__le32 *)(table) + 10, SET_DCTL_MASK_AES_IV_H, 1256 GENMASK(31, 0)); 1257 } 1258 1259 #define SET_DCTL_MASK_SEQ0 GENMASK(11, 0) 1260 static inline void SET_DCTL_SEQ0_V1(void *table, u32 val) 1261 { 1262 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 0)); 1263 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ0, 1264 GENMASK(11, 0)); 1265 } 1266 1267 #define SET_DCTL_MASK_SEQ1 GENMASK(11, 0) 1268 static inline void SET_DCTL_SEQ1_V1(void *table, u32 val) 1269 { 1270 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(23, 12)); 1271 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ1, 1272 GENMASK(23, 12)); 1273 } 1274 1275 #define SET_DCTL_MASK_AMSDU_MAX_LEN GENMASK(2, 0) 1276 static inline void SET_DCTL_AMSDU_MAX_LEN_V1(void *table, u32 val) 1277 { 1278 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 24)); 1279 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_AMSDU_MAX_LEN, 1280 GENMASK(26, 24)); 1281 } 1282 1283 #define SET_DCTL_MASK_STA_AMSDU_EN BIT(0) 1284 static inline void SET_DCTL_STA_AMSDU_EN_V1(void *table, u32 val) 1285 { 1286 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); 1287 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_STA_AMSDU_EN, 1288 BIT(27)); 1289 } 1290 1291 #define SET_DCTL_MASK_CHKSUM_OFLD_EN BIT(0) 1292 static inline void SET_DCTL_CHKSUM_OFLD_EN_V1(void *table, u32 val) 1293 { 1294 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(28)); 1295 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_CHKSUM_OFLD_EN, 1296 BIT(28)); 1297 } 1298 1299 #define SET_DCTL_MASK_WITH_LLC BIT(0) 1300 static inline void SET_DCTL_WITH_LLC_V1(void *table, u32 val) 1301 { 1302 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(29)); 1303 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_WITH_LLC, 1304 BIT(29)); 1305 } 1306 1307 #define SET_DCTL_MASK_SEQ2 GENMASK(11, 0) 1308 static inline void SET_DCTL_SEQ2_V1(void *table, u32 val) 1309 { 1310 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(11, 0)); 1311 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ2, 1312 GENMASK(11, 0)); 1313 } 1314 1315 #define SET_DCTL_MASK_SEQ3 GENMASK(11, 0) 1316 static inline void SET_DCTL_SEQ3_V1(void *table, u32 val) 1317 { 1318 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(23, 12)); 1319 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ3, 1320 GENMASK(23, 12)); 1321 } 1322 1323 #define SET_DCTL_MASK_TGT_IND GENMASK(3, 0) 1324 static inline void SET_DCTL_TGT_IND_V1(void *table, u32 val) 1325 { 1326 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 24)); 1327 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND, 1328 GENMASK(27, 24)); 1329 } 1330 1331 #define SET_DCTL_MASK_TGT_IND_EN BIT(0) 1332 static inline void SET_DCTL_TGT_IND_EN_V1(void *table, u32 val) 1333 { 1334 le32p_replace_bits((__le32 *)(table) + 4, val, BIT(28)); 1335 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND_EN, 1336 BIT(28)); 1337 } 1338 1339 #define SET_DCTL_MASK_HTC_LB GENMASK(2, 0) 1340 static inline void SET_DCTL_HTC_LB_V1(void *table, u32 val) 1341 { 1342 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 29)); 1343 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_HTC_LB, 1344 GENMASK(31, 29)); 1345 } 1346 1347 #define SET_DCTL_MASK_MHDR_LEN GENMASK(4, 0) 1348 static inline void SET_DCTL_MHDR_LEN_V1(void *table, u32 val) 1349 { 1350 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(4, 0)); 1351 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_MHDR_LEN, 1352 GENMASK(4, 0)); 1353 } 1354 1355 #define SET_DCTL_MASK_VLAN_TAG_VALID BIT(0) 1356 static inline void SET_DCTL_VLAN_TAG_VALID_V1(void *table, u32 val) 1357 { 1358 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(5)); 1359 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_VALID, 1360 BIT(5)); 1361 } 1362 1363 #define SET_DCTL_MASK_VLAN_TAG_SEL GENMASK(1, 0) 1364 static inline void SET_DCTL_VLAN_TAG_SEL_V1(void *table, u32 val) 1365 { 1366 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 6)); 1367 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_SEL, 1368 GENMASK(7, 6)); 1369 } 1370 1371 #define SET_DCTL_MASK_HTC_ORDER BIT(0) 1372 static inline void SET_DCTL_HTC_ORDER_V1(void *table, u32 val) 1373 { 1374 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); 1375 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_HTC_ORDER, 1376 BIT(8)); 1377 } 1378 1379 #define SET_DCTL_MASK_SEC_KEY_ID GENMASK(1, 0) 1380 static inline void SET_DCTL_SEC_KEY_ID_V1(void *table, u32 val) 1381 { 1382 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(10, 9)); 1383 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_KEY_ID, 1384 GENMASK(10, 9)); 1385 } 1386 1387 #define SET_DCTL_MASK_WAPI BIT(0) 1388 static inline void SET_DCTL_WAPI_V1(void *table, u32 val) 1389 { 1390 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); 1391 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_WAPI, 1392 BIT(15)); 1393 } 1394 1395 #define SET_DCTL_MASK_SEC_ENT_MODE GENMASK(1, 0) 1396 static inline void SET_DCTL_SEC_ENT_MODE_V1(void *table, u32 val) 1397 { 1398 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(17, 16)); 1399 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENT_MODE, 1400 GENMASK(17, 16)); 1401 } 1402 1403 #define SET_DCTL_MASK_SEC_ENTX_KEYID GENMASK(1, 0) 1404 static inline void SET_DCTL_SEC_ENT0_KEYID_V1(void *table, u32 val) 1405 { 1406 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(19, 18)); 1407 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1408 GENMASK(19, 18)); 1409 } 1410 1411 static inline void SET_DCTL_SEC_ENT1_KEYID_V1(void *table, u32 val) 1412 { 1413 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(21, 20)); 1414 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1415 GENMASK(21, 20)); 1416 } 1417 1418 static inline void SET_DCTL_SEC_ENT2_KEYID_V1(void *table, u32 val) 1419 { 1420 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(23, 22)); 1421 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1422 GENMASK(23, 22)); 1423 } 1424 1425 static inline void SET_DCTL_SEC_ENT3_KEYID_V1(void *table, u32 val) 1426 { 1427 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(25, 24)); 1428 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1429 GENMASK(25, 24)); 1430 } 1431 1432 static inline void SET_DCTL_SEC_ENT4_KEYID_V1(void *table, u32 val) 1433 { 1434 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(27, 26)); 1435 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1436 GENMASK(27, 26)); 1437 } 1438 1439 static inline void SET_DCTL_SEC_ENT5_KEYID_V1(void *table, u32 val) 1440 { 1441 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(29, 28)); 1442 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1443 GENMASK(29, 28)); 1444 } 1445 1446 static inline void SET_DCTL_SEC_ENT6_KEYID_V1(void *table, u32 val) 1447 { 1448 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 30)); 1449 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1450 GENMASK(31, 30)); 1451 } 1452 1453 #define SET_DCTL_MASK_SEC_ENT_VALID GENMASK(7, 0) 1454 static inline void SET_DCTL_SEC_ENT_VALID_V1(void *table, u32 val) 1455 { 1456 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(7, 0)); 1457 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENT_VALID, 1458 GENMASK(7, 0)); 1459 } 1460 1461 #define SET_DCTL_MASK_SEC_ENTX GENMASK(7, 0) 1462 static inline void SET_DCTL_SEC_ENT0_V1(void *table, u32 val) 1463 { 1464 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(15, 8)); 1465 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1466 GENMASK(15, 8)); 1467 } 1468 1469 static inline void SET_DCTL_SEC_ENT1_V1(void *table, u32 val) 1470 { 1471 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 16)); 1472 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1473 GENMASK(23, 16)); 1474 } 1475 1476 static inline void SET_DCTL_SEC_ENT2_V1(void *table, u32 val) 1477 { 1478 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(31, 24)); 1479 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1480 GENMASK(31, 24)); 1481 } 1482 1483 static inline void SET_DCTL_SEC_ENT3_V1(void *table, u32 val) 1484 { 1485 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); 1486 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1487 GENMASK(7, 0)); 1488 } 1489 1490 static inline void SET_DCTL_SEC_ENT4_V1(void *table, u32 val) 1491 { 1492 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(15, 8)); 1493 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1494 GENMASK(15, 8)); 1495 } 1496 1497 static inline void SET_DCTL_SEC_ENT5_V1(void *table, u32 val) 1498 { 1499 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 16)); 1500 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1501 GENMASK(23, 16)); 1502 } 1503 1504 static inline void SET_DCTL_SEC_ENT6_V1(void *table, u32 val) 1505 { 1506 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 24)); 1507 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1508 GENMASK(31, 24)); 1509 } 1510 1511 static inline void SET_BCN_UPD_PORT(void *h2c, u32 val) 1512 { 1513 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1514 } 1515 1516 static inline void SET_BCN_UPD_MBSSID(void *h2c, u32 val) 1517 { 1518 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1519 } 1520 1521 static inline void SET_BCN_UPD_BAND(void *h2c, u32 val) 1522 { 1523 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1524 } 1525 1526 static inline void SET_BCN_UPD_GRP_IE_OFST(void *h2c, u32 val) 1527 { 1528 le32p_replace_bits((__le32 *)h2c, (val - 24) | BIT(7), GENMASK(31, 24)); 1529 } 1530 1531 static inline void SET_BCN_UPD_MACID(void *h2c, u32 val) 1532 { 1533 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1534 } 1535 1536 static inline void SET_BCN_UPD_SSN_SEL(void *h2c, u32 val) 1537 { 1538 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(9, 8)); 1539 } 1540 1541 static inline void SET_BCN_UPD_SSN_MODE(void *h2c, u32 val) 1542 { 1543 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(11, 10)); 1544 } 1545 1546 static inline void SET_BCN_UPD_RATE(void *h2c, u32 val) 1547 { 1548 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(20, 12)); 1549 } 1550 1551 static inline void SET_BCN_UPD_TXPWR(void *h2c, u32 val) 1552 { 1553 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(23, 21)); 1554 } 1555 1556 static inline void SET_BCN_UPD_TXINFO_CTRL_EN(void *h2c, u32 val) 1557 { 1558 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(0)); 1559 } 1560 1561 static inline void SET_BCN_UPD_NTX_PATH_EN(void *h2c, u32 val) 1562 { 1563 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(4, 1)); 1564 } 1565 1566 static inline void SET_BCN_UPD_PATH_MAP_A(void *h2c, u32 val) 1567 { 1568 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(6, 5)); 1569 } 1570 1571 static inline void SET_BCN_UPD_PATH_MAP_B(void *h2c, u32 val) 1572 { 1573 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(8, 7)); 1574 } 1575 1576 static inline void SET_BCN_UPD_PATH_MAP_C(void *h2c, u32 val) 1577 { 1578 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(10, 9)); 1579 } 1580 1581 static inline void SET_BCN_UPD_PATH_MAP_D(void *h2c, u32 val) 1582 { 1583 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(12, 11)); 1584 } 1585 1586 static inline void SET_BCN_UPD_PATH_ANTSEL_A(void *h2c, u32 val) 1587 { 1588 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(13)); 1589 } 1590 1591 static inline void SET_BCN_UPD_PATH_ANTSEL_B(void *h2c, u32 val) 1592 { 1593 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(14)); 1594 } 1595 1596 static inline void SET_BCN_UPD_PATH_ANTSEL_C(void *h2c, u32 val) 1597 { 1598 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(15)); 1599 } 1600 1601 static inline void SET_BCN_UPD_PATH_ANTSEL_D(void *h2c, u32 val) 1602 { 1603 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(16)); 1604 } 1605 1606 static inline void SET_BCN_UPD_CSA_OFST(void *h2c, u32 val) 1607 { 1608 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 17)); 1609 } 1610 1611 static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val) 1612 { 1613 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1614 } 1615 1616 static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val) 1617 { 1618 le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8)); 1619 } 1620 1621 static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val) 1622 { 1623 le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10)); 1624 } 1625 1626 static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val) 1627 { 1628 le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13)); 1629 } 1630 1631 static inline void SET_JOININFO_MACID(void *h2c, u32 val) 1632 { 1633 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1634 } 1635 1636 static inline void SET_JOININFO_OP(void *h2c, u32 val) 1637 { 1638 le32p_replace_bits((__le32 *)h2c, val, BIT(8)); 1639 } 1640 1641 static inline void SET_JOININFO_BAND(void *h2c, u32 val) 1642 { 1643 le32p_replace_bits((__le32 *)h2c, val, BIT(9)); 1644 } 1645 1646 static inline void SET_JOININFO_WMM(void *h2c, u32 val) 1647 { 1648 le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10)); 1649 } 1650 1651 static inline void SET_JOININFO_TGR(void *h2c, u32 val) 1652 { 1653 le32p_replace_bits((__le32 *)h2c, val, BIT(12)); 1654 } 1655 1656 static inline void SET_JOININFO_ISHESTA(void *h2c, u32 val) 1657 { 1658 le32p_replace_bits((__le32 *)h2c, val, BIT(13)); 1659 } 1660 1661 static inline void SET_JOININFO_DLBW(void *h2c, u32 val) 1662 { 1663 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14)); 1664 } 1665 1666 static inline void SET_JOININFO_TF_MAC_PAD(void *h2c, u32 val) 1667 { 1668 le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16)); 1669 } 1670 1671 static inline void SET_JOININFO_DL_T_PE(void *h2c, u32 val) 1672 { 1673 le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18)); 1674 } 1675 1676 static inline void SET_JOININFO_PORT_ID(void *h2c, u32 val) 1677 { 1678 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21)); 1679 } 1680 1681 static inline void SET_JOININFO_NET_TYPE(void *h2c, u32 val) 1682 { 1683 le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24)); 1684 } 1685 1686 static inline void SET_JOININFO_WIFI_ROLE(void *h2c, u32 val) 1687 { 1688 le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26)); 1689 } 1690 1691 static inline void SET_JOININFO_SELF_ROLE(void *h2c, u32 val) 1692 { 1693 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30)); 1694 } 1695 1696 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val) 1697 { 1698 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1699 } 1700 1701 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val) 1702 { 1703 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1704 } 1705 1706 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val) 1707 { 1708 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1709 } 1710 1711 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val) 1712 { 1713 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1714 } 1715 1716 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val) 1717 { 1718 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1719 } 1720 1721 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val) 1722 { 1723 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); 1724 } 1725 1726 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val) 1727 { 1728 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1729 } 1730 1731 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val) 1732 { 1733 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1734 } 1735 1736 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val) 1737 { 1738 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)); 1739 } 1740 1741 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val) 1742 { 1743 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0)); 1744 } 1745 1746 static inline void SET_BA_CAM_VALID(void *h2c, u32 val) 1747 { 1748 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 1749 } 1750 1751 static inline void SET_BA_CAM_INIT_REQ(void *h2c, u32 val) 1752 { 1753 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 1754 } 1755 1756 static inline void SET_BA_CAM_ENTRY_IDX(void *h2c, u32 val) 1757 { 1758 le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2)); 1759 } 1760 1761 static inline void SET_BA_CAM_TID(void *h2c, u32 val) 1762 { 1763 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4)); 1764 } 1765 1766 static inline void SET_BA_CAM_MACID(void *h2c, u32 val) 1767 { 1768 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1769 } 1770 1771 static inline void SET_BA_CAM_BMAP_SIZE(void *h2c, u32 val) 1772 { 1773 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); 1774 } 1775 1776 static inline void SET_BA_CAM_SSN(void *h2c, u32 val) 1777 { 1778 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20)); 1779 } 1780 1781 static inline void SET_BA_CAM_UID(void *h2c, u32 val) 1782 { 1783 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(7, 0)); 1784 } 1785 1786 static inline void SET_BA_CAM_STD_EN(void *h2c, u32 val) 1787 { 1788 le32p_replace_bits((__le32 *)h2c + 1, val, BIT(8)); 1789 } 1790 1791 static inline void SET_BA_CAM_BAND(void *h2c, u32 val) 1792 { 1793 le32p_replace_bits((__le32 *)h2c + 1, val, BIT(9)); 1794 } 1795 1796 static inline void SET_BA_CAM_ENTRY_IDX_V1(void *h2c, u32 val) 1797 { 1798 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 28)); 1799 } 1800 1801 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val) 1802 { 1803 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1804 } 1805 1806 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val) 1807 { 1808 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1809 } 1810 1811 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val) 1812 { 1813 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); 1814 } 1815 1816 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val) 1817 { 1818 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20)); 1819 } 1820 1821 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val) 1822 { 1823 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1824 } 1825 1826 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val) 1827 { 1828 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0)); 1829 } 1830 1831 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val) 1832 { 1833 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1)); 1834 } 1835 1836 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val) 1837 { 1838 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2)); 1839 } 1840 1841 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val) 1842 { 1843 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3)); 1844 } 1845 1846 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val) 1847 { 1848 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); 1849 } 1850 1851 static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val) 1852 { 1853 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0)); 1854 } 1855 1856 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val) 1857 { 1858 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 1859 } 1860 1861 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val) 1862 { 1863 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 1864 } 1865 1866 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val) 1867 { 1868 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 1869 } 1870 1871 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val) 1872 { 1873 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 1874 } 1875 1876 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val) 1877 { 1878 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0)); 1879 } 1880 1881 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val) 1882 { 1883 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8)); 1884 } 1885 1886 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val) 1887 { 1888 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 1889 } 1890 1891 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val) 1892 { 1893 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0)); 1894 } 1895 1896 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val) 1897 { 1898 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0)); 1899 } 1900 1901 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val) 1902 { 1903 le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0)); 1904 } 1905 1906 static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val) 1907 { 1908 le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0)); 1909 } 1910 1911 static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val) 1912 { 1913 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1914 } 1915 1916 static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val) 1917 { 1918 le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16)); 1919 } 1920 1921 static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val) 1922 { 1923 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1924 } 1925 1926 static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val) 1927 { 1928 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 1929 } 1930 1931 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val) 1932 { 1933 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 1934 } 1935 1936 static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val) 1937 { 1938 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); 1939 } 1940 1941 static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val) 1942 { 1943 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1944 } 1945 1946 static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val) 1947 { 1948 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1949 } 1950 1951 static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val) 1952 { 1953 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1954 } 1955 1956 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val) 1957 { 1958 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1959 } 1960 1961 static inline void RTW89_SET_WOW_GLOBAL_ENABLE(void *h2c, u32 val) 1962 { 1963 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 1964 } 1965 1966 static inline void RTW89_SET_WOW_GLOBAL_DROP_ALL_PKT(void *h2c, u32 val) 1967 { 1968 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 1969 } 1970 1971 static inline void RTW89_SET_WOW_GLOBAL_RX_PARSE_AFTER_WAKE(void *h2c, u32 val) 1972 { 1973 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); 1974 } 1975 1976 static inline void RTW89_SET_WOW_GLOBAL_WAKE_BAR_PULLED(void *h2c, u32 val) 1977 { 1978 le32p_replace_bits((__le32 *)h2c, val, BIT(3)); 1979 } 1980 1981 static inline void RTW89_SET_WOW_GLOBAL_MAC_ID(void *h2c, u32 val) 1982 { 1983 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1984 } 1985 1986 static inline void RTW89_SET_WOW_GLOBAL_PAIRWISE_SEC_ALGO(void *h2c, u32 val) 1987 { 1988 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1989 } 1990 1991 static inline void RTW89_SET_WOW_GLOBAL_GROUP_SEC_ALGO(void *h2c, u32 val) 1992 { 1993 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1994 } 1995 1996 static inline void RTW89_SET_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT(void *h2c, u32 val) 1997 { 1998 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)); 1999 } 2000 2001 static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val) 2002 { 2003 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 2004 } 2005 2006 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val) 2007 { 2008 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 2009 } 2010 2011 static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val) 2012 { 2013 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); 2014 } 2015 2016 static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val) 2017 { 2018 le32p_replace_bits((__le32 *)h2c, val, BIT(3)); 2019 } 2020 2021 static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val) 2022 { 2023 le32p_replace_bits((__le32 *)h2c, val, BIT(4)); 2024 } 2025 2026 static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val) 2027 { 2028 le32p_replace_bits((__le32 *)h2c, val, BIT(5)); 2029 } 2030 2031 static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val) 2032 { 2033 le32p_replace_bits((__le32 *)h2c, val, BIT(6)); 2034 } 2035 2036 static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val) 2037 { 2038 le32p_replace_bits((__le32 *)h2c, val, BIT(7)); 2039 } 2040 2041 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val) 2042 { 2043 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 2044 } 2045 2046 static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val) 2047 { 2048 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 2049 } 2050 2051 static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val) 2052 { 2053 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1)); 2054 } 2055 2056 static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val) 2057 { 2058 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0)); 2059 } 2060 2061 static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val) 2062 { 2063 le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0)); 2064 } 2065 2066 static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val) 2067 { 2068 le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0)); 2069 } 2070 2071 static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val) 2072 { 2073 le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0)); 2074 } 2075 2076 static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val) 2077 { 2078 le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0)); 2079 } 2080 2081 static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val) 2082 { 2083 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22)); 2084 } 2085 2086 static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val) 2087 { 2088 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23)); 2089 } 2090 2091 static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val) 2092 { 2093 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24)); 2094 } 2095 2096 static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val) 2097 { 2098 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25)); 2099 } 2100 2101 static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val) 2102 { 2103 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26)); 2104 } 2105 2106 static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val) 2107 { 2108 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31)); 2109 } 2110 2111 enum rtw89_btc_btf_h2c_class { 2112 BTFC_SET = 0x10, 2113 BTFC_GET = 0x11, 2114 BTFC_FW_EVENT = 0x12, 2115 }; 2116 2117 enum rtw89_btc_btf_set { 2118 SET_REPORT_EN = 0x0, 2119 SET_SLOT_TABLE, 2120 SET_MREG_TABLE, 2121 SET_CX_POLICY, 2122 SET_GPIO_DBG, 2123 SET_DRV_INFO, 2124 SET_DRV_EVENT, 2125 SET_BT_WREG_ADDR, 2126 SET_BT_WREG_VAL, 2127 SET_BT_RREG_ADDR, 2128 SET_BT_WL_CH_INFO, 2129 SET_BT_INFO_REPORT, 2130 SET_BT_IGNORE_WLAN_ACT, 2131 SET_BT_TX_PWR, 2132 SET_BT_LNA_CONSTRAIN, 2133 SET_BT_GOLDEN_RX_RANGE, 2134 SET_BT_PSD_REPORT, 2135 SET_H2C_TEST, 2136 SET_MAX1, 2137 }; 2138 2139 enum rtw89_btc_cxdrvinfo { 2140 CXDRVINFO_INIT = 0, 2141 CXDRVINFO_ROLE, 2142 CXDRVINFO_DBCC, 2143 CXDRVINFO_SMAP, 2144 CXDRVINFO_RFK, 2145 CXDRVINFO_RUN, 2146 CXDRVINFO_CTRL, 2147 CXDRVINFO_SCAN, 2148 CXDRVINFO_MAX, 2149 }; 2150 2151 enum rtw89_scan_mode { 2152 RTW89_SCAN_IMMEDIATE, 2153 }; 2154 2155 enum rtw89_scan_type { 2156 RTW89_SCAN_ONCE, 2157 }; 2158 2159 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val) 2160 { 2161 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0)); 2162 } 2163 2164 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val) 2165 { 2166 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0)); 2167 } 2168 2169 static inline void RTW89_SET_FWCMD_CXINIT_ANT_TYPE(void *cmd, u8 val) 2170 { 2171 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)); 2172 } 2173 2174 static inline void RTW89_SET_FWCMD_CXINIT_ANT_NUM(void *cmd, u8 val) 2175 { 2176 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)); 2177 } 2178 2179 static inline void RTW89_SET_FWCMD_CXINIT_ANT_ISO(void *cmd, u8 val) 2180 { 2181 u8p_replace_bits((u8 *)(cmd) + 4, val, GENMASK(7, 0)); 2182 } 2183 2184 static inline void RTW89_SET_FWCMD_CXINIT_ANT_POS(void *cmd, u8 val) 2185 { 2186 u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(0)); 2187 } 2188 2189 static inline void RTW89_SET_FWCMD_CXINIT_ANT_DIVERSITY(void *cmd, u8 val) 2190 { 2191 u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(1)); 2192 } 2193 2194 static inline void RTW89_SET_FWCMD_CXINIT_MOD_RFE(void *cmd, u8 val) 2195 { 2196 u8p_replace_bits((u8 *)(cmd) + 6, val, GENMASK(7, 0)); 2197 } 2198 2199 static inline void RTW89_SET_FWCMD_CXINIT_MOD_CV(void *cmd, u8 val) 2200 { 2201 u8p_replace_bits((u8 *)(cmd) + 7, val, GENMASK(7, 0)); 2202 } 2203 2204 static inline void RTW89_SET_FWCMD_CXINIT_MOD_BT_SOLO(void *cmd, u8 val) 2205 { 2206 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(0)); 2207 } 2208 2209 static inline void RTW89_SET_FWCMD_CXINIT_MOD_BT_POS(void *cmd, u8 val) 2210 { 2211 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(1)); 2212 } 2213 2214 static inline void RTW89_SET_FWCMD_CXINIT_MOD_SW_TYPE(void *cmd, u8 val) 2215 { 2216 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(2)); 2217 } 2218 2219 static inline void RTW89_SET_FWCMD_CXINIT_WL_GCH(void *cmd, u8 val) 2220 { 2221 u8p_replace_bits((u8 *)(cmd) + 10, val, GENMASK(7, 0)); 2222 } 2223 2224 static inline void RTW89_SET_FWCMD_CXINIT_WL_ONLY(void *cmd, u8 val) 2225 { 2226 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(0)); 2227 } 2228 2229 static inline void RTW89_SET_FWCMD_CXINIT_WL_INITOK(void *cmd, u8 val) 2230 { 2231 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(1)); 2232 } 2233 2234 static inline void RTW89_SET_FWCMD_CXINIT_DBCC_EN(void *cmd, u8 val) 2235 { 2236 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(2)); 2237 } 2238 2239 static inline void RTW89_SET_FWCMD_CXINIT_CX_OTHER(void *cmd, u8 val) 2240 { 2241 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(3)); 2242 } 2243 2244 static inline void RTW89_SET_FWCMD_CXINIT_BT_ONLY(void *cmd, u8 val) 2245 { 2246 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(4)); 2247 } 2248 2249 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val) 2250 { 2251 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)); 2252 } 2253 2254 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val) 2255 { 2256 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)); 2257 } 2258 2259 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val) 2260 { 2261 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0)); 2262 } 2263 2264 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val) 2265 { 2266 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1)); 2267 } 2268 2269 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val) 2270 { 2271 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2)); 2272 } 2273 2274 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val) 2275 { 2276 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3)); 2277 } 2278 2279 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val) 2280 { 2281 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4)); 2282 } 2283 2284 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val) 2285 { 2286 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5)); 2287 } 2288 2289 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val) 2290 { 2291 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6)); 2292 } 2293 2294 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val) 2295 { 2296 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7)); 2297 } 2298 2299 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val) 2300 { 2301 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8)); 2302 } 2303 2304 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val) 2305 { 2306 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9)); 2307 } 2308 2309 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val) 2310 { 2311 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10)); 2312 } 2313 2314 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val) 2315 { 2316 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11)); 2317 } 2318 2319 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset) 2320 { 2321 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0)); 2322 } 2323 2324 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset) 2325 { 2326 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1)); 2327 } 2328 2329 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset) 2330 { 2331 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4)); 2332 } 2333 2334 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset) 2335 { 2336 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5)); 2337 } 2338 2339 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset) 2340 { 2341 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6)); 2342 } 2343 2344 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset) 2345 { 2346 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0)); 2347 } 2348 2349 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset) 2350 { 2351 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1)); 2352 } 2353 2354 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset) 2355 { 2356 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0)); 2357 } 2358 2359 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset) 2360 { 2361 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0)); 2362 } 2363 2364 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset) 2365 { 2366 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0)); 2367 } 2368 2369 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset) 2370 { 2371 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0)); 2372 } 2373 2374 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset) 2375 { 2376 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0)); 2377 } 2378 2379 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset) 2380 { 2381 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0)); 2382 } 2383 2384 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset) 2385 { 2386 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0)); 2387 } 2388 2389 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset) 2390 { 2391 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0)); 2392 } 2393 2394 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset) 2395 { 2396 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0)); 2397 } 2398 2399 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset) 2400 { 2401 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0)); 2402 } 2403 2404 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset) 2405 { 2406 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1)); 2407 } 2408 2409 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset) 2410 { 2411 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2)); 2412 } 2413 2414 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset) 2415 { 2416 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4)); 2417 } 2418 2419 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val) 2420 { 2421 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0)); 2422 } 2423 2424 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val) 2425 { 2426 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1)); 2427 } 2428 2429 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val) 2430 { 2431 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2)); 2432 } 2433 2434 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val) 2435 { 2436 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3)); 2437 } 2438 2439 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val) 2440 { 2441 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0)); 2442 } 2443 2444 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val) 2445 { 2446 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2)); 2447 } 2448 2449 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val) 2450 { 2451 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6)); 2452 } 2453 2454 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val) 2455 { 2456 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8)); 2457 } 2458 2459 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val) 2460 { 2461 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10)); 2462 } 2463 2464 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val) 2465 { 2466 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2467 } 2468 2469 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val) 2470 { 2471 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8)); 2472 } 2473 2474 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val) 2475 { 2476 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16)); 2477 } 2478 2479 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_NUM(void *cmd, u32 val) 2480 { 2481 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2482 } 2483 2484 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_SIZE(void *cmd, u32 val) 2485 { 2486 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8)); 2487 } 2488 2489 static inline void RTW89_SET_FWCMD_CHINFO_PERIOD(void *cmd, u32 val) 2490 { 2491 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2492 } 2493 2494 static inline void RTW89_SET_FWCMD_CHINFO_DWELL(void *cmd, u32 val) 2495 { 2496 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8)); 2497 } 2498 2499 static inline void RTW89_SET_FWCMD_CHINFO_CENTER_CH(void *cmd, u32 val) 2500 { 2501 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 16)); 2502 } 2503 2504 static inline void RTW89_SET_FWCMD_CHINFO_PRI_CH(void *cmd, u32 val) 2505 { 2506 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 24)); 2507 } 2508 2509 static inline void RTW89_SET_FWCMD_CHINFO_BW(void *cmd, u32 val) 2510 { 2511 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(2, 0)); 2512 } 2513 2514 static inline void RTW89_SET_FWCMD_CHINFO_ACTION(void *cmd, u32 val) 2515 { 2516 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 3)); 2517 } 2518 2519 static inline void RTW89_SET_FWCMD_CHINFO_NUM_PKT(void *cmd, u32 val) 2520 { 2521 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(11, 8)); 2522 } 2523 2524 static inline void RTW89_SET_FWCMD_CHINFO_TX(void *cmd, u32 val) 2525 { 2526 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(12)); 2527 } 2528 2529 static inline void RTW89_SET_FWCMD_CHINFO_PAUSE_DATA(void *cmd, u32 val) 2530 { 2531 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(13)); 2532 } 2533 2534 static inline void RTW89_SET_FWCMD_CHINFO_BAND(void *cmd, u32 val) 2535 { 2536 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 14)); 2537 } 2538 2539 static inline void RTW89_SET_FWCMD_CHINFO_PKT_ID(void *cmd, u32 val) 2540 { 2541 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16)); 2542 } 2543 2544 static inline void RTW89_SET_FWCMD_CHINFO_DFS(void *cmd, u32 val) 2545 { 2546 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(24)); 2547 } 2548 2549 static inline void RTW89_SET_FWCMD_CHINFO_TX_NULL(void *cmd, u32 val) 2550 { 2551 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(25)); 2552 } 2553 2554 static inline void RTW89_SET_FWCMD_CHINFO_RANDOM(void *cmd, u32 val) 2555 { 2556 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(26)); 2557 } 2558 2559 static inline void RTW89_SET_FWCMD_CHINFO_CFG_TX(void *cmd, u32 val) 2560 { 2561 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(27)); 2562 } 2563 2564 static inline void RTW89_SET_FWCMD_CHINFO_PKT0(void *cmd, u32 val) 2565 { 2566 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(7, 0)); 2567 } 2568 2569 static inline void RTW89_SET_FWCMD_CHINFO_PKT1(void *cmd, u32 val) 2570 { 2571 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 8)); 2572 } 2573 2574 static inline void RTW89_SET_FWCMD_CHINFO_PKT2(void *cmd, u32 val) 2575 { 2576 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16)); 2577 } 2578 2579 static inline void RTW89_SET_FWCMD_CHINFO_PKT3(void *cmd, u32 val) 2580 { 2581 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(31, 24)); 2582 } 2583 2584 static inline void RTW89_SET_FWCMD_CHINFO_PKT4(void *cmd, u32 val) 2585 { 2586 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(7, 0)); 2587 } 2588 2589 static inline void RTW89_SET_FWCMD_CHINFO_PKT5(void *cmd, u32 val) 2590 { 2591 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(15, 8)); 2592 } 2593 2594 static inline void RTW89_SET_FWCMD_CHINFO_PKT6(void *cmd, u32 val) 2595 { 2596 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(23, 16)); 2597 } 2598 2599 static inline void RTW89_SET_FWCMD_CHINFO_PKT7(void *cmd, u32 val) 2600 { 2601 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 24)); 2602 } 2603 2604 static inline void RTW89_SET_FWCMD_CHINFO_POWER_IDX(void *cmd, u32 val) 2605 { 2606 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(15, 0)); 2607 } 2608 2609 static inline void RTW89_SET_FWCMD_SCANOFLD_MACID(void *cmd, u32 val) 2610 { 2611 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2612 } 2613 2614 static inline void RTW89_SET_FWCMD_SCANOFLD_NORM_CY(void *cmd, u32 val) 2615 { 2616 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8)); 2617 } 2618 2619 static inline void RTW89_SET_FWCMD_SCANOFLD_PORT_ID(void *cmd, u32 val) 2620 { 2621 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(18, 16)); 2622 } 2623 2624 static inline void RTW89_SET_FWCMD_SCANOFLD_BAND(void *cmd, u32 val) 2625 { 2626 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, BIT(19)); 2627 } 2628 2629 static inline void RTW89_SET_FWCMD_SCANOFLD_OPERATION(void *cmd, u32 val) 2630 { 2631 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(21, 20)); 2632 } 2633 2634 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_BAND(void *cmd, u32 val) 2635 { 2636 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 22)); 2637 } 2638 2639 static inline void RTW89_SET_FWCMD_SCANOFLD_NOTIFY_END(void *cmd, u32 val) 2640 { 2641 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(0)); 2642 } 2643 2644 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_MODE(void *cmd, u32 val) 2645 { 2646 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(1)); 2647 } 2648 2649 static inline void RTW89_SET_FWCMD_SCANOFLD_START_MODE(void *cmd, u32 val) 2650 { 2651 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(2)); 2652 } 2653 2654 static inline void RTW89_SET_FWCMD_SCANOFLD_SCAN_TYPE(void *cmd, u32 val) 2655 { 2656 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(4, 3)); 2657 } 2658 2659 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_BW(void *cmd, u32 val) 2660 { 2661 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 5)); 2662 } 2663 2664 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_PRI_CH(void *cmd, u32 val) 2665 { 2666 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 8)); 2667 } 2668 2669 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CENTRAL_CH(void *cmd, 2670 u32 val) 2671 { 2672 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16)); 2673 } 2674 2675 static inline void RTW89_SET_FWCMD_SCANOFLD_PROBE_REQ_PKT_ID(void *cmd, u32 val) 2676 { 2677 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(31, 24)); 2678 } 2679 2680 static inline void RTW89_SET_FWCMD_SCANOFLD_NORM_PD(void *cmd, u32 val) 2681 { 2682 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 0)); 2683 } 2684 2685 static inline void RTW89_SET_FWCMD_SCANOFLD_SLOW_PD(void *cmd, u32 val) 2686 { 2687 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16)); 2688 } 2689 2690 static inline void RTW89_SET_FWCMD_SCANOFLD_TSF_HIGH(void *cmd, u32 val) 2691 { 2692 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 0)); 2693 } 2694 2695 static inline void RTW89_SET_FWCMD_SCANOFLD_TSF_SLOW(void *cmd, u32 val) 2696 { 2697 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(31, 0)); 2698 } 2699 2700 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val) 2701 { 2702 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 2703 } 2704 2705 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val) 2706 { 2707 le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8)); 2708 } 2709 2710 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val) 2711 { 2712 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12)); 2713 } 2714 2715 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val) 2716 { 2717 le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16)); 2718 } 2719 2720 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val) 2721 { 2722 le32p_replace_bits((__le32 *)cmd, val, BIT(20)); 2723 } 2724 2725 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val) 2726 { 2727 le32p_replace_bits((__le32 *)cmd, val, BIT(21)); 2728 } 2729 2730 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val) 2731 { 2732 *((__le32 *)cmd + 1) = val; 2733 } 2734 2735 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val) 2736 { 2737 *((__le32 *)cmd + 2) = val; 2738 } 2739 2740 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val) 2741 { 2742 *((__le32 *)cmd + 3) = val; 2743 } 2744 2745 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val) 2746 { 2747 le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0)); 2748 } 2749 2750 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val) 2751 { 2752 u8 ctwnd; 2753 2754 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT)) 2755 return; 2756 ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val); 2757 le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8)); 2758 } 2759 2760 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val) 2761 { 2762 le32p_replace_bits((__le32 *)cmd, val, BIT(0)); 2763 } 2764 2765 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val) 2766 { 2767 le32p_replace_bits((__le32 *)cmd, val, BIT(1)); 2768 } 2769 2770 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val) 2771 { 2772 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2)); 2773 } 2774 2775 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val) 2776 { 2777 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16)); 2778 } 2779 2780 enum rtw89_fw_mcc_c2h_rpt_cfg { 2781 RTW89_FW_MCC_C2H_RPT_OFF = 0, 2782 RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1, 2783 RTW89_FW_MCC_C2H_RPT_ALL = 2, 2784 }; 2785 2786 struct rtw89_fw_mcc_add_req { 2787 u8 macid; 2788 u8 central_ch_seg0; 2789 u8 central_ch_seg1; 2790 u8 primary_ch; 2791 enum rtw89_bandwidth bandwidth: 4; 2792 u32 group: 2; 2793 u32 c2h_rpt: 2; 2794 u32 dis_tx_null: 1; 2795 u32 dis_sw_retry: 1; 2796 u32 in_curr_ch: 1; 2797 u32 sw_retry_count: 3; 2798 u32 tx_null_early: 4; 2799 u32 btc_in_2g: 1; 2800 u32 pta_en: 1; 2801 u32 rfk_by_pass: 1; 2802 u32 ch_band_type: 2; 2803 u32 rsvd0: 9; 2804 u32 duration; 2805 u8 courtesy_en; 2806 u8 courtesy_num; 2807 u8 courtesy_target; 2808 u8 rsvd1; 2809 }; 2810 2811 static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val) 2812 { 2813 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 2814 } 2815 2816 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val) 2817 { 2818 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 2819 } 2820 2821 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val) 2822 { 2823 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 2824 } 2825 2826 static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val) 2827 { 2828 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 2829 } 2830 2831 static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val) 2832 { 2833 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0)); 2834 } 2835 2836 static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val) 2837 { 2838 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4)); 2839 } 2840 2841 static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val) 2842 { 2843 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6)); 2844 } 2845 2846 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val) 2847 { 2848 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8)); 2849 } 2850 2851 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val) 2852 { 2853 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9)); 2854 } 2855 2856 static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val) 2857 { 2858 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10)); 2859 } 2860 2861 static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val) 2862 { 2863 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11)); 2864 } 2865 2866 static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val) 2867 { 2868 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14)); 2869 } 2870 2871 static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val) 2872 { 2873 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18)); 2874 } 2875 2876 static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val) 2877 { 2878 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19)); 2879 } 2880 2881 static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val) 2882 { 2883 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20)); 2884 } 2885 2886 static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val) 2887 { 2888 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21)); 2889 } 2890 2891 static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val) 2892 { 2893 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 2894 } 2895 2896 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val) 2897 { 2898 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0)); 2899 } 2900 2901 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val) 2902 { 2903 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8)); 2904 } 2905 2906 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val) 2907 { 2908 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16)); 2909 } 2910 2911 struct rtw89_fw_mcc_start_req { 2912 u32 group: 2; 2913 u32 btc_in_group: 1; 2914 u32 old_group_action: 2; 2915 u32 old_group: 2; 2916 u32 rsvd0: 9; 2917 u32 notify_cnt: 3; 2918 u32 rsvd1: 2; 2919 u32 notify_rxdbg_en: 1; 2920 u32 rsvd2: 2; 2921 u32 macid: 8; 2922 u32 tsf_low; 2923 u32 tsf_high; 2924 }; 2925 2926 static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val) 2927 { 2928 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 2929 } 2930 2931 static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val) 2932 { 2933 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 2934 } 2935 2936 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val) 2937 { 2938 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3)); 2939 } 2940 2941 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val) 2942 { 2943 le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5)); 2944 } 2945 2946 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val) 2947 { 2948 le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16)); 2949 } 2950 2951 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val) 2952 { 2953 le32p_replace_bits((__le32 *)cmd, val, BIT(21)); 2954 } 2955 2956 static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val) 2957 { 2958 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 2959 } 2960 2961 static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val) 2962 { 2963 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0)); 2964 } 2965 2966 static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val) 2967 { 2968 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 2969 } 2970 2971 static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val) 2972 { 2973 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 2974 } 2975 2976 static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val) 2977 { 2978 le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8)); 2979 } 2980 2981 static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val) 2982 { 2983 le32p_replace_bits((__le32 *)cmd, val, BIT(10)); 2984 } 2985 2986 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val) 2987 { 2988 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 2989 } 2990 2991 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val) 2992 { 2993 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 2994 } 2995 2996 static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val) 2997 { 2998 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 2999 } 3000 3001 struct rtw89_fw_mcc_tsf_req { 3002 u8 group: 2; 3003 u8 rsvd0: 6; 3004 u8 macid_x; 3005 u8 macid_y; 3006 u8 rsvd1; 3007 }; 3008 3009 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val) 3010 { 3011 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3012 } 3013 3014 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val) 3015 { 3016 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3017 } 3018 3019 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val) 3020 { 3021 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3022 } 3023 3024 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val) 3025 { 3026 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3027 } 3028 3029 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val) 3030 { 3031 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3032 } 3033 3034 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val) 3035 { 3036 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3037 } 3038 3039 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd, 3040 u8 *bitmap, u8 len) 3041 { 3042 memcpy((__le32 *)cmd + 1, bitmap, len); 3043 } 3044 3045 static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val) 3046 { 3047 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3048 } 3049 3050 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val) 3051 { 3052 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3053 } 3054 3055 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val) 3056 { 3057 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3058 } 3059 3060 static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val) 3061 { 3062 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 3063 } 3064 3065 struct rtw89_fw_mcc_duration { 3066 u32 group: 2; 3067 u32 btc_in_group: 1; 3068 u32 rsvd0: 5; 3069 u32 start_macid: 8; 3070 u32 macid_x: 8; 3071 u32 macid_y: 8; 3072 u32 start_tsf_low; 3073 u32 start_tsf_high; 3074 u32 duration_x; 3075 u32 duration_y; 3076 }; 3077 3078 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val) 3079 { 3080 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3081 } 3082 3083 static 3084 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val) 3085 { 3086 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 3087 } 3088 3089 static 3090 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val) 3091 { 3092 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3093 } 3094 3095 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val) 3096 { 3097 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3098 } 3099 3100 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val) 3101 { 3102 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 3103 } 3104 3105 static 3106 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val) 3107 { 3108 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0)); 3109 } 3110 3111 static 3112 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val) 3113 { 3114 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 3115 } 3116 3117 static 3118 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val) 3119 { 3120 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0)); 3121 } 3122 3123 static 3124 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val) 3125 { 3126 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0)); 3127 } 3128 3129 #define RTW89_C2H_HEADER_LEN 8 3130 3131 #define RTW89_GET_C2H_CATEGORY(c2h) \ 3132 le32_get_bits(*((const __le32 *)c2h), GENMASK(1, 0)) 3133 #define RTW89_GET_C2H_CLASS(c2h) \ 3134 le32_get_bits(*((const __le32 *)c2h), GENMASK(7, 2)) 3135 #define RTW89_GET_C2H_FUNC(c2h) \ 3136 le32_get_bits(*((const __le32 *)c2h), GENMASK(15, 8)) 3137 #define RTW89_GET_C2H_LEN(c2h) \ 3138 le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(13, 0)) 3139 3140 struct rtw89_fw_c2h_attr { 3141 u8 category; 3142 u8 class; 3143 u8 func; 3144 u16 len; 3145 }; 3146 3147 static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb) 3148 { 3149 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr)); 3150 3151 return (struct rtw89_fw_c2h_attr *)skb->cb; 3152 } 3153 3154 #define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2) 3155 #define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN) 3156 3157 #define RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h) \ 3158 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3159 #define RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h) \ 3160 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 3161 #define RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h) \ 3162 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3163 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h) \ 3164 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 3165 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h) \ 3166 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24)) 3167 3168 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \ 3169 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3170 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \ 3171 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 3172 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \ 3173 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3174 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \ 3175 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 3176 3177 #define RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h) \ 3178 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 0)) 3179 #define RTW89_GET_PHY_C2H_RA_RPT_RETRY_RATIO(c2h) \ 3180 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 3181 #define RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h) \ 3182 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(6, 0)) 3183 #define RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h) \ 3184 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(9, 8)) 3185 #define RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h) \ 3186 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(12, 10)) 3187 #define RTW89_GET_PHY_C2H_RA_RPT_BW(c2h) \ 3188 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(14, 13)) 3189 3190 /* VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS 3191 * HT-new: [6:5]: NA, [4:0]: MCS 3192 */ 3193 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4) 3194 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0) 3195 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0) 3196 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \ 3197 FIELD_PREP(GENMASK(2, 0), mcs)) 3198 3199 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \ 3200 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 3201 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \ 3202 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8)) 3203 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \ 3204 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16)) 3205 3206 #define RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h) \ 3207 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 3208 #define RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h) \ 3209 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(19, 16)) 3210 #define RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h) \ 3211 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 20)) 3212 #define RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h) \ 3213 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24)) 3214 #define RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h) \ 3215 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(3, 0)) 3216 #define RTW89_GET_MAC_C2H_SCANOFLD_AIR_DENSITY(c2h) \ 3217 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(7, 4)) 3218 #define RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h) \ 3219 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(25, 24)) 3220 3221 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \ 3222 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3223 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \ 3224 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3225 3226 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \ 3227 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3228 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \ 3229 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 3230 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \ 3231 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3232 3233 struct rtw89_mac_mcc_tsf_rpt { 3234 u32 macid_x; 3235 u32 macid_y; 3236 u32 tsf_x_low; 3237 u32 tsf_x_high; 3238 u32 tsf_y_low; 3239 u32 tsf_y_high; 3240 }; 3241 3242 static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE); 3243 3244 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \ 3245 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 3246 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \ 3247 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3248 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \ 3249 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16)) 3250 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \ 3251 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0)) 3252 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \ 3253 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0)) 3254 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \ 3255 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0)) 3256 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \ 3257 le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0)) 3258 3259 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \ 3260 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0)) 3261 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \ 3262 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6)) 3263 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \ 3264 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3265 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \ 3266 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0)) 3267 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \ 3268 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0)) 3269 3270 #define RTW89_FW_HDR_SIZE 32 3271 #define RTW89_FW_SECTION_HDR_SIZE 16 3272 3273 #define RTW89_MFW_SIG 0xFF 3274 3275 struct rtw89_mfw_info { 3276 u8 cv; 3277 u8 type; /* enum rtw89_fw_type */ 3278 u8 mp; 3279 u8 rsvd; 3280 __le32 shift; 3281 __le32 size; 3282 u8 rsvd2[4]; 3283 } __packed; 3284 3285 struct rtw89_mfw_hdr { 3286 u8 sig; /* RTW89_MFW_SIG */ 3287 u8 fw_nr; 3288 u8 rsvd0[2]; 3289 struct { 3290 u8 major; 3291 u8 minor; 3292 u8 sub; 3293 u8 idx; 3294 } ver; 3295 u8 rsvd1[8]; 3296 struct rtw89_mfw_info info[]; 3297 } __packed; 3298 3299 struct fwcmd_hdr { 3300 __le32 hdr0; 3301 __le32 hdr1; 3302 }; 3303 3304 union rtw89_compat_fw_hdr { 3305 struct rtw89_mfw_hdr mfw_hdr; 3306 u8 fw_hdr[RTW89_FW_HDR_SIZE]; 3307 }; 3308 3309 static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf) 3310 { 3311 const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf; 3312 3313 if (compat->mfw_hdr.sig == RTW89_MFW_SIG) 3314 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr); 3315 else 3316 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr); 3317 } 3318 3319 #define RTW89_H2C_RF_PAGE_SIZE 500 3320 #define RTW89_H2C_RF_PAGE_NUM 3 3321 struct rtw89_fw_h2c_rf_reg_info { 3322 enum rtw89_rf_path rf_path; 3323 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE]; 3324 u16 curr_idx; 3325 }; 3326 3327 #define H2C_SEC_CAM_LEN 24 3328 3329 #define H2C_HEADER_LEN 8 3330 #define H2C_HDR_CAT GENMASK(1, 0) 3331 #define H2C_HDR_CLASS GENMASK(7, 2) 3332 #define H2C_HDR_FUNC GENMASK(15, 8) 3333 #define H2C_HDR_DEL_TYPE GENMASK(19, 16) 3334 #define H2C_HDR_H2C_SEQ GENMASK(31, 24) 3335 #define H2C_HDR_TOTAL_LEN GENMASK(13, 0) 3336 #define H2C_HDR_REC_ACK BIT(14) 3337 #define H2C_HDR_DONE_ACK BIT(15) 3338 3339 #define FWCMD_TYPE_H2C 0 3340 3341 #define H2C_CAT_TEST 0x0 3342 3343 /* CLASS 5 - FW STATUS TEST */ 3344 #define H2C_CL_FW_STATUS_TEST 0x5 3345 #define H2C_FUNC_CPU_EXCEPTION 0x1 3346 3347 #define H2C_CAT_MAC 0x1 3348 3349 /* CLASS 0 - FW INFO */ 3350 #define H2C_CL_FW_INFO 0x0 3351 #define H2C_FUNC_LOG_CFG 0x0 3352 #define H2C_FUNC_MAC_GENERAL_PKT 0x1 3353 3354 /* CLASS 1 - WOW */ 3355 #define H2C_CL_MAC_WOW 0x1 3356 #define H2C_FUNC_KEEP_ALIVE 0x0 3357 #define H2C_FUNC_DISCONNECT_DETECT 0x1 3358 #define H2C_FUNC_WOW_GLOBAL 0x2 3359 #define H2C_FUNC_WAKEUP_CTRL 0x8 3360 #define H2C_FUNC_WOW_CAM_UPD 0xC 3361 3362 /* CLASS 2 - PS */ 3363 #define H2C_CL_MAC_PS 0x2 3364 #define H2C_FUNC_MAC_LPS_PARM 0x0 3365 #define H2C_FUNC_P2P_ACT 0x1 3366 3367 /* CLASS 3 - FW download */ 3368 #define H2C_CL_MAC_FWDL 0x3 3369 #define H2C_FUNC_MAC_FWHDR_DL 0x0 3370 3371 /* CLASS 5 - Frame Exchange */ 3372 #define H2C_CL_MAC_FR_EXCHG 0x5 3373 #define H2C_FUNC_MAC_CCTLINFO_UD 0x2 3374 #define H2C_FUNC_MAC_BCN_UPD 0x5 3375 #define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9 3376 #define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa 3377 3378 /* CLASS 6 - Address CAM */ 3379 #define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6 3380 #define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0 3381 3382 /* CLASS 8 - Media Status Report */ 3383 #define H2C_CL_MAC_MEDIA_RPT 0x8 3384 #define H2C_FUNC_MAC_JOININFO 0x0 3385 #define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4 3386 3387 /* CLASS 9 - FW offload */ 3388 #define H2C_CL_MAC_FW_OFLD 0x9 3389 #define H2C_FUNC_PACKET_OFLD 0x1 3390 #define H2C_FUNC_MAC_MACID_PAUSE 0x8 3391 #define H2C_FUNC_USR_EDCA 0xF 3392 #define H2C_FUNC_TSF32_TOGL 0x10 3393 #define H2C_FUNC_OFLD_CFG 0x14 3394 #define H2C_FUNC_ADD_SCANOFLD_CH 0x16 3395 #define H2C_FUNC_SCANOFLD 0x17 3396 #define H2C_FUNC_PKT_DROP 0x1b 3397 3398 /* CLASS 10 - Security CAM */ 3399 #define H2C_CL_MAC_SEC_CAM 0xa 3400 #define H2C_FUNC_MAC_SEC_UPD 0x1 3401 3402 /* CLASS 12 - BA CAM */ 3403 #define H2C_CL_BA_CAM 0xc 3404 #define H2C_FUNC_MAC_BA_CAM 0x0 3405 3406 /* CLASS 14 - MCC */ 3407 #define H2C_CL_MCC 0xe 3408 enum rtw89_mcc_h2c_func { 3409 H2C_FUNC_ADD_MCC = 0x0, 3410 H2C_FUNC_START_MCC = 0x1, 3411 H2C_FUNC_STOP_MCC = 0x2, 3412 H2C_FUNC_DEL_MCC_GROUP = 0x3, 3413 H2C_FUNC_RESET_MCC_GROUP = 0x4, 3414 H2C_FUNC_MCC_REQ_TSF = 0x5, 3415 H2C_FUNC_MCC_MACID_BITMAP = 0x6, 3416 H2C_FUNC_MCC_SYNC = 0x7, 3417 H2C_FUNC_MCC_SET_DURATION = 0x8, 3418 3419 NUM_OF_RTW89_MCC_H2C_FUNC, 3420 }; 3421 3422 #define RTW89_MCC_WAIT_COND(group, func) \ 3423 ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func)) 3424 3425 #define H2C_CAT_OUTSRC 0x2 3426 3427 #define H2C_CL_OUTSRC_RA 0x1 3428 #define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0 3429 3430 #define H2C_CL_OUTSRC_RF_REG_A 0x8 3431 #define H2C_CL_OUTSRC_RF_REG_B 0x9 3432 #define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa 3433 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2 3434 3435 struct rtw89_fw_h2c_rf_get_mccch { 3436 __le32 ch_0; 3437 __le32 ch_1; 3438 __le32 band_0; 3439 __le32 band_1; 3440 __le32 current_channel; 3441 __le32 current_band_type; 3442 } __packed; 3443 3444 #define RTW89_FW_RSVD_PLE_SIZE 0x800 3445 3446 #define RTW89_WCPU_BASE_MASK GENMASK(27, 0) 3447 3448 #define RTW89_FW_BACKTRACE_INFO_SIZE 8 3449 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \ 3450 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0) 3451 3452 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */ 3453 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE 3454 3455 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev); 3456 int rtw89_fw_recognize(struct rtw89_dev *rtwdev); 3457 const struct firmware * 3458 rtw89_early_fw_feature_recognize(struct device *device, 3459 const struct rtw89_chip_info *chip, 3460 u32 *early_feat_map); 3461 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type); 3462 int rtw89_load_firmware(struct rtw89_dev *rtwdev); 3463 void rtw89_unload_firmware(struct rtw89_dev *rtwdev); 3464 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev); 3465 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb, 3466 u8 type, u8 cat, u8 class, u8 func, 3467 bool rack, bool dack, u32 len); 3468 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, 3469 struct rtw89_vif *rtwvif); 3470 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, 3471 struct ieee80211_vif *vif, 3472 struct ieee80211_sta *sta); 3473 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev, 3474 struct rtw89_sta *rtwsta); 3475 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev, 3476 struct rtw89_sta *rtwsta); 3477 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev, 3478 struct rtw89_vif *rtwvif); 3479 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif, 3480 struct rtw89_sta *rtwsta, const u8 *scan_mac_addr); 3481 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev, 3482 struct rtw89_vif *rtwvif, 3483 struct rtw89_sta *rtwsta); 3484 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h); 3485 void rtw89_fw_c2h_work(struct work_struct *work); 3486 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev, 3487 struct rtw89_vif *rtwvif, 3488 struct rtw89_sta *rtwsta, 3489 enum rtw89_upd_mode upd_mode); 3490 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3491 struct rtw89_sta *rtwsta, bool dis_conn); 3492 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp, 3493 bool pause); 3494 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3495 u8 ac, u32 val); 3496 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev); 3497 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi); 3498 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev); 3499 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev); 3500 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev); 3501 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev); 3502 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev); 3503 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id); 3504 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id, 3505 struct sk_buff *skb_ofld); 3506 int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int len, 3507 struct list_head *chan_list); 3508 int rtw89_fw_h2c_scan_offload(struct rtw89_dev *rtwdev, 3509 struct rtw89_scan_option *opt, 3510 struct rtw89_vif *vif); 3511 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev, 3512 struct rtw89_fw_h2c_rf_reg_info *info, 3513 u16 len, u8 page); 3514 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev); 3515 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, 3516 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, 3517 bool rack, bool dack); 3518 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len); 3519 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev); 3520 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev); 3521 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3522 u8 macid); 3523 void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev, 3524 struct rtw89_vif *rtwvif, bool notify_fw); 3525 void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw); 3526 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 3527 bool valid, struct ieee80211_ampdu_params *params); 3528 void rtw89_fw_h2c_init_ba_cam_v1(struct rtw89_dev *rtwdev); 3529 3530 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev, 3531 struct rtw89_lps_parm *lps_param); 3532 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len); 3533 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len); 3534 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev, 3535 struct rtw89_mac_h2c_info *h2c_info, 3536 struct rtw89_mac_c2h_info *c2h_info); 3537 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable); 3538 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev); 3539 void rtw89_store_op_chan(struct rtw89_dev *rtwdev, bool backup); 3540 void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3541 struct ieee80211_scan_request *req); 3542 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3543 bool aborted); 3544 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3545 bool enable); 3546 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 3547 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev); 3548 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev, 3549 const struct rtw89_pkt_drop_params *params); 3550 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3551 struct ieee80211_p2p_noa_desc *desc, 3552 u8 act, u8 noa_id); 3553 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3554 bool en); 3555 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3556 bool enable); 3557 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev, 3558 struct rtw89_vif *rtwvif, bool enable); 3559 int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3560 bool enable); 3561 int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev, 3562 struct rtw89_vif *rtwvif, bool enable); 3563 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3564 bool enable); 3565 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev, 3566 struct rtw89_vif *rtwvif, bool enable); 3567 int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev, 3568 struct rtw89_wow_cam_info *cam_info); 3569 int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev, 3570 const struct rtw89_fw_mcc_add_req *p); 3571 int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev, 3572 const struct rtw89_fw_mcc_start_req *p); 3573 int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid, 3574 bool prev_groups); 3575 int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group, 3576 bool prev_groups); 3577 int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group); 3578 int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev, 3579 const struct rtw89_fw_mcc_tsf_req *req, 3580 struct rtw89_mac_mcc_tsf_rpt *rpt); 3581 int rtw89_fw_h2c_mcc_macid_bitamp(struct rtw89_dev *rtwdev, u8 group, u8 macid, 3582 u8 *bitmap); 3583 int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source, 3584 u8 target, u8 offset); 3585 int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev, 3586 const struct rtw89_fw_mcc_duration *p); 3587 3588 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev) 3589 { 3590 const struct rtw89_chip_info *chip = rtwdev->chip; 3591 3592 if (chip->bacam_v1) 3593 rtw89_fw_h2c_init_ba_cam_v1(rtwdev); 3594 } 3595 3596 #endif 3597