1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_FW_H__ 6 #define __RTW89_FW_H__ 7 8 #include "core.h" 9 10 enum rtw89_fw_dl_status { 11 RTW89_FWDL_INITIAL_STATE = 0, 12 RTW89_FWDL_FWDL_ONGOING = 1, 13 RTW89_FWDL_CHECKSUM_FAIL = 2, 14 RTW89_FWDL_SECURITY_FAIL = 3, 15 RTW89_FWDL_CV_NOT_MATCH = 4, 16 RTW89_FWDL_RSVD0 = 5, 17 RTW89_FWDL_WCPU_FWDL_RDY = 6, 18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7 19 }; 20 21 #define RTW89_GET_C2H_HDR_FUNC(info) \ 22 u32_get_bits(info, GENMASK(6, 0)) 23 #define RTW89_GET_C2H_HDR_LEN(info) \ 24 u32_get_bits(info, GENMASK(11, 8)) 25 26 #define RTW89_SET_H2CREG_HDR_FUNC(info, val) \ 27 u32p_replace_bits(info, val, GENMASK(6, 0)) 28 #define RTW89_SET_H2CREG_HDR_LEN(info, val) \ 29 u32p_replace_bits(info, val, GENMASK(11, 8)) 30 31 #define RTW89_H2CREG_MAX 4 32 #define RTW89_C2HREG_MAX 4 33 #define RTW89_C2HREG_HDR_LEN 2 34 #define RTW89_H2CREG_HDR_LEN 2 35 #define RTW89_C2H_TIMEOUT 1000000 36 struct rtw89_mac_c2h_info { 37 u8 id; 38 u8 content_len; 39 u32 c2hreg[RTW89_C2HREG_MAX]; 40 }; 41 42 struct rtw89_mac_h2c_info { 43 u8 id; 44 u8 content_len; 45 u32 h2creg[RTW89_H2CREG_MAX]; 46 }; 47 48 enum rtw89_mac_h2c_type { 49 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0, 50 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD, 51 RTW89_FWCMD_H2CREG_FUNC_FWERR, 52 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE, 53 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM, 54 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN 55 }; 56 57 enum rtw89_mac_c2h_type { 58 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0, 59 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT, 60 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG, 61 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP, 62 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT, 63 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF 64 }; 65 66 struct rtw89_c2h_phy_cap { 67 u32 func:7; 68 u32 ack:1; 69 u32 len:4; 70 u32 seq:4; 71 u32 rx_nss:8; 72 u32 bw:8; 73 74 u32 tx_nss:8; 75 u32 prot:8; 76 u32 nic:8; 77 u32 wl_func:8; 78 79 u32 hw_type:8; 80 } __packed; 81 82 enum rtw89_fw_c2h_category { 83 RTW89_C2H_CAT_TEST, 84 RTW89_C2H_CAT_MAC, 85 RTW89_C2H_CAT_OUTSRC, 86 }; 87 88 enum rtw89_fw_log_level { 89 RTW89_FW_LOG_LEVEL_OFF, 90 RTW89_FW_LOG_LEVEL_CRT, 91 RTW89_FW_LOG_LEVEL_SER, 92 RTW89_FW_LOG_LEVEL_WARN, 93 RTW89_FW_LOG_LEVEL_LOUD, 94 RTW89_FW_LOG_LEVEL_TR, 95 }; 96 97 enum rtw89_fw_log_path { 98 RTW89_FW_LOG_LEVEL_UART, 99 RTW89_FW_LOG_LEVEL_C2H, 100 RTW89_FW_LOG_LEVEL_SNI, 101 }; 102 103 enum rtw89_fw_log_comp { 104 RTW89_FW_LOG_COMP_VER, 105 RTW89_FW_LOG_COMP_INIT, 106 RTW89_FW_LOG_COMP_TASK, 107 RTW89_FW_LOG_COMP_CNS, 108 RTW89_FW_LOG_COMP_H2C, 109 RTW89_FW_LOG_COMP_C2H, 110 RTW89_FW_LOG_COMP_TX, 111 RTW89_FW_LOG_COMP_RX, 112 RTW89_FW_LOG_COMP_IPSEC, 113 RTW89_FW_LOG_COMP_TIMER, 114 RTW89_FW_LOG_COMP_DBGPKT, 115 RTW89_FW_LOG_COMP_PS, 116 RTW89_FW_LOG_COMP_ERROR, 117 RTW89_FW_LOG_COMP_WOWLAN, 118 RTW89_FW_LOG_COMP_SECURE_BOOT, 119 RTW89_FW_LOG_COMP_BTC, 120 RTW89_FW_LOG_COMP_BB, 121 RTW89_FW_LOG_COMP_TWT, 122 RTW89_FW_LOG_COMP_RF, 123 RTW89_FW_LOG_COMP_MCC = 20, 124 }; 125 126 #define FWDL_SECTION_MAX_NUM 10 127 #define FWDL_SECTION_CHKSUM_LEN 8 128 #define FWDL_SECTION_PER_PKT_LEN 2020 129 130 struct rtw89_fw_hdr_section_info { 131 u8 redl; 132 const u8 *addr; 133 u32 len; 134 u32 dladdr; 135 }; 136 137 struct rtw89_fw_bin_info { 138 u8 section_num; 139 u32 hdr_len; 140 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM]; 141 }; 142 143 struct rtw89_fw_macid_pause_grp { 144 __le32 pause_grp[4]; 145 __le32 mask_grp[4]; 146 } __packed; 147 148 struct rtw89_h2creg_sch_tx_en { 149 u8 func:7; 150 u8 ack:1; 151 u8 total_len:4; 152 u8 seq_num:4; 153 u16 tx_en:16; 154 u16 mask:16; 155 u8 band:1; 156 u16 rsvd:15; 157 } __packed; 158 159 #define RTW89_SET_FWCMD_RA_IS_DIS(cmd, val) \ 160 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(0)) 161 #define RTW89_SET_FWCMD_RA_MODE(cmd, val) \ 162 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(5, 1)) 163 #define RTW89_SET_FWCMD_RA_BW_CAP(cmd, val) \ 164 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 6)) 165 #define RTW89_SET_FWCMD_RA_MACID(cmd, val) \ 166 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)) 167 #define RTW89_SET_FWCMD_RA_DCM(cmd, val) \ 168 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(16)) 169 #define RTW89_SET_FWCMD_RA_ER(cmd, val) \ 170 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(17)) 171 #define RTW89_SET_FWCMD_RA_INIT_RATE_LV(cmd, val) \ 172 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(19, 18)) 173 #define RTW89_SET_FWCMD_RA_UPD_ALL(cmd, val) \ 174 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(20)) 175 #define RTW89_SET_FWCMD_RA_SGI(cmd, val) \ 176 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(21)) 177 #define RTW89_SET_FWCMD_RA_LDPC(cmd, val) \ 178 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(22)) 179 #define RTW89_SET_FWCMD_RA_STBC(cmd, val) \ 180 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(23)) 181 #define RTW89_SET_FWCMD_RA_SS_NUM(cmd, val) \ 182 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(26, 24)) 183 #define RTW89_SET_FWCMD_RA_GILTF(cmd, val) \ 184 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(29, 27)) 185 #define RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(cmd, val) \ 186 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(30)) 187 #define RTW89_SET_FWCMD_RA_UPD_MASK(cmd, val) \ 188 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(31)) 189 #define RTW89_SET_FWCMD_RA_MASK_0(cmd, val) \ 190 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(7, 0)) 191 #define RTW89_SET_FWCMD_RA_MASK_1(cmd, val) \ 192 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(15, 8)) 193 #define RTW89_SET_FWCMD_RA_MASK_2(cmd, val) \ 194 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(23, 16)) 195 #define RTW89_SET_FWCMD_RA_MASK_3(cmd, val) \ 196 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 24)) 197 #define RTW89_SET_FWCMD_RA_MASK_4(cmd, val) \ 198 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(7, 0)) 199 #define RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(cmd, val) \ 200 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, BIT(31)) 201 #define RTW89_SET_FWCMD_RA_BAND_NUM(cmd, val) \ 202 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(7, 0)) 203 #define RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(cmd, val) \ 204 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(8)) 205 #define RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(cmd, val) \ 206 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(9)) 207 #define RTW89_SET_FWCMD_RA_CR_TBL_SEL(cmd, val) \ 208 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(10)) 209 #define RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(cmd, val) \ 210 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(23, 16)) 211 #define RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(cmd, val) \ 212 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(25, 24)) 213 #define RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(cmd, val) \ 214 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(28, 26)) 215 #define RTW89_SET_FWCMD_RA_FIXED_CSI_BW(cmd, val) \ 216 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 29)) 217 218 #define RTW89_SET_FWCMD_SEC_IDX(cmd, val) \ 219 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)) 220 #define RTW89_SET_FWCMD_SEC_OFFSET(cmd, val) \ 221 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)) 222 #define RTW89_SET_FWCMD_SEC_LEN(cmd, val) \ 223 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)) 224 #define RTW89_SET_FWCMD_SEC_TYPE(cmd, val) \ 225 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0)) 226 #define RTW89_SET_FWCMD_SEC_EXT_KEY(cmd, val) \ 227 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4)) 228 #define RTW89_SET_FWCMD_SEC_SPP_MODE(cmd, val) \ 229 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5)) 230 #define RTW89_SET_FWCMD_SEC_KEY0(cmd, val) \ 231 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0)) 232 #define RTW89_SET_FWCMD_SEC_KEY1(cmd, val) \ 233 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0)) 234 #define RTW89_SET_FWCMD_SEC_KEY2(cmd, val) \ 235 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0)) 236 #define RTW89_SET_FWCMD_SEC_KEY3(cmd, val) \ 237 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0)) 238 239 #define RTW89_SET_EDCA_SEL(cmd, val) \ 240 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0)) 241 #define RTW89_SET_EDCA_BAND(cmd, val) \ 242 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3)) 243 #define RTW89_SET_EDCA_WMM(cmd, val) \ 244 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4)) 245 #define RTW89_SET_EDCA_AC(cmd, val) \ 246 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5)) 247 #define RTW89_SET_EDCA_PARAM(cmd, val) \ 248 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0)) 249 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16) 250 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12) 251 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8) 252 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0) 253 254 #define GET_FWSECTION_HDR_SEC_SIZE(fwhdr) \ 255 le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(23, 0)) 256 #define GET_FWSECTION_HDR_CHECKSUM(fwhdr) \ 257 le32_get_bits(*((__le32 *)(fwhdr) + 1), BIT(28)) 258 #define GET_FWSECTION_HDR_REDL(fwhdr) \ 259 le32_get_bits(*((__le32 *)(fwhdr) + 1), BIT(29)) 260 #define GET_FWSECTION_HDR_DL_ADDR(fwhdr) \ 261 le32_get_bits(*((__le32 *)(fwhdr)), GENMASK(31, 0)) 262 263 #define GET_FW_HDR_MAJOR_VERSION(fwhdr) \ 264 le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(7, 0)) 265 #define GET_FW_HDR_MINOR_VERSION(fwhdr) \ 266 le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(15, 8)) 267 #define GET_FW_HDR_SUBVERSION(fwhdr) \ 268 le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(23, 16)) 269 #define GET_FW_HDR_SUBINDEX(fwhdr) \ 270 le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(31, 24)) 271 #define GET_FW_HDR_MONTH(fwhdr) \ 272 le32_get_bits(*((__le32 *)(fwhdr) + 4), GENMASK(7, 0)) 273 #define GET_FW_HDR_DATE(fwhdr) \ 274 le32_get_bits(*((__le32 *)(fwhdr) + 4), GENMASK(15, 8)) 275 #define GET_FW_HDR_HOUR(fwhdr) \ 276 le32_get_bits(*((__le32 *)(fwhdr) + 4), GENMASK(23, 16)) 277 #define GET_FW_HDR_MIN(fwhdr) \ 278 le32_get_bits(*((__le32 *)(fwhdr) + 4), GENMASK(31, 24)) 279 #define GET_FW_HDR_YEAR(fwhdr) \ 280 le32_get_bits(*((__le32 *)(fwhdr) + 5), GENMASK(31, 0)) 281 #define GET_FW_HDR_SEC_NUM(fwhdr) \ 282 le32_get_bits(*((__le32 *)(fwhdr) + 6), GENMASK(15, 8)) 283 #define GET_FW_HDR_CMD_VERSERION(fwhdr) \ 284 le32_get_bits(*((__le32 *)(fwhdr) + 7), GENMASK(31, 24)) 285 #define SET_FW_HDR_PART_SIZE(fwhdr, val) \ 286 le32p_replace_bits((__le32 *)(fwhdr) + 7, val, GENMASK(15, 0)) 287 288 #define SET_CTRL_INFO_MACID(table, val) \ 289 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)) 290 #define SET_CTRL_INFO_OPERATION(table, val) \ 291 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)) 292 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0) 293 #define SET_CMC_TBL_DATARATE(table, val) \ 294 do { \ 295 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0)); \ 296 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE, \ 297 GENMASK(8, 0)); \ 298 } while (0) 299 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0) 300 #define SET_CMC_TBL_FORCE_TXOP(table, val) \ 301 do { \ 302 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9)); \ 303 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP, \ 304 BIT(9)); \ 305 } while (0) 306 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0) 307 #define SET_CMC_TBL_DATA_BW(table, val) \ 308 do { \ 309 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10)); \ 310 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW, \ 311 GENMASK(11, 10)); \ 312 } while (0) 313 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0) 314 #define SET_CMC_TBL_DATA_GI_LTF(table, val) \ 315 do { \ 316 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12)); \ 317 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF, \ 318 GENMASK(14, 12)); \ 319 } while (0) 320 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0) 321 #define SET_CMC_TBL_DARF_TC_INDEX(table, val) \ 322 do { \ 323 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); \ 324 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX, \ 325 BIT(15)); \ 326 } while (0) 327 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0) 328 #define SET_CMC_TBL_ARFR_CTRL(table, val) \ 329 do { \ 330 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16)); \ 331 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL, \ 332 GENMASK(19, 16)); \ 333 } while (0) 334 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0) 335 #define SET_CMC_TBL_ACQ_RPT_EN(table, val) \ 336 do { \ 337 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20)); \ 338 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN, \ 339 BIT(20)); \ 340 } while (0) 341 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0) 342 #define SET_CMC_TBL_MGQ_RPT_EN(table, val) \ 343 do { \ 344 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21)); \ 345 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN, \ 346 BIT(21)); \ 347 } while (0) 348 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0) 349 #define SET_CMC_TBL_ULQ_RPT_EN(table, val) \ 350 do { \ 351 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22)); \ 352 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN, \ 353 BIT(22)); \ 354 } while (0) 355 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0) 356 #define SET_CMC_TBL_TWTQ_RPT_EN(table, val) \ 357 do { \ 358 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23)); \ 359 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN, \ 360 BIT(23)); \ 361 } while (0) 362 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0) 363 #define SET_CMC_TBL_DISRTSFB(table, val) \ 364 do { \ 365 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25)); \ 366 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB, \ 367 BIT(25)); \ 368 } while (0) 369 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0) 370 #define SET_CMC_TBL_DISDATAFB(table, val) \ 371 do { \ 372 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26)); \ 373 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB, \ 374 BIT(26)); \ 375 } while (0) 376 #define SET_CMC_TBL_MASK_TRYRATE BIT(0) 377 #define SET_CMC_TBL_TRYRATE(table, val) \ 378 do { \ 379 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27)); \ 380 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE, \ 381 BIT(27)); \ 382 } while (0) 383 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0) 384 #define SET_CMC_TBL_AMPDU_DENSITY(table, val) \ 385 do { \ 386 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28)); \ 387 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY, \ 388 GENMASK(31, 28)); \ 389 } while (0) 390 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0) 391 #define SET_CMC_TBL_DATA_RTY_LOWEST_RATE(table, val) \ 392 do { \ 393 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0)); \ 394 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE, \ 395 GENMASK(8, 0)); \ 396 } while (0) 397 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0) 398 #define SET_CMC_TBL_AMPDU_TIME_SEL(table, val) \ 399 do { \ 400 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9)); \ 401 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL, \ 402 BIT(9)); \ 403 } while (0) 404 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0) 405 #define SET_CMC_TBL_AMPDU_LEN_SEL(table, val) \ 406 do { \ 407 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10)); \ 408 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL, \ 409 BIT(10)); \ 410 } while (0) 411 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0) 412 #define SET_CMC_TBL_RTS_TXCNT_LMT_SEL(table, val) \ 413 do { \ 414 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11)); \ 415 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL, \ 416 BIT(11)); \ 417 } while (0) 418 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0) 419 #define SET_CMC_TBL_RTS_TXCNT_LMT(table, val) \ 420 do { \ 421 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12)); \ 422 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT, \ 423 GENMASK(15, 12)); \ 424 } while (0) 425 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0) 426 #define SET_CMC_TBL_RTSRATE(table, val) \ 427 do { \ 428 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16)); \ 429 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE, \ 430 GENMASK(24, 16)); \ 431 } while (0) 432 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0) 433 #define SET_CMC_TBL_VCS_STBC(table, val) \ 434 do { \ 435 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27)); \ 436 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC, \ 437 BIT(27)); \ 438 } while (0) 439 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0) 440 #define SET_CMC_TBL_RTS_RTY_LOWEST_RATE(table, val) \ 441 do { \ 442 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28)); \ 443 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE, \ 444 GENMASK(31, 28)); \ 445 } while (0) 446 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0) 447 #define SET_CMC_TBL_DATA_TX_CNT_LMT(table, val) \ 448 do { \ 449 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0)); \ 450 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT, \ 451 GENMASK(5, 0)); \ 452 } while (0) 453 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0) 454 #define SET_CMC_TBL_DATA_TXCNT_LMT_SEL(table, val) \ 455 do { \ 456 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6)); \ 457 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL, \ 458 BIT(6)); \ 459 } while (0) 460 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0) 461 #define SET_CMC_TBL_MAX_AGG_NUM_SEL(table, val) \ 462 do { \ 463 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7)); \ 464 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL, \ 465 BIT(7)); \ 466 } while (0) 467 #define SET_CMC_TBL_MASK_RTS_EN BIT(0) 468 #define SET_CMC_TBL_RTS_EN(table, val) \ 469 do { \ 470 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8)); \ 471 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN, \ 472 BIT(8)); \ 473 } while (0) 474 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0) 475 #define SET_CMC_TBL_CTS2SELF_EN(table, val) \ 476 do { \ 477 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9)); \ 478 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN, \ 479 BIT(9)); \ 480 } while (0) 481 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0) 482 #define SET_CMC_TBL_CCA_RTS(table, val) \ 483 do { \ 484 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10)); \ 485 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS, \ 486 GENMASK(11, 10)); \ 487 } while (0) 488 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0) 489 #define SET_CMC_TBL_HW_RTS_EN(table, val) \ 490 do { \ 491 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12)); \ 492 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN, \ 493 BIT(12)); \ 494 } while (0) 495 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0) 496 #define SET_CMC_TBL_RTS_DROP_DATA_MODE(table, val) \ 497 do { \ 498 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13)); \ 499 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE, \ 500 GENMASK(14, 13)); \ 501 } while (0) 502 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0) 503 #define SET_CMC_TBL_AMPDU_MAX_LEN(table, val) \ 504 do { \ 505 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16)); \ 506 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN, \ 507 GENMASK(26, 16)); \ 508 } while (0) 509 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0) 510 #define SET_CMC_TBL_UL_MU_DIS(table, val) \ 511 do { \ 512 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); \ 513 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS, \ 514 BIT(27)); \ 515 } while (0) 516 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0) 517 #define SET_CMC_TBL_AMPDU_MAX_TIME(table, val) \ 518 do { \ 519 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28)); \ 520 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME, \ 521 GENMASK(31, 28)); \ 522 } while (0) 523 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0) 524 #define SET_CMC_TBL_MAX_AGG_NUM(table, val) \ 525 do { \ 526 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0)); \ 527 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM, \ 528 GENMASK(7, 0)); \ 529 } while (0) 530 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0) 531 #define SET_CMC_TBL_BA_BMAP(table, val) \ 532 do { \ 533 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8)); \ 534 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP, \ 535 GENMASK(9, 8)); \ 536 } while (0) 537 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0) 538 #define SET_CMC_TBL_VO_LFTIME_SEL(table, val) \ 539 do { \ 540 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16)); \ 541 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL, \ 542 GENMASK(18, 16)); \ 543 } while (0) 544 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0) 545 #define SET_CMC_TBL_VI_LFTIME_SEL(table, val) \ 546 do { \ 547 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19)); \ 548 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL, \ 549 GENMASK(21, 19)); \ 550 } while (0) 551 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0) 552 #define SET_CMC_TBL_BE_LFTIME_SEL(table, val) \ 553 do { \ 554 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22)); \ 555 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL, \ 556 GENMASK(24, 22)); \ 557 } while (0) 558 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0) 559 #define SET_CMC_TBL_BK_LFTIME_SEL(table, val) \ 560 do { \ 561 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25)); \ 562 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL, \ 563 GENMASK(27, 25)); \ 564 } while (0) 565 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0) 566 #define SET_CMC_TBL_SECTYPE(table, val) \ 567 do { \ 568 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28)); \ 569 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE, \ 570 GENMASK(31, 28)); \ 571 } while (0) 572 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0) 573 #define SET_CMC_TBL_MULTI_PORT_ID(table, val) \ 574 do { \ 575 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0)); \ 576 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID, \ 577 GENMASK(2, 0)); \ 578 } while (0) 579 #define SET_CMC_TBL_MASK_BMC BIT(0) 580 #define SET_CMC_TBL_BMC(table, val) \ 581 do { \ 582 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3)); \ 583 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC, \ 584 BIT(3)); \ 585 } while (0) 586 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0) 587 #define SET_CMC_TBL_MBSSID(table, val) \ 588 do { \ 589 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4)); \ 590 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID, \ 591 GENMASK(7, 4)); \ 592 } while (0) 593 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0) 594 #define SET_CMC_TBL_NAVUSEHDR(table, val) \ 595 do { \ 596 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); \ 597 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR, \ 598 BIT(8)); \ 599 } while (0) 600 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0) 601 #define SET_CMC_TBL_TXPWR_MODE(table, val) \ 602 do { \ 603 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9)); \ 604 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE, \ 605 GENMASK(11, 9)); \ 606 } while (0) 607 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0) 608 #define SET_CMC_TBL_DATA_DCM(table, val) \ 609 do { \ 610 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12)); \ 611 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM, \ 612 BIT(12)); \ 613 } while (0) 614 #define SET_CMC_TBL_MASK_DATA_ER BIT(0) 615 #define SET_CMC_TBL_DATA_ER(table, val) \ 616 do { \ 617 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13)); \ 618 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER, \ 619 BIT(13)); \ 620 } while (0) 621 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0) 622 #define SET_CMC_TBL_DATA_LDPC(table, val) \ 623 do { \ 624 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14)); \ 625 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC, \ 626 BIT(14)); \ 627 } while (0) 628 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0) 629 #define SET_CMC_TBL_DATA_STBC(table, val) \ 630 do { \ 631 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); \ 632 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC, \ 633 BIT(15)); \ 634 } while (0) 635 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0) 636 #define SET_CMC_TBL_A_CTRL_BQR(table, val) \ 637 do { \ 638 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16)); \ 639 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR, \ 640 BIT(16)); \ 641 } while (0) 642 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0) 643 #define SET_CMC_TBL_A_CTRL_UPH(table, val) \ 644 do { \ 645 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17)); \ 646 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH, \ 647 BIT(17)); \ 648 } while (0) 649 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0) 650 #define SET_CMC_TBL_A_CTRL_BSR(table, val) \ 651 do { \ 652 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18)); \ 653 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR, \ 654 BIT(18)); \ 655 } while (0) 656 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0) 657 #define SET_CMC_TBL_A_CTRL_CAS(table, val) \ 658 do { \ 659 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19)); \ 660 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS, \ 661 BIT(19)); \ 662 } while (0) 663 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0) 664 #define SET_CMC_TBL_DATA_BW_ER(table, val) \ 665 do { \ 666 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20)); \ 667 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER, \ 668 BIT(20)); \ 669 } while (0) 670 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0) 671 #define SET_CMC_TBL_LSIG_TXOP_EN(table, val) \ 672 do { \ 673 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21)); \ 674 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN, \ 675 BIT(21)); \ 676 } while (0) 677 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0) 678 #define SET_CMC_TBL_CTRL_CNT_VLD(table, val) \ 679 do { \ 680 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27)); \ 681 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD, \ 682 BIT(27)); \ 683 } while (0) 684 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0) 685 #define SET_CMC_TBL_CTRL_CNT(table, val) \ 686 do { \ 687 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28)); \ 688 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT, \ 689 GENMASK(31, 28)); \ 690 } while (0) 691 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0) 692 #define SET_CMC_TBL_RESP_REF_RATE(table, val) \ 693 do { \ 694 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0)); \ 695 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE, \ 696 GENMASK(8, 0)); \ 697 } while (0) 698 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0) 699 #define SET_CMC_TBL_ALL_ACK_SUPPORT(table, val) \ 700 do { \ 701 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12)); \ 702 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT, \ 703 BIT(12)); \ 704 } while (0) 705 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0) 706 #define SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(table, val) \ 707 do { \ 708 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13)); \ 709 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT, \ 710 BIT(13)); \ 711 } while (0) 712 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0) 713 #define SET_CMC_TBL_NTX_PATH_EN(table, val) \ 714 do { \ 715 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16)); \ 716 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN, \ 717 GENMASK(19, 16)); \ 718 } while (0) 719 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0) 720 #define SET_CMC_TBL_PATH_MAP_A(table, val) \ 721 do { \ 722 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20)); \ 723 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A, \ 724 GENMASK(21, 20)); \ 725 } while (0) 726 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0) 727 #define SET_CMC_TBL_PATH_MAP_B(table, val) \ 728 do { \ 729 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22)); \ 730 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B, \ 731 GENMASK(23, 22)); \ 732 } while (0) 733 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0) 734 #define SET_CMC_TBL_PATH_MAP_C(table, val) \ 735 do { \ 736 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24)); \ 737 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C, \ 738 GENMASK(25, 24)); \ 739 } while (0) 740 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0) 741 #define SET_CMC_TBL_PATH_MAP_D(table, val) \ 742 do { \ 743 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26)); \ 744 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D, \ 745 GENMASK(27, 26)); \ 746 } while (0) 747 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0) 748 #define SET_CMC_TBL_ANTSEL_A(table, val) \ 749 do { \ 750 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28)); \ 751 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A, \ 752 BIT(28)); \ 753 } while (0) 754 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0) 755 #define SET_CMC_TBL_ANTSEL_B(table, val) \ 756 do { \ 757 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29)); \ 758 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B, \ 759 BIT(29)); \ 760 } while (0) 761 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0) 762 #define SET_CMC_TBL_ANTSEL_C(table, val) \ 763 do { \ 764 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30)); \ 765 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C, \ 766 BIT(30)); \ 767 } while (0) 768 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0) 769 #define SET_CMC_TBL_ANTSEL_D(table, val) \ 770 do { \ 771 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31)); \ 772 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D, \ 773 BIT(31)); \ 774 } while (0) 775 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0) 776 #define SET_CMC_TBL_ADDR_CAM_INDEX(table, val) \ 777 do { \ 778 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); \ 779 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX, \ 780 GENMASK(7, 0)); \ 781 } while (0) 782 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0) 783 #define SET_CMC_TBL_PAID(table, val) \ 784 do { \ 785 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8)); \ 786 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID, \ 787 GENMASK(16, 8)); \ 788 } while (0) 789 #define SET_CMC_TBL_MASK_ULDL BIT(0) 790 #define SET_CMC_TBL_ULDL(table, val) \ 791 do { \ 792 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17)); \ 793 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL, \ 794 BIT(17)); \ 795 } while (0) 796 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0) 797 #define SET_CMC_TBL_DOPPLER_CTRL(table, val) \ 798 do { \ 799 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18)); \ 800 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL, \ 801 GENMASK(19, 18)); \ 802 } while (0) 803 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0) 804 #define SET_CMC_TBL_NOMINAL_PKT_PADDING(table, val) \ 805 do { \ 806 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20)); \ 807 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, \ 808 GENMASK(21, 20)); \ 809 } while (0) 810 #define SET_CMC_TBL_NOMINAL_PKT_PADDING40(table, val) \ 811 do { \ 812 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22)); \ 813 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, \ 814 GENMASK(23, 22)); \ 815 } while (0) 816 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0) 817 #define SET_CMC_TBL_TXPWR_TOLERENCE(table, val) \ 818 do { \ 819 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24)); \ 820 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE, \ 821 GENMASK(27, 24)); \ 822 } while (0) 823 #define SET_CMC_TBL_NOMINAL_PKT_PADDING80(table, val) \ 824 do { \ 825 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30)); \ 826 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, \ 827 GENMASK(31, 30)); \ 828 } while (0) 829 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0) 830 #define SET_CMC_TBL_NC(table, val) \ 831 do { \ 832 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0)); \ 833 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC, \ 834 GENMASK(2, 0)); \ 835 } while (0) 836 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0) 837 #define SET_CMC_TBL_NR(table, val) \ 838 do { \ 839 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3)); \ 840 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR, \ 841 GENMASK(5, 3)); \ 842 } while (0) 843 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0) 844 #define SET_CMC_TBL_NG(table, val) \ 845 do { \ 846 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6)); \ 847 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG, \ 848 GENMASK(7, 6)); \ 849 } while (0) 850 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0) 851 #define SET_CMC_TBL_CB(table, val) \ 852 do { \ 853 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8)); \ 854 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB, \ 855 GENMASK(9, 8)); \ 856 } while (0) 857 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0) 858 #define SET_CMC_TBL_CS(table, val) \ 859 do { \ 860 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10)); \ 861 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS, \ 862 GENMASK(11, 10)); \ 863 } while (0) 864 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0) 865 #define SET_CMC_TBL_CSI_TXBF_EN(table, val) \ 866 do { \ 867 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12)); \ 868 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN, \ 869 BIT(12)); \ 870 } while (0) 871 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0) 872 #define SET_CMC_TBL_CSI_STBC_EN(table, val) \ 873 do { \ 874 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13)); \ 875 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN, \ 876 BIT(13)); \ 877 } while (0) 878 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0) 879 #define SET_CMC_TBL_CSI_LDPC_EN(table, val) \ 880 do { \ 881 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14)); \ 882 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN, \ 883 BIT(14)); \ 884 } while (0) 885 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0) 886 #define SET_CMC_TBL_CSI_PARA_EN(table, val) \ 887 do { \ 888 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15)); \ 889 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN, \ 890 BIT(15)); \ 891 } while (0) 892 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0) 893 #define SET_CMC_TBL_CSI_FIX_RATE(table, val) \ 894 do { \ 895 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16)); \ 896 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE, \ 897 GENMASK(24, 16)); \ 898 } while (0) 899 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0) 900 #define SET_CMC_TBL_CSI_GI_LTF(table, val) \ 901 do { \ 902 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25)); \ 903 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF, \ 904 GENMASK(27, 25)); \ 905 } while (0) 906 #define SET_CMC_TBL_MASK_CSI_GID_SEL BIT(0) 907 #define SET_CMC_TBL_CSI_GID_SEL(table, val) \ 908 do { \ 909 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(29)); \ 910 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GID_SEL, \ 911 BIT(29)); \ 912 } while (0) 913 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0) 914 #define SET_CMC_TBL_CSI_BW(table, val) \ 915 do { \ 916 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30)); \ 917 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW, \ 918 GENMASK(31, 30)); \ 919 } while (0) 920 921 #define SET_FWROLE_MAINTAIN_MACID(h2c, val) \ 922 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) 923 #define SET_FWROLE_MAINTAIN_SELF_ROLE(h2c, val) \ 924 le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8)) 925 #define SET_FWROLE_MAINTAIN_UPD_MODE(h2c, val) \ 926 le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10)) 927 #define SET_FWROLE_MAINTAIN_WIFI_ROLE(h2c, val) \ 928 le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13)) 929 930 #define SET_JOININFO_MACID(h2c, val) \ 931 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) 932 #define SET_JOININFO_OP(h2c, val) \ 933 le32p_replace_bits((__le32 *)h2c, val, BIT(8)) 934 #define SET_JOININFO_BAND(h2c, val) \ 935 le32p_replace_bits((__le32 *)h2c, val, BIT(9)) 936 #define SET_JOININFO_WMM(h2c, val) \ 937 le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10)) 938 #define SET_JOININFO_TGR(h2c, val) \ 939 le32p_replace_bits((__le32 *)h2c, val, BIT(12)) 940 #define SET_JOININFO_ISHESTA(h2c, val) \ 941 le32p_replace_bits((__le32 *)h2c, val, BIT(13)) 942 #define SET_JOININFO_DLBW(h2c, val) \ 943 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14)) 944 #define SET_JOININFO_TF_MAC_PAD(h2c, val) \ 945 le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16)) 946 #define SET_JOININFO_DL_T_PE(h2c, val) \ 947 le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18)) 948 #define SET_JOININFO_PORT_ID(h2c, val) \ 949 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21)) 950 #define SET_JOININFO_NET_TYPE(h2c, val) \ 951 le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24)) 952 #define SET_JOININFO_WIFI_ROLE(h2c, val) \ 953 le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26)) 954 #define SET_JOININFO_SELF_ROLE(h2c, val) \ 955 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30)) 956 957 #define SET_GENERAL_PKT_MACID(h2c, val) \ 958 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) 959 #define SET_GENERAL_PKT_PROBRSP_ID(h2c, val) \ 960 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)) 961 #define SET_GENERAL_PKT_PSPOLL_ID(h2c, val) \ 962 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)) 963 #define SET_GENERAL_PKT_NULL_ID(h2c, val) \ 964 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)) 965 #define SET_GENERAL_PKT_QOS_NULL_ID(h2c, val) \ 966 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)) 967 #define SET_GENERAL_PKT_CTS2SELF_ID(h2c, val) \ 968 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)) 969 970 #define SET_LOG_CFG_LEVEL(h2c, val) \ 971 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) 972 #define SET_LOG_CFG_PATH(h2c, val) \ 973 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)) 974 #define SET_LOG_CFG_COMP(h2c, val) \ 975 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)) 976 #define SET_LOG_CFG_COMP_EXT(h2c, val) \ 977 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0)) 978 979 #define SET_BA_CAM_VALID(h2c, val) \ 980 le32p_replace_bits((__le32 *)h2c, val, BIT(0)) 981 #define SET_BA_CAM_INIT_REQ(h2c, val) \ 982 le32p_replace_bits((__le32 *)h2c, val, BIT(1)) 983 #define SET_BA_CAM_ENTRY_IDX(h2c, val) \ 984 le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2)) 985 #define SET_BA_CAM_TID(h2c, val) \ 986 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4)) 987 #define SET_BA_CAM_MACID(h2c, val) \ 988 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)) 989 #define SET_BA_CAM_BMAP_SIZE(h2c, val) \ 990 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)) 991 #define SET_BA_CAM_SSN(h2c, val) \ 992 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20)) 993 994 #define SET_LPS_PARM_MACID(h2c, val) \ 995 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) 996 #define SET_LPS_PARM_PSMODE(h2c, val) \ 997 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)) 998 #define SET_LPS_PARM_RLBM(h2c, val) \ 999 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)) 1000 #define SET_LPS_PARM_SMARTPS(h2c, val) \ 1001 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20)) 1002 #define SET_LPS_PARM_AWAKEINTERVAL(h2c, val) \ 1003 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)) 1004 #define SET_LPS_PARM_VOUAPSD(h2c, val) \ 1005 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0)) 1006 #define SET_LPS_PARM_VIUAPSD(h2c, val) \ 1007 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1)) 1008 #define SET_LPS_PARM_BEUAPSD(h2c, val) \ 1009 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2)) 1010 #define SET_LPS_PARM_BKUAPSD(h2c, val) \ 1011 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3)) 1012 #define SET_LPS_PARM_LASTRPWM(h2c, val) \ 1013 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)) 1014 1015 enum rtw89_btc_btf_h2c_class { 1016 BTFC_SET = 0x10, 1017 BTFC_GET = 0x11, 1018 BTFC_FW_EVENT = 0x12, 1019 }; 1020 1021 enum rtw89_btc_btf_set { 1022 SET_REPORT_EN = 0x0, 1023 SET_SLOT_TABLE, 1024 SET_MREG_TABLE, 1025 SET_CX_POLICY, 1026 SET_GPIO_DBG, 1027 SET_DRV_INFO, 1028 SET_DRV_EVENT, 1029 SET_BT_WREG_ADDR, 1030 SET_BT_WREG_VAL, 1031 SET_BT_RREG_ADDR, 1032 SET_BT_WL_CH_INFO, 1033 SET_BT_INFO_REPORT, 1034 SET_BT_IGNORE_WLAN_ACT, 1035 SET_BT_TX_PWR, 1036 SET_BT_LNA_CONSTRAIN, 1037 SET_BT_GOLDEN_RX_RANGE, 1038 SET_BT_PSD_REPORT, 1039 SET_H2C_TEST, 1040 SET_MAX1, 1041 }; 1042 1043 enum rtw89_btc_cxdrvinfo { 1044 CXDRVINFO_INIT = 0, 1045 CXDRVINFO_ROLE, 1046 CXDRVINFO_DBCC, 1047 CXDRVINFO_SMAP, 1048 CXDRVINFO_RFK, 1049 CXDRVINFO_RUN, 1050 CXDRVINFO_CTRL, 1051 CXDRVINFO_SCAN, 1052 CXDRVINFO_MAX, 1053 }; 1054 1055 #define RTW89_SET_FWCMD_CXHDR_TYPE(cmd, val) \ 1056 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0)) 1057 #define RTW89_SET_FWCMD_CXHDR_LEN(cmd, val) \ 1058 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0)) 1059 1060 #define RTW89_SET_FWCMD_CXINIT_ANT_TYPE(cmd, val) \ 1061 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)) 1062 #define RTW89_SET_FWCMD_CXINIT_ANT_NUM(cmd, val) \ 1063 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)) 1064 #define RTW89_SET_FWCMD_CXINIT_ANT_ISO(cmd, val) \ 1065 u8p_replace_bits((u8 *)(cmd) + 4, val, GENMASK(7, 0)) 1066 #define RTW89_SET_FWCMD_CXINIT_ANT_POS(cmd, val) \ 1067 u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(0)) 1068 #define RTW89_SET_FWCMD_CXINIT_ANT_DIVERSITY(cmd, val) \ 1069 u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(1)) 1070 #define RTW89_SET_FWCMD_CXINIT_MOD_RFE(cmd, val) \ 1071 u8p_replace_bits((u8 *)(cmd) + 6, val, GENMASK(7, 0)) 1072 #define RTW89_SET_FWCMD_CXINIT_MOD_CV(cmd, val) \ 1073 u8p_replace_bits((u8 *)(cmd) + 7, val, GENMASK(7, 0)) 1074 #define RTW89_SET_FWCMD_CXINIT_MOD_BT_SOLO(cmd, val) \ 1075 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(0)) 1076 #define RTW89_SET_FWCMD_CXINIT_MOD_BT_POS(cmd, val) \ 1077 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(1)) 1078 #define RTW89_SET_FWCMD_CXINIT_MOD_SW_TYPE(cmd, val) \ 1079 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(2)) 1080 #define RTW89_SET_FWCMD_CXINIT_WL_GCH(cmd, val) \ 1081 u8p_replace_bits((u8 *)(cmd) + 10, val, GENMASK(7, 0)) 1082 #define RTW89_SET_FWCMD_CXINIT_WL_ONLY(cmd, val) \ 1083 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(0)) 1084 #define RTW89_SET_FWCMD_CXINIT_WL_INITOK(cmd, val) \ 1085 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(1)) 1086 #define RTW89_SET_FWCMD_CXINIT_DBCC_EN(cmd, val) \ 1087 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(2)) 1088 #define RTW89_SET_FWCMD_CXINIT_CX_OTHER(cmd, val) \ 1089 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(3)) 1090 #define RTW89_SET_FWCMD_CXINIT_BT_ONLY(cmd, val) \ 1091 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(4)) 1092 1093 #define RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(cmd, val) \ 1094 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)) 1095 #define RTW89_SET_FWCMD_CXROLE_LINK_MODE(cmd, val) \ 1096 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)) 1097 #define RTW89_SET_FWCMD_CXROLE_ROLE_NONE(cmd, val) \ 1098 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0)) 1099 #define RTW89_SET_FWCMD_CXROLE_ROLE_STA(cmd, val) \ 1100 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1)) 1101 #define RTW89_SET_FWCMD_CXROLE_ROLE_AP(cmd, val) \ 1102 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2)) 1103 #define RTW89_SET_FWCMD_CXROLE_ROLE_VAP(cmd, val) \ 1104 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3)) 1105 #define RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(cmd, val) \ 1106 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4)) 1107 #define RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(cmd, val) \ 1108 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5)) 1109 #define RTW89_SET_FWCMD_CXROLE_ROLE_MESH(cmd, val) \ 1110 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6)) 1111 #define RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(cmd, val) \ 1112 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7)) 1113 #define RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(cmd, val) \ 1114 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8)) 1115 #define RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(cmd, val) \ 1116 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9)) 1117 #define RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(cmd, val) \ 1118 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10)) 1119 #define RTW89_SET_FWCMD_CXROLE_ROLE_NAN(cmd, val) \ 1120 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11)) 1121 #define RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(cmd, val, n) \ 1122 u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(0)) 1123 #define RTW89_SET_FWCMD_CXROLE_ACT_PID(cmd, val, n) \ 1124 u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, GENMASK(3, 1)) 1125 #define RTW89_SET_FWCMD_CXROLE_ACT_PHY(cmd, val, n) \ 1126 u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(4)) 1127 #define RTW89_SET_FWCMD_CXROLE_ACT_NOA(cmd, val, n) \ 1128 u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(5)) 1129 #define RTW89_SET_FWCMD_CXROLE_ACT_BAND(cmd, val, n) \ 1130 u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, GENMASK(7, 6)) 1131 #define RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(cmd, val, n) \ 1132 u8p_replace_bits((u8 *)(cmd) + (7 + 12 * (n)), val, BIT(0)) 1133 #define RTW89_SET_FWCMD_CXROLE_ACT_BW(cmd, val, n) \ 1134 u8p_replace_bits((u8 *)(cmd) + (7 + 12 * (n)), val, GENMASK(7, 1)) 1135 #define RTW89_SET_FWCMD_CXROLE_ACT_ROLE(cmd, val, n) \ 1136 u8p_replace_bits((u8 *)(cmd) + (8 + 12 * (n)), val, GENMASK(7, 0)) 1137 #define RTW89_SET_FWCMD_CXROLE_ACT_CH(cmd, val, n) \ 1138 u8p_replace_bits((u8 *)(cmd) + (9 + 12 * (n)), val, GENMASK(7, 0)) 1139 #define RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(cmd, val, n) \ 1140 le16p_replace_bits((__le16 *)((u8 *)(cmd) + (10 + 12 * (n))), val, GENMASK(15, 0)) 1141 #define RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(cmd, val, n) \ 1142 le16p_replace_bits((__le16 *)((u8 *)(cmd) + (12 + 12 * (n))), val, GENMASK(15, 0)) 1143 #define RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(cmd, val, n) \ 1144 le16p_replace_bits((__le16 *)((u8 *)(cmd) + (14 + 12 * (n))), val, GENMASK(15, 0)) 1145 #define RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(cmd, val, n) \ 1146 le16p_replace_bits((__le16 *)((u8 *)(cmd) + (16 + 12 * (n))), val, GENMASK(15, 0)) 1147 1148 #define RTW89_SET_FWCMD_CXCTRL_MANUAL(cmd, val) \ 1149 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0)) 1150 #define RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(cmd, val) \ 1151 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1)) 1152 #define RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(cmd, val) \ 1153 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2)) 1154 #define RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(cmd, val) \ 1155 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3)) 1156 1157 #define RTW89_SET_FWCMD_CXRFK_STATE(cmd, val) \ 1158 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0)) 1159 #define RTW89_SET_FWCMD_CXRFK_PATH_MAP(cmd, val) \ 1160 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2)) 1161 #define RTW89_SET_FWCMD_CXRFK_PHY_MAP(cmd, val) \ 1162 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6)) 1163 #define RTW89_SET_FWCMD_CXRFK_BAND(cmd, val) \ 1164 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8)) 1165 #define RTW89_SET_FWCMD_CXRFK_TYPE(cmd, val) \ 1166 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10)) 1167 1168 #define RTW89_C2H_HEADER_LEN 8 1169 1170 #define RTW89_GET_C2H_CATEGORY(c2h) \ 1171 le32_get_bits(*((__le32 *)c2h), GENMASK(1, 0)) 1172 #define RTW89_GET_C2H_CLASS(c2h) \ 1173 le32_get_bits(*((__le32 *)c2h), GENMASK(7, 2)) 1174 #define RTW89_GET_C2H_FUNC(c2h) \ 1175 le32_get_bits(*((__le32 *)c2h), GENMASK(15, 8)) 1176 #define RTW89_GET_C2H_LEN(c2h) \ 1177 le32_get_bits(*((__le32 *)(c2h) + 1), GENMASK(13, 0)) 1178 1179 #define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2) 1180 #define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN) 1181 1182 #define RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h) \ 1183 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(1, 0)) 1184 #define RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h) \ 1185 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(7, 2)) 1186 #define RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h) \ 1187 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(15, 8)) 1188 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h) \ 1189 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(23, 16)) 1190 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h) \ 1191 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(31, 24)) 1192 1193 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \ 1194 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(1, 0)) 1195 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \ 1196 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(7, 2)) 1197 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \ 1198 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(15, 8)) 1199 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \ 1200 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(23, 16)) 1201 1202 #define RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h) \ 1203 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(15, 0)) 1204 #define RTW89_GET_PHY_C2H_RA_RPT_RETRY_RATIO(c2h) \ 1205 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(23, 16)) 1206 #define RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h) \ 1207 le32_get_bits(*((__le32 *)(c2h) + 3), GENMASK(6, 0)) 1208 #define RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h) \ 1209 le32_get_bits(*((__le32 *)(c2h) + 3), GENMASK(9, 8)) 1210 #define RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h) \ 1211 le32_get_bits(*((__le32 *)(c2h) + 3), GENMASK(12, 10)) 1212 #define RTW89_GET_PHY_C2H_RA_RPT_BW(c2h) \ 1213 le32_get_bits(*((__le32 *)(c2h) + 3), GENMASK(14, 13)) 1214 1215 /* VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS 1216 * HT-new: [6:5]: NA, [4:0]: MCS 1217 */ 1218 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4) 1219 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0) 1220 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0) 1221 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \ 1222 FIELD_PREP(GENMASK(2, 0), mcs)) 1223 1224 #define RTW89_FW_HDR_SIZE 32 1225 #define RTW89_FW_SECTION_HDR_SIZE 16 1226 1227 #define RTW89_MFW_SIG 0xFF 1228 1229 struct rtw89_mfw_info { 1230 u8 cv; 1231 u8 type; /* enum rtw89_fw_type */ 1232 u8 mp; 1233 u8 rsvd; 1234 __le32 shift; 1235 __le32 size; 1236 u8 rsvd2[4]; 1237 } __packed; 1238 1239 struct rtw89_mfw_hdr { 1240 u8 sig; /* RTW89_MFW_SIG */ 1241 u8 fw_nr; 1242 u8 rsvd[14]; 1243 struct rtw89_mfw_info info[]; 1244 } __packed; 1245 1246 struct fwcmd_hdr { 1247 __le32 hdr0; 1248 __le32 hdr1; 1249 }; 1250 1251 #define RTW89_H2C_RF_PAGE_SIZE 500 1252 #define RTW89_H2C_RF_PAGE_NUM 3 1253 struct rtw89_fw_h2c_rf_reg_info { 1254 enum rtw89_rf_path rf_path; 1255 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE]; 1256 u16 curr_idx; 1257 }; 1258 1259 #define H2C_SEC_CAM_LEN 24 1260 1261 #define H2C_HEADER_LEN 8 1262 #define H2C_HDR_CAT GENMASK(1, 0) 1263 #define H2C_HDR_CLASS GENMASK(7, 2) 1264 #define H2C_HDR_FUNC GENMASK(15, 8) 1265 #define H2C_HDR_DEL_TYPE GENMASK(19, 16) 1266 #define H2C_HDR_H2C_SEQ GENMASK(31, 24) 1267 #define H2C_HDR_TOTAL_LEN GENMASK(13, 0) 1268 #define H2C_HDR_REC_ACK BIT(14) 1269 #define H2C_HDR_DONE_ACK BIT(15) 1270 1271 #define FWCMD_TYPE_H2C 0 1272 1273 #define H2C_CAT_MAC 0x1 1274 1275 /* CLASS 0 - FW INFO */ 1276 #define H2C_CL_FW_INFO 0x0 1277 #define H2C_FUNC_LOG_CFG 0x0 1278 #define H2C_FUNC_MAC_GENERAL_PKT 0x1 1279 1280 /* CLASS 2 - PS */ 1281 #define H2C_CL_MAC_PS 0x2 1282 #define H2C_FUNC_MAC_LPS_PARM 0x0 1283 1284 /* CLASS 3 - FW download */ 1285 #define H2C_CL_MAC_FWDL 0x3 1286 #define H2C_FUNC_MAC_FWHDR_DL 0x0 1287 1288 /* CLASS 5 - Frame Exchange */ 1289 #define H2C_CL_MAC_FR_EXCHG 0x5 1290 #define H2C_FUNC_MAC_CCTLINFO_UD 0x2 1291 1292 /* CLASS 6 - Address CAM */ 1293 #define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6 1294 #define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0 1295 1296 /* CLASS 8 - Media Status Report */ 1297 #define H2C_CL_MAC_MEDIA_RPT 0x8 1298 #define H2C_FUNC_MAC_JOININFO 0x0 1299 #define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4 1300 1301 /* CLASS 9 - FW offload */ 1302 #define H2C_CL_MAC_FW_OFLD 0x9 1303 #define H2C_FUNC_MAC_MACID_PAUSE 0x8 1304 #define H2C_FUNC_USR_EDCA 0xF 1305 #define H2C_FUNC_OFLD_CFG 0x14 1306 1307 /* CLASS 10 - Security CAM */ 1308 #define H2C_CL_MAC_SEC_CAM 0xa 1309 #define H2C_FUNC_MAC_SEC_UPD 0x1 1310 1311 /* CLASS 12 - BA CAM */ 1312 #define H2C_CL_BA_CAM 0xc 1313 #define H2C_FUNC_MAC_BA_CAM 0x0 1314 1315 #define H2C_CAT_OUTSRC 0x2 1316 1317 #define H2C_CL_OUTSRC_RA 0x1 1318 #define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0 1319 1320 #define H2C_CL_OUTSRC_RF_REG_A 0x8 1321 #define H2C_CL_OUTSRC_RF_REG_B 0x9 1322 1323 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev); 1324 int rtw89_fw_recognize(struct rtw89_dev *rtwdev); 1325 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type); 1326 int rtw89_load_firmware(struct rtw89_dev *rtwdev); 1327 void rtw89_unload_firmware(struct rtw89_dev *rtwdev); 1328 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev); 1329 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1330 u8 type, u8 cat, u8 class, u8 func, 1331 bool rack, bool dack, u32 len); 1332 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, u8 macid); 1333 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, 1334 struct ieee80211_vif *vif, 1335 struct ieee80211_sta *sta); 1336 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev, 1337 struct rtw89_sta *rtwsta); 1338 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); 1339 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h); 1340 void rtw89_fw_c2h_work(struct work_struct *work); 1341 int rtw89_fw_h2c_vif_maintain(struct rtw89_dev *rtwdev, 1342 struct rtw89_vif *rtwvif, 1343 enum rtw89_upd_mode upd_mode); 1344 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1345 u8 dis_conn); 1346 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp, 1347 bool pause); 1348 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1349 u8 ac, u32 val); 1350 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev); 1351 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi); 1352 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev); 1353 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev); 1354 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev); 1355 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev); 1356 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev, 1357 struct rtw89_fw_h2c_rf_reg_info *info, 1358 u16 len, u8 page); 1359 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, 1360 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, 1361 bool rack, bool dack); 1362 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len); 1363 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev); 1364 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev); 1365 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, u8 macid); 1366 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, bool valid, u8 macid, 1367 struct ieee80211_ampdu_params *params); 1368 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev, 1369 struct rtw89_lps_parm *lps_param); 1370 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(u32 len); 1371 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(u32 len); 1372 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev, 1373 struct rtw89_mac_h2c_info *h2c_info, 1374 struct rtw89_mac_c2h_info *c2h_info); 1375 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable); 1376 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev); 1377 1378 #endif 1379