1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_FW_H__ 6 #define __RTW89_FW_H__ 7 8 #include "core.h" 9 10 enum rtw89_fw_dl_status { 11 RTW89_FWDL_INITIAL_STATE = 0, 12 RTW89_FWDL_FWDL_ONGOING = 1, 13 RTW89_FWDL_CHECKSUM_FAIL = 2, 14 RTW89_FWDL_SECURITY_FAIL = 3, 15 RTW89_FWDL_CV_NOT_MATCH = 4, 16 RTW89_FWDL_RSVD0 = 5, 17 RTW89_FWDL_WCPU_FWDL_RDY = 6, 18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7 19 }; 20 21 #define RTW89_GET_C2H_HDR_FUNC(info) \ 22 u32_get_bits(info, GENMASK(6, 0)) 23 #define RTW89_GET_C2H_HDR_LEN(info) \ 24 u32_get_bits(info, GENMASK(11, 8)) 25 26 #define RTW89_SET_H2CREG_HDR_FUNC(info, val) \ 27 u32p_replace_bits(info, val, GENMASK(6, 0)) 28 #define RTW89_SET_H2CREG_HDR_LEN(info, val) \ 29 u32p_replace_bits(info, val, GENMASK(11, 8)) 30 31 #define RTW89_H2CREG_MAX 4 32 #define RTW89_C2HREG_MAX 4 33 #define RTW89_C2HREG_HDR_LEN 2 34 #define RTW89_H2CREG_HDR_LEN 2 35 #define RTW89_C2H_TIMEOUT 1000000 36 struct rtw89_mac_c2h_info { 37 u8 id; 38 u8 content_len; 39 u32 c2hreg[RTW89_C2HREG_MAX]; 40 }; 41 42 struct rtw89_mac_h2c_info { 43 u8 id; 44 u8 content_len; 45 u32 h2creg[RTW89_H2CREG_MAX]; 46 }; 47 48 enum rtw89_mac_h2c_type { 49 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0, 50 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD, 51 RTW89_FWCMD_H2CREG_FUNC_FWERR, 52 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE, 53 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM, 54 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN 55 }; 56 57 enum rtw89_mac_c2h_type { 58 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0, 59 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT, 60 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG, 61 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP, 62 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT, 63 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF 64 }; 65 66 #define RTW89_GET_C2H_PHYCAP_FUNC(info) \ 67 u32_get_bits(*((const u32 *)(info)), GENMASK(6, 0)) 68 #define RTW89_GET_C2H_PHYCAP_ACK(info) \ 69 u32_get_bits(*((const u32 *)(info)), BIT(7)) 70 #define RTW89_GET_C2H_PHYCAP_LEN(info) \ 71 u32_get_bits(*((const u32 *)(info)), GENMASK(11, 8)) 72 #define RTW89_GET_C2H_PHYCAP_SEQ(info) \ 73 u32_get_bits(*((const u32 *)(info)), GENMASK(15, 12)) 74 #define RTW89_GET_C2H_PHYCAP_RX_NSS(info) \ 75 u32_get_bits(*((const u32 *)(info)), GENMASK(23, 16)) 76 #define RTW89_GET_C2H_PHYCAP_BW(info) \ 77 u32_get_bits(*((const u32 *)(info)), GENMASK(31, 24)) 78 #define RTW89_GET_C2H_PHYCAP_TX_NSS(info) \ 79 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(7, 0)) 80 #define RTW89_GET_C2H_PHYCAP_PROT(info) \ 81 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(15, 8)) 82 #define RTW89_GET_C2H_PHYCAP_NIC(info) \ 83 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(23, 16)) 84 #define RTW89_GET_C2H_PHYCAP_WL_FUNC(info) \ 85 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(31, 24)) 86 #define RTW89_GET_C2H_PHYCAP_HW_TYPE(info) \ 87 u32_get_bits(*((const u32 *)(info) + 2), GENMASK(7, 0)) 88 #define RTW89_GET_C2H_PHYCAP_ANT_TX_NUM(info) \ 89 u32_get_bits(*((const u32 *)(info) + 3), GENMASK(15, 8)) 90 #define RTW89_GET_C2H_PHYCAP_ANT_RX_NUM(info) \ 91 u32_get_bits(*((const u32 *)(info) + 3), GENMASK(23, 16)) 92 93 enum rtw89_fw_c2h_category { 94 RTW89_C2H_CAT_TEST, 95 RTW89_C2H_CAT_MAC, 96 RTW89_C2H_CAT_OUTSRC, 97 }; 98 99 enum rtw89_fw_log_level { 100 RTW89_FW_LOG_LEVEL_OFF, 101 RTW89_FW_LOG_LEVEL_CRT, 102 RTW89_FW_LOG_LEVEL_SER, 103 RTW89_FW_LOG_LEVEL_WARN, 104 RTW89_FW_LOG_LEVEL_LOUD, 105 RTW89_FW_LOG_LEVEL_TR, 106 }; 107 108 enum rtw89_fw_log_path { 109 RTW89_FW_LOG_LEVEL_UART, 110 RTW89_FW_LOG_LEVEL_C2H, 111 RTW89_FW_LOG_LEVEL_SNI, 112 }; 113 114 enum rtw89_fw_log_comp { 115 RTW89_FW_LOG_COMP_VER, 116 RTW89_FW_LOG_COMP_INIT, 117 RTW89_FW_LOG_COMP_TASK, 118 RTW89_FW_LOG_COMP_CNS, 119 RTW89_FW_LOG_COMP_H2C, 120 RTW89_FW_LOG_COMP_C2H, 121 RTW89_FW_LOG_COMP_TX, 122 RTW89_FW_LOG_COMP_RX, 123 RTW89_FW_LOG_COMP_IPSEC, 124 RTW89_FW_LOG_COMP_TIMER, 125 RTW89_FW_LOG_COMP_DBGPKT, 126 RTW89_FW_LOG_COMP_PS, 127 RTW89_FW_LOG_COMP_ERROR, 128 RTW89_FW_LOG_COMP_WOWLAN, 129 RTW89_FW_LOG_COMP_SECURE_BOOT, 130 RTW89_FW_LOG_COMP_BTC, 131 RTW89_FW_LOG_COMP_BB, 132 RTW89_FW_LOG_COMP_TWT, 133 RTW89_FW_LOG_COMP_RF, 134 RTW89_FW_LOG_COMP_MCC = 20, 135 }; 136 137 enum rtw89_pkt_offload_op { 138 RTW89_PKT_OFLD_OP_ADD, 139 RTW89_PKT_OFLD_OP_DEL, 140 RTW89_PKT_OFLD_OP_READ, 141 }; 142 143 enum rtw89_scanofld_notify_reason { 144 RTW89_SCAN_DWELL_NOTIFY, 145 RTW89_SCAN_PRE_TX_NOTIFY, 146 RTW89_SCAN_POST_TX_NOTIFY, 147 RTW89_SCAN_ENTER_CH_NOTIFY, 148 RTW89_SCAN_LEAVE_CH_NOTIFY, 149 RTW89_SCAN_END_SCAN_NOTIFY, 150 }; 151 152 enum rtw89_chan_type { 153 RTW89_CHAN_OPERATE = 0, 154 RTW89_CHAN_ACTIVE, 155 RTW89_CHAN_DFS, 156 }; 157 158 enum rtw89_p2pps_action { 159 RTW89_P2P_ACT_INIT = 0, 160 RTW89_P2P_ACT_UPDATE = 1, 161 RTW89_P2P_ACT_REMOVE = 2, 162 RTW89_P2P_ACT_TERMINATE = 3, 163 }; 164 165 #define FWDL_SECTION_MAX_NUM 10 166 #define FWDL_SECTION_CHKSUM_LEN 8 167 #define FWDL_SECTION_PER_PKT_LEN 2020 168 169 struct rtw89_fw_hdr_section_info { 170 u8 redl; 171 const u8 *addr; 172 u32 len; 173 u32 dladdr; 174 }; 175 176 struct rtw89_fw_bin_info { 177 u8 section_num; 178 u32 hdr_len; 179 bool dynamic_hdr_en; 180 u32 dynamic_hdr_len; 181 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM]; 182 }; 183 184 struct rtw89_fw_macid_pause_grp { 185 __le32 pause_grp[4]; 186 __le32 mask_grp[4]; 187 } __packed; 188 189 struct rtw89_h2creg_sch_tx_en { 190 u8 func:7; 191 u8 ack:1; 192 u8 total_len:4; 193 u8 seq_num:4; 194 u16 tx_en:16; 195 u16 mask:16; 196 u8 band:1; 197 u16 rsvd:15; 198 } __packed; 199 200 #define RTW89_H2C_MAX_SIZE 2048 201 #define RTW89_CHANNEL_TIME 45 202 #define RTW89_CHANNEL_TIME_6G 20 203 #define RTW89_DFS_CHAN_TIME 105 204 #define RTW89_OFF_CHAN_TIME 100 205 #define RTW89_DWELL_TIME 20 206 #define RTW89_SCAN_WIDTH 0 207 #define RTW89_SCANOFLD_MAX_SSID 8 208 #define RTW89_SCANOFLD_MAX_IE_LEN 512 209 #define RTW89_SCANOFLD_PKT_NONE 0xFF 210 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F 211 #define RTW89_MAC_CHINFO_SIZE 24 212 #define RTW89_SCAN_LIST_GUARD 4 213 #define RTW89_SCAN_LIST_LIMIT \ 214 ((RTW89_H2C_MAX_SIZE / RTW89_MAC_CHINFO_SIZE) - RTW89_SCAN_LIST_GUARD) 215 216 struct rtw89_mac_chinfo { 217 u8 period; 218 u8 dwell_time; 219 u8 central_ch; 220 u8 pri_ch; 221 u8 bw:3; 222 u8 notify_action:5; 223 u8 num_pkt:4; 224 u8 tx_pkt:1; 225 u8 pause_data:1; 226 u8 ch_band:2; 227 u8 probe_id; 228 u8 dfs_ch:1; 229 u8 tx_null:1; 230 u8 rand_seq_num:1; 231 u8 cfg_tx_pwr:1; 232 u8 rsvd0: 4; 233 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID]; 234 u16 tx_pwr_idx; 235 u8 rsvd1; 236 struct list_head list; 237 }; 238 239 struct rtw89_scan_option { 240 bool enable; 241 bool target_ch_mode; 242 }; 243 244 struct rtw89_pktofld_info { 245 struct list_head list; 246 u8 id; 247 }; 248 249 static inline void RTW89_SET_FWCMD_RA_IS_DIS(void *cmd, u32 val) 250 { 251 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(0)); 252 } 253 254 static inline void RTW89_SET_FWCMD_RA_MODE(void *cmd, u32 val) 255 { 256 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(5, 1)); 257 } 258 259 static inline void RTW89_SET_FWCMD_RA_BW_CAP(void *cmd, u32 val) 260 { 261 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 6)); 262 } 263 264 static inline void RTW89_SET_FWCMD_RA_MACID(void *cmd, u32 val) 265 { 266 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); 267 } 268 269 static inline void RTW89_SET_FWCMD_RA_DCM(void *cmd, u32 val) 270 { 271 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(16)); 272 } 273 274 static inline void RTW89_SET_FWCMD_RA_ER(void *cmd, u32 val) 275 { 276 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(17)); 277 } 278 279 static inline void RTW89_SET_FWCMD_RA_INIT_RATE_LV(void *cmd, u32 val) 280 { 281 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(19, 18)); 282 } 283 284 static inline void RTW89_SET_FWCMD_RA_UPD_ALL(void *cmd, u32 val) 285 { 286 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(20)); 287 } 288 289 static inline void RTW89_SET_FWCMD_RA_SGI(void *cmd, u32 val) 290 { 291 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(21)); 292 } 293 294 static inline void RTW89_SET_FWCMD_RA_LDPC(void *cmd, u32 val) 295 { 296 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(22)); 297 } 298 299 static inline void RTW89_SET_FWCMD_RA_STBC(void *cmd, u32 val) 300 { 301 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(23)); 302 } 303 304 static inline void RTW89_SET_FWCMD_RA_SS_NUM(void *cmd, u32 val) 305 { 306 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(26, 24)); 307 } 308 309 static inline void RTW89_SET_FWCMD_RA_GILTF(void *cmd, u32 val) 310 { 311 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(29, 27)); 312 } 313 314 static inline void RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(void *cmd, u32 val) 315 { 316 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(30)); 317 } 318 319 static inline void RTW89_SET_FWCMD_RA_UPD_MASK(void *cmd, u32 val) 320 { 321 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(31)); 322 } 323 324 static inline void RTW89_SET_FWCMD_RA_MASK_0(void *cmd, u32 val) 325 { 326 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(7, 0)); 327 } 328 329 static inline void RTW89_SET_FWCMD_RA_MASK_1(void *cmd, u32 val) 330 { 331 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(15, 8)); 332 } 333 334 static inline void RTW89_SET_FWCMD_RA_MASK_2(void *cmd, u32 val) 335 { 336 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(23, 16)); 337 } 338 339 static inline void RTW89_SET_FWCMD_RA_MASK_3(void *cmd, u32 val) 340 { 341 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 24)); 342 } 343 344 static inline void RTW89_SET_FWCMD_RA_MASK_4(void *cmd, u32 val) 345 { 346 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(7, 0)); 347 } 348 349 static inline void RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(void *cmd, u32 val) 350 { 351 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, BIT(31)); 352 } 353 354 static inline void RTW89_SET_FWCMD_RA_BAND_NUM(void *cmd, u32 val) 355 { 356 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(7, 0)); 357 } 358 359 static inline void RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(void *cmd, u32 val) 360 { 361 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(8)); 362 } 363 364 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(void *cmd, u32 val) 365 { 366 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(9)); 367 } 368 369 static inline void RTW89_SET_FWCMD_RA_CR_TBL_SEL(void *cmd, u32 val) 370 { 371 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(10)); 372 } 373 374 static inline void RTW89_SET_FWCMD_RA_FIX_GILTF_EN(void *cmd, u32 val) 375 { 376 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(11)); 377 } 378 379 static inline void RTW89_SET_FWCMD_RA_FIX_GILTF(void *cmd, u32 val) 380 { 381 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(14, 12)); 382 } 383 384 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(void *cmd, u32 val) 385 { 386 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(23, 16)); 387 } 388 389 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(void *cmd, u32 val) 390 { 391 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(25, 24)); 392 } 393 394 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(void *cmd, u32 val) 395 { 396 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(28, 26)); 397 } 398 399 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_BW(void *cmd, u32 val) 400 { 401 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 29)); 402 } 403 404 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val) 405 { 406 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)); 407 } 408 409 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val) 410 { 411 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); 412 } 413 414 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val) 415 { 416 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)); 417 } 418 419 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val) 420 { 421 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0)); 422 } 423 424 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val) 425 { 426 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4)); 427 } 428 429 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val) 430 { 431 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5)); 432 } 433 434 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val) 435 { 436 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0)); 437 } 438 439 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val) 440 { 441 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0)); 442 } 443 444 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val) 445 { 446 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0)); 447 } 448 449 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val) 450 { 451 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0)); 452 } 453 454 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val) 455 { 456 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0)); 457 } 458 459 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val) 460 { 461 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3)); 462 } 463 464 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val) 465 { 466 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4)); 467 } 468 469 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val) 470 { 471 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5)); 472 } 473 474 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val) 475 { 476 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0)); 477 } 478 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16) 479 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12) 480 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8) 481 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0) 482 483 #define GET_FWSECTION_HDR_SEC_SIZE(fwhdr) \ 484 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 0)) 485 #define GET_FWSECTION_HDR_CHECKSUM(fwhdr) \ 486 le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(28)) 487 #define GET_FWSECTION_HDR_REDL(fwhdr) \ 488 le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(29)) 489 #define GET_FWSECTION_HDR_DL_ADDR(fwhdr) \ 490 le32_get_bits(*((const __le32 *)(fwhdr)), GENMASK(31, 0)) 491 492 #define GET_FW_HDR_MAJOR_VERSION(fwhdr) \ 493 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(7, 0)) 494 #define GET_FW_HDR_MINOR_VERSION(fwhdr) \ 495 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(15, 8)) 496 #define GET_FW_HDR_SUBVERSION(fwhdr) \ 497 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 16)) 498 #define GET_FW_HDR_SUBINDEX(fwhdr) \ 499 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(31, 24)) 500 #define GET_FW_HDR_LEN(fwhdr) \ 501 le32_get_bits(*((const __le32 *)(fwhdr) + 3), GENMASK(23, 16)) 502 #define GET_FW_HDR_MONTH(fwhdr) \ 503 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(7, 0)) 504 #define GET_FW_HDR_DATE(fwhdr) \ 505 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(15, 8)) 506 #define GET_FW_HDR_HOUR(fwhdr) \ 507 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(23, 16)) 508 #define GET_FW_HDR_MIN(fwhdr) \ 509 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(31, 24)) 510 #define GET_FW_HDR_YEAR(fwhdr) \ 511 le32_get_bits(*((const __le32 *)(fwhdr) + 5), GENMASK(31, 0)) 512 #define GET_FW_HDR_SEC_NUM(fwhdr) \ 513 le32_get_bits(*((const __le32 *)(fwhdr) + 6), GENMASK(15, 8)) 514 #define GET_FW_HDR_DYN_HDR(fwhdr) \ 515 le32_get_bits(*((const __le32 *)(fwhdr) + 7), BIT(16)) 516 #define GET_FW_HDR_CMD_VERSERION(fwhdr) \ 517 le32_get_bits(*((const __le32 *)(fwhdr) + 7), GENMASK(31, 24)) 518 519 #define GET_FW_DYNHDR_LEN(fwdynhdr) \ 520 le32_get_bits(*((const __le32 *)(fwdynhdr)), GENMASK(31, 0)) 521 #define GET_FW_DYNHDR_COUNT(fwdynhdr) \ 522 le32_get_bits(*((const __le32 *)(fwdynhdr) + 1), GENMASK(31, 0)) 523 524 static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val) 525 { 526 le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0)); 527 } 528 529 static inline void SET_CTRL_INFO_MACID(void *table, u32 val) 530 { 531 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)); 532 } 533 534 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val) 535 { 536 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); 537 } 538 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0) 539 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val) 540 { 541 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0)); 542 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE, 543 GENMASK(8, 0)); 544 } 545 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0) 546 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val) 547 { 548 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9)); 549 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP, 550 BIT(9)); 551 } 552 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0) 553 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val) 554 { 555 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10)); 556 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW, 557 GENMASK(11, 10)); 558 } 559 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0) 560 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val) 561 { 562 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12)); 563 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF, 564 GENMASK(14, 12)); 565 } 566 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0) 567 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val) 568 { 569 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); 570 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX, 571 BIT(15)); 572 } 573 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0) 574 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val) 575 { 576 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16)); 577 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL, 578 GENMASK(19, 16)); 579 } 580 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0) 581 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val) 582 { 583 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20)); 584 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN, 585 BIT(20)); 586 } 587 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0) 588 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val) 589 { 590 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21)); 591 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN, 592 BIT(21)); 593 } 594 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0) 595 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val) 596 { 597 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22)); 598 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN, 599 BIT(22)); 600 } 601 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0) 602 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val) 603 { 604 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23)); 605 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN, 606 BIT(23)); 607 } 608 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0) 609 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val) 610 { 611 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25)); 612 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB, 613 BIT(25)); 614 } 615 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0) 616 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val) 617 { 618 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26)); 619 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB, 620 BIT(26)); 621 } 622 #define SET_CMC_TBL_MASK_TRYRATE BIT(0) 623 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val) 624 { 625 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27)); 626 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE, 627 BIT(27)); 628 } 629 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0) 630 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val) 631 { 632 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28)); 633 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY, 634 GENMASK(31, 28)); 635 } 636 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0) 637 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val) 638 { 639 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0)); 640 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE, 641 GENMASK(8, 0)); 642 } 643 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0) 644 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val) 645 { 646 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9)); 647 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL, 648 BIT(9)); 649 } 650 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0) 651 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val) 652 { 653 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10)); 654 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL, 655 BIT(10)); 656 } 657 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0) 658 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val) 659 { 660 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11)); 661 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL, 662 BIT(11)); 663 } 664 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0) 665 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val) 666 { 667 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12)); 668 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT, 669 GENMASK(15, 12)); 670 } 671 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0) 672 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val) 673 { 674 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16)); 675 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE, 676 GENMASK(24, 16)); 677 } 678 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0) 679 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val) 680 { 681 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27)); 682 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC, 683 BIT(27)); 684 } 685 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0) 686 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val) 687 { 688 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28)); 689 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE, 690 GENMASK(31, 28)); 691 } 692 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0) 693 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val) 694 { 695 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0)); 696 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT, 697 GENMASK(5, 0)); 698 } 699 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0) 700 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val) 701 { 702 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6)); 703 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL, 704 BIT(6)); 705 } 706 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0) 707 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val) 708 { 709 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7)); 710 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL, 711 BIT(7)); 712 } 713 #define SET_CMC_TBL_MASK_RTS_EN BIT(0) 714 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val) 715 { 716 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8)); 717 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN, 718 BIT(8)); 719 } 720 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0) 721 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val) 722 { 723 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9)); 724 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN, 725 BIT(9)); 726 } 727 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0) 728 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val) 729 { 730 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10)); 731 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS, 732 GENMASK(11, 10)); 733 } 734 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0) 735 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val) 736 { 737 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12)); 738 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN, 739 BIT(12)); 740 } 741 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0) 742 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val) 743 { 744 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13)); 745 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE, 746 GENMASK(14, 13)); 747 } 748 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0) 749 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val) 750 { 751 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16)); 752 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN, 753 GENMASK(26, 16)); 754 } 755 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0) 756 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val) 757 { 758 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); 759 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS, 760 BIT(27)); 761 } 762 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0) 763 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val) 764 { 765 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28)); 766 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME, 767 GENMASK(31, 28)); 768 } 769 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0) 770 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val) 771 { 772 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0)); 773 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM, 774 GENMASK(7, 0)); 775 } 776 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0) 777 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val) 778 { 779 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8)); 780 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP, 781 GENMASK(9, 8)); 782 } 783 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0) 784 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val) 785 { 786 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16)); 787 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL, 788 GENMASK(18, 16)); 789 } 790 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0) 791 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val) 792 { 793 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19)); 794 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL, 795 GENMASK(21, 19)); 796 } 797 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0) 798 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val) 799 { 800 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22)); 801 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL, 802 GENMASK(24, 22)); 803 } 804 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0) 805 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val) 806 { 807 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25)); 808 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL, 809 GENMASK(27, 25)); 810 } 811 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0) 812 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val) 813 { 814 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28)); 815 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE, 816 GENMASK(31, 28)); 817 } 818 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0) 819 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val) 820 { 821 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0)); 822 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID, 823 GENMASK(2, 0)); 824 } 825 #define SET_CMC_TBL_MASK_BMC BIT(0) 826 static inline void SET_CMC_TBL_BMC(void *table, u32 val) 827 { 828 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3)); 829 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC, 830 BIT(3)); 831 } 832 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0) 833 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val) 834 { 835 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4)); 836 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID, 837 GENMASK(7, 4)); 838 } 839 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0) 840 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val) 841 { 842 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); 843 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR, 844 BIT(8)); 845 } 846 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0) 847 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val) 848 { 849 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9)); 850 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE, 851 GENMASK(11, 9)); 852 } 853 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0) 854 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val) 855 { 856 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12)); 857 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM, 858 BIT(12)); 859 } 860 #define SET_CMC_TBL_MASK_DATA_ER BIT(0) 861 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val) 862 { 863 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13)); 864 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER, 865 BIT(13)); 866 } 867 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0) 868 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val) 869 { 870 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14)); 871 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC, 872 BIT(14)); 873 } 874 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0) 875 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val) 876 { 877 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); 878 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC, 879 BIT(15)); 880 } 881 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0) 882 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val) 883 { 884 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16)); 885 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR, 886 BIT(16)); 887 } 888 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0) 889 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val) 890 { 891 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17)); 892 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH, 893 BIT(17)); 894 } 895 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0) 896 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val) 897 { 898 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18)); 899 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR, 900 BIT(18)); 901 } 902 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0) 903 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val) 904 { 905 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19)); 906 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS, 907 BIT(19)); 908 } 909 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0) 910 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val) 911 { 912 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20)); 913 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER, 914 BIT(20)); 915 } 916 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0) 917 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val) 918 { 919 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21)); 920 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN, 921 BIT(21)); 922 } 923 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0) 924 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val) 925 { 926 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27)); 927 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD, 928 BIT(27)); 929 } 930 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0) 931 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val) 932 { 933 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28)); 934 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT, 935 GENMASK(31, 28)); 936 } 937 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0) 938 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val) 939 { 940 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0)); 941 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE, 942 GENMASK(8, 0)); 943 } 944 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0) 945 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val) 946 { 947 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12)); 948 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT, 949 BIT(12)); 950 } 951 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0) 952 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val) 953 { 954 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13)); 955 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT, 956 BIT(13)); 957 } 958 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0) 959 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val) 960 { 961 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16)); 962 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN, 963 GENMASK(19, 16)); 964 } 965 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0) 966 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val) 967 { 968 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20)); 969 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A, 970 GENMASK(21, 20)); 971 } 972 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0) 973 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val) 974 { 975 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22)); 976 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B, 977 GENMASK(23, 22)); 978 } 979 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0) 980 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val) 981 { 982 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24)); 983 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C, 984 GENMASK(25, 24)); 985 } 986 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0) 987 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val) 988 { 989 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26)); 990 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D, 991 GENMASK(27, 26)); 992 } 993 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0) 994 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val) 995 { 996 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28)); 997 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A, 998 BIT(28)); 999 } 1000 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0) 1001 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val) 1002 { 1003 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29)); 1004 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B, 1005 BIT(29)); 1006 } 1007 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0) 1008 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val) 1009 { 1010 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30)); 1011 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C, 1012 BIT(30)); 1013 } 1014 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0) 1015 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val) 1016 { 1017 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31)); 1018 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D, 1019 BIT(31)); 1020 } 1021 1022 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0) 1023 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val) 1024 { 1025 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0)); 1026 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1027 GENMASK(1, 0)); 1028 } 1029 1030 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val) 1031 { 1032 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2)); 1033 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1034 GENMASK(3, 2)); 1035 } 1036 1037 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val) 1038 { 1039 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4)); 1040 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1041 GENMASK(5, 4)); 1042 } 1043 1044 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val) 1045 { 1046 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6)); 1047 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1048 GENMASK(7, 6)); 1049 } 1050 1051 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0) 1052 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val) 1053 { 1054 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); 1055 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX, 1056 GENMASK(7, 0)); 1057 } 1058 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0) 1059 static inline void SET_CMC_TBL_PAID(void *table, u32 val) 1060 { 1061 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8)); 1062 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID, 1063 GENMASK(16, 8)); 1064 } 1065 #define SET_CMC_TBL_MASK_ULDL BIT(0) 1066 static inline void SET_CMC_TBL_ULDL(void *table, u32 val) 1067 { 1068 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17)); 1069 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL, 1070 BIT(17)); 1071 } 1072 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0) 1073 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val) 1074 { 1075 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18)); 1076 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL, 1077 GENMASK(19, 18)); 1078 } 1079 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val) 1080 { 1081 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20)); 1082 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1083 GENMASK(21, 20)); 1084 } 1085 1086 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val) 1087 { 1088 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22)); 1089 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1090 GENMASK(23, 22)); 1091 } 1092 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0) 1093 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val) 1094 { 1095 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24)); 1096 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE, 1097 GENMASK(27, 24)); 1098 } 1099 1100 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val) 1101 { 1102 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30)); 1103 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1104 GENMASK(31, 30)); 1105 } 1106 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0) 1107 static inline void SET_CMC_TBL_NC(void *table, u32 val) 1108 { 1109 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0)); 1110 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC, 1111 GENMASK(2, 0)); 1112 } 1113 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0) 1114 static inline void SET_CMC_TBL_NR(void *table, u32 val) 1115 { 1116 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3)); 1117 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR, 1118 GENMASK(5, 3)); 1119 } 1120 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0) 1121 static inline void SET_CMC_TBL_NG(void *table, u32 val) 1122 { 1123 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6)); 1124 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG, 1125 GENMASK(7, 6)); 1126 } 1127 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0) 1128 static inline void SET_CMC_TBL_CB(void *table, u32 val) 1129 { 1130 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8)); 1131 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB, 1132 GENMASK(9, 8)); 1133 } 1134 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0) 1135 static inline void SET_CMC_TBL_CS(void *table, u32 val) 1136 { 1137 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10)); 1138 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS, 1139 GENMASK(11, 10)); 1140 } 1141 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0) 1142 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val) 1143 { 1144 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12)); 1145 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN, 1146 BIT(12)); 1147 } 1148 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0) 1149 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val) 1150 { 1151 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13)); 1152 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN, 1153 BIT(13)); 1154 } 1155 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0) 1156 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val) 1157 { 1158 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14)); 1159 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN, 1160 BIT(14)); 1161 } 1162 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0) 1163 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val) 1164 { 1165 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15)); 1166 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN, 1167 BIT(15)); 1168 } 1169 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0) 1170 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val) 1171 { 1172 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16)); 1173 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE, 1174 GENMASK(24, 16)); 1175 } 1176 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0) 1177 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val) 1178 { 1179 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25)); 1180 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF, 1181 GENMASK(27, 25)); 1182 } 1183 1184 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val) 1185 { 1186 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28)); 1187 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1188 GENMASK(29, 28)); 1189 } 1190 1191 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0) 1192 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val) 1193 { 1194 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30)); 1195 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW, 1196 GENMASK(31, 30)); 1197 } 1198 1199 static inline void SET_DCTL_MACID_V1(void *table, u32 val) 1200 { 1201 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)); 1202 } 1203 1204 static inline void SET_DCTL_OPERATION_V1(void *table, u32 val) 1205 { 1206 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); 1207 } 1208 1209 #define SET_DCTL_MASK_QOS_FIELD_V1 GENMASK(7, 0) 1210 static inline void SET_DCTL_QOS_FIELD_V1(void *table, u32 val) 1211 { 1212 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(7, 0)); 1213 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_FIELD_V1, 1214 GENMASK(7, 0)); 1215 } 1216 1217 #define SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID GENMASK(6, 0) 1218 static inline void SET_DCTL_HW_EXSEQ_MACID_V1(void *table, u32 val) 1219 { 1220 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 8)); 1221 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID, 1222 GENMASK(14, 8)); 1223 } 1224 1225 #define SET_DCTL_MASK_QOS_DATA BIT(0) 1226 static inline void SET_DCTL_QOS_DATA_V1(void *table, u32 val) 1227 { 1228 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); 1229 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_DATA, 1230 BIT(15)); 1231 } 1232 1233 #define SET_DCTL_MASK_AES_IV_L GENMASK(15, 0) 1234 static inline void SET_DCTL_AES_IV_L_V1(void *table, u32 val) 1235 { 1236 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 16)); 1237 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_AES_IV_L, 1238 GENMASK(31, 16)); 1239 } 1240 1241 #define SET_DCTL_MASK_AES_IV_H GENMASK(31, 0) 1242 static inline void SET_DCTL_AES_IV_H_V1(void *table, u32 val) 1243 { 1244 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 0)); 1245 le32p_replace_bits((__le32 *)(table) + 10, SET_DCTL_MASK_AES_IV_H, 1246 GENMASK(31, 0)); 1247 } 1248 1249 #define SET_DCTL_MASK_SEQ0 GENMASK(11, 0) 1250 static inline void SET_DCTL_SEQ0_V1(void *table, u32 val) 1251 { 1252 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 0)); 1253 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ0, 1254 GENMASK(11, 0)); 1255 } 1256 1257 #define SET_DCTL_MASK_SEQ1 GENMASK(11, 0) 1258 static inline void SET_DCTL_SEQ1_V1(void *table, u32 val) 1259 { 1260 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(23, 12)); 1261 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ1, 1262 GENMASK(23, 12)); 1263 } 1264 1265 #define SET_DCTL_MASK_AMSDU_MAX_LEN GENMASK(2, 0) 1266 static inline void SET_DCTL_AMSDU_MAX_LEN_V1(void *table, u32 val) 1267 { 1268 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 24)); 1269 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_AMSDU_MAX_LEN, 1270 GENMASK(26, 24)); 1271 } 1272 1273 #define SET_DCTL_MASK_STA_AMSDU_EN BIT(0) 1274 static inline void SET_DCTL_STA_AMSDU_EN_V1(void *table, u32 val) 1275 { 1276 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); 1277 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_STA_AMSDU_EN, 1278 BIT(27)); 1279 } 1280 1281 #define SET_DCTL_MASK_CHKSUM_OFLD_EN BIT(0) 1282 static inline void SET_DCTL_CHKSUM_OFLD_EN_V1(void *table, u32 val) 1283 { 1284 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(28)); 1285 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_CHKSUM_OFLD_EN, 1286 BIT(28)); 1287 } 1288 1289 #define SET_DCTL_MASK_WITH_LLC BIT(0) 1290 static inline void SET_DCTL_WITH_LLC_V1(void *table, u32 val) 1291 { 1292 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(29)); 1293 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_WITH_LLC, 1294 BIT(29)); 1295 } 1296 1297 #define SET_DCTL_MASK_SEQ2 GENMASK(11, 0) 1298 static inline void SET_DCTL_SEQ2_V1(void *table, u32 val) 1299 { 1300 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(11, 0)); 1301 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ2, 1302 GENMASK(11, 0)); 1303 } 1304 1305 #define SET_DCTL_MASK_SEQ3 GENMASK(11, 0) 1306 static inline void SET_DCTL_SEQ3_V1(void *table, u32 val) 1307 { 1308 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(23, 12)); 1309 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ3, 1310 GENMASK(23, 12)); 1311 } 1312 1313 #define SET_DCTL_MASK_TGT_IND GENMASK(3, 0) 1314 static inline void SET_DCTL_TGT_IND_V1(void *table, u32 val) 1315 { 1316 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 24)); 1317 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND, 1318 GENMASK(27, 24)); 1319 } 1320 1321 #define SET_DCTL_MASK_TGT_IND_EN BIT(0) 1322 static inline void SET_DCTL_TGT_IND_EN_V1(void *table, u32 val) 1323 { 1324 le32p_replace_bits((__le32 *)(table) + 4, val, BIT(28)); 1325 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND_EN, 1326 BIT(28)); 1327 } 1328 1329 #define SET_DCTL_MASK_HTC_LB GENMASK(2, 0) 1330 static inline void SET_DCTL_HTC_LB_V1(void *table, u32 val) 1331 { 1332 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 29)); 1333 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_HTC_LB, 1334 GENMASK(31, 29)); 1335 } 1336 1337 #define SET_DCTL_MASK_MHDR_LEN GENMASK(4, 0) 1338 static inline void SET_DCTL_MHDR_LEN_V1(void *table, u32 val) 1339 { 1340 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(4, 0)); 1341 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_MHDR_LEN, 1342 GENMASK(4, 0)); 1343 } 1344 1345 #define SET_DCTL_MASK_VLAN_TAG_VALID BIT(0) 1346 static inline void SET_DCTL_VLAN_TAG_VALID_V1(void *table, u32 val) 1347 { 1348 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(5)); 1349 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_VALID, 1350 BIT(5)); 1351 } 1352 1353 #define SET_DCTL_MASK_VLAN_TAG_SEL GENMASK(1, 0) 1354 static inline void SET_DCTL_VLAN_TAG_SEL_V1(void *table, u32 val) 1355 { 1356 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 6)); 1357 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_SEL, 1358 GENMASK(7, 6)); 1359 } 1360 1361 #define SET_DCTL_MASK_HTC_ORDER BIT(0) 1362 static inline void SET_DCTL_HTC_ORDER_V1(void *table, u32 val) 1363 { 1364 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); 1365 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_HTC_ORDER, 1366 BIT(8)); 1367 } 1368 1369 #define SET_DCTL_MASK_SEC_KEY_ID GENMASK(1, 0) 1370 static inline void SET_DCTL_SEC_KEY_ID_V1(void *table, u32 val) 1371 { 1372 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(10, 9)); 1373 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_KEY_ID, 1374 GENMASK(10, 9)); 1375 } 1376 1377 #define SET_DCTL_MASK_WAPI BIT(0) 1378 static inline void SET_DCTL_WAPI_V1(void *table, u32 val) 1379 { 1380 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); 1381 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_WAPI, 1382 BIT(15)); 1383 } 1384 1385 #define SET_DCTL_MASK_SEC_ENT_MODE GENMASK(1, 0) 1386 static inline void SET_DCTL_SEC_ENT_MODE_V1(void *table, u32 val) 1387 { 1388 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(17, 16)); 1389 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENT_MODE, 1390 GENMASK(17, 16)); 1391 } 1392 1393 #define SET_DCTL_MASK_SEC_ENTX_KEYID GENMASK(1, 0) 1394 static inline void SET_DCTL_SEC_ENT0_KEYID_V1(void *table, u32 val) 1395 { 1396 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(19, 18)); 1397 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1398 GENMASK(19, 18)); 1399 } 1400 1401 static inline void SET_DCTL_SEC_ENT1_KEYID_V1(void *table, u32 val) 1402 { 1403 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(21, 20)); 1404 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1405 GENMASK(21, 20)); 1406 } 1407 1408 static inline void SET_DCTL_SEC_ENT2_KEYID_V1(void *table, u32 val) 1409 { 1410 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(23, 22)); 1411 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1412 GENMASK(23, 22)); 1413 } 1414 1415 static inline void SET_DCTL_SEC_ENT3_KEYID_V1(void *table, u32 val) 1416 { 1417 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(25, 24)); 1418 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1419 GENMASK(25, 24)); 1420 } 1421 1422 static inline void SET_DCTL_SEC_ENT4_KEYID_V1(void *table, u32 val) 1423 { 1424 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(27, 26)); 1425 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1426 GENMASK(27, 26)); 1427 } 1428 1429 static inline void SET_DCTL_SEC_ENT5_KEYID_V1(void *table, u32 val) 1430 { 1431 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(29, 28)); 1432 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1433 GENMASK(29, 28)); 1434 } 1435 1436 static inline void SET_DCTL_SEC_ENT6_KEYID_V1(void *table, u32 val) 1437 { 1438 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 30)); 1439 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1440 GENMASK(31, 30)); 1441 } 1442 1443 #define SET_DCTL_MASK_SEC_ENT_VALID GENMASK(7, 0) 1444 static inline void SET_DCTL_SEC_ENT_VALID_V1(void *table, u32 val) 1445 { 1446 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(7, 0)); 1447 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENT_VALID, 1448 GENMASK(7, 0)); 1449 } 1450 1451 #define SET_DCTL_MASK_SEC_ENTX GENMASK(7, 0) 1452 static inline void SET_DCTL_SEC_ENT0_V1(void *table, u32 val) 1453 { 1454 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(15, 8)); 1455 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1456 GENMASK(15, 8)); 1457 } 1458 1459 static inline void SET_DCTL_SEC_ENT1_V1(void *table, u32 val) 1460 { 1461 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 16)); 1462 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1463 GENMASK(23, 16)); 1464 } 1465 1466 static inline void SET_DCTL_SEC_ENT2_V1(void *table, u32 val) 1467 { 1468 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(31, 24)); 1469 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1470 GENMASK(31, 24)); 1471 } 1472 1473 static inline void SET_DCTL_SEC_ENT3_V1(void *table, u32 val) 1474 { 1475 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); 1476 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1477 GENMASK(7, 0)); 1478 } 1479 1480 static inline void SET_DCTL_SEC_ENT4_V1(void *table, u32 val) 1481 { 1482 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(15, 8)); 1483 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1484 GENMASK(15, 8)); 1485 } 1486 1487 static inline void SET_DCTL_SEC_ENT5_V1(void *table, u32 val) 1488 { 1489 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 16)); 1490 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1491 GENMASK(23, 16)); 1492 } 1493 1494 static inline void SET_DCTL_SEC_ENT6_V1(void *table, u32 val) 1495 { 1496 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 24)); 1497 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1498 GENMASK(31, 24)); 1499 } 1500 1501 static inline void SET_BCN_UPD_PORT(void *h2c, u32 val) 1502 { 1503 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1504 } 1505 1506 static inline void SET_BCN_UPD_MBSSID(void *h2c, u32 val) 1507 { 1508 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1509 } 1510 1511 static inline void SET_BCN_UPD_BAND(void *h2c, u32 val) 1512 { 1513 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1514 } 1515 1516 static inline void SET_BCN_UPD_GRP_IE_OFST(void *h2c, u32 val) 1517 { 1518 le32p_replace_bits((__le32 *)h2c, (val - 24) | BIT(7), GENMASK(31, 24)); 1519 } 1520 1521 static inline void SET_BCN_UPD_MACID(void *h2c, u32 val) 1522 { 1523 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1524 } 1525 1526 static inline void SET_BCN_UPD_SSN_SEL(void *h2c, u32 val) 1527 { 1528 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(9, 8)); 1529 } 1530 1531 static inline void SET_BCN_UPD_SSN_MODE(void *h2c, u32 val) 1532 { 1533 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(11, 10)); 1534 } 1535 1536 static inline void SET_BCN_UPD_RATE(void *h2c, u32 val) 1537 { 1538 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(20, 12)); 1539 } 1540 1541 static inline void SET_BCN_UPD_TXPWR(void *h2c, u32 val) 1542 { 1543 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(23, 21)); 1544 } 1545 1546 static inline void SET_BCN_UPD_TXINFO_CTRL_EN(void *h2c, u32 val) 1547 { 1548 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(0)); 1549 } 1550 1551 static inline void SET_BCN_UPD_NTX_PATH_EN(void *h2c, u32 val) 1552 { 1553 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(4, 1)); 1554 } 1555 1556 static inline void SET_BCN_UPD_PATH_MAP_A(void *h2c, u32 val) 1557 { 1558 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(6, 5)); 1559 } 1560 1561 static inline void SET_BCN_UPD_PATH_MAP_B(void *h2c, u32 val) 1562 { 1563 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(8, 7)); 1564 } 1565 1566 static inline void SET_BCN_UPD_PATH_MAP_C(void *h2c, u32 val) 1567 { 1568 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(10, 9)); 1569 } 1570 1571 static inline void SET_BCN_UPD_PATH_MAP_D(void *h2c, u32 val) 1572 { 1573 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(12, 11)); 1574 } 1575 1576 static inline void SET_BCN_UPD_PATH_ANTSEL_A(void *h2c, u32 val) 1577 { 1578 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(13)); 1579 } 1580 1581 static inline void SET_BCN_UPD_PATH_ANTSEL_B(void *h2c, u32 val) 1582 { 1583 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(14)); 1584 } 1585 1586 static inline void SET_BCN_UPD_PATH_ANTSEL_C(void *h2c, u32 val) 1587 { 1588 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(15)); 1589 } 1590 1591 static inline void SET_BCN_UPD_PATH_ANTSEL_D(void *h2c, u32 val) 1592 { 1593 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(16)); 1594 } 1595 1596 static inline void SET_BCN_UPD_CSA_OFST(void *h2c, u32 val) 1597 { 1598 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 17)); 1599 } 1600 1601 static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val) 1602 { 1603 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1604 } 1605 1606 static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val) 1607 { 1608 le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8)); 1609 } 1610 1611 static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val) 1612 { 1613 le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10)); 1614 } 1615 1616 static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val) 1617 { 1618 le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13)); 1619 } 1620 1621 static inline void SET_JOININFO_MACID(void *h2c, u32 val) 1622 { 1623 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1624 } 1625 1626 static inline void SET_JOININFO_OP(void *h2c, u32 val) 1627 { 1628 le32p_replace_bits((__le32 *)h2c, val, BIT(8)); 1629 } 1630 1631 static inline void SET_JOININFO_BAND(void *h2c, u32 val) 1632 { 1633 le32p_replace_bits((__le32 *)h2c, val, BIT(9)); 1634 } 1635 1636 static inline void SET_JOININFO_WMM(void *h2c, u32 val) 1637 { 1638 le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10)); 1639 } 1640 1641 static inline void SET_JOININFO_TGR(void *h2c, u32 val) 1642 { 1643 le32p_replace_bits((__le32 *)h2c, val, BIT(12)); 1644 } 1645 1646 static inline void SET_JOININFO_ISHESTA(void *h2c, u32 val) 1647 { 1648 le32p_replace_bits((__le32 *)h2c, val, BIT(13)); 1649 } 1650 1651 static inline void SET_JOININFO_DLBW(void *h2c, u32 val) 1652 { 1653 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14)); 1654 } 1655 1656 static inline void SET_JOININFO_TF_MAC_PAD(void *h2c, u32 val) 1657 { 1658 le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16)); 1659 } 1660 1661 static inline void SET_JOININFO_DL_T_PE(void *h2c, u32 val) 1662 { 1663 le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18)); 1664 } 1665 1666 static inline void SET_JOININFO_PORT_ID(void *h2c, u32 val) 1667 { 1668 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21)); 1669 } 1670 1671 static inline void SET_JOININFO_NET_TYPE(void *h2c, u32 val) 1672 { 1673 le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24)); 1674 } 1675 1676 static inline void SET_JOININFO_WIFI_ROLE(void *h2c, u32 val) 1677 { 1678 le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26)); 1679 } 1680 1681 static inline void SET_JOININFO_SELF_ROLE(void *h2c, u32 val) 1682 { 1683 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30)); 1684 } 1685 1686 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val) 1687 { 1688 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1689 } 1690 1691 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val) 1692 { 1693 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1694 } 1695 1696 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val) 1697 { 1698 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1699 } 1700 1701 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val) 1702 { 1703 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1704 } 1705 1706 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val) 1707 { 1708 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1709 } 1710 1711 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val) 1712 { 1713 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); 1714 } 1715 1716 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val) 1717 { 1718 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1719 } 1720 1721 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val) 1722 { 1723 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1724 } 1725 1726 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val) 1727 { 1728 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)); 1729 } 1730 1731 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val) 1732 { 1733 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0)); 1734 } 1735 1736 static inline void SET_BA_CAM_VALID(void *h2c, u32 val) 1737 { 1738 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 1739 } 1740 1741 static inline void SET_BA_CAM_INIT_REQ(void *h2c, u32 val) 1742 { 1743 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 1744 } 1745 1746 static inline void SET_BA_CAM_ENTRY_IDX(void *h2c, u32 val) 1747 { 1748 le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2)); 1749 } 1750 1751 static inline void SET_BA_CAM_TID(void *h2c, u32 val) 1752 { 1753 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4)); 1754 } 1755 1756 static inline void SET_BA_CAM_MACID(void *h2c, u32 val) 1757 { 1758 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1759 } 1760 1761 static inline void SET_BA_CAM_BMAP_SIZE(void *h2c, u32 val) 1762 { 1763 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); 1764 } 1765 1766 static inline void SET_BA_CAM_SSN(void *h2c, u32 val) 1767 { 1768 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20)); 1769 } 1770 1771 static inline void SET_BA_CAM_UID(void *h2c, u32 val) 1772 { 1773 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(7, 0)); 1774 } 1775 1776 static inline void SET_BA_CAM_STD_EN(void *h2c, u32 val) 1777 { 1778 le32p_replace_bits((__le32 *)h2c + 1, val, BIT(8)); 1779 } 1780 1781 static inline void SET_BA_CAM_BAND(void *h2c, u32 val) 1782 { 1783 le32p_replace_bits((__le32 *)h2c + 1, val, BIT(9)); 1784 } 1785 1786 static inline void SET_BA_CAM_ENTRY_IDX_V1(void *h2c, u32 val) 1787 { 1788 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 28)); 1789 } 1790 1791 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val) 1792 { 1793 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1794 } 1795 1796 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val) 1797 { 1798 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1799 } 1800 1801 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val) 1802 { 1803 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); 1804 } 1805 1806 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val) 1807 { 1808 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20)); 1809 } 1810 1811 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val) 1812 { 1813 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1814 } 1815 1816 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val) 1817 { 1818 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0)); 1819 } 1820 1821 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val) 1822 { 1823 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1)); 1824 } 1825 1826 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val) 1827 { 1828 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2)); 1829 } 1830 1831 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val) 1832 { 1833 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3)); 1834 } 1835 1836 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val) 1837 { 1838 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); 1839 } 1840 1841 static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val) 1842 { 1843 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0)); 1844 } 1845 1846 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val) 1847 { 1848 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 1849 } 1850 1851 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val) 1852 { 1853 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 1854 } 1855 1856 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val) 1857 { 1858 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 1859 } 1860 1861 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val) 1862 { 1863 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 1864 } 1865 1866 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val) 1867 { 1868 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0)); 1869 } 1870 1871 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val) 1872 { 1873 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8)); 1874 } 1875 1876 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val) 1877 { 1878 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 1879 } 1880 1881 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val) 1882 { 1883 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0)); 1884 } 1885 1886 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val) 1887 { 1888 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0)); 1889 } 1890 1891 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val) 1892 { 1893 le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0)); 1894 } 1895 1896 static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val) 1897 { 1898 le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0)); 1899 } 1900 1901 static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val) 1902 { 1903 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1904 } 1905 1906 static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val) 1907 { 1908 le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16)); 1909 } 1910 1911 static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val) 1912 { 1913 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1914 } 1915 1916 static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val) 1917 { 1918 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 1919 } 1920 1921 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val) 1922 { 1923 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 1924 } 1925 1926 static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val) 1927 { 1928 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); 1929 } 1930 1931 static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val) 1932 { 1933 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1934 } 1935 1936 static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val) 1937 { 1938 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1939 } 1940 1941 static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val) 1942 { 1943 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1944 } 1945 1946 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val) 1947 { 1948 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1949 } 1950 1951 static inline void RTW89_SET_WOW_GLOBAL_ENABLE(void *h2c, u32 val) 1952 { 1953 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 1954 } 1955 1956 static inline void RTW89_SET_WOW_GLOBAL_DROP_ALL_PKT(void *h2c, u32 val) 1957 { 1958 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 1959 } 1960 1961 static inline void RTW89_SET_WOW_GLOBAL_RX_PARSE_AFTER_WAKE(void *h2c, u32 val) 1962 { 1963 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); 1964 } 1965 1966 static inline void RTW89_SET_WOW_GLOBAL_WAKE_BAR_PULLED(void *h2c, u32 val) 1967 { 1968 le32p_replace_bits((__le32 *)h2c, val, BIT(3)); 1969 } 1970 1971 static inline void RTW89_SET_WOW_GLOBAL_MAC_ID(void *h2c, u32 val) 1972 { 1973 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1974 } 1975 1976 static inline void RTW89_SET_WOW_GLOBAL_PAIRWISE_SEC_ALGO(void *h2c, u32 val) 1977 { 1978 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1979 } 1980 1981 static inline void RTW89_SET_WOW_GLOBAL_GROUP_SEC_ALGO(void *h2c, u32 val) 1982 { 1983 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1984 } 1985 1986 static inline void RTW89_SET_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT(void *h2c, u32 val) 1987 { 1988 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)); 1989 } 1990 1991 static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val) 1992 { 1993 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 1994 } 1995 1996 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val) 1997 { 1998 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 1999 } 2000 2001 static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val) 2002 { 2003 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); 2004 } 2005 2006 static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val) 2007 { 2008 le32p_replace_bits((__le32 *)h2c, val, BIT(3)); 2009 } 2010 2011 static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val) 2012 { 2013 le32p_replace_bits((__le32 *)h2c, val, BIT(4)); 2014 } 2015 2016 static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val) 2017 { 2018 le32p_replace_bits((__le32 *)h2c, val, BIT(5)); 2019 } 2020 2021 static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val) 2022 { 2023 le32p_replace_bits((__le32 *)h2c, val, BIT(6)); 2024 } 2025 2026 static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val) 2027 { 2028 le32p_replace_bits((__le32 *)h2c, val, BIT(7)); 2029 } 2030 2031 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val) 2032 { 2033 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 2034 } 2035 2036 static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val) 2037 { 2038 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 2039 } 2040 2041 static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val) 2042 { 2043 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1)); 2044 } 2045 2046 static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val) 2047 { 2048 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0)); 2049 } 2050 2051 static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val) 2052 { 2053 le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0)); 2054 } 2055 2056 static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val) 2057 { 2058 le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0)); 2059 } 2060 2061 static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val) 2062 { 2063 le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0)); 2064 } 2065 2066 static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val) 2067 { 2068 le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0)); 2069 } 2070 2071 static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val) 2072 { 2073 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22)); 2074 } 2075 2076 static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val) 2077 { 2078 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23)); 2079 } 2080 2081 static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val) 2082 { 2083 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24)); 2084 } 2085 2086 static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val) 2087 { 2088 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25)); 2089 } 2090 2091 static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val) 2092 { 2093 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26)); 2094 } 2095 2096 static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val) 2097 { 2098 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31)); 2099 } 2100 2101 enum rtw89_btc_btf_h2c_class { 2102 BTFC_SET = 0x10, 2103 BTFC_GET = 0x11, 2104 BTFC_FW_EVENT = 0x12, 2105 }; 2106 2107 enum rtw89_btc_btf_set { 2108 SET_REPORT_EN = 0x0, 2109 SET_SLOT_TABLE, 2110 SET_MREG_TABLE, 2111 SET_CX_POLICY, 2112 SET_GPIO_DBG, 2113 SET_DRV_INFO, 2114 SET_DRV_EVENT, 2115 SET_BT_WREG_ADDR, 2116 SET_BT_WREG_VAL, 2117 SET_BT_RREG_ADDR, 2118 SET_BT_WL_CH_INFO, 2119 SET_BT_INFO_REPORT, 2120 SET_BT_IGNORE_WLAN_ACT, 2121 SET_BT_TX_PWR, 2122 SET_BT_LNA_CONSTRAIN, 2123 SET_BT_GOLDEN_RX_RANGE, 2124 SET_BT_PSD_REPORT, 2125 SET_H2C_TEST, 2126 SET_MAX1, 2127 }; 2128 2129 enum rtw89_btc_cxdrvinfo { 2130 CXDRVINFO_INIT = 0, 2131 CXDRVINFO_ROLE, 2132 CXDRVINFO_DBCC, 2133 CXDRVINFO_SMAP, 2134 CXDRVINFO_RFK, 2135 CXDRVINFO_RUN, 2136 CXDRVINFO_CTRL, 2137 CXDRVINFO_SCAN, 2138 CXDRVINFO_MAX, 2139 }; 2140 2141 enum rtw89_scan_mode { 2142 RTW89_SCAN_IMMEDIATE, 2143 }; 2144 2145 enum rtw89_scan_type { 2146 RTW89_SCAN_ONCE, 2147 }; 2148 2149 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val) 2150 { 2151 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0)); 2152 } 2153 2154 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val) 2155 { 2156 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0)); 2157 } 2158 2159 static inline void RTW89_SET_FWCMD_CXINIT_ANT_TYPE(void *cmd, u8 val) 2160 { 2161 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)); 2162 } 2163 2164 static inline void RTW89_SET_FWCMD_CXINIT_ANT_NUM(void *cmd, u8 val) 2165 { 2166 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)); 2167 } 2168 2169 static inline void RTW89_SET_FWCMD_CXINIT_ANT_ISO(void *cmd, u8 val) 2170 { 2171 u8p_replace_bits((u8 *)(cmd) + 4, val, GENMASK(7, 0)); 2172 } 2173 2174 static inline void RTW89_SET_FWCMD_CXINIT_ANT_POS(void *cmd, u8 val) 2175 { 2176 u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(0)); 2177 } 2178 2179 static inline void RTW89_SET_FWCMD_CXINIT_ANT_DIVERSITY(void *cmd, u8 val) 2180 { 2181 u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(1)); 2182 } 2183 2184 static inline void RTW89_SET_FWCMD_CXINIT_MOD_RFE(void *cmd, u8 val) 2185 { 2186 u8p_replace_bits((u8 *)(cmd) + 6, val, GENMASK(7, 0)); 2187 } 2188 2189 static inline void RTW89_SET_FWCMD_CXINIT_MOD_CV(void *cmd, u8 val) 2190 { 2191 u8p_replace_bits((u8 *)(cmd) + 7, val, GENMASK(7, 0)); 2192 } 2193 2194 static inline void RTW89_SET_FWCMD_CXINIT_MOD_BT_SOLO(void *cmd, u8 val) 2195 { 2196 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(0)); 2197 } 2198 2199 static inline void RTW89_SET_FWCMD_CXINIT_MOD_BT_POS(void *cmd, u8 val) 2200 { 2201 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(1)); 2202 } 2203 2204 static inline void RTW89_SET_FWCMD_CXINIT_MOD_SW_TYPE(void *cmd, u8 val) 2205 { 2206 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(2)); 2207 } 2208 2209 static inline void RTW89_SET_FWCMD_CXINIT_WL_GCH(void *cmd, u8 val) 2210 { 2211 u8p_replace_bits((u8 *)(cmd) + 10, val, GENMASK(7, 0)); 2212 } 2213 2214 static inline void RTW89_SET_FWCMD_CXINIT_WL_ONLY(void *cmd, u8 val) 2215 { 2216 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(0)); 2217 } 2218 2219 static inline void RTW89_SET_FWCMD_CXINIT_WL_INITOK(void *cmd, u8 val) 2220 { 2221 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(1)); 2222 } 2223 2224 static inline void RTW89_SET_FWCMD_CXINIT_DBCC_EN(void *cmd, u8 val) 2225 { 2226 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(2)); 2227 } 2228 2229 static inline void RTW89_SET_FWCMD_CXINIT_CX_OTHER(void *cmd, u8 val) 2230 { 2231 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(3)); 2232 } 2233 2234 static inline void RTW89_SET_FWCMD_CXINIT_BT_ONLY(void *cmd, u8 val) 2235 { 2236 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(4)); 2237 } 2238 2239 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val) 2240 { 2241 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)); 2242 } 2243 2244 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val) 2245 { 2246 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)); 2247 } 2248 2249 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val) 2250 { 2251 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0)); 2252 } 2253 2254 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val) 2255 { 2256 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1)); 2257 } 2258 2259 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val) 2260 { 2261 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2)); 2262 } 2263 2264 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val) 2265 { 2266 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3)); 2267 } 2268 2269 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val) 2270 { 2271 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4)); 2272 } 2273 2274 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val) 2275 { 2276 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5)); 2277 } 2278 2279 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val) 2280 { 2281 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6)); 2282 } 2283 2284 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val) 2285 { 2286 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7)); 2287 } 2288 2289 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val) 2290 { 2291 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8)); 2292 } 2293 2294 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val) 2295 { 2296 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9)); 2297 } 2298 2299 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val) 2300 { 2301 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10)); 2302 } 2303 2304 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val) 2305 { 2306 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11)); 2307 } 2308 2309 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset) 2310 { 2311 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0)); 2312 } 2313 2314 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset) 2315 { 2316 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1)); 2317 } 2318 2319 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset) 2320 { 2321 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4)); 2322 } 2323 2324 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset) 2325 { 2326 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5)); 2327 } 2328 2329 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset) 2330 { 2331 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6)); 2332 } 2333 2334 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset) 2335 { 2336 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0)); 2337 } 2338 2339 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset) 2340 { 2341 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1)); 2342 } 2343 2344 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset) 2345 { 2346 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0)); 2347 } 2348 2349 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset) 2350 { 2351 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0)); 2352 } 2353 2354 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset) 2355 { 2356 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0)); 2357 } 2358 2359 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset) 2360 { 2361 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0)); 2362 } 2363 2364 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset) 2365 { 2366 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0)); 2367 } 2368 2369 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset) 2370 { 2371 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0)); 2372 } 2373 2374 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset) 2375 { 2376 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0)); 2377 } 2378 2379 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset) 2380 { 2381 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0)); 2382 } 2383 2384 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset) 2385 { 2386 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0)); 2387 } 2388 2389 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset) 2390 { 2391 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0)); 2392 } 2393 2394 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset) 2395 { 2396 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1)); 2397 } 2398 2399 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset) 2400 { 2401 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2)); 2402 } 2403 2404 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset) 2405 { 2406 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4)); 2407 } 2408 2409 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val) 2410 { 2411 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0)); 2412 } 2413 2414 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val) 2415 { 2416 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1)); 2417 } 2418 2419 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val) 2420 { 2421 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2)); 2422 } 2423 2424 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val) 2425 { 2426 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3)); 2427 } 2428 2429 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val) 2430 { 2431 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0)); 2432 } 2433 2434 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val) 2435 { 2436 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2)); 2437 } 2438 2439 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val) 2440 { 2441 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6)); 2442 } 2443 2444 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val) 2445 { 2446 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8)); 2447 } 2448 2449 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val) 2450 { 2451 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10)); 2452 } 2453 2454 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val) 2455 { 2456 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2457 } 2458 2459 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val) 2460 { 2461 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8)); 2462 } 2463 2464 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val) 2465 { 2466 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16)); 2467 } 2468 2469 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_NUM(void *cmd, u32 val) 2470 { 2471 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2472 } 2473 2474 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_SIZE(void *cmd, u32 val) 2475 { 2476 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8)); 2477 } 2478 2479 static inline void RTW89_SET_FWCMD_CHINFO_PERIOD(void *cmd, u32 val) 2480 { 2481 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2482 } 2483 2484 static inline void RTW89_SET_FWCMD_CHINFO_DWELL(void *cmd, u32 val) 2485 { 2486 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8)); 2487 } 2488 2489 static inline void RTW89_SET_FWCMD_CHINFO_CENTER_CH(void *cmd, u32 val) 2490 { 2491 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 16)); 2492 } 2493 2494 static inline void RTW89_SET_FWCMD_CHINFO_PRI_CH(void *cmd, u32 val) 2495 { 2496 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 24)); 2497 } 2498 2499 static inline void RTW89_SET_FWCMD_CHINFO_BW(void *cmd, u32 val) 2500 { 2501 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(2, 0)); 2502 } 2503 2504 static inline void RTW89_SET_FWCMD_CHINFO_ACTION(void *cmd, u32 val) 2505 { 2506 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 3)); 2507 } 2508 2509 static inline void RTW89_SET_FWCMD_CHINFO_NUM_PKT(void *cmd, u32 val) 2510 { 2511 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(11, 8)); 2512 } 2513 2514 static inline void RTW89_SET_FWCMD_CHINFO_TX(void *cmd, u32 val) 2515 { 2516 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(12)); 2517 } 2518 2519 static inline void RTW89_SET_FWCMD_CHINFO_PAUSE_DATA(void *cmd, u32 val) 2520 { 2521 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(13)); 2522 } 2523 2524 static inline void RTW89_SET_FWCMD_CHINFO_BAND(void *cmd, u32 val) 2525 { 2526 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 14)); 2527 } 2528 2529 static inline void RTW89_SET_FWCMD_CHINFO_PKT_ID(void *cmd, u32 val) 2530 { 2531 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16)); 2532 } 2533 2534 static inline void RTW89_SET_FWCMD_CHINFO_DFS(void *cmd, u32 val) 2535 { 2536 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(24)); 2537 } 2538 2539 static inline void RTW89_SET_FWCMD_CHINFO_TX_NULL(void *cmd, u32 val) 2540 { 2541 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(25)); 2542 } 2543 2544 static inline void RTW89_SET_FWCMD_CHINFO_RANDOM(void *cmd, u32 val) 2545 { 2546 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(26)); 2547 } 2548 2549 static inline void RTW89_SET_FWCMD_CHINFO_CFG_TX(void *cmd, u32 val) 2550 { 2551 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(27)); 2552 } 2553 2554 static inline void RTW89_SET_FWCMD_CHINFO_PKT0(void *cmd, u32 val) 2555 { 2556 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(7, 0)); 2557 } 2558 2559 static inline void RTW89_SET_FWCMD_CHINFO_PKT1(void *cmd, u32 val) 2560 { 2561 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 8)); 2562 } 2563 2564 static inline void RTW89_SET_FWCMD_CHINFO_PKT2(void *cmd, u32 val) 2565 { 2566 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16)); 2567 } 2568 2569 static inline void RTW89_SET_FWCMD_CHINFO_PKT3(void *cmd, u32 val) 2570 { 2571 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(31, 24)); 2572 } 2573 2574 static inline void RTW89_SET_FWCMD_CHINFO_PKT4(void *cmd, u32 val) 2575 { 2576 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(7, 0)); 2577 } 2578 2579 static inline void RTW89_SET_FWCMD_CHINFO_PKT5(void *cmd, u32 val) 2580 { 2581 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(15, 8)); 2582 } 2583 2584 static inline void RTW89_SET_FWCMD_CHINFO_PKT6(void *cmd, u32 val) 2585 { 2586 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(23, 16)); 2587 } 2588 2589 static inline void RTW89_SET_FWCMD_CHINFO_PKT7(void *cmd, u32 val) 2590 { 2591 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 24)); 2592 } 2593 2594 static inline void RTW89_SET_FWCMD_CHINFO_POWER_IDX(void *cmd, u32 val) 2595 { 2596 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(15, 0)); 2597 } 2598 2599 static inline void RTW89_SET_FWCMD_SCANOFLD_MACID(void *cmd, u32 val) 2600 { 2601 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2602 } 2603 2604 static inline void RTW89_SET_FWCMD_SCANOFLD_NORM_CY(void *cmd, u32 val) 2605 { 2606 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8)); 2607 } 2608 2609 static inline void RTW89_SET_FWCMD_SCANOFLD_PORT_ID(void *cmd, u32 val) 2610 { 2611 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(18, 16)); 2612 } 2613 2614 static inline void RTW89_SET_FWCMD_SCANOFLD_BAND(void *cmd, u32 val) 2615 { 2616 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, BIT(19)); 2617 } 2618 2619 static inline void RTW89_SET_FWCMD_SCANOFLD_OPERATION(void *cmd, u32 val) 2620 { 2621 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(21, 20)); 2622 } 2623 2624 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_BAND(void *cmd, u32 val) 2625 { 2626 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 22)); 2627 } 2628 2629 static inline void RTW89_SET_FWCMD_SCANOFLD_NOTIFY_END(void *cmd, u32 val) 2630 { 2631 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(0)); 2632 } 2633 2634 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_MODE(void *cmd, u32 val) 2635 { 2636 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(1)); 2637 } 2638 2639 static inline void RTW89_SET_FWCMD_SCANOFLD_START_MODE(void *cmd, u32 val) 2640 { 2641 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(2)); 2642 } 2643 2644 static inline void RTW89_SET_FWCMD_SCANOFLD_SCAN_TYPE(void *cmd, u32 val) 2645 { 2646 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(4, 3)); 2647 } 2648 2649 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_BW(void *cmd, u32 val) 2650 { 2651 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 5)); 2652 } 2653 2654 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_PRI_CH(void *cmd, u32 val) 2655 { 2656 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 8)); 2657 } 2658 2659 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CENTRAL_CH(void *cmd, 2660 u32 val) 2661 { 2662 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16)); 2663 } 2664 2665 static inline void RTW89_SET_FWCMD_SCANOFLD_PROBE_REQ_PKT_ID(void *cmd, u32 val) 2666 { 2667 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(31, 24)); 2668 } 2669 2670 static inline void RTW89_SET_FWCMD_SCANOFLD_NORM_PD(void *cmd, u32 val) 2671 { 2672 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 0)); 2673 } 2674 2675 static inline void RTW89_SET_FWCMD_SCANOFLD_SLOW_PD(void *cmd, u32 val) 2676 { 2677 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16)); 2678 } 2679 2680 static inline void RTW89_SET_FWCMD_SCANOFLD_TSF_HIGH(void *cmd, u32 val) 2681 { 2682 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 0)); 2683 } 2684 2685 static inline void RTW89_SET_FWCMD_SCANOFLD_TSF_SLOW(void *cmd, u32 val) 2686 { 2687 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(31, 0)); 2688 } 2689 2690 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val) 2691 { 2692 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 2693 } 2694 2695 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val) 2696 { 2697 le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8)); 2698 } 2699 2700 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val) 2701 { 2702 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12)); 2703 } 2704 2705 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val) 2706 { 2707 le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16)); 2708 } 2709 2710 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val) 2711 { 2712 le32p_replace_bits((__le32 *)cmd, val, BIT(20)); 2713 } 2714 2715 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val) 2716 { 2717 le32p_replace_bits((__le32 *)cmd, val, BIT(21)); 2718 } 2719 2720 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val) 2721 { 2722 *((__le32 *)cmd + 1) = val; 2723 } 2724 2725 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val) 2726 { 2727 *((__le32 *)cmd + 2) = val; 2728 } 2729 2730 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val) 2731 { 2732 *((__le32 *)cmd + 3) = val; 2733 } 2734 2735 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val) 2736 { 2737 le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0)); 2738 } 2739 2740 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val) 2741 { 2742 u8 ctwnd; 2743 2744 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT)) 2745 return; 2746 ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val); 2747 le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8)); 2748 } 2749 2750 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val) 2751 { 2752 le32p_replace_bits((__le32 *)cmd, val, BIT(0)); 2753 } 2754 2755 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val) 2756 { 2757 le32p_replace_bits((__le32 *)cmd, val, BIT(1)); 2758 } 2759 2760 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val) 2761 { 2762 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2)); 2763 } 2764 2765 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val) 2766 { 2767 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16)); 2768 } 2769 2770 enum rtw89_fw_mcc_c2h_rpt_cfg { 2771 RTW89_FW_MCC_C2H_RPT_OFF = 0, 2772 RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1, 2773 RTW89_FW_MCC_C2H_RPT_ALL = 2, 2774 }; 2775 2776 struct rtw89_fw_mcc_add_req { 2777 u8 macid; 2778 u8 central_ch_seg0; 2779 u8 central_ch_seg1; 2780 u8 primary_ch; 2781 enum rtw89_bandwidth bandwidth: 4; 2782 u32 group: 2; 2783 u32 c2h_rpt: 2; 2784 u32 dis_tx_null: 1; 2785 u32 dis_sw_retry: 1; 2786 u32 in_curr_ch: 1; 2787 u32 sw_retry_count: 3; 2788 u32 tx_null_early: 4; 2789 u32 btc_in_2g: 1; 2790 u32 pta_en: 1; 2791 u32 rfk_by_pass: 1; 2792 u32 ch_band_type: 2; 2793 u32 rsvd0: 9; 2794 u32 duration; 2795 u8 courtesy_en; 2796 u8 courtesy_num; 2797 u8 courtesy_target; 2798 u8 rsvd1; 2799 }; 2800 2801 static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val) 2802 { 2803 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 2804 } 2805 2806 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val) 2807 { 2808 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 2809 } 2810 2811 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val) 2812 { 2813 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 2814 } 2815 2816 static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val) 2817 { 2818 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 2819 } 2820 2821 static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val) 2822 { 2823 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0)); 2824 } 2825 2826 static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val) 2827 { 2828 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4)); 2829 } 2830 2831 static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val) 2832 { 2833 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6)); 2834 } 2835 2836 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val) 2837 { 2838 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8)); 2839 } 2840 2841 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val) 2842 { 2843 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9)); 2844 } 2845 2846 static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val) 2847 { 2848 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10)); 2849 } 2850 2851 static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val) 2852 { 2853 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11)); 2854 } 2855 2856 static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val) 2857 { 2858 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14)); 2859 } 2860 2861 static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val) 2862 { 2863 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18)); 2864 } 2865 2866 static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val) 2867 { 2868 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19)); 2869 } 2870 2871 static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val) 2872 { 2873 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20)); 2874 } 2875 2876 static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val) 2877 { 2878 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21)); 2879 } 2880 2881 static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val) 2882 { 2883 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 2884 } 2885 2886 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val) 2887 { 2888 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0)); 2889 } 2890 2891 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val) 2892 { 2893 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8)); 2894 } 2895 2896 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val) 2897 { 2898 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16)); 2899 } 2900 2901 struct rtw89_fw_mcc_start_req { 2902 u32 group: 2; 2903 u32 btc_in_group: 1; 2904 u32 old_group_action: 2; 2905 u32 old_group: 2; 2906 u32 rsvd0: 9; 2907 u32 notify_cnt: 3; 2908 u32 rsvd1: 2; 2909 u32 notify_rxdbg_en: 1; 2910 u32 rsvd2: 2; 2911 u32 macid: 8; 2912 u32 tsf_low; 2913 u32 tsf_high; 2914 }; 2915 2916 static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val) 2917 { 2918 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 2919 } 2920 2921 static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val) 2922 { 2923 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 2924 } 2925 2926 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val) 2927 { 2928 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3)); 2929 } 2930 2931 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val) 2932 { 2933 le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5)); 2934 } 2935 2936 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val) 2937 { 2938 le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16)); 2939 } 2940 2941 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val) 2942 { 2943 le32p_replace_bits((__le32 *)cmd, val, BIT(21)); 2944 } 2945 2946 static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val) 2947 { 2948 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 2949 } 2950 2951 static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val) 2952 { 2953 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0)); 2954 } 2955 2956 static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val) 2957 { 2958 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 2959 } 2960 2961 static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val) 2962 { 2963 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 2964 } 2965 2966 static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val) 2967 { 2968 le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8)); 2969 } 2970 2971 static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val) 2972 { 2973 le32p_replace_bits((__le32 *)cmd, val, BIT(10)); 2974 } 2975 2976 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val) 2977 { 2978 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 2979 } 2980 2981 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val) 2982 { 2983 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 2984 } 2985 2986 static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val) 2987 { 2988 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 2989 } 2990 2991 struct rtw89_fw_mcc_tsf_req { 2992 u8 group: 2; 2993 u8 rsvd0: 6; 2994 u8 macid_x; 2995 u8 macid_y; 2996 u8 rsvd1; 2997 }; 2998 2999 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val) 3000 { 3001 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3002 } 3003 3004 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val) 3005 { 3006 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3007 } 3008 3009 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val) 3010 { 3011 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3012 } 3013 3014 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val) 3015 { 3016 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3017 } 3018 3019 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val) 3020 { 3021 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3022 } 3023 3024 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val) 3025 { 3026 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3027 } 3028 3029 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd, 3030 u8 *bitmap, u8 len) 3031 { 3032 memcpy((__le32 *)cmd + 1, bitmap, len); 3033 } 3034 3035 static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val) 3036 { 3037 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3038 } 3039 3040 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val) 3041 { 3042 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3043 } 3044 3045 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val) 3046 { 3047 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3048 } 3049 3050 static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val) 3051 { 3052 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 3053 } 3054 3055 struct rtw89_fw_mcc_duration { 3056 u32 group: 2; 3057 u32 btc_in_group: 1; 3058 u32 rsvd0: 5; 3059 u32 start_macid: 8; 3060 u32 macid_x: 8; 3061 u32 macid_y: 8; 3062 u32 start_tsf_low; 3063 u32 start_tsf_high; 3064 u32 duration_x; 3065 u32 duration_y; 3066 }; 3067 3068 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val) 3069 { 3070 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3071 } 3072 3073 static 3074 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val) 3075 { 3076 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 3077 } 3078 3079 static 3080 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val) 3081 { 3082 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3083 } 3084 3085 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val) 3086 { 3087 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3088 } 3089 3090 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val) 3091 { 3092 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 3093 } 3094 3095 static 3096 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val) 3097 { 3098 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0)); 3099 } 3100 3101 static 3102 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val) 3103 { 3104 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 3105 } 3106 3107 static 3108 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val) 3109 { 3110 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0)); 3111 } 3112 3113 static 3114 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val) 3115 { 3116 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0)); 3117 } 3118 3119 #define RTW89_C2H_HEADER_LEN 8 3120 3121 #define RTW89_GET_C2H_CATEGORY(c2h) \ 3122 le32_get_bits(*((const __le32 *)c2h), GENMASK(1, 0)) 3123 #define RTW89_GET_C2H_CLASS(c2h) \ 3124 le32_get_bits(*((const __le32 *)c2h), GENMASK(7, 2)) 3125 #define RTW89_GET_C2H_FUNC(c2h) \ 3126 le32_get_bits(*((const __le32 *)c2h), GENMASK(15, 8)) 3127 #define RTW89_GET_C2H_LEN(c2h) \ 3128 le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(13, 0)) 3129 3130 struct rtw89_fw_c2h_attr { 3131 u8 category; 3132 u8 class; 3133 u8 func; 3134 u16 len; 3135 }; 3136 3137 static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb) 3138 { 3139 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr)); 3140 3141 return (struct rtw89_fw_c2h_attr *)skb->cb; 3142 } 3143 3144 #define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2) 3145 #define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN) 3146 3147 #define RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h) \ 3148 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3149 #define RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h) \ 3150 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 3151 #define RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h) \ 3152 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3153 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h) \ 3154 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 3155 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h) \ 3156 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24)) 3157 3158 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \ 3159 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3160 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \ 3161 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 3162 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \ 3163 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3164 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \ 3165 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 3166 3167 #define RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h) \ 3168 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 0)) 3169 #define RTW89_GET_PHY_C2H_RA_RPT_RETRY_RATIO(c2h) \ 3170 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 3171 #define RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h) \ 3172 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(6, 0)) 3173 #define RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h) \ 3174 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(9, 8)) 3175 #define RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h) \ 3176 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(12, 10)) 3177 #define RTW89_GET_PHY_C2H_RA_RPT_BW(c2h) \ 3178 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(14, 13)) 3179 3180 /* VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS 3181 * HT-new: [6:5]: NA, [4:0]: MCS 3182 */ 3183 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4) 3184 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0) 3185 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0) 3186 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \ 3187 FIELD_PREP(GENMASK(2, 0), mcs)) 3188 3189 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \ 3190 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 3191 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \ 3192 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8)) 3193 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \ 3194 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16)) 3195 3196 #define RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h) \ 3197 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 3198 #define RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h) \ 3199 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(19, 16)) 3200 #define RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h) \ 3201 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 20)) 3202 #define RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h) \ 3203 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24)) 3204 #define RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h) \ 3205 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(3, 0)) 3206 #define RTW89_GET_MAC_C2H_SCANOFLD_AIR_DENSITY(c2h) \ 3207 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(7, 4)) 3208 #define RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h) \ 3209 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(25, 24)) 3210 3211 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \ 3212 le32_get_bits(*((const __le32 *)(c2h)), GENMASK(1, 0)) 3213 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \ 3214 le32_get_bits(*((const __le32 *)(c2h)), GENMASK(15, 8)) 3215 3216 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \ 3217 le32_get_bits(*((const __le32 *)(c2h)), GENMASK(1, 0)) 3218 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \ 3219 le32_get_bits(*((const __le32 *)(c2h)), GENMASK(7, 2)) 3220 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \ 3221 le32_get_bits(*((const __le32 *)(c2h)), GENMASK(15, 8)) 3222 3223 struct rtw89_mac_mcc_tsf_rpt { 3224 u32 macid_x; 3225 u32 macid_y; 3226 u32 tsf_x_low; 3227 u32 tsf_x_high; 3228 u32 tsf_y_low; 3229 u32 tsf_y_high; 3230 }; 3231 3232 static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE); 3233 3234 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \ 3235 le32_get_bits(*((const __le32 *)(c2h)), GENMASK(7, 0)) 3236 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \ 3237 le32_get_bits(*((const __le32 *)(c2h)), GENMASK(15, 8)) 3238 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \ 3239 le32_get_bits(*((const __le32 *)(c2h)), GENMASK(17, 16)) 3240 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \ 3241 le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(31, 0)) 3242 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \ 3243 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 0)) 3244 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \ 3245 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0)) 3246 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \ 3247 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0)) 3248 3249 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \ 3250 le32_get_bits(*((const __le32 *)(c2h)), GENMASK(5, 0)) 3251 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \ 3252 le32_get_bits(*((const __le32 *)(c2h)), GENMASK(7, 6)) 3253 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \ 3254 le32_get_bits(*((const __le32 *)(c2h)), GENMASK(15, 8)) 3255 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \ 3256 le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(31, 0)) 3257 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \ 3258 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 0)) 3259 3260 #define RTW89_FW_HDR_SIZE 32 3261 #define RTW89_FW_SECTION_HDR_SIZE 16 3262 3263 #define RTW89_MFW_SIG 0xFF 3264 3265 struct rtw89_mfw_info { 3266 u8 cv; 3267 u8 type; /* enum rtw89_fw_type */ 3268 u8 mp; 3269 u8 rsvd; 3270 __le32 shift; 3271 __le32 size; 3272 u8 rsvd2[4]; 3273 } __packed; 3274 3275 struct rtw89_mfw_hdr { 3276 u8 sig; /* RTW89_MFW_SIG */ 3277 u8 fw_nr; 3278 u8 rsvd0[2]; 3279 struct { 3280 u8 major; 3281 u8 minor; 3282 u8 sub; 3283 u8 idx; 3284 } ver; 3285 u8 rsvd1[8]; 3286 struct rtw89_mfw_info info[]; 3287 } __packed; 3288 3289 struct fwcmd_hdr { 3290 __le32 hdr0; 3291 __le32 hdr1; 3292 }; 3293 3294 union rtw89_compat_fw_hdr { 3295 struct rtw89_mfw_hdr mfw_hdr; 3296 u8 fw_hdr[RTW89_FW_HDR_SIZE]; 3297 }; 3298 3299 static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf) 3300 { 3301 const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf; 3302 3303 if (compat->mfw_hdr.sig == RTW89_MFW_SIG) 3304 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr); 3305 else 3306 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr); 3307 } 3308 3309 #define RTW89_H2C_RF_PAGE_SIZE 500 3310 #define RTW89_H2C_RF_PAGE_NUM 3 3311 struct rtw89_fw_h2c_rf_reg_info { 3312 enum rtw89_rf_path rf_path; 3313 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE]; 3314 u16 curr_idx; 3315 }; 3316 3317 #define H2C_SEC_CAM_LEN 24 3318 3319 #define H2C_HEADER_LEN 8 3320 #define H2C_HDR_CAT GENMASK(1, 0) 3321 #define H2C_HDR_CLASS GENMASK(7, 2) 3322 #define H2C_HDR_FUNC GENMASK(15, 8) 3323 #define H2C_HDR_DEL_TYPE GENMASK(19, 16) 3324 #define H2C_HDR_H2C_SEQ GENMASK(31, 24) 3325 #define H2C_HDR_TOTAL_LEN GENMASK(13, 0) 3326 #define H2C_HDR_REC_ACK BIT(14) 3327 #define H2C_HDR_DONE_ACK BIT(15) 3328 3329 #define FWCMD_TYPE_H2C 0 3330 3331 #define H2C_CAT_TEST 0x0 3332 3333 /* CLASS 5 - FW STATUS TEST */ 3334 #define H2C_CL_FW_STATUS_TEST 0x5 3335 #define H2C_FUNC_CPU_EXCEPTION 0x1 3336 3337 #define H2C_CAT_MAC 0x1 3338 3339 /* CLASS 0 - FW INFO */ 3340 #define H2C_CL_FW_INFO 0x0 3341 #define H2C_FUNC_LOG_CFG 0x0 3342 #define H2C_FUNC_MAC_GENERAL_PKT 0x1 3343 3344 /* CLASS 1 - WOW */ 3345 #define H2C_CL_MAC_WOW 0x1 3346 #define H2C_FUNC_KEEP_ALIVE 0x0 3347 #define H2C_FUNC_DISCONNECT_DETECT 0x1 3348 #define H2C_FUNC_WOW_GLOBAL 0x2 3349 #define H2C_FUNC_WAKEUP_CTRL 0x8 3350 #define H2C_FUNC_WOW_CAM_UPD 0xC 3351 3352 /* CLASS 2 - PS */ 3353 #define H2C_CL_MAC_PS 0x2 3354 #define H2C_FUNC_MAC_LPS_PARM 0x0 3355 #define H2C_FUNC_P2P_ACT 0x1 3356 3357 /* CLASS 3 - FW download */ 3358 #define H2C_CL_MAC_FWDL 0x3 3359 #define H2C_FUNC_MAC_FWHDR_DL 0x0 3360 3361 /* CLASS 5 - Frame Exchange */ 3362 #define H2C_CL_MAC_FR_EXCHG 0x5 3363 #define H2C_FUNC_MAC_CCTLINFO_UD 0x2 3364 #define H2C_FUNC_MAC_BCN_UPD 0x5 3365 #define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9 3366 #define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa 3367 3368 /* CLASS 6 - Address CAM */ 3369 #define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6 3370 #define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0 3371 3372 /* CLASS 8 - Media Status Report */ 3373 #define H2C_CL_MAC_MEDIA_RPT 0x8 3374 #define H2C_FUNC_MAC_JOININFO 0x0 3375 #define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4 3376 3377 /* CLASS 9 - FW offload */ 3378 #define H2C_CL_MAC_FW_OFLD 0x9 3379 #define H2C_FUNC_PACKET_OFLD 0x1 3380 #define H2C_FUNC_MAC_MACID_PAUSE 0x8 3381 #define H2C_FUNC_USR_EDCA 0xF 3382 #define H2C_FUNC_TSF32_TOGL 0x10 3383 #define H2C_FUNC_OFLD_CFG 0x14 3384 #define H2C_FUNC_ADD_SCANOFLD_CH 0x16 3385 #define H2C_FUNC_SCANOFLD 0x17 3386 #define H2C_FUNC_PKT_DROP 0x1b 3387 3388 /* CLASS 10 - Security CAM */ 3389 #define H2C_CL_MAC_SEC_CAM 0xa 3390 #define H2C_FUNC_MAC_SEC_UPD 0x1 3391 3392 /* CLASS 12 - BA CAM */ 3393 #define H2C_CL_BA_CAM 0xc 3394 #define H2C_FUNC_MAC_BA_CAM 0x0 3395 3396 /* CLASS 14 - MCC */ 3397 #define H2C_CL_MCC 0xe 3398 enum rtw89_mcc_h2c_func { 3399 H2C_FUNC_ADD_MCC = 0x0, 3400 H2C_FUNC_START_MCC = 0x1, 3401 H2C_FUNC_STOP_MCC = 0x2, 3402 H2C_FUNC_DEL_MCC_GROUP = 0x3, 3403 H2C_FUNC_RESET_MCC_GROUP = 0x4, 3404 H2C_FUNC_MCC_REQ_TSF = 0x5, 3405 H2C_FUNC_MCC_MACID_BITMAP = 0x6, 3406 H2C_FUNC_MCC_SYNC = 0x7, 3407 H2C_FUNC_MCC_SET_DURATION = 0x8, 3408 3409 NUM_OF_RTW89_MCC_H2C_FUNC, 3410 }; 3411 3412 #define RTW89_MCC_WAIT_COND(group, func) \ 3413 ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func)) 3414 3415 #define H2C_CAT_OUTSRC 0x2 3416 3417 #define H2C_CL_OUTSRC_RA 0x1 3418 #define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0 3419 3420 #define H2C_CL_OUTSRC_RF_REG_A 0x8 3421 #define H2C_CL_OUTSRC_RF_REG_B 0x9 3422 #define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa 3423 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2 3424 3425 struct rtw89_fw_h2c_rf_get_mccch { 3426 __le32 ch_0; 3427 __le32 ch_1; 3428 __le32 band_0; 3429 __le32 band_1; 3430 __le32 current_channel; 3431 __le32 current_band_type; 3432 } __packed; 3433 3434 #define RTW89_FW_RSVD_PLE_SIZE 0x800 3435 3436 #define RTW89_WCPU_BASE_MASK GENMASK(27, 0) 3437 3438 #define RTW89_FW_BACKTRACE_INFO_SIZE 8 3439 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \ 3440 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0) 3441 3442 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */ 3443 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE 3444 3445 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev); 3446 int rtw89_fw_recognize(struct rtw89_dev *rtwdev); 3447 const struct firmware * 3448 rtw89_early_fw_feature_recognize(struct device *device, 3449 const struct rtw89_chip_info *chip, 3450 u32 *early_feat_map); 3451 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type); 3452 int rtw89_load_firmware(struct rtw89_dev *rtwdev); 3453 void rtw89_unload_firmware(struct rtw89_dev *rtwdev); 3454 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev); 3455 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb, 3456 u8 type, u8 cat, u8 class, u8 func, 3457 bool rack, bool dack, u32 len); 3458 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, 3459 struct rtw89_vif *rtwvif); 3460 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, 3461 struct ieee80211_vif *vif, 3462 struct ieee80211_sta *sta); 3463 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev, 3464 struct rtw89_sta *rtwsta); 3465 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev, 3466 struct rtw89_sta *rtwsta); 3467 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev, 3468 struct rtw89_vif *rtwvif); 3469 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif, 3470 struct rtw89_sta *rtwsta, const u8 *scan_mac_addr); 3471 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev, 3472 struct rtw89_vif *rtwvif, 3473 struct rtw89_sta *rtwsta); 3474 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h); 3475 void rtw89_fw_c2h_work(struct work_struct *work); 3476 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev, 3477 struct rtw89_vif *rtwvif, 3478 struct rtw89_sta *rtwsta, 3479 enum rtw89_upd_mode upd_mode); 3480 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3481 struct rtw89_sta *rtwsta, bool dis_conn); 3482 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp, 3483 bool pause); 3484 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3485 u8 ac, u32 val); 3486 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev); 3487 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi); 3488 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev); 3489 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev); 3490 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev); 3491 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev); 3492 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev); 3493 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id); 3494 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id, 3495 struct sk_buff *skb_ofld); 3496 int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int len, 3497 struct list_head *chan_list); 3498 int rtw89_fw_h2c_scan_offload(struct rtw89_dev *rtwdev, 3499 struct rtw89_scan_option *opt, 3500 struct rtw89_vif *vif); 3501 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev, 3502 struct rtw89_fw_h2c_rf_reg_info *info, 3503 u16 len, u8 page); 3504 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev); 3505 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, 3506 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, 3507 bool rack, bool dack); 3508 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len); 3509 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev); 3510 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev); 3511 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, u8 macid); 3512 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 3513 bool valid, struct ieee80211_ampdu_params *params); 3514 void rtw89_fw_h2c_init_ba_cam_v1(struct rtw89_dev *rtwdev); 3515 3516 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev, 3517 struct rtw89_lps_parm *lps_param); 3518 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len); 3519 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len); 3520 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev, 3521 struct rtw89_mac_h2c_info *h2c_info, 3522 struct rtw89_mac_c2h_info *c2h_info); 3523 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable); 3524 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev); 3525 void rtw89_store_op_chan(struct rtw89_dev *rtwdev, bool backup); 3526 void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3527 struct ieee80211_scan_request *req); 3528 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3529 bool aborted); 3530 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3531 bool enable); 3532 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 3533 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev); 3534 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev, 3535 const struct rtw89_pkt_drop_params *params); 3536 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3537 struct ieee80211_p2p_noa_desc *desc, 3538 u8 act, u8 noa_id); 3539 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3540 bool en); 3541 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3542 bool enable); 3543 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev, 3544 struct rtw89_vif *rtwvif, bool enable); 3545 int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3546 bool enable); 3547 int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev, 3548 struct rtw89_vif *rtwvif, bool enable); 3549 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3550 bool enable); 3551 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev, 3552 struct rtw89_vif *rtwvif, bool enable); 3553 int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev, 3554 struct rtw89_wow_cam_info *cam_info); 3555 int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev, 3556 const struct rtw89_fw_mcc_add_req *p); 3557 int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev, 3558 const struct rtw89_fw_mcc_start_req *p); 3559 int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid, 3560 bool prev_groups); 3561 int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group, 3562 bool prev_groups); 3563 int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group); 3564 int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev, 3565 const struct rtw89_fw_mcc_tsf_req *req, 3566 struct rtw89_mac_mcc_tsf_rpt *rpt); 3567 int rtw89_fw_h2c_mcc_macid_bitamp(struct rtw89_dev *rtwdev, u8 group, u8 macid, 3568 u8 *bitmap); 3569 int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source, 3570 u8 target, u8 offset); 3571 int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev, 3572 const struct rtw89_fw_mcc_duration *p); 3573 3574 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev) 3575 { 3576 const struct rtw89_chip_info *chip = rtwdev->chip; 3577 3578 if (chip->bacam_v1) 3579 rtw89_fw_h2c_init_ba_cam_v1(rtwdev); 3580 } 3581 3582 #endif 3583