1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020  Realtek Corporation
3  */
4 
5 #ifndef __RTW89_FW_H__
6 #define __RTW89_FW_H__
7 
8 #include "core.h"
9 
10 enum rtw89_fw_dl_status {
11 	RTW89_FWDL_INITIAL_STATE = 0,
12 	RTW89_FWDL_FWDL_ONGOING = 1,
13 	RTW89_FWDL_CHECKSUM_FAIL = 2,
14 	RTW89_FWDL_SECURITY_FAIL = 3,
15 	RTW89_FWDL_CV_NOT_MATCH = 4,
16 	RTW89_FWDL_RSVD0 = 5,
17 	RTW89_FWDL_WCPU_FWDL_RDY = 6,
18 	RTW89_FWDL_WCPU_FW_INIT_RDY = 7
19 };
20 
21 #define RTW89_GET_C2H_HDR_FUNC(info) \
22 	u32_get_bits(info, GENMASK(6, 0))
23 #define RTW89_GET_C2H_HDR_LEN(info) \
24 	u32_get_bits(info, GENMASK(11, 8))
25 
26 #define RTW89_SET_H2CREG_HDR_FUNC(info, val) \
27 	u32p_replace_bits(info, val, GENMASK(6, 0))
28 #define RTW89_SET_H2CREG_HDR_LEN(info, val) \
29 	u32p_replace_bits(info, val, GENMASK(11, 8))
30 
31 #define RTW89_H2CREG_MAX 4
32 #define RTW89_C2HREG_MAX 4
33 #define RTW89_C2HREG_HDR_LEN 2
34 #define RTW89_H2CREG_HDR_LEN 2
35 #define RTW89_C2H_TIMEOUT 1000000
36 struct rtw89_mac_c2h_info {
37 	u8 id;
38 	u8 content_len;
39 	u32 c2hreg[RTW89_C2HREG_MAX];
40 };
41 
42 struct rtw89_mac_h2c_info {
43 	u8 id;
44 	u8 content_len;
45 	u32 h2creg[RTW89_H2CREG_MAX];
46 };
47 
48 enum rtw89_mac_h2c_type {
49 	RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0,
50 	RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD,
51 	RTW89_FWCMD_H2CREG_FUNC_FWERR,
52 	RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE,
53 	RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM,
54 	RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN
55 };
56 
57 enum rtw89_mac_c2h_type {
58 	RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0,
59 	RTW89_FWCMD_C2HREG_FUNC_ERR_RPT,
60 	RTW89_FWCMD_C2HREG_FUNC_ERR_MSG,
61 	RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,
62 	RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,
63 	RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF
64 };
65 
66 struct rtw89_c2h_phy_cap {
67 	u32 func:7;
68 	u32 ack:1;
69 	u32 len:4;
70 	u32 seq:4;
71 	u32 rx_nss:8;
72 	u32 bw:8;
73 
74 	u32 tx_nss:8;
75 	u32 prot:8;
76 	u32 nic:8;
77 	u32 wl_func:8;
78 
79 	u32 hw_type:8;
80 } __packed;
81 
82 enum rtw89_fw_c2h_category {
83 	RTW89_C2H_CAT_TEST,
84 	RTW89_C2H_CAT_MAC,
85 	RTW89_C2H_CAT_OUTSRC,
86 };
87 
88 enum rtw89_fw_log_level {
89 	RTW89_FW_LOG_LEVEL_OFF,
90 	RTW89_FW_LOG_LEVEL_CRT,
91 	RTW89_FW_LOG_LEVEL_SER,
92 	RTW89_FW_LOG_LEVEL_WARN,
93 	RTW89_FW_LOG_LEVEL_LOUD,
94 	RTW89_FW_LOG_LEVEL_TR,
95 };
96 
97 enum rtw89_fw_log_path {
98 	RTW89_FW_LOG_LEVEL_UART,
99 	RTW89_FW_LOG_LEVEL_C2H,
100 	RTW89_FW_LOG_LEVEL_SNI,
101 };
102 
103 enum rtw89_fw_log_comp {
104 	RTW89_FW_LOG_COMP_VER,
105 	RTW89_FW_LOG_COMP_INIT,
106 	RTW89_FW_LOG_COMP_TASK,
107 	RTW89_FW_LOG_COMP_CNS,
108 	RTW89_FW_LOG_COMP_H2C,
109 	RTW89_FW_LOG_COMP_C2H,
110 	RTW89_FW_LOG_COMP_TX,
111 	RTW89_FW_LOG_COMP_RX,
112 	RTW89_FW_LOG_COMP_IPSEC,
113 	RTW89_FW_LOG_COMP_TIMER,
114 	RTW89_FW_LOG_COMP_DBGPKT,
115 	RTW89_FW_LOG_COMP_PS,
116 	RTW89_FW_LOG_COMP_ERROR,
117 	RTW89_FW_LOG_COMP_WOWLAN,
118 	RTW89_FW_LOG_COMP_SECURE_BOOT,
119 	RTW89_FW_LOG_COMP_BTC,
120 	RTW89_FW_LOG_COMP_BB,
121 	RTW89_FW_LOG_COMP_TWT,
122 	RTW89_FW_LOG_COMP_RF,
123 	RTW89_FW_LOG_COMP_MCC = 20,
124 };
125 
126 enum rtw89_pkt_offload_op {
127 	RTW89_PKT_OFLD_OP_ADD,
128 	RTW89_PKT_OFLD_OP_DEL,
129 	RTW89_PKT_OFLD_OP_READ,
130 };
131 
132 enum rtw89_scanofld_notify_reason {
133 	RTW89_SCAN_DWELL_NOTIFY,
134 	RTW89_SCAN_PRE_TX_NOTIFY,
135 	RTW89_SCAN_POST_TX_NOTIFY,
136 	RTW89_SCAN_ENTER_CH_NOTIFY,
137 	RTW89_SCAN_LEAVE_CH_NOTIFY,
138 	RTW89_SCAN_END_SCAN_NOTIFY,
139 };
140 
141 enum rtw89_chan_type {
142 	RTW89_CHAN_OPERATE = 0,
143 	RTW89_CHAN_ACTIVE,
144 	RTW89_CHAN_DFS,
145 };
146 
147 #define FWDL_SECTION_MAX_NUM 10
148 #define FWDL_SECTION_CHKSUM_LEN	8
149 #define FWDL_SECTION_PER_PKT_LEN 2020
150 
151 struct rtw89_fw_hdr_section_info {
152 	u8 redl;
153 	const u8 *addr;
154 	u32 len;
155 	u32 dladdr;
156 };
157 
158 struct rtw89_fw_bin_info {
159 	u8 section_num;
160 	u32 hdr_len;
161 	struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];
162 };
163 
164 struct rtw89_fw_macid_pause_grp {
165 	__le32 pause_grp[4];
166 	__le32 mask_grp[4];
167 } __packed;
168 
169 struct rtw89_h2creg_sch_tx_en {
170 	u8 func:7;
171 	u8 ack:1;
172 	u8 total_len:4;
173 	u8 seq_num:4;
174 	u16 tx_en:16;
175 	u16 mask:16;
176 	u8 band:1;
177 	u16 rsvd:15;
178 } __packed;
179 
180 #define RTW89_CHANNEL_TIME 45
181 #define RTW89_DFS_CHAN_TIME 105
182 #define RTW89_OFF_CHAN_TIME 100
183 #define RTW89_DWELL_TIME 20
184 #define RTW89_SCAN_WIDTH 0
185 #define RTW89_SCANOFLD_MAX_SSID 8
186 #define RTW89_SCANOFLD_MAX_IE_LEN 512
187 #define RTW89_SCANOFLD_PKT_NONE 0xFF
188 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F
189 #define RTW89_MAC_CHINFO_SIZE 20
190 
191 struct rtw89_mac_chinfo {
192 	u8 period;
193 	u8 dwell_time;
194 	u8 central_ch;
195 	u8 pri_ch;
196 	u8 bw:3;
197 	u8 notify_action:5;
198 	u8 num_pkt:4;
199 	u8 tx_pkt:1;
200 	u8 pause_data:1;
201 	u8 ch_band:2;
202 	u8 probe_id;
203 	u8 dfs_ch:1;
204 	u8 tx_null:1;
205 	u8 rand_seq_num:1;
206 	u8 cfg_tx_pwr:1;
207 	u8 rsvd0: 4;
208 	u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
209 	u16 tx_pwr_idx;
210 	u8 rsvd1;
211 	struct list_head list;
212 };
213 
214 struct rtw89_scan_option {
215 	bool enable;
216 	bool target_ch_mode;
217 };
218 
219 struct rtw89_pktofld_info {
220 	struct list_head list;
221 	u8 id;
222 };
223 
224 static inline void RTW89_SET_FWCMD_RA_IS_DIS(void *cmd, u32 val)
225 {
226 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(0));
227 }
228 
229 static inline void RTW89_SET_FWCMD_RA_MODE(void *cmd, u32 val)
230 {
231 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(5, 1));
232 }
233 
234 static inline void RTW89_SET_FWCMD_RA_BW_CAP(void *cmd, u32 val)
235 {
236 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 6));
237 }
238 
239 static inline void RTW89_SET_FWCMD_RA_MACID(void *cmd, u32 val)
240 {
241 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
242 }
243 
244 static inline void RTW89_SET_FWCMD_RA_DCM(void *cmd, u32 val)
245 {
246 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(16));
247 }
248 
249 static inline void RTW89_SET_FWCMD_RA_ER(void *cmd, u32 val)
250 {
251 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(17));
252 }
253 
254 static inline void RTW89_SET_FWCMD_RA_INIT_RATE_LV(void *cmd, u32 val)
255 {
256 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(19, 18));
257 }
258 
259 static inline void RTW89_SET_FWCMD_RA_UPD_ALL(void *cmd, u32 val)
260 {
261 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(20));
262 }
263 
264 static inline void RTW89_SET_FWCMD_RA_SGI(void *cmd, u32 val)
265 {
266 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(21));
267 }
268 
269 static inline void RTW89_SET_FWCMD_RA_LDPC(void *cmd, u32 val)
270 {
271 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(22));
272 }
273 
274 static inline void RTW89_SET_FWCMD_RA_STBC(void *cmd, u32 val)
275 {
276 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(23));
277 }
278 
279 static inline void RTW89_SET_FWCMD_RA_SS_NUM(void *cmd, u32 val)
280 {
281 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(26, 24));
282 }
283 
284 static inline void RTW89_SET_FWCMD_RA_GILTF(void *cmd, u32 val)
285 {
286 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(29, 27));
287 }
288 
289 static inline void RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(void *cmd, u32 val)
290 {
291 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(30));
292 }
293 
294 static inline void RTW89_SET_FWCMD_RA_UPD_MASK(void *cmd, u32 val)
295 {
296 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(31));
297 }
298 
299 static inline void RTW89_SET_FWCMD_RA_MASK_0(void *cmd, u32 val)
300 {
301 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(7, 0));
302 }
303 
304 static inline void RTW89_SET_FWCMD_RA_MASK_1(void *cmd, u32 val)
305 {
306 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(15, 8));
307 }
308 
309 static inline void RTW89_SET_FWCMD_RA_MASK_2(void *cmd, u32 val)
310 {
311 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(23, 16));
312 }
313 
314 static inline void RTW89_SET_FWCMD_RA_MASK_3(void *cmd, u32 val)
315 {
316 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 24));
317 }
318 
319 static inline void RTW89_SET_FWCMD_RA_MASK_4(void *cmd, u32 val)
320 {
321 	le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(7, 0));
322 }
323 
324 static inline void RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(void *cmd, u32 val)
325 {
326 	le32p_replace_bits((__le32 *)(cmd) + 0x02, val, BIT(31));
327 }
328 
329 static inline void RTW89_SET_FWCMD_RA_BAND_NUM(void *cmd, u32 val)
330 {
331 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(7, 0));
332 }
333 
334 static inline void RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(void *cmd, u32 val)
335 {
336 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(8));
337 }
338 
339 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(void *cmd, u32 val)
340 {
341 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(9));
342 }
343 
344 static inline void RTW89_SET_FWCMD_RA_CR_TBL_SEL(void *cmd, u32 val)
345 {
346 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(10));
347 }
348 
349 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(void *cmd, u32 val)
350 {
351 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(23, 16));
352 }
353 
354 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(void *cmd, u32 val)
355 {
356 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(25, 24));
357 }
358 
359 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(void *cmd, u32 val)
360 {
361 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(28, 26));
362 }
363 
364 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_BW(void *cmd, u32 val)
365 {
366 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 29));
367 }
368 
369 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)
370 {
371 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));
372 }
373 
374 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val)
375 {
376 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
377 }
378 
379 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val)
380 {
381 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16));
382 }
383 
384 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val)
385 {
386 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0));
387 }
388 
389 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val)
390 {
391 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4));
392 }
393 
394 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val)
395 {
396 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5));
397 }
398 
399 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val)
400 {
401 	le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0));
402 }
403 
404 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val)
405 {
406 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0));
407 }
408 
409 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val)
410 {
411 	le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0));
412 }
413 
414 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val)
415 {
416 	le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0));
417 }
418 
419 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val)
420 {
421 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0));
422 }
423 
424 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val)
425 {
426 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3));
427 }
428 
429 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val)
430 {
431 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4));
432 }
433 
434 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val)
435 {
436 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5));
437 }
438 
439 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val)
440 {
441 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0));
442 }
443 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)
444 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)
445 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)
446 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)
447 
448 #define GET_FWSECTION_HDR_SEC_SIZE(fwhdr)	\
449 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 0))
450 #define GET_FWSECTION_HDR_CHECKSUM(fwhdr)	\
451 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(28))
452 #define GET_FWSECTION_HDR_REDL(fwhdr)	\
453 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(29))
454 #define GET_FWSECTION_HDR_DL_ADDR(fwhdr)	\
455 	le32_get_bits(*((const __le32 *)(fwhdr)), GENMASK(31, 0))
456 
457 #define GET_FW_HDR_MAJOR_VERSION(fwhdr)	\
458 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(7, 0))
459 #define GET_FW_HDR_MINOR_VERSION(fwhdr)	\
460 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(15, 8))
461 #define GET_FW_HDR_SUBVERSION(fwhdr)	\
462 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 16))
463 #define GET_FW_HDR_SUBINDEX(fwhdr)	\
464 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(31, 24))
465 #define GET_FW_HDR_MONTH(fwhdr)		\
466 	le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(7, 0))
467 #define GET_FW_HDR_DATE(fwhdr)		\
468 	le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(15, 8))
469 #define GET_FW_HDR_HOUR(fwhdr)		\
470 	le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(23, 16))
471 #define GET_FW_HDR_MIN(fwhdr)		\
472 	le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(31, 24))
473 #define GET_FW_HDR_YEAR(fwhdr)		\
474 	le32_get_bits(*((const __le32 *)(fwhdr) + 5), GENMASK(31, 0))
475 #define GET_FW_HDR_SEC_NUM(fwhdr)	\
476 	le32_get_bits(*((const __le32 *)(fwhdr) + 6), GENMASK(15, 8))
477 #define GET_FW_HDR_CMD_VERSERION(fwhdr)	\
478 	le32_get_bits(*((const __le32 *)(fwhdr) + 7), GENMASK(31, 24))
479 static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val)
480 {
481 	le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0));
482 }
483 
484 static inline void SET_CTRL_INFO_MACID(void *table, u32 val)
485 {
486 	le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
487 }
488 
489 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val)
490 {
491 	le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
492 }
493 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)
494 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val)
495 {
496 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0));
497 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE,
498 			   GENMASK(8, 0));
499 }
500 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
501 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val)
502 {
503 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9));
504 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP,
505 			   BIT(9));
506 }
507 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0)
508 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val)
509 {
510 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10));
511 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW,
512 			   GENMASK(11, 10));
513 }
514 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0)
515 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val)
516 {
517 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12));
518 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF,
519 			   GENMASK(14, 12));
520 }
521 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
522 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val)
523 {
524 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
525 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX,
526 			   BIT(15));
527 }
528 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0)
529 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val)
530 {
531 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16));
532 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL,
533 			   GENMASK(19, 16));
534 }
535 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
536 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val)
537 {
538 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20));
539 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN,
540 			   BIT(20));
541 }
542 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
543 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val)
544 {
545 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21));
546 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN,
547 			   BIT(21));
548 }
549 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
550 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val)
551 {
552 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22));
553 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN,
554 			   BIT(22));
555 }
556 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
557 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val)
558 {
559 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23));
560 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN,
561 			   BIT(23));
562 }
563 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
564 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val)
565 {
566 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25));
567 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB,
568 			   BIT(25));
569 }
570 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
571 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val)
572 {
573 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26));
574 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB,
575 			   BIT(26));
576 }
577 #define SET_CMC_TBL_MASK_TRYRATE BIT(0)
578 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val)
579 {
580 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27));
581 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE,
582 			   BIT(27));
583 }
584 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0)
585 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val)
586 {
587 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28));
588 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY,
589 			   GENMASK(31, 28));
590 }
591 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)
592 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val)
593 {
594 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0));
595 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE,
596 			   GENMASK(8, 0));
597 }
598 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
599 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val)
600 {
601 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9));
602 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL,
603 			   BIT(9));
604 }
605 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
606 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val)
607 {
608 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10));
609 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL,
610 			   BIT(10));
611 }
612 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
613 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val)
614 {
615 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11));
616 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL,
617 			   BIT(11));
618 }
619 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0)
620 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val)
621 {
622 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12));
623 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT,
624 			   GENMASK(15, 12));
625 }
626 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)
627 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val)
628 {
629 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16));
630 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE,
631 			   GENMASK(24, 16));
632 }
633 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
634 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val)
635 {
636 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27));
637 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC,
638 			   BIT(27));
639 }
640 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0)
641 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val)
642 {
643 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28));
644 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE,
645 			   GENMASK(31, 28));
646 }
647 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0)
648 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val)
649 {
650 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0));
651 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT,
652 			   GENMASK(5, 0));
653 }
654 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
655 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val)
656 {
657 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6));
658 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL,
659 			   BIT(6));
660 }
661 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
662 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val)
663 {
664 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7));
665 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL,
666 			   BIT(7));
667 }
668 #define SET_CMC_TBL_MASK_RTS_EN BIT(0)
669 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val)
670 {
671 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8));
672 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN,
673 			   BIT(8));
674 }
675 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
676 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val)
677 {
678 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9));
679 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN,
680 			   BIT(9));
681 }
682 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0)
683 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val)
684 {
685 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10));
686 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS,
687 			   GENMASK(11, 10));
688 }
689 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
690 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val)
691 {
692 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12));
693 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN,
694 			   BIT(12));
695 }
696 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0)
697 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val)
698 {
699 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13));
700 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE,
701 			   GENMASK(14, 13));
702 }
703 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0)
704 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val)
705 {
706 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16));
707 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN,
708 			   GENMASK(26, 16));
709 }
710 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
711 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val)
712 {
713 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
714 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS,
715 			   BIT(27));
716 }
717 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0)
718 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val)
719 {
720 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28));
721 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME,
722 			   GENMASK(31, 28));
723 }
724 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)
725 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val)
726 {
727 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0));
728 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM,
729 			   GENMASK(7, 0));
730 }
731 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0)
732 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val)
733 {
734 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8));
735 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP,
736 			   GENMASK(9, 8));
737 }
738 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0)
739 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val)
740 {
741 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16));
742 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL,
743 			   GENMASK(18, 16));
744 }
745 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0)
746 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val)
747 {
748 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19));
749 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL,
750 			   GENMASK(21, 19));
751 }
752 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0)
753 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val)
754 {
755 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22));
756 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL,
757 			   GENMASK(24, 22));
758 }
759 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0)
760 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val)
761 {
762 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25));
763 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL,
764 			   GENMASK(27, 25));
765 }
766 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0)
767 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val)
768 {
769 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28));
770 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE,
771 			   GENMASK(31, 28));
772 }
773 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0)
774 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val)
775 {
776 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0));
777 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID,
778 			   GENMASK(2, 0));
779 }
780 #define SET_CMC_TBL_MASK_BMC BIT(0)
781 static inline void SET_CMC_TBL_BMC(void *table, u32 val)
782 {
783 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3));
784 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC,
785 			   BIT(3));
786 }
787 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0)
788 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val)
789 {
790 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4));
791 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID,
792 			   GENMASK(7, 4));
793 }
794 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
795 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val)
796 {
797 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
798 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR,
799 			   BIT(8));
800 }
801 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0)
802 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val)
803 {
804 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9));
805 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE,
806 			   GENMASK(11, 9));
807 }
808 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
809 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val)
810 {
811 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12));
812 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM,
813 			   BIT(12));
814 }
815 #define SET_CMC_TBL_MASK_DATA_ER BIT(0)
816 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val)
817 {
818 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13));
819 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER,
820 			   BIT(13));
821 }
822 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
823 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val)
824 {
825 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14));
826 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC,
827 			   BIT(14));
828 }
829 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
830 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val)
831 {
832 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
833 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC,
834 			   BIT(15));
835 }
836 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
837 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val)
838 {
839 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16));
840 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR,
841 			   BIT(16));
842 }
843 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
844 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val)
845 {
846 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17));
847 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH,
848 			   BIT(17));
849 }
850 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
851 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val)
852 {
853 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18));
854 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR,
855 			   BIT(18));
856 }
857 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
858 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val)
859 {
860 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19));
861 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS,
862 			   BIT(19));
863 }
864 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
865 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val)
866 {
867 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20));
868 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER,
869 			   BIT(20));
870 }
871 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
872 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val)
873 {
874 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21));
875 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN,
876 			   BIT(21));
877 }
878 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
879 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val)
880 {
881 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27));
882 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD,
883 			   BIT(27));
884 }
885 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0)
886 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val)
887 {
888 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28));
889 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT,
890 			   GENMASK(31, 28));
891 }
892 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)
893 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val)
894 {
895 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0));
896 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE,
897 			   GENMASK(8, 0));
898 }
899 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
900 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val)
901 {
902 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12));
903 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT,
904 			   BIT(12));
905 }
906 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
907 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val)
908 {
909 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13));
910 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT,
911 			   BIT(13));
912 }
913 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0)
914 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val)
915 {
916 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16));
917 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN,
918 			   GENMASK(19, 16));
919 }
920 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0)
921 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val)
922 {
923 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20));
924 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A,
925 			   GENMASK(21, 20));
926 }
927 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0)
928 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val)
929 {
930 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22));
931 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B,
932 			   GENMASK(23, 22));
933 }
934 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0)
935 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val)
936 {
937 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24));
938 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C,
939 			   GENMASK(25, 24));
940 }
941 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0)
942 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val)
943 {
944 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26));
945 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D,
946 			   GENMASK(27, 26));
947 }
948 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
949 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val)
950 {
951 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28));
952 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A,
953 			   BIT(28));
954 }
955 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
956 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val)
957 {
958 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29));
959 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B,
960 			   BIT(29));
961 }
962 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
963 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val)
964 {
965 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30));
966 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C,
967 			   BIT(30));
968 }
969 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
970 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val)
971 {
972 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31));
973 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D,
974 			   BIT(31));
975 }
976 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)
977 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val)
978 {
979 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
980 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX,
981 			   GENMASK(7, 0));
982 }
983 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)
984 static inline void SET_CMC_TBL_PAID(void *table, u32 val)
985 {
986 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8));
987 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID,
988 			   GENMASK(16, 8));
989 }
990 #define SET_CMC_TBL_MASK_ULDL BIT(0)
991 static inline void SET_CMC_TBL_ULDL(void *table, u32 val)
992 {
993 	le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17));
994 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL,
995 			   BIT(17));
996 }
997 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0)
998 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val)
999 {
1000 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18));
1001 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL,
1002 			   GENMASK(19, 18));
1003 }
1004 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0)
1005 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val)
1006 {
1007 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20));
1008 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1009 			   GENMASK(21, 20));
1010 }
1011 
1012 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val)
1013 {
1014 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22));
1015 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1016 			   GENMASK(23, 22));
1017 }
1018 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0)
1019 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val)
1020 {
1021 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24));
1022 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE,
1023 			   GENMASK(27, 24));
1024 }
1025 
1026 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val)
1027 {
1028 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30));
1029 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1030 			   GENMASK(31, 30));
1031 }
1032 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0)
1033 static inline void SET_CMC_TBL_NC(void *table, u32 val)
1034 {
1035 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0));
1036 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC,
1037 			   GENMASK(2, 0));
1038 }
1039 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0)
1040 static inline void SET_CMC_TBL_NR(void *table, u32 val)
1041 {
1042 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3));
1043 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR,
1044 			   GENMASK(5, 3));
1045 }
1046 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0)
1047 static inline void SET_CMC_TBL_NG(void *table, u32 val)
1048 {
1049 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6));
1050 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG,
1051 			   GENMASK(7, 6));
1052 }
1053 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0)
1054 static inline void SET_CMC_TBL_CB(void *table, u32 val)
1055 {
1056 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8));
1057 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB,
1058 			   GENMASK(9, 8));
1059 }
1060 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0)
1061 static inline void SET_CMC_TBL_CS(void *table, u32 val)
1062 {
1063 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10));
1064 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS,
1065 			   GENMASK(11, 10));
1066 }
1067 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
1068 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val)
1069 {
1070 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12));
1071 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN,
1072 			   BIT(12));
1073 }
1074 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
1075 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val)
1076 {
1077 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13));
1078 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN,
1079 			   BIT(13));
1080 }
1081 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
1082 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val)
1083 {
1084 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14));
1085 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN,
1086 			   BIT(14));
1087 }
1088 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
1089 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val)
1090 {
1091 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15));
1092 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN,
1093 			   BIT(15));
1094 }
1095 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)
1096 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val)
1097 {
1098 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16));
1099 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE,
1100 			   GENMASK(24, 16));
1101 }
1102 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0)
1103 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val)
1104 {
1105 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25));
1106 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF,
1107 			   GENMASK(27, 25));
1108 }
1109 #define SET_CMC_TBL_MASK_CSI_GID_SEL BIT(0)
1110 static inline void SET_CMC_TBL_CSI_GID_SEL(void *table, u32 val)
1111 {
1112 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(29));
1113 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GID_SEL,
1114 			   BIT(29));
1115 }
1116 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0)
1117 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val)
1118 {
1119 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30));
1120 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW,
1121 			   GENMASK(31, 30));
1122 }
1123 
1124 static inline void SET_BCN_UPD_PORT(void *h2c, u32 val)
1125 {
1126 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1127 }
1128 
1129 static inline void SET_BCN_UPD_MBSSID(void *h2c, u32 val)
1130 {
1131 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1132 }
1133 
1134 static inline void SET_BCN_UPD_BAND(void *h2c, u32 val)
1135 {
1136 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1137 }
1138 
1139 static inline void SET_BCN_UPD_GRP_IE_OFST(void *h2c, u32 val)
1140 {
1141 	le32p_replace_bits((__le32 *)h2c, (val - 24) | BIT(7), GENMASK(31, 24));
1142 }
1143 
1144 static inline void SET_BCN_UPD_MACID(void *h2c, u32 val)
1145 {
1146 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1147 }
1148 
1149 static inline void SET_BCN_UPD_SSN_SEL(void *h2c, u32 val)
1150 {
1151 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(9, 8));
1152 }
1153 
1154 static inline void SET_BCN_UPD_SSN_MODE(void *h2c, u32 val)
1155 {
1156 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(11, 10));
1157 }
1158 
1159 static inline void SET_BCN_UPD_RATE(void *h2c, u32 val)
1160 {
1161 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(20, 12));
1162 }
1163 
1164 static inline void SET_BCN_UPD_TXPWR(void *h2c, u32 val)
1165 {
1166 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(23, 21));
1167 }
1168 
1169 static inline void SET_BCN_UPD_TXINFO_CTRL_EN(void *h2c, u32 val)
1170 {
1171 	le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(0));
1172 }
1173 
1174 static inline void SET_BCN_UPD_NTX_PATH_EN(void *h2c, u32 val)
1175 {
1176 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(4, 1));
1177 }
1178 
1179 static inline void SET_BCN_UPD_PATH_MAP_A(void *h2c, u32 val)
1180 {
1181 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(6, 5));
1182 }
1183 
1184 static inline void SET_BCN_UPD_PATH_MAP_B(void *h2c, u32 val)
1185 {
1186 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(8, 7));
1187 }
1188 
1189 static inline void SET_BCN_UPD_PATH_MAP_C(void *h2c, u32 val)
1190 {
1191 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(10, 9));
1192 }
1193 
1194 static inline void SET_BCN_UPD_PATH_MAP_D(void *h2c, u32 val)
1195 {
1196 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(12, 11));
1197 }
1198 
1199 static inline void SET_BCN_UPD_PATH_ANTSEL_A(void *h2c, u32 val)
1200 {
1201 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  BIT(13));
1202 }
1203 
1204 static inline void SET_BCN_UPD_PATH_ANTSEL_B(void *h2c, u32 val)
1205 {
1206 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  BIT(14));
1207 }
1208 
1209 static inline void SET_BCN_UPD_PATH_ANTSEL_C(void *h2c, u32 val)
1210 {
1211 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  BIT(15));
1212 }
1213 
1214 static inline void SET_BCN_UPD_PATH_ANTSEL_D(void *h2c, u32 val)
1215 {
1216 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  BIT(16));
1217 }
1218 
1219 static inline void SET_BCN_UPD_CSA_OFST(void *h2c, u32 val)
1220 {
1221 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(31, 17));
1222 }
1223 
1224 static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val)
1225 {
1226 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1227 }
1228 
1229 static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val)
1230 {
1231 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8));
1232 }
1233 
1234 static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val)
1235 {
1236 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10));
1237 }
1238 
1239 static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val)
1240 {
1241 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13));
1242 }
1243 
1244 static inline void SET_JOININFO_MACID(void *h2c, u32 val)
1245 {
1246 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1247 }
1248 
1249 static inline void SET_JOININFO_OP(void *h2c, u32 val)
1250 {
1251 	le32p_replace_bits((__le32 *)h2c, val, BIT(8));
1252 }
1253 
1254 static inline void SET_JOININFO_BAND(void *h2c, u32 val)
1255 {
1256 	le32p_replace_bits((__le32 *)h2c, val, BIT(9));
1257 }
1258 
1259 static inline void SET_JOININFO_WMM(void *h2c, u32 val)
1260 {
1261 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10));
1262 }
1263 
1264 static inline void SET_JOININFO_TGR(void *h2c, u32 val)
1265 {
1266 	le32p_replace_bits((__le32 *)h2c, val, BIT(12));
1267 }
1268 
1269 static inline void SET_JOININFO_ISHESTA(void *h2c, u32 val)
1270 {
1271 	le32p_replace_bits((__le32 *)h2c, val, BIT(13));
1272 }
1273 
1274 static inline void SET_JOININFO_DLBW(void *h2c, u32 val)
1275 {
1276 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14));
1277 }
1278 
1279 static inline void SET_JOININFO_TF_MAC_PAD(void *h2c, u32 val)
1280 {
1281 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16));
1282 }
1283 
1284 static inline void SET_JOININFO_DL_T_PE(void *h2c, u32 val)
1285 {
1286 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18));
1287 }
1288 
1289 static inline void SET_JOININFO_PORT_ID(void *h2c, u32 val)
1290 {
1291 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21));
1292 }
1293 
1294 static inline void SET_JOININFO_NET_TYPE(void *h2c, u32 val)
1295 {
1296 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24));
1297 }
1298 
1299 static inline void SET_JOININFO_WIFI_ROLE(void *h2c, u32 val)
1300 {
1301 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26));
1302 }
1303 
1304 static inline void SET_JOININFO_SELF_ROLE(void *h2c, u32 val)
1305 {
1306 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30));
1307 }
1308 
1309 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val)
1310 {
1311 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1312 }
1313 
1314 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val)
1315 {
1316 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1317 }
1318 
1319 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val)
1320 {
1321 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1322 }
1323 
1324 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val)
1325 {
1326 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1327 }
1328 
1329 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val)
1330 {
1331 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1332 }
1333 
1334 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val)
1335 {
1336 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1337 }
1338 
1339 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val)
1340 {
1341 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1342 }
1343 
1344 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val)
1345 {
1346 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1347 }
1348 
1349 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val)
1350 {
1351 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
1352 }
1353 
1354 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val)
1355 {
1356 	le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0));
1357 }
1358 
1359 static inline void SET_BA_CAM_VALID(void *h2c, u32 val)
1360 {
1361 	le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1362 }
1363 
1364 static inline void SET_BA_CAM_INIT_REQ(void *h2c, u32 val)
1365 {
1366 	le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1367 }
1368 
1369 static inline void SET_BA_CAM_ENTRY_IDX(void *h2c, u32 val)
1370 {
1371 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2));
1372 }
1373 
1374 static inline void SET_BA_CAM_TID(void *h2c, u32 val)
1375 {
1376 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4));
1377 }
1378 
1379 static inline void SET_BA_CAM_MACID(void *h2c, u32 val)
1380 {
1381 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1382 }
1383 
1384 static inline void SET_BA_CAM_BMAP_SIZE(void *h2c, u32 val)
1385 {
1386 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1387 }
1388 
1389 static inline void SET_BA_CAM_SSN(void *h2c, u32 val)
1390 {
1391 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20));
1392 }
1393 
1394 static inline void SET_BA_CAM_UID(void *h2c, u32 val)
1395 {
1396 	le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(7, 0));
1397 }
1398 
1399 static inline void SET_BA_CAM_STD_EN(void *h2c, u32 val)
1400 {
1401 	le32p_replace_bits((__le32 *)h2c + 1, val, BIT(8));
1402 }
1403 
1404 static inline void SET_BA_CAM_BAND(void *h2c, u32 val)
1405 {
1406 	le32p_replace_bits((__le32 *)h2c + 1, val, BIT(9));
1407 }
1408 
1409 static inline void SET_BA_CAM_ENTRY_IDX_V1(void *h2c, u32 val)
1410 {
1411 	le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 28));
1412 }
1413 
1414 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val)
1415 {
1416 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1417 }
1418 
1419 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val)
1420 {
1421 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1422 }
1423 
1424 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val)
1425 {
1426 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1427 }
1428 
1429 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val)
1430 {
1431 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20));
1432 }
1433 
1434 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val)
1435 {
1436 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1437 }
1438 
1439 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val)
1440 {
1441 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0));
1442 }
1443 
1444 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val)
1445 {
1446 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1));
1447 }
1448 
1449 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val)
1450 {
1451 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2));
1452 }
1453 
1454 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val)
1455 {
1456 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3));
1457 }
1458 
1459 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val)
1460 {
1461 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1462 }
1463 
1464 enum rtw89_btc_btf_h2c_class {
1465 	BTFC_SET = 0x10,
1466 	BTFC_GET = 0x11,
1467 	BTFC_FW_EVENT = 0x12,
1468 };
1469 
1470 enum rtw89_btc_btf_set {
1471 	SET_REPORT_EN = 0x0,
1472 	SET_SLOT_TABLE,
1473 	SET_MREG_TABLE,
1474 	SET_CX_POLICY,
1475 	SET_GPIO_DBG,
1476 	SET_DRV_INFO,
1477 	SET_DRV_EVENT,
1478 	SET_BT_WREG_ADDR,
1479 	SET_BT_WREG_VAL,
1480 	SET_BT_RREG_ADDR,
1481 	SET_BT_WL_CH_INFO,
1482 	SET_BT_INFO_REPORT,
1483 	SET_BT_IGNORE_WLAN_ACT,
1484 	SET_BT_TX_PWR,
1485 	SET_BT_LNA_CONSTRAIN,
1486 	SET_BT_GOLDEN_RX_RANGE,
1487 	SET_BT_PSD_REPORT,
1488 	SET_H2C_TEST,
1489 	SET_MAX1,
1490 };
1491 
1492 enum rtw89_btc_cxdrvinfo {
1493 	CXDRVINFO_INIT = 0,
1494 	CXDRVINFO_ROLE,
1495 	CXDRVINFO_DBCC,
1496 	CXDRVINFO_SMAP,
1497 	CXDRVINFO_RFK,
1498 	CXDRVINFO_RUN,
1499 	CXDRVINFO_CTRL,
1500 	CXDRVINFO_SCAN,
1501 	CXDRVINFO_MAX,
1502 };
1503 
1504 enum rtw89_scan_mode {
1505 	RTW89_SCAN_IMMEDIATE,
1506 };
1507 
1508 enum rtw89_scan_type {
1509 	RTW89_SCAN_ONCE,
1510 };
1511 
1512 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val)
1513 {
1514 	u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0));
1515 }
1516 
1517 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val)
1518 {
1519 	u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0));
1520 }
1521 
1522 static inline void RTW89_SET_FWCMD_CXINIT_ANT_TYPE(void *cmd, u8 val)
1523 {
1524 	u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0));
1525 }
1526 
1527 static inline void RTW89_SET_FWCMD_CXINIT_ANT_NUM(void *cmd, u8 val)
1528 {
1529 	u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0));
1530 }
1531 
1532 static inline void RTW89_SET_FWCMD_CXINIT_ANT_ISO(void *cmd, u8 val)
1533 {
1534 	u8p_replace_bits((u8 *)(cmd) + 4, val, GENMASK(7, 0));
1535 }
1536 
1537 static inline void RTW89_SET_FWCMD_CXINIT_ANT_POS(void *cmd, u8 val)
1538 {
1539 	u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(0));
1540 }
1541 
1542 static inline void RTW89_SET_FWCMD_CXINIT_ANT_DIVERSITY(void *cmd, u8 val)
1543 {
1544 	u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(1));
1545 }
1546 
1547 static inline void RTW89_SET_FWCMD_CXINIT_MOD_RFE(void *cmd, u8 val)
1548 {
1549 	u8p_replace_bits((u8 *)(cmd) + 6, val, GENMASK(7, 0));
1550 }
1551 
1552 static inline void RTW89_SET_FWCMD_CXINIT_MOD_CV(void *cmd, u8 val)
1553 {
1554 	u8p_replace_bits((u8 *)(cmd) + 7, val, GENMASK(7, 0));
1555 }
1556 
1557 static inline void RTW89_SET_FWCMD_CXINIT_MOD_BT_SOLO(void *cmd, u8 val)
1558 {
1559 	u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(0));
1560 }
1561 
1562 static inline void RTW89_SET_FWCMD_CXINIT_MOD_BT_POS(void *cmd, u8 val)
1563 {
1564 	u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(1));
1565 }
1566 
1567 static inline void RTW89_SET_FWCMD_CXINIT_MOD_SW_TYPE(void *cmd, u8 val)
1568 {
1569 	u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(2));
1570 }
1571 
1572 static inline void RTW89_SET_FWCMD_CXINIT_WL_GCH(void *cmd, u8 val)
1573 {
1574 	u8p_replace_bits((u8 *)(cmd) + 10, val, GENMASK(7, 0));
1575 }
1576 
1577 static inline void RTW89_SET_FWCMD_CXINIT_WL_ONLY(void *cmd, u8 val)
1578 {
1579 	u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(0));
1580 }
1581 
1582 static inline void RTW89_SET_FWCMD_CXINIT_WL_INITOK(void *cmd, u8 val)
1583 {
1584 	u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(1));
1585 }
1586 
1587 static inline void RTW89_SET_FWCMD_CXINIT_DBCC_EN(void *cmd, u8 val)
1588 {
1589 	u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(2));
1590 }
1591 
1592 static inline void RTW89_SET_FWCMD_CXINIT_CX_OTHER(void *cmd, u8 val)
1593 {
1594 	u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(3));
1595 }
1596 
1597 static inline void RTW89_SET_FWCMD_CXINIT_BT_ONLY(void *cmd, u8 val)
1598 {
1599 	u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(4));
1600 }
1601 
1602 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val)
1603 {
1604 	u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0));
1605 }
1606 
1607 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val)
1608 {
1609 	u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0));
1610 }
1611 
1612 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val)
1613 {
1614 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0));
1615 }
1616 
1617 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val)
1618 {
1619 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1));
1620 }
1621 
1622 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val)
1623 {
1624 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2));
1625 }
1626 
1627 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val)
1628 {
1629 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3));
1630 }
1631 
1632 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val)
1633 {
1634 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4));
1635 }
1636 
1637 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val)
1638 {
1639 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5));
1640 }
1641 
1642 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val)
1643 {
1644 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6));
1645 }
1646 
1647 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val)
1648 {
1649 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7));
1650 }
1651 
1652 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val)
1653 {
1654 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8));
1655 }
1656 
1657 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val)
1658 {
1659 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9));
1660 }
1661 
1662 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val)
1663 {
1664 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10));
1665 }
1666 
1667 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val)
1668 {
1669 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11));
1670 }
1671 
1672 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n)
1673 {
1674 	u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(0));
1675 }
1676 
1677 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n)
1678 {
1679 	u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, GENMASK(3, 1));
1680 }
1681 
1682 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n)
1683 {
1684 	u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(4));
1685 }
1686 
1687 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n)
1688 {
1689 	u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(5));
1690 }
1691 
1692 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n)
1693 {
1694 	u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, GENMASK(7, 6));
1695 }
1696 
1697 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n)
1698 {
1699 	u8p_replace_bits((u8 *)(cmd) + (7 + 12 * (n)), val, BIT(0));
1700 }
1701 
1702 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n)
1703 {
1704 	u8p_replace_bits((u8 *)(cmd) + (7 + 12 * (n)), val, GENMASK(7, 1));
1705 }
1706 
1707 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n)
1708 {
1709 	u8p_replace_bits((u8 *)(cmd) + (8 + 12 * (n)), val, GENMASK(7, 0));
1710 }
1711 
1712 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n)
1713 {
1714 	u8p_replace_bits((u8 *)(cmd) + (9 + 12 * (n)), val, GENMASK(7, 0));
1715 }
1716 
1717 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n)
1718 {
1719 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + (10 + 12 * (n))), val, GENMASK(15, 0));
1720 }
1721 
1722 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n)
1723 {
1724 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + (12 + 12 * (n))), val, GENMASK(15, 0));
1725 }
1726 
1727 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n)
1728 {
1729 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + (14 + 12 * (n))), val, GENMASK(15, 0));
1730 }
1731 
1732 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n)
1733 {
1734 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + (16 + 12 * (n))), val, GENMASK(15, 0));
1735 }
1736 
1737 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val)
1738 {
1739 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0));
1740 }
1741 
1742 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val)
1743 {
1744 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1));
1745 }
1746 
1747 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val)
1748 {
1749 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2));
1750 }
1751 
1752 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val)
1753 {
1754 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3));
1755 }
1756 
1757 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val)
1758 {
1759 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0));
1760 }
1761 
1762 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val)
1763 {
1764 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2));
1765 }
1766 
1767 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val)
1768 {
1769 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6));
1770 }
1771 
1772 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val)
1773 {
1774 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8));
1775 }
1776 
1777 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val)
1778 {
1779 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10));
1780 }
1781 
1782 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val)
1783 {
1784 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
1785 }
1786 
1787 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val)
1788 {
1789 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8));
1790 }
1791 
1792 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val)
1793 {
1794 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16));
1795 }
1796 
1797 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_NUM(void *cmd, u32 val)
1798 {
1799 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
1800 }
1801 
1802 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_SIZE(void *cmd, u32 val)
1803 {
1804 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8));
1805 }
1806 
1807 static inline void RTW89_SET_FWCMD_CHINFO_PERIOD(void *cmd, u32 val)
1808 {
1809 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
1810 }
1811 
1812 static inline void RTW89_SET_FWCMD_CHINFO_DWELL(void *cmd, u32 val)
1813 {
1814 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8));
1815 }
1816 
1817 static inline void RTW89_SET_FWCMD_CHINFO_CENTER_CH(void *cmd, u32 val)
1818 {
1819 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 16));
1820 }
1821 
1822 static inline void RTW89_SET_FWCMD_CHINFO_PRI_CH(void *cmd, u32 val)
1823 {
1824 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 24));
1825 }
1826 
1827 static inline void RTW89_SET_FWCMD_CHINFO_BW(void *cmd, u32 val)
1828 {
1829 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(2, 0));
1830 }
1831 
1832 static inline void RTW89_SET_FWCMD_CHINFO_ACTION(void *cmd, u32 val)
1833 {
1834 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 3));
1835 }
1836 
1837 static inline void RTW89_SET_FWCMD_CHINFO_NUM_PKT(void *cmd, u32 val)
1838 {
1839 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(11, 8));
1840 }
1841 
1842 static inline void RTW89_SET_FWCMD_CHINFO_TX(void *cmd, u32 val)
1843 {
1844 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(12));
1845 }
1846 
1847 static inline void RTW89_SET_FWCMD_CHINFO_PAUSE_DATA(void *cmd, u32 val)
1848 {
1849 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(13));
1850 }
1851 
1852 static inline void RTW89_SET_FWCMD_CHINFO_BAND(void *cmd, u32 val)
1853 {
1854 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 14));
1855 }
1856 
1857 static inline void RTW89_SET_FWCMD_CHINFO_PKT_ID(void *cmd, u32 val)
1858 {
1859 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16));
1860 }
1861 
1862 static inline void RTW89_SET_FWCMD_CHINFO_DFS(void *cmd, u32 val)
1863 {
1864 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(24));
1865 }
1866 
1867 static inline void RTW89_SET_FWCMD_CHINFO_TX_NULL(void *cmd, u32 val)
1868 {
1869 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(25));
1870 }
1871 
1872 static inline void RTW89_SET_FWCMD_CHINFO_RANDOM(void *cmd, u32 val)
1873 {
1874 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(26));
1875 }
1876 
1877 static inline void RTW89_SET_FWCMD_CHINFO_CFG_TX(void *cmd, u32 val)
1878 {
1879 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(27));
1880 }
1881 
1882 static inline void RTW89_SET_FWCMD_CHINFO_PKT0(void *cmd, u32 val)
1883 {
1884 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(7, 0));
1885 }
1886 
1887 static inline void RTW89_SET_FWCMD_CHINFO_PKT1(void *cmd, u32 val)
1888 {
1889 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 8));
1890 }
1891 
1892 static inline void RTW89_SET_FWCMD_CHINFO_PKT2(void *cmd, u32 val)
1893 {
1894 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16));
1895 }
1896 
1897 static inline void RTW89_SET_FWCMD_CHINFO_PKT3(void *cmd, u32 val)
1898 {
1899 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(31, 24));
1900 }
1901 
1902 static inline void RTW89_SET_FWCMD_CHINFO_PKT4(void *cmd, u32 val)
1903 {
1904 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(7, 0));
1905 }
1906 
1907 static inline void RTW89_SET_FWCMD_CHINFO_PKT5(void *cmd, u32 val)
1908 {
1909 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(15, 8));
1910 }
1911 
1912 static inline void RTW89_SET_FWCMD_CHINFO_PKT6(void *cmd, u32 val)
1913 {
1914 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(23, 16));
1915 }
1916 
1917 static inline void RTW89_SET_FWCMD_CHINFO_PKT7(void *cmd, u32 val)
1918 {
1919 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 24));
1920 }
1921 
1922 static inline void RTW89_SET_FWCMD_CHINFO_POWER_IDX(void *cmd, u32 val)
1923 {
1924 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(15, 0));
1925 }
1926 
1927 static inline void RTW89_SET_FWCMD_SCANOFLD_MACID(void *cmd, u32 val)
1928 {
1929 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
1930 }
1931 
1932 static inline void RTW89_SET_FWCMD_SCANOFLD_NORM_CY(void *cmd, u32 val)
1933 {
1934 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8));
1935 }
1936 
1937 static inline void RTW89_SET_FWCMD_SCANOFLD_PORT_ID(void *cmd, u32 val)
1938 {
1939 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(18, 16));
1940 }
1941 
1942 static inline void RTW89_SET_FWCMD_SCANOFLD_BAND(void *cmd, u32 val)
1943 {
1944 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, BIT(19));
1945 }
1946 
1947 static inline void RTW89_SET_FWCMD_SCANOFLD_OPERATION(void *cmd, u32 val)
1948 {
1949 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(21, 20));
1950 }
1951 
1952 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_BAND(void *cmd, u32 val)
1953 {
1954 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 22));
1955 }
1956 
1957 static inline void RTW89_SET_FWCMD_SCANOFLD_NOTIFY_END(void *cmd, u32 val)
1958 {
1959 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(0));
1960 }
1961 
1962 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_MODE(void *cmd, u32 val)
1963 {
1964 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(1));
1965 }
1966 
1967 static inline void RTW89_SET_FWCMD_SCANOFLD_START_MODE(void *cmd, u32 val)
1968 {
1969 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(2));
1970 }
1971 
1972 static inline void RTW89_SET_FWCMD_SCANOFLD_SCAN_TYPE(void *cmd, u32 val)
1973 {
1974 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(4, 3));
1975 }
1976 
1977 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_BW(void *cmd, u32 val)
1978 {
1979 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 5));
1980 }
1981 
1982 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_PRI_CH(void *cmd, u32 val)
1983 {
1984 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 8));
1985 }
1986 
1987 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CENTRAL_CH(void *cmd,
1988 							      u32 val)
1989 {
1990 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16));
1991 }
1992 
1993 static inline void RTW89_SET_FWCMD_SCANOFLD_PROBE_REQ_PKT_ID(void *cmd, u32 val)
1994 {
1995 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(31, 24));
1996 }
1997 
1998 static inline void RTW89_SET_FWCMD_SCANOFLD_NORM_PD(void *cmd, u32 val)
1999 {
2000 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 0));
2001 }
2002 
2003 static inline void RTW89_SET_FWCMD_SCANOFLD_SLOW_PD(void *cmd, u32 val)
2004 {
2005 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16));
2006 }
2007 
2008 static inline void RTW89_SET_FWCMD_SCANOFLD_TSF_HIGH(void *cmd, u32 val)
2009 {
2010 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 0));
2011 }
2012 
2013 static inline void RTW89_SET_FWCMD_SCANOFLD_TSF_SLOW(void *cmd, u32 val)
2014 {
2015 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(31, 0));
2016 }
2017 
2018 #define RTW89_C2H_HEADER_LEN 8
2019 
2020 #define RTW89_GET_C2H_CATEGORY(c2h) \
2021 	le32_get_bits(*((const __le32 *)c2h), GENMASK(1, 0))
2022 #define RTW89_GET_C2H_CLASS(c2h) \
2023 	le32_get_bits(*((const __le32 *)c2h), GENMASK(7, 2))
2024 #define RTW89_GET_C2H_FUNC(c2h) \
2025 	le32_get_bits(*((const __le32 *)c2h), GENMASK(15, 8))
2026 #define RTW89_GET_C2H_LEN(c2h) \
2027 	le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(13, 0))
2028 
2029 #define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2)
2030 #define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN)
2031 
2032 #define RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h) \
2033 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
2034 #define RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h) \
2035 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
2036 #define RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h) \
2037 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
2038 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h) \
2039 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
2040 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h) \
2041 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24))
2042 
2043 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \
2044 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
2045 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \
2046 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
2047 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \
2048 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
2049 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \
2050 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
2051 
2052 #define RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h) \
2053 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 0))
2054 #define RTW89_GET_PHY_C2H_RA_RPT_RETRY_RATIO(c2h) \
2055 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
2056 #define RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h) \
2057 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(6, 0))
2058 #define RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h) \
2059 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(9, 8))
2060 #define RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h) \
2061 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(12, 10))
2062 #define RTW89_GET_PHY_C2H_RA_RPT_BW(c2h) \
2063 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(14, 13))
2064 
2065 /* VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
2066  * HT-new: [6:5]: NA, [4:0]: MCS
2067  */
2068 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
2069 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
2070 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
2071 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
2072 				    FIELD_PREP(GENMASK(2, 0), mcs))
2073 
2074 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \
2075 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
2076 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \
2077 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))
2078 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \
2079 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))
2080 
2081 #define RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h) \
2082 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
2083 #define RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h) \
2084 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(19, 16))
2085 #define RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h) \
2086 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 20))
2087 #define RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h) \
2088 	le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(3, 0))
2089 #define RTW89_GET_MAC_C2H_SCANOFLD_AIR_DENSITY(c2h) \
2090 	le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(7, 4))
2091 #define RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h) \
2092 	le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(25, 24))
2093 
2094 #define RTW89_FW_HDR_SIZE 32
2095 #define RTW89_FW_SECTION_HDR_SIZE 16
2096 
2097 #define RTW89_MFW_SIG	0xFF
2098 
2099 struct rtw89_mfw_info {
2100 	u8 cv;
2101 	u8 type; /* enum rtw89_fw_type */
2102 	u8 mp;
2103 	u8 rsvd;
2104 	__le32 shift;
2105 	__le32 size;
2106 	u8 rsvd2[4];
2107 } __packed;
2108 
2109 struct rtw89_mfw_hdr {
2110 	u8 sig;	/* RTW89_MFW_SIG */
2111 	u8 fw_nr;
2112 	u8 rsvd[14];
2113 	struct rtw89_mfw_info info[];
2114 } __packed;
2115 
2116 struct fwcmd_hdr {
2117 	__le32 hdr0;
2118 	__le32 hdr1;
2119 };
2120 
2121 #define RTW89_H2C_RF_PAGE_SIZE 500
2122 #define RTW89_H2C_RF_PAGE_NUM 3
2123 struct rtw89_fw_h2c_rf_reg_info {
2124 	enum rtw89_rf_path rf_path;
2125 	__le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE];
2126 	u16 curr_idx;
2127 };
2128 
2129 #define H2C_SEC_CAM_LEN			24
2130 
2131 #define H2C_HEADER_LEN			8
2132 #define H2C_HDR_CAT			GENMASK(1, 0)
2133 #define H2C_HDR_CLASS			GENMASK(7, 2)
2134 #define H2C_HDR_FUNC			GENMASK(15, 8)
2135 #define H2C_HDR_DEL_TYPE		GENMASK(19, 16)
2136 #define H2C_HDR_H2C_SEQ			GENMASK(31, 24)
2137 #define H2C_HDR_TOTAL_LEN		GENMASK(13, 0)
2138 #define H2C_HDR_REC_ACK			BIT(14)
2139 #define H2C_HDR_DONE_ACK		BIT(15)
2140 
2141 #define FWCMD_TYPE_H2C			0
2142 
2143 #define H2C_CAT_MAC		0x1
2144 
2145 /* CLASS 0 - FW INFO */
2146 #define H2C_CL_FW_INFO			0x0
2147 #define H2C_FUNC_LOG_CFG		0x0
2148 #define H2C_FUNC_MAC_GENERAL_PKT	0x1
2149 
2150 /* CLASS 2 - PS */
2151 #define H2C_CL_MAC_PS			0x2
2152 #define H2C_FUNC_MAC_LPS_PARM		0x0
2153 
2154 /* CLASS 3 - FW download */
2155 #define H2C_CL_MAC_FWDL		0x3
2156 #define H2C_FUNC_MAC_FWHDR_DL		0x0
2157 
2158 /* CLASS 5 - Frame Exchange */
2159 #define H2C_CL_MAC_FR_EXCHG		0x5
2160 #define H2C_FUNC_MAC_CCTLINFO_UD	0x2
2161 #define H2C_FUNC_MAC_BCN_UPD		0x5
2162 
2163 /* CLASS 6 - Address CAM */
2164 #define H2C_CL_MAC_ADDR_CAM_UPDATE	0x6
2165 #define H2C_FUNC_MAC_ADDR_CAM_UPD	0x0
2166 
2167 /* CLASS 8 - Media Status Report */
2168 #define H2C_CL_MAC_MEDIA_RPT		0x8
2169 #define H2C_FUNC_MAC_JOININFO		0x0
2170 #define H2C_FUNC_MAC_FWROLE_MAINTAIN	0x4
2171 
2172 /* CLASS 9 - FW offload */
2173 #define H2C_CL_MAC_FW_OFLD		0x9
2174 #define H2C_FUNC_PACKET_OFLD		0x1
2175 #define H2C_FUNC_MAC_MACID_PAUSE	0x8
2176 #define H2C_FUNC_USR_EDCA		0xF
2177 #define H2C_FUNC_OFLD_CFG		0x14
2178 #define H2C_FUNC_ADD_SCANOFLD_CH	0x16
2179 #define H2C_FUNC_SCANOFLD		0x17
2180 
2181 /* CLASS 10 - Security CAM */
2182 #define H2C_CL_MAC_SEC_CAM		0xa
2183 #define H2C_FUNC_MAC_SEC_UPD		0x1
2184 
2185 /* CLASS 12 - BA CAM */
2186 #define H2C_CL_BA_CAM			0xc
2187 #define H2C_FUNC_MAC_BA_CAM		0x0
2188 
2189 #define H2C_CAT_OUTSRC			0x2
2190 
2191 #define H2C_CL_OUTSRC_RA		0x1
2192 #define H2C_FUNC_OUTSRC_RA_MACIDCFG	0x0
2193 
2194 #define H2C_CL_OUTSRC_RF_REG_A		0x8
2195 #define H2C_CL_OUTSRC_RF_REG_B		0x9
2196 
2197 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev);
2198 int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
2199 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type);
2200 int rtw89_load_firmware(struct rtw89_dev *rtwdev);
2201 void rtw89_unload_firmware(struct rtw89_dev *rtwdev);
2202 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev);
2203 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb,
2204 			   u8 type, u8 cat, u8 class, u8 func,
2205 			   bool rack, bool dack, u32 len);
2206 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
2207 				  struct rtw89_vif *rtwvif);
2208 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
2209 				struct ieee80211_vif *vif,
2210 				struct ieee80211_sta *sta);
2211 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
2212 				 struct rtw89_sta *rtwsta);
2213 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev,
2214 			       struct rtw89_vif *rtwvif);
2215 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif,
2216 		     struct rtw89_sta *rtwsta, const u8 *scan_mac_addr);
2217 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h);
2218 void rtw89_fw_c2h_work(struct work_struct *work);
2219 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev,
2220 			       struct rtw89_vif *rtwvif,
2221 			       struct rtw89_sta *rtwsta,
2222 			       enum rtw89_upd_mode upd_mode);
2223 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
2224 			   struct rtw89_sta *rtwsta, bool dis_conn);
2225 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp,
2226 			     bool pause);
2227 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
2228 			  u8 ac, u32 val);
2229 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev);
2230 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi);
2231 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev);
2232 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev);
2233 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev);
2234 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev);
2235 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id);
2236 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
2237 				 struct sk_buff *skb_ofld);
2238 int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int len,
2239 				   struct list_head *chan_list);
2240 int rtw89_fw_h2c_scan_offload(struct rtw89_dev *rtwdev,
2241 			      struct rtw89_scan_option *opt,
2242 			      struct rtw89_vif *vif);
2243 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
2244 			struct rtw89_fw_h2c_rf_reg_info *info,
2245 			u16 len, u8 page);
2246 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
2247 			      u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
2248 			      bool rack, bool dack);
2249 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len);
2250 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev);
2251 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
2252 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, u8 macid);
2253 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
2254 			bool valid, struct ieee80211_ampdu_params *params);
2255 
2256 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,
2257 			  struct rtw89_lps_parm *lps_param);
2258 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(u32 len);
2259 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(u32 len);
2260 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev,
2261 		     struct rtw89_mac_h2c_info *h2c_info,
2262 		     struct rtw89_mac_c2h_info *c2h_info);
2263 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable);
2264 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev);
2265 void rtw89_store_op_chan(struct rtw89_dev *rtwdev);
2266 void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
2267 			 struct ieee80211_scan_request *req);
2268 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
2269 			    bool aborted);
2270 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
2271 			  bool enable);
2272 void rtw89_hw_scan_status_report(struct rtw89_dev *rtwdev, struct sk_buff *skb);
2273 void rtw89_hw_scan_chan_switch(struct rtw89_dev *rtwdev, struct sk_buff *skb);
2274 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
2275 void rtw89_store_op_chan(struct rtw89_dev *rtwdev);
2276 
2277 #endif
2278