1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_FW_H__ 6 #define __RTW89_FW_H__ 7 8 #include "core.h" 9 10 enum rtw89_fw_dl_status { 11 RTW89_FWDL_INITIAL_STATE = 0, 12 RTW89_FWDL_FWDL_ONGOING = 1, 13 RTW89_FWDL_CHECKSUM_FAIL = 2, 14 RTW89_FWDL_SECURITY_FAIL = 3, 15 RTW89_FWDL_CV_NOT_MATCH = 4, 16 RTW89_FWDL_RSVD0 = 5, 17 RTW89_FWDL_WCPU_FWDL_RDY = 6, 18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7 19 }; 20 21 #define RTW89_GET_C2H_HDR_FUNC(info) \ 22 u32_get_bits(info, GENMASK(6, 0)) 23 #define RTW89_GET_C2H_HDR_LEN(info) \ 24 u32_get_bits(info, GENMASK(11, 8)) 25 26 #define RTW89_SET_H2CREG_HDR_FUNC(info, val) \ 27 u32p_replace_bits(info, val, GENMASK(6, 0)) 28 #define RTW89_SET_H2CREG_HDR_LEN(info, val) \ 29 u32p_replace_bits(info, val, GENMASK(11, 8)) 30 31 #define RTW89_H2CREG_MAX 4 32 #define RTW89_C2HREG_MAX 4 33 #define RTW89_C2HREG_HDR_LEN 2 34 #define RTW89_H2CREG_HDR_LEN 2 35 #define RTW89_C2H_TIMEOUT 1000000 36 struct rtw89_mac_c2h_info { 37 u8 id; 38 u8 content_len; 39 u32 c2hreg[RTW89_C2HREG_MAX]; 40 }; 41 42 struct rtw89_mac_h2c_info { 43 u8 id; 44 u8 content_len; 45 u32 h2creg[RTW89_H2CREG_MAX]; 46 }; 47 48 enum rtw89_mac_h2c_type { 49 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0, 50 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD, 51 RTW89_FWCMD_H2CREG_FUNC_FWERR, 52 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE, 53 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM, 54 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN 55 }; 56 57 enum rtw89_mac_c2h_type { 58 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0, 59 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT, 60 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG, 61 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP, 62 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT, 63 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF 64 }; 65 66 #define RTW89_GET_C2H_PHYCAP_FUNC(info) \ 67 u32_get_bits(*((const u32 *)(info)), GENMASK(6, 0)) 68 #define RTW89_GET_C2H_PHYCAP_ACK(info) \ 69 u32_get_bits(*((const u32 *)(info)), BIT(7)) 70 #define RTW89_GET_C2H_PHYCAP_LEN(info) \ 71 u32_get_bits(*((const u32 *)(info)), GENMASK(11, 8)) 72 #define RTW89_GET_C2H_PHYCAP_SEQ(info) \ 73 u32_get_bits(*((const u32 *)(info)), GENMASK(15, 12)) 74 #define RTW89_GET_C2H_PHYCAP_RX_NSS(info) \ 75 u32_get_bits(*((const u32 *)(info)), GENMASK(23, 16)) 76 #define RTW89_GET_C2H_PHYCAP_BW(info) \ 77 u32_get_bits(*((const u32 *)(info)), GENMASK(31, 24)) 78 #define RTW89_GET_C2H_PHYCAP_TX_NSS(info) \ 79 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(7, 0)) 80 #define RTW89_GET_C2H_PHYCAP_PROT(info) \ 81 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(15, 8)) 82 #define RTW89_GET_C2H_PHYCAP_NIC(info) \ 83 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(23, 16)) 84 #define RTW89_GET_C2H_PHYCAP_WL_FUNC(info) \ 85 u32_get_bits(*((const u32 *)(info) + 1), GENMASK(31, 24)) 86 #define RTW89_GET_C2H_PHYCAP_HW_TYPE(info) \ 87 u32_get_bits(*((const u32 *)(info) + 2), GENMASK(7, 0)) 88 #define RTW89_GET_C2H_PHYCAP_ANT_TX_NUM(info) \ 89 u32_get_bits(*((const u32 *)(info) + 3), GENMASK(15, 8)) 90 #define RTW89_GET_C2H_PHYCAP_ANT_RX_NUM(info) \ 91 u32_get_bits(*((const u32 *)(info) + 3), GENMASK(23, 16)) 92 93 enum rtw89_fw_c2h_category { 94 RTW89_C2H_CAT_TEST, 95 RTW89_C2H_CAT_MAC, 96 RTW89_C2H_CAT_OUTSRC, 97 }; 98 99 enum rtw89_fw_log_level { 100 RTW89_FW_LOG_LEVEL_OFF, 101 RTW89_FW_LOG_LEVEL_CRT, 102 RTW89_FW_LOG_LEVEL_SER, 103 RTW89_FW_LOG_LEVEL_WARN, 104 RTW89_FW_LOG_LEVEL_LOUD, 105 RTW89_FW_LOG_LEVEL_TR, 106 }; 107 108 enum rtw89_fw_log_path { 109 RTW89_FW_LOG_LEVEL_UART, 110 RTW89_FW_LOG_LEVEL_C2H, 111 RTW89_FW_LOG_LEVEL_SNI, 112 }; 113 114 enum rtw89_fw_log_comp { 115 RTW89_FW_LOG_COMP_VER, 116 RTW89_FW_LOG_COMP_INIT, 117 RTW89_FW_LOG_COMP_TASK, 118 RTW89_FW_LOG_COMP_CNS, 119 RTW89_FW_LOG_COMP_H2C, 120 RTW89_FW_LOG_COMP_C2H, 121 RTW89_FW_LOG_COMP_TX, 122 RTW89_FW_LOG_COMP_RX, 123 RTW89_FW_LOG_COMP_IPSEC, 124 RTW89_FW_LOG_COMP_TIMER, 125 RTW89_FW_LOG_COMP_DBGPKT, 126 RTW89_FW_LOG_COMP_PS, 127 RTW89_FW_LOG_COMP_ERROR, 128 RTW89_FW_LOG_COMP_WOWLAN, 129 RTW89_FW_LOG_COMP_SECURE_BOOT, 130 RTW89_FW_LOG_COMP_BTC, 131 RTW89_FW_LOG_COMP_BB, 132 RTW89_FW_LOG_COMP_TWT, 133 RTW89_FW_LOG_COMP_RF, 134 RTW89_FW_LOG_COMP_MCC = 20, 135 }; 136 137 enum rtw89_pkt_offload_op { 138 RTW89_PKT_OFLD_OP_ADD, 139 RTW89_PKT_OFLD_OP_DEL, 140 RTW89_PKT_OFLD_OP_READ, 141 }; 142 143 enum rtw89_scanofld_notify_reason { 144 RTW89_SCAN_DWELL_NOTIFY, 145 RTW89_SCAN_PRE_TX_NOTIFY, 146 RTW89_SCAN_POST_TX_NOTIFY, 147 RTW89_SCAN_ENTER_CH_NOTIFY, 148 RTW89_SCAN_LEAVE_CH_NOTIFY, 149 RTW89_SCAN_END_SCAN_NOTIFY, 150 }; 151 152 enum rtw89_chan_type { 153 RTW89_CHAN_OPERATE = 0, 154 RTW89_CHAN_ACTIVE, 155 RTW89_CHAN_DFS, 156 }; 157 158 enum rtw89_p2pps_action { 159 RTW89_P2P_ACT_INIT = 0, 160 RTW89_P2P_ACT_UPDATE = 1, 161 RTW89_P2P_ACT_REMOVE = 2, 162 RTW89_P2P_ACT_TERMINATE = 3, 163 }; 164 165 #define FWDL_SECTION_MAX_NUM 10 166 #define FWDL_SECTION_CHKSUM_LEN 8 167 #define FWDL_SECTION_PER_PKT_LEN 2020 168 169 struct rtw89_fw_hdr_section_info { 170 u8 redl; 171 const u8 *addr; 172 u32 len; 173 u32 dladdr; 174 }; 175 176 struct rtw89_fw_bin_info { 177 u8 section_num; 178 u32 hdr_len; 179 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM]; 180 }; 181 182 struct rtw89_fw_macid_pause_grp { 183 __le32 pause_grp[4]; 184 __le32 mask_grp[4]; 185 } __packed; 186 187 struct rtw89_h2creg_sch_tx_en { 188 u8 func:7; 189 u8 ack:1; 190 u8 total_len:4; 191 u8 seq_num:4; 192 u16 tx_en:16; 193 u16 mask:16; 194 u8 band:1; 195 u16 rsvd:15; 196 } __packed; 197 198 #define RTW89_H2C_MAX_SIZE 2048 199 #define RTW89_CHANNEL_TIME 45 200 #define RTW89_CHANNEL_TIME_6G 20 201 #define RTW89_DFS_CHAN_TIME 105 202 #define RTW89_OFF_CHAN_TIME 100 203 #define RTW89_DWELL_TIME 20 204 #define RTW89_SCAN_WIDTH 0 205 #define RTW89_SCANOFLD_MAX_SSID 8 206 #define RTW89_SCANOFLD_MAX_IE_LEN 512 207 #define RTW89_SCANOFLD_PKT_NONE 0xFF 208 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F 209 #define RTW89_MAC_CHINFO_SIZE 24 210 #define RTW89_SCAN_LIST_GUARD 4 211 #define RTW89_SCAN_LIST_LIMIT \ 212 ((RTW89_H2C_MAX_SIZE / RTW89_MAC_CHINFO_SIZE) - RTW89_SCAN_LIST_GUARD) 213 214 struct rtw89_mac_chinfo { 215 u8 period; 216 u8 dwell_time; 217 u8 central_ch; 218 u8 pri_ch; 219 u8 bw:3; 220 u8 notify_action:5; 221 u8 num_pkt:4; 222 u8 tx_pkt:1; 223 u8 pause_data:1; 224 u8 ch_band:2; 225 u8 probe_id; 226 u8 dfs_ch:1; 227 u8 tx_null:1; 228 u8 rand_seq_num:1; 229 u8 cfg_tx_pwr:1; 230 u8 rsvd0: 4; 231 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID]; 232 u16 tx_pwr_idx; 233 u8 rsvd1; 234 struct list_head list; 235 }; 236 237 struct rtw89_scan_option { 238 bool enable; 239 bool target_ch_mode; 240 }; 241 242 struct rtw89_pktofld_info { 243 struct list_head list; 244 u8 id; 245 }; 246 247 static inline void RTW89_SET_FWCMD_RA_IS_DIS(void *cmd, u32 val) 248 { 249 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(0)); 250 } 251 252 static inline void RTW89_SET_FWCMD_RA_MODE(void *cmd, u32 val) 253 { 254 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(5, 1)); 255 } 256 257 static inline void RTW89_SET_FWCMD_RA_BW_CAP(void *cmd, u32 val) 258 { 259 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 6)); 260 } 261 262 static inline void RTW89_SET_FWCMD_RA_MACID(void *cmd, u32 val) 263 { 264 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); 265 } 266 267 static inline void RTW89_SET_FWCMD_RA_DCM(void *cmd, u32 val) 268 { 269 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(16)); 270 } 271 272 static inline void RTW89_SET_FWCMD_RA_ER(void *cmd, u32 val) 273 { 274 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(17)); 275 } 276 277 static inline void RTW89_SET_FWCMD_RA_INIT_RATE_LV(void *cmd, u32 val) 278 { 279 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(19, 18)); 280 } 281 282 static inline void RTW89_SET_FWCMD_RA_UPD_ALL(void *cmd, u32 val) 283 { 284 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(20)); 285 } 286 287 static inline void RTW89_SET_FWCMD_RA_SGI(void *cmd, u32 val) 288 { 289 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(21)); 290 } 291 292 static inline void RTW89_SET_FWCMD_RA_LDPC(void *cmd, u32 val) 293 { 294 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(22)); 295 } 296 297 static inline void RTW89_SET_FWCMD_RA_STBC(void *cmd, u32 val) 298 { 299 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(23)); 300 } 301 302 static inline void RTW89_SET_FWCMD_RA_SS_NUM(void *cmd, u32 val) 303 { 304 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(26, 24)); 305 } 306 307 static inline void RTW89_SET_FWCMD_RA_GILTF(void *cmd, u32 val) 308 { 309 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(29, 27)); 310 } 311 312 static inline void RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(void *cmd, u32 val) 313 { 314 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(30)); 315 } 316 317 static inline void RTW89_SET_FWCMD_RA_UPD_MASK(void *cmd, u32 val) 318 { 319 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(31)); 320 } 321 322 static inline void RTW89_SET_FWCMD_RA_MASK_0(void *cmd, u32 val) 323 { 324 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(7, 0)); 325 } 326 327 static inline void RTW89_SET_FWCMD_RA_MASK_1(void *cmd, u32 val) 328 { 329 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(15, 8)); 330 } 331 332 static inline void RTW89_SET_FWCMD_RA_MASK_2(void *cmd, u32 val) 333 { 334 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(23, 16)); 335 } 336 337 static inline void RTW89_SET_FWCMD_RA_MASK_3(void *cmd, u32 val) 338 { 339 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 24)); 340 } 341 342 static inline void RTW89_SET_FWCMD_RA_MASK_4(void *cmd, u32 val) 343 { 344 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(7, 0)); 345 } 346 347 static inline void RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(void *cmd, u32 val) 348 { 349 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, BIT(31)); 350 } 351 352 static inline void RTW89_SET_FWCMD_RA_BAND_NUM(void *cmd, u32 val) 353 { 354 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(7, 0)); 355 } 356 357 static inline void RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(void *cmd, u32 val) 358 { 359 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(8)); 360 } 361 362 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(void *cmd, u32 val) 363 { 364 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(9)); 365 } 366 367 static inline void RTW89_SET_FWCMD_RA_CR_TBL_SEL(void *cmd, u32 val) 368 { 369 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(10)); 370 } 371 372 static inline void RTW89_SET_FWCMD_RA_FIX_GILTF_EN(void *cmd, u32 val) 373 { 374 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(11)); 375 } 376 377 static inline void RTW89_SET_FWCMD_RA_FIX_GILTF(void *cmd, u32 val) 378 { 379 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(14, 12)); 380 } 381 382 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(void *cmd, u32 val) 383 { 384 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(23, 16)); 385 } 386 387 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(void *cmd, u32 val) 388 { 389 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(25, 24)); 390 } 391 392 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(void *cmd, u32 val) 393 { 394 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(28, 26)); 395 } 396 397 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_BW(void *cmd, u32 val) 398 { 399 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 29)); 400 } 401 402 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val) 403 { 404 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)); 405 } 406 407 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val) 408 { 409 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); 410 } 411 412 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val) 413 { 414 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)); 415 } 416 417 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val) 418 { 419 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0)); 420 } 421 422 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val) 423 { 424 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4)); 425 } 426 427 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val) 428 { 429 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5)); 430 } 431 432 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val) 433 { 434 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0)); 435 } 436 437 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val) 438 { 439 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0)); 440 } 441 442 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val) 443 { 444 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0)); 445 } 446 447 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val) 448 { 449 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0)); 450 } 451 452 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val) 453 { 454 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0)); 455 } 456 457 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val) 458 { 459 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3)); 460 } 461 462 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val) 463 { 464 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4)); 465 } 466 467 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val) 468 { 469 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5)); 470 } 471 472 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val) 473 { 474 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0)); 475 } 476 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16) 477 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12) 478 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8) 479 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0) 480 481 #define GET_FWSECTION_HDR_SEC_SIZE(fwhdr) \ 482 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 0)) 483 #define GET_FWSECTION_HDR_CHECKSUM(fwhdr) \ 484 le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(28)) 485 #define GET_FWSECTION_HDR_REDL(fwhdr) \ 486 le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(29)) 487 #define GET_FWSECTION_HDR_DL_ADDR(fwhdr) \ 488 le32_get_bits(*((const __le32 *)(fwhdr)), GENMASK(31, 0)) 489 490 #define GET_FW_HDR_MAJOR_VERSION(fwhdr) \ 491 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(7, 0)) 492 #define GET_FW_HDR_MINOR_VERSION(fwhdr) \ 493 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(15, 8)) 494 #define GET_FW_HDR_SUBVERSION(fwhdr) \ 495 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 16)) 496 #define GET_FW_HDR_SUBINDEX(fwhdr) \ 497 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(31, 24)) 498 #define GET_FW_HDR_MONTH(fwhdr) \ 499 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(7, 0)) 500 #define GET_FW_HDR_DATE(fwhdr) \ 501 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(15, 8)) 502 #define GET_FW_HDR_HOUR(fwhdr) \ 503 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(23, 16)) 504 #define GET_FW_HDR_MIN(fwhdr) \ 505 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(31, 24)) 506 #define GET_FW_HDR_YEAR(fwhdr) \ 507 le32_get_bits(*((const __le32 *)(fwhdr) + 5), GENMASK(31, 0)) 508 #define GET_FW_HDR_SEC_NUM(fwhdr) \ 509 le32_get_bits(*((const __le32 *)(fwhdr) + 6), GENMASK(15, 8)) 510 #define GET_FW_HDR_CMD_VERSERION(fwhdr) \ 511 le32_get_bits(*((const __le32 *)(fwhdr) + 7), GENMASK(31, 24)) 512 static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val) 513 { 514 le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0)); 515 } 516 517 static inline void SET_CTRL_INFO_MACID(void *table, u32 val) 518 { 519 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)); 520 } 521 522 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val) 523 { 524 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); 525 } 526 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0) 527 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val) 528 { 529 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0)); 530 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE, 531 GENMASK(8, 0)); 532 } 533 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0) 534 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val) 535 { 536 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9)); 537 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP, 538 BIT(9)); 539 } 540 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0) 541 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val) 542 { 543 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10)); 544 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW, 545 GENMASK(11, 10)); 546 } 547 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0) 548 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val) 549 { 550 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12)); 551 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF, 552 GENMASK(14, 12)); 553 } 554 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0) 555 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val) 556 { 557 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); 558 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX, 559 BIT(15)); 560 } 561 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0) 562 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val) 563 { 564 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16)); 565 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL, 566 GENMASK(19, 16)); 567 } 568 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0) 569 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val) 570 { 571 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20)); 572 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN, 573 BIT(20)); 574 } 575 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0) 576 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val) 577 { 578 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21)); 579 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN, 580 BIT(21)); 581 } 582 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0) 583 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val) 584 { 585 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22)); 586 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN, 587 BIT(22)); 588 } 589 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0) 590 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val) 591 { 592 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23)); 593 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN, 594 BIT(23)); 595 } 596 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0) 597 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val) 598 { 599 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25)); 600 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB, 601 BIT(25)); 602 } 603 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0) 604 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val) 605 { 606 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26)); 607 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB, 608 BIT(26)); 609 } 610 #define SET_CMC_TBL_MASK_TRYRATE BIT(0) 611 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val) 612 { 613 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27)); 614 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE, 615 BIT(27)); 616 } 617 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0) 618 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val) 619 { 620 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28)); 621 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY, 622 GENMASK(31, 28)); 623 } 624 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0) 625 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val) 626 { 627 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0)); 628 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE, 629 GENMASK(8, 0)); 630 } 631 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0) 632 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val) 633 { 634 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9)); 635 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL, 636 BIT(9)); 637 } 638 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0) 639 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val) 640 { 641 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10)); 642 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL, 643 BIT(10)); 644 } 645 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0) 646 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val) 647 { 648 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11)); 649 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL, 650 BIT(11)); 651 } 652 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0) 653 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val) 654 { 655 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12)); 656 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT, 657 GENMASK(15, 12)); 658 } 659 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0) 660 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val) 661 { 662 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16)); 663 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE, 664 GENMASK(24, 16)); 665 } 666 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0) 667 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val) 668 { 669 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27)); 670 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC, 671 BIT(27)); 672 } 673 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0) 674 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val) 675 { 676 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28)); 677 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE, 678 GENMASK(31, 28)); 679 } 680 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0) 681 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val) 682 { 683 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0)); 684 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT, 685 GENMASK(5, 0)); 686 } 687 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0) 688 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val) 689 { 690 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6)); 691 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL, 692 BIT(6)); 693 } 694 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0) 695 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val) 696 { 697 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7)); 698 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL, 699 BIT(7)); 700 } 701 #define SET_CMC_TBL_MASK_RTS_EN BIT(0) 702 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val) 703 { 704 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8)); 705 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN, 706 BIT(8)); 707 } 708 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0) 709 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val) 710 { 711 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9)); 712 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN, 713 BIT(9)); 714 } 715 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0) 716 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val) 717 { 718 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10)); 719 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS, 720 GENMASK(11, 10)); 721 } 722 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0) 723 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val) 724 { 725 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12)); 726 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN, 727 BIT(12)); 728 } 729 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0) 730 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val) 731 { 732 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13)); 733 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE, 734 GENMASK(14, 13)); 735 } 736 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0) 737 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val) 738 { 739 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16)); 740 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN, 741 GENMASK(26, 16)); 742 } 743 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0) 744 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val) 745 { 746 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); 747 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS, 748 BIT(27)); 749 } 750 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0) 751 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val) 752 { 753 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28)); 754 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME, 755 GENMASK(31, 28)); 756 } 757 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0) 758 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val) 759 { 760 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0)); 761 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM, 762 GENMASK(7, 0)); 763 } 764 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0) 765 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val) 766 { 767 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8)); 768 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP, 769 GENMASK(9, 8)); 770 } 771 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0) 772 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val) 773 { 774 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16)); 775 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL, 776 GENMASK(18, 16)); 777 } 778 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0) 779 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val) 780 { 781 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19)); 782 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL, 783 GENMASK(21, 19)); 784 } 785 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0) 786 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val) 787 { 788 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22)); 789 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL, 790 GENMASK(24, 22)); 791 } 792 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0) 793 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val) 794 { 795 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25)); 796 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL, 797 GENMASK(27, 25)); 798 } 799 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0) 800 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val) 801 { 802 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28)); 803 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE, 804 GENMASK(31, 28)); 805 } 806 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0) 807 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val) 808 { 809 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0)); 810 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID, 811 GENMASK(2, 0)); 812 } 813 #define SET_CMC_TBL_MASK_BMC BIT(0) 814 static inline void SET_CMC_TBL_BMC(void *table, u32 val) 815 { 816 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3)); 817 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC, 818 BIT(3)); 819 } 820 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0) 821 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val) 822 { 823 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4)); 824 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID, 825 GENMASK(7, 4)); 826 } 827 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0) 828 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val) 829 { 830 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); 831 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR, 832 BIT(8)); 833 } 834 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0) 835 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val) 836 { 837 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9)); 838 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE, 839 GENMASK(11, 9)); 840 } 841 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0) 842 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val) 843 { 844 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12)); 845 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM, 846 BIT(12)); 847 } 848 #define SET_CMC_TBL_MASK_DATA_ER BIT(0) 849 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val) 850 { 851 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13)); 852 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER, 853 BIT(13)); 854 } 855 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0) 856 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val) 857 { 858 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14)); 859 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC, 860 BIT(14)); 861 } 862 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0) 863 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val) 864 { 865 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); 866 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC, 867 BIT(15)); 868 } 869 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0) 870 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val) 871 { 872 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16)); 873 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR, 874 BIT(16)); 875 } 876 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0) 877 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val) 878 { 879 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17)); 880 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH, 881 BIT(17)); 882 } 883 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0) 884 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val) 885 { 886 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18)); 887 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR, 888 BIT(18)); 889 } 890 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0) 891 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val) 892 { 893 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19)); 894 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS, 895 BIT(19)); 896 } 897 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0) 898 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val) 899 { 900 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20)); 901 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER, 902 BIT(20)); 903 } 904 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0) 905 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val) 906 { 907 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21)); 908 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN, 909 BIT(21)); 910 } 911 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0) 912 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val) 913 { 914 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27)); 915 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD, 916 BIT(27)); 917 } 918 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0) 919 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val) 920 { 921 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28)); 922 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT, 923 GENMASK(31, 28)); 924 } 925 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0) 926 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val) 927 { 928 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0)); 929 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE, 930 GENMASK(8, 0)); 931 } 932 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0) 933 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val) 934 { 935 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12)); 936 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT, 937 BIT(12)); 938 } 939 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0) 940 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val) 941 { 942 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13)); 943 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT, 944 BIT(13)); 945 } 946 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0) 947 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val) 948 { 949 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16)); 950 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN, 951 GENMASK(19, 16)); 952 } 953 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0) 954 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val) 955 { 956 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20)); 957 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A, 958 GENMASK(21, 20)); 959 } 960 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0) 961 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val) 962 { 963 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22)); 964 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B, 965 GENMASK(23, 22)); 966 } 967 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0) 968 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val) 969 { 970 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24)); 971 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C, 972 GENMASK(25, 24)); 973 } 974 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0) 975 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val) 976 { 977 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26)); 978 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D, 979 GENMASK(27, 26)); 980 } 981 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0) 982 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val) 983 { 984 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28)); 985 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A, 986 BIT(28)); 987 } 988 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0) 989 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val) 990 { 991 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29)); 992 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B, 993 BIT(29)); 994 } 995 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0) 996 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val) 997 { 998 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30)); 999 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C, 1000 BIT(30)); 1001 } 1002 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0) 1003 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val) 1004 { 1005 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31)); 1006 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D, 1007 BIT(31)); 1008 } 1009 1010 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0) 1011 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val) 1012 { 1013 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0)); 1014 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1015 GENMASK(1, 0)); 1016 } 1017 1018 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val) 1019 { 1020 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2)); 1021 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1022 GENMASK(3, 2)); 1023 } 1024 1025 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val) 1026 { 1027 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4)); 1028 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1029 GENMASK(5, 4)); 1030 } 1031 1032 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val) 1033 { 1034 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6)); 1035 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1036 GENMASK(7, 6)); 1037 } 1038 1039 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0) 1040 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val) 1041 { 1042 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); 1043 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX, 1044 GENMASK(7, 0)); 1045 } 1046 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0) 1047 static inline void SET_CMC_TBL_PAID(void *table, u32 val) 1048 { 1049 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8)); 1050 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID, 1051 GENMASK(16, 8)); 1052 } 1053 #define SET_CMC_TBL_MASK_ULDL BIT(0) 1054 static inline void SET_CMC_TBL_ULDL(void *table, u32 val) 1055 { 1056 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17)); 1057 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL, 1058 BIT(17)); 1059 } 1060 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0) 1061 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val) 1062 { 1063 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18)); 1064 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL, 1065 GENMASK(19, 18)); 1066 } 1067 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val) 1068 { 1069 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20)); 1070 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1071 GENMASK(21, 20)); 1072 } 1073 1074 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val) 1075 { 1076 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22)); 1077 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1078 GENMASK(23, 22)); 1079 } 1080 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0) 1081 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val) 1082 { 1083 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24)); 1084 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE, 1085 GENMASK(27, 24)); 1086 } 1087 1088 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val) 1089 { 1090 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30)); 1091 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1092 GENMASK(31, 30)); 1093 } 1094 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0) 1095 static inline void SET_CMC_TBL_NC(void *table, u32 val) 1096 { 1097 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0)); 1098 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC, 1099 GENMASK(2, 0)); 1100 } 1101 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0) 1102 static inline void SET_CMC_TBL_NR(void *table, u32 val) 1103 { 1104 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3)); 1105 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR, 1106 GENMASK(5, 3)); 1107 } 1108 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0) 1109 static inline void SET_CMC_TBL_NG(void *table, u32 val) 1110 { 1111 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6)); 1112 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG, 1113 GENMASK(7, 6)); 1114 } 1115 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0) 1116 static inline void SET_CMC_TBL_CB(void *table, u32 val) 1117 { 1118 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8)); 1119 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB, 1120 GENMASK(9, 8)); 1121 } 1122 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0) 1123 static inline void SET_CMC_TBL_CS(void *table, u32 val) 1124 { 1125 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10)); 1126 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS, 1127 GENMASK(11, 10)); 1128 } 1129 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0) 1130 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val) 1131 { 1132 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12)); 1133 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN, 1134 BIT(12)); 1135 } 1136 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0) 1137 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val) 1138 { 1139 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13)); 1140 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN, 1141 BIT(13)); 1142 } 1143 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0) 1144 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val) 1145 { 1146 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14)); 1147 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN, 1148 BIT(14)); 1149 } 1150 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0) 1151 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val) 1152 { 1153 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15)); 1154 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN, 1155 BIT(15)); 1156 } 1157 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0) 1158 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val) 1159 { 1160 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16)); 1161 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE, 1162 GENMASK(24, 16)); 1163 } 1164 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0) 1165 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val) 1166 { 1167 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25)); 1168 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF, 1169 GENMASK(27, 25)); 1170 } 1171 1172 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val) 1173 { 1174 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28)); 1175 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1176 GENMASK(29, 28)); 1177 } 1178 1179 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0) 1180 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val) 1181 { 1182 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30)); 1183 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW, 1184 GENMASK(31, 30)); 1185 } 1186 1187 static inline void SET_DCTL_MACID_V1(void *table, u32 val) 1188 { 1189 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)); 1190 } 1191 1192 static inline void SET_DCTL_OPERATION_V1(void *table, u32 val) 1193 { 1194 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); 1195 } 1196 1197 #define SET_DCTL_MASK_QOS_FIELD_V1 GENMASK(7, 0) 1198 static inline void SET_DCTL_QOS_FIELD_V1(void *table, u32 val) 1199 { 1200 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(7, 0)); 1201 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_FIELD_V1, 1202 GENMASK(7, 0)); 1203 } 1204 1205 #define SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID GENMASK(6, 0) 1206 static inline void SET_DCTL_HW_EXSEQ_MACID_V1(void *table, u32 val) 1207 { 1208 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 8)); 1209 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID, 1210 GENMASK(14, 8)); 1211 } 1212 1213 #define SET_DCTL_MASK_QOS_DATA BIT(0) 1214 static inline void SET_DCTL_QOS_DATA_V1(void *table, u32 val) 1215 { 1216 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); 1217 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_DATA, 1218 BIT(15)); 1219 } 1220 1221 #define SET_DCTL_MASK_AES_IV_L GENMASK(15, 0) 1222 static inline void SET_DCTL_AES_IV_L_V1(void *table, u32 val) 1223 { 1224 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 16)); 1225 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_AES_IV_L, 1226 GENMASK(31, 16)); 1227 } 1228 1229 #define SET_DCTL_MASK_AES_IV_H GENMASK(31, 0) 1230 static inline void SET_DCTL_AES_IV_H_V1(void *table, u32 val) 1231 { 1232 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 0)); 1233 le32p_replace_bits((__le32 *)(table) + 10, SET_DCTL_MASK_AES_IV_H, 1234 GENMASK(31, 0)); 1235 } 1236 1237 #define SET_DCTL_MASK_SEQ0 GENMASK(11, 0) 1238 static inline void SET_DCTL_SEQ0_V1(void *table, u32 val) 1239 { 1240 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 0)); 1241 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ0, 1242 GENMASK(11, 0)); 1243 } 1244 1245 #define SET_DCTL_MASK_SEQ1 GENMASK(11, 0) 1246 static inline void SET_DCTL_SEQ1_V1(void *table, u32 val) 1247 { 1248 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(23, 12)); 1249 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ1, 1250 GENMASK(23, 12)); 1251 } 1252 1253 #define SET_DCTL_MASK_AMSDU_MAX_LEN GENMASK(2, 0) 1254 static inline void SET_DCTL_AMSDU_MAX_LEN_V1(void *table, u32 val) 1255 { 1256 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 24)); 1257 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_AMSDU_MAX_LEN, 1258 GENMASK(26, 24)); 1259 } 1260 1261 #define SET_DCTL_MASK_STA_AMSDU_EN BIT(0) 1262 static inline void SET_DCTL_STA_AMSDU_EN_V1(void *table, u32 val) 1263 { 1264 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); 1265 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_STA_AMSDU_EN, 1266 BIT(27)); 1267 } 1268 1269 #define SET_DCTL_MASK_CHKSUM_OFLD_EN BIT(0) 1270 static inline void SET_DCTL_CHKSUM_OFLD_EN_V1(void *table, u32 val) 1271 { 1272 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(28)); 1273 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_CHKSUM_OFLD_EN, 1274 BIT(28)); 1275 } 1276 1277 #define SET_DCTL_MASK_WITH_LLC BIT(0) 1278 static inline void SET_DCTL_WITH_LLC_V1(void *table, u32 val) 1279 { 1280 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(29)); 1281 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_WITH_LLC, 1282 BIT(29)); 1283 } 1284 1285 #define SET_DCTL_MASK_SEQ2 GENMASK(11, 0) 1286 static inline void SET_DCTL_SEQ2_V1(void *table, u32 val) 1287 { 1288 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(11, 0)); 1289 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ2, 1290 GENMASK(11, 0)); 1291 } 1292 1293 #define SET_DCTL_MASK_SEQ3 GENMASK(11, 0) 1294 static inline void SET_DCTL_SEQ3_V1(void *table, u32 val) 1295 { 1296 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(23, 12)); 1297 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ3, 1298 GENMASK(23, 12)); 1299 } 1300 1301 #define SET_DCTL_MASK_TGT_IND GENMASK(3, 0) 1302 static inline void SET_DCTL_TGT_IND_V1(void *table, u32 val) 1303 { 1304 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 24)); 1305 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND, 1306 GENMASK(27, 24)); 1307 } 1308 1309 #define SET_DCTL_MASK_TGT_IND_EN BIT(0) 1310 static inline void SET_DCTL_TGT_IND_EN_V1(void *table, u32 val) 1311 { 1312 le32p_replace_bits((__le32 *)(table) + 4, val, BIT(28)); 1313 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND_EN, 1314 BIT(28)); 1315 } 1316 1317 #define SET_DCTL_MASK_HTC_LB GENMASK(2, 0) 1318 static inline void SET_DCTL_HTC_LB_V1(void *table, u32 val) 1319 { 1320 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 29)); 1321 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_HTC_LB, 1322 GENMASK(31, 29)); 1323 } 1324 1325 #define SET_DCTL_MASK_MHDR_LEN GENMASK(4, 0) 1326 static inline void SET_DCTL_MHDR_LEN_V1(void *table, u32 val) 1327 { 1328 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(4, 0)); 1329 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_MHDR_LEN, 1330 GENMASK(4, 0)); 1331 } 1332 1333 #define SET_DCTL_MASK_VLAN_TAG_VALID BIT(0) 1334 static inline void SET_DCTL_VLAN_TAG_VALID_V1(void *table, u32 val) 1335 { 1336 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(5)); 1337 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_VALID, 1338 BIT(5)); 1339 } 1340 1341 #define SET_DCTL_MASK_VLAN_TAG_SEL GENMASK(1, 0) 1342 static inline void SET_DCTL_VLAN_TAG_SEL_V1(void *table, u32 val) 1343 { 1344 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 6)); 1345 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_SEL, 1346 GENMASK(7, 6)); 1347 } 1348 1349 #define SET_DCTL_MASK_HTC_ORDER BIT(0) 1350 static inline void SET_DCTL_HTC_ORDER_V1(void *table, u32 val) 1351 { 1352 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); 1353 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_HTC_ORDER, 1354 BIT(8)); 1355 } 1356 1357 #define SET_DCTL_MASK_SEC_KEY_ID GENMASK(1, 0) 1358 static inline void SET_DCTL_SEC_KEY_ID_V1(void *table, u32 val) 1359 { 1360 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(10, 9)); 1361 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_KEY_ID, 1362 GENMASK(10, 9)); 1363 } 1364 1365 #define SET_DCTL_MASK_WAPI BIT(0) 1366 static inline void SET_DCTL_WAPI_V1(void *table, u32 val) 1367 { 1368 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); 1369 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_WAPI, 1370 BIT(15)); 1371 } 1372 1373 #define SET_DCTL_MASK_SEC_ENT_MODE GENMASK(1, 0) 1374 static inline void SET_DCTL_SEC_ENT_MODE_V1(void *table, u32 val) 1375 { 1376 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(17, 16)); 1377 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENT_MODE, 1378 GENMASK(17, 16)); 1379 } 1380 1381 #define SET_DCTL_MASK_SEC_ENTX_KEYID GENMASK(1, 0) 1382 static inline void SET_DCTL_SEC_ENT0_KEYID_V1(void *table, u32 val) 1383 { 1384 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(19, 18)); 1385 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1386 GENMASK(19, 18)); 1387 } 1388 1389 static inline void SET_DCTL_SEC_ENT1_KEYID_V1(void *table, u32 val) 1390 { 1391 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(21, 20)); 1392 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1393 GENMASK(21, 20)); 1394 } 1395 1396 static inline void SET_DCTL_SEC_ENT2_KEYID_V1(void *table, u32 val) 1397 { 1398 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(23, 22)); 1399 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1400 GENMASK(23, 22)); 1401 } 1402 1403 static inline void SET_DCTL_SEC_ENT3_KEYID_V1(void *table, u32 val) 1404 { 1405 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(25, 24)); 1406 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1407 GENMASK(25, 24)); 1408 } 1409 1410 static inline void SET_DCTL_SEC_ENT4_KEYID_V1(void *table, u32 val) 1411 { 1412 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(27, 26)); 1413 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1414 GENMASK(27, 26)); 1415 } 1416 1417 static inline void SET_DCTL_SEC_ENT5_KEYID_V1(void *table, u32 val) 1418 { 1419 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(29, 28)); 1420 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1421 GENMASK(29, 28)); 1422 } 1423 1424 static inline void SET_DCTL_SEC_ENT6_KEYID_V1(void *table, u32 val) 1425 { 1426 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 30)); 1427 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1428 GENMASK(31, 30)); 1429 } 1430 1431 #define SET_DCTL_MASK_SEC_ENT_VALID GENMASK(7, 0) 1432 static inline void SET_DCTL_SEC_ENT_VALID_V1(void *table, u32 val) 1433 { 1434 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(7, 0)); 1435 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENT_VALID, 1436 GENMASK(7, 0)); 1437 } 1438 1439 #define SET_DCTL_MASK_SEC_ENTX GENMASK(7, 0) 1440 static inline void SET_DCTL_SEC_ENT0_V1(void *table, u32 val) 1441 { 1442 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(15, 8)); 1443 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1444 GENMASK(15, 8)); 1445 } 1446 1447 static inline void SET_DCTL_SEC_ENT1_V1(void *table, u32 val) 1448 { 1449 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 16)); 1450 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1451 GENMASK(23, 16)); 1452 } 1453 1454 static inline void SET_DCTL_SEC_ENT2_V1(void *table, u32 val) 1455 { 1456 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(31, 24)); 1457 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1458 GENMASK(31, 24)); 1459 } 1460 1461 static inline void SET_DCTL_SEC_ENT3_V1(void *table, u32 val) 1462 { 1463 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); 1464 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1465 GENMASK(7, 0)); 1466 } 1467 1468 static inline void SET_DCTL_SEC_ENT4_V1(void *table, u32 val) 1469 { 1470 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(15, 8)); 1471 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1472 GENMASK(15, 8)); 1473 } 1474 1475 static inline void SET_DCTL_SEC_ENT5_V1(void *table, u32 val) 1476 { 1477 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 16)); 1478 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1479 GENMASK(23, 16)); 1480 } 1481 1482 static inline void SET_DCTL_SEC_ENT6_V1(void *table, u32 val) 1483 { 1484 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 24)); 1485 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1486 GENMASK(31, 24)); 1487 } 1488 1489 static inline void SET_BCN_UPD_PORT(void *h2c, u32 val) 1490 { 1491 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1492 } 1493 1494 static inline void SET_BCN_UPD_MBSSID(void *h2c, u32 val) 1495 { 1496 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1497 } 1498 1499 static inline void SET_BCN_UPD_BAND(void *h2c, u32 val) 1500 { 1501 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1502 } 1503 1504 static inline void SET_BCN_UPD_GRP_IE_OFST(void *h2c, u32 val) 1505 { 1506 le32p_replace_bits((__le32 *)h2c, (val - 24) | BIT(7), GENMASK(31, 24)); 1507 } 1508 1509 static inline void SET_BCN_UPD_MACID(void *h2c, u32 val) 1510 { 1511 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1512 } 1513 1514 static inline void SET_BCN_UPD_SSN_SEL(void *h2c, u32 val) 1515 { 1516 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(9, 8)); 1517 } 1518 1519 static inline void SET_BCN_UPD_SSN_MODE(void *h2c, u32 val) 1520 { 1521 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(11, 10)); 1522 } 1523 1524 static inline void SET_BCN_UPD_RATE(void *h2c, u32 val) 1525 { 1526 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(20, 12)); 1527 } 1528 1529 static inline void SET_BCN_UPD_TXPWR(void *h2c, u32 val) 1530 { 1531 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(23, 21)); 1532 } 1533 1534 static inline void SET_BCN_UPD_TXINFO_CTRL_EN(void *h2c, u32 val) 1535 { 1536 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(0)); 1537 } 1538 1539 static inline void SET_BCN_UPD_NTX_PATH_EN(void *h2c, u32 val) 1540 { 1541 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(4, 1)); 1542 } 1543 1544 static inline void SET_BCN_UPD_PATH_MAP_A(void *h2c, u32 val) 1545 { 1546 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(6, 5)); 1547 } 1548 1549 static inline void SET_BCN_UPD_PATH_MAP_B(void *h2c, u32 val) 1550 { 1551 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(8, 7)); 1552 } 1553 1554 static inline void SET_BCN_UPD_PATH_MAP_C(void *h2c, u32 val) 1555 { 1556 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(10, 9)); 1557 } 1558 1559 static inline void SET_BCN_UPD_PATH_MAP_D(void *h2c, u32 val) 1560 { 1561 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(12, 11)); 1562 } 1563 1564 static inline void SET_BCN_UPD_PATH_ANTSEL_A(void *h2c, u32 val) 1565 { 1566 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(13)); 1567 } 1568 1569 static inline void SET_BCN_UPD_PATH_ANTSEL_B(void *h2c, u32 val) 1570 { 1571 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(14)); 1572 } 1573 1574 static inline void SET_BCN_UPD_PATH_ANTSEL_C(void *h2c, u32 val) 1575 { 1576 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(15)); 1577 } 1578 1579 static inline void SET_BCN_UPD_PATH_ANTSEL_D(void *h2c, u32 val) 1580 { 1581 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(16)); 1582 } 1583 1584 static inline void SET_BCN_UPD_CSA_OFST(void *h2c, u32 val) 1585 { 1586 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 17)); 1587 } 1588 1589 static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val) 1590 { 1591 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1592 } 1593 1594 static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val) 1595 { 1596 le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8)); 1597 } 1598 1599 static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val) 1600 { 1601 le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10)); 1602 } 1603 1604 static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val) 1605 { 1606 le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13)); 1607 } 1608 1609 static inline void SET_JOININFO_MACID(void *h2c, u32 val) 1610 { 1611 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1612 } 1613 1614 static inline void SET_JOININFO_OP(void *h2c, u32 val) 1615 { 1616 le32p_replace_bits((__le32 *)h2c, val, BIT(8)); 1617 } 1618 1619 static inline void SET_JOININFO_BAND(void *h2c, u32 val) 1620 { 1621 le32p_replace_bits((__le32 *)h2c, val, BIT(9)); 1622 } 1623 1624 static inline void SET_JOININFO_WMM(void *h2c, u32 val) 1625 { 1626 le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10)); 1627 } 1628 1629 static inline void SET_JOININFO_TGR(void *h2c, u32 val) 1630 { 1631 le32p_replace_bits((__le32 *)h2c, val, BIT(12)); 1632 } 1633 1634 static inline void SET_JOININFO_ISHESTA(void *h2c, u32 val) 1635 { 1636 le32p_replace_bits((__le32 *)h2c, val, BIT(13)); 1637 } 1638 1639 static inline void SET_JOININFO_DLBW(void *h2c, u32 val) 1640 { 1641 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14)); 1642 } 1643 1644 static inline void SET_JOININFO_TF_MAC_PAD(void *h2c, u32 val) 1645 { 1646 le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16)); 1647 } 1648 1649 static inline void SET_JOININFO_DL_T_PE(void *h2c, u32 val) 1650 { 1651 le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18)); 1652 } 1653 1654 static inline void SET_JOININFO_PORT_ID(void *h2c, u32 val) 1655 { 1656 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21)); 1657 } 1658 1659 static inline void SET_JOININFO_NET_TYPE(void *h2c, u32 val) 1660 { 1661 le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24)); 1662 } 1663 1664 static inline void SET_JOININFO_WIFI_ROLE(void *h2c, u32 val) 1665 { 1666 le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26)); 1667 } 1668 1669 static inline void SET_JOININFO_SELF_ROLE(void *h2c, u32 val) 1670 { 1671 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30)); 1672 } 1673 1674 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val) 1675 { 1676 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1677 } 1678 1679 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val) 1680 { 1681 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1682 } 1683 1684 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val) 1685 { 1686 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1687 } 1688 1689 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val) 1690 { 1691 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1692 } 1693 1694 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val) 1695 { 1696 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1697 } 1698 1699 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val) 1700 { 1701 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); 1702 } 1703 1704 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val) 1705 { 1706 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1707 } 1708 1709 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val) 1710 { 1711 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1712 } 1713 1714 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val) 1715 { 1716 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)); 1717 } 1718 1719 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val) 1720 { 1721 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0)); 1722 } 1723 1724 static inline void SET_BA_CAM_VALID(void *h2c, u32 val) 1725 { 1726 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 1727 } 1728 1729 static inline void SET_BA_CAM_INIT_REQ(void *h2c, u32 val) 1730 { 1731 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 1732 } 1733 1734 static inline void SET_BA_CAM_ENTRY_IDX(void *h2c, u32 val) 1735 { 1736 le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2)); 1737 } 1738 1739 static inline void SET_BA_CAM_TID(void *h2c, u32 val) 1740 { 1741 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4)); 1742 } 1743 1744 static inline void SET_BA_CAM_MACID(void *h2c, u32 val) 1745 { 1746 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1747 } 1748 1749 static inline void SET_BA_CAM_BMAP_SIZE(void *h2c, u32 val) 1750 { 1751 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); 1752 } 1753 1754 static inline void SET_BA_CAM_SSN(void *h2c, u32 val) 1755 { 1756 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20)); 1757 } 1758 1759 static inline void SET_BA_CAM_UID(void *h2c, u32 val) 1760 { 1761 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(7, 0)); 1762 } 1763 1764 static inline void SET_BA_CAM_STD_EN(void *h2c, u32 val) 1765 { 1766 le32p_replace_bits((__le32 *)h2c + 1, val, BIT(8)); 1767 } 1768 1769 static inline void SET_BA_CAM_BAND(void *h2c, u32 val) 1770 { 1771 le32p_replace_bits((__le32 *)h2c + 1, val, BIT(9)); 1772 } 1773 1774 static inline void SET_BA_CAM_ENTRY_IDX_V1(void *h2c, u32 val) 1775 { 1776 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 28)); 1777 } 1778 1779 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val) 1780 { 1781 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1782 } 1783 1784 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val) 1785 { 1786 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1787 } 1788 1789 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val) 1790 { 1791 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); 1792 } 1793 1794 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val) 1795 { 1796 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20)); 1797 } 1798 1799 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val) 1800 { 1801 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1802 } 1803 1804 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val) 1805 { 1806 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0)); 1807 } 1808 1809 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val) 1810 { 1811 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1)); 1812 } 1813 1814 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val) 1815 { 1816 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2)); 1817 } 1818 1819 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val) 1820 { 1821 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3)); 1822 } 1823 1824 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val) 1825 { 1826 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); 1827 } 1828 1829 static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val) 1830 { 1831 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0)); 1832 } 1833 1834 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val) 1835 { 1836 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 1837 } 1838 1839 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val) 1840 { 1841 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 1842 } 1843 1844 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val) 1845 { 1846 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 1847 } 1848 1849 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val) 1850 { 1851 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 1852 } 1853 1854 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val) 1855 { 1856 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0)); 1857 } 1858 1859 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val) 1860 { 1861 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8)); 1862 } 1863 1864 enum rtw89_btc_btf_h2c_class { 1865 BTFC_SET = 0x10, 1866 BTFC_GET = 0x11, 1867 BTFC_FW_EVENT = 0x12, 1868 }; 1869 1870 enum rtw89_btc_btf_set { 1871 SET_REPORT_EN = 0x0, 1872 SET_SLOT_TABLE, 1873 SET_MREG_TABLE, 1874 SET_CX_POLICY, 1875 SET_GPIO_DBG, 1876 SET_DRV_INFO, 1877 SET_DRV_EVENT, 1878 SET_BT_WREG_ADDR, 1879 SET_BT_WREG_VAL, 1880 SET_BT_RREG_ADDR, 1881 SET_BT_WL_CH_INFO, 1882 SET_BT_INFO_REPORT, 1883 SET_BT_IGNORE_WLAN_ACT, 1884 SET_BT_TX_PWR, 1885 SET_BT_LNA_CONSTRAIN, 1886 SET_BT_GOLDEN_RX_RANGE, 1887 SET_BT_PSD_REPORT, 1888 SET_H2C_TEST, 1889 SET_MAX1, 1890 }; 1891 1892 enum rtw89_btc_cxdrvinfo { 1893 CXDRVINFO_INIT = 0, 1894 CXDRVINFO_ROLE, 1895 CXDRVINFO_DBCC, 1896 CXDRVINFO_SMAP, 1897 CXDRVINFO_RFK, 1898 CXDRVINFO_RUN, 1899 CXDRVINFO_CTRL, 1900 CXDRVINFO_SCAN, 1901 CXDRVINFO_MAX, 1902 }; 1903 1904 enum rtw89_scan_mode { 1905 RTW89_SCAN_IMMEDIATE, 1906 }; 1907 1908 enum rtw89_scan_type { 1909 RTW89_SCAN_ONCE, 1910 }; 1911 1912 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val) 1913 { 1914 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0)); 1915 } 1916 1917 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val) 1918 { 1919 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0)); 1920 } 1921 1922 static inline void RTW89_SET_FWCMD_CXINIT_ANT_TYPE(void *cmd, u8 val) 1923 { 1924 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)); 1925 } 1926 1927 static inline void RTW89_SET_FWCMD_CXINIT_ANT_NUM(void *cmd, u8 val) 1928 { 1929 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)); 1930 } 1931 1932 static inline void RTW89_SET_FWCMD_CXINIT_ANT_ISO(void *cmd, u8 val) 1933 { 1934 u8p_replace_bits((u8 *)(cmd) + 4, val, GENMASK(7, 0)); 1935 } 1936 1937 static inline void RTW89_SET_FWCMD_CXINIT_ANT_POS(void *cmd, u8 val) 1938 { 1939 u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(0)); 1940 } 1941 1942 static inline void RTW89_SET_FWCMD_CXINIT_ANT_DIVERSITY(void *cmd, u8 val) 1943 { 1944 u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(1)); 1945 } 1946 1947 static inline void RTW89_SET_FWCMD_CXINIT_MOD_RFE(void *cmd, u8 val) 1948 { 1949 u8p_replace_bits((u8 *)(cmd) + 6, val, GENMASK(7, 0)); 1950 } 1951 1952 static inline void RTW89_SET_FWCMD_CXINIT_MOD_CV(void *cmd, u8 val) 1953 { 1954 u8p_replace_bits((u8 *)(cmd) + 7, val, GENMASK(7, 0)); 1955 } 1956 1957 static inline void RTW89_SET_FWCMD_CXINIT_MOD_BT_SOLO(void *cmd, u8 val) 1958 { 1959 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(0)); 1960 } 1961 1962 static inline void RTW89_SET_FWCMD_CXINIT_MOD_BT_POS(void *cmd, u8 val) 1963 { 1964 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(1)); 1965 } 1966 1967 static inline void RTW89_SET_FWCMD_CXINIT_MOD_SW_TYPE(void *cmd, u8 val) 1968 { 1969 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(2)); 1970 } 1971 1972 static inline void RTW89_SET_FWCMD_CXINIT_WL_GCH(void *cmd, u8 val) 1973 { 1974 u8p_replace_bits((u8 *)(cmd) + 10, val, GENMASK(7, 0)); 1975 } 1976 1977 static inline void RTW89_SET_FWCMD_CXINIT_WL_ONLY(void *cmd, u8 val) 1978 { 1979 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(0)); 1980 } 1981 1982 static inline void RTW89_SET_FWCMD_CXINIT_WL_INITOK(void *cmd, u8 val) 1983 { 1984 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(1)); 1985 } 1986 1987 static inline void RTW89_SET_FWCMD_CXINIT_DBCC_EN(void *cmd, u8 val) 1988 { 1989 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(2)); 1990 } 1991 1992 static inline void RTW89_SET_FWCMD_CXINIT_CX_OTHER(void *cmd, u8 val) 1993 { 1994 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(3)); 1995 } 1996 1997 static inline void RTW89_SET_FWCMD_CXINIT_BT_ONLY(void *cmd, u8 val) 1998 { 1999 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(4)); 2000 } 2001 2002 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val) 2003 { 2004 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)); 2005 } 2006 2007 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val) 2008 { 2009 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)); 2010 } 2011 2012 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val) 2013 { 2014 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0)); 2015 } 2016 2017 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val) 2018 { 2019 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1)); 2020 } 2021 2022 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val) 2023 { 2024 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2)); 2025 } 2026 2027 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val) 2028 { 2029 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3)); 2030 } 2031 2032 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val) 2033 { 2034 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4)); 2035 } 2036 2037 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val) 2038 { 2039 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5)); 2040 } 2041 2042 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val) 2043 { 2044 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6)); 2045 } 2046 2047 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val) 2048 { 2049 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7)); 2050 } 2051 2052 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val) 2053 { 2054 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8)); 2055 } 2056 2057 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val) 2058 { 2059 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9)); 2060 } 2061 2062 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val) 2063 { 2064 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10)); 2065 } 2066 2067 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val) 2068 { 2069 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11)); 2070 } 2071 2072 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset) 2073 { 2074 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0)); 2075 } 2076 2077 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset) 2078 { 2079 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1)); 2080 } 2081 2082 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset) 2083 { 2084 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4)); 2085 } 2086 2087 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset) 2088 { 2089 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5)); 2090 } 2091 2092 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset) 2093 { 2094 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6)); 2095 } 2096 2097 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset) 2098 { 2099 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0)); 2100 } 2101 2102 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset) 2103 { 2104 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1)); 2105 } 2106 2107 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset) 2108 { 2109 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0)); 2110 } 2111 2112 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset) 2113 { 2114 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0)); 2115 } 2116 2117 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset) 2118 { 2119 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0)); 2120 } 2121 2122 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset) 2123 { 2124 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0)); 2125 } 2126 2127 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset) 2128 { 2129 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0)); 2130 } 2131 2132 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset) 2133 { 2134 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0)); 2135 } 2136 2137 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset) 2138 { 2139 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0)); 2140 } 2141 2142 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset) 2143 { 2144 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0)); 2145 } 2146 2147 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset) 2148 { 2149 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0)); 2150 } 2151 2152 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset) 2153 { 2154 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0)); 2155 } 2156 2157 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset) 2158 { 2159 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1)); 2160 } 2161 2162 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset) 2163 { 2164 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2)); 2165 } 2166 2167 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset) 2168 { 2169 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4)); 2170 } 2171 2172 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val) 2173 { 2174 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0)); 2175 } 2176 2177 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val) 2178 { 2179 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1)); 2180 } 2181 2182 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val) 2183 { 2184 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2)); 2185 } 2186 2187 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val) 2188 { 2189 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3)); 2190 } 2191 2192 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val) 2193 { 2194 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0)); 2195 } 2196 2197 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val) 2198 { 2199 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2)); 2200 } 2201 2202 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val) 2203 { 2204 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6)); 2205 } 2206 2207 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val) 2208 { 2209 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8)); 2210 } 2211 2212 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val) 2213 { 2214 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10)); 2215 } 2216 2217 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val) 2218 { 2219 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2220 } 2221 2222 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val) 2223 { 2224 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8)); 2225 } 2226 2227 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val) 2228 { 2229 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16)); 2230 } 2231 2232 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_NUM(void *cmd, u32 val) 2233 { 2234 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2235 } 2236 2237 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_SIZE(void *cmd, u32 val) 2238 { 2239 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8)); 2240 } 2241 2242 static inline void RTW89_SET_FWCMD_CHINFO_PERIOD(void *cmd, u32 val) 2243 { 2244 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2245 } 2246 2247 static inline void RTW89_SET_FWCMD_CHINFO_DWELL(void *cmd, u32 val) 2248 { 2249 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8)); 2250 } 2251 2252 static inline void RTW89_SET_FWCMD_CHINFO_CENTER_CH(void *cmd, u32 val) 2253 { 2254 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 16)); 2255 } 2256 2257 static inline void RTW89_SET_FWCMD_CHINFO_PRI_CH(void *cmd, u32 val) 2258 { 2259 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 24)); 2260 } 2261 2262 static inline void RTW89_SET_FWCMD_CHINFO_BW(void *cmd, u32 val) 2263 { 2264 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(2, 0)); 2265 } 2266 2267 static inline void RTW89_SET_FWCMD_CHINFO_ACTION(void *cmd, u32 val) 2268 { 2269 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 3)); 2270 } 2271 2272 static inline void RTW89_SET_FWCMD_CHINFO_NUM_PKT(void *cmd, u32 val) 2273 { 2274 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(11, 8)); 2275 } 2276 2277 static inline void RTW89_SET_FWCMD_CHINFO_TX(void *cmd, u32 val) 2278 { 2279 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(12)); 2280 } 2281 2282 static inline void RTW89_SET_FWCMD_CHINFO_PAUSE_DATA(void *cmd, u32 val) 2283 { 2284 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(13)); 2285 } 2286 2287 static inline void RTW89_SET_FWCMD_CHINFO_BAND(void *cmd, u32 val) 2288 { 2289 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 14)); 2290 } 2291 2292 static inline void RTW89_SET_FWCMD_CHINFO_PKT_ID(void *cmd, u32 val) 2293 { 2294 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16)); 2295 } 2296 2297 static inline void RTW89_SET_FWCMD_CHINFO_DFS(void *cmd, u32 val) 2298 { 2299 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(24)); 2300 } 2301 2302 static inline void RTW89_SET_FWCMD_CHINFO_TX_NULL(void *cmd, u32 val) 2303 { 2304 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(25)); 2305 } 2306 2307 static inline void RTW89_SET_FWCMD_CHINFO_RANDOM(void *cmd, u32 val) 2308 { 2309 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(26)); 2310 } 2311 2312 static inline void RTW89_SET_FWCMD_CHINFO_CFG_TX(void *cmd, u32 val) 2313 { 2314 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(27)); 2315 } 2316 2317 static inline void RTW89_SET_FWCMD_CHINFO_PKT0(void *cmd, u32 val) 2318 { 2319 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(7, 0)); 2320 } 2321 2322 static inline void RTW89_SET_FWCMD_CHINFO_PKT1(void *cmd, u32 val) 2323 { 2324 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 8)); 2325 } 2326 2327 static inline void RTW89_SET_FWCMD_CHINFO_PKT2(void *cmd, u32 val) 2328 { 2329 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16)); 2330 } 2331 2332 static inline void RTW89_SET_FWCMD_CHINFO_PKT3(void *cmd, u32 val) 2333 { 2334 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(31, 24)); 2335 } 2336 2337 static inline void RTW89_SET_FWCMD_CHINFO_PKT4(void *cmd, u32 val) 2338 { 2339 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(7, 0)); 2340 } 2341 2342 static inline void RTW89_SET_FWCMD_CHINFO_PKT5(void *cmd, u32 val) 2343 { 2344 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(15, 8)); 2345 } 2346 2347 static inline void RTW89_SET_FWCMD_CHINFO_PKT6(void *cmd, u32 val) 2348 { 2349 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(23, 16)); 2350 } 2351 2352 static inline void RTW89_SET_FWCMD_CHINFO_PKT7(void *cmd, u32 val) 2353 { 2354 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 24)); 2355 } 2356 2357 static inline void RTW89_SET_FWCMD_CHINFO_POWER_IDX(void *cmd, u32 val) 2358 { 2359 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(15, 0)); 2360 } 2361 2362 static inline void RTW89_SET_FWCMD_SCANOFLD_MACID(void *cmd, u32 val) 2363 { 2364 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2365 } 2366 2367 static inline void RTW89_SET_FWCMD_SCANOFLD_NORM_CY(void *cmd, u32 val) 2368 { 2369 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8)); 2370 } 2371 2372 static inline void RTW89_SET_FWCMD_SCANOFLD_PORT_ID(void *cmd, u32 val) 2373 { 2374 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(18, 16)); 2375 } 2376 2377 static inline void RTW89_SET_FWCMD_SCANOFLD_BAND(void *cmd, u32 val) 2378 { 2379 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, BIT(19)); 2380 } 2381 2382 static inline void RTW89_SET_FWCMD_SCANOFLD_OPERATION(void *cmd, u32 val) 2383 { 2384 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(21, 20)); 2385 } 2386 2387 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_BAND(void *cmd, u32 val) 2388 { 2389 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 22)); 2390 } 2391 2392 static inline void RTW89_SET_FWCMD_SCANOFLD_NOTIFY_END(void *cmd, u32 val) 2393 { 2394 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(0)); 2395 } 2396 2397 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_MODE(void *cmd, u32 val) 2398 { 2399 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(1)); 2400 } 2401 2402 static inline void RTW89_SET_FWCMD_SCANOFLD_START_MODE(void *cmd, u32 val) 2403 { 2404 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(2)); 2405 } 2406 2407 static inline void RTW89_SET_FWCMD_SCANOFLD_SCAN_TYPE(void *cmd, u32 val) 2408 { 2409 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(4, 3)); 2410 } 2411 2412 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_BW(void *cmd, u32 val) 2413 { 2414 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 5)); 2415 } 2416 2417 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_PRI_CH(void *cmd, u32 val) 2418 { 2419 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 8)); 2420 } 2421 2422 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CENTRAL_CH(void *cmd, 2423 u32 val) 2424 { 2425 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16)); 2426 } 2427 2428 static inline void RTW89_SET_FWCMD_SCANOFLD_PROBE_REQ_PKT_ID(void *cmd, u32 val) 2429 { 2430 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(31, 24)); 2431 } 2432 2433 static inline void RTW89_SET_FWCMD_SCANOFLD_NORM_PD(void *cmd, u32 val) 2434 { 2435 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 0)); 2436 } 2437 2438 static inline void RTW89_SET_FWCMD_SCANOFLD_SLOW_PD(void *cmd, u32 val) 2439 { 2440 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16)); 2441 } 2442 2443 static inline void RTW89_SET_FWCMD_SCANOFLD_TSF_HIGH(void *cmd, u32 val) 2444 { 2445 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 0)); 2446 } 2447 2448 static inline void RTW89_SET_FWCMD_SCANOFLD_TSF_SLOW(void *cmd, u32 val) 2449 { 2450 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(31, 0)); 2451 } 2452 2453 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val) 2454 { 2455 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 2456 } 2457 2458 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val) 2459 { 2460 le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8)); 2461 } 2462 2463 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val) 2464 { 2465 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12)); 2466 } 2467 2468 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val) 2469 { 2470 le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16)); 2471 } 2472 2473 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val) 2474 { 2475 le32p_replace_bits((__le32 *)cmd, val, BIT(20)); 2476 } 2477 2478 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val) 2479 { 2480 le32p_replace_bits((__le32 *)cmd, val, BIT(21)); 2481 } 2482 2483 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val) 2484 { 2485 *((__le32 *)cmd + 1) = val; 2486 } 2487 2488 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val) 2489 { 2490 *((__le32 *)cmd + 2) = val; 2491 } 2492 2493 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val) 2494 { 2495 *((__le32 *)cmd + 3) = val; 2496 } 2497 2498 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val) 2499 { 2500 le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0)); 2501 } 2502 2503 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val) 2504 { 2505 u8 ctwnd; 2506 2507 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT)) 2508 return; 2509 ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val); 2510 le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8)); 2511 } 2512 2513 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val) 2514 { 2515 le32p_replace_bits((__le32 *)cmd, val, BIT(0)); 2516 } 2517 2518 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val) 2519 { 2520 le32p_replace_bits((__le32 *)cmd, val, BIT(1)); 2521 } 2522 2523 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val) 2524 { 2525 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2)); 2526 } 2527 2528 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val) 2529 { 2530 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16)); 2531 } 2532 2533 #define RTW89_C2H_HEADER_LEN 8 2534 2535 #define RTW89_GET_C2H_CATEGORY(c2h) \ 2536 le32_get_bits(*((const __le32 *)c2h), GENMASK(1, 0)) 2537 #define RTW89_GET_C2H_CLASS(c2h) \ 2538 le32_get_bits(*((const __le32 *)c2h), GENMASK(7, 2)) 2539 #define RTW89_GET_C2H_FUNC(c2h) \ 2540 le32_get_bits(*((const __le32 *)c2h), GENMASK(15, 8)) 2541 #define RTW89_GET_C2H_LEN(c2h) \ 2542 le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(13, 0)) 2543 2544 #define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2) 2545 #define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN) 2546 2547 #define RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h) \ 2548 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 2549 #define RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h) \ 2550 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 2551 #define RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h) \ 2552 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 2553 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h) \ 2554 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 2555 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h) \ 2556 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24)) 2557 2558 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \ 2559 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 2560 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \ 2561 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 2562 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \ 2563 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 2564 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \ 2565 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 2566 2567 #define RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h) \ 2568 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 0)) 2569 #define RTW89_GET_PHY_C2H_RA_RPT_RETRY_RATIO(c2h) \ 2570 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 2571 #define RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h) \ 2572 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(6, 0)) 2573 #define RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h) \ 2574 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(9, 8)) 2575 #define RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h) \ 2576 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(12, 10)) 2577 #define RTW89_GET_PHY_C2H_RA_RPT_BW(c2h) \ 2578 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(14, 13)) 2579 2580 /* VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS 2581 * HT-new: [6:5]: NA, [4:0]: MCS 2582 */ 2583 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4) 2584 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0) 2585 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0) 2586 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \ 2587 FIELD_PREP(GENMASK(2, 0), mcs)) 2588 2589 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \ 2590 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 2591 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \ 2592 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8)) 2593 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \ 2594 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16)) 2595 2596 #define RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h) \ 2597 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 2598 #define RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h) \ 2599 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(19, 16)) 2600 #define RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h) \ 2601 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 20)) 2602 #define RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h) \ 2603 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24)) 2604 #define RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h) \ 2605 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(3, 0)) 2606 #define RTW89_GET_MAC_C2H_SCANOFLD_AIR_DENSITY(c2h) \ 2607 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(7, 4)) 2608 #define RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h) \ 2609 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(25, 24)) 2610 2611 #define RTW89_FW_HDR_SIZE 32 2612 #define RTW89_FW_SECTION_HDR_SIZE 16 2613 2614 #define RTW89_MFW_SIG 0xFF 2615 2616 struct rtw89_mfw_info { 2617 u8 cv; 2618 u8 type; /* enum rtw89_fw_type */ 2619 u8 mp; 2620 u8 rsvd; 2621 __le32 shift; 2622 __le32 size; 2623 u8 rsvd2[4]; 2624 } __packed; 2625 2626 struct rtw89_mfw_hdr { 2627 u8 sig; /* RTW89_MFW_SIG */ 2628 u8 fw_nr; 2629 u8 rsvd0[2]; 2630 struct { 2631 u8 major; 2632 u8 minor; 2633 u8 sub; 2634 u8 idx; 2635 } ver; 2636 u8 rsvd1[8]; 2637 struct rtw89_mfw_info info[]; 2638 } __packed; 2639 2640 struct fwcmd_hdr { 2641 __le32 hdr0; 2642 __le32 hdr1; 2643 }; 2644 2645 #define RTW89_H2C_RF_PAGE_SIZE 500 2646 #define RTW89_H2C_RF_PAGE_NUM 3 2647 struct rtw89_fw_h2c_rf_reg_info { 2648 enum rtw89_rf_path rf_path; 2649 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE]; 2650 u16 curr_idx; 2651 }; 2652 2653 #define H2C_SEC_CAM_LEN 24 2654 2655 #define H2C_HEADER_LEN 8 2656 #define H2C_HDR_CAT GENMASK(1, 0) 2657 #define H2C_HDR_CLASS GENMASK(7, 2) 2658 #define H2C_HDR_FUNC GENMASK(15, 8) 2659 #define H2C_HDR_DEL_TYPE GENMASK(19, 16) 2660 #define H2C_HDR_H2C_SEQ GENMASK(31, 24) 2661 #define H2C_HDR_TOTAL_LEN GENMASK(13, 0) 2662 #define H2C_HDR_REC_ACK BIT(14) 2663 #define H2C_HDR_DONE_ACK BIT(15) 2664 2665 #define FWCMD_TYPE_H2C 0 2666 2667 #define H2C_CAT_TEST 0x0 2668 2669 /* CLASS 5 - FW STATUS TEST */ 2670 #define H2C_CL_FW_STATUS_TEST 0x5 2671 #define H2C_FUNC_CPU_EXCEPTION 0x1 2672 2673 #define H2C_CAT_MAC 0x1 2674 2675 /* CLASS 0 - FW INFO */ 2676 #define H2C_CL_FW_INFO 0x0 2677 #define H2C_FUNC_LOG_CFG 0x0 2678 #define H2C_FUNC_MAC_GENERAL_PKT 0x1 2679 2680 /* CLASS 2 - PS */ 2681 #define H2C_CL_MAC_PS 0x2 2682 #define H2C_FUNC_MAC_LPS_PARM 0x0 2683 #define H2C_FUNC_P2P_ACT 0x1 2684 2685 /* CLASS 3 - FW download */ 2686 #define H2C_CL_MAC_FWDL 0x3 2687 #define H2C_FUNC_MAC_FWHDR_DL 0x0 2688 2689 /* CLASS 5 - Frame Exchange */ 2690 #define H2C_CL_MAC_FR_EXCHG 0x5 2691 #define H2C_FUNC_MAC_CCTLINFO_UD 0x2 2692 #define H2C_FUNC_MAC_BCN_UPD 0x5 2693 #define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9 2694 #define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa 2695 2696 /* CLASS 6 - Address CAM */ 2697 #define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6 2698 #define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0 2699 2700 /* CLASS 8 - Media Status Report */ 2701 #define H2C_CL_MAC_MEDIA_RPT 0x8 2702 #define H2C_FUNC_MAC_JOININFO 0x0 2703 #define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4 2704 2705 /* CLASS 9 - FW offload */ 2706 #define H2C_CL_MAC_FW_OFLD 0x9 2707 #define H2C_FUNC_PACKET_OFLD 0x1 2708 #define H2C_FUNC_MAC_MACID_PAUSE 0x8 2709 #define H2C_FUNC_USR_EDCA 0xF 2710 #define H2C_FUNC_TSF32_TOGL 0x10 2711 #define H2C_FUNC_OFLD_CFG 0x14 2712 #define H2C_FUNC_ADD_SCANOFLD_CH 0x16 2713 #define H2C_FUNC_SCANOFLD 0x17 2714 #define H2C_FUNC_PKT_DROP 0x1b 2715 2716 /* CLASS 10 - Security CAM */ 2717 #define H2C_CL_MAC_SEC_CAM 0xa 2718 #define H2C_FUNC_MAC_SEC_UPD 0x1 2719 2720 /* CLASS 12 - BA CAM */ 2721 #define H2C_CL_BA_CAM 0xc 2722 #define H2C_FUNC_MAC_BA_CAM 0x0 2723 2724 #define H2C_CAT_OUTSRC 0x2 2725 2726 #define H2C_CL_OUTSRC_RA 0x1 2727 #define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0 2728 2729 #define H2C_CL_OUTSRC_RF_REG_A 0x8 2730 #define H2C_CL_OUTSRC_RF_REG_B 0x9 2731 #define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa 2732 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2 2733 2734 struct rtw89_fw_h2c_rf_get_mccch { 2735 __le32 ch_0; 2736 __le32 ch_1; 2737 __le32 band_0; 2738 __le32 band_1; 2739 __le32 current_channel; 2740 __le32 current_band_type; 2741 } __packed; 2742 2743 #define RTW89_FW_RSVD_PLE_SIZE 0x800 2744 2745 #define RTW89_WCPU_BASE_MASK GENMASK(27, 0) 2746 2747 #define RTW89_FW_BACKTRACE_INFO_SIZE 8 2748 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \ 2749 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0) 2750 2751 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */ 2752 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE 2753 2754 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev); 2755 int rtw89_fw_recognize(struct rtw89_dev *rtwdev); 2756 void rtw89_early_fw_feature_recognize(struct device *device, 2757 const struct rtw89_chip_info *chip, 2758 u32 *early_feat_map); 2759 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type); 2760 int rtw89_load_firmware(struct rtw89_dev *rtwdev); 2761 void rtw89_unload_firmware(struct rtw89_dev *rtwdev); 2762 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev); 2763 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb, 2764 u8 type, u8 cat, u8 class, u8 func, 2765 bool rack, bool dack, u32 len); 2766 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, 2767 struct rtw89_vif *rtwvif); 2768 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, 2769 struct ieee80211_vif *vif, 2770 struct ieee80211_sta *sta); 2771 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev, 2772 struct rtw89_sta *rtwsta); 2773 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev, 2774 struct rtw89_sta *rtwsta); 2775 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev, 2776 struct rtw89_vif *rtwvif); 2777 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif, 2778 struct rtw89_sta *rtwsta, const u8 *scan_mac_addr); 2779 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev, 2780 struct rtw89_vif *rtwvif, 2781 struct rtw89_sta *rtwsta); 2782 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h); 2783 void rtw89_fw_c2h_work(struct work_struct *work); 2784 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev, 2785 struct rtw89_vif *rtwvif, 2786 struct rtw89_sta *rtwsta, 2787 enum rtw89_upd_mode upd_mode); 2788 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 2789 struct rtw89_sta *rtwsta, bool dis_conn); 2790 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp, 2791 bool pause); 2792 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 2793 u8 ac, u32 val); 2794 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev); 2795 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi); 2796 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev); 2797 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev); 2798 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev); 2799 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev); 2800 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev); 2801 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id); 2802 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id, 2803 struct sk_buff *skb_ofld); 2804 int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int len, 2805 struct list_head *chan_list); 2806 int rtw89_fw_h2c_scan_offload(struct rtw89_dev *rtwdev, 2807 struct rtw89_scan_option *opt, 2808 struct rtw89_vif *vif); 2809 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev, 2810 struct rtw89_fw_h2c_rf_reg_info *info, 2811 u16 len, u8 page); 2812 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev); 2813 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, 2814 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, 2815 bool rack, bool dack); 2816 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len); 2817 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev); 2818 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev); 2819 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, u8 macid); 2820 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 2821 bool valid, struct ieee80211_ampdu_params *params); 2822 void rtw89_fw_h2c_init_ba_cam_v1(struct rtw89_dev *rtwdev); 2823 2824 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev, 2825 struct rtw89_lps_parm *lps_param); 2826 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len); 2827 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len); 2828 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev, 2829 struct rtw89_mac_h2c_info *h2c_info, 2830 struct rtw89_mac_c2h_info *c2h_info); 2831 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable); 2832 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev); 2833 void rtw89_store_op_chan(struct rtw89_dev *rtwdev, bool backup); 2834 void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 2835 struct ieee80211_scan_request *req); 2836 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 2837 bool aborted); 2838 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 2839 bool enable); 2840 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 2841 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev); 2842 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev, 2843 const struct rtw89_pkt_drop_params *params); 2844 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 2845 struct ieee80211_p2p_noa_desc *desc, 2846 u8 act, u8 noa_id); 2847 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 2848 bool en); 2849 2850 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev) 2851 { 2852 const struct rtw89_chip_info *chip = rtwdev->chip; 2853 2854 if (chip->bacam_v1) 2855 rtw89_fw_h2c_init_ba_cam_v1(rtwdev); 2856 } 2857 2858 #endif 2859