1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020  Realtek Corporation
3  */
4 
5 #ifndef __RTW89_FW_H__
6 #define __RTW89_FW_H__
7 
8 #include "core.h"
9 
10 enum rtw89_fw_dl_status {
11 	RTW89_FWDL_INITIAL_STATE = 0,
12 	RTW89_FWDL_FWDL_ONGOING = 1,
13 	RTW89_FWDL_CHECKSUM_FAIL = 2,
14 	RTW89_FWDL_SECURITY_FAIL = 3,
15 	RTW89_FWDL_CV_NOT_MATCH = 4,
16 	RTW89_FWDL_RSVD0 = 5,
17 	RTW89_FWDL_WCPU_FWDL_RDY = 6,
18 	RTW89_FWDL_WCPU_FW_INIT_RDY = 7
19 };
20 
21 #define RTW89_GET_C2H_HDR_FUNC(info) \
22 	u32_get_bits(info, GENMASK(6, 0))
23 #define RTW89_GET_C2H_HDR_LEN(info) \
24 	u32_get_bits(info, GENMASK(11, 8))
25 
26 #define RTW89_SET_H2CREG_HDR_FUNC(info, val) \
27 	u32p_replace_bits(info, val, GENMASK(6, 0))
28 #define RTW89_SET_H2CREG_HDR_LEN(info, val) \
29 	u32p_replace_bits(info, val, GENMASK(11, 8))
30 
31 #define RTW89_H2CREG_MAX 4
32 #define RTW89_C2HREG_MAX 4
33 #define RTW89_C2HREG_HDR_LEN 2
34 #define RTW89_H2CREG_HDR_LEN 2
35 #define RTW89_C2H_TIMEOUT 1000000
36 struct rtw89_mac_c2h_info {
37 	u8 id;
38 	u8 content_len;
39 	u32 c2hreg[RTW89_C2HREG_MAX];
40 };
41 
42 struct rtw89_mac_h2c_info {
43 	u8 id;
44 	u8 content_len;
45 	u32 h2creg[RTW89_H2CREG_MAX];
46 };
47 
48 enum rtw89_mac_h2c_type {
49 	RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0,
50 	RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD,
51 	RTW89_FWCMD_H2CREG_FUNC_FWERR,
52 	RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE,
53 	RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM,
54 	RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN
55 };
56 
57 enum rtw89_mac_c2h_type {
58 	RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0,
59 	RTW89_FWCMD_C2HREG_FUNC_ERR_RPT,
60 	RTW89_FWCMD_C2HREG_FUNC_ERR_MSG,
61 	RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,
62 	RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,
63 	RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF
64 };
65 
66 #define RTW89_GET_C2H_PHYCAP_FUNC(info) \
67 	u32_get_bits(*((const u32 *)(info)), GENMASK(6, 0))
68 #define RTW89_GET_C2H_PHYCAP_ACK(info) \
69 	u32_get_bits(*((const u32 *)(info)), BIT(7))
70 #define RTW89_GET_C2H_PHYCAP_LEN(info) \
71 	u32_get_bits(*((const u32 *)(info)), GENMASK(11, 8))
72 #define RTW89_GET_C2H_PHYCAP_SEQ(info) \
73 	u32_get_bits(*((const u32 *)(info)), GENMASK(15, 12))
74 #define RTW89_GET_C2H_PHYCAP_RX_NSS(info) \
75 	u32_get_bits(*((const u32 *)(info)), GENMASK(23, 16))
76 #define RTW89_GET_C2H_PHYCAP_BW(info) \
77 	u32_get_bits(*((const u32 *)(info)), GENMASK(31, 24))
78 #define RTW89_GET_C2H_PHYCAP_TX_NSS(info) \
79 	u32_get_bits(*((const u32 *)(info) + 1), GENMASK(7, 0))
80 #define RTW89_GET_C2H_PHYCAP_PROT(info) \
81 	u32_get_bits(*((const u32 *)(info) + 1), GENMASK(15, 8))
82 #define RTW89_GET_C2H_PHYCAP_NIC(info) \
83 	u32_get_bits(*((const u32 *)(info) + 1), GENMASK(23, 16))
84 #define RTW89_GET_C2H_PHYCAP_WL_FUNC(info) \
85 	u32_get_bits(*((const u32 *)(info) + 1), GENMASK(31, 24))
86 #define RTW89_GET_C2H_PHYCAP_HW_TYPE(info) \
87 	u32_get_bits(*((const u32 *)(info) + 2), GENMASK(7, 0))
88 #define RTW89_GET_C2H_PHYCAP_ANT_TX_NUM(info) \
89 	u32_get_bits(*((const u32 *)(info) + 3), GENMASK(15, 8))
90 #define RTW89_GET_C2H_PHYCAP_ANT_RX_NUM(info) \
91 	u32_get_bits(*((const u32 *)(info) + 3), GENMASK(23, 16))
92 
93 enum rtw89_fw_c2h_category {
94 	RTW89_C2H_CAT_TEST,
95 	RTW89_C2H_CAT_MAC,
96 	RTW89_C2H_CAT_OUTSRC,
97 };
98 
99 enum rtw89_fw_log_level {
100 	RTW89_FW_LOG_LEVEL_OFF,
101 	RTW89_FW_LOG_LEVEL_CRT,
102 	RTW89_FW_LOG_LEVEL_SER,
103 	RTW89_FW_LOG_LEVEL_WARN,
104 	RTW89_FW_LOG_LEVEL_LOUD,
105 	RTW89_FW_LOG_LEVEL_TR,
106 };
107 
108 enum rtw89_fw_log_path {
109 	RTW89_FW_LOG_LEVEL_UART,
110 	RTW89_FW_LOG_LEVEL_C2H,
111 	RTW89_FW_LOG_LEVEL_SNI,
112 };
113 
114 enum rtw89_fw_log_comp {
115 	RTW89_FW_LOG_COMP_VER,
116 	RTW89_FW_LOG_COMP_INIT,
117 	RTW89_FW_LOG_COMP_TASK,
118 	RTW89_FW_LOG_COMP_CNS,
119 	RTW89_FW_LOG_COMP_H2C,
120 	RTW89_FW_LOG_COMP_C2H,
121 	RTW89_FW_LOG_COMP_TX,
122 	RTW89_FW_LOG_COMP_RX,
123 	RTW89_FW_LOG_COMP_IPSEC,
124 	RTW89_FW_LOG_COMP_TIMER,
125 	RTW89_FW_LOG_COMP_DBGPKT,
126 	RTW89_FW_LOG_COMP_PS,
127 	RTW89_FW_LOG_COMP_ERROR,
128 	RTW89_FW_LOG_COMP_WOWLAN,
129 	RTW89_FW_LOG_COMP_SECURE_BOOT,
130 	RTW89_FW_LOG_COMP_BTC,
131 	RTW89_FW_LOG_COMP_BB,
132 	RTW89_FW_LOG_COMP_TWT,
133 	RTW89_FW_LOG_COMP_RF,
134 	RTW89_FW_LOG_COMP_MCC = 20,
135 };
136 
137 enum rtw89_pkt_offload_op {
138 	RTW89_PKT_OFLD_OP_ADD,
139 	RTW89_PKT_OFLD_OP_DEL,
140 	RTW89_PKT_OFLD_OP_READ,
141 
142 	NUM_OF_RTW89_PKT_OFFLOAD_OP,
143 };
144 
145 #define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) \
146 	((pkt_id) * NUM_OF_RTW89_PKT_OFFLOAD_OP + (pkt_op))
147 
148 enum rtw89_scanofld_notify_reason {
149 	RTW89_SCAN_DWELL_NOTIFY,
150 	RTW89_SCAN_PRE_TX_NOTIFY,
151 	RTW89_SCAN_POST_TX_NOTIFY,
152 	RTW89_SCAN_ENTER_CH_NOTIFY,
153 	RTW89_SCAN_LEAVE_CH_NOTIFY,
154 	RTW89_SCAN_END_SCAN_NOTIFY,
155 };
156 
157 enum rtw89_chan_type {
158 	RTW89_CHAN_OPERATE = 0,
159 	RTW89_CHAN_ACTIVE,
160 	RTW89_CHAN_DFS,
161 };
162 
163 enum rtw89_p2pps_action {
164 	RTW89_P2P_ACT_INIT = 0,
165 	RTW89_P2P_ACT_UPDATE = 1,
166 	RTW89_P2P_ACT_REMOVE = 2,
167 	RTW89_P2P_ACT_TERMINATE = 3,
168 };
169 
170 enum rtw89_bcn_fltr_offload_mode {
171 	RTW89_BCN_FLTR_OFFLOAD_MODE_0 = 0,
172 	RTW89_BCN_FLTR_OFFLOAD_MODE_1,
173 	RTW89_BCN_FLTR_OFFLOAD_MODE_2,
174 	RTW89_BCN_FLTR_OFFLOAD_MODE_3,
175 
176 	RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT = RTW89_BCN_FLTR_OFFLOAD_MODE_0,
177 };
178 
179 enum rtw89_bcn_fltr_type {
180 	RTW89_BCN_FLTR_BEACON_LOSS,
181 	RTW89_BCN_FLTR_RSSI,
182 	RTW89_BCN_FLTR_NOTIFY,
183 };
184 
185 enum rtw89_bcn_fltr_rssi_event {
186 	RTW89_BCN_FLTR_RSSI_NOT_CHANGED,
187 	RTW89_BCN_FLTR_RSSI_HIGH,
188 	RTW89_BCN_FLTR_RSSI_LOW,
189 };
190 
191 #define FWDL_SECTION_MAX_NUM 10
192 #define FWDL_SECTION_CHKSUM_LEN	8
193 #define FWDL_SECTION_PER_PKT_LEN 2020
194 
195 struct rtw89_fw_hdr_section_info {
196 	u8 redl;
197 	const u8 *addr;
198 	u32 len;
199 	u32 dladdr;
200 	u32 mssc;
201 	u8 type;
202 };
203 
204 struct rtw89_fw_bin_info {
205 	u8 section_num;
206 	u32 hdr_len;
207 	bool dynamic_hdr_en;
208 	u32 dynamic_hdr_len;
209 	struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];
210 };
211 
212 struct rtw89_fw_macid_pause_grp {
213 	__le32 pause_grp[4];
214 	__le32 mask_grp[4];
215 } __packed;
216 
217 struct rtw89_h2creg_sch_tx_en {
218 	u8 func:7;
219 	u8 ack:1;
220 	u8 total_len:4;
221 	u8 seq_num:4;
222 	u16 tx_en:16;
223 	u16 mask:16;
224 	u8 band:1;
225 	u16 rsvd:15;
226 } __packed;
227 
228 #define RTW89_H2C_MAX_SIZE 2048
229 #define RTW89_CHANNEL_TIME 45
230 #define RTW89_CHANNEL_TIME_6G 20
231 #define RTW89_DFS_CHAN_TIME 105
232 #define RTW89_OFF_CHAN_TIME 100
233 #define RTW89_DWELL_TIME 20
234 #define RTW89_DWELL_TIME_6G 10
235 #define RTW89_SCAN_WIDTH 0
236 #define RTW89_SCANOFLD_MAX_SSID 8
237 #define RTW89_SCANOFLD_MAX_IE_LEN 512
238 #define RTW89_SCANOFLD_PKT_NONE 0xFF
239 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F
240 #define RTW89_MAC_CHINFO_SIZE 24
241 #define RTW89_SCAN_LIST_GUARD 4
242 #define RTW89_SCAN_LIST_LIMIT \
243 		((RTW89_H2C_MAX_SIZE / RTW89_MAC_CHINFO_SIZE) - RTW89_SCAN_LIST_GUARD)
244 
245 #define RTW89_BCN_LOSS_CNT 10
246 
247 struct rtw89_mac_chinfo {
248 	u8 period;
249 	u8 dwell_time;
250 	u8 central_ch;
251 	u8 pri_ch;
252 	u8 bw:3;
253 	u8 notify_action:5;
254 	u8 num_pkt:4;
255 	u8 tx_pkt:1;
256 	u8 pause_data:1;
257 	u8 ch_band:2;
258 	u8 probe_id;
259 	u8 dfs_ch:1;
260 	u8 tx_null:1;
261 	u8 rand_seq_num:1;
262 	u8 cfg_tx_pwr:1;
263 	u8 rsvd0: 4;
264 	u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
265 	u16 tx_pwr_idx;
266 	u8 rsvd1;
267 	struct list_head list;
268 	bool is_psc;
269 };
270 
271 struct rtw89_scan_option {
272 	bool enable;
273 	bool target_ch_mode;
274 };
275 
276 struct rtw89_pktofld_info {
277 	struct list_head list;
278 	u8 id;
279 
280 	/* Below fields are for 6 GHz RNR use only */
281 	u8 ssid[IEEE80211_MAX_SSID_LEN];
282 	u8 ssid_len;
283 	u8 bssid[ETH_ALEN];
284 	u16 channel_6ghz;
285 	bool cancel;
286 };
287 
288 static inline void RTW89_SET_FWCMD_RA_IS_DIS(void *cmd, u32 val)
289 {
290 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(0));
291 }
292 
293 static inline void RTW89_SET_FWCMD_RA_MODE(void *cmd, u32 val)
294 {
295 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(5, 1));
296 }
297 
298 static inline void RTW89_SET_FWCMD_RA_BW_CAP(void *cmd, u32 val)
299 {
300 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 6));
301 }
302 
303 static inline void RTW89_SET_FWCMD_RA_MACID(void *cmd, u32 val)
304 {
305 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
306 }
307 
308 static inline void RTW89_SET_FWCMD_RA_DCM(void *cmd, u32 val)
309 {
310 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(16));
311 }
312 
313 static inline void RTW89_SET_FWCMD_RA_ER(void *cmd, u32 val)
314 {
315 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(17));
316 }
317 
318 static inline void RTW89_SET_FWCMD_RA_INIT_RATE_LV(void *cmd, u32 val)
319 {
320 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(19, 18));
321 }
322 
323 static inline void RTW89_SET_FWCMD_RA_UPD_ALL(void *cmd, u32 val)
324 {
325 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(20));
326 }
327 
328 static inline void RTW89_SET_FWCMD_RA_SGI(void *cmd, u32 val)
329 {
330 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(21));
331 }
332 
333 static inline void RTW89_SET_FWCMD_RA_LDPC(void *cmd, u32 val)
334 {
335 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(22));
336 }
337 
338 static inline void RTW89_SET_FWCMD_RA_STBC(void *cmd, u32 val)
339 {
340 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(23));
341 }
342 
343 static inline void RTW89_SET_FWCMD_RA_SS_NUM(void *cmd, u32 val)
344 {
345 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(26, 24));
346 }
347 
348 static inline void RTW89_SET_FWCMD_RA_GILTF(void *cmd, u32 val)
349 {
350 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(29, 27));
351 }
352 
353 static inline void RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(void *cmd, u32 val)
354 {
355 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(30));
356 }
357 
358 static inline void RTW89_SET_FWCMD_RA_UPD_MASK(void *cmd, u32 val)
359 {
360 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(31));
361 }
362 
363 static inline void RTW89_SET_FWCMD_RA_MASK_0(void *cmd, u32 val)
364 {
365 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(7, 0));
366 }
367 
368 static inline void RTW89_SET_FWCMD_RA_MASK_1(void *cmd, u32 val)
369 {
370 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(15, 8));
371 }
372 
373 static inline void RTW89_SET_FWCMD_RA_MASK_2(void *cmd, u32 val)
374 {
375 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(23, 16));
376 }
377 
378 static inline void RTW89_SET_FWCMD_RA_MASK_3(void *cmd, u32 val)
379 {
380 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 24));
381 }
382 
383 static inline void RTW89_SET_FWCMD_RA_MASK_4(void *cmd, u32 val)
384 {
385 	le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(7, 0));
386 }
387 
388 static inline void RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(void *cmd, u32 val)
389 {
390 	le32p_replace_bits((__le32 *)(cmd) + 0x02, val, BIT(31));
391 }
392 
393 static inline void RTW89_SET_FWCMD_RA_BAND_NUM(void *cmd, u32 val)
394 {
395 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(7, 0));
396 }
397 
398 static inline void RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(void *cmd, u32 val)
399 {
400 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(8));
401 }
402 
403 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(void *cmd, u32 val)
404 {
405 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(9));
406 }
407 
408 static inline void RTW89_SET_FWCMD_RA_CR_TBL_SEL(void *cmd, u32 val)
409 {
410 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(10));
411 }
412 
413 static inline void RTW89_SET_FWCMD_RA_FIX_GILTF_EN(void *cmd, u32 val)
414 {
415 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(11));
416 }
417 
418 static inline void RTW89_SET_FWCMD_RA_FIX_GILTF(void *cmd, u32 val)
419 {
420 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(14, 12));
421 }
422 
423 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(void *cmd, u32 val)
424 {
425 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(23, 16));
426 }
427 
428 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(void *cmd, u32 val)
429 {
430 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(25, 24));
431 }
432 
433 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(void *cmd, u32 val)
434 {
435 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(28, 26));
436 }
437 
438 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_BW(void *cmd, u32 val)
439 {
440 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 29));
441 }
442 
443 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)
444 {
445 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));
446 }
447 
448 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val)
449 {
450 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
451 }
452 
453 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val)
454 {
455 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16));
456 }
457 
458 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val)
459 {
460 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0));
461 }
462 
463 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val)
464 {
465 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4));
466 }
467 
468 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val)
469 {
470 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5));
471 }
472 
473 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val)
474 {
475 	le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0));
476 }
477 
478 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val)
479 {
480 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0));
481 }
482 
483 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val)
484 {
485 	le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0));
486 }
487 
488 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val)
489 {
490 	le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0));
491 }
492 
493 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val)
494 {
495 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0));
496 }
497 
498 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val)
499 {
500 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3));
501 }
502 
503 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val)
504 {
505 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4));
506 }
507 
508 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val)
509 {
510 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5));
511 }
512 
513 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val)
514 {
515 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0));
516 }
517 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)
518 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)
519 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)
520 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)
521 
522 #define FWDL_SECURITY_SECTION_TYPE 9
523 #define FWDL_SECURITY_SIGLEN 512
524 
525 #define GET_FWSECTION_HDR_DL_ADDR(fwhdr)	\
526 	le32_get_bits(*((const __le32 *)(fwhdr)), GENMASK(31, 0))
527 #define GET_FWSECTION_HDR_SECTIONTYPE(fwhdr)	\
528 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(27, 24))
529 #define GET_FWSECTION_HDR_SEC_SIZE(fwhdr)	\
530 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 0))
531 #define GET_FWSECTION_HDR_CHECKSUM(fwhdr)	\
532 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(28))
533 #define GET_FWSECTION_HDR_REDL(fwhdr)	\
534 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(29))
535 #define GET_FWSECTION_HDR_MSSC(fwhdr)	\
536 	le32_get_bits(*((const __le32 *)(fwhdr) + 2), GENMASK(31, 0))
537 
538 #define GET_FW_HDR_MAJOR_VERSION(fwhdr)	\
539 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(7, 0))
540 #define GET_FW_HDR_MINOR_VERSION(fwhdr)	\
541 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(15, 8))
542 #define GET_FW_HDR_SUBVERSION(fwhdr)	\
543 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 16))
544 #define GET_FW_HDR_SUBINDEX(fwhdr)	\
545 	le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(31, 24))
546 #define GET_FW_HDR_LEN(fwhdr)	\
547 	le32_get_bits(*((const __le32 *)(fwhdr) + 3), GENMASK(23, 16))
548 #define GET_FW_HDR_MONTH(fwhdr)		\
549 	le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(7, 0))
550 #define GET_FW_HDR_DATE(fwhdr)		\
551 	le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(15, 8))
552 #define GET_FW_HDR_HOUR(fwhdr)		\
553 	le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(23, 16))
554 #define GET_FW_HDR_MIN(fwhdr)		\
555 	le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(31, 24))
556 #define GET_FW_HDR_YEAR(fwhdr)		\
557 	le32_get_bits(*((const __le32 *)(fwhdr) + 5), GENMASK(31, 0))
558 #define GET_FW_HDR_SEC_NUM(fwhdr)	\
559 	le32_get_bits(*((const __le32 *)(fwhdr) + 6), GENMASK(15, 8))
560 #define GET_FW_HDR_DYN_HDR(fwhdr)	\
561 	le32_get_bits(*((const __le32 *)(fwhdr) + 7), BIT(16))
562 #define GET_FW_HDR_CMD_VERSERION(fwhdr)	\
563 	le32_get_bits(*((const __le32 *)(fwhdr) + 7), GENMASK(31, 24))
564 
565 #define GET_FW_DYNHDR_LEN(fwdynhdr)	\
566 	le32_get_bits(*((const __le32 *)(fwdynhdr)), GENMASK(31, 0))
567 #define GET_FW_DYNHDR_COUNT(fwdynhdr)	\
568 	le32_get_bits(*((const __le32 *)(fwdynhdr) + 1), GENMASK(31, 0))
569 
570 static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val)
571 {
572 	le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0));
573 }
574 
575 static inline void SET_CTRL_INFO_MACID(void *table, u32 val)
576 {
577 	le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
578 }
579 
580 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val)
581 {
582 	le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
583 }
584 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)
585 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val)
586 {
587 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0));
588 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE,
589 			   GENMASK(8, 0));
590 }
591 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
592 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val)
593 {
594 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9));
595 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP,
596 			   BIT(9));
597 }
598 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0)
599 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val)
600 {
601 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10));
602 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW,
603 			   GENMASK(11, 10));
604 }
605 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0)
606 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val)
607 {
608 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12));
609 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF,
610 			   GENMASK(14, 12));
611 }
612 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
613 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val)
614 {
615 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
616 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX,
617 			   BIT(15));
618 }
619 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0)
620 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val)
621 {
622 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16));
623 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL,
624 			   GENMASK(19, 16));
625 }
626 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
627 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val)
628 {
629 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20));
630 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN,
631 			   BIT(20));
632 }
633 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
634 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val)
635 {
636 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21));
637 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN,
638 			   BIT(21));
639 }
640 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
641 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val)
642 {
643 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22));
644 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN,
645 			   BIT(22));
646 }
647 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
648 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val)
649 {
650 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23));
651 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN,
652 			   BIT(23));
653 }
654 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
655 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val)
656 {
657 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25));
658 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB,
659 			   BIT(25));
660 }
661 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
662 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val)
663 {
664 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26));
665 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB,
666 			   BIT(26));
667 }
668 #define SET_CMC_TBL_MASK_TRYRATE BIT(0)
669 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val)
670 {
671 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27));
672 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE,
673 			   BIT(27));
674 }
675 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0)
676 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val)
677 {
678 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28));
679 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY,
680 			   GENMASK(31, 28));
681 }
682 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)
683 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val)
684 {
685 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0));
686 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE,
687 			   GENMASK(8, 0));
688 }
689 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
690 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val)
691 {
692 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9));
693 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL,
694 			   BIT(9));
695 }
696 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
697 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val)
698 {
699 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10));
700 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL,
701 			   BIT(10));
702 }
703 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
704 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val)
705 {
706 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11));
707 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL,
708 			   BIT(11));
709 }
710 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0)
711 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val)
712 {
713 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12));
714 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT,
715 			   GENMASK(15, 12));
716 }
717 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)
718 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val)
719 {
720 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16));
721 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE,
722 			   GENMASK(24, 16));
723 }
724 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
725 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val)
726 {
727 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27));
728 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC,
729 			   BIT(27));
730 }
731 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0)
732 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val)
733 {
734 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28));
735 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE,
736 			   GENMASK(31, 28));
737 }
738 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0)
739 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val)
740 {
741 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0));
742 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT,
743 			   GENMASK(5, 0));
744 }
745 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
746 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val)
747 {
748 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6));
749 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL,
750 			   BIT(6));
751 }
752 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
753 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val)
754 {
755 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7));
756 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL,
757 			   BIT(7));
758 }
759 #define SET_CMC_TBL_MASK_RTS_EN BIT(0)
760 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val)
761 {
762 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8));
763 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN,
764 			   BIT(8));
765 }
766 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
767 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val)
768 {
769 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9));
770 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN,
771 			   BIT(9));
772 }
773 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0)
774 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val)
775 {
776 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10));
777 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS,
778 			   GENMASK(11, 10));
779 }
780 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
781 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val)
782 {
783 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12));
784 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN,
785 			   BIT(12));
786 }
787 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0)
788 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val)
789 {
790 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13));
791 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE,
792 			   GENMASK(14, 13));
793 }
794 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0)
795 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val)
796 {
797 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16));
798 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN,
799 			   GENMASK(26, 16));
800 }
801 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
802 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val)
803 {
804 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
805 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS,
806 			   BIT(27));
807 }
808 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0)
809 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val)
810 {
811 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28));
812 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME,
813 			   GENMASK(31, 28));
814 }
815 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)
816 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val)
817 {
818 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0));
819 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM,
820 			   GENMASK(7, 0));
821 }
822 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0)
823 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val)
824 {
825 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8));
826 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP,
827 			   GENMASK(9, 8));
828 }
829 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0)
830 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val)
831 {
832 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16));
833 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL,
834 			   GENMASK(18, 16));
835 }
836 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0)
837 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val)
838 {
839 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19));
840 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL,
841 			   GENMASK(21, 19));
842 }
843 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0)
844 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val)
845 {
846 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22));
847 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL,
848 			   GENMASK(24, 22));
849 }
850 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0)
851 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val)
852 {
853 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25));
854 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL,
855 			   GENMASK(27, 25));
856 }
857 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0)
858 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val)
859 {
860 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28));
861 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE,
862 			   GENMASK(31, 28));
863 }
864 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0)
865 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val)
866 {
867 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0));
868 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID,
869 			   GENMASK(2, 0));
870 }
871 #define SET_CMC_TBL_MASK_BMC BIT(0)
872 static inline void SET_CMC_TBL_BMC(void *table, u32 val)
873 {
874 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3));
875 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC,
876 			   BIT(3));
877 }
878 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0)
879 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val)
880 {
881 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4));
882 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID,
883 			   GENMASK(7, 4));
884 }
885 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
886 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val)
887 {
888 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
889 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR,
890 			   BIT(8));
891 }
892 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0)
893 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val)
894 {
895 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9));
896 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE,
897 			   GENMASK(11, 9));
898 }
899 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
900 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val)
901 {
902 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12));
903 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM,
904 			   BIT(12));
905 }
906 #define SET_CMC_TBL_MASK_DATA_ER BIT(0)
907 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val)
908 {
909 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13));
910 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER,
911 			   BIT(13));
912 }
913 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
914 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val)
915 {
916 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14));
917 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC,
918 			   BIT(14));
919 }
920 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
921 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val)
922 {
923 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
924 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC,
925 			   BIT(15));
926 }
927 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
928 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val)
929 {
930 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16));
931 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR,
932 			   BIT(16));
933 }
934 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
935 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val)
936 {
937 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17));
938 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH,
939 			   BIT(17));
940 }
941 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
942 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val)
943 {
944 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18));
945 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR,
946 			   BIT(18));
947 }
948 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
949 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val)
950 {
951 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19));
952 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS,
953 			   BIT(19));
954 }
955 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
956 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val)
957 {
958 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20));
959 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER,
960 			   BIT(20));
961 }
962 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
963 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val)
964 {
965 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21));
966 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN,
967 			   BIT(21));
968 }
969 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
970 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val)
971 {
972 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27));
973 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD,
974 			   BIT(27));
975 }
976 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0)
977 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val)
978 {
979 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28));
980 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT,
981 			   GENMASK(31, 28));
982 }
983 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)
984 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val)
985 {
986 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0));
987 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE,
988 			   GENMASK(8, 0));
989 }
990 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
991 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val)
992 {
993 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12));
994 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT,
995 			   BIT(12));
996 }
997 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
998 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val)
999 {
1000 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13));
1001 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT,
1002 			   BIT(13));
1003 }
1004 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0)
1005 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val)
1006 {
1007 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16));
1008 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN,
1009 			   GENMASK(19, 16));
1010 }
1011 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0)
1012 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val)
1013 {
1014 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20));
1015 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A,
1016 			   GENMASK(21, 20));
1017 }
1018 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0)
1019 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val)
1020 {
1021 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22));
1022 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B,
1023 			   GENMASK(23, 22));
1024 }
1025 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0)
1026 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val)
1027 {
1028 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24));
1029 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C,
1030 			   GENMASK(25, 24));
1031 }
1032 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0)
1033 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val)
1034 {
1035 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26));
1036 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D,
1037 			   GENMASK(27, 26));
1038 }
1039 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
1040 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val)
1041 {
1042 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28));
1043 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A,
1044 			   BIT(28));
1045 }
1046 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
1047 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val)
1048 {
1049 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29));
1050 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B,
1051 			   BIT(29));
1052 }
1053 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
1054 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val)
1055 {
1056 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30));
1057 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C,
1058 			   BIT(30));
1059 }
1060 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
1061 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val)
1062 {
1063 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31));
1064 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D,
1065 			   BIT(31));
1066 }
1067 
1068 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0)
1069 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val)
1070 {
1071 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0));
1072 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1073 			   GENMASK(1, 0));
1074 }
1075 
1076 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val)
1077 {
1078 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2));
1079 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1080 			   GENMASK(3, 2));
1081 }
1082 
1083 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val)
1084 {
1085 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4));
1086 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1087 			   GENMASK(5, 4));
1088 }
1089 
1090 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val)
1091 {
1092 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6));
1093 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1094 			   GENMASK(7, 6));
1095 }
1096 
1097 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)
1098 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val)
1099 {
1100 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1101 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX,
1102 			   GENMASK(7, 0));
1103 }
1104 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)
1105 static inline void SET_CMC_TBL_PAID(void *table, u32 val)
1106 {
1107 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8));
1108 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID,
1109 			   GENMASK(16, 8));
1110 }
1111 #define SET_CMC_TBL_MASK_ULDL BIT(0)
1112 static inline void SET_CMC_TBL_ULDL(void *table, u32 val)
1113 {
1114 	le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17));
1115 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL,
1116 			   BIT(17));
1117 }
1118 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0)
1119 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val)
1120 {
1121 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18));
1122 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL,
1123 			   GENMASK(19, 18));
1124 }
1125 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val)
1126 {
1127 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20));
1128 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1129 			   GENMASK(21, 20));
1130 }
1131 
1132 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val)
1133 {
1134 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22));
1135 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1136 			   GENMASK(23, 22));
1137 }
1138 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0)
1139 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val)
1140 {
1141 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24));
1142 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE,
1143 			   GENMASK(27, 24));
1144 }
1145 
1146 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val)
1147 {
1148 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30));
1149 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1150 			   GENMASK(31, 30));
1151 }
1152 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0)
1153 static inline void SET_CMC_TBL_NC(void *table, u32 val)
1154 {
1155 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0));
1156 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC,
1157 			   GENMASK(2, 0));
1158 }
1159 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0)
1160 static inline void SET_CMC_TBL_NR(void *table, u32 val)
1161 {
1162 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3));
1163 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR,
1164 			   GENMASK(5, 3));
1165 }
1166 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0)
1167 static inline void SET_CMC_TBL_NG(void *table, u32 val)
1168 {
1169 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6));
1170 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG,
1171 			   GENMASK(7, 6));
1172 }
1173 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0)
1174 static inline void SET_CMC_TBL_CB(void *table, u32 val)
1175 {
1176 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8));
1177 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB,
1178 			   GENMASK(9, 8));
1179 }
1180 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0)
1181 static inline void SET_CMC_TBL_CS(void *table, u32 val)
1182 {
1183 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10));
1184 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS,
1185 			   GENMASK(11, 10));
1186 }
1187 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
1188 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val)
1189 {
1190 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12));
1191 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN,
1192 			   BIT(12));
1193 }
1194 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
1195 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val)
1196 {
1197 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13));
1198 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN,
1199 			   BIT(13));
1200 }
1201 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
1202 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val)
1203 {
1204 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14));
1205 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN,
1206 			   BIT(14));
1207 }
1208 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
1209 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val)
1210 {
1211 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15));
1212 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN,
1213 			   BIT(15));
1214 }
1215 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)
1216 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val)
1217 {
1218 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16));
1219 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE,
1220 			   GENMASK(24, 16));
1221 }
1222 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0)
1223 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val)
1224 {
1225 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25));
1226 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF,
1227 			   GENMASK(27, 25));
1228 }
1229 
1230 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val)
1231 {
1232 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28));
1233 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1234 			   GENMASK(29, 28));
1235 }
1236 
1237 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0)
1238 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val)
1239 {
1240 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30));
1241 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW,
1242 			   GENMASK(31, 30));
1243 }
1244 
1245 static inline void SET_DCTL_MACID_V1(void *table, u32 val)
1246 {
1247 	le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
1248 }
1249 
1250 static inline void SET_DCTL_OPERATION_V1(void *table, u32 val)
1251 {
1252 	le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
1253 }
1254 
1255 #define SET_DCTL_MASK_QOS_FIELD_V1 GENMASK(7, 0)
1256 static inline void SET_DCTL_QOS_FIELD_V1(void *table, u32 val)
1257 {
1258 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(7, 0));
1259 	le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_FIELD_V1,
1260 			   GENMASK(7, 0));
1261 }
1262 
1263 #define SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID GENMASK(6, 0)
1264 static inline void SET_DCTL_HW_EXSEQ_MACID_V1(void *table, u32 val)
1265 {
1266 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 8));
1267 	le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID,
1268 			   GENMASK(14, 8));
1269 }
1270 
1271 #define SET_DCTL_MASK_QOS_DATA BIT(0)
1272 static inline void SET_DCTL_QOS_DATA_V1(void *table, u32 val)
1273 {
1274 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
1275 	le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_DATA,
1276 			   BIT(15));
1277 }
1278 
1279 #define SET_DCTL_MASK_AES_IV_L GENMASK(15, 0)
1280 static inline void SET_DCTL_AES_IV_L_V1(void *table, u32 val)
1281 {
1282 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 16));
1283 	le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_AES_IV_L,
1284 			   GENMASK(31, 16));
1285 }
1286 
1287 #define SET_DCTL_MASK_AES_IV_H GENMASK(31, 0)
1288 static inline void SET_DCTL_AES_IV_H_V1(void *table, u32 val)
1289 {
1290 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 0));
1291 	le32p_replace_bits((__le32 *)(table) + 10, SET_DCTL_MASK_AES_IV_H,
1292 			   GENMASK(31, 0));
1293 }
1294 
1295 #define SET_DCTL_MASK_SEQ0 GENMASK(11, 0)
1296 static inline void SET_DCTL_SEQ0_V1(void *table, u32 val)
1297 {
1298 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 0));
1299 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ0,
1300 			   GENMASK(11, 0));
1301 }
1302 
1303 #define SET_DCTL_MASK_SEQ1 GENMASK(11, 0)
1304 static inline void SET_DCTL_SEQ1_V1(void *table, u32 val)
1305 {
1306 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(23, 12));
1307 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ1,
1308 			   GENMASK(23, 12));
1309 }
1310 
1311 #define SET_DCTL_MASK_AMSDU_MAX_LEN GENMASK(2, 0)
1312 static inline void SET_DCTL_AMSDU_MAX_LEN_V1(void *table, u32 val)
1313 {
1314 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 24));
1315 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_AMSDU_MAX_LEN,
1316 			   GENMASK(26, 24));
1317 }
1318 
1319 #define SET_DCTL_MASK_STA_AMSDU_EN BIT(0)
1320 static inline void SET_DCTL_STA_AMSDU_EN_V1(void *table, u32 val)
1321 {
1322 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
1323 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_STA_AMSDU_EN,
1324 			   BIT(27));
1325 }
1326 
1327 #define SET_DCTL_MASK_CHKSUM_OFLD_EN BIT(0)
1328 static inline void SET_DCTL_CHKSUM_OFLD_EN_V1(void *table, u32 val)
1329 {
1330 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(28));
1331 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_CHKSUM_OFLD_EN,
1332 			   BIT(28));
1333 }
1334 
1335 #define SET_DCTL_MASK_WITH_LLC BIT(0)
1336 static inline void SET_DCTL_WITH_LLC_V1(void *table, u32 val)
1337 {
1338 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(29));
1339 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_WITH_LLC,
1340 			   BIT(29));
1341 }
1342 
1343 #define SET_DCTL_MASK_SEQ2 GENMASK(11, 0)
1344 static inline void SET_DCTL_SEQ2_V1(void *table, u32 val)
1345 {
1346 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(11, 0));
1347 	le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ2,
1348 			   GENMASK(11, 0));
1349 }
1350 
1351 #define SET_DCTL_MASK_SEQ3 GENMASK(11, 0)
1352 static inline void SET_DCTL_SEQ3_V1(void *table, u32 val)
1353 {
1354 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(23, 12));
1355 	le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ3,
1356 			   GENMASK(23, 12));
1357 }
1358 
1359 #define SET_DCTL_MASK_TGT_IND GENMASK(3, 0)
1360 static inline void SET_DCTL_TGT_IND_V1(void *table, u32 val)
1361 {
1362 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 24));
1363 	le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND,
1364 			   GENMASK(27, 24));
1365 }
1366 
1367 #define SET_DCTL_MASK_TGT_IND_EN BIT(0)
1368 static inline void SET_DCTL_TGT_IND_EN_V1(void *table, u32 val)
1369 {
1370 	le32p_replace_bits((__le32 *)(table) + 4, val, BIT(28));
1371 	le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND_EN,
1372 			   BIT(28));
1373 }
1374 
1375 #define SET_DCTL_MASK_HTC_LB GENMASK(2, 0)
1376 static inline void SET_DCTL_HTC_LB_V1(void *table, u32 val)
1377 {
1378 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 29));
1379 	le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_HTC_LB,
1380 			   GENMASK(31, 29));
1381 }
1382 
1383 #define SET_DCTL_MASK_MHDR_LEN GENMASK(4, 0)
1384 static inline void SET_DCTL_MHDR_LEN_V1(void *table, u32 val)
1385 {
1386 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(4, 0));
1387 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_MHDR_LEN,
1388 			   GENMASK(4, 0));
1389 }
1390 
1391 #define SET_DCTL_MASK_VLAN_TAG_VALID BIT(0)
1392 static inline void SET_DCTL_VLAN_TAG_VALID_V1(void *table, u32 val)
1393 {
1394 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(5));
1395 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_VALID,
1396 			   BIT(5));
1397 }
1398 
1399 #define SET_DCTL_MASK_VLAN_TAG_SEL GENMASK(1, 0)
1400 static inline void SET_DCTL_VLAN_TAG_SEL_V1(void *table, u32 val)
1401 {
1402 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 6));
1403 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_SEL,
1404 			   GENMASK(7, 6));
1405 }
1406 
1407 #define SET_DCTL_MASK_HTC_ORDER BIT(0)
1408 static inline void SET_DCTL_HTC_ORDER_V1(void *table, u32 val)
1409 {
1410 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
1411 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_HTC_ORDER,
1412 			   BIT(8));
1413 }
1414 
1415 #define SET_DCTL_MASK_SEC_KEY_ID GENMASK(1, 0)
1416 static inline void SET_DCTL_SEC_KEY_ID_V1(void *table, u32 val)
1417 {
1418 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(10, 9));
1419 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_KEY_ID,
1420 			   GENMASK(10, 9));
1421 }
1422 
1423 #define SET_DCTL_MASK_WAPI BIT(0)
1424 static inline void SET_DCTL_WAPI_V1(void *table, u32 val)
1425 {
1426 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
1427 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_WAPI,
1428 			   BIT(15));
1429 }
1430 
1431 #define SET_DCTL_MASK_SEC_ENT_MODE GENMASK(1, 0)
1432 static inline void SET_DCTL_SEC_ENT_MODE_V1(void *table, u32 val)
1433 {
1434 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(17, 16));
1435 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENT_MODE,
1436 			   GENMASK(17, 16));
1437 }
1438 
1439 #define SET_DCTL_MASK_SEC_ENTX_KEYID GENMASK(1, 0)
1440 static inline void SET_DCTL_SEC_ENT0_KEYID_V1(void *table, u32 val)
1441 {
1442 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(19, 18));
1443 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1444 			   GENMASK(19, 18));
1445 }
1446 
1447 static inline void SET_DCTL_SEC_ENT1_KEYID_V1(void *table, u32 val)
1448 {
1449 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(21, 20));
1450 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1451 			   GENMASK(21, 20));
1452 }
1453 
1454 static inline void SET_DCTL_SEC_ENT2_KEYID_V1(void *table, u32 val)
1455 {
1456 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(23, 22));
1457 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1458 			   GENMASK(23, 22));
1459 }
1460 
1461 static inline void SET_DCTL_SEC_ENT3_KEYID_V1(void *table, u32 val)
1462 {
1463 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(25, 24));
1464 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1465 			   GENMASK(25, 24));
1466 }
1467 
1468 static inline void SET_DCTL_SEC_ENT4_KEYID_V1(void *table, u32 val)
1469 {
1470 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(27, 26));
1471 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1472 			   GENMASK(27, 26));
1473 }
1474 
1475 static inline void SET_DCTL_SEC_ENT5_KEYID_V1(void *table, u32 val)
1476 {
1477 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(29, 28));
1478 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1479 			   GENMASK(29, 28));
1480 }
1481 
1482 static inline void SET_DCTL_SEC_ENT6_KEYID_V1(void *table, u32 val)
1483 {
1484 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 30));
1485 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1486 			   GENMASK(31, 30));
1487 }
1488 
1489 #define SET_DCTL_MASK_SEC_ENT_VALID GENMASK(7, 0)
1490 static inline void SET_DCTL_SEC_ENT_VALID_V1(void *table, u32 val)
1491 {
1492 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(7, 0));
1493 	le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENT_VALID,
1494 			   GENMASK(7, 0));
1495 }
1496 
1497 #define SET_DCTL_MASK_SEC_ENTX GENMASK(7, 0)
1498 static inline void SET_DCTL_SEC_ENT0_V1(void *table, u32 val)
1499 {
1500 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(15, 8));
1501 	le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1502 			   GENMASK(15, 8));
1503 }
1504 
1505 static inline void SET_DCTL_SEC_ENT1_V1(void *table, u32 val)
1506 {
1507 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 16));
1508 	le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1509 			   GENMASK(23, 16));
1510 }
1511 
1512 static inline void SET_DCTL_SEC_ENT2_V1(void *table, u32 val)
1513 {
1514 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(31, 24));
1515 	le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1516 			   GENMASK(31, 24));
1517 }
1518 
1519 static inline void SET_DCTL_SEC_ENT3_V1(void *table, u32 val)
1520 {
1521 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1522 	le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1523 			   GENMASK(7, 0));
1524 }
1525 
1526 static inline void SET_DCTL_SEC_ENT4_V1(void *table, u32 val)
1527 {
1528 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(15, 8));
1529 	le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1530 			   GENMASK(15, 8));
1531 }
1532 
1533 static inline void SET_DCTL_SEC_ENT5_V1(void *table, u32 val)
1534 {
1535 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 16));
1536 	le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1537 			   GENMASK(23, 16));
1538 }
1539 
1540 static inline void SET_DCTL_SEC_ENT6_V1(void *table, u32 val)
1541 {
1542 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 24));
1543 	le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1544 			   GENMASK(31, 24));
1545 }
1546 
1547 static inline void SET_BCN_UPD_PORT(void *h2c, u32 val)
1548 {
1549 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1550 }
1551 
1552 static inline void SET_BCN_UPD_MBSSID(void *h2c, u32 val)
1553 {
1554 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1555 }
1556 
1557 static inline void SET_BCN_UPD_BAND(void *h2c, u32 val)
1558 {
1559 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1560 }
1561 
1562 static inline void SET_BCN_UPD_GRP_IE_OFST(void *h2c, u32 val)
1563 {
1564 	le32p_replace_bits((__le32 *)h2c, (val - 24) | BIT(7), GENMASK(31, 24));
1565 }
1566 
1567 static inline void SET_BCN_UPD_MACID(void *h2c, u32 val)
1568 {
1569 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1570 }
1571 
1572 static inline void SET_BCN_UPD_SSN_SEL(void *h2c, u32 val)
1573 {
1574 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(9, 8));
1575 }
1576 
1577 static inline void SET_BCN_UPD_SSN_MODE(void *h2c, u32 val)
1578 {
1579 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(11, 10));
1580 }
1581 
1582 static inline void SET_BCN_UPD_RATE(void *h2c, u32 val)
1583 {
1584 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(20, 12));
1585 }
1586 
1587 static inline void SET_BCN_UPD_TXPWR(void *h2c, u32 val)
1588 {
1589 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(23, 21));
1590 }
1591 
1592 static inline void SET_BCN_UPD_TXINFO_CTRL_EN(void *h2c, u32 val)
1593 {
1594 	le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(0));
1595 }
1596 
1597 static inline void SET_BCN_UPD_NTX_PATH_EN(void *h2c, u32 val)
1598 {
1599 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(4, 1));
1600 }
1601 
1602 static inline void SET_BCN_UPD_PATH_MAP_A(void *h2c, u32 val)
1603 {
1604 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(6, 5));
1605 }
1606 
1607 static inline void SET_BCN_UPD_PATH_MAP_B(void *h2c, u32 val)
1608 {
1609 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(8, 7));
1610 }
1611 
1612 static inline void SET_BCN_UPD_PATH_MAP_C(void *h2c, u32 val)
1613 {
1614 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(10, 9));
1615 }
1616 
1617 static inline void SET_BCN_UPD_PATH_MAP_D(void *h2c, u32 val)
1618 {
1619 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(12, 11));
1620 }
1621 
1622 static inline void SET_BCN_UPD_PATH_ANTSEL_A(void *h2c, u32 val)
1623 {
1624 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  BIT(13));
1625 }
1626 
1627 static inline void SET_BCN_UPD_PATH_ANTSEL_B(void *h2c, u32 val)
1628 {
1629 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  BIT(14));
1630 }
1631 
1632 static inline void SET_BCN_UPD_PATH_ANTSEL_C(void *h2c, u32 val)
1633 {
1634 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  BIT(15));
1635 }
1636 
1637 static inline void SET_BCN_UPD_PATH_ANTSEL_D(void *h2c, u32 val)
1638 {
1639 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  BIT(16));
1640 }
1641 
1642 static inline void SET_BCN_UPD_CSA_OFST(void *h2c, u32 val)
1643 {
1644 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(31, 17));
1645 }
1646 
1647 static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val)
1648 {
1649 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1650 }
1651 
1652 static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val)
1653 {
1654 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8));
1655 }
1656 
1657 static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val)
1658 {
1659 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10));
1660 }
1661 
1662 static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val)
1663 {
1664 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13));
1665 }
1666 
1667 static inline void SET_JOININFO_MACID(void *h2c, u32 val)
1668 {
1669 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1670 }
1671 
1672 static inline void SET_JOININFO_OP(void *h2c, u32 val)
1673 {
1674 	le32p_replace_bits((__le32 *)h2c, val, BIT(8));
1675 }
1676 
1677 static inline void SET_JOININFO_BAND(void *h2c, u32 val)
1678 {
1679 	le32p_replace_bits((__le32 *)h2c, val, BIT(9));
1680 }
1681 
1682 static inline void SET_JOININFO_WMM(void *h2c, u32 val)
1683 {
1684 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10));
1685 }
1686 
1687 static inline void SET_JOININFO_TGR(void *h2c, u32 val)
1688 {
1689 	le32p_replace_bits((__le32 *)h2c, val, BIT(12));
1690 }
1691 
1692 static inline void SET_JOININFO_ISHESTA(void *h2c, u32 val)
1693 {
1694 	le32p_replace_bits((__le32 *)h2c, val, BIT(13));
1695 }
1696 
1697 static inline void SET_JOININFO_DLBW(void *h2c, u32 val)
1698 {
1699 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14));
1700 }
1701 
1702 static inline void SET_JOININFO_TF_MAC_PAD(void *h2c, u32 val)
1703 {
1704 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16));
1705 }
1706 
1707 static inline void SET_JOININFO_DL_T_PE(void *h2c, u32 val)
1708 {
1709 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18));
1710 }
1711 
1712 static inline void SET_JOININFO_PORT_ID(void *h2c, u32 val)
1713 {
1714 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21));
1715 }
1716 
1717 static inline void SET_JOININFO_NET_TYPE(void *h2c, u32 val)
1718 {
1719 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24));
1720 }
1721 
1722 static inline void SET_JOININFO_WIFI_ROLE(void *h2c, u32 val)
1723 {
1724 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26));
1725 }
1726 
1727 static inline void SET_JOININFO_SELF_ROLE(void *h2c, u32 val)
1728 {
1729 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30));
1730 }
1731 
1732 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val)
1733 {
1734 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1735 }
1736 
1737 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val)
1738 {
1739 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1740 }
1741 
1742 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val)
1743 {
1744 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1745 }
1746 
1747 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val)
1748 {
1749 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1750 }
1751 
1752 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val)
1753 {
1754 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1755 }
1756 
1757 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val)
1758 {
1759 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1760 }
1761 
1762 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val)
1763 {
1764 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1765 }
1766 
1767 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val)
1768 {
1769 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1770 }
1771 
1772 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val)
1773 {
1774 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
1775 }
1776 
1777 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val)
1778 {
1779 	le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0));
1780 }
1781 
1782 static inline void SET_BA_CAM_VALID(void *h2c, u32 val)
1783 {
1784 	le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1785 }
1786 
1787 static inline void SET_BA_CAM_INIT_REQ(void *h2c, u32 val)
1788 {
1789 	le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1790 }
1791 
1792 static inline void SET_BA_CAM_ENTRY_IDX(void *h2c, u32 val)
1793 {
1794 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2));
1795 }
1796 
1797 static inline void SET_BA_CAM_TID(void *h2c, u32 val)
1798 {
1799 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4));
1800 }
1801 
1802 static inline void SET_BA_CAM_MACID(void *h2c, u32 val)
1803 {
1804 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1805 }
1806 
1807 static inline void SET_BA_CAM_BMAP_SIZE(void *h2c, u32 val)
1808 {
1809 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1810 }
1811 
1812 static inline void SET_BA_CAM_SSN(void *h2c, u32 val)
1813 {
1814 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20));
1815 }
1816 
1817 static inline void SET_BA_CAM_UID(void *h2c, u32 val)
1818 {
1819 	le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(7, 0));
1820 }
1821 
1822 static inline void SET_BA_CAM_STD_EN(void *h2c, u32 val)
1823 {
1824 	le32p_replace_bits((__le32 *)h2c + 1, val, BIT(8));
1825 }
1826 
1827 static inline void SET_BA_CAM_BAND(void *h2c, u32 val)
1828 {
1829 	le32p_replace_bits((__le32 *)h2c + 1, val, BIT(9));
1830 }
1831 
1832 static inline void SET_BA_CAM_ENTRY_IDX_V1(void *h2c, u32 val)
1833 {
1834 	le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 28));
1835 }
1836 
1837 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val)
1838 {
1839 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1840 }
1841 
1842 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val)
1843 {
1844 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1845 }
1846 
1847 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val)
1848 {
1849 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1850 }
1851 
1852 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val)
1853 {
1854 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20));
1855 }
1856 
1857 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val)
1858 {
1859 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1860 }
1861 
1862 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val)
1863 {
1864 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0));
1865 }
1866 
1867 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val)
1868 {
1869 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1));
1870 }
1871 
1872 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val)
1873 {
1874 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2));
1875 }
1876 
1877 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val)
1878 {
1879 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3));
1880 }
1881 
1882 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val)
1883 {
1884 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1885 }
1886 
1887 static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val)
1888 {
1889 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0));
1890 }
1891 
1892 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val)
1893 {
1894 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
1895 }
1896 
1897 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val)
1898 {
1899 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
1900 }
1901 
1902 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val)
1903 {
1904 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
1905 }
1906 
1907 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val)
1908 {
1909 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
1910 }
1911 
1912 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val)
1913 {
1914 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0));
1915 }
1916 
1917 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val)
1918 {
1919 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8));
1920 }
1921 
1922 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val)
1923 {
1924 	le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
1925 }
1926 
1927 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val)
1928 {
1929 	le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
1930 }
1931 
1932 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val)
1933 {
1934 	le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
1935 }
1936 
1937 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val)
1938 {
1939 	le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0));
1940 }
1941 
1942 static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val)
1943 {
1944 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0));
1945 }
1946 
1947 static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val)
1948 {
1949 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1950 }
1951 
1952 static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val)
1953 {
1954 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16));
1955 }
1956 
1957 static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val)
1958 {
1959 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1960 }
1961 
1962 static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val)
1963 {
1964 	le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1965 }
1966 
1967 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val)
1968 {
1969 	le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1970 }
1971 
1972 static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val)
1973 {
1974 	le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1975 }
1976 
1977 static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val)
1978 {
1979 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1980 }
1981 
1982 static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val)
1983 {
1984 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1985 }
1986 
1987 static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val)
1988 {
1989 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1990 }
1991 
1992 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val)
1993 {
1994 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1995 }
1996 
1997 static inline void RTW89_SET_WOW_GLOBAL_ENABLE(void *h2c, u32 val)
1998 {
1999 	le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2000 }
2001 
2002 static inline void RTW89_SET_WOW_GLOBAL_DROP_ALL_PKT(void *h2c, u32 val)
2003 {
2004 	le32p_replace_bits((__le32 *)h2c, val, BIT(1));
2005 }
2006 
2007 static inline void RTW89_SET_WOW_GLOBAL_RX_PARSE_AFTER_WAKE(void *h2c, u32 val)
2008 {
2009 	le32p_replace_bits((__le32 *)h2c, val, BIT(2));
2010 }
2011 
2012 static inline void RTW89_SET_WOW_GLOBAL_WAKE_BAR_PULLED(void *h2c, u32 val)
2013 {
2014 	le32p_replace_bits((__le32 *)h2c, val, BIT(3));
2015 }
2016 
2017 static inline void RTW89_SET_WOW_GLOBAL_MAC_ID(void *h2c, u32 val)
2018 {
2019 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
2020 }
2021 
2022 static inline void RTW89_SET_WOW_GLOBAL_PAIRWISE_SEC_ALGO(void *h2c, u32 val)
2023 {
2024 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
2025 }
2026 
2027 static inline void RTW89_SET_WOW_GLOBAL_GROUP_SEC_ALGO(void *h2c, u32 val)
2028 {
2029 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
2030 }
2031 
2032 static inline void RTW89_SET_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT(void *h2c, u32 val)
2033 {
2034 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
2035 }
2036 
2037 static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val)
2038 {
2039 	le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2040 }
2041 
2042 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val)
2043 {
2044 	le32p_replace_bits((__le32 *)h2c, val, BIT(1));
2045 }
2046 
2047 static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val)
2048 {
2049 	le32p_replace_bits((__le32 *)h2c, val, BIT(2));
2050 }
2051 
2052 static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val)
2053 {
2054 	le32p_replace_bits((__le32 *)h2c, val, BIT(3));
2055 }
2056 
2057 static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val)
2058 {
2059 	le32p_replace_bits((__le32 *)h2c, val, BIT(4));
2060 }
2061 
2062 static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val)
2063 {
2064 	le32p_replace_bits((__le32 *)h2c, val, BIT(5));
2065 }
2066 
2067 static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val)
2068 {
2069 	le32p_replace_bits((__le32 *)h2c, val, BIT(6));
2070 }
2071 
2072 static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val)
2073 {
2074 	le32p_replace_bits((__le32 *)h2c, val, BIT(7));
2075 }
2076 
2077 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val)
2078 {
2079 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
2080 }
2081 
2082 static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val)
2083 {
2084 	le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2085 }
2086 
2087 static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val)
2088 {
2089 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1));
2090 }
2091 
2092 static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val)
2093 {
2094 	le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0));
2095 }
2096 
2097 static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val)
2098 {
2099 	le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0));
2100 }
2101 
2102 static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val)
2103 {
2104 	le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0));
2105 }
2106 
2107 static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val)
2108 {
2109 	le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0));
2110 }
2111 
2112 static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val)
2113 {
2114 	le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0));
2115 }
2116 
2117 static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val)
2118 {
2119 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22));
2120 }
2121 
2122 static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val)
2123 {
2124 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23));
2125 }
2126 
2127 static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val)
2128 {
2129 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24));
2130 }
2131 
2132 static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val)
2133 {
2134 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25));
2135 }
2136 
2137 static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val)
2138 {
2139 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26));
2140 }
2141 
2142 static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val)
2143 {
2144 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31));
2145 }
2146 
2147 enum rtw89_btc_btf_h2c_class {
2148 	BTFC_SET = 0x10,
2149 	BTFC_GET = 0x11,
2150 	BTFC_FW_EVENT = 0x12,
2151 };
2152 
2153 enum rtw89_btc_btf_set {
2154 	SET_REPORT_EN = 0x0,
2155 	SET_SLOT_TABLE,
2156 	SET_MREG_TABLE,
2157 	SET_CX_POLICY,
2158 	SET_GPIO_DBG,
2159 	SET_DRV_INFO,
2160 	SET_DRV_EVENT,
2161 	SET_BT_WREG_ADDR,
2162 	SET_BT_WREG_VAL,
2163 	SET_BT_RREG_ADDR,
2164 	SET_BT_WL_CH_INFO,
2165 	SET_BT_INFO_REPORT,
2166 	SET_BT_IGNORE_WLAN_ACT,
2167 	SET_BT_TX_PWR,
2168 	SET_BT_LNA_CONSTRAIN,
2169 	SET_BT_GOLDEN_RX_RANGE,
2170 	SET_BT_PSD_REPORT,
2171 	SET_H2C_TEST,
2172 	SET_MAX1,
2173 };
2174 
2175 enum rtw89_btc_cxdrvinfo {
2176 	CXDRVINFO_INIT = 0,
2177 	CXDRVINFO_ROLE,
2178 	CXDRVINFO_DBCC,
2179 	CXDRVINFO_SMAP,
2180 	CXDRVINFO_RFK,
2181 	CXDRVINFO_RUN,
2182 	CXDRVINFO_CTRL,
2183 	CXDRVINFO_SCAN,
2184 	CXDRVINFO_TRX,  /* WL traffic to WL fw */
2185 	CXDRVINFO_MAX,
2186 };
2187 
2188 enum rtw89_scan_mode {
2189 	RTW89_SCAN_IMMEDIATE,
2190 };
2191 
2192 enum rtw89_scan_type {
2193 	RTW89_SCAN_ONCE,
2194 };
2195 
2196 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val)
2197 {
2198 	u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0));
2199 }
2200 
2201 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val)
2202 {
2203 	u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0));
2204 }
2205 
2206 struct rtw89_h2c_cxhdr {
2207 	u8 type;
2208 	u8 len;
2209 } __packed;
2210 
2211 #define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr)
2212 
2213 struct rtw89_h2c_cxinit {
2214 	struct rtw89_h2c_cxhdr hdr;
2215 	u8 ant_type;
2216 	u8 ant_num;
2217 	u8 ant_iso;
2218 	u8 ant_info;
2219 	u8 mod_rfe;
2220 	u8 mod_cv;
2221 	u8 mod_info;
2222 	u8 mod_adie_kt;
2223 	u8 wl_gch;
2224 	u8 info;
2225 	u8 rsvd;
2226 	u8 rsvd1;
2227 } __packed;
2228 
2229 #define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0)
2230 #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1)
2231 #define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2)
2232 #define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4)
2233 
2234 #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0)
2235 #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1)
2236 #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2)
2237 #define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3)
2238 
2239 #define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0)
2240 #define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1)
2241 #define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2)
2242 #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3)
2243 #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4)
2244 
2245 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val)
2246 {
2247 	u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0));
2248 }
2249 
2250 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val)
2251 {
2252 	u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0));
2253 }
2254 
2255 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val)
2256 {
2257 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0));
2258 }
2259 
2260 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val)
2261 {
2262 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1));
2263 }
2264 
2265 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val)
2266 {
2267 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2));
2268 }
2269 
2270 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val)
2271 {
2272 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3));
2273 }
2274 
2275 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val)
2276 {
2277 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4));
2278 }
2279 
2280 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val)
2281 {
2282 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5));
2283 }
2284 
2285 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val)
2286 {
2287 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6));
2288 }
2289 
2290 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val)
2291 {
2292 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7));
2293 }
2294 
2295 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val)
2296 {
2297 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8));
2298 }
2299 
2300 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val)
2301 {
2302 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9));
2303 }
2304 
2305 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val)
2306 {
2307 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10));
2308 }
2309 
2310 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val)
2311 {
2312 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11));
2313 }
2314 
2315 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset)
2316 {
2317 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2318 }
2319 
2320 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset)
2321 {
2322 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2323 }
2324 
2325 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset)
2326 {
2327 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2328 }
2329 
2330 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset)
2331 {
2332 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2333 }
2334 
2335 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset)
2336 {
2337 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2338 }
2339 
2340 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset)
2341 {
2342 	u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2343 }
2344 
2345 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset)
2346 {
2347 	u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2348 }
2349 
2350 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset)
2351 {
2352 	u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2353 }
2354 
2355 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset)
2356 {
2357 	u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2358 }
2359 
2360 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset)
2361 {
2362 	le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0));
2363 }
2364 
2365 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset)
2366 {
2367 	le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0));
2368 }
2369 
2370 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset)
2371 {
2372 	le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0));
2373 }
2374 
2375 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset)
2376 {
2377 	le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0));
2378 }
2379 
2380 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset)
2381 {
2382 	le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0));
2383 }
2384 
2385 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset)
2386 {
2387 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2388 }
2389 
2390 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset)
2391 {
2392 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2393 }
2394 
2395 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset)
2396 {
2397 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2398 }
2399 
2400 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset)
2401 {
2402 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2403 }
2404 
2405 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset)
2406 {
2407 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2408 }
2409 
2410 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset)
2411 {
2412 	u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2413 }
2414 
2415 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset)
2416 {
2417 	u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2418 }
2419 
2420 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset)
2421 {
2422 	u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2423 }
2424 
2425 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset)
2426 {
2427 	u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2428 }
2429 
2430 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset)
2431 {
2432 	le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0));
2433 }
2434 
2435 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset)
2436 {
2437 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0));
2438 }
2439 
2440 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset)
2441 {
2442 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0));
2443 }
2444 
2445 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset)
2446 {
2447 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0));
2448 }
2449 
2450 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset)
2451 {
2452 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1));
2453 }
2454 
2455 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset)
2456 {
2457 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2));
2458 }
2459 
2460 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset)
2461 {
2462 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4));
2463 }
2464 
2465 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val)
2466 {
2467 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0));
2468 }
2469 
2470 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val)
2471 {
2472 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1));
2473 }
2474 
2475 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val)
2476 {
2477 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2));
2478 }
2479 
2480 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val)
2481 {
2482 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3));
2483 }
2484 
2485 static inline void RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val)
2486 {
2487 	u8p_replace_bits((u8 *)cmd + 2, val, GENMASK(7, 0));
2488 }
2489 
2490 static inline void RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val)
2491 {
2492 	u8p_replace_bits((u8 *)cmd + 3, val, GENMASK(7, 0));
2493 }
2494 
2495 static inline void RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val)
2496 {
2497 	u8p_replace_bits((u8 *)cmd + 4, val, GENMASK(7, 0));
2498 }
2499 
2500 static inline void RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val)
2501 {
2502 	u8p_replace_bits((u8 *)cmd + 5, val, GENMASK(7, 0));
2503 }
2504 
2505 static inline void RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val)
2506 {
2507 	u8p_replace_bits((u8 *)cmd + 6, val, GENMASK(7, 0));
2508 }
2509 
2510 static inline void RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val)
2511 {
2512 	u8p_replace_bits((u8 *)cmd + 7, val, GENMASK(7, 0));
2513 }
2514 
2515 static inline void RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val)
2516 {
2517 	u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0));
2518 }
2519 
2520 static inline void RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val)
2521 {
2522 	u8p_replace_bits((u8 *)cmd + 9, val, GENMASK(7, 0));
2523 }
2524 
2525 static inline void RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val)
2526 {
2527 	u8p_replace_bits((u8 *)cmd + 10, val, GENMASK(7, 0));
2528 }
2529 
2530 static inline void RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val)
2531 {
2532 	u8p_replace_bits((u8 *)cmd + 11, val, GENMASK(7, 0));
2533 }
2534 
2535 static inline void RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val)
2536 {
2537 	u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0));
2538 }
2539 
2540 static inline void RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val)
2541 {
2542 	u8p_replace_bits((u8 *)cmd + 13, val, GENMASK(7, 0));
2543 }
2544 
2545 static inline void RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val)
2546 {
2547 	le16p_replace_bits((__le16 *)((u8 *)cmd + 14), val, GENMASK(15, 0));
2548 }
2549 
2550 static inline void RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val)
2551 {
2552 	le16p_replace_bits((__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0));
2553 }
2554 
2555 static inline void RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val)
2556 {
2557 	le32p_replace_bits((__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0));
2558 }
2559 
2560 static inline void RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val)
2561 {
2562 	le32p_replace_bits((__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0));
2563 }
2564 
2565 static inline void RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val)
2566 {
2567 	le32p_replace_bits((__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0));
2568 }
2569 
2570 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val)
2571 {
2572 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0));
2573 }
2574 
2575 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val)
2576 {
2577 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2));
2578 }
2579 
2580 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val)
2581 {
2582 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6));
2583 }
2584 
2585 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val)
2586 {
2587 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8));
2588 }
2589 
2590 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val)
2591 {
2592 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10));
2593 }
2594 
2595 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val)
2596 {
2597 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2598 }
2599 
2600 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val)
2601 {
2602 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8));
2603 }
2604 
2605 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val)
2606 {
2607 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16));
2608 }
2609 
2610 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_NUM(void *cmd, u32 val)
2611 {
2612 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2613 }
2614 
2615 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_SIZE(void *cmd, u32 val)
2616 {
2617 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8));
2618 }
2619 
2620 static inline void RTW89_SET_FWCMD_CHINFO_PERIOD(void *cmd, u32 val)
2621 {
2622 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2623 }
2624 
2625 static inline void RTW89_SET_FWCMD_CHINFO_DWELL(void *cmd, u32 val)
2626 {
2627 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8));
2628 }
2629 
2630 static inline void RTW89_SET_FWCMD_CHINFO_CENTER_CH(void *cmd, u32 val)
2631 {
2632 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 16));
2633 }
2634 
2635 static inline void RTW89_SET_FWCMD_CHINFO_PRI_CH(void *cmd, u32 val)
2636 {
2637 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 24));
2638 }
2639 
2640 static inline void RTW89_SET_FWCMD_CHINFO_BW(void *cmd, u32 val)
2641 {
2642 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(2, 0));
2643 }
2644 
2645 static inline void RTW89_SET_FWCMD_CHINFO_ACTION(void *cmd, u32 val)
2646 {
2647 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 3));
2648 }
2649 
2650 static inline void RTW89_SET_FWCMD_CHINFO_NUM_PKT(void *cmd, u32 val)
2651 {
2652 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(11, 8));
2653 }
2654 
2655 static inline void RTW89_SET_FWCMD_CHINFO_TX(void *cmd, u32 val)
2656 {
2657 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(12));
2658 }
2659 
2660 static inline void RTW89_SET_FWCMD_CHINFO_PAUSE_DATA(void *cmd, u32 val)
2661 {
2662 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(13));
2663 }
2664 
2665 static inline void RTW89_SET_FWCMD_CHINFO_BAND(void *cmd, u32 val)
2666 {
2667 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 14));
2668 }
2669 
2670 static inline void RTW89_SET_FWCMD_CHINFO_PKT_ID(void *cmd, u32 val)
2671 {
2672 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16));
2673 }
2674 
2675 static inline void RTW89_SET_FWCMD_CHINFO_DFS(void *cmd, u32 val)
2676 {
2677 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(24));
2678 }
2679 
2680 static inline void RTW89_SET_FWCMD_CHINFO_TX_NULL(void *cmd, u32 val)
2681 {
2682 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(25));
2683 }
2684 
2685 static inline void RTW89_SET_FWCMD_CHINFO_RANDOM(void *cmd, u32 val)
2686 {
2687 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(26));
2688 }
2689 
2690 static inline void RTW89_SET_FWCMD_CHINFO_CFG_TX(void *cmd, u32 val)
2691 {
2692 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(27));
2693 }
2694 
2695 static inline void RTW89_SET_FWCMD_CHINFO_PKT0(void *cmd, u32 val)
2696 {
2697 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(7, 0));
2698 }
2699 
2700 static inline void RTW89_SET_FWCMD_CHINFO_PKT1(void *cmd, u32 val)
2701 {
2702 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 8));
2703 }
2704 
2705 static inline void RTW89_SET_FWCMD_CHINFO_PKT2(void *cmd, u32 val)
2706 {
2707 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16));
2708 }
2709 
2710 static inline void RTW89_SET_FWCMD_CHINFO_PKT3(void *cmd, u32 val)
2711 {
2712 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(31, 24));
2713 }
2714 
2715 static inline void RTW89_SET_FWCMD_CHINFO_PKT4(void *cmd, u32 val)
2716 {
2717 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(7, 0));
2718 }
2719 
2720 static inline void RTW89_SET_FWCMD_CHINFO_PKT5(void *cmd, u32 val)
2721 {
2722 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(15, 8));
2723 }
2724 
2725 static inline void RTW89_SET_FWCMD_CHINFO_PKT6(void *cmd, u32 val)
2726 {
2727 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(23, 16));
2728 }
2729 
2730 static inline void RTW89_SET_FWCMD_CHINFO_PKT7(void *cmd, u32 val)
2731 {
2732 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 24));
2733 }
2734 
2735 static inline void RTW89_SET_FWCMD_CHINFO_POWER_IDX(void *cmd, u32 val)
2736 {
2737 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(15, 0));
2738 }
2739 
2740 struct rtw89_h2c_scanofld {
2741 	__le32 w0;
2742 	__le32 w1;
2743 	__le32 w2;
2744 	__le32 tsf_high;
2745 	__le32 tsf_low;
2746 	__le32 w5;
2747 	__le32 w6;
2748 } __packed;
2749 
2750 #define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0)
2751 #define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8)
2752 #define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16)
2753 #define RTW89_H2C_SCANOFLD_W0_BAND BIT(19)
2754 #define RTW89_H2C_SCANOFLD_W0_OPERATION GENMASK(21, 20)
2755 #define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND GENMASK(23, 22)
2756 #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0)
2757 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1)
2758 #define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2)
2759 #define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE GENMASK(4, 3)
2760 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5)
2761 #define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8)
2762 #define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16)
2763 #define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24)
2764 #define RTW89_H2C_SCANOFLD_W2_NORM_PD GENMASK(15, 0)
2765 #define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16)
2766 
2767 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val)
2768 {
2769 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2770 }
2771 
2772 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val)
2773 {
2774 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8));
2775 }
2776 
2777 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val)
2778 {
2779 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12));
2780 }
2781 
2782 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val)
2783 {
2784 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16));
2785 }
2786 
2787 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val)
2788 {
2789 	le32p_replace_bits((__le32 *)cmd, val, BIT(20));
2790 }
2791 
2792 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val)
2793 {
2794 	le32p_replace_bits((__le32 *)cmd, val, BIT(21));
2795 }
2796 
2797 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val)
2798 {
2799 	*((__le32 *)cmd + 1) = val;
2800 }
2801 
2802 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val)
2803 {
2804 	*((__le32 *)cmd + 2) = val;
2805 }
2806 
2807 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val)
2808 {
2809 	*((__le32 *)cmd + 3) = val;
2810 }
2811 
2812 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val)
2813 {
2814 	le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0));
2815 }
2816 
2817 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val)
2818 {
2819 	u8 ctwnd;
2820 
2821 	if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT))
2822 		return;
2823 	ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val);
2824 	le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8));
2825 }
2826 
2827 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val)
2828 {
2829 	le32p_replace_bits((__le32 *)cmd, val, BIT(0));
2830 }
2831 
2832 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val)
2833 {
2834 	le32p_replace_bits((__le32 *)cmd, val, BIT(1));
2835 }
2836 
2837 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val)
2838 {
2839 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2));
2840 }
2841 
2842 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val)
2843 {
2844 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16));
2845 }
2846 
2847 enum rtw89_fw_mcc_c2h_rpt_cfg {
2848 	RTW89_FW_MCC_C2H_RPT_OFF	= 0,
2849 	RTW89_FW_MCC_C2H_RPT_FAIL_ONLY	= 1,
2850 	RTW89_FW_MCC_C2H_RPT_ALL	= 2,
2851 };
2852 
2853 struct rtw89_fw_mcc_add_req {
2854 	u8 macid;
2855 	u8 central_ch_seg0;
2856 	u8 central_ch_seg1;
2857 	u8 primary_ch;
2858 	enum rtw89_bandwidth bandwidth: 4;
2859 	u32 group: 2;
2860 	u32 c2h_rpt: 2;
2861 	u32 dis_tx_null: 1;
2862 	u32 dis_sw_retry: 1;
2863 	u32 in_curr_ch: 1;
2864 	u32 sw_retry_count: 3;
2865 	u32 tx_null_early: 4;
2866 	u32 btc_in_2g: 1;
2867 	u32 pta_en: 1;
2868 	u32 rfk_by_pass: 1;
2869 	u32 ch_band_type: 2;
2870 	u32 rsvd0: 9;
2871 	u32 duration;
2872 	u8 courtesy_en;
2873 	u8 courtesy_num;
2874 	u8 courtesy_target;
2875 	u8 rsvd1;
2876 };
2877 
2878 static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val)
2879 {
2880 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2881 }
2882 
2883 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val)
2884 {
2885 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
2886 }
2887 
2888 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val)
2889 {
2890 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
2891 }
2892 
2893 static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val)
2894 {
2895 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
2896 }
2897 
2898 static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val)
2899 {
2900 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0));
2901 }
2902 
2903 static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val)
2904 {
2905 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4));
2906 }
2907 
2908 static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val)
2909 {
2910 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6));
2911 }
2912 
2913 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val)
2914 {
2915 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8));
2916 }
2917 
2918 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val)
2919 {
2920 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9));
2921 }
2922 
2923 static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val)
2924 {
2925 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10));
2926 }
2927 
2928 static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val)
2929 {
2930 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11));
2931 }
2932 
2933 static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val)
2934 {
2935 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14));
2936 }
2937 
2938 static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val)
2939 {
2940 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18));
2941 }
2942 
2943 static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val)
2944 {
2945 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19));
2946 }
2947 
2948 static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val)
2949 {
2950 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20));
2951 }
2952 
2953 static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val)
2954 {
2955 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21));
2956 }
2957 
2958 static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val)
2959 {
2960 	le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
2961 }
2962 
2963 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val)
2964 {
2965 	le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0));
2966 }
2967 
2968 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val)
2969 {
2970 	le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8));
2971 }
2972 
2973 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val)
2974 {
2975 	le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16));
2976 }
2977 
2978 struct rtw89_fw_mcc_start_req {
2979 	u32 group: 2;
2980 	u32 btc_in_group: 1;
2981 	u32 old_group_action: 2;
2982 	u32 old_group: 2;
2983 	u32 rsvd0: 9;
2984 	u32 notify_cnt: 3;
2985 	u32 rsvd1: 2;
2986 	u32 notify_rxdbg_en: 1;
2987 	u32 rsvd2: 2;
2988 	u32 macid: 8;
2989 	u32 tsf_low;
2990 	u32 tsf_high;
2991 };
2992 
2993 static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val)
2994 {
2995 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
2996 }
2997 
2998 static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val)
2999 {
3000 	le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3001 }
3002 
3003 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val)
3004 {
3005 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3));
3006 }
3007 
3008 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val)
3009 {
3010 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5));
3011 }
3012 
3013 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val)
3014 {
3015 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16));
3016 }
3017 
3018 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val)
3019 {
3020 	le32p_replace_bits((__le32 *)cmd, val, BIT(21));
3021 }
3022 
3023 static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val)
3024 {
3025 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3026 }
3027 
3028 static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val)
3029 {
3030 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3031 }
3032 
3033 static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val)
3034 {
3035 	le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3036 }
3037 
3038 static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val)
3039 {
3040 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
3041 }
3042 
3043 static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val)
3044 {
3045 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8));
3046 }
3047 
3048 static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val)
3049 {
3050 	le32p_replace_bits((__le32 *)cmd, val, BIT(10));
3051 }
3052 
3053 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val)
3054 {
3055 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3056 }
3057 
3058 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val)
3059 {
3060 	le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3061 }
3062 
3063 static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val)
3064 {
3065 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3066 }
3067 
3068 struct rtw89_fw_mcc_tsf_req {
3069 	u8 group: 2;
3070 	u8 rsvd0: 6;
3071 	u8 macid_x;
3072 	u8 macid_y;
3073 	u8 rsvd1;
3074 };
3075 
3076 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val)
3077 {
3078 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3079 }
3080 
3081 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val)
3082 {
3083 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3084 }
3085 
3086 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val)
3087 {
3088 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3089 }
3090 
3091 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val)
3092 {
3093 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3094 }
3095 
3096 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val)
3097 {
3098 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3099 }
3100 
3101 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val)
3102 {
3103 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3104 }
3105 
3106 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd,
3107 							   u8 *bitmap, u8 len)
3108 {
3109 	memcpy((__le32 *)cmd + 1, bitmap, len);
3110 }
3111 
3112 static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val)
3113 {
3114 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3115 }
3116 
3117 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val)
3118 {
3119 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3120 }
3121 
3122 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val)
3123 {
3124 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3125 }
3126 
3127 static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val)
3128 {
3129 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3130 }
3131 
3132 struct rtw89_fw_mcc_duration {
3133 	u32 group: 2;
3134 	u32 btc_in_group: 1;
3135 	u32 rsvd0: 5;
3136 	u32 start_macid: 8;
3137 	u32 macid_x: 8;
3138 	u32 macid_y: 8;
3139 	u32 start_tsf_low;
3140 	u32 start_tsf_high;
3141 	u32 duration_x;
3142 	u32 duration_y;
3143 };
3144 
3145 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val)
3146 {
3147 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3148 }
3149 
3150 static
3151 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val)
3152 {
3153 	le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3154 }
3155 
3156 static
3157 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val)
3158 {
3159 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3160 }
3161 
3162 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val)
3163 {
3164 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3165 }
3166 
3167 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val)
3168 {
3169 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3170 }
3171 
3172 static
3173 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val)
3174 {
3175 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3176 }
3177 
3178 static
3179 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val)
3180 {
3181 	le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3182 }
3183 
3184 static
3185 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val)
3186 {
3187 	le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
3188 }
3189 
3190 static
3191 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val)
3192 {
3193 	le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
3194 }
3195 
3196 #define RTW89_C2H_HEADER_LEN 8
3197 
3198 #define RTW89_GET_C2H_CATEGORY(c2h) \
3199 	le32_get_bits(*((const __le32 *)c2h), GENMASK(1, 0))
3200 #define RTW89_GET_C2H_CLASS(c2h) \
3201 	le32_get_bits(*((const __le32 *)c2h), GENMASK(7, 2))
3202 #define RTW89_GET_C2H_FUNC(c2h) \
3203 	le32_get_bits(*((const __le32 *)c2h), GENMASK(15, 8))
3204 #define RTW89_GET_C2H_LEN(c2h) \
3205 	le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(13, 0))
3206 
3207 struct rtw89_fw_c2h_attr {
3208 	u8 category;
3209 	u8 class;
3210 	u8 func;
3211 	u16 len;
3212 };
3213 
3214 static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb)
3215 {
3216 	static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
3217 
3218 	return (struct rtw89_fw_c2h_attr *)skb->cb;
3219 }
3220 
3221 #define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2)
3222 #define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN)
3223 
3224 struct rtw89_c2h_done_ack {
3225 	__le32 w0;
3226 	__le32 w1;
3227 	__le32 w2;
3228 } __packed;
3229 
3230 #define RTW89_C2H_DONE_ACK_W2_CAT GENMASK(1, 0)
3231 #define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2)
3232 #define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8)
3233 #define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16)
3234 #define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24)
3235 
3236 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \
3237 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3238 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \
3239 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3240 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \
3241 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3242 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \
3243 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
3244 
3245 struct rtw89_c2h_mac_bcnfltr_rpt {
3246 	__le32 w0;
3247 	__le32 w1;
3248 	__le32 w2;
3249 } __packed;
3250 
3251 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0)
3252 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8)
3253 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10)
3254 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16)
3255 
3256 #define RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h) \
3257 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 0))
3258 #define RTW89_GET_PHY_C2H_RA_RPT_RETRY_RATIO(c2h) \
3259 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
3260 #define RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h) \
3261 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(6, 0))
3262 #define RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h) \
3263 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(9, 8))
3264 #define RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h) \
3265 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(12, 10))
3266 #define RTW89_GET_PHY_C2H_RA_RPT_BW(c2h) \
3267 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(14, 13))
3268 
3269 /* VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
3270  * HT-new: [6:5]: NA, [4:0]: MCS
3271  */
3272 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
3273 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
3274 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
3275 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
3276 				    FIELD_PREP(GENMASK(2, 0), mcs))
3277 
3278 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \
3279 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3280 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \
3281 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))
3282 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \
3283 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))
3284 
3285 #define RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h) \
3286 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3287 #define RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h) \
3288 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(19, 16))
3289 #define RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h) \
3290 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 20))
3291 #define RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h) \
3292 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24))
3293 #define RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h) \
3294 	le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(3, 0))
3295 #define RTW89_GET_MAC_C2H_SCANOFLD_AIR_DENSITY(c2h) \
3296 	le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(7, 4))
3297 #define RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h) \
3298 	le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(25, 24))
3299 
3300 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \
3301 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3302 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \
3303 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3304 
3305 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \
3306 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3307 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \
3308 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3309 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \
3310 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3311 
3312 struct rtw89_mac_mcc_tsf_rpt {
3313 	u32 macid_x;
3314 	u32 macid_y;
3315 	u32 tsf_x_low;
3316 	u32 tsf_x_high;
3317 	u32 tsf_y_low;
3318 	u32 tsf_y_high;
3319 };
3320 
3321 static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3322 
3323 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \
3324 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3325 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \
3326 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3327 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \
3328 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16))
3329 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \
3330 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3331 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \
3332 	le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3333 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \
3334 	le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0))
3335 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \
3336 	le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0))
3337 
3338 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \
3339 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0))
3340 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \
3341 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6))
3342 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \
3343 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3344 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \
3345 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3346 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \
3347 	le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3348 
3349 struct rtw89_c2h_pkt_ofld_rsp {
3350 	__le32 w0;
3351 	__le32 w1;
3352 	__le32 w2;
3353 } __packed;
3354 
3355 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0)
3356 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8)
3357 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16)
3358 
3359 struct rtw89_h2c_bcnfltr {
3360 	__le32 w0;
3361 } __packed;
3362 
3363 #define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0)
3364 #define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1)
3365 #define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2)
3366 #define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3)
3367 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT GENMASK(11, 8)
3368 #define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12)
3369 #define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16)
3370 #define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24)
3371 
3372 struct rtw89_h2c_ofld_rssi {
3373 	__le32 w0;
3374 	__le32 w1;
3375 } __packed;
3376 
3377 #define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0)
3378 #define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8)
3379 #define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0)
3380 
3381 struct rtw89_h2c_ofld {
3382 	__le32 w0;
3383 } __packed;
3384 
3385 #define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0)
3386 #define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8)
3387 #define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18)
3388 
3389 #define RTW89_FW_HDR_SIZE 32
3390 #define RTW89_FW_SECTION_HDR_SIZE 16
3391 
3392 #define RTW89_MFW_SIG	0xFF
3393 
3394 struct rtw89_mfw_info {
3395 	u8 cv;
3396 	u8 type; /* enum rtw89_fw_type */
3397 	u8 mp;
3398 	u8 rsvd;
3399 	__le32 shift;
3400 	__le32 size;
3401 	u8 rsvd2[4];
3402 } __packed;
3403 
3404 struct rtw89_mfw_hdr {
3405 	u8 sig;	/* RTW89_MFW_SIG */
3406 	u8 fw_nr;
3407 	u8 rsvd0[2];
3408 	struct {
3409 		u8 major;
3410 		u8 minor;
3411 		u8 sub;
3412 		u8 idx;
3413 	} ver;
3414 	u8 rsvd1[8];
3415 	struct rtw89_mfw_info info[];
3416 } __packed;
3417 
3418 struct fwcmd_hdr {
3419 	__le32 hdr0;
3420 	__le32 hdr1;
3421 };
3422 
3423 union rtw89_compat_fw_hdr {
3424 	struct rtw89_mfw_hdr mfw_hdr;
3425 	u8 fw_hdr[RTW89_FW_HDR_SIZE];
3426 };
3427 
3428 static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf)
3429 {
3430 	const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf;
3431 
3432 	if (compat->mfw_hdr.sig == RTW89_MFW_SIG)
3433 		return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr);
3434 	else
3435 		return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr);
3436 }
3437 
3438 static inline void rtw89_fw_get_filename(char *buf, size_t size,
3439 					 const char *fw_basename, int fw_format)
3440 {
3441 	if (fw_format <= 0)
3442 		snprintf(buf, size, "%s.bin", fw_basename);
3443 	else
3444 		snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format);
3445 }
3446 
3447 #define RTW89_H2C_RF_PAGE_SIZE 500
3448 #define RTW89_H2C_RF_PAGE_NUM 3
3449 struct rtw89_fw_h2c_rf_reg_info {
3450 	enum rtw89_rf_path rf_path;
3451 	__le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE];
3452 	u16 curr_idx;
3453 };
3454 
3455 #define H2C_SEC_CAM_LEN			24
3456 
3457 #define H2C_HEADER_LEN			8
3458 #define H2C_HDR_CAT			GENMASK(1, 0)
3459 #define H2C_HDR_CLASS			GENMASK(7, 2)
3460 #define H2C_HDR_FUNC			GENMASK(15, 8)
3461 #define H2C_HDR_DEL_TYPE		GENMASK(19, 16)
3462 #define H2C_HDR_H2C_SEQ			GENMASK(31, 24)
3463 #define H2C_HDR_TOTAL_LEN		GENMASK(13, 0)
3464 #define H2C_HDR_REC_ACK			BIT(14)
3465 #define H2C_HDR_DONE_ACK		BIT(15)
3466 
3467 #define FWCMD_TYPE_H2C			0
3468 
3469 #define H2C_CAT_TEST		0x0
3470 
3471 /* CLASS 5 - FW STATUS TEST */
3472 #define H2C_CL_FW_STATUS_TEST		0x5
3473 #define H2C_FUNC_CPU_EXCEPTION		0x1
3474 
3475 #define H2C_CAT_MAC		0x1
3476 
3477 /* CLASS 0 - FW INFO */
3478 #define H2C_CL_FW_INFO			0x0
3479 #define H2C_FUNC_LOG_CFG		0x0
3480 #define H2C_FUNC_MAC_GENERAL_PKT	0x1
3481 
3482 /* CLASS 1 - WOW */
3483 #define H2C_CL_MAC_WOW			0x1
3484 #define H2C_FUNC_KEEP_ALIVE		0x0
3485 #define H2C_FUNC_DISCONNECT_DETECT	0x1
3486 #define H2C_FUNC_WOW_GLOBAL		0x2
3487 #define H2C_FUNC_WAKEUP_CTRL		0x8
3488 #define H2C_FUNC_WOW_CAM_UPD		0xC
3489 
3490 /* CLASS 2 - PS */
3491 #define H2C_CL_MAC_PS			0x2
3492 #define H2C_FUNC_MAC_LPS_PARM		0x0
3493 #define H2C_FUNC_P2P_ACT		0x1
3494 
3495 /* CLASS 3 - FW download */
3496 #define H2C_CL_MAC_FWDL		0x3
3497 #define H2C_FUNC_MAC_FWHDR_DL		0x0
3498 
3499 /* CLASS 5 - Frame Exchange */
3500 #define H2C_CL_MAC_FR_EXCHG		0x5
3501 #define H2C_FUNC_MAC_CCTLINFO_UD	0x2
3502 #define H2C_FUNC_MAC_BCN_UPD		0x5
3503 #define H2C_FUNC_MAC_DCTLINFO_UD_V1	0x9
3504 #define H2C_FUNC_MAC_CCTLINFO_UD_V1	0xa
3505 
3506 /* CLASS 6 - Address CAM */
3507 #define H2C_CL_MAC_ADDR_CAM_UPDATE	0x6
3508 #define H2C_FUNC_MAC_ADDR_CAM_UPD	0x0
3509 
3510 /* CLASS 8 - Media Status Report */
3511 #define H2C_CL_MAC_MEDIA_RPT		0x8
3512 #define H2C_FUNC_MAC_JOININFO		0x0
3513 #define H2C_FUNC_MAC_FWROLE_MAINTAIN	0x4
3514 
3515 /* CLASS 9 - FW offload */
3516 #define H2C_CL_MAC_FW_OFLD		0x9
3517 enum rtw89_fw_ofld_h2c_func {
3518 	H2C_FUNC_PACKET_OFLD		= 0x1,
3519 	H2C_FUNC_MAC_MACID_PAUSE	= 0x8,
3520 	H2C_FUNC_USR_EDCA		= 0xF,
3521 	H2C_FUNC_TSF32_TOGL		= 0x10,
3522 	H2C_FUNC_OFLD_CFG		= 0x14,
3523 	H2C_FUNC_ADD_SCANOFLD_CH	= 0x16,
3524 	H2C_FUNC_SCANOFLD		= 0x17,
3525 	H2C_FUNC_PKT_DROP		= 0x1b,
3526 	H2C_FUNC_CFG_BCNFLTR		= 0x1e,
3527 	H2C_FUNC_OFLD_RSSI		= 0x1f,
3528 	H2C_FUNC_OFLD_TP		= 0x20,
3529 
3530 	NUM_OF_RTW89_FW_OFLD_H2C_FUNC,
3531 };
3532 
3533 #define RTW89_FW_OFLD_WAIT_COND(tag, func) \
3534 	((tag) * NUM_OF_RTW89_FW_OFLD_H2C_FUNC + (func))
3535 
3536 #define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \
3537 	RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \
3538 				H2C_FUNC_PACKET_OFLD)
3539 
3540 /* CLASS 10 - Security CAM */
3541 #define H2C_CL_MAC_SEC_CAM		0xa
3542 #define H2C_FUNC_MAC_SEC_UPD		0x1
3543 
3544 /* CLASS 12 - BA CAM */
3545 #define H2C_CL_BA_CAM			0xc
3546 #define H2C_FUNC_MAC_BA_CAM		0x0
3547 
3548 /* CLASS 14 - MCC */
3549 #define H2C_CL_MCC			0xe
3550 enum rtw89_mcc_h2c_func {
3551 	H2C_FUNC_ADD_MCC		= 0x0,
3552 	H2C_FUNC_START_MCC		= 0x1,
3553 	H2C_FUNC_STOP_MCC		= 0x2,
3554 	H2C_FUNC_DEL_MCC_GROUP		= 0x3,
3555 	H2C_FUNC_RESET_MCC_GROUP	= 0x4,
3556 	H2C_FUNC_MCC_REQ_TSF		= 0x5,
3557 	H2C_FUNC_MCC_MACID_BITMAP	= 0x6,
3558 	H2C_FUNC_MCC_SYNC		= 0x7,
3559 	H2C_FUNC_MCC_SET_DURATION	= 0x8,
3560 
3561 	NUM_OF_RTW89_MCC_H2C_FUNC,
3562 };
3563 
3564 #define RTW89_MCC_WAIT_COND(group, func) \
3565 	((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func))
3566 
3567 #define H2C_CAT_OUTSRC			0x2
3568 
3569 #define H2C_CL_OUTSRC_RA		0x1
3570 #define H2C_FUNC_OUTSRC_RA_MACIDCFG	0x0
3571 
3572 #define H2C_CL_OUTSRC_RF_REG_A		0x8
3573 #define H2C_CL_OUTSRC_RF_REG_B		0x9
3574 #define H2C_CL_OUTSRC_RF_FW_NOTIFY	0xa
3575 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH	0x2
3576 
3577 struct rtw89_fw_h2c_rf_get_mccch {
3578 	__le32 ch_0;
3579 	__le32 ch_1;
3580 	__le32 band_0;
3581 	__le32 band_1;
3582 	__le32 current_channel;
3583 	__le32 current_band_type;
3584 } __packed;
3585 
3586 #define RTW89_FW_RSVD_PLE_SIZE 0x800
3587 
3588 #define RTW89_WCPU_BASE_MASK GENMASK(27, 0)
3589 
3590 #define RTW89_FW_BACKTRACE_INFO_SIZE 8
3591 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \
3592 	((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0)
3593 
3594 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */
3595 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE
3596 
3597 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev);
3598 int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
3599 const struct firmware *
3600 rtw89_early_fw_feature_recognize(struct device *device,
3601 				 const struct rtw89_chip_info *chip,
3602 				 struct rtw89_fw_info *early_fw,
3603 				 int *used_fw_format);
3604 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type);
3605 void rtw89_load_firmware_work(struct work_struct *work);
3606 void rtw89_unload_firmware(struct rtw89_dev *rtwdev);
3607 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev);
3608 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb,
3609 			   u8 type, u8 cat, u8 class, u8 func,
3610 			   bool rack, bool dack, u32 len);
3611 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
3612 				  struct rtw89_vif *rtwvif);
3613 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
3614 				struct ieee80211_vif *vif,
3615 				struct ieee80211_sta *sta);
3616 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
3617 				 struct rtw89_sta *rtwsta);
3618 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev,
3619 				 struct rtw89_sta *rtwsta);
3620 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev,
3621 			       struct rtw89_vif *rtwvif);
3622 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif,
3623 		     struct rtw89_sta *rtwsta, const u8 *scan_mac_addr);
3624 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev,
3625 				 struct rtw89_vif *rtwvif,
3626 				 struct rtw89_sta *rtwsta);
3627 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h);
3628 void rtw89_fw_c2h_work(struct work_struct *work);
3629 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev,
3630 			       struct rtw89_vif *rtwvif,
3631 			       struct rtw89_sta *rtwsta,
3632 			       enum rtw89_upd_mode upd_mode);
3633 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3634 			   struct rtw89_sta *rtwsta, bool dis_conn);
3635 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp,
3636 			     bool pause);
3637 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3638 			  u8 ac, u32 val);
3639 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev);
3640 int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev,
3641 				  struct ieee80211_vif *vif,
3642 				  bool connect);
3643 int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev,
3644 			      struct rtw89_rx_phy_ppdu *phy_ppdu);
3645 int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
3646 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi);
3647 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev);
3648 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev);
3649 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev);
3650 int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev);
3651 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev);
3652 int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev);
3653 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev);
3654 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id);
3655 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
3656 				 struct sk_buff *skb_ofld);
3657 int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int len,
3658 				   struct list_head *chan_list);
3659 int rtw89_fw_h2c_scan_offload(struct rtw89_dev *rtwdev,
3660 			      struct rtw89_scan_option *opt,
3661 			      struct rtw89_vif *vif);
3662 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
3663 			struct rtw89_fw_h2c_rf_reg_info *info,
3664 			u16 len, u8 page);
3665 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev);
3666 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
3667 			      u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
3668 			      bool rack, bool dack);
3669 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len);
3670 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev);
3671 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
3672 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3673 			     u8 macid);
3674 void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev,
3675 					   struct rtw89_vif *rtwvif, bool notify_fw);
3676 void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw);
3677 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
3678 			bool valid, struct ieee80211_ampdu_params *params);
3679 void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev);
3680 
3681 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,
3682 			  struct rtw89_lps_parm *lps_param);
3683 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len);
3684 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len);
3685 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev,
3686 		     struct rtw89_mac_h2c_info *h2c_info,
3687 		     struct rtw89_mac_c2h_info *c2h_info);
3688 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable);
3689 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev);
3690 void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3691 			 struct ieee80211_scan_request *req);
3692 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3693 			    bool aborted);
3694 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3695 			  bool enable);
3696 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
3697 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev);
3698 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev,
3699 			  const struct rtw89_pkt_drop_params *params);
3700 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3701 			 struct ieee80211_p2p_noa_desc *desc,
3702 			 u8 act, u8 noa_id);
3703 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3704 			      bool en);
3705 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3706 			    bool enable);
3707 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
3708 				 struct rtw89_vif *rtwvif, bool enable);
3709 int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3710 			    bool enable);
3711 int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
3712 				   struct rtw89_vif *rtwvif, bool enable);
3713 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3714 			    bool enable);
3715 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
3716 				 struct rtw89_vif *rtwvif, bool enable);
3717 int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
3718 			    struct rtw89_wow_cam_info *cam_info);
3719 int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
3720 			 const struct rtw89_fw_mcc_add_req *p);
3721 int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
3722 			   const struct rtw89_fw_mcc_start_req *p);
3723 int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
3724 			  bool prev_groups);
3725 int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
3726 			       bool prev_groups);
3727 int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group);
3728 int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
3729 			     const struct rtw89_fw_mcc_tsf_req *req,
3730 			     struct rtw89_mac_mcc_tsf_rpt *rpt);
3731 int rtw89_fw_h2c_mcc_macid_bitamp(struct rtw89_dev *rtwdev, u8 group, u8 macid,
3732 				  u8 *bitmap);
3733 int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
3734 			  u8 target, u8 offset);
3735 int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
3736 				  const struct rtw89_fw_mcc_duration *p);
3737 
3738 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
3739 {
3740 	const struct rtw89_chip_info *chip = rtwdev->chip;
3741 
3742 	if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
3743 		rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev);
3744 }
3745 
3746 #endif
3747