1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_FW_H__ 6 #define __RTW89_FW_H__ 7 8 #include "core.h" 9 10 enum rtw89_fw_dl_status { 11 RTW89_FWDL_INITIAL_STATE = 0, 12 RTW89_FWDL_FWDL_ONGOING = 1, 13 RTW89_FWDL_CHECKSUM_FAIL = 2, 14 RTW89_FWDL_SECURITY_FAIL = 3, 15 RTW89_FWDL_CV_NOT_MATCH = 4, 16 RTW89_FWDL_RSVD0 = 5, 17 RTW89_FWDL_WCPU_FWDL_RDY = 6, 18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7 19 }; 20 21 #define RTW89_GET_C2H_HDR_FUNC(info) \ 22 u32_get_bits(info, GENMASK(6, 0)) 23 #define RTW89_GET_C2H_HDR_LEN(info) \ 24 u32_get_bits(info, GENMASK(11, 8)) 25 26 #define RTW89_SET_H2CREG_HDR_FUNC(info, val) \ 27 u32p_replace_bits(info, val, GENMASK(6, 0)) 28 #define RTW89_SET_H2CREG_HDR_LEN(info, val) \ 29 u32p_replace_bits(info, val, GENMASK(11, 8)) 30 31 #define RTW89_H2CREG_MAX 4 32 #define RTW89_C2HREG_MAX 4 33 #define RTW89_C2HREG_HDR_LEN 2 34 #define RTW89_H2CREG_HDR_LEN 2 35 #define RTW89_C2H_TIMEOUT 1000000 36 struct rtw89_mac_c2h_info { 37 u8 id; 38 u8 content_len; 39 u32 c2hreg[RTW89_C2HREG_MAX]; 40 }; 41 42 struct rtw89_mac_h2c_info { 43 u8 id; 44 u8 content_len; 45 u32 h2creg[RTW89_H2CREG_MAX]; 46 }; 47 48 enum rtw89_mac_h2c_type { 49 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0, 50 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD, 51 RTW89_FWCMD_H2CREG_FUNC_FWERR, 52 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE, 53 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM, 54 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN 55 }; 56 57 enum rtw89_mac_c2h_type { 58 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0, 59 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT, 60 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG, 61 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP, 62 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT, 63 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF 64 }; 65 66 struct rtw89_c2h_phy_cap { 67 u32 func:7; 68 u32 ack:1; 69 u32 len:4; 70 u32 seq:4; 71 u32 rx_nss:8; 72 u32 bw:8; 73 74 u32 tx_nss:8; 75 u32 prot:8; 76 u32 nic:8; 77 u32 wl_func:8; 78 79 u32 hw_type:8; 80 } __packed; 81 82 enum rtw89_fw_c2h_category { 83 RTW89_C2H_CAT_TEST, 84 RTW89_C2H_CAT_MAC, 85 RTW89_C2H_CAT_OUTSRC, 86 }; 87 88 enum rtw89_fw_log_level { 89 RTW89_FW_LOG_LEVEL_OFF, 90 RTW89_FW_LOG_LEVEL_CRT, 91 RTW89_FW_LOG_LEVEL_SER, 92 RTW89_FW_LOG_LEVEL_WARN, 93 RTW89_FW_LOG_LEVEL_LOUD, 94 RTW89_FW_LOG_LEVEL_TR, 95 }; 96 97 enum rtw89_fw_log_path { 98 RTW89_FW_LOG_LEVEL_UART, 99 RTW89_FW_LOG_LEVEL_C2H, 100 RTW89_FW_LOG_LEVEL_SNI, 101 }; 102 103 enum rtw89_fw_log_comp { 104 RTW89_FW_LOG_COMP_VER, 105 RTW89_FW_LOG_COMP_INIT, 106 RTW89_FW_LOG_COMP_TASK, 107 RTW89_FW_LOG_COMP_CNS, 108 RTW89_FW_LOG_COMP_H2C, 109 RTW89_FW_LOG_COMP_C2H, 110 RTW89_FW_LOG_COMP_TX, 111 RTW89_FW_LOG_COMP_RX, 112 RTW89_FW_LOG_COMP_IPSEC, 113 RTW89_FW_LOG_COMP_TIMER, 114 RTW89_FW_LOG_COMP_DBGPKT, 115 RTW89_FW_LOG_COMP_PS, 116 RTW89_FW_LOG_COMP_ERROR, 117 RTW89_FW_LOG_COMP_WOWLAN, 118 RTW89_FW_LOG_COMP_SECURE_BOOT, 119 RTW89_FW_LOG_COMP_BTC, 120 RTW89_FW_LOG_COMP_BB, 121 RTW89_FW_LOG_COMP_TWT, 122 RTW89_FW_LOG_COMP_RF, 123 RTW89_FW_LOG_COMP_MCC = 20, 124 }; 125 126 #define FWDL_SECTION_MAX_NUM 10 127 #define FWDL_SECTION_CHKSUM_LEN 8 128 #define FWDL_SECTION_PER_PKT_LEN 2020 129 130 struct rtw89_fw_hdr_section_info { 131 u8 redl; 132 const u8 *addr; 133 u32 len; 134 u32 dladdr; 135 }; 136 137 struct rtw89_fw_bin_info { 138 u8 section_num; 139 u32 hdr_len; 140 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM]; 141 }; 142 143 struct rtw89_fw_macid_pause_grp { 144 __le32 pause_grp[4]; 145 __le32 mask_grp[4]; 146 } __packed; 147 148 struct rtw89_h2creg_sch_tx_en { 149 u8 func:7; 150 u8 ack:1; 151 u8 total_len:4; 152 u8 seq_num:4; 153 u16 tx_en:16; 154 u16 mask:16; 155 u8 band:1; 156 u16 rsvd:15; 157 } __packed; 158 159 #define RTW89_SET_FWCMD_RA_IS_DIS(cmd, val) \ 160 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(0)) 161 #define RTW89_SET_FWCMD_RA_MODE(cmd, val) \ 162 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(5, 1)) 163 #define RTW89_SET_FWCMD_RA_BW_CAP(cmd, val) \ 164 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 6)) 165 #define RTW89_SET_FWCMD_RA_MACID(cmd, val) \ 166 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)) 167 #define RTW89_SET_FWCMD_RA_DCM(cmd, val) \ 168 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(16)) 169 #define RTW89_SET_FWCMD_RA_ER(cmd, val) \ 170 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(17)) 171 #define RTW89_SET_FWCMD_RA_INIT_RATE_LV(cmd, val) \ 172 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(19, 18)) 173 #define RTW89_SET_FWCMD_RA_UPD_ALL(cmd, val) \ 174 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(20)) 175 #define RTW89_SET_FWCMD_RA_SGI(cmd, val) \ 176 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(21)) 177 #define RTW89_SET_FWCMD_RA_LDPC(cmd, val) \ 178 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(22)) 179 #define RTW89_SET_FWCMD_RA_STBC(cmd, val) \ 180 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(23)) 181 #define RTW89_SET_FWCMD_RA_SS_NUM(cmd, val) \ 182 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(26, 24)) 183 #define RTW89_SET_FWCMD_RA_GILTF(cmd, val) \ 184 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(29, 27)) 185 #define RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(cmd, val) \ 186 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(30)) 187 #define RTW89_SET_FWCMD_RA_UPD_MASK(cmd, val) \ 188 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(31)) 189 #define RTW89_SET_FWCMD_RA_MASK_0(cmd, val) \ 190 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(7, 0)) 191 #define RTW89_SET_FWCMD_RA_MASK_1(cmd, val) \ 192 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(15, 8)) 193 #define RTW89_SET_FWCMD_RA_MASK_2(cmd, val) \ 194 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(23, 16)) 195 #define RTW89_SET_FWCMD_RA_MASK_3(cmd, val) \ 196 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 24)) 197 #define RTW89_SET_FWCMD_RA_MASK_4(cmd, val) \ 198 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(7, 0)) 199 #define RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(cmd, val) \ 200 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, BIT(31)) 201 #define RTW89_SET_FWCMD_RA_BAND_NUM(cmd, val) \ 202 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(7, 0)) 203 #define RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(cmd, val) \ 204 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(8)) 205 #define RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(cmd, val) \ 206 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(9)) 207 #define RTW89_SET_FWCMD_RA_CR_TBL_SEL(cmd, val) \ 208 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(10)) 209 #define RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(cmd, val) \ 210 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(23, 16)) 211 #define RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(cmd, val) \ 212 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(25, 24)) 213 #define RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(cmd, val) \ 214 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(28, 26)) 215 #define RTW89_SET_FWCMD_RA_FIXED_CSI_BW(cmd, val) \ 216 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 29)) 217 218 #define RTW89_SET_FWCMD_SEC_IDX(cmd, val) \ 219 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)) 220 #define RTW89_SET_FWCMD_SEC_OFFSET(cmd, val) \ 221 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)) 222 #define RTW89_SET_FWCMD_SEC_LEN(cmd, val) \ 223 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)) 224 #define RTW89_SET_FWCMD_SEC_TYPE(cmd, val) \ 225 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0)) 226 #define RTW89_SET_FWCMD_SEC_EXT_KEY(cmd, val) \ 227 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4)) 228 #define RTW89_SET_FWCMD_SEC_SPP_MODE(cmd, val) \ 229 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5)) 230 #define RTW89_SET_FWCMD_SEC_KEY0(cmd, val) \ 231 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0)) 232 #define RTW89_SET_FWCMD_SEC_KEY1(cmd, val) \ 233 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0)) 234 #define RTW89_SET_FWCMD_SEC_KEY2(cmd, val) \ 235 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0)) 236 #define RTW89_SET_FWCMD_SEC_KEY3(cmd, val) \ 237 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0)) 238 239 #define RTW89_SET_EDCA_SEL(cmd, val) \ 240 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0)) 241 #define RTW89_SET_EDCA_BAND(cmd, val) \ 242 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3)) 243 #define RTW89_SET_EDCA_WMM(cmd, val) \ 244 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4)) 245 #define RTW89_SET_EDCA_AC(cmd, val) \ 246 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5)) 247 #define RTW89_SET_EDCA_PARAM(cmd, val) \ 248 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0)) 249 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16) 250 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12) 251 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8) 252 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0) 253 254 #define GET_FWSECTION_HDR_SEC_SIZE(fwhdr) \ 255 le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(23, 0)) 256 #define GET_FWSECTION_HDR_CHECKSUM(fwhdr) \ 257 le32_get_bits(*((__le32 *)(fwhdr) + 1), BIT(28)) 258 #define GET_FWSECTION_HDR_REDL(fwhdr) \ 259 le32_get_bits(*((__le32 *)(fwhdr) + 1), BIT(29)) 260 #define GET_FWSECTION_HDR_DL_ADDR(fwhdr) \ 261 le32_get_bits(*((__le32 *)(fwhdr)), GENMASK(31, 0)) 262 263 #define GET_FW_HDR_MAJOR_VERSION(fwhdr) \ 264 le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(7, 0)) 265 #define GET_FW_HDR_MINOR_VERSION(fwhdr) \ 266 le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(15, 8)) 267 #define GET_FW_HDR_SUBVERSION(fwhdr) \ 268 le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(23, 16)) 269 #define GET_FW_HDR_SUBINDEX(fwhdr) \ 270 le32_get_bits(*((__le32 *)(fwhdr) + 1), GENMASK(31, 24)) 271 #define GET_FW_HDR_MONTH(fwhdr) \ 272 le32_get_bits(*((__le32 *)(fwhdr) + 4), GENMASK(7, 0)) 273 #define GET_FW_HDR_DATE(fwhdr) \ 274 le32_get_bits(*((__le32 *)(fwhdr) + 4), GENMASK(15, 8)) 275 #define GET_FW_HDR_HOUR(fwhdr) \ 276 le32_get_bits(*((__le32 *)(fwhdr) + 4), GENMASK(23, 16)) 277 #define GET_FW_HDR_MIN(fwhdr) \ 278 le32_get_bits(*((__le32 *)(fwhdr) + 4), GENMASK(31, 24)) 279 #define GET_FW_HDR_YEAR(fwhdr) \ 280 le32_get_bits(*((__le32 *)(fwhdr) + 5), GENMASK(31, 0)) 281 #define GET_FW_HDR_SEC_NUM(fwhdr) \ 282 le32_get_bits(*((__le32 *)(fwhdr) + 6), GENMASK(15, 8)) 283 #define GET_FW_HDR_CMD_VERSERION(fwhdr) \ 284 le32_get_bits(*((__le32 *)(fwhdr) + 7), GENMASK(31, 24)) 285 static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val) 286 { 287 le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0)); 288 } 289 290 #define SET_CTRL_INFO_MACID(table, val) \ 291 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)) 292 #define SET_CTRL_INFO_OPERATION(table, val) \ 293 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)) 294 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0) 295 #define SET_CMC_TBL_DATARATE(table, val) \ 296 do { \ 297 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0)); \ 298 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE, \ 299 GENMASK(8, 0)); \ 300 } while (0) 301 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0) 302 #define SET_CMC_TBL_FORCE_TXOP(table, val) \ 303 do { \ 304 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9)); \ 305 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP, \ 306 BIT(9)); \ 307 } while (0) 308 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0) 309 #define SET_CMC_TBL_DATA_BW(table, val) \ 310 do { \ 311 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10)); \ 312 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW, \ 313 GENMASK(11, 10)); \ 314 } while (0) 315 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0) 316 #define SET_CMC_TBL_DATA_GI_LTF(table, val) \ 317 do { \ 318 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12)); \ 319 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF, \ 320 GENMASK(14, 12)); \ 321 } while (0) 322 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0) 323 #define SET_CMC_TBL_DARF_TC_INDEX(table, val) \ 324 do { \ 325 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); \ 326 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX, \ 327 BIT(15)); \ 328 } while (0) 329 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0) 330 #define SET_CMC_TBL_ARFR_CTRL(table, val) \ 331 do { \ 332 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16)); \ 333 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL, \ 334 GENMASK(19, 16)); \ 335 } while (0) 336 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0) 337 #define SET_CMC_TBL_ACQ_RPT_EN(table, val) \ 338 do { \ 339 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20)); \ 340 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN, \ 341 BIT(20)); \ 342 } while (0) 343 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0) 344 #define SET_CMC_TBL_MGQ_RPT_EN(table, val) \ 345 do { \ 346 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21)); \ 347 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN, \ 348 BIT(21)); \ 349 } while (0) 350 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0) 351 #define SET_CMC_TBL_ULQ_RPT_EN(table, val) \ 352 do { \ 353 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22)); \ 354 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN, \ 355 BIT(22)); \ 356 } while (0) 357 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0) 358 #define SET_CMC_TBL_TWTQ_RPT_EN(table, val) \ 359 do { \ 360 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23)); \ 361 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN, \ 362 BIT(23)); \ 363 } while (0) 364 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0) 365 #define SET_CMC_TBL_DISRTSFB(table, val) \ 366 do { \ 367 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25)); \ 368 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB, \ 369 BIT(25)); \ 370 } while (0) 371 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0) 372 #define SET_CMC_TBL_DISDATAFB(table, val) \ 373 do { \ 374 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26)); \ 375 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB, \ 376 BIT(26)); \ 377 } while (0) 378 #define SET_CMC_TBL_MASK_TRYRATE BIT(0) 379 #define SET_CMC_TBL_TRYRATE(table, val) \ 380 do { \ 381 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27)); \ 382 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE, \ 383 BIT(27)); \ 384 } while (0) 385 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0) 386 #define SET_CMC_TBL_AMPDU_DENSITY(table, val) \ 387 do { \ 388 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28)); \ 389 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY, \ 390 GENMASK(31, 28)); \ 391 } while (0) 392 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0) 393 #define SET_CMC_TBL_DATA_RTY_LOWEST_RATE(table, val) \ 394 do { \ 395 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0)); \ 396 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE, \ 397 GENMASK(8, 0)); \ 398 } while (0) 399 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0) 400 #define SET_CMC_TBL_AMPDU_TIME_SEL(table, val) \ 401 do { \ 402 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9)); \ 403 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL, \ 404 BIT(9)); \ 405 } while (0) 406 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0) 407 #define SET_CMC_TBL_AMPDU_LEN_SEL(table, val) \ 408 do { \ 409 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10)); \ 410 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL, \ 411 BIT(10)); \ 412 } while (0) 413 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0) 414 #define SET_CMC_TBL_RTS_TXCNT_LMT_SEL(table, val) \ 415 do { \ 416 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11)); \ 417 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL, \ 418 BIT(11)); \ 419 } while (0) 420 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0) 421 #define SET_CMC_TBL_RTS_TXCNT_LMT(table, val) \ 422 do { \ 423 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12)); \ 424 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT, \ 425 GENMASK(15, 12)); \ 426 } while (0) 427 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0) 428 #define SET_CMC_TBL_RTSRATE(table, val) \ 429 do { \ 430 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16)); \ 431 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE, \ 432 GENMASK(24, 16)); \ 433 } while (0) 434 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0) 435 #define SET_CMC_TBL_VCS_STBC(table, val) \ 436 do { \ 437 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27)); \ 438 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC, \ 439 BIT(27)); \ 440 } while (0) 441 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0) 442 #define SET_CMC_TBL_RTS_RTY_LOWEST_RATE(table, val) \ 443 do { \ 444 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28)); \ 445 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE, \ 446 GENMASK(31, 28)); \ 447 } while (0) 448 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0) 449 #define SET_CMC_TBL_DATA_TX_CNT_LMT(table, val) \ 450 do { \ 451 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0)); \ 452 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT, \ 453 GENMASK(5, 0)); \ 454 } while (0) 455 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0) 456 #define SET_CMC_TBL_DATA_TXCNT_LMT_SEL(table, val) \ 457 do { \ 458 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6)); \ 459 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL, \ 460 BIT(6)); \ 461 } while (0) 462 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0) 463 #define SET_CMC_TBL_MAX_AGG_NUM_SEL(table, val) \ 464 do { \ 465 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7)); \ 466 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL, \ 467 BIT(7)); \ 468 } while (0) 469 #define SET_CMC_TBL_MASK_RTS_EN BIT(0) 470 #define SET_CMC_TBL_RTS_EN(table, val) \ 471 do { \ 472 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8)); \ 473 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN, \ 474 BIT(8)); \ 475 } while (0) 476 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0) 477 #define SET_CMC_TBL_CTS2SELF_EN(table, val) \ 478 do { \ 479 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9)); \ 480 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN, \ 481 BIT(9)); \ 482 } while (0) 483 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0) 484 #define SET_CMC_TBL_CCA_RTS(table, val) \ 485 do { \ 486 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10)); \ 487 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS, \ 488 GENMASK(11, 10)); \ 489 } while (0) 490 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0) 491 #define SET_CMC_TBL_HW_RTS_EN(table, val) \ 492 do { \ 493 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12)); \ 494 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN, \ 495 BIT(12)); \ 496 } while (0) 497 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0) 498 #define SET_CMC_TBL_RTS_DROP_DATA_MODE(table, val) \ 499 do { \ 500 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13)); \ 501 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE, \ 502 GENMASK(14, 13)); \ 503 } while (0) 504 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0) 505 #define SET_CMC_TBL_AMPDU_MAX_LEN(table, val) \ 506 do { \ 507 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16)); \ 508 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN, \ 509 GENMASK(26, 16)); \ 510 } while (0) 511 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0) 512 #define SET_CMC_TBL_UL_MU_DIS(table, val) \ 513 do { \ 514 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); \ 515 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS, \ 516 BIT(27)); \ 517 } while (0) 518 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0) 519 #define SET_CMC_TBL_AMPDU_MAX_TIME(table, val) \ 520 do { \ 521 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28)); \ 522 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME, \ 523 GENMASK(31, 28)); \ 524 } while (0) 525 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0) 526 #define SET_CMC_TBL_MAX_AGG_NUM(table, val) \ 527 do { \ 528 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0)); \ 529 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM, \ 530 GENMASK(7, 0)); \ 531 } while (0) 532 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0) 533 #define SET_CMC_TBL_BA_BMAP(table, val) \ 534 do { \ 535 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8)); \ 536 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP, \ 537 GENMASK(9, 8)); \ 538 } while (0) 539 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0) 540 #define SET_CMC_TBL_VO_LFTIME_SEL(table, val) \ 541 do { \ 542 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16)); \ 543 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL, \ 544 GENMASK(18, 16)); \ 545 } while (0) 546 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0) 547 #define SET_CMC_TBL_VI_LFTIME_SEL(table, val) \ 548 do { \ 549 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19)); \ 550 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL, \ 551 GENMASK(21, 19)); \ 552 } while (0) 553 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0) 554 #define SET_CMC_TBL_BE_LFTIME_SEL(table, val) \ 555 do { \ 556 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22)); \ 557 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL, \ 558 GENMASK(24, 22)); \ 559 } while (0) 560 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0) 561 #define SET_CMC_TBL_BK_LFTIME_SEL(table, val) \ 562 do { \ 563 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25)); \ 564 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL, \ 565 GENMASK(27, 25)); \ 566 } while (0) 567 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0) 568 #define SET_CMC_TBL_SECTYPE(table, val) \ 569 do { \ 570 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28)); \ 571 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE, \ 572 GENMASK(31, 28)); \ 573 } while (0) 574 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0) 575 #define SET_CMC_TBL_MULTI_PORT_ID(table, val) \ 576 do { \ 577 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0)); \ 578 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID, \ 579 GENMASK(2, 0)); \ 580 } while (0) 581 #define SET_CMC_TBL_MASK_BMC BIT(0) 582 #define SET_CMC_TBL_BMC(table, val) \ 583 do { \ 584 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3)); \ 585 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC, \ 586 BIT(3)); \ 587 } while (0) 588 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0) 589 #define SET_CMC_TBL_MBSSID(table, val) \ 590 do { \ 591 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4)); \ 592 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID, \ 593 GENMASK(7, 4)); \ 594 } while (0) 595 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0) 596 #define SET_CMC_TBL_NAVUSEHDR(table, val) \ 597 do { \ 598 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); \ 599 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR, \ 600 BIT(8)); \ 601 } while (0) 602 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0) 603 #define SET_CMC_TBL_TXPWR_MODE(table, val) \ 604 do { \ 605 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9)); \ 606 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE, \ 607 GENMASK(11, 9)); \ 608 } while (0) 609 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0) 610 #define SET_CMC_TBL_DATA_DCM(table, val) \ 611 do { \ 612 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12)); \ 613 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM, \ 614 BIT(12)); \ 615 } while (0) 616 #define SET_CMC_TBL_MASK_DATA_ER BIT(0) 617 #define SET_CMC_TBL_DATA_ER(table, val) \ 618 do { \ 619 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13)); \ 620 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER, \ 621 BIT(13)); \ 622 } while (0) 623 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0) 624 #define SET_CMC_TBL_DATA_LDPC(table, val) \ 625 do { \ 626 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14)); \ 627 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC, \ 628 BIT(14)); \ 629 } while (0) 630 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0) 631 #define SET_CMC_TBL_DATA_STBC(table, val) \ 632 do { \ 633 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); \ 634 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC, \ 635 BIT(15)); \ 636 } while (0) 637 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0) 638 #define SET_CMC_TBL_A_CTRL_BQR(table, val) \ 639 do { \ 640 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16)); \ 641 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR, \ 642 BIT(16)); \ 643 } while (0) 644 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0) 645 #define SET_CMC_TBL_A_CTRL_UPH(table, val) \ 646 do { \ 647 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17)); \ 648 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH, \ 649 BIT(17)); \ 650 } while (0) 651 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0) 652 #define SET_CMC_TBL_A_CTRL_BSR(table, val) \ 653 do { \ 654 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18)); \ 655 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR, \ 656 BIT(18)); \ 657 } while (0) 658 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0) 659 #define SET_CMC_TBL_A_CTRL_CAS(table, val) \ 660 do { \ 661 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19)); \ 662 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS, \ 663 BIT(19)); \ 664 } while (0) 665 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0) 666 #define SET_CMC_TBL_DATA_BW_ER(table, val) \ 667 do { \ 668 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20)); \ 669 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER, \ 670 BIT(20)); \ 671 } while (0) 672 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0) 673 #define SET_CMC_TBL_LSIG_TXOP_EN(table, val) \ 674 do { \ 675 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21)); \ 676 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN, \ 677 BIT(21)); \ 678 } while (0) 679 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0) 680 #define SET_CMC_TBL_CTRL_CNT_VLD(table, val) \ 681 do { \ 682 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27)); \ 683 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD, \ 684 BIT(27)); \ 685 } while (0) 686 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0) 687 #define SET_CMC_TBL_CTRL_CNT(table, val) \ 688 do { \ 689 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28)); \ 690 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT, \ 691 GENMASK(31, 28)); \ 692 } while (0) 693 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0) 694 #define SET_CMC_TBL_RESP_REF_RATE(table, val) \ 695 do { \ 696 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0)); \ 697 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE, \ 698 GENMASK(8, 0)); \ 699 } while (0) 700 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0) 701 #define SET_CMC_TBL_ALL_ACK_SUPPORT(table, val) \ 702 do { \ 703 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12)); \ 704 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT, \ 705 BIT(12)); \ 706 } while (0) 707 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0) 708 #define SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(table, val) \ 709 do { \ 710 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13)); \ 711 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT, \ 712 BIT(13)); \ 713 } while (0) 714 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0) 715 #define SET_CMC_TBL_NTX_PATH_EN(table, val) \ 716 do { \ 717 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16)); \ 718 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN, \ 719 GENMASK(19, 16)); \ 720 } while (0) 721 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0) 722 #define SET_CMC_TBL_PATH_MAP_A(table, val) \ 723 do { \ 724 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20)); \ 725 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A, \ 726 GENMASK(21, 20)); \ 727 } while (0) 728 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0) 729 #define SET_CMC_TBL_PATH_MAP_B(table, val) \ 730 do { \ 731 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22)); \ 732 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B, \ 733 GENMASK(23, 22)); \ 734 } while (0) 735 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0) 736 #define SET_CMC_TBL_PATH_MAP_C(table, val) \ 737 do { \ 738 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24)); \ 739 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C, \ 740 GENMASK(25, 24)); \ 741 } while (0) 742 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0) 743 #define SET_CMC_TBL_PATH_MAP_D(table, val) \ 744 do { \ 745 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26)); \ 746 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D, \ 747 GENMASK(27, 26)); \ 748 } while (0) 749 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0) 750 #define SET_CMC_TBL_ANTSEL_A(table, val) \ 751 do { \ 752 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28)); \ 753 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A, \ 754 BIT(28)); \ 755 } while (0) 756 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0) 757 #define SET_CMC_TBL_ANTSEL_B(table, val) \ 758 do { \ 759 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29)); \ 760 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B, \ 761 BIT(29)); \ 762 } while (0) 763 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0) 764 #define SET_CMC_TBL_ANTSEL_C(table, val) \ 765 do { \ 766 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30)); \ 767 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C, \ 768 BIT(30)); \ 769 } while (0) 770 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0) 771 #define SET_CMC_TBL_ANTSEL_D(table, val) \ 772 do { \ 773 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31)); \ 774 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D, \ 775 BIT(31)); \ 776 } while (0) 777 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0) 778 #define SET_CMC_TBL_ADDR_CAM_INDEX(table, val) \ 779 do { \ 780 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); \ 781 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX, \ 782 GENMASK(7, 0)); \ 783 } while (0) 784 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0) 785 #define SET_CMC_TBL_PAID(table, val) \ 786 do { \ 787 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8)); \ 788 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID, \ 789 GENMASK(16, 8)); \ 790 } while (0) 791 #define SET_CMC_TBL_MASK_ULDL BIT(0) 792 #define SET_CMC_TBL_ULDL(table, val) \ 793 do { \ 794 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17)); \ 795 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL, \ 796 BIT(17)); \ 797 } while (0) 798 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0) 799 #define SET_CMC_TBL_DOPPLER_CTRL(table, val) \ 800 do { \ 801 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18)); \ 802 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL, \ 803 GENMASK(19, 18)); \ 804 } while (0) 805 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0) 806 #define SET_CMC_TBL_NOMINAL_PKT_PADDING(table, val) \ 807 do { \ 808 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20)); \ 809 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, \ 810 GENMASK(21, 20)); \ 811 } while (0) 812 #define SET_CMC_TBL_NOMINAL_PKT_PADDING40(table, val) \ 813 do { \ 814 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22)); \ 815 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, \ 816 GENMASK(23, 22)); \ 817 } while (0) 818 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0) 819 #define SET_CMC_TBL_TXPWR_TOLERENCE(table, val) \ 820 do { \ 821 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24)); \ 822 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE, \ 823 GENMASK(27, 24)); \ 824 } while (0) 825 #define SET_CMC_TBL_NOMINAL_PKT_PADDING80(table, val) \ 826 do { \ 827 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30)); \ 828 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, \ 829 GENMASK(31, 30)); \ 830 } while (0) 831 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0) 832 #define SET_CMC_TBL_NC(table, val) \ 833 do { \ 834 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0)); \ 835 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC, \ 836 GENMASK(2, 0)); \ 837 } while (0) 838 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0) 839 #define SET_CMC_TBL_NR(table, val) \ 840 do { \ 841 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3)); \ 842 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR, \ 843 GENMASK(5, 3)); \ 844 } while (0) 845 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0) 846 #define SET_CMC_TBL_NG(table, val) \ 847 do { \ 848 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6)); \ 849 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG, \ 850 GENMASK(7, 6)); \ 851 } while (0) 852 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0) 853 #define SET_CMC_TBL_CB(table, val) \ 854 do { \ 855 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8)); \ 856 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB, \ 857 GENMASK(9, 8)); \ 858 } while (0) 859 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0) 860 #define SET_CMC_TBL_CS(table, val) \ 861 do { \ 862 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10)); \ 863 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS, \ 864 GENMASK(11, 10)); \ 865 } while (0) 866 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0) 867 #define SET_CMC_TBL_CSI_TXBF_EN(table, val) \ 868 do { \ 869 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12)); \ 870 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN, \ 871 BIT(12)); \ 872 } while (0) 873 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0) 874 #define SET_CMC_TBL_CSI_STBC_EN(table, val) \ 875 do { \ 876 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13)); \ 877 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN, \ 878 BIT(13)); \ 879 } while (0) 880 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0) 881 #define SET_CMC_TBL_CSI_LDPC_EN(table, val) \ 882 do { \ 883 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14)); \ 884 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN, \ 885 BIT(14)); \ 886 } while (0) 887 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0) 888 #define SET_CMC_TBL_CSI_PARA_EN(table, val) \ 889 do { \ 890 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15)); \ 891 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN, \ 892 BIT(15)); \ 893 } while (0) 894 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0) 895 #define SET_CMC_TBL_CSI_FIX_RATE(table, val) \ 896 do { \ 897 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16)); \ 898 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE, \ 899 GENMASK(24, 16)); \ 900 } while (0) 901 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0) 902 #define SET_CMC_TBL_CSI_GI_LTF(table, val) \ 903 do { \ 904 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25)); \ 905 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF, \ 906 GENMASK(27, 25)); \ 907 } while (0) 908 #define SET_CMC_TBL_MASK_CSI_GID_SEL BIT(0) 909 #define SET_CMC_TBL_CSI_GID_SEL(table, val) \ 910 do { \ 911 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(29)); \ 912 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GID_SEL, \ 913 BIT(29)); \ 914 } while (0) 915 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0) 916 #define SET_CMC_TBL_CSI_BW(table, val) \ 917 do { \ 918 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30)); \ 919 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW, \ 920 GENMASK(31, 30)); \ 921 } while (0) 922 923 #define SET_FWROLE_MAINTAIN_MACID(h2c, val) \ 924 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) 925 #define SET_FWROLE_MAINTAIN_SELF_ROLE(h2c, val) \ 926 le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8)) 927 #define SET_FWROLE_MAINTAIN_UPD_MODE(h2c, val) \ 928 le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10)) 929 #define SET_FWROLE_MAINTAIN_WIFI_ROLE(h2c, val) \ 930 le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13)) 931 932 #define SET_JOININFO_MACID(h2c, val) \ 933 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) 934 #define SET_JOININFO_OP(h2c, val) \ 935 le32p_replace_bits((__le32 *)h2c, val, BIT(8)) 936 #define SET_JOININFO_BAND(h2c, val) \ 937 le32p_replace_bits((__le32 *)h2c, val, BIT(9)) 938 #define SET_JOININFO_WMM(h2c, val) \ 939 le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10)) 940 #define SET_JOININFO_TGR(h2c, val) \ 941 le32p_replace_bits((__le32 *)h2c, val, BIT(12)) 942 #define SET_JOININFO_ISHESTA(h2c, val) \ 943 le32p_replace_bits((__le32 *)h2c, val, BIT(13)) 944 #define SET_JOININFO_DLBW(h2c, val) \ 945 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14)) 946 #define SET_JOININFO_TF_MAC_PAD(h2c, val) \ 947 le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16)) 948 #define SET_JOININFO_DL_T_PE(h2c, val) \ 949 le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18)) 950 #define SET_JOININFO_PORT_ID(h2c, val) \ 951 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21)) 952 #define SET_JOININFO_NET_TYPE(h2c, val) \ 953 le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24)) 954 #define SET_JOININFO_WIFI_ROLE(h2c, val) \ 955 le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26)) 956 #define SET_JOININFO_SELF_ROLE(h2c, val) \ 957 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30)) 958 959 #define SET_GENERAL_PKT_MACID(h2c, val) \ 960 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) 961 #define SET_GENERAL_PKT_PROBRSP_ID(h2c, val) \ 962 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)) 963 #define SET_GENERAL_PKT_PSPOLL_ID(h2c, val) \ 964 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)) 965 #define SET_GENERAL_PKT_NULL_ID(h2c, val) \ 966 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)) 967 #define SET_GENERAL_PKT_QOS_NULL_ID(h2c, val) \ 968 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)) 969 #define SET_GENERAL_PKT_CTS2SELF_ID(h2c, val) \ 970 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)) 971 972 #define SET_LOG_CFG_LEVEL(h2c, val) \ 973 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) 974 #define SET_LOG_CFG_PATH(h2c, val) \ 975 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)) 976 #define SET_LOG_CFG_COMP(h2c, val) \ 977 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)) 978 #define SET_LOG_CFG_COMP_EXT(h2c, val) \ 979 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0)) 980 981 #define SET_BA_CAM_VALID(h2c, val) \ 982 le32p_replace_bits((__le32 *)h2c, val, BIT(0)) 983 #define SET_BA_CAM_INIT_REQ(h2c, val) \ 984 le32p_replace_bits((__le32 *)h2c, val, BIT(1)) 985 #define SET_BA_CAM_ENTRY_IDX(h2c, val) \ 986 le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2)) 987 #define SET_BA_CAM_TID(h2c, val) \ 988 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4)) 989 #define SET_BA_CAM_MACID(h2c, val) \ 990 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)) 991 #define SET_BA_CAM_BMAP_SIZE(h2c, val) \ 992 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)) 993 #define SET_BA_CAM_SSN(h2c, val) \ 994 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20)) 995 996 #define SET_LPS_PARM_MACID(h2c, val) \ 997 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)) 998 #define SET_LPS_PARM_PSMODE(h2c, val) \ 999 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)) 1000 #define SET_LPS_PARM_RLBM(h2c, val) \ 1001 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)) 1002 #define SET_LPS_PARM_SMARTPS(h2c, val) \ 1003 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20)) 1004 #define SET_LPS_PARM_AWAKEINTERVAL(h2c, val) \ 1005 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)) 1006 #define SET_LPS_PARM_VOUAPSD(h2c, val) \ 1007 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0)) 1008 #define SET_LPS_PARM_VIUAPSD(h2c, val) \ 1009 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1)) 1010 #define SET_LPS_PARM_BEUAPSD(h2c, val) \ 1011 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2)) 1012 #define SET_LPS_PARM_BKUAPSD(h2c, val) \ 1013 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3)) 1014 #define SET_LPS_PARM_LASTRPWM(h2c, val) \ 1015 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)) 1016 1017 enum rtw89_btc_btf_h2c_class { 1018 BTFC_SET = 0x10, 1019 BTFC_GET = 0x11, 1020 BTFC_FW_EVENT = 0x12, 1021 }; 1022 1023 enum rtw89_btc_btf_set { 1024 SET_REPORT_EN = 0x0, 1025 SET_SLOT_TABLE, 1026 SET_MREG_TABLE, 1027 SET_CX_POLICY, 1028 SET_GPIO_DBG, 1029 SET_DRV_INFO, 1030 SET_DRV_EVENT, 1031 SET_BT_WREG_ADDR, 1032 SET_BT_WREG_VAL, 1033 SET_BT_RREG_ADDR, 1034 SET_BT_WL_CH_INFO, 1035 SET_BT_INFO_REPORT, 1036 SET_BT_IGNORE_WLAN_ACT, 1037 SET_BT_TX_PWR, 1038 SET_BT_LNA_CONSTRAIN, 1039 SET_BT_GOLDEN_RX_RANGE, 1040 SET_BT_PSD_REPORT, 1041 SET_H2C_TEST, 1042 SET_MAX1, 1043 }; 1044 1045 enum rtw89_btc_cxdrvinfo { 1046 CXDRVINFO_INIT = 0, 1047 CXDRVINFO_ROLE, 1048 CXDRVINFO_DBCC, 1049 CXDRVINFO_SMAP, 1050 CXDRVINFO_RFK, 1051 CXDRVINFO_RUN, 1052 CXDRVINFO_CTRL, 1053 CXDRVINFO_SCAN, 1054 CXDRVINFO_MAX, 1055 }; 1056 1057 #define RTW89_SET_FWCMD_CXHDR_TYPE(cmd, val) \ 1058 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0)) 1059 #define RTW89_SET_FWCMD_CXHDR_LEN(cmd, val) \ 1060 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0)) 1061 1062 #define RTW89_SET_FWCMD_CXINIT_ANT_TYPE(cmd, val) \ 1063 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)) 1064 #define RTW89_SET_FWCMD_CXINIT_ANT_NUM(cmd, val) \ 1065 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)) 1066 #define RTW89_SET_FWCMD_CXINIT_ANT_ISO(cmd, val) \ 1067 u8p_replace_bits((u8 *)(cmd) + 4, val, GENMASK(7, 0)) 1068 #define RTW89_SET_FWCMD_CXINIT_ANT_POS(cmd, val) \ 1069 u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(0)) 1070 #define RTW89_SET_FWCMD_CXINIT_ANT_DIVERSITY(cmd, val) \ 1071 u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(1)) 1072 #define RTW89_SET_FWCMD_CXINIT_MOD_RFE(cmd, val) \ 1073 u8p_replace_bits((u8 *)(cmd) + 6, val, GENMASK(7, 0)) 1074 #define RTW89_SET_FWCMD_CXINIT_MOD_CV(cmd, val) \ 1075 u8p_replace_bits((u8 *)(cmd) + 7, val, GENMASK(7, 0)) 1076 #define RTW89_SET_FWCMD_CXINIT_MOD_BT_SOLO(cmd, val) \ 1077 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(0)) 1078 #define RTW89_SET_FWCMD_CXINIT_MOD_BT_POS(cmd, val) \ 1079 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(1)) 1080 #define RTW89_SET_FWCMD_CXINIT_MOD_SW_TYPE(cmd, val) \ 1081 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(2)) 1082 #define RTW89_SET_FWCMD_CXINIT_WL_GCH(cmd, val) \ 1083 u8p_replace_bits((u8 *)(cmd) + 10, val, GENMASK(7, 0)) 1084 #define RTW89_SET_FWCMD_CXINIT_WL_ONLY(cmd, val) \ 1085 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(0)) 1086 #define RTW89_SET_FWCMD_CXINIT_WL_INITOK(cmd, val) \ 1087 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(1)) 1088 #define RTW89_SET_FWCMD_CXINIT_DBCC_EN(cmd, val) \ 1089 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(2)) 1090 #define RTW89_SET_FWCMD_CXINIT_CX_OTHER(cmd, val) \ 1091 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(3)) 1092 #define RTW89_SET_FWCMD_CXINIT_BT_ONLY(cmd, val) \ 1093 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(4)) 1094 1095 #define RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(cmd, val) \ 1096 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)) 1097 #define RTW89_SET_FWCMD_CXROLE_LINK_MODE(cmd, val) \ 1098 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)) 1099 #define RTW89_SET_FWCMD_CXROLE_ROLE_NONE(cmd, val) \ 1100 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0)) 1101 #define RTW89_SET_FWCMD_CXROLE_ROLE_STA(cmd, val) \ 1102 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1)) 1103 #define RTW89_SET_FWCMD_CXROLE_ROLE_AP(cmd, val) \ 1104 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2)) 1105 #define RTW89_SET_FWCMD_CXROLE_ROLE_VAP(cmd, val) \ 1106 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3)) 1107 #define RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(cmd, val) \ 1108 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4)) 1109 #define RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(cmd, val) \ 1110 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5)) 1111 #define RTW89_SET_FWCMD_CXROLE_ROLE_MESH(cmd, val) \ 1112 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6)) 1113 #define RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(cmd, val) \ 1114 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7)) 1115 #define RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(cmd, val) \ 1116 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8)) 1117 #define RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(cmd, val) \ 1118 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9)) 1119 #define RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(cmd, val) \ 1120 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10)) 1121 #define RTW89_SET_FWCMD_CXROLE_ROLE_NAN(cmd, val) \ 1122 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11)) 1123 #define RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(cmd, val, n) \ 1124 u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(0)) 1125 #define RTW89_SET_FWCMD_CXROLE_ACT_PID(cmd, val, n) \ 1126 u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, GENMASK(3, 1)) 1127 #define RTW89_SET_FWCMD_CXROLE_ACT_PHY(cmd, val, n) \ 1128 u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(4)) 1129 #define RTW89_SET_FWCMD_CXROLE_ACT_NOA(cmd, val, n) \ 1130 u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(5)) 1131 #define RTW89_SET_FWCMD_CXROLE_ACT_BAND(cmd, val, n) \ 1132 u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, GENMASK(7, 6)) 1133 #define RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(cmd, val, n) \ 1134 u8p_replace_bits((u8 *)(cmd) + (7 + 12 * (n)), val, BIT(0)) 1135 #define RTW89_SET_FWCMD_CXROLE_ACT_BW(cmd, val, n) \ 1136 u8p_replace_bits((u8 *)(cmd) + (7 + 12 * (n)), val, GENMASK(7, 1)) 1137 #define RTW89_SET_FWCMD_CXROLE_ACT_ROLE(cmd, val, n) \ 1138 u8p_replace_bits((u8 *)(cmd) + (8 + 12 * (n)), val, GENMASK(7, 0)) 1139 #define RTW89_SET_FWCMD_CXROLE_ACT_CH(cmd, val, n) \ 1140 u8p_replace_bits((u8 *)(cmd) + (9 + 12 * (n)), val, GENMASK(7, 0)) 1141 #define RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(cmd, val, n) \ 1142 le16p_replace_bits((__le16 *)((u8 *)(cmd) + (10 + 12 * (n))), val, GENMASK(15, 0)) 1143 #define RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(cmd, val, n) \ 1144 le16p_replace_bits((__le16 *)((u8 *)(cmd) + (12 + 12 * (n))), val, GENMASK(15, 0)) 1145 #define RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(cmd, val, n) \ 1146 le16p_replace_bits((__le16 *)((u8 *)(cmd) + (14 + 12 * (n))), val, GENMASK(15, 0)) 1147 #define RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(cmd, val, n) \ 1148 le16p_replace_bits((__le16 *)((u8 *)(cmd) + (16 + 12 * (n))), val, GENMASK(15, 0)) 1149 1150 #define RTW89_SET_FWCMD_CXCTRL_MANUAL(cmd, val) \ 1151 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0)) 1152 #define RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(cmd, val) \ 1153 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1)) 1154 #define RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(cmd, val) \ 1155 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2)) 1156 #define RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(cmd, val) \ 1157 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3)) 1158 1159 #define RTW89_SET_FWCMD_CXRFK_STATE(cmd, val) \ 1160 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0)) 1161 #define RTW89_SET_FWCMD_CXRFK_PATH_MAP(cmd, val) \ 1162 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2)) 1163 #define RTW89_SET_FWCMD_CXRFK_PHY_MAP(cmd, val) \ 1164 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6)) 1165 #define RTW89_SET_FWCMD_CXRFK_BAND(cmd, val) \ 1166 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8)) 1167 #define RTW89_SET_FWCMD_CXRFK_TYPE(cmd, val) \ 1168 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10)) 1169 1170 #define RTW89_C2H_HEADER_LEN 8 1171 1172 #define RTW89_GET_C2H_CATEGORY(c2h) \ 1173 le32_get_bits(*((__le32 *)c2h), GENMASK(1, 0)) 1174 #define RTW89_GET_C2H_CLASS(c2h) \ 1175 le32_get_bits(*((__le32 *)c2h), GENMASK(7, 2)) 1176 #define RTW89_GET_C2H_FUNC(c2h) \ 1177 le32_get_bits(*((__le32 *)c2h), GENMASK(15, 8)) 1178 #define RTW89_GET_C2H_LEN(c2h) \ 1179 le32_get_bits(*((__le32 *)(c2h) + 1), GENMASK(13, 0)) 1180 1181 #define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2) 1182 #define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN) 1183 1184 #define RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h) \ 1185 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(1, 0)) 1186 #define RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h) \ 1187 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(7, 2)) 1188 #define RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h) \ 1189 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(15, 8)) 1190 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h) \ 1191 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(23, 16)) 1192 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h) \ 1193 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(31, 24)) 1194 1195 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \ 1196 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(1, 0)) 1197 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \ 1198 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(7, 2)) 1199 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \ 1200 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(15, 8)) 1201 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \ 1202 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(23, 16)) 1203 1204 #define RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h) \ 1205 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(15, 0)) 1206 #define RTW89_GET_PHY_C2H_RA_RPT_RETRY_RATIO(c2h) \ 1207 le32_get_bits(*((__le32 *)(c2h) + 2), GENMASK(23, 16)) 1208 #define RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h) \ 1209 le32_get_bits(*((__le32 *)(c2h) + 3), GENMASK(6, 0)) 1210 #define RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h) \ 1211 le32_get_bits(*((__le32 *)(c2h) + 3), GENMASK(9, 8)) 1212 #define RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h) \ 1213 le32_get_bits(*((__le32 *)(c2h) + 3), GENMASK(12, 10)) 1214 #define RTW89_GET_PHY_C2H_RA_RPT_BW(c2h) \ 1215 le32_get_bits(*((__le32 *)(c2h) + 3), GENMASK(14, 13)) 1216 1217 /* VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS 1218 * HT-new: [6:5]: NA, [4:0]: MCS 1219 */ 1220 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4) 1221 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0) 1222 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0) 1223 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \ 1224 FIELD_PREP(GENMASK(2, 0), mcs)) 1225 1226 #define RTW89_FW_HDR_SIZE 32 1227 #define RTW89_FW_SECTION_HDR_SIZE 16 1228 1229 #define RTW89_MFW_SIG 0xFF 1230 1231 struct rtw89_mfw_info { 1232 u8 cv; 1233 u8 type; /* enum rtw89_fw_type */ 1234 u8 mp; 1235 u8 rsvd; 1236 __le32 shift; 1237 __le32 size; 1238 u8 rsvd2[4]; 1239 } __packed; 1240 1241 struct rtw89_mfw_hdr { 1242 u8 sig; /* RTW89_MFW_SIG */ 1243 u8 fw_nr; 1244 u8 rsvd[14]; 1245 struct rtw89_mfw_info info[]; 1246 } __packed; 1247 1248 struct fwcmd_hdr { 1249 __le32 hdr0; 1250 __le32 hdr1; 1251 }; 1252 1253 #define RTW89_H2C_RF_PAGE_SIZE 500 1254 #define RTW89_H2C_RF_PAGE_NUM 3 1255 struct rtw89_fw_h2c_rf_reg_info { 1256 enum rtw89_rf_path rf_path; 1257 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE]; 1258 u16 curr_idx; 1259 }; 1260 1261 #define H2C_SEC_CAM_LEN 24 1262 1263 #define H2C_HEADER_LEN 8 1264 #define H2C_HDR_CAT GENMASK(1, 0) 1265 #define H2C_HDR_CLASS GENMASK(7, 2) 1266 #define H2C_HDR_FUNC GENMASK(15, 8) 1267 #define H2C_HDR_DEL_TYPE GENMASK(19, 16) 1268 #define H2C_HDR_H2C_SEQ GENMASK(31, 24) 1269 #define H2C_HDR_TOTAL_LEN GENMASK(13, 0) 1270 #define H2C_HDR_REC_ACK BIT(14) 1271 #define H2C_HDR_DONE_ACK BIT(15) 1272 1273 #define FWCMD_TYPE_H2C 0 1274 1275 #define H2C_CAT_MAC 0x1 1276 1277 /* CLASS 0 - FW INFO */ 1278 #define H2C_CL_FW_INFO 0x0 1279 #define H2C_FUNC_LOG_CFG 0x0 1280 #define H2C_FUNC_MAC_GENERAL_PKT 0x1 1281 1282 /* CLASS 2 - PS */ 1283 #define H2C_CL_MAC_PS 0x2 1284 #define H2C_FUNC_MAC_LPS_PARM 0x0 1285 1286 /* CLASS 3 - FW download */ 1287 #define H2C_CL_MAC_FWDL 0x3 1288 #define H2C_FUNC_MAC_FWHDR_DL 0x0 1289 1290 /* CLASS 5 - Frame Exchange */ 1291 #define H2C_CL_MAC_FR_EXCHG 0x5 1292 #define H2C_FUNC_MAC_CCTLINFO_UD 0x2 1293 1294 /* CLASS 6 - Address CAM */ 1295 #define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6 1296 #define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0 1297 1298 /* CLASS 8 - Media Status Report */ 1299 #define H2C_CL_MAC_MEDIA_RPT 0x8 1300 #define H2C_FUNC_MAC_JOININFO 0x0 1301 #define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4 1302 1303 /* CLASS 9 - FW offload */ 1304 #define H2C_CL_MAC_FW_OFLD 0x9 1305 #define H2C_FUNC_MAC_MACID_PAUSE 0x8 1306 #define H2C_FUNC_USR_EDCA 0xF 1307 #define H2C_FUNC_OFLD_CFG 0x14 1308 1309 /* CLASS 10 - Security CAM */ 1310 #define H2C_CL_MAC_SEC_CAM 0xa 1311 #define H2C_FUNC_MAC_SEC_UPD 0x1 1312 1313 /* CLASS 12 - BA CAM */ 1314 #define H2C_CL_BA_CAM 0xc 1315 #define H2C_FUNC_MAC_BA_CAM 0x0 1316 1317 #define H2C_CAT_OUTSRC 0x2 1318 1319 #define H2C_CL_OUTSRC_RA 0x1 1320 #define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0 1321 1322 #define H2C_CL_OUTSRC_RF_REG_A 0x8 1323 #define H2C_CL_OUTSRC_RF_REG_B 0x9 1324 1325 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev); 1326 int rtw89_fw_recognize(struct rtw89_dev *rtwdev); 1327 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type); 1328 int rtw89_load_firmware(struct rtw89_dev *rtwdev); 1329 void rtw89_unload_firmware(struct rtw89_dev *rtwdev); 1330 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev); 1331 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1332 u8 type, u8 cat, u8 class, u8 func, 1333 bool rack, bool dack, u32 len); 1334 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, u8 macid); 1335 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, 1336 struct ieee80211_vif *vif, 1337 struct ieee80211_sta *sta); 1338 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev, 1339 struct rtw89_sta *rtwsta); 1340 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); 1341 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h); 1342 void rtw89_fw_c2h_work(struct work_struct *work); 1343 int rtw89_fw_h2c_vif_maintain(struct rtw89_dev *rtwdev, 1344 struct rtw89_vif *rtwvif, 1345 enum rtw89_upd_mode upd_mode); 1346 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1347 u8 dis_conn); 1348 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp, 1349 bool pause); 1350 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1351 u8 ac, u32 val); 1352 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev); 1353 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi); 1354 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev); 1355 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev); 1356 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev); 1357 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev); 1358 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev, 1359 struct rtw89_fw_h2c_rf_reg_info *info, 1360 u16 len, u8 page); 1361 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, 1362 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, 1363 bool rack, bool dack); 1364 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len); 1365 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev); 1366 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev); 1367 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, u8 macid); 1368 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, bool valid, u8 macid, 1369 struct ieee80211_ampdu_params *params); 1370 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev, 1371 struct rtw89_lps_parm *lps_param); 1372 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(u32 len); 1373 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(u32 len); 1374 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev, 1375 struct rtw89_mac_h2c_info *h2c_info, 1376 struct rtw89_mac_c2h_info *c2h_info); 1377 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable); 1378 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev); 1379 1380 #endif 1381