1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020  Realtek Corporation
3  */
4 
5 #ifndef __RTW89_FW_H__
6 #define __RTW89_FW_H__
7 
8 #include "core.h"
9 
10 enum rtw89_fw_dl_status {
11 	RTW89_FWDL_INITIAL_STATE = 0,
12 	RTW89_FWDL_FWDL_ONGOING = 1,
13 	RTW89_FWDL_CHECKSUM_FAIL = 2,
14 	RTW89_FWDL_SECURITY_FAIL = 3,
15 	RTW89_FWDL_CV_NOT_MATCH = 4,
16 	RTW89_FWDL_RSVD0 = 5,
17 	RTW89_FWDL_WCPU_FWDL_RDY = 6,
18 	RTW89_FWDL_WCPU_FW_INIT_RDY = 7
19 };
20 
21 struct rtw89_c2hreg_hdr {
22 	u32 w0;
23 };
24 
25 #define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0)
26 #define RTW89_C2HREG_HDR_ACK BIT(7)
27 #define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8)
28 #define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)
29 
30 struct rtw89_c2hreg_phycap {
31 	u32 w0;
32 	u32 w1;
33 	u32 w2;
34 	u32 w3;
35 } __packed;
36 
37 #define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0)
38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
39 #define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8)
40 #define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)
41 #define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16)
42 #define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)
43 #define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0)
44 #define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8)
45 #define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16)
46 #define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24)
47 #define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0)
48 #define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8)
49 #define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16)
50 
51 struct rtw89_h2creg_hdr {
52 	u32 w0;
53 };
54 
55 #define RTW89_H2CREG_HDR_FUNC_MASK GENMASK(6, 0)
56 #define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8)
57 
58 struct rtw89_h2creg_sch_tx_en {
59 	u32 w0;
60 	u32 w1;
61 } __packed;
62 
63 #define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16)
64 #define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0)
65 #define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)
66 
67 #define RTW89_H2CREG_MAX 4
68 #define RTW89_C2HREG_MAX 4
69 #define RTW89_C2HREG_HDR_LEN 2
70 #define RTW89_H2CREG_HDR_LEN 2
71 #define RTW89_C2H_TIMEOUT 1000000
72 struct rtw89_mac_c2h_info {
73 	u8 id;
74 	u8 content_len;
75 	union {
76 		u32 c2hreg[RTW89_C2HREG_MAX];
77 		struct rtw89_c2hreg_hdr hdr;
78 		struct rtw89_c2hreg_phycap phycap;
79 	} u;
80 };
81 
82 struct rtw89_mac_h2c_info {
83 	u8 id;
84 	u8 content_len;
85 	union {
86 		u32 h2creg[RTW89_H2CREG_MAX];
87 		struct rtw89_h2creg_hdr hdr;
88 		struct rtw89_h2creg_sch_tx_en sch_tx_en;
89 	} u;
90 };
91 
92 enum rtw89_mac_h2c_type {
93 	RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0,
94 	RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD,
95 	RTW89_FWCMD_H2CREG_FUNC_FWERR,
96 	RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE,
97 	RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM,
98 	RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN
99 };
100 
101 enum rtw89_mac_c2h_type {
102 	RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0,
103 	RTW89_FWCMD_C2HREG_FUNC_ERR_RPT,
104 	RTW89_FWCMD_C2HREG_FUNC_ERR_MSG,
105 	RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,
106 	RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,
107 	RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF
108 };
109 
110 enum rtw89_fw_c2h_category {
111 	RTW89_C2H_CAT_TEST,
112 	RTW89_C2H_CAT_MAC,
113 	RTW89_C2H_CAT_OUTSRC,
114 };
115 
116 enum rtw89_fw_log_level {
117 	RTW89_FW_LOG_LEVEL_OFF,
118 	RTW89_FW_LOG_LEVEL_CRT,
119 	RTW89_FW_LOG_LEVEL_SER,
120 	RTW89_FW_LOG_LEVEL_WARN,
121 	RTW89_FW_LOG_LEVEL_LOUD,
122 	RTW89_FW_LOG_LEVEL_TR,
123 };
124 
125 enum rtw89_fw_log_path {
126 	RTW89_FW_LOG_LEVEL_UART,
127 	RTW89_FW_LOG_LEVEL_C2H,
128 	RTW89_FW_LOG_LEVEL_SNI,
129 };
130 
131 enum rtw89_fw_log_comp {
132 	RTW89_FW_LOG_COMP_VER,
133 	RTW89_FW_LOG_COMP_INIT,
134 	RTW89_FW_LOG_COMP_TASK,
135 	RTW89_FW_LOG_COMP_CNS,
136 	RTW89_FW_LOG_COMP_H2C,
137 	RTW89_FW_LOG_COMP_C2H,
138 	RTW89_FW_LOG_COMP_TX,
139 	RTW89_FW_LOG_COMP_RX,
140 	RTW89_FW_LOG_COMP_IPSEC,
141 	RTW89_FW_LOG_COMP_TIMER,
142 	RTW89_FW_LOG_COMP_DBGPKT,
143 	RTW89_FW_LOG_COMP_PS,
144 	RTW89_FW_LOG_COMP_ERROR,
145 	RTW89_FW_LOG_COMP_WOWLAN,
146 	RTW89_FW_LOG_COMP_SECURE_BOOT,
147 	RTW89_FW_LOG_COMP_BTC,
148 	RTW89_FW_LOG_COMP_BB,
149 	RTW89_FW_LOG_COMP_TWT,
150 	RTW89_FW_LOG_COMP_RF,
151 	RTW89_FW_LOG_COMP_MCC = 20,
152 };
153 
154 enum rtw89_pkt_offload_op {
155 	RTW89_PKT_OFLD_OP_ADD,
156 	RTW89_PKT_OFLD_OP_DEL,
157 	RTW89_PKT_OFLD_OP_READ,
158 
159 	NUM_OF_RTW89_PKT_OFFLOAD_OP,
160 };
161 
162 #define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) \
163 	((pkt_id) * NUM_OF_RTW89_PKT_OFFLOAD_OP + (pkt_op))
164 
165 enum rtw89_scanofld_notify_reason {
166 	RTW89_SCAN_DWELL_NOTIFY,
167 	RTW89_SCAN_PRE_TX_NOTIFY,
168 	RTW89_SCAN_POST_TX_NOTIFY,
169 	RTW89_SCAN_ENTER_CH_NOTIFY,
170 	RTW89_SCAN_LEAVE_CH_NOTIFY,
171 	RTW89_SCAN_END_SCAN_NOTIFY,
172 };
173 
174 enum rtw89_chan_type {
175 	RTW89_CHAN_OPERATE = 0,
176 	RTW89_CHAN_ACTIVE,
177 	RTW89_CHAN_DFS,
178 };
179 
180 enum rtw89_p2pps_action {
181 	RTW89_P2P_ACT_INIT = 0,
182 	RTW89_P2P_ACT_UPDATE = 1,
183 	RTW89_P2P_ACT_REMOVE = 2,
184 	RTW89_P2P_ACT_TERMINATE = 3,
185 };
186 
187 enum rtw89_bcn_fltr_offload_mode {
188 	RTW89_BCN_FLTR_OFFLOAD_MODE_0 = 0,
189 	RTW89_BCN_FLTR_OFFLOAD_MODE_1,
190 	RTW89_BCN_FLTR_OFFLOAD_MODE_2,
191 	RTW89_BCN_FLTR_OFFLOAD_MODE_3,
192 
193 	RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT = RTW89_BCN_FLTR_OFFLOAD_MODE_0,
194 };
195 
196 enum rtw89_bcn_fltr_type {
197 	RTW89_BCN_FLTR_BEACON_LOSS,
198 	RTW89_BCN_FLTR_RSSI,
199 	RTW89_BCN_FLTR_NOTIFY,
200 };
201 
202 enum rtw89_bcn_fltr_rssi_event {
203 	RTW89_BCN_FLTR_RSSI_NOT_CHANGED,
204 	RTW89_BCN_FLTR_RSSI_HIGH,
205 	RTW89_BCN_FLTR_RSSI_LOW,
206 };
207 
208 #define FWDL_SECTION_MAX_NUM 10
209 #define FWDL_SECTION_CHKSUM_LEN	8
210 #define FWDL_SECTION_PER_PKT_LEN 2020
211 
212 struct rtw89_fw_hdr_section_info {
213 	u8 redl;
214 	const u8 *addr;
215 	u32 len;
216 	u32 dladdr;
217 	u32 mssc;
218 	u8 type;
219 };
220 
221 struct rtw89_fw_bin_info {
222 	u8 section_num;
223 	u32 hdr_len;
224 	bool dynamic_hdr_en;
225 	u32 dynamic_hdr_len;
226 	struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];
227 };
228 
229 struct rtw89_fw_macid_pause_grp {
230 	__le32 pause_grp[4];
231 	__le32 mask_grp[4];
232 } __packed;
233 
234 #define RTW89_H2C_MAX_SIZE 2048
235 #define RTW89_CHANNEL_TIME 45
236 #define RTW89_CHANNEL_TIME_6G 20
237 #define RTW89_DFS_CHAN_TIME 105
238 #define RTW89_OFF_CHAN_TIME 100
239 #define RTW89_DWELL_TIME 20
240 #define RTW89_DWELL_TIME_6G 10
241 #define RTW89_SCAN_WIDTH 0
242 #define RTW89_SCANOFLD_MAX_SSID 8
243 #define RTW89_SCANOFLD_MAX_IE_LEN 512
244 #define RTW89_SCANOFLD_PKT_NONE 0xFF
245 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F
246 #define RTW89_MAC_CHINFO_SIZE 28
247 #define RTW89_SCAN_LIST_GUARD 4
248 #define RTW89_SCAN_LIST_LIMIT \
249 		((RTW89_H2C_MAX_SIZE / RTW89_MAC_CHINFO_SIZE) - RTW89_SCAN_LIST_GUARD)
250 
251 #define RTW89_BCN_LOSS_CNT 10
252 
253 struct rtw89_mac_chinfo {
254 	u8 period;
255 	u8 dwell_time;
256 	u8 central_ch;
257 	u8 pri_ch;
258 	u8 bw:3;
259 	u8 notify_action:5;
260 	u8 num_pkt:4;
261 	u8 tx_pkt:1;
262 	u8 pause_data:1;
263 	u8 ch_band:2;
264 	u8 probe_id;
265 	u8 dfs_ch:1;
266 	u8 tx_null:1;
267 	u8 rand_seq_num:1;
268 	u8 cfg_tx_pwr:1;
269 	u8 rsvd0: 4;
270 	u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
271 	u16 tx_pwr_idx;
272 	u8 rsvd1;
273 	struct list_head list;
274 	bool is_psc;
275 };
276 
277 struct rtw89_scan_option {
278 	bool enable;
279 	bool target_ch_mode;
280 };
281 
282 struct rtw89_pktofld_info {
283 	struct list_head list;
284 	u8 id;
285 
286 	/* Below fields are for 6 GHz RNR use only */
287 	u8 ssid[IEEE80211_MAX_SSID_LEN];
288 	u8 ssid_len;
289 	u8 bssid[ETH_ALEN];
290 	u16 channel_6ghz;
291 	bool cancel;
292 };
293 
294 struct rtw89_h2c_ra {
295 	__le32 w0;
296 	__le32 w1;
297 	__le32 w2;
298 	__le32 w3;
299 } __packed;
300 
301 #define RTW89_H2C_RA_W0_IS_DIS BIT(0)
302 #define RTW89_H2C_RA_W0_MODE GENMASK(5, 1)
303 #define RTW89_H2C_RA_W0_BW_CAP GENMASK(7, 6)
304 #define RTW89_H2C_RA_W0_MACID GENMASK(15, 8)
305 #define RTW89_H2C_RA_W0_DCM BIT(16)
306 #define RTW89_H2C_RA_W0_ER BIT(17)
307 #define RTW89_H2C_RA_W0_INIT_RATE_LV GENMASK(19, 18)
308 #define RTW89_H2C_RA_W0_UPD_ALL BIT(20)
309 #define RTW89_H2C_RA_W0_SGI BIT(21)
310 #define RTW89_H2C_RA_W0_LDPC BIT(22)
311 #define RTW89_H2C_RA_W0_STBC BIT(23)
312 #define RTW89_H2C_RA_W0_SS_NUM GENMASK(26, 24)
313 #define RTW89_H2C_RA_W0_GILTF GENMASK(29, 27)
314 #define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK BIT(30)
315 #define RTW89_H2C_RA_W0_UPD_MASK BIT(31)
316 #define RTW89_H2C_RA_W1_RAMASK_LO32 GENMASK(31, 0)
317 #define RTW89_H2C_RA_W2_RAMASK_HI32 GENMASK(30, 0)
318 #define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31)
319 #define RTW89_H2C_RA_W3_BAND_NUM GENMASK(7, 0)
320 #define RTW89_H2C_RA_W3_RA_CSI_RATE_EN BIT(8)
321 #define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN BIT(9)
322 #define RTW89_H2C_RA_W3_CR_TBL_SEL BIT(10)
323 #define RTW89_H2C_RA_W3_FIX_GILTF_EN BIT(11)
324 #define RTW89_H2C_RA_W3_FIX_GILTF GENMASK(14, 12)
325 #define RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX GENMASK(23, 16)
326 #define RTW89_H2C_RA_W3_FIXED_CSI_MODE GENMASK(25, 24)
327 #define RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF GENMASK(28, 26)
328 #define RTW89_H2C_RA_W3_FIXED_CSI_BW GENMASK(31, 29)
329 
330 struct rtw89_h2c_ra_v1 {
331 	struct rtw89_h2c_ra v0;
332 	__le32 w4;
333 	__le32 w5;
334 } __packed;
335 
336 #define RTW89_H2C_RA_V1_W4_MODE_EHT GENMASK(6, 0)
337 #define RTW89_H2C_RA_V1_W4_BW_EHT GENMASK(10, 8)
338 #define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16)
339 #define RTW89_H2C_RA_V1_W5_RAMASK_UHH16 GENMASK(15, 0)
340 
341 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)
342 {
343 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));
344 }
345 
346 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val)
347 {
348 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
349 }
350 
351 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val)
352 {
353 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16));
354 }
355 
356 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val)
357 {
358 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0));
359 }
360 
361 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val)
362 {
363 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4));
364 }
365 
366 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val)
367 {
368 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5));
369 }
370 
371 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val)
372 {
373 	le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0));
374 }
375 
376 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val)
377 {
378 	le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0));
379 }
380 
381 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val)
382 {
383 	le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0));
384 }
385 
386 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val)
387 {
388 	le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0));
389 }
390 
391 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val)
392 {
393 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0));
394 }
395 
396 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val)
397 {
398 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3));
399 }
400 
401 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val)
402 {
403 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4));
404 }
405 
406 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val)
407 {
408 	le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5));
409 }
410 
411 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val)
412 {
413 	le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0));
414 }
415 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)
416 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)
417 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)
418 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)
419 
420 #define FWDL_SECURITY_SECTION_TYPE 9
421 #define FWDL_SECURITY_SIGLEN 512
422 
423 struct rtw89_fw_dynhdr_sec {
424 	__le32 w0;
425 	u8 content[];
426 } __packed;
427 
428 struct rtw89_fw_dynhdr_hdr {
429 	__le32 hdr_len;
430 	__le32 setcion_count;
431 	/* struct rtw89_fw_dynhdr_sec (nested flexible structures) */
432 } __packed;
433 
434 struct rtw89_fw_hdr_section {
435 	__le32 w0;
436 	__le32 w1;
437 	__le32 w2;
438 	__le32 w3;
439 } __packed;
440 
441 #define FWSECTION_HDR_W0_DL_ADDR GENMASK(31, 0)
442 #define FWSECTION_HDR_W1_METADATA GENMASK(31, 24)
443 #define FWSECTION_HDR_W1_SECTIONTYPE GENMASK(27, 24)
444 #define FWSECTION_HDR_W1_SEC_SIZE GENMASK(23, 0)
445 #define FWSECTION_HDR_W1_CHECKSUM BIT(28)
446 #define FWSECTION_HDR_W1_REDL BIT(29)
447 #define FWSECTION_HDR_W2_MSSC GENMASK(31, 0)
448 
449 struct rtw89_fw_hdr {
450 	__le32 w0;
451 	__le32 w1;
452 	__le32 w2;
453 	__le32 w3;
454 	__le32 w4;
455 	__le32 w5;
456 	__le32 w6;
457 	__le32 w7;
458 	struct rtw89_fw_hdr_section sections[];
459 	/* struct rtw89_fw_dynhdr_hdr (optional) */
460 } __packed;
461 
462 #define FW_HDR_W1_MAJOR_VERSION GENMASK(7, 0)
463 #define FW_HDR_W1_MINOR_VERSION GENMASK(15, 8)
464 #define FW_HDR_W1_SUBVERSION GENMASK(23, 16)
465 #define FW_HDR_W1_SUBINDEX GENMASK(31, 24)
466 #define FW_HDR_W2_COMMITID GENMASK(31, 0)
467 #define FW_HDR_W3_LEN GENMASK(23, 16)
468 #define FW_HDR_W3_HDR_VER GENMASK(31, 24)
469 #define FW_HDR_W4_MONTH GENMASK(7, 0)
470 #define FW_HDR_W4_DATE GENMASK(15, 8)
471 #define FW_HDR_W4_HOUR GENMASK(23, 16)
472 #define FW_HDR_W4_MIN GENMASK(31, 24)
473 #define FW_HDR_W5_YEAR GENMASK(31, 0)
474 #define FW_HDR_W6_SEC_NUM GENMASK(15, 8)
475 #define FW_HDR_W7_DYN_HDR BIT(16)
476 #define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24)
477 
478 struct rtw89_fw_hdr_section_v1 {
479 	__le32 w0;
480 	__le32 w1;
481 	__le32 w2;
482 	__le32 w3;
483 } __packed;
484 
485 #define FWSECTION_HDR_V1_W0_DL_ADDR GENMASK(31, 0)
486 #define FWSECTION_HDR_V1_W1_METADATA GENMASK(31, 24)
487 #define FWSECTION_HDR_V1_W1_SECTIONTYPE GENMASK(27, 24)
488 #define FWSECTION_HDR_V1_W1_SEC_SIZE GENMASK(23, 0)
489 #define FWSECTION_HDR_V1_W1_CHECKSUM BIT(28)
490 #define FWSECTION_HDR_V1_W1_REDL BIT(29)
491 #define FWSECTION_HDR_V1_W2_MSSC GENMASK(7, 0)
492 #define FWSECTION_HDR_V1_W2_BBMCU_IDX GENMASK(27, 24)
493 
494 struct rtw89_fw_hdr_v1 {
495 	__le32 w0;
496 	__le32 w1;
497 	__le32 w2;
498 	__le32 w3;
499 	__le32 w4;
500 	__le32 w5;
501 	__le32 w6;
502 	__le32 w7;
503 	__le32 w8;
504 	__le32 w9;
505 	__le32 w10;
506 	__le32 w11;
507 	struct rtw89_fw_hdr_section_v1 sections[];
508 } __packed;
509 
510 #define FW_HDR_V1_W1_MAJOR_VERSION GENMASK(7, 0)
511 #define FW_HDR_V1_W1_MINOR_VERSION GENMASK(15, 8)
512 #define FW_HDR_V1_W1_SUBVERSION GENMASK(23, 16)
513 #define FW_HDR_V1_W1_SUBINDEX GENMASK(31, 24)
514 #define FW_HDR_V1_W2_COMMITID GENMASK(31, 0)
515 #define FW_HDR_V1_W3_CMD_VERSERION GENMASK(23, 16)
516 #define FW_HDR_V1_W3_HDR_VER GENMASK(31, 24)
517 #define FW_HDR_V1_W4_MONTH GENMASK(7, 0)
518 #define FW_HDR_V1_W4_DATE GENMASK(15, 8)
519 #define FW_HDR_V1_W4_HOUR GENMASK(23, 16)
520 #define FW_HDR_V1_W4_MIN GENMASK(31, 24)
521 #define FW_HDR_V1_W5_YEAR GENMASK(15, 0)
522 #define FW_HDR_V1_W5_HDR_SIZE GENMASK(31, 16)
523 #define FW_HDR_V1_W6_SEC_NUM GENMASK(15, 8)
524 #define FW_HDR_V1_W7_DYN_HDR BIT(16)
525 
526 static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val)
527 {
528 	le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0));
529 }
530 
531 static inline void SET_CTRL_INFO_MACID(void *table, u32 val)
532 {
533 	le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
534 }
535 
536 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val)
537 {
538 	le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
539 }
540 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)
541 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val)
542 {
543 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0));
544 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE,
545 			   GENMASK(8, 0));
546 }
547 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
548 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val)
549 {
550 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9));
551 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP,
552 			   BIT(9));
553 }
554 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0)
555 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val)
556 {
557 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10));
558 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW,
559 			   GENMASK(11, 10));
560 }
561 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0)
562 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val)
563 {
564 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12));
565 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF,
566 			   GENMASK(14, 12));
567 }
568 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
569 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val)
570 {
571 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
572 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX,
573 			   BIT(15));
574 }
575 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0)
576 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val)
577 {
578 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16));
579 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL,
580 			   GENMASK(19, 16));
581 }
582 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
583 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val)
584 {
585 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20));
586 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN,
587 			   BIT(20));
588 }
589 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
590 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val)
591 {
592 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21));
593 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN,
594 			   BIT(21));
595 }
596 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
597 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val)
598 {
599 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22));
600 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN,
601 			   BIT(22));
602 }
603 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
604 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val)
605 {
606 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23));
607 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN,
608 			   BIT(23));
609 }
610 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
611 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val)
612 {
613 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25));
614 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB,
615 			   BIT(25));
616 }
617 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
618 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val)
619 {
620 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26));
621 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB,
622 			   BIT(26));
623 }
624 #define SET_CMC_TBL_MASK_TRYRATE BIT(0)
625 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val)
626 {
627 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27));
628 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE,
629 			   BIT(27));
630 }
631 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0)
632 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val)
633 {
634 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28));
635 	le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY,
636 			   GENMASK(31, 28));
637 }
638 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)
639 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val)
640 {
641 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0));
642 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE,
643 			   GENMASK(8, 0));
644 }
645 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
646 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val)
647 {
648 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9));
649 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL,
650 			   BIT(9));
651 }
652 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
653 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val)
654 {
655 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10));
656 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL,
657 			   BIT(10));
658 }
659 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
660 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val)
661 {
662 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11));
663 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL,
664 			   BIT(11));
665 }
666 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0)
667 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val)
668 {
669 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12));
670 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT,
671 			   GENMASK(15, 12));
672 }
673 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)
674 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val)
675 {
676 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16));
677 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE,
678 			   GENMASK(24, 16));
679 }
680 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
681 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val)
682 {
683 	le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27));
684 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC,
685 			   BIT(27));
686 }
687 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0)
688 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val)
689 {
690 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28));
691 	le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE,
692 			   GENMASK(31, 28));
693 }
694 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0)
695 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val)
696 {
697 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0));
698 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT,
699 			   GENMASK(5, 0));
700 }
701 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
702 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val)
703 {
704 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6));
705 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL,
706 			   BIT(6));
707 }
708 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
709 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val)
710 {
711 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7));
712 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL,
713 			   BIT(7));
714 }
715 #define SET_CMC_TBL_MASK_RTS_EN BIT(0)
716 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val)
717 {
718 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8));
719 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN,
720 			   BIT(8));
721 }
722 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
723 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val)
724 {
725 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9));
726 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN,
727 			   BIT(9));
728 }
729 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0)
730 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val)
731 {
732 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10));
733 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS,
734 			   GENMASK(11, 10));
735 }
736 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
737 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val)
738 {
739 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12));
740 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN,
741 			   BIT(12));
742 }
743 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0)
744 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val)
745 {
746 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13));
747 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE,
748 			   GENMASK(14, 13));
749 }
750 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0)
751 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val)
752 {
753 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16));
754 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN,
755 			   GENMASK(26, 16));
756 }
757 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
758 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val)
759 {
760 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
761 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS,
762 			   BIT(27));
763 }
764 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0)
765 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val)
766 {
767 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28));
768 	le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME,
769 			   GENMASK(31, 28));
770 }
771 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)
772 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val)
773 {
774 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0));
775 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM,
776 			   GENMASK(7, 0));
777 }
778 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0)
779 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val)
780 {
781 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8));
782 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP,
783 			   GENMASK(9, 8));
784 }
785 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0)
786 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val)
787 {
788 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16));
789 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL,
790 			   GENMASK(18, 16));
791 }
792 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0)
793 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val)
794 {
795 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19));
796 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL,
797 			   GENMASK(21, 19));
798 }
799 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0)
800 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val)
801 {
802 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22));
803 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL,
804 			   GENMASK(24, 22));
805 }
806 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0)
807 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val)
808 {
809 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25));
810 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL,
811 			   GENMASK(27, 25));
812 }
813 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0)
814 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val)
815 {
816 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28));
817 	le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE,
818 			   GENMASK(31, 28));
819 }
820 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0)
821 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val)
822 {
823 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0));
824 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID,
825 			   GENMASK(2, 0));
826 }
827 #define SET_CMC_TBL_MASK_BMC BIT(0)
828 static inline void SET_CMC_TBL_BMC(void *table, u32 val)
829 {
830 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3));
831 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC,
832 			   BIT(3));
833 }
834 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0)
835 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val)
836 {
837 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4));
838 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID,
839 			   GENMASK(7, 4));
840 }
841 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
842 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val)
843 {
844 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
845 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR,
846 			   BIT(8));
847 }
848 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0)
849 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val)
850 {
851 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9));
852 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE,
853 			   GENMASK(11, 9));
854 }
855 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
856 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val)
857 {
858 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12));
859 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM,
860 			   BIT(12));
861 }
862 #define SET_CMC_TBL_MASK_DATA_ER BIT(0)
863 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val)
864 {
865 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13));
866 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER,
867 			   BIT(13));
868 }
869 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
870 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val)
871 {
872 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14));
873 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC,
874 			   BIT(14));
875 }
876 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
877 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val)
878 {
879 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
880 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC,
881 			   BIT(15));
882 }
883 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
884 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val)
885 {
886 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16));
887 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR,
888 			   BIT(16));
889 }
890 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
891 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val)
892 {
893 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17));
894 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH,
895 			   BIT(17));
896 }
897 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
898 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val)
899 {
900 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18));
901 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR,
902 			   BIT(18));
903 }
904 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
905 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val)
906 {
907 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19));
908 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS,
909 			   BIT(19));
910 }
911 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
912 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val)
913 {
914 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20));
915 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER,
916 			   BIT(20));
917 }
918 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
919 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val)
920 {
921 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21));
922 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN,
923 			   BIT(21));
924 }
925 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
926 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val)
927 {
928 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27));
929 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD,
930 			   BIT(27));
931 }
932 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0)
933 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val)
934 {
935 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28));
936 	le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT,
937 			   GENMASK(31, 28));
938 }
939 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)
940 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val)
941 {
942 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0));
943 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE,
944 			   GENMASK(8, 0));
945 }
946 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
947 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val)
948 {
949 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12));
950 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT,
951 			   BIT(12));
952 }
953 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
954 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val)
955 {
956 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13));
957 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT,
958 			   BIT(13));
959 }
960 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0)
961 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val)
962 {
963 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16));
964 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN,
965 			   GENMASK(19, 16));
966 }
967 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0)
968 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val)
969 {
970 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20));
971 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A,
972 			   GENMASK(21, 20));
973 }
974 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0)
975 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val)
976 {
977 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22));
978 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B,
979 			   GENMASK(23, 22));
980 }
981 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0)
982 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val)
983 {
984 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24));
985 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C,
986 			   GENMASK(25, 24));
987 }
988 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0)
989 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val)
990 {
991 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26));
992 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D,
993 			   GENMASK(27, 26));
994 }
995 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
996 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val)
997 {
998 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28));
999 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A,
1000 			   BIT(28));
1001 }
1002 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
1003 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val)
1004 {
1005 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29));
1006 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B,
1007 			   BIT(29));
1008 }
1009 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
1010 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val)
1011 {
1012 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30));
1013 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C,
1014 			   BIT(30));
1015 }
1016 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
1017 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val)
1018 {
1019 	le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31));
1020 	le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D,
1021 			   BIT(31));
1022 }
1023 
1024 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0)
1025 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val)
1026 {
1027 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0));
1028 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1029 			   GENMASK(1, 0));
1030 }
1031 
1032 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val)
1033 {
1034 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2));
1035 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1036 			   GENMASK(3, 2));
1037 }
1038 
1039 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val)
1040 {
1041 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4));
1042 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1043 			   GENMASK(5, 4));
1044 }
1045 
1046 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val)
1047 {
1048 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6));
1049 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1050 			   GENMASK(7, 6));
1051 }
1052 
1053 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)
1054 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val)
1055 {
1056 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1057 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX,
1058 			   GENMASK(7, 0));
1059 }
1060 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)
1061 static inline void SET_CMC_TBL_PAID(void *table, u32 val)
1062 {
1063 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8));
1064 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID,
1065 			   GENMASK(16, 8));
1066 }
1067 #define SET_CMC_TBL_MASK_ULDL BIT(0)
1068 static inline void SET_CMC_TBL_ULDL(void *table, u32 val)
1069 {
1070 	le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17));
1071 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL,
1072 			   BIT(17));
1073 }
1074 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0)
1075 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val)
1076 {
1077 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18));
1078 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL,
1079 			   GENMASK(19, 18));
1080 }
1081 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val)
1082 {
1083 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20));
1084 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1085 			   GENMASK(21, 20));
1086 }
1087 
1088 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val)
1089 {
1090 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22));
1091 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1092 			   GENMASK(23, 22));
1093 }
1094 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0)
1095 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val)
1096 {
1097 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24));
1098 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE,
1099 			   GENMASK(27, 24));
1100 }
1101 
1102 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val)
1103 {
1104 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30));
1105 	le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1106 			   GENMASK(31, 30));
1107 }
1108 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0)
1109 static inline void SET_CMC_TBL_NC(void *table, u32 val)
1110 {
1111 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0));
1112 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC,
1113 			   GENMASK(2, 0));
1114 }
1115 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0)
1116 static inline void SET_CMC_TBL_NR(void *table, u32 val)
1117 {
1118 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3));
1119 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR,
1120 			   GENMASK(5, 3));
1121 }
1122 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0)
1123 static inline void SET_CMC_TBL_NG(void *table, u32 val)
1124 {
1125 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6));
1126 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG,
1127 			   GENMASK(7, 6));
1128 }
1129 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0)
1130 static inline void SET_CMC_TBL_CB(void *table, u32 val)
1131 {
1132 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8));
1133 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB,
1134 			   GENMASK(9, 8));
1135 }
1136 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0)
1137 static inline void SET_CMC_TBL_CS(void *table, u32 val)
1138 {
1139 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10));
1140 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS,
1141 			   GENMASK(11, 10));
1142 }
1143 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
1144 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val)
1145 {
1146 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12));
1147 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN,
1148 			   BIT(12));
1149 }
1150 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
1151 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val)
1152 {
1153 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13));
1154 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN,
1155 			   BIT(13));
1156 }
1157 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
1158 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val)
1159 {
1160 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14));
1161 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN,
1162 			   BIT(14));
1163 }
1164 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
1165 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val)
1166 {
1167 	le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15));
1168 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN,
1169 			   BIT(15));
1170 }
1171 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)
1172 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val)
1173 {
1174 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16));
1175 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE,
1176 			   GENMASK(24, 16));
1177 }
1178 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0)
1179 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val)
1180 {
1181 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25));
1182 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF,
1183 			   GENMASK(27, 25));
1184 }
1185 
1186 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val)
1187 {
1188 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28));
1189 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1190 			   GENMASK(29, 28));
1191 }
1192 
1193 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0)
1194 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val)
1195 {
1196 	le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30));
1197 	le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW,
1198 			   GENMASK(31, 30));
1199 }
1200 
1201 static inline void SET_DCTL_MACID_V1(void *table, u32 val)
1202 {
1203 	le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
1204 }
1205 
1206 static inline void SET_DCTL_OPERATION_V1(void *table, u32 val)
1207 {
1208 	le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
1209 }
1210 
1211 #define SET_DCTL_MASK_QOS_FIELD_V1 GENMASK(7, 0)
1212 static inline void SET_DCTL_QOS_FIELD_V1(void *table, u32 val)
1213 {
1214 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(7, 0));
1215 	le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_FIELD_V1,
1216 			   GENMASK(7, 0));
1217 }
1218 
1219 #define SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID GENMASK(6, 0)
1220 static inline void SET_DCTL_HW_EXSEQ_MACID_V1(void *table, u32 val)
1221 {
1222 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 8));
1223 	le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID,
1224 			   GENMASK(14, 8));
1225 }
1226 
1227 #define SET_DCTL_MASK_QOS_DATA BIT(0)
1228 static inline void SET_DCTL_QOS_DATA_V1(void *table, u32 val)
1229 {
1230 	le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
1231 	le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_DATA,
1232 			   BIT(15));
1233 }
1234 
1235 #define SET_DCTL_MASK_AES_IV_L GENMASK(15, 0)
1236 static inline void SET_DCTL_AES_IV_L_V1(void *table, u32 val)
1237 {
1238 	le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 16));
1239 	le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_AES_IV_L,
1240 			   GENMASK(31, 16));
1241 }
1242 
1243 #define SET_DCTL_MASK_AES_IV_H GENMASK(31, 0)
1244 static inline void SET_DCTL_AES_IV_H_V1(void *table, u32 val)
1245 {
1246 	le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 0));
1247 	le32p_replace_bits((__le32 *)(table) + 10, SET_DCTL_MASK_AES_IV_H,
1248 			   GENMASK(31, 0));
1249 }
1250 
1251 #define SET_DCTL_MASK_SEQ0 GENMASK(11, 0)
1252 static inline void SET_DCTL_SEQ0_V1(void *table, u32 val)
1253 {
1254 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 0));
1255 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ0,
1256 			   GENMASK(11, 0));
1257 }
1258 
1259 #define SET_DCTL_MASK_SEQ1 GENMASK(11, 0)
1260 static inline void SET_DCTL_SEQ1_V1(void *table, u32 val)
1261 {
1262 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(23, 12));
1263 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ1,
1264 			   GENMASK(23, 12));
1265 }
1266 
1267 #define SET_DCTL_MASK_AMSDU_MAX_LEN GENMASK(2, 0)
1268 static inline void SET_DCTL_AMSDU_MAX_LEN_V1(void *table, u32 val)
1269 {
1270 	le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 24));
1271 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_AMSDU_MAX_LEN,
1272 			   GENMASK(26, 24));
1273 }
1274 
1275 #define SET_DCTL_MASK_STA_AMSDU_EN BIT(0)
1276 static inline void SET_DCTL_STA_AMSDU_EN_V1(void *table, u32 val)
1277 {
1278 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
1279 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_STA_AMSDU_EN,
1280 			   BIT(27));
1281 }
1282 
1283 #define SET_DCTL_MASK_CHKSUM_OFLD_EN BIT(0)
1284 static inline void SET_DCTL_CHKSUM_OFLD_EN_V1(void *table, u32 val)
1285 {
1286 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(28));
1287 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_CHKSUM_OFLD_EN,
1288 			   BIT(28));
1289 }
1290 
1291 #define SET_DCTL_MASK_WITH_LLC BIT(0)
1292 static inline void SET_DCTL_WITH_LLC_V1(void *table, u32 val)
1293 {
1294 	le32p_replace_bits((__le32 *)(table) + 3, val, BIT(29));
1295 	le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_WITH_LLC,
1296 			   BIT(29));
1297 }
1298 
1299 #define SET_DCTL_MASK_SEQ2 GENMASK(11, 0)
1300 static inline void SET_DCTL_SEQ2_V1(void *table, u32 val)
1301 {
1302 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(11, 0));
1303 	le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ2,
1304 			   GENMASK(11, 0));
1305 }
1306 
1307 #define SET_DCTL_MASK_SEQ3 GENMASK(11, 0)
1308 static inline void SET_DCTL_SEQ3_V1(void *table, u32 val)
1309 {
1310 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(23, 12));
1311 	le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ3,
1312 			   GENMASK(23, 12));
1313 }
1314 
1315 #define SET_DCTL_MASK_TGT_IND GENMASK(3, 0)
1316 static inline void SET_DCTL_TGT_IND_V1(void *table, u32 val)
1317 {
1318 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 24));
1319 	le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND,
1320 			   GENMASK(27, 24));
1321 }
1322 
1323 #define SET_DCTL_MASK_TGT_IND_EN BIT(0)
1324 static inline void SET_DCTL_TGT_IND_EN_V1(void *table, u32 val)
1325 {
1326 	le32p_replace_bits((__le32 *)(table) + 4, val, BIT(28));
1327 	le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND_EN,
1328 			   BIT(28));
1329 }
1330 
1331 #define SET_DCTL_MASK_HTC_LB GENMASK(2, 0)
1332 static inline void SET_DCTL_HTC_LB_V1(void *table, u32 val)
1333 {
1334 	le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 29));
1335 	le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_HTC_LB,
1336 			   GENMASK(31, 29));
1337 }
1338 
1339 #define SET_DCTL_MASK_MHDR_LEN GENMASK(4, 0)
1340 static inline void SET_DCTL_MHDR_LEN_V1(void *table, u32 val)
1341 {
1342 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(4, 0));
1343 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_MHDR_LEN,
1344 			   GENMASK(4, 0));
1345 }
1346 
1347 #define SET_DCTL_MASK_VLAN_TAG_VALID BIT(0)
1348 static inline void SET_DCTL_VLAN_TAG_VALID_V1(void *table, u32 val)
1349 {
1350 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(5));
1351 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_VALID,
1352 			   BIT(5));
1353 }
1354 
1355 #define SET_DCTL_MASK_VLAN_TAG_SEL GENMASK(1, 0)
1356 static inline void SET_DCTL_VLAN_TAG_SEL_V1(void *table, u32 val)
1357 {
1358 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 6));
1359 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_SEL,
1360 			   GENMASK(7, 6));
1361 }
1362 
1363 #define SET_DCTL_MASK_HTC_ORDER BIT(0)
1364 static inline void SET_DCTL_HTC_ORDER_V1(void *table, u32 val)
1365 {
1366 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
1367 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_HTC_ORDER,
1368 			   BIT(8));
1369 }
1370 
1371 #define SET_DCTL_MASK_SEC_KEY_ID GENMASK(1, 0)
1372 static inline void SET_DCTL_SEC_KEY_ID_V1(void *table, u32 val)
1373 {
1374 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(10, 9));
1375 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_KEY_ID,
1376 			   GENMASK(10, 9));
1377 }
1378 
1379 #define SET_DCTL_MASK_WAPI BIT(0)
1380 static inline void SET_DCTL_WAPI_V1(void *table, u32 val)
1381 {
1382 	le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
1383 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_WAPI,
1384 			   BIT(15));
1385 }
1386 
1387 #define SET_DCTL_MASK_SEC_ENT_MODE GENMASK(1, 0)
1388 static inline void SET_DCTL_SEC_ENT_MODE_V1(void *table, u32 val)
1389 {
1390 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(17, 16));
1391 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENT_MODE,
1392 			   GENMASK(17, 16));
1393 }
1394 
1395 #define SET_DCTL_MASK_SEC_ENTX_KEYID GENMASK(1, 0)
1396 static inline void SET_DCTL_SEC_ENT0_KEYID_V1(void *table, u32 val)
1397 {
1398 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(19, 18));
1399 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1400 			   GENMASK(19, 18));
1401 }
1402 
1403 static inline void SET_DCTL_SEC_ENT1_KEYID_V1(void *table, u32 val)
1404 {
1405 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(21, 20));
1406 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1407 			   GENMASK(21, 20));
1408 }
1409 
1410 static inline void SET_DCTL_SEC_ENT2_KEYID_V1(void *table, u32 val)
1411 {
1412 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(23, 22));
1413 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1414 			   GENMASK(23, 22));
1415 }
1416 
1417 static inline void SET_DCTL_SEC_ENT3_KEYID_V1(void *table, u32 val)
1418 {
1419 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(25, 24));
1420 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1421 			   GENMASK(25, 24));
1422 }
1423 
1424 static inline void SET_DCTL_SEC_ENT4_KEYID_V1(void *table, u32 val)
1425 {
1426 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(27, 26));
1427 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1428 			   GENMASK(27, 26));
1429 }
1430 
1431 static inline void SET_DCTL_SEC_ENT5_KEYID_V1(void *table, u32 val)
1432 {
1433 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(29, 28));
1434 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1435 			   GENMASK(29, 28));
1436 }
1437 
1438 static inline void SET_DCTL_SEC_ENT6_KEYID_V1(void *table, u32 val)
1439 {
1440 	le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 30));
1441 	le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID,
1442 			   GENMASK(31, 30));
1443 }
1444 
1445 #define SET_DCTL_MASK_SEC_ENT_VALID GENMASK(7, 0)
1446 static inline void SET_DCTL_SEC_ENT_VALID_V1(void *table, u32 val)
1447 {
1448 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(7, 0));
1449 	le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENT_VALID,
1450 			   GENMASK(7, 0));
1451 }
1452 
1453 #define SET_DCTL_MASK_SEC_ENTX GENMASK(7, 0)
1454 static inline void SET_DCTL_SEC_ENT0_V1(void *table, u32 val)
1455 {
1456 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(15, 8));
1457 	le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1458 			   GENMASK(15, 8));
1459 }
1460 
1461 static inline void SET_DCTL_SEC_ENT1_V1(void *table, u32 val)
1462 {
1463 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 16));
1464 	le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1465 			   GENMASK(23, 16));
1466 }
1467 
1468 static inline void SET_DCTL_SEC_ENT2_V1(void *table, u32 val)
1469 {
1470 	le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(31, 24));
1471 	le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX,
1472 			   GENMASK(31, 24));
1473 }
1474 
1475 static inline void SET_DCTL_SEC_ENT3_V1(void *table, u32 val)
1476 {
1477 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1478 	le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1479 			   GENMASK(7, 0));
1480 }
1481 
1482 static inline void SET_DCTL_SEC_ENT4_V1(void *table, u32 val)
1483 {
1484 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(15, 8));
1485 	le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1486 			   GENMASK(15, 8));
1487 }
1488 
1489 static inline void SET_DCTL_SEC_ENT5_V1(void *table, u32 val)
1490 {
1491 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 16));
1492 	le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1493 			   GENMASK(23, 16));
1494 }
1495 
1496 static inline void SET_DCTL_SEC_ENT6_V1(void *table, u32 val)
1497 {
1498 	le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 24));
1499 	le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX,
1500 			   GENMASK(31, 24));
1501 }
1502 
1503 static inline void SET_BCN_UPD_PORT(void *h2c, u32 val)
1504 {
1505 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1506 }
1507 
1508 static inline void SET_BCN_UPD_MBSSID(void *h2c, u32 val)
1509 {
1510 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1511 }
1512 
1513 static inline void SET_BCN_UPD_BAND(void *h2c, u32 val)
1514 {
1515 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1516 }
1517 
1518 static inline void SET_BCN_UPD_GRP_IE_OFST(void *h2c, u32 val)
1519 {
1520 	le32p_replace_bits((__le32 *)h2c, (val - 24) | BIT(7), GENMASK(31, 24));
1521 }
1522 
1523 static inline void SET_BCN_UPD_MACID(void *h2c, u32 val)
1524 {
1525 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1526 }
1527 
1528 static inline void SET_BCN_UPD_SSN_SEL(void *h2c, u32 val)
1529 {
1530 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(9, 8));
1531 }
1532 
1533 static inline void SET_BCN_UPD_SSN_MODE(void *h2c, u32 val)
1534 {
1535 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(11, 10));
1536 }
1537 
1538 static inline void SET_BCN_UPD_RATE(void *h2c, u32 val)
1539 {
1540 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(20, 12));
1541 }
1542 
1543 static inline void SET_BCN_UPD_TXPWR(void *h2c, u32 val)
1544 {
1545 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(23, 21));
1546 }
1547 
1548 static inline void SET_BCN_UPD_TXINFO_CTRL_EN(void *h2c, u32 val)
1549 {
1550 	le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(0));
1551 }
1552 
1553 static inline void SET_BCN_UPD_NTX_PATH_EN(void *h2c, u32 val)
1554 {
1555 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(4, 1));
1556 }
1557 
1558 static inline void SET_BCN_UPD_PATH_MAP_A(void *h2c, u32 val)
1559 {
1560 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(6, 5));
1561 }
1562 
1563 static inline void SET_BCN_UPD_PATH_MAP_B(void *h2c, u32 val)
1564 {
1565 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(8, 7));
1566 }
1567 
1568 static inline void SET_BCN_UPD_PATH_MAP_C(void *h2c, u32 val)
1569 {
1570 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(10, 9));
1571 }
1572 
1573 static inline void SET_BCN_UPD_PATH_MAP_D(void *h2c, u32 val)
1574 {
1575 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(12, 11));
1576 }
1577 
1578 static inline void SET_BCN_UPD_PATH_ANTSEL_A(void *h2c, u32 val)
1579 {
1580 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  BIT(13));
1581 }
1582 
1583 static inline void SET_BCN_UPD_PATH_ANTSEL_B(void *h2c, u32 val)
1584 {
1585 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  BIT(14));
1586 }
1587 
1588 static inline void SET_BCN_UPD_PATH_ANTSEL_C(void *h2c, u32 val)
1589 {
1590 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  BIT(15));
1591 }
1592 
1593 static inline void SET_BCN_UPD_PATH_ANTSEL_D(void *h2c, u32 val)
1594 {
1595 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  BIT(16));
1596 }
1597 
1598 static inline void SET_BCN_UPD_CSA_OFST(void *h2c, u32 val)
1599 {
1600 	le32p_replace_bits((__le32 *)(h2c) + 2, val,  GENMASK(31, 17));
1601 }
1602 
1603 static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val)
1604 {
1605 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1606 }
1607 
1608 static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val)
1609 {
1610 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8));
1611 }
1612 
1613 static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val)
1614 {
1615 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10));
1616 }
1617 
1618 static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val)
1619 {
1620 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13));
1621 }
1622 
1623 static inline void SET_JOININFO_MACID(void *h2c, u32 val)
1624 {
1625 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1626 }
1627 
1628 static inline void SET_JOININFO_OP(void *h2c, u32 val)
1629 {
1630 	le32p_replace_bits((__le32 *)h2c, val, BIT(8));
1631 }
1632 
1633 static inline void SET_JOININFO_BAND(void *h2c, u32 val)
1634 {
1635 	le32p_replace_bits((__le32 *)h2c, val, BIT(9));
1636 }
1637 
1638 static inline void SET_JOININFO_WMM(void *h2c, u32 val)
1639 {
1640 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10));
1641 }
1642 
1643 static inline void SET_JOININFO_TGR(void *h2c, u32 val)
1644 {
1645 	le32p_replace_bits((__le32 *)h2c, val, BIT(12));
1646 }
1647 
1648 static inline void SET_JOININFO_ISHESTA(void *h2c, u32 val)
1649 {
1650 	le32p_replace_bits((__le32 *)h2c, val, BIT(13));
1651 }
1652 
1653 static inline void SET_JOININFO_DLBW(void *h2c, u32 val)
1654 {
1655 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14));
1656 }
1657 
1658 static inline void SET_JOININFO_TF_MAC_PAD(void *h2c, u32 val)
1659 {
1660 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16));
1661 }
1662 
1663 static inline void SET_JOININFO_DL_T_PE(void *h2c, u32 val)
1664 {
1665 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18));
1666 }
1667 
1668 static inline void SET_JOININFO_PORT_ID(void *h2c, u32 val)
1669 {
1670 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21));
1671 }
1672 
1673 static inline void SET_JOININFO_NET_TYPE(void *h2c, u32 val)
1674 {
1675 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24));
1676 }
1677 
1678 static inline void SET_JOININFO_WIFI_ROLE(void *h2c, u32 val)
1679 {
1680 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26));
1681 }
1682 
1683 static inline void SET_JOININFO_SELF_ROLE(void *h2c, u32 val)
1684 {
1685 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30));
1686 }
1687 
1688 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val)
1689 {
1690 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1691 }
1692 
1693 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val)
1694 {
1695 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1696 }
1697 
1698 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val)
1699 {
1700 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1701 }
1702 
1703 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val)
1704 {
1705 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1706 }
1707 
1708 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val)
1709 {
1710 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1711 }
1712 
1713 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val)
1714 {
1715 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1716 }
1717 
1718 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val)
1719 {
1720 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1721 }
1722 
1723 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val)
1724 {
1725 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1726 }
1727 
1728 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val)
1729 {
1730 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
1731 }
1732 
1733 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val)
1734 {
1735 	le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0));
1736 }
1737 
1738 static inline void SET_BA_CAM_VALID(void *h2c, u32 val)
1739 {
1740 	le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1741 }
1742 
1743 static inline void SET_BA_CAM_INIT_REQ(void *h2c, u32 val)
1744 {
1745 	le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1746 }
1747 
1748 static inline void SET_BA_CAM_ENTRY_IDX(void *h2c, u32 val)
1749 {
1750 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2));
1751 }
1752 
1753 static inline void SET_BA_CAM_TID(void *h2c, u32 val)
1754 {
1755 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4));
1756 }
1757 
1758 static inline void SET_BA_CAM_MACID(void *h2c, u32 val)
1759 {
1760 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1761 }
1762 
1763 static inline void SET_BA_CAM_BMAP_SIZE(void *h2c, u32 val)
1764 {
1765 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1766 }
1767 
1768 static inline void SET_BA_CAM_SSN(void *h2c, u32 val)
1769 {
1770 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20));
1771 }
1772 
1773 static inline void SET_BA_CAM_UID(void *h2c, u32 val)
1774 {
1775 	le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(7, 0));
1776 }
1777 
1778 static inline void SET_BA_CAM_STD_EN(void *h2c, u32 val)
1779 {
1780 	le32p_replace_bits((__le32 *)h2c + 1, val, BIT(8));
1781 }
1782 
1783 static inline void SET_BA_CAM_BAND(void *h2c, u32 val)
1784 {
1785 	le32p_replace_bits((__le32 *)h2c + 1, val, BIT(9));
1786 }
1787 
1788 static inline void SET_BA_CAM_ENTRY_IDX_V1(void *h2c, u32 val)
1789 {
1790 	le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 28));
1791 }
1792 
1793 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val)
1794 {
1795 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1796 }
1797 
1798 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val)
1799 {
1800 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1801 }
1802 
1803 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val)
1804 {
1805 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1806 }
1807 
1808 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val)
1809 {
1810 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20));
1811 }
1812 
1813 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val)
1814 {
1815 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1816 }
1817 
1818 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val)
1819 {
1820 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0));
1821 }
1822 
1823 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val)
1824 {
1825 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1));
1826 }
1827 
1828 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val)
1829 {
1830 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2));
1831 }
1832 
1833 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val)
1834 {
1835 	le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3));
1836 }
1837 
1838 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val)
1839 {
1840 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1841 }
1842 
1843 static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val)
1844 {
1845 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0));
1846 }
1847 
1848 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val)
1849 {
1850 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
1851 }
1852 
1853 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val)
1854 {
1855 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
1856 }
1857 
1858 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val)
1859 {
1860 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
1861 }
1862 
1863 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val)
1864 {
1865 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
1866 }
1867 
1868 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val)
1869 {
1870 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0));
1871 }
1872 
1873 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val)
1874 {
1875 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8));
1876 }
1877 
1878 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val)
1879 {
1880 	le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
1881 }
1882 
1883 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val)
1884 {
1885 	le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
1886 }
1887 
1888 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val)
1889 {
1890 	le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
1891 }
1892 
1893 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val)
1894 {
1895 	le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0));
1896 }
1897 
1898 static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val)
1899 {
1900 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0));
1901 }
1902 
1903 static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val)
1904 {
1905 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1906 }
1907 
1908 static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val)
1909 {
1910 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16));
1911 }
1912 
1913 static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val)
1914 {
1915 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1916 }
1917 
1918 static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val)
1919 {
1920 	le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1921 }
1922 
1923 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val)
1924 {
1925 	le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1926 }
1927 
1928 static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val)
1929 {
1930 	le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1931 }
1932 
1933 static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val)
1934 {
1935 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1936 }
1937 
1938 static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val)
1939 {
1940 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1941 }
1942 
1943 static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val)
1944 {
1945 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1946 }
1947 
1948 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val)
1949 {
1950 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1951 }
1952 
1953 static inline void RTW89_SET_WOW_GLOBAL_ENABLE(void *h2c, u32 val)
1954 {
1955 	le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1956 }
1957 
1958 static inline void RTW89_SET_WOW_GLOBAL_DROP_ALL_PKT(void *h2c, u32 val)
1959 {
1960 	le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1961 }
1962 
1963 static inline void RTW89_SET_WOW_GLOBAL_RX_PARSE_AFTER_WAKE(void *h2c, u32 val)
1964 {
1965 	le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1966 }
1967 
1968 static inline void RTW89_SET_WOW_GLOBAL_WAKE_BAR_PULLED(void *h2c, u32 val)
1969 {
1970 	le32p_replace_bits((__le32 *)h2c, val, BIT(3));
1971 }
1972 
1973 static inline void RTW89_SET_WOW_GLOBAL_MAC_ID(void *h2c, u32 val)
1974 {
1975 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1976 }
1977 
1978 static inline void RTW89_SET_WOW_GLOBAL_PAIRWISE_SEC_ALGO(void *h2c, u32 val)
1979 {
1980 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1981 }
1982 
1983 static inline void RTW89_SET_WOW_GLOBAL_GROUP_SEC_ALGO(void *h2c, u32 val)
1984 {
1985 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1986 }
1987 
1988 static inline void RTW89_SET_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT(void *h2c, u32 val)
1989 {
1990 	le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
1991 }
1992 
1993 static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val)
1994 {
1995 	le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1996 }
1997 
1998 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val)
1999 {
2000 	le32p_replace_bits((__le32 *)h2c, val, BIT(1));
2001 }
2002 
2003 static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val)
2004 {
2005 	le32p_replace_bits((__le32 *)h2c, val, BIT(2));
2006 }
2007 
2008 static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val)
2009 {
2010 	le32p_replace_bits((__le32 *)h2c, val, BIT(3));
2011 }
2012 
2013 static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val)
2014 {
2015 	le32p_replace_bits((__le32 *)h2c, val, BIT(4));
2016 }
2017 
2018 static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val)
2019 {
2020 	le32p_replace_bits((__le32 *)h2c, val, BIT(5));
2021 }
2022 
2023 static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val)
2024 {
2025 	le32p_replace_bits((__le32 *)h2c, val, BIT(6));
2026 }
2027 
2028 static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val)
2029 {
2030 	le32p_replace_bits((__le32 *)h2c, val, BIT(7));
2031 }
2032 
2033 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val)
2034 {
2035 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
2036 }
2037 
2038 static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val)
2039 {
2040 	le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2041 }
2042 
2043 static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val)
2044 {
2045 	le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1));
2046 }
2047 
2048 static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val)
2049 {
2050 	le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0));
2051 }
2052 
2053 static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val)
2054 {
2055 	le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0));
2056 }
2057 
2058 static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val)
2059 {
2060 	le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0));
2061 }
2062 
2063 static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val)
2064 {
2065 	le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0));
2066 }
2067 
2068 static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val)
2069 {
2070 	le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0));
2071 }
2072 
2073 static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val)
2074 {
2075 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22));
2076 }
2077 
2078 static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val)
2079 {
2080 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23));
2081 }
2082 
2083 static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val)
2084 {
2085 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24));
2086 }
2087 
2088 static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val)
2089 {
2090 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25));
2091 }
2092 
2093 static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val)
2094 {
2095 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26));
2096 }
2097 
2098 static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val)
2099 {
2100 	le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31));
2101 }
2102 
2103 enum rtw89_btc_btf_h2c_class {
2104 	BTFC_SET = 0x10,
2105 	BTFC_GET = 0x11,
2106 	BTFC_FW_EVENT = 0x12,
2107 };
2108 
2109 enum rtw89_btc_btf_set {
2110 	SET_REPORT_EN = 0x0,
2111 	SET_SLOT_TABLE,
2112 	SET_MREG_TABLE,
2113 	SET_CX_POLICY,
2114 	SET_GPIO_DBG,
2115 	SET_DRV_INFO,
2116 	SET_DRV_EVENT,
2117 	SET_BT_WREG_ADDR,
2118 	SET_BT_WREG_VAL,
2119 	SET_BT_RREG_ADDR,
2120 	SET_BT_WL_CH_INFO,
2121 	SET_BT_INFO_REPORT,
2122 	SET_BT_IGNORE_WLAN_ACT,
2123 	SET_BT_TX_PWR,
2124 	SET_BT_LNA_CONSTRAIN,
2125 	SET_BT_GOLDEN_RX_RANGE,
2126 	SET_BT_PSD_REPORT,
2127 	SET_H2C_TEST,
2128 	SET_MAX1,
2129 };
2130 
2131 enum rtw89_btc_cxdrvinfo {
2132 	CXDRVINFO_INIT = 0,
2133 	CXDRVINFO_ROLE,
2134 	CXDRVINFO_DBCC,
2135 	CXDRVINFO_SMAP,
2136 	CXDRVINFO_RFK,
2137 	CXDRVINFO_RUN,
2138 	CXDRVINFO_CTRL,
2139 	CXDRVINFO_SCAN,
2140 	CXDRVINFO_TRX,  /* WL traffic to WL fw */
2141 	CXDRVINFO_MAX,
2142 };
2143 
2144 enum rtw89_scan_mode {
2145 	RTW89_SCAN_IMMEDIATE,
2146 };
2147 
2148 enum rtw89_scan_type {
2149 	RTW89_SCAN_ONCE,
2150 };
2151 
2152 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val)
2153 {
2154 	u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0));
2155 }
2156 
2157 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val)
2158 {
2159 	u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0));
2160 }
2161 
2162 struct rtw89_h2c_cxhdr {
2163 	u8 type;
2164 	u8 len;
2165 } __packed;
2166 
2167 #define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr)
2168 
2169 struct rtw89_h2c_cxinit {
2170 	struct rtw89_h2c_cxhdr hdr;
2171 	u8 ant_type;
2172 	u8 ant_num;
2173 	u8 ant_iso;
2174 	u8 ant_info;
2175 	u8 mod_rfe;
2176 	u8 mod_cv;
2177 	u8 mod_info;
2178 	u8 mod_adie_kt;
2179 	u8 wl_gch;
2180 	u8 info;
2181 	u8 rsvd;
2182 	u8 rsvd1;
2183 } __packed;
2184 
2185 #define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0)
2186 #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1)
2187 #define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2)
2188 #define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4)
2189 
2190 #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0)
2191 #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1)
2192 #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2)
2193 #define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3)
2194 
2195 #define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0)
2196 #define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1)
2197 #define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2)
2198 #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3)
2199 #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4)
2200 
2201 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val)
2202 {
2203 	u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0));
2204 }
2205 
2206 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val)
2207 {
2208 	u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0));
2209 }
2210 
2211 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val)
2212 {
2213 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0));
2214 }
2215 
2216 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val)
2217 {
2218 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1));
2219 }
2220 
2221 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val)
2222 {
2223 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2));
2224 }
2225 
2226 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val)
2227 {
2228 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3));
2229 }
2230 
2231 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val)
2232 {
2233 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4));
2234 }
2235 
2236 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val)
2237 {
2238 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5));
2239 }
2240 
2241 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val)
2242 {
2243 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6));
2244 }
2245 
2246 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val)
2247 {
2248 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7));
2249 }
2250 
2251 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val)
2252 {
2253 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8));
2254 }
2255 
2256 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val)
2257 {
2258 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9));
2259 }
2260 
2261 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val)
2262 {
2263 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10));
2264 }
2265 
2266 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val)
2267 {
2268 	le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11));
2269 }
2270 
2271 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset)
2272 {
2273 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2274 }
2275 
2276 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset)
2277 {
2278 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2279 }
2280 
2281 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset)
2282 {
2283 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2284 }
2285 
2286 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset)
2287 {
2288 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2289 }
2290 
2291 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset)
2292 {
2293 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2294 }
2295 
2296 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset)
2297 {
2298 	u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2299 }
2300 
2301 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset)
2302 {
2303 	u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2304 }
2305 
2306 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset)
2307 {
2308 	u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2309 }
2310 
2311 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset)
2312 {
2313 	u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2314 }
2315 
2316 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset)
2317 {
2318 	le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0));
2319 }
2320 
2321 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset)
2322 {
2323 	le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0));
2324 }
2325 
2326 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset)
2327 {
2328 	le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0));
2329 }
2330 
2331 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset)
2332 {
2333 	le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0));
2334 }
2335 
2336 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset)
2337 {
2338 	le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0));
2339 }
2340 
2341 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset)
2342 {
2343 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2344 }
2345 
2346 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset)
2347 {
2348 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2349 }
2350 
2351 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset)
2352 {
2353 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2354 }
2355 
2356 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset)
2357 {
2358 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2359 }
2360 
2361 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset)
2362 {
2363 	u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2364 }
2365 
2366 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset)
2367 {
2368 	u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2369 }
2370 
2371 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset)
2372 {
2373 	u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2374 }
2375 
2376 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset)
2377 {
2378 	u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2379 }
2380 
2381 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset)
2382 {
2383 	u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2384 }
2385 
2386 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset)
2387 {
2388 	le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0));
2389 }
2390 
2391 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset)
2392 {
2393 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0));
2394 }
2395 
2396 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset)
2397 {
2398 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0));
2399 }
2400 
2401 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset)
2402 {
2403 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0));
2404 }
2405 
2406 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset)
2407 {
2408 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1));
2409 }
2410 
2411 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset)
2412 {
2413 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2));
2414 }
2415 
2416 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset)
2417 {
2418 	le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4));
2419 }
2420 
2421 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val)
2422 {
2423 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0));
2424 }
2425 
2426 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val)
2427 {
2428 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1));
2429 }
2430 
2431 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val)
2432 {
2433 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2));
2434 }
2435 
2436 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val)
2437 {
2438 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3));
2439 }
2440 
2441 static inline void RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val)
2442 {
2443 	u8p_replace_bits((u8 *)cmd + 2, val, GENMASK(7, 0));
2444 }
2445 
2446 static inline void RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val)
2447 {
2448 	u8p_replace_bits((u8 *)cmd + 3, val, GENMASK(7, 0));
2449 }
2450 
2451 static inline void RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val)
2452 {
2453 	u8p_replace_bits((u8 *)cmd + 4, val, GENMASK(7, 0));
2454 }
2455 
2456 static inline void RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val)
2457 {
2458 	u8p_replace_bits((u8 *)cmd + 5, val, GENMASK(7, 0));
2459 }
2460 
2461 static inline void RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val)
2462 {
2463 	u8p_replace_bits((u8 *)cmd + 6, val, GENMASK(7, 0));
2464 }
2465 
2466 static inline void RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val)
2467 {
2468 	u8p_replace_bits((u8 *)cmd + 7, val, GENMASK(7, 0));
2469 }
2470 
2471 static inline void RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val)
2472 {
2473 	u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0));
2474 }
2475 
2476 static inline void RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val)
2477 {
2478 	u8p_replace_bits((u8 *)cmd + 9, val, GENMASK(7, 0));
2479 }
2480 
2481 static inline void RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val)
2482 {
2483 	u8p_replace_bits((u8 *)cmd + 10, val, GENMASK(7, 0));
2484 }
2485 
2486 static inline void RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val)
2487 {
2488 	u8p_replace_bits((u8 *)cmd + 11, val, GENMASK(7, 0));
2489 }
2490 
2491 static inline void RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val)
2492 {
2493 	u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0));
2494 }
2495 
2496 static inline void RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val)
2497 {
2498 	u8p_replace_bits((u8 *)cmd + 13, val, GENMASK(7, 0));
2499 }
2500 
2501 static inline void RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val)
2502 {
2503 	le16p_replace_bits((__le16 *)((u8 *)cmd + 14), val, GENMASK(15, 0));
2504 }
2505 
2506 static inline void RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val)
2507 {
2508 	le16p_replace_bits((__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0));
2509 }
2510 
2511 static inline void RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val)
2512 {
2513 	le32p_replace_bits((__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0));
2514 }
2515 
2516 static inline void RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val)
2517 {
2518 	le32p_replace_bits((__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0));
2519 }
2520 
2521 static inline void RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val)
2522 {
2523 	le32p_replace_bits((__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0));
2524 }
2525 
2526 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val)
2527 {
2528 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0));
2529 }
2530 
2531 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val)
2532 {
2533 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2));
2534 }
2535 
2536 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val)
2537 {
2538 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6));
2539 }
2540 
2541 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val)
2542 {
2543 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8));
2544 }
2545 
2546 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val)
2547 {
2548 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10));
2549 }
2550 
2551 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val)
2552 {
2553 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2554 }
2555 
2556 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val)
2557 {
2558 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8));
2559 }
2560 
2561 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val)
2562 {
2563 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16));
2564 }
2565 
2566 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_NUM(void *cmd, u32 val)
2567 {
2568 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2569 }
2570 
2571 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_SIZE(void *cmd, u32 val)
2572 {
2573 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8));
2574 }
2575 
2576 static inline void RTW89_SET_FWCMD_CHINFO_PERIOD(void *cmd, u32 val)
2577 {
2578 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2579 }
2580 
2581 static inline void RTW89_SET_FWCMD_CHINFO_DWELL(void *cmd, u32 val)
2582 {
2583 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8));
2584 }
2585 
2586 static inline void RTW89_SET_FWCMD_CHINFO_CENTER_CH(void *cmd, u32 val)
2587 {
2588 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 16));
2589 }
2590 
2591 static inline void RTW89_SET_FWCMD_CHINFO_PRI_CH(void *cmd, u32 val)
2592 {
2593 	le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 24));
2594 }
2595 
2596 static inline void RTW89_SET_FWCMD_CHINFO_BW(void *cmd, u32 val)
2597 {
2598 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(2, 0));
2599 }
2600 
2601 static inline void RTW89_SET_FWCMD_CHINFO_ACTION(void *cmd, u32 val)
2602 {
2603 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 3));
2604 }
2605 
2606 static inline void RTW89_SET_FWCMD_CHINFO_NUM_PKT(void *cmd, u32 val)
2607 {
2608 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(11, 8));
2609 }
2610 
2611 static inline void RTW89_SET_FWCMD_CHINFO_TX(void *cmd, u32 val)
2612 {
2613 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(12));
2614 }
2615 
2616 static inline void RTW89_SET_FWCMD_CHINFO_PAUSE_DATA(void *cmd, u32 val)
2617 {
2618 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(13));
2619 }
2620 
2621 static inline void RTW89_SET_FWCMD_CHINFO_BAND(void *cmd, u32 val)
2622 {
2623 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 14));
2624 }
2625 
2626 static inline void RTW89_SET_FWCMD_CHINFO_PKT_ID(void *cmd, u32 val)
2627 {
2628 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16));
2629 }
2630 
2631 static inline void RTW89_SET_FWCMD_CHINFO_DFS(void *cmd, u32 val)
2632 {
2633 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(24));
2634 }
2635 
2636 static inline void RTW89_SET_FWCMD_CHINFO_TX_NULL(void *cmd, u32 val)
2637 {
2638 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(25));
2639 }
2640 
2641 static inline void RTW89_SET_FWCMD_CHINFO_RANDOM(void *cmd, u32 val)
2642 {
2643 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(26));
2644 }
2645 
2646 static inline void RTW89_SET_FWCMD_CHINFO_CFG_TX(void *cmd, u32 val)
2647 {
2648 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(27));
2649 }
2650 
2651 static inline void RTW89_SET_FWCMD_CHINFO_PKT0(void *cmd, u32 val)
2652 {
2653 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(7, 0));
2654 }
2655 
2656 static inline void RTW89_SET_FWCMD_CHINFO_PKT1(void *cmd, u32 val)
2657 {
2658 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 8));
2659 }
2660 
2661 static inline void RTW89_SET_FWCMD_CHINFO_PKT2(void *cmd, u32 val)
2662 {
2663 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16));
2664 }
2665 
2666 static inline void RTW89_SET_FWCMD_CHINFO_PKT3(void *cmd, u32 val)
2667 {
2668 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(31, 24));
2669 }
2670 
2671 static inline void RTW89_SET_FWCMD_CHINFO_PKT4(void *cmd, u32 val)
2672 {
2673 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(7, 0));
2674 }
2675 
2676 static inline void RTW89_SET_FWCMD_CHINFO_PKT5(void *cmd, u32 val)
2677 {
2678 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(15, 8));
2679 }
2680 
2681 static inline void RTW89_SET_FWCMD_CHINFO_PKT6(void *cmd, u32 val)
2682 {
2683 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(23, 16));
2684 }
2685 
2686 static inline void RTW89_SET_FWCMD_CHINFO_PKT7(void *cmd, u32 val)
2687 {
2688 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 24));
2689 }
2690 
2691 static inline void RTW89_SET_FWCMD_CHINFO_POWER_IDX(void *cmd, u32 val)
2692 {
2693 	le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(15, 0));
2694 }
2695 
2696 struct rtw89_h2c_scanofld {
2697 	__le32 w0;
2698 	__le32 w1;
2699 	__le32 w2;
2700 	__le32 tsf_high;
2701 	__le32 tsf_low;
2702 	__le32 w5;
2703 	__le32 w6;
2704 } __packed;
2705 
2706 #define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0)
2707 #define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8)
2708 #define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16)
2709 #define RTW89_H2C_SCANOFLD_W0_BAND BIT(19)
2710 #define RTW89_H2C_SCANOFLD_W0_OPERATION GENMASK(21, 20)
2711 #define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND GENMASK(23, 22)
2712 #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0)
2713 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1)
2714 #define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2)
2715 #define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE GENMASK(4, 3)
2716 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5)
2717 #define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8)
2718 #define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16)
2719 #define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24)
2720 #define RTW89_H2C_SCANOFLD_W2_NORM_PD GENMASK(15, 0)
2721 #define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16)
2722 
2723 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val)
2724 {
2725 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2726 }
2727 
2728 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val)
2729 {
2730 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8));
2731 }
2732 
2733 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val)
2734 {
2735 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12));
2736 }
2737 
2738 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val)
2739 {
2740 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16));
2741 }
2742 
2743 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val)
2744 {
2745 	le32p_replace_bits((__le32 *)cmd, val, BIT(20));
2746 }
2747 
2748 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val)
2749 {
2750 	le32p_replace_bits((__le32 *)cmd, val, BIT(21));
2751 }
2752 
2753 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val)
2754 {
2755 	*((__le32 *)cmd + 1) = val;
2756 }
2757 
2758 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val)
2759 {
2760 	*((__le32 *)cmd + 2) = val;
2761 }
2762 
2763 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val)
2764 {
2765 	*((__le32 *)cmd + 3) = val;
2766 }
2767 
2768 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val)
2769 {
2770 	le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0));
2771 }
2772 
2773 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val)
2774 {
2775 	u8 ctwnd;
2776 
2777 	if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT))
2778 		return;
2779 	ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val);
2780 	le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8));
2781 }
2782 
2783 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val)
2784 {
2785 	le32p_replace_bits((__le32 *)cmd, val, BIT(0));
2786 }
2787 
2788 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val)
2789 {
2790 	le32p_replace_bits((__le32 *)cmd, val, BIT(1));
2791 }
2792 
2793 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val)
2794 {
2795 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2));
2796 }
2797 
2798 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val)
2799 {
2800 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16));
2801 }
2802 
2803 enum rtw89_fw_mcc_c2h_rpt_cfg {
2804 	RTW89_FW_MCC_C2H_RPT_OFF	= 0,
2805 	RTW89_FW_MCC_C2H_RPT_FAIL_ONLY	= 1,
2806 	RTW89_FW_MCC_C2H_RPT_ALL	= 2,
2807 };
2808 
2809 struct rtw89_fw_mcc_add_req {
2810 	u8 macid;
2811 	u8 central_ch_seg0;
2812 	u8 central_ch_seg1;
2813 	u8 primary_ch;
2814 	enum rtw89_bandwidth bandwidth: 4;
2815 	u32 group: 2;
2816 	u32 c2h_rpt: 2;
2817 	u32 dis_tx_null: 1;
2818 	u32 dis_sw_retry: 1;
2819 	u32 in_curr_ch: 1;
2820 	u32 sw_retry_count: 3;
2821 	u32 tx_null_early: 4;
2822 	u32 btc_in_2g: 1;
2823 	u32 pta_en: 1;
2824 	u32 rfk_by_pass: 1;
2825 	u32 ch_band_type: 2;
2826 	u32 rsvd0: 9;
2827 	u32 duration;
2828 	u8 courtesy_en;
2829 	u8 courtesy_num;
2830 	u8 courtesy_target;
2831 	u8 rsvd1;
2832 };
2833 
2834 static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val)
2835 {
2836 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2837 }
2838 
2839 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val)
2840 {
2841 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
2842 }
2843 
2844 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val)
2845 {
2846 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
2847 }
2848 
2849 static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val)
2850 {
2851 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
2852 }
2853 
2854 static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val)
2855 {
2856 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0));
2857 }
2858 
2859 static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val)
2860 {
2861 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4));
2862 }
2863 
2864 static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val)
2865 {
2866 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6));
2867 }
2868 
2869 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val)
2870 {
2871 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8));
2872 }
2873 
2874 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val)
2875 {
2876 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9));
2877 }
2878 
2879 static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val)
2880 {
2881 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10));
2882 }
2883 
2884 static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val)
2885 {
2886 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11));
2887 }
2888 
2889 static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val)
2890 {
2891 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14));
2892 }
2893 
2894 static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val)
2895 {
2896 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18));
2897 }
2898 
2899 static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val)
2900 {
2901 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19));
2902 }
2903 
2904 static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val)
2905 {
2906 	le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20));
2907 }
2908 
2909 static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val)
2910 {
2911 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21));
2912 }
2913 
2914 static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val)
2915 {
2916 	le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
2917 }
2918 
2919 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val)
2920 {
2921 	le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0));
2922 }
2923 
2924 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val)
2925 {
2926 	le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8));
2927 }
2928 
2929 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val)
2930 {
2931 	le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16));
2932 }
2933 
2934 struct rtw89_fw_mcc_start_req {
2935 	u32 group: 2;
2936 	u32 btc_in_group: 1;
2937 	u32 old_group_action: 2;
2938 	u32 old_group: 2;
2939 	u32 rsvd0: 9;
2940 	u32 notify_cnt: 3;
2941 	u32 rsvd1: 2;
2942 	u32 notify_rxdbg_en: 1;
2943 	u32 rsvd2: 2;
2944 	u32 macid: 8;
2945 	u32 tsf_low;
2946 	u32 tsf_high;
2947 };
2948 
2949 static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val)
2950 {
2951 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
2952 }
2953 
2954 static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val)
2955 {
2956 	le32p_replace_bits((__le32 *)cmd, val, BIT(2));
2957 }
2958 
2959 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val)
2960 {
2961 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3));
2962 }
2963 
2964 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val)
2965 {
2966 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5));
2967 }
2968 
2969 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val)
2970 {
2971 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16));
2972 }
2973 
2974 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val)
2975 {
2976 	le32p_replace_bits((__le32 *)cmd, val, BIT(21));
2977 }
2978 
2979 static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val)
2980 {
2981 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
2982 }
2983 
2984 static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val)
2985 {
2986 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
2987 }
2988 
2989 static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val)
2990 {
2991 	le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
2992 }
2993 
2994 static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val)
2995 {
2996 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2997 }
2998 
2999 static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val)
3000 {
3001 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8));
3002 }
3003 
3004 static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val)
3005 {
3006 	le32p_replace_bits((__le32 *)cmd, val, BIT(10));
3007 }
3008 
3009 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val)
3010 {
3011 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3012 }
3013 
3014 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val)
3015 {
3016 	le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3017 }
3018 
3019 static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val)
3020 {
3021 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3022 }
3023 
3024 struct rtw89_fw_mcc_tsf_req {
3025 	u8 group: 2;
3026 	u8 rsvd0: 6;
3027 	u8 macid_x;
3028 	u8 macid_y;
3029 	u8 rsvd1;
3030 };
3031 
3032 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val)
3033 {
3034 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3035 }
3036 
3037 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val)
3038 {
3039 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3040 }
3041 
3042 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val)
3043 {
3044 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3045 }
3046 
3047 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val)
3048 {
3049 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3050 }
3051 
3052 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val)
3053 {
3054 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3055 }
3056 
3057 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val)
3058 {
3059 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3060 }
3061 
3062 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd,
3063 							   u8 *bitmap, u8 len)
3064 {
3065 	memcpy((__le32 *)cmd + 1, bitmap, len);
3066 }
3067 
3068 static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val)
3069 {
3070 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3071 }
3072 
3073 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val)
3074 {
3075 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3076 }
3077 
3078 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val)
3079 {
3080 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3081 }
3082 
3083 static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val)
3084 {
3085 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3086 }
3087 
3088 struct rtw89_fw_mcc_duration {
3089 	u32 group: 2;
3090 	u32 btc_in_group: 1;
3091 	u32 rsvd0: 5;
3092 	u32 start_macid: 8;
3093 	u32 macid_x: 8;
3094 	u32 macid_y: 8;
3095 	u32 start_tsf_low;
3096 	u32 start_tsf_high;
3097 	u32 duration_x;
3098 	u32 duration_y;
3099 };
3100 
3101 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val)
3102 {
3103 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3104 }
3105 
3106 static
3107 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val)
3108 {
3109 	le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3110 }
3111 
3112 static
3113 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val)
3114 {
3115 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3116 }
3117 
3118 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val)
3119 {
3120 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3121 }
3122 
3123 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val)
3124 {
3125 	le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3126 }
3127 
3128 static
3129 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val)
3130 {
3131 	le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3132 }
3133 
3134 static
3135 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val)
3136 {
3137 	le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3138 }
3139 
3140 static
3141 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val)
3142 {
3143 	le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
3144 }
3145 
3146 static
3147 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val)
3148 {
3149 	le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
3150 }
3151 
3152 #define RTW89_C2H_HEADER_LEN 8
3153 
3154 struct rtw89_c2h_hdr {
3155 	__le32 w0;
3156 	__le32 w1;
3157 } __packed;
3158 
3159 #define RTW89_C2H_HDR_W0_CATEGORY GENMASK(1, 0)
3160 #define RTW89_C2H_HDR_W0_CLASS GENMASK(7, 2)
3161 #define RTW89_C2H_HDR_W0_FUNC GENMASK(15, 8)
3162 #define RTW89_C2H_HDR_W1_LEN GENMASK(13, 0)
3163 
3164 struct rtw89_fw_c2h_attr {
3165 	u8 category;
3166 	u8 class;
3167 	u8 func;
3168 	u16 len;
3169 };
3170 
3171 static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb)
3172 {
3173 	static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
3174 
3175 	return (struct rtw89_fw_c2h_attr *)skb->cb;
3176 }
3177 
3178 struct rtw89_c2h_done_ack {
3179 	__le32 w0;
3180 	__le32 w1;
3181 	__le32 w2;
3182 } __packed;
3183 
3184 #define RTW89_C2H_DONE_ACK_W2_CAT GENMASK(1, 0)
3185 #define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2)
3186 #define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8)
3187 #define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16)
3188 #define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24)
3189 
3190 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \
3191 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3192 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \
3193 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3194 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \
3195 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3196 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \
3197 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
3198 
3199 struct rtw89_fw_c2h_log_fmt {
3200 	__le16 signature;
3201 	u8 feature;
3202 	u8 syntax;
3203 	__le32 fmt_id;
3204 	u8 file_num;
3205 	__le16 line_num;
3206 	u8 argc;
3207 	union {
3208 		DECLARE_FLEX_ARRAY(u8, raw);
3209 		DECLARE_FLEX_ARRAY(__le32, argv);
3210 	} __packed u;
3211 } __packed;
3212 
3213 #define RTW89_C2H_FW_FORMATTED_LOG_MIN_LEN 11
3214 #define RTW89_C2H_FW_LOG_FEATURE_PARA_INT BIT(2)
3215 #define RTW89_C2H_FW_LOG_MAX_PARA_NUM 16
3216 #define RTW89_C2H_FW_LOG_SIGNATURE 0xA5A5
3217 #define RTW89_C2H_FW_LOG_STR_BUF_SIZE 512
3218 
3219 struct rtw89_c2h_mac_bcnfltr_rpt {
3220 	__le32 w0;
3221 	__le32 w1;
3222 	__le32 w2;
3223 } __packed;
3224 
3225 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0)
3226 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8)
3227 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10)
3228 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16)
3229 
3230 struct rtw89_c2h_ra_rpt {
3231 	struct rtw89_c2h_hdr hdr;
3232 	__le32 w2;
3233 	__le32 w3;
3234 } __packed;
3235 
3236 #define RTW89_C2H_RA_RPT_W2_MACID GENMASK(15, 0)
3237 #define RTW89_C2H_RA_RPT_W2_RETRY_RATIO GENMASK(23, 16)
3238 #define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31)
3239 #define RTW89_C2H_RA_RPT_W3_MCSNSS GENMASK(6, 0)
3240 #define RTW89_C2H_RA_RPT_W3_MD_SEL GENMASK(9, 8)
3241 #define RTW89_C2H_RA_RPT_W3_GILTF GENMASK(12, 10)
3242 #define RTW89_C2H_RA_RPT_W3_BW GENMASK(14, 13)
3243 #define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15)
3244 #define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16)
3245 
3246 /* For WiFi 6 chips:
3247  *   VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
3248  *   HT-new: [6:5]: NA, [4:0]: MCS
3249  * For WiFi 7 chips (V1):
3250  *   HT, VHT, HE, EHT: [7:5]: NSS, [4:0]: MCS
3251  */
3252 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
3253 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
3254 #define RTW89_RA_RATE_MASK_NSS_V1 GENMASK(7, 5)
3255 #define RTW89_RA_RATE_MASK_MCS_V1 GENMASK(4, 0)
3256 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
3257 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
3258 				    FIELD_PREP(GENMASK(2, 0), mcs))
3259 
3260 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \
3261 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3262 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \
3263 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))
3264 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \
3265 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))
3266 
3267 #define RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h) \
3268 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3269 #define RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h) \
3270 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(19, 16))
3271 #define RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h) \
3272 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 20))
3273 #define RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h) \
3274 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24))
3275 #define RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h) \
3276 	le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(3, 0))
3277 #define RTW89_GET_MAC_C2H_SCANOFLD_AIR_DENSITY(c2h) \
3278 	le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(7, 4))
3279 #define RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h) \
3280 	le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(25, 24))
3281 
3282 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \
3283 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3284 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \
3285 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3286 
3287 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \
3288 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3289 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \
3290 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3291 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \
3292 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3293 
3294 struct rtw89_mac_mcc_tsf_rpt {
3295 	u32 macid_x;
3296 	u32 macid_y;
3297 	u32 tsf_x_low;
3298 	u32 tsf_x_high;
3299 	u32 tsf_y_low;
3300 	u32 tsf_y_high;
3301 };
3302 
3303 static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3304 
3305 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \
3306 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3307 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \
3308 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3309 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \
3310 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16))
3311 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \
3312 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3313 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \
3314 	le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3315 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \
3316 	le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0))
3317 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \
3318 	le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0))
3319 
3320 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \
3321 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0))
3322 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \
3323 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6))
3324 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \
3325 	le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3326 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \
3327 	le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3328 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \
3329 	le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3330 
3331 struct rtw89_c2h_pkt_ofld_rsp {
3332 	__le32 w0;
3333 	__le32 w1;
3334 	__le32 w2;
3335 } __packed;
3336 
3337 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0)
3338 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8)
3339 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16)
3340 
3341 struct rtw89_h2c_bcnfltr {
3342 	__le32 w0;
3343 } __packed;
3344 
3345 #define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0)
3346 #define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1)
3347 #define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2)
3348 #define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3)
3349 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT GENMASK(11, 8)
3350 #define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12)
3351 #define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16)
3352 #define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24)
3353 
3354 struct rtw89_h2c_ofld_rssi {
3355 	__le32 w0;
3356 	__le32 w1;
3357 } __packed;
3358 
3359 #define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0)
3360 #define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8)
3361 #define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0)
3362 
3363 struct rtw89_h2c_ofld {
3364 	__le32 w0;
3365 } __packed;
3366 
3367 #define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0)
3368 #define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8)
3369 #define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18)
3370 
3371 #define RTW89_MFW_SIG	0xFF
3372 
3373 struct rtw89_mfw_info {
3374 	u8 cv;
3375 	u8 type; /* enum rtw89_fw_type */
3376 	u8 mp;
3377 	u8 rsvd;
3378 	__le32 shift;
3379 	__le32 size;
3380 	u8 rsvd2[4];
3381 } __packed;
3382 
3383 struct rtw89_mfw_hdr {
3384 	u8 sig;	/* RTW89_MFW_SIG */
3385 	u8 fw_nr;
3386 	u8 rsvd0[2];
3387 	struct {
3388 		u8 major;
3389 		u8 minor;
3390 		u8 sub;
3391 		u8 idx;
3392 	} ver;
3393 	u8 rsvd1[8];
3394 	struct rtw89_mfw_info info[];
3395 } __packed;
3396 
3397 struct rtw89_fw_logsuit_hdr {
3398 	__le32 rsvd;
3399 	__le32 count;
3400 	__le32 ids[];
3401 } __packed;
3402 
3403 #define RTW89_FW_ELEMENT_ALIGN 16
3404 
3405 enum rtw89_fw_element_id {
3406 	RTW89_FW_ELEMENT_ID_BBMCU0 = 0,
3407 	RTW89_FW_ELEMENT_ID_BBMCU1 = 1,
3408 	RTW89_FW_ELEMENT_ID_BB_REG = 2,
3409 	RTW89_FW_ELEMENT_ID_BB_GAIN = 3,
3410 	RTW89_FW_ELEMENT_ID_RADIO_A = 4,
3411 	RTW89_FW_ELEMENT_ID_RADIO_B = 5,
3412 	RTW89_FW_ELEMENT_ID_RADIO_C = 6,
3413 	RTW89_FW_ELEMENT_ID_RADIO_D = 7,
3414 	RTW89_FW_ELEMENT_ID_RF_NCTL = 8,
3415 
3416 	RTW89_FW_ELEMENT_ID_NUM,
3417 };
3418 
3419 struct rtw89_fw_element_hdr {
3420 	__le32 id; /* enum rtw89_fw_element_id */
3421 	__le32 size; /* exclude header size */
3422 	u8 ver[4];
3423 	__le32 rsvd0;
3424 	__le32 rsvd1;
3425 	__le32 rsvd2;
3426 	union {
3427 		struct {
3428 			u8 priv[8];
3429 			u8 contents[];
3430 		} __packed common;
3431 		struct {
3432 			u8 idx;
3433 			u8 rsvd[7];
3434 			struct {
3435 				__le32 addr;
3436 				__le32 data;
3437 			} __packed regs[];
3438 		} __packed reg2;
3439 	} __packed u;
3440 } __packed;
3441 
3442 struct fwcmd_hdr {
3443 	__le32 hdr0;
3444 	__le32 hdr1;
3445 };
3446 
3447 union rtw89_compat_fw_hdr {
3448 	struct rtw89_mfw_hdr mfw_hdr;
3449 	struct rtw89_fw_hdr fw_hdr;
3450 };
3451 
3452 static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf)
3453 {
3454 	const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf;
3455 
3456 	if (compat->mfw_hdr.sig == RTW89_MFW_SIG)
3457 		return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr);
3458 	else
3459 		return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr);
3460 }
3461 
3462 static inline void rtw89_fw_get_filename(char *buf, size_t size,
3463 					 const char *fw_basename, int fw_format)
3464 {
3465 	if (fw_format <= 0)
3466 		snprintf(buf, size, "%s.bin", fw_basename);
3467 	else
3468 		snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format);
3469 }
3470 
3471 #define RTW89_H2C_RF_PAGE_SIZE 500
3472 #define RTW89_H2C_RF_PAGE_NUM 3
3473 struct rtw89_fw_h2c_rf_reg_info {
3474 	enum rtw89_rf_path rf_path;
3475 	__le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE];
3476 	u16 curr_idx;
3477 };
3478 
3479 #define H2C_SEC_CAM_LEN			24
3480 
3481 #define H2C_HEADER_LEN			8
3482 #define H2C_HDR_CAT			GENMASK(1, 0)
3483 #define H2C_HDR_CLASS			GENMASK(7, 2)
3484 #define H2C_HDR_FUNC			GENMASK(15, 8)
3485 #define H2C_HDR_DEL_TYPE		GENMASK(19, 16)
3486 #define H2C_HDR_H2C_SEQ			GENMASK(31, 24)
3487 #define H2C_HDR_TOTAL_LEN		GENMASK(13, 0)
3488 #define H2C_HDR_REC_ACK			BIT(14)
3489 #define H2C_HDR_DONE_ACK		BIT(15)
3490 
3491 #define FWCMD_TYPE_H2C			0
3492 
3493 #define H2C_CAT_TEST		0x0
3494 
3495 /* CLASS 5 - FW STATUS TEST */
3496 #define H2C_CL_FW_STATUS_TEST		0x5
3497 #define H2C_FUNC_CPU_EXCEPTION		0x1
3498 
3499 #define H2C_CAT_MAC		0x1
3500 
3501 /* CLASS 0 - FW INFO */
3502 #define H2C_CL_FW_INFO			0x0
3503 #define H2C_FUNC_LOG_CFG		0x0
3504 #define H2C_FUNC_MAC_GENERAL_PKT	0x1
3505 
3506 /* CLASS 1 - WOW */
3507 #define H2C_CL_MAC_WOW			0x1
3508 #define H2C_FUNC_KEEP_ALIVE		0x0
3509 #define H2C_FUNC_DISCONNECT_DETECT	0x1
3510 #define H2C_FUNC_WOW_GLOBAL		0x2
3511 #define H2C_FUNC_WAKEUP_CTRL		0x8
3512 #define H2C_FUNC_WOW_CAM_UPD		0xC
3513 
3514 /* CLASS 2 - PS */
3515 #define H2C_CL_MAC_PS			0x2
3516 #define H2C_FUNC_MAC_LPS_PARM		0x0
3517 #define H2C_FUNC_P2P_ACT		0x1
3518 
3519 /* CLASS 3 - FW download */
3520 #define H2C_CL_MAC_FWDL		0x3
3521 #define H2C_FUNC_MAC_FWHDR_DL		0x0
3522 
3523 /* CLASS 5 - Frame Exchange */
3524 #define H2C_CL_MAC_FR_EXCHG		0x5
3525 #define H2C_FUNC_MAC_CCTLINFO_UD	0x2
3526 #define H2C_FUNC_MAC_BCN_UPD		0x5
3527 #define H2C_FUNC_MAC_DCTLINFO_UD_V1	0x9
3528 #define H2C_FUNC_MAC_CCTLINFO_UD_V1	0xa
3529 
3530 /* CLASS 6 - Address CAM */
3531 #define H2C_CL_MAC_ADDR_CAM_UPDATE	0x6
3532 #define H2C_FUNC_MAC_ADDR_CAM_UPD	0x0
3533 
3534 /* CLASS 8 - Media Status Report */
3535 #define H2C_CL_MAC_MEDIA_RPT		0x8
3536 #define H2C_FUNC_MAC_JOININFO		0x0
3537 #define H2C_FUNC_MAC_FWROLE_MAINTAIN	0x4
3538 
3539 /* CLASS 9 - FW offload */
3540 #define H2C_CL_MAC_FW_OFLD		0x9
3541 enum rtw89_fw_ofld_h2c_func {
3542 	H2C_FUNC_PACKET_OFLD		= 0x1,
3543 	H2C_FUNC_MAC_MACID_PAUSE	= 0x8,
3544 	H2C_FUNC_USR_EDCA		= 0xF,
3545 	H2C_FUNC_TSF32_TOGL		= 0x10,
3546 	H2C_FUNC_OFLD_CFG		= 0x14,
3547 	H2C_FUNC_ADD_SCANOFLD_CH	= 0x16,
3548 	H2C_FUNC_SCANOFLD		= 0x17,
3549 	H2C_FUNC_PKT_DROP		= 0x1b,
3550 	H2C_FUNC_CFG_BCNFLTR		= 0x1e,
3551 	H2C_FUNC_OFLD_RSSI		= 0x1f,
3552 	H2C_FUNC_OFLD_TP		= 0x20,
3553 
3554 	NUM_OF_RTW89_FW_OFLD_H2C_FUNC,
3555 };
3556 
3557 #define RTW89_FW_OFLD_WAIT_COND(tag, func) \
3558 	((tag) * NUM_OF_RTW89_FW_OFLD_H2C_FUNC + (func))
3559 
3560 #define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \
3561 	RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \
3562 				H2C_FUNC_PACKET_OFLD)
3563 
3564 /* CLASS 10 - Security CAM */
3565 #define H2C_CL_MAC_SEC_CAM		0xa
3566 #define H2C_FUNC_MAC_SEC_UPD		0x1
3567 
3568 /* CLASS 12 - BA CAM */
3569 #define H2C_CL_BA_CAM			0xc
3570 #define H2C_FUNC_MAC_BA_CAM		0x0
3571 
3572 /* CLASS 14 - MCC */
3573 #define H2C_CL_MCC			0xe
3574 enum rtw89_mcc_h2c_func {
3575 	H2C_FUNC_ADD_MCC		= 0x0,
3576 	H2C_FUNC_START_MCC		= 0x1,
3577 	H2C_FUNC_STOP_MCC		= 0x2,
3578 	H2C_FUNC_DEL_MCC_GROUP		= 0x3,
3579 	H2C_FUNC_RESET_MCC_GROUP	= 0x4,
3580 	H2C_FUNC_MCC_REQ_TSF		= 0x5,
3581 	H2C_FUNC_MCC_MACID_BITMAP	= 0x6,
3582 	H2C_FUNC_MCC_SYNC		= 0x7,
3583 	H2C_FUNC_MCC_SET_DURATION	= 0x8,
3584 
3585 	NUM_OF_RTW89_MCC_H2C_FUNC,
3586 };
3587 
3588 #define RTW89_MCC_WAIT_COND(group, func) \
3589 	((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func))
3590 
3591 #define H2C_CAT_OUTSRC			0x2
3592 
3593 #define H2C_CL_OUTSRC_RA		0x1
3594 #define H2C_FUNC_OUTSRC_RA_MACIDCFG	0x0
3595 
3596 #define H2C_CL_OUTSRC_RF_REG_A		0x8
3597 #define H2C_CL_OUTSRC_RF_REG_B		0x9
3598 #define H2C_CL_OUTSRC_RF_FW_NOTIFY	0xa
3599 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH	0x2
3600 
3601 struct rtw89_fw_h2c_rf_get_mccch {
3602 	__le32 ch_0;
3603 	__le32 ch_1;
3604 	__le32 band_0;
3605 	__le32 band_1;
3606 	__le32 current_channel;
3607 	__le32 current_band_type;
3608 } __packed;
3609 
3610 #define RTW89_FW_RSVD_PLE_SIZE 0x800
3611 
3612 #define RTW89_WCPU_BASE_MASK GENMASK(27, 0)
3613 
3614 #define RTW89_FW_BACKTRACE_INFO_SIZE 8
3615 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \
3616 	((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0)
3617 
3618 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */
3619 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE
3620 
3621 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev);
3622 int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
3623 int rtw89_fw_recognize_elements(struct rtw89_dev *rtwdev);
3624 const struct firmware *
3625 rtw89_early_fw_feature_recognize(struct device *device,
3626 				 const struct rtw89_chip_info *chip,
3627 				 struct rtw89_fw_info *early_fw,
3628 				 int *used_fw_format);
3629 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type);
3630 void rtw89_load_firmware_work(struct work_struct *work);
3631 void rtw89_unload_firmware(struct rtw89_dev *rtwdev);
3632 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev);
3633 int rtw89_fw_log_prepare(struct rtw89_dev *rtwdev);
3634 void rtw89_fw_log_dump(struct rtw89_dev *rtwdev, u8 *buf, u32 len);
3635 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb,
3636 			   u8 type, u8 cat, u8 class, u8 func,
3637 			   bool rack, bool dack, u32 len);
3638 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
3639 				  struct rtw89_vif *rtwvif);
3640 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
3641 				struct ieee80211_vif *vif,
3642 				struct ieee80211_sta *sta);
3643 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
3644 				 struct rtw89_sta *rtwsta);
3645 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev,
3646 				 struct rtw89_sta *rtwsta);
3647 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev,
3648 			       struct rtw89_vif *rtwvif);
3649 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif,
3650 		     struct rtw89_sta *rtwsta, const u8 *scan_mac_addr);
3651 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev,
3652 				 struct rtw89_vif *rtwvif,
3653 				 struct rtw89_sta *rtwsta);
3654 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h);
3655 void rtw89_fw_c2h_work(struct work_struct *work);
3656 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev,
3657 			       struct rtw89_vif *rtwvif,
3658 			       struct rtw89_sta *rtwsta,
3659 			       enum rtw89_upd_mode upd_mode);
3660 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3661 			   struct rtw89_sta *rtwsta, bool dis_conn);
3662 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp,
3663 			     bool pause);
3664 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3665 			  u8 ac, u32 val);
3666 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev);
3667 int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev,
3668 				  struct ieee80211_vif *vif,
3669 				  bool connect);
3670 int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev,
3671 			      struct rtw89_rx_phy_ppdu *phy_ppdu);
3672 int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
3673 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi);
3674 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev);
3675 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev);
3676 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev);
3677 int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev);
3678 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev);
3679 int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev);
3680 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev);
3681 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id);
3682 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
3683 				 struct sk_buff *skb_ofld);
3684 int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int len,
3685 				   struct list_head *chan_list);
3686 int rtw89_fw_h2c_scan_offload(struct rtw89_dev *rtwdev,
3687 			      struct rtw89_scan_option *opt,
3688 			      struct rtw89_vif *vif);
3689 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
3690 			struct rtw89_fw_h2c_rf_reg_info *info,
3691 			u16 len, u8 page);
3692 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev);
3693 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
3694 			      u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
3695 			      bool rack, bool dack);
3696 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len);
3697 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev);
3698 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
3699 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3700 			     u8 macid);
3701 void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev,
3702 					   struct rtw89_vif *rtwvif, bool notify_fw);
3703 void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw);
3704 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
3705 			bool valid, struct ieee80211_ampdu_params *params);
3706 void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev);
3707 
3708 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,
3709 			  struct rtw89_lps_parm *lps_param);
3710 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len);
3711 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len);
3712 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev,
3713 		     struct rtw89_mac_h2c_info *h2c_info,
3714 		     struct rtw89_mac_c2h_info *c2h_info);
3715 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable);
3716 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev);
3717 void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3718 			 struct ieee80211_scan_request *req);
3719 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3720 			    bool aborted);
3721 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3722 			  bool enable);
3723 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
3724 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev);
3725 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev,
3726 			  const struct rtw89_pkt_drop_params *params);
3727 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3728 			 struct ieee80211_p2p_noa_desc *desc,
3729 			 u8 act, u8 noa_id);
3730 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3731 			      bool en);
3732 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3733 			    bool enable);
3734 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
3735 				 struct rtw89_vif *rtwvif, bool enable);
3736 int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3737 			    bool enable);
3738 int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
3739 				   struct rtw89_vif *rtwvif, bool enable);
3740 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3741 			    bool enable);
3742 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
3743 				 struct rtw89_vif *rtwvif, bool enable);
3744 int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
3745 			    struct rtw89_wow_cam_info *cam_info);
3746 int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
3747 			 const struct rtw89_fw_mcc_add_req *p);
3748 int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
3749 			   const struct rtw89_fw_mcc_start_req *p);
3750 int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
3751 			  bool prev_groups);
3752 int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
3753 			       bool prev_groups);
3754 int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group);
3755 int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
3756 			     const struct rtw89_fw_mcc_tsf_req *req,
3757 			     struct rtw89_mac_mcc_tsf_rpt *rpt);
3758 int rtw89_fw_h2c_mcc_macid_bitamp(struct rtw89_dev *rtwdev, u8 group, u8 macid,
3759 				  u8 *bitmap);
3760 int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
3761 			  u8 target, u8 offset);
3762 int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
3763 				  const struct rtw89_fw_mcc_duration *p);
3764 
3765 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
3766 {
3767 	const struct rtw89_chip_info *chip = rtwdev->chip;
3768 
3769 	if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
3770 		rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev);
3771 }
3772 
3773 #endif
3774