1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_FW_H__ 6 #define __RTW89_FW_H__ 7 8 #include "core.h" 9 10 enum rtw89_fw_dl_status { 11 RTW89_FWDL_INITIAL_STATE = 0, 12 RTW89_FWDL_FWDL_ONGOING = 1, 13 RTW89_FWDL_CHECKSUM_FAIL = 2, 14 RTW89_FWDL_SECURITY_FAIL = 3, 15 RTW89_FWDL_CV_NOT_MATCH = 4, 16 RTW89_FWDL_RSVD0 = 5, 17 RTW89_FWDL_WCPU_FWDL_RDY = 6, 18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7 19 }; 20 21 #define RTW89_GET_C2H_HDR_FUNC(info) \ 22 u32_get_bits(info, GENMASK(6, 0)) 23 #define RTW89_GET_C2H_HDR_LEN(info) \ 24 u32_get_bits(info, GENMASK(11, 8)) 25 26 #define RTW89_SET_H2CREG_HDR_FUNC(info, val) \ 27 u32p_replace_bits(info, val, GENMASK(6, 0)) 28 #define RTW89_SET_H2CREG_HDR_LEN(info, val) \ 29 u32p_replace_bits(info, val, GENMASK(11, 8)) 30 31 #define RTW89_H2CREG_MAX 4 32 #define RTW89_C2HREG_MAX 4 33 #define RTW89_C2HREG_HDR_LEN 2 34 #define RTW89_H2CREG_HDR_LEN 2 35 #define RTW89_C2H_TIMEOUT 1000000 36 struct rtw89_mac_c2h_info { 37 u8 id; 38 u8 content_len; 39 u32 c2hreg[RTW89_C2HREG_MAX]; 40 }; 41 42 struct rtw89_mac_h2c_info { 43 u8 id; 44 u8 content_len; 45 u32 h2creg[RTW89_H2CREG_MAX]; 46 }; 47 48 enum rtw89_mac_h2c_type { 49 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0, 50 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD, 51 RTW89_FWCMD_H2CREG_FUNC_FWERR, 52 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE, 53 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM, 54 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN 55 }; 56 57 enum rtw89_mac_c2h_type { 58 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0, 59 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT, 60 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG, 61 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP, 62 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT, 63 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF 64 }; 65 66 struct rtw89_c2h_phy_cap { 67 u32 func:7; 68 u32 ack:1; 69 u32 len:4; 70 u32 seq:4; 71 u32 rx_nss:8; 72 u32 bw:8; 73 74 u32 tx_nss:8; 75 u32 prot:8; 76 u32 nic:8; 77 u32 wl_func:8; 78 79 u32 hw_type:8; 80 } __packed; 81 82 enum rtw89_fw_c2h_category { 83 RTW89_C2H_CAT_TEST, 84 RTW89_C2H_CAT_MAC, 85 RTW89_C2H_CAT_OUTSRC, 86 }; 87 88 enum rtw89_fw_log_level { 89 RTW89_FW_LOG_LEVEL_OFF, 90 RTW89_FW_LOG_LEVEL_CRT, 91 RTW89_FW_LOG_LEVEL_SER, 92 RTW89_FW_LOG_LEVEL_WARN, 93 RTW89_FW_LOG_LEVEL_LOUD, 94 RTW89_FW_LOG_LEVEL_TR, 95 }; 96 97 enum rtw89_fw_log_path { 98 RTW89_FW_LOG_LEVEL_UART, 99 RTW89_FW_LOG_LEVEL_C2H, 100 RTW89_FW_LOG_LEVEL_SNI, 101 }; 102 103 enum rtw89_fw_log_comp { 104 RTW89_FW_LOG_COMP_VER, 105 RTW89_FW_LOG_COMP_INIT, 106 RTW89_FW_LOG_COMP_TASK, 107 RTW89_FW_LOG_COMP_CNS, 108 RTW89_FW_LOG_COMP_H2C, 109 RTW89_FW_LOG_COMP_C2H, 110 RTW89_FW_LOG_COMP_TX, 111 RTW89_FW_LOG_COMP_RX, 112 RTW89_FW_LOG_COMP_IPSEC, 113 RTW89_FW_LOG_COMP_TIMER, 114 RTW89_FW_LOG_COMP_DBGPKT, 115 RTW89_FW_LOG_COMP_PS, 116 RTW89_FW_LOG_COMP_ERROR, 117 RTW89_FW_LOG_COMP_WOWLAN, 118 RTW89_FW_LOG_COMP_SECURE_BOOT, 119 RTW89_FW_LOG_COMP_BTC, 120 RTW89_FW_LOG_COMP_BB, 121 RTW89_FW_LOG_COMP_TWT, 122 RTW89_FW_LOG_COMP_RF, 123 RTW89_FW_LOG_COMP_MCC = 20, 124 }; 125 126 #define FWDL_SECTION_MAX_NUM 10 127 #define FWDL_SECTION_CHKSUM_LEN 8 128 #define FWDL_SECTION_PER_PKT_LEN 2020 129 130 struct rtw89_fw_hdr_section_info { 131 u8 redl; 132 const u8 *addr; 133 u32 len; 134 u32 dladdr; 135 }; 136 137 struct rtw89_fw_bin_info { 138 u8 section_num; 139 u32 hdr_len; 140 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM]; 141 }; 142 143 struct rtw89_fw_macid_pause_grp { 144 __le32 pause_grp[4]; 145 __le32 mask_grp[4]; 146 } __packed; 147 148 struct rtw89_h2creg_sch_tx_en { 149 u8 func:7; 150 u8 ack:1; 151 u8 total_len:4; 152 u8 seq_num:4; 153 u16 tx_en:16; 154 u16 mask:16; 155 u8 band:1; 156 u16 rsvd:15; 157 } __packed; 158 159 static inline void RTW89_SET_FWCMD_RA_IS_DIS(void *cmd, u32 val) 160 { 161 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(0)); 162 } 163 164 static inline void RTW89_SET_FWCMD_RA_MODE(void *cmd, u32 val) 165 { 166 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(5, 1)); 167 } 168 169 static inline void RTW89_SET_FWCMD_RA_BW_CAP(void *cmd, u32 val) 170 { 171 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 6)); 172 } 173 174 static inline void RTW89_SET_FWCMD_RA_MACID(void *cmd, u32 val) 175 { 176 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); 177 } 178 179 static inline void RTW89_SET_FWCMD_RA_DCM(void *cmd, u32 val) 180 { 181 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(16)); 182 } 183 184 static inline void RTW89_SET_FWCMD_RA_ER(void *cmd, u32 val) 185 { 186 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(17)); 187 } 188 189 static inline void RTW89_SET_FWCMD_RA_INIT_RATE_LV(void *cmd, u32 val) 190 { 191 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(19, 18)); 192 } 193 194 static inline void RTW89_SET_FWCMD_RA_UPD_ALL(void *cmd, u32 val) 195 { 196 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(20)); 197 } 198 199 static inline void RTW89_SET_FWCMD_RA_SGI(void *cmd, u32 val) 200 { 201 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(21)); 202 } 203 204 static inline void RTW89_SET_FWCMD_RA_LDPC(void *cmd, u32 val) 205 { 206 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(22)); 207 } 208 209 static inline void RTW89_SET_FWCMD_RA_STBC(void *cmd, u32 val) 210 { 211 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(23)); 212 } 213 214 static inline void RTW89_SET_FWCMD_RA_SS_NUM(void *cmd, u32 val) 215 { 216 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(26, 24)); 217 } 218 219 static inline void RTW89_SET_FWCMD_RA_GILTF(void *cmd, u32 val) 220 { 221 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(29, 27)); 222 } 223 224 static inline void RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(void *cmd, u32 val) 225 { 226 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(30)); 227 } 228 229 static inline void RTW89_SET_FWCMD_RA_UPD_MASK(void *cmd, u32 val) 230 { 231 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(31)); 232 } 233 234 static inline void RTW89_SET_FWCMD_RA_MASK_0(void *cmd, u32 val) 235 { 236 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(7, 0)); 237 } 238 239 static inline void RTW89_SET_FWCMD_RA_MASK_1(void *cmd, u32 val) 240 { 241 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(15, 8)); 242 } 243 244 static inline void RTW89_SET_FWCMD_RA_MASK_2(void *cmd, u32 val) 245 { 246 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(23, 16)); 247 } 248 249 static inline void RTW89_SET_FWCMD_RA_MASK_3(void *cmd, u32 val) 250 { 251 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 24)); 252 } 253 254 static inline void RTW89_SET_FWCMD_RA_MASK_4(void *cmd, u32 val) 255 { 256 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(7, 0)); 257 } 258 259 static inline void RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(void *cmd, u32 val) 260 { 261 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, BIT(31)); 262 } 263 264 static inline void RTW89_SET_FWCMD_RA_BAND_NUM(void *cmd, u32 val) 265 { 266 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(7, 0)); 267 } 268 269 static inline void RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(void *cmd, u32 val) 270 { 271 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(8)); 272 } 273 274 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(void *cmd, u32 val) 275 { 276 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(9)); 277 } 278 279 static inline void RTW89_SET_FWCMD_RA_CR_TBL_SEL(void *cmd, u32 val) 280 { 281 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(10)); 282 } 283 284 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(void *cmd, u32 val) 285 { 286 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(23, 16)); 287 } 288 289 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(void *cmd, u32 val) 290 { 291 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(25, 24)); 292 } 293 294 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(void *cmd, u32 val) 295 { 296 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(28, 26)); 297 } 298 299 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_BW(void *cmd, u32 val) 300 { 301 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 29)); 302 } 303 304 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val) 305 { 306 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)); 307 } 308 309 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val) 310 { 311 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); 312 } 313 314 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val) 315 { 316 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)); 317 } 318 319 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val) 320 { 321 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0)); 322 } 323 324 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val) 325 { 326 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4)); 327 } 328 329 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val) 330 { 331 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5)); 332 } 333 334 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val) 335 { 336 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0)); 337 } 338 339 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val) 340 { 341 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0)); 342 } 343 344 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val) 345 { 346 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0)); 347 } 348 349 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val) 350 { 351 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0)); 352 } 353 354 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val) 355 { 356 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0)); 357 } 358 359 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val) 360 { 361 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3)); 362 } 363 364 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val) 365 { 366 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4)); 367 } 368 369 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val) 370 { 371 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5)); 372 } 373 374 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val) 375 { 376 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0)); 377 } 378 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16) 379 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12) 380 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8) 381 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0) 382 383 #define GET_FWSECTION_HDR_SEC_SIZE(fwhdr) \ 384 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 0)) 385 #define GET_FWSECTION_HDR_CHECKSUM(fwhdr) \ 386 le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(28)) 387 #define GET_FWSECTION_HDR_REDL(fwhdr) \ 388 le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(29)) 389 #define GET_FWSECTION_HDR_DL_ADDR(fwhdr) \ 390 le32_get_bits(*((const __le32 *)(fwhdr)), GENMASK(31, 0)) 391 392 #define GET_FW_HDR_MAJOR_VERSION(fwhdr) \ 393 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(7, 0)) 394 #define GET_FW_HDR_MINOR_VERSION(fwhdr) \ 395 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(15, 8)) 396 #define GET_FW_HDR_SUBVERSION(fwhdr) \ 397 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 16)) 398 #define GET_FW_HDR_SUBINDEX(fwhdr) \ 399 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(31, 24)) 400 #define GET_FW_HDR_MONTH(fwhdr) \ 401 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(7, 0)) 402 #define GET_FW_HDR_DATE(fwhdr) \ 403 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(15, 8)) 404 #define GET_FW_HDR_HOUR(fwhdr) \ 405 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(23, 16)) 406 #define GET_FW_HDR_MIN(fwhdr) \ 407 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(31, 24)) 408 #define GET_FW_HDR_YEAR(fwhdr) \ 409 le32_get_bits(*((const __le32 *)(fwhdr) + 5), GENMASK(31, 0)) 410 #define GET_FW_HDR_SEC_NUM(fwhdr) \ 411 le32_get_bits(*((const __le32 *)(fwhdr) + 6), GENMASK(15, 8)) 412 #define GET_FW_HDR_CMD_VERSERION(fwhdr) \ 413 le32_get_bits(*((const __le32 *)(fwhdr) + 7), GENMASK(31, 24)) 414 static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val) 415 { 416 le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0)); 417 } 418 419 static inline void SET_CTRL_INFO_MACID(void *table, u32 val) 420 { 421 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)); 422 } 423 424 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val) 425 { 426 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); 427 } 428 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0) 429 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val) 430 { 431 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0)); 432 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE, 433 GENMASK(8, 0)); 434 } 435 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0) 436 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val) 437 { 438 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9)); 439 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP, 440 BIT(9)); 441 } 442 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0) 443 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val) 444 { 445 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10)); 446 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW, 447 GENMASK(11, 10)); 448 } 449 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0) 450 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val) 451 { 452 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12)); 453 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF, 454 GENMASK(14, 12)); 455 } 456 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0) 457 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val) 458 { 459 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); 460 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX, 461 BIT(15)); 462 } 463 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0) 464 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val) 465 { 466 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16)); 467 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL, 468 GENMASK(19, 16)); 469 } 470 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0) 471 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val) 472 { 473 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20)); 474 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN, 475 BIT(20)); 476 } 477 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0) 478 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val) 479 { 480 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21)); 481 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN, 482 BIT(21)); 483 } 484 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0) 485 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val) 486 { 487 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22)); 488 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN, 489 BIT(22)); 490 } 491 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0) 492 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val) 493 { 494 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23)); 495 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN, 496 BIT(23)); 497 } 498 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0) 499 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val) 500 { 501 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25)); 502 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB, 503 BIT(25)); 504 } 505 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0) 506 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val) 507 { 508 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26)); 509 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB, 510 BIT(26)); 511 } 512 #define SET_CMC_TBL_MASK_TRYRATE BIT(0) 513 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val) 514 { 515 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27)); 516 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE, 517 BIT(27)); 518 } 519 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0) 520 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val) 521 { 522 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28)); 523 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY, 524 GENMASK(31, 28)); 525 } 526 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0) 527 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val) 528 { 529 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0)); 530 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE, 531 GENMASK(8, 0)); 532 } 533 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0) 534 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val) 535 { 536 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9)); 537 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL, 538 BIT(9)); 539 } 540 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0) 541 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val) 542 { 543 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10)); 544 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL, 545 BIT(10)); 546 } 547 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0) 548 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val) 549 { 550 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11)); 551 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL, 552 BIT(11)); 553 } 554 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0) 555 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val) 556 { 557 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12)); 558 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT, 559 GENMASK(15, 12)); 560 } 561 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0) 562 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val) 563 { 564 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16)); 565 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE, 566 GENMASK(24, 16)); 567 } 568 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0) 569 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val) 570 { 571 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27)); 572 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC, 573 BIT(27)); 574 } 575 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0) 576 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val) 577 { 578 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28)); 579 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE, 580 GENMASK(31, 28)); 581 } 582 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0) 583 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val) 584 { 585 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0)); 586 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT, 587 GENMASK(5, 0)); 588 } 589 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0) 590 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val) 591 { 592 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6)); 593 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL, 594 BIT(6)); 595 } 596 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0) 597 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val) 598 { 599 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7)); 600 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL, 601 BIT(7)); 602 } 603 #define SET_CMC_TBL_MASK_RTS_EN BIT(0) 604 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val) 605 { 606 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8)); 607 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN, 608 BIT(8)); 609 } 610 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0) 611 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val) 612 { 613 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9)); 614 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN, 615 BIT(9)); 616 } 617 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0) 618 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val) 619 { 620 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10)); 621 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS, 622 GENMASK(11, 10)); 623 } 624 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0) 625 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val) 626 { 627 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12)); 628 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN, 629 BIT(12)); 630 } 631 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0) 632 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val) 633 { 634 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13)); 635 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE, 636 GENMASK(14, 13)); 637 } 638 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0) 639 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val) 640 { 641 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16)); 642 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN, 643 GENMASK(26, 16)); 644 } 645 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0) 646 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val) 647 { 648 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); 649 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS, 650 BIT(27)); 651 } 652 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0) 653 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val) 654 { 655 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28)); 656 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME, 657 GENMASK(31, 28)); 658 } 659 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0) 660 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val) 661 { 662 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0)); 663 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM, 664 GENMASK(7, 0)); 665 } 666 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0) 667 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val) 668 { 669 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8)); 670 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP, 671 GENMASK(9, 8)); 672 } 673 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0) 674 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val) 675 { 676 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16)); 677 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL, 678 GENMASK(18, 16)); 679 } 680 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0) 681 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val) 682 { 683 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19)); 684 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL, 685 GENMASK(21, 19)); 686 } 687 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0) 688 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val) 689 { 690 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22)); 691 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL, 692 GENMASK(24, 22)); 693 } 694 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0) 695 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val) 696 { 697 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25)); 698 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL, 699 GENMASK(27, 25)); 700 } 701 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0) 702 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val) 703 { 704 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28)); 705 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE, 706 GENMASK(31, 28)); 707 } 708 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0) 709 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val) 710 { 711 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0)); 712 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID, 713 GENMASK(2, 0)); 714 } 715 #define SET_CMC_TBL_MASK_BMC BIT(0) 716 static inline void SET_CMC_TBL_BMC(void *table, u32 val) 717 { 718 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3)); 719 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC, 720 BIT(3)); 721 } 722 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0) 723 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val) 724 { 725 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4)); 726 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID, 727 GENMASK(7, 4)); 728 } 729 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0) 730 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val) 731 { 732 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); 733 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR, 734 BIT(8)); 735 } 736 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0) 737 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val) 738 { 739 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9)); 740 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE, 741 GENMASK(11, 9)); 742 } 743 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0) 744 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val) 745 { 746 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12)); 747 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM, 748 BIT(12)); 749 } 750 #define SET_CMC_TBL_MASK_DATA_ER BIT(0) 751 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val) 752 { 753 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13)); 754 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER, 755 BIT(13)); 756 } 757 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0) 758 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val) 759 { 760 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14)); 761 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC, 762 BIT(14)); 763 } 764 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0) 765 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val) 766 { 767 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); 768 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC, 769 BIT(15)); 770 } 771 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0) 772 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val) 773 { 774 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16)); 775 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR, 776 BIT(16)); 777 } 778 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0) 779 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val) 780 { 781 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17)); 782 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH, 783 BIT(17)); 784 } 785 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0) 786 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val) 787 { 788 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18)); 789 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR, 790 BIT(18)); 791 } 792 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0) 793 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val) 794 { 795 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19)); 796 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS, 797 BIT(19)); 798 } 799 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0) 800 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val) 801 { 802 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20)); 803 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER, 804 BIT(20)); 805 } 806 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0) 807 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val) 808 { 809 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21)); 810 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN, 811 BIT(21)); 812 } 813 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0) 814 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val) 815 { 816 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27)); 817 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD, 818 BIT(27)); 819 } 820 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0) 821 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val) 822 { 823 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28)); 824 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT, 825 GENMASK(31, 28)); 826 } 827 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0) 828 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val) 829 { 830 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0)); 831 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE, 832 GENMASK(8, 0)); 833 } 834 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0) 835 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val) 836 { 837 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12)); 838 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT, 839 BIT(12)); 840 } 841 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0) 842 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val) 843 { 844 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13)); 845 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT, 846 BIT(13)); 847 } 848 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0) 849 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val) 850 { 851 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16)); 852 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN, 853 GENMASK(19, 16)); 854 } 855 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0) 856 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val) 857 { 858 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20)); 859 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A, 860 GENMASK(21, 20)); 861 } 862 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0) 863 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val) 864 { 865 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22)); 866 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B, 867 GENMASK(23, 22)); 868 } 869 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0) 870 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val) 871 { 872 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24)); 873 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C, 874 GENMASK(25, 24)); 875 } 876 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0) 877 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val) 878 { 879 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26)); 880 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D, 881 GENMASK(27, 26)); 882 } 883 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0) 884 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val) 885 { 886 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28)); 887 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A, 888 BIT(28)); 889 } 890 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0) 891 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val) 892 { 893 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29)); 894 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B, 895 BIT(29)); 896 } 897 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0) 898 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val) 899 { 900 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30)); 901 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C, 902 BIT(30)); 903 } 904 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0) 905 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val) 906 { 907 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31)); 908 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D, 909 BIT(31)); 910 } 911 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0) 912 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val) 913 { 914 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); 915 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX, 916 GENMASK(7, 0)); 917 } 918 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0) 919 static inline void SET_CMC_TBL_PAID(void *table, u32 val) 920 { 921 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8)); 922 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID, 923 GENMASK(16, 8)); 924 } 925 #define SET_CMC_TBL_MASK_ULDL BIT(0) 926 static inline void SET_CMC_TBL_ULDL(void *table, u32 val) 927 { 928 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17)); 929 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL, 930 BIT(17)); 931 } 932 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0) 933 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val) 934 { 935 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18)); 936 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL, 937 GENMASK(19, 18)); 938 } 939 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0) 940 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val) 941 { 942 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20)); 943 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 944 GENMASK(21, 20)); 945 } 946 947 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val) 948 { 949 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22)); 950 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 951 GENMASK(23, 22)); 952 } 953 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0) 954 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val) 955 { 956 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24)); 957 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE, 958 GENMASK(27, 24)); 959 } 960 961 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val) 962 { 963 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30)); 964 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 965 GENMASK(31, 30)); 966 } 967 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0) 968 static inline void SET_CMC_TBL_NC(void *table, u32 val) 969 { 970 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0)); 971 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC, 972 GENMASK(2, 0)); 973 } 974 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0) 975 static inline void SET_CMC_TBL_NR(void *table, u32 val) 976 { 977 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3)); 978 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR, 979 GENMASK(5, 3)); 980 } 981 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0) 982 static inline void SET_CMC_TBL_NG(void *table, u32 val) 983 { 984 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6)); 985 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG, 986 GENMASK(7, 6)); 987 } 988 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0) 989 static inline void SET_CMC_TBL_CB(void *table, u32 val) 990 { 991 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8)); 992 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB, 993 GENMASK(9, 8)); 994 } 995 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0) 996 static inline void SET_CMC_TBL_CS(void *table, u32 val) 997 { 998 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10)); 999 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS, 1000 GENMASK(11, 10)); 1001 } 1002 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0) 1003 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val) 1004 { 1005 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12)); 1006 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN, 1007 BIT(12)); 1008 } 1009 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0) 1010 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val) 1011 { 1012 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13)); 1013 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN, 1014 BIT(13)); 1015 } 1016 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0) 1017 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val) 1018 { 1019 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14)); 1020 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN, 1021 BIT(14)); 1022 } 1023 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0) 1024 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val) 1025 { 1026 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15)); 1027 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN, 1028 BIT(15)); 1029 } 1030 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0) 1031 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val) 1032 { 1033 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16)); 1034 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE, 1035 GENMASK(24, 16)); 1036 } 1037 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0) 1038 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val) 1039 { 1040 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25)); 1041 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF, 1042 GENMASK(27, 25)); 1043 } 1044 #define SET_CMC_TBL_MASK_CSI_GID_SEL BIT(0) 1045 static inline void SET_CMC_TBL_CSI_GID_SEL(void *table, u32 val) 1046 { 1047 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(29)); 1048 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GID_SEL, 1049 BIT(29)); 1050 } 1051 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0) 1052 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val) 1053 { 1054 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30)); 1055 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW, 1056 GENMASK(31, 30)); 1057 } 1058 1059 static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val) 1060 { 1061 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1062 } 1063 1064 static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val) 1065 { 1066 le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8)); 1067 } 1068 1069 static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val) 1070 { 1071 le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10)); 1072 } 1073 1074 static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val) 1075 { 1076 le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13)); 1077 } 1078 1079 static inline void SET_JOININFO_MACID(void *h2c, u32 val) 1080 { 1081 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1082 } 1083 1084 static inline void SET_JOININFO_OP(void *h2c, u32 val) 1085 { 1086 le32p_replace_bits((__le32 *)h2c, val, BIT(8)); 1087 } 1088 1089 static inline void SET_JOININFO_BAND(void *h2c, u32 val) 1090 { 1091 le32p_replace_bits((__le32 *)h2c, val, BIT(9)); 1092 } 1093 1094 static inline void SET_JOININFO_WMM(void *h2c, u32 val) 1095 { 1096 le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10)); 1097 } 1098 1099 static inline void SET_JOININFO_TGR(void *h2c, u32 val) 1100 { 1101 le32p_replace_bits((__le32 *)h2c, val, BIT(12)); 1102 } 1103 1104 static inline void SET_JOININFO_ISHESTA(void *h2c, u32 val) 1105 { 1106 le32p_replace_bits((__le32 *)h2c, val, BIT(13)); 1107 } 1108 1109 static inline void SET_JOININFO_DLBW(void *h2c, u32 val) 1110 { 1111 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14)); 1112 } 1113 1114 static inline void SET_JOININFO_TF_MAC_PAD(void *h2c, u32 val) 1115 { 1116 le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16)); 1117 } 1118 1119 static inline void SET_JOININFO_DL_T_PE(void *h2c, u32 val) 1120 { 1121 le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18)); 1122 } 1123 1124 static inline void SET_JOININFO_PORT_ID(void *h2c, u32 val) 1125 { 1126 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21)); 1127 } 1128 1129 static inline void SET_JOININFO_NET_TYPE(void *h2c, u32 val) 1130 { 1131 le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24)); 1132 } 1133 1134 static inline void SET_JOININFO_WIFI_ROLE(void *h2c, u32 val) 1135 { 1136 le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26)); 1137 } 1138 1139 static inline void SET_JOININFO_SELF_ROLE(void *h2c, u32 val) 1140 { 1141 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30)); 1142 } 1143 1144 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val) 1145 { 1146 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1147 } 1148 1149 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val) 1150 { 1151 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1152 } 1153 1154 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val) 1155 { 1156 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1157 } 1158 1159 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val) 1160 { 1161 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1162 } 1163 1164 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val) 1165 { 1166 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1167 } 1168 1169 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val) 1170 { 1171 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); 1172 } 1173 1174 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val) 1175 { 1176 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1177 } 1178 1179 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val) 1180 { 1181 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1182 } 1183 1184 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val) 1185 { 1186 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)); 1187 } 1188 1189 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val) 1190 { 1191 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0)); 1192 } 1193 1194 static inline void SET_BA_CAM_VALID(void *h2c, u32 val) 1195 { 1196 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 1197 } 1198 1199 static inline void SET_BA_CAM_INIT_REQ(void *h2c, u32 val) 1200 { 1201 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 1202 } 1203 1204 static inline void SET_BA_CAM_ENTRY_IDX(void *h2c, u32 val) 1205 { 1206 le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2)); 1207 } 1208 1209 static inline void SET_BA_CAM_TID(void *h2c, u32 val) 1210 { 1211 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4)); 1212 } 1213 1214 static inline void SET_BA_CAM_MACID(void *h2c, u32 val) 1215 { 1216 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1217 } 1218 1219 static inline void SET_BA_CAM_BMAP_SIZE(void *h2c, u32 val) 1220 { 1221 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); 1222 } 1223 1224 static inline void SET_BA_CAM_SSN(void *h2c, u32 val) 1225 { 1226 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20)); 1227 } 1228 1229 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val) 1230 { 1231 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1232 } 1233 1234 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val) 1235 { 1236 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1237 } 1238 1239 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val) 1240 { 1241 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); 1242 } 1243 1244 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val) 1245 { 1246 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20)); 1247 } 1248 1249 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val) 1250 { 1251 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1252 } 1253 1254 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val) 1255 { 1256 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0)); 1257 } 1258 1259 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val) 1260 { 1261 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1)); 1262 } 1263 1264 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val) 1265 { 1266 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2)); 1267 } 1268 1269 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val) 1270 { 1271 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3)); 1272 } 1273 1274 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val) 1275 { 1276 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); 1277 } 1278 1279 enum rtw89_btc_btf_h2c_class { 1280 BTFC_SET = 0x10, 1281 BTFC_GET = 0x11, 1282 BTFC_FW_EVENT = 0x12, 1283 }; 1284 1285 enum rtw89_btc_btf_set { 1286 SET_REPORT_EN = 0x0, 1287 SET_SLOT_TABLE, 1288 SET_MREG_TABLE, 1289 SET_CX_POLICY, 1290 SET_GPIO_DBG, 1291 SET_DRV_INFO, 1292 SET_DRV_EVENT, 1293 SET_BT_WREG_ADDR, 1294 SET_BT_WREG_VAL, 1295 SET_BT_RREG_ADDR, 1296 SET_BT_WL_CH_INFO, 1297 SET_BT_INFO_REPORT, 1298 SET_BT_IGNORE_WLAN_ACT, 1299 SET_BT_TX_PWR, 1300 SET_BT_LNA_CONSTRAIN, 1301 SET_BT_GOLDEN_RX_RANGE, 1302 SET_BT_PSD_REPORT, 1303 SET_H2C_TEST, 1304 SET_MAX1, 1305 }; 1306 1307 enum rtw89_btc_cxdrvinfo { 1308 CXDRVINFO_INIT = 0, 1309 CXDRVINFO_ROLE, 1310 CXDRVINFO_DBCC, 1311 CXDRVINFO_SMAP, 1312 CXDRVINFO_RFK, 1313 CXDRVINFO_RUN, 1314 CXDRVINFO_CTRL, 1315 CXDRVINFO_SCAN, 1316 CXDRVINFO_MAX, 1317 }; 1318 1319 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val) 1320 { 1321 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0)); 1322 } 1323 1324 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val) 1325 { 1326 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0)); 1327 } 1328 1329 static inline void RTW89_SET_FWCMD_CXINIT_ANT_TYPE(void *cmd, u8 val) 1330 { 1331 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)); 1332 } 1333 1334 static inline void RTW89_SET_FWCMD_CXINIT_ANT_NUM(void *cmd, u8 val) 1335 { 1336 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)); 1337 } 1338 1339 static inline void RTW89_SET_FWCMD_CXINIT_ANT_ISO(void *cmd, u8 val) 1340 { 1341 u8p_replace_bits((u8 *)(cmd) + 4, val, GENMASK(7, 0)); 1342 } 1343 1344 static inline void RTW89_SET_FWCMD_CXINIT_ANT_POS(void *cmd, u8 val) 1345 { 1346 u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(0)); 1347 } 1348 1349 static inline void RTW89_SET_FWCMD_CXINIT_ANT_DIVERSITY(void *cmd, u8 val) 1350 { 1351 u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(1)); 1352 } 1353 1354 static inline void RTW89_SET_FWCMD_CXINIT_MOD_RFE(void *cmd, u8 val) 1355 { 1356 u8p_replace_bits((u8 *)(cmd) + 6, val, GENMASK(7, 0)); 1357 } 1358 1359 static inline void RTW89_SET_FWCMD_CXINIT_MOD_CV(void *cmd, u8 val) 1360 { 1361 u8p_replace_bits((u8 *)(cmd) + 7, val, GENMASK(7, 0)); 1362 } 1363 1364 static inline void RTW89_SET_FWCMD_CXINIT_MOD_BT_SOLO(void *cmd, u8 val) 1365 { 1366 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(0)); 1367 } 1368 1369 static inline void RTW89_SET_FWCMD_CXINIT_MOD_BT_POS(void *cmd, u8 val) 1370 { 1371 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(1)); 1372 } 1373 1374 static inline void RTW89_SET_FWCMD_CXINIT_MOD_SW_TYPE(void *cmd, u8 val) 1375 { 1376 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(2)); 1377 } 1378 1379 static inline void RTW89_SET_FWCMD_CXINIT_WL_GCH(void *cmd, u8 val) 1380 { 1381 u8p_replace_bits((u8 *)(cmd) + 10, val, GENMASK(7, 0)); 1382 } 1383 1384 static inline void RTW89_SET_FWCMD_CXINIT_WL_ONLY(void *cmd, u8 val) 1385 { 1386 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(0)); 1387 } 1388 1389 static inline void RTW89_SET_FWCMD_CXINIT_WL_INITOK(void *cmd, u8 val) 1390 { 1391 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(1)); 1392 } 1393 1394 static inline void RTW89_SET_FWCMD_CXINIT_DBCC_EN(void *cmd, u8 val) 1395 { 1396 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(2)); 1397 } 1398 1399 static inline void RTW89_SET_FWCMD_CXINIT_CX_OTHER(void *cmd, u8 val) 1400 { 1401 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(3)); 1402 } 1403 1404 static inline void RTW89_SET_FWCMD_CXINIT_BT_ONLY(void *cmd, u8 val) 1405 { 1406 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(4)); 1407 } 1408 1409 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val) 1410 { 1411 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)); 1412 } 1413 1414 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val) 1415 { 1416 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)); 1417 } 1418 1419 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val) 1420 { 1421 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0)); 1422 } 1423 1424 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val) 1425 { 1426 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1)); 1427 } 1428 1429 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val) 1430 { 1431 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2)); 1432 } 1433 1434 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val) 1435 { 1436 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3)); 1437 } 1438 1439 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val) 1440 { 1441 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4)); 1442 } 1443 1444 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val) 1445 { 1446 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5)); 1447 } 1448 1449 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val) 1450 { 1451 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6)); 1452 } 1453 1454 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val) 1455 { 1456 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7)); 1457 } 1458 1459 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val) 1460 { 1461 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8)); 1462 } 1463 1464 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val) 1465 { 1466 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9)); 1467 } 1468 1469 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val) 1470 { 1471 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10)); 1472 } 1473 1474 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val) 1475 { 1476 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11)); 1477 } 1478 1479 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n) 1480 { 1481 u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(0)); 1482 } 1483 1484 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n) 1485 { 1486 u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, GENMASK(3, 1)); 1487 } 1488 1489 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n) 1490 { 1491 u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(4)); 1492 } 1493 1494 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n) 1495 { 1496 u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, BIT(5)); 1497 } 1498 1499 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n) 1500 { 1501 u8p_replace_bits((u8 *)(cmd) + (6 + 12 * (n)), val, GENMASK(7, 6)); 1502 } 1503 1504 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n) 1505 { 1506 u8p_replace_bits((u8 *)(cmd) + (7 + 12 * (n)), val, BIT(0)); 1507 } 1508 1509 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n) 1510 { 1511 u8p_replace_bits((u8 *)(cmd) + (7 + 12 * (n)), val, GENMASK(7, 1)); 1512 } 1513 1514 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n) 1515 { 1516 u8p_replace_bits((u8 *)(cmd) + (8 + 12 * (n)), val, GENMASK(7, 0)); 1517 } 1518 1519 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n) 1520 { 1521 u8p_replace_bits((u8 *)(cmd) + (9 + 12 * (n)), val, GENMASK(7, 0)); 1522 } 1523 1524 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n) 1525 { 1526 le16p_replace_bits((__le16 *)((u8 *)(cmd) + (10 + 12 * (n))), val, GENMASK(15, 0)); 1527 } 1528 1529 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n) 1530 { 1531 le16p_replace_bits((__le16 *)((u8 *)(cmd) + (12 + 12 * (n))), val, GENMASK(15, 0)); 1532 } 1533 1534 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n) 1535 { 1536 le16p_replace_bits((__le16 *)((u8 *)(cmd) + (14 + 12 * (n))), val, GENMASK(15, 0)); 1537 } 1538 1539 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n) 1540 { 1541 le16p_replace_bits((__le16 *)((u8 *)(cmd) + (16 + 12 * (n))), val, GENMASK(15, 0)); 1542 } 1543 1544 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val) 1545 { 1546 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0)); 1547 } 1548 1549 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val) 1550 { 1551 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1)); 1552 } 1553 1554 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val) 1555 { 1556 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2)); 1557 } 1558 1559 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val) 1560 { 1561 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3)); 1562 } 1563 1564 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val) 1565 { 1566 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0)); 1567 } 1568 1569 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val) 1570 { 1571 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2)); 1572 } 1573 1574 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val) 1575 { 1576 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6)); 1577 } 1578 1579 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val) 1580 { 1581 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8)); 1582 } 1583 1584 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val) 1585 { 1586 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10)); 1587 } 1588 1589 #define RTW89_C2H_HEADER_LEN 8 1590 1591 #define RTW89_GET_C2H_CATEGORY(c2h) \ 1592 le32_get_bits(*((const __le32 *)c2h), GENMASK(1, 0)) 1593 #define RTW89_GET_C2H_CLASS(c2h) \ 1594 le32_get_bits(*((const __le32 *)c2h), GENMASK(7, 2)) 1595 #define RTW89_GET_C2H_FUNC(c2h) \ 1596 le32_get_bits(*((const __le32 *)c2h), GENMASK(15, 8)) 1597 #define RTW89_GET_C2H_LEN(c2h) \ 1598 le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(13, 0)) 1599 1600 #define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2) 1601 #define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN) 1602 1603 #define RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h) \ 1604 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 1605 #define RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h) \ 1606 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 1607 #define RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h) \ 1608 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 1609 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h) \ 1610 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 1611 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h) \ 1612 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24)) 1613 1614 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \ 1615 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 1616 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \ 1617 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 1618 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \ 1619 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 1620 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \ 1621 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 1622 1623 #define RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h) \ 1624 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 0)) 1625 #define RTW89_GET_PHY_C2H_RA_RPT_RETRY_RATIO(c2h) \ 1626 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 1627 #define RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h) \ 1628 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(6, 0)) 1629 #define RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h) \ 1630 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(9, 8)) 1631 #define RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h) \ 1632 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(12, 10)) 1633 #define RTW89_GET_PHY_C2H_RA_RPT_BW(c2h) \ 1634 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(14, 13)) 1635 1636 /* VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS 1637 * HT-new: [6:5]: NA, [4:0]: MCS 1638 */ 1639 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4) 1640 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0) 1641 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0) 1642 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \ 1643 FIELD_PREP(GENMASK(2, 0), mcs)) 1644 1645 #define RTW89_FW_HDR_SIZE 32 1646 #define RTW89_FW_SECTION_HDR_SIZE 16 1647 1648 #define RTW89_MFW_SIG 0xFF 1649 1650 struct rtw89_mfw_info { 1651 u8 cv; 1652 u8 type; /* enum rtw89_fw_type */ 1653 u8 mp; 1654 u8 rsvd; 1655 __le32 shift; 1656 __le32 size; 1657 u8 rsvd2[4]; 1658 } __packed; 1659 1660 struct rtw89_mfw_hdr { 1661 u8 sig; /* RTW89_MFW_SIG */ 1662 u8 fw_nr; 1663 u8 rsvd[14]; 1664 struct rtw89_mfw_info info[]; 1665 } __packed; 1666 1667 struct fwcmd_hdr { 1668 __le32 hdr0; 1669 __le32 hdr1; 1670 }; 1671 1672 #define RTW89_H2C_RF_PAGE_SIZE 500 1673 #define RTW89_H2C_RF_PAGE_NUM 3 1674 struct rtw89_fw_h2c_rf_reg_info { 1675 enum rtw89_rf_path rf_path; 1676 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE]; 1677 u16 curr_idx; 1678 }; 1679 1680 #define H2C_SEC_CAM_LEN 24 1681 1682 #define H2C_HEADER_LEN 8 1683 #define H2C_HDR_CAT GENMASK(1, 0) 1684 #define H2C_HDR_CLASS GENMASK(7, 2) 1685 #define H2C_HDR_FUNC GENMASK(15, 8) 1686 #define H2C_HDR_DEL_TYPE GENMASK(19, 16) 1687 #define H2C_HDR_H2C_SEQ GENMASK(31, 24) 1688 #define H2C_HDR_TOTAL_LEN GENMASK(13, 0) 1689 #define H2C_HDR_REC_ACK BIT(14) 1690 #define H2C_HDR_DONE_ACK BIT(15) 1691 1692 #define FWCMD_TYPE_H2C 0 1693 1694 #define H2C_CAT_MAC 0x1 1695 1696 /* CLASS 0 - FW INFO */ 1697 #define H2C_CL_FW_INFO 0x0 1698 #define H2C_FUNC_LOG_CFG 0x0 1699 #define H2C_FUNC_MAC_GENERAL_PKT 0x1 1700 1701 /* CLASS 2 - PS */ 1702 #define H2C_CL_MAC_PS 0x2 1703 #define H2C_FUNC_MAC_LPS_PARM 0x0 1704 1705 /* CLASS 3 - FW download */ 1706 #define H2C_CL_MAC_FWDL 0x3 1707 #define H2C_FUNC_MAC_FWHDR_DL 0x0 1708 1709 /* CLASS 5 - Frame Exchange */ 1710 #define H2C_CL_MAC_FR_EXCHG 0x5 1711 #define H2C_FUNC_MAC_CCTLINFO_UD 0x2 1712 1713 /* CLASS 6 - Address CAM */ 1714 #define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6 1715 #define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0 1716 1717 /* CLASS 8 - Media Status Report */ 1718 #define H2C_CL_MAC_MEDIA_RPT 0x8 1719 #define H2C_FUNC_MAC_JOININFO 0x0 1720 #define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4 1721 1722 /* CLASS 9 - FW offload */ 1723 #define H2C_CL_MAC_FW_OFLD 0x9 1724 #define H2C_FUNC_MAC_MACID_PAUSE 0x8 1725 #define H2C_FUNC_USR_EDCA 0xF 1726 #define H2C_FUNC_OFLD_CFG 0x14 1727 1728 /* CLASS 10 - Security CAM */ 1729 #define H2C_CL_MAC_SEC_CAM 0xa 1730 #define H2C_FUNC_MAC_SEC_UPD 0x1 1731 1732 /* CLASS 12 - BA CAM */ 1733 #define H2C_CL_BA_CAM 0xc 1734 #define H2C_FUNC_MAC_BA_CAM 0x0 1735 1736 #define H2C_CAT_OUTSRC 0x2 1737 1738 #define H2C_CL_OUTSRC_RA 0x1 1739 #define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0 1740 1741 #define H2C_CL_OUTSRC_RF_REG_A 0x8 1742 #define H2C_CL_OUTSRC_RF_REG_B 0x9 1743 1744 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev); 1745 int rtw89_fw_recognize(struct rtw89_dev *rtwdev); 1746 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type); 1747 int rtw89_load_firmware(struct rtw89_dev *rtwdev); 1748 void rtw89_unload_firmware(struct rtw89_dev *rtwdev); 1749 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev); 1750 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1751 u8 type, u8 cat, u8 class, u8 func, 1752 bool rack, bool dack, u32 len); 1753 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, u8 macid); 1754 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, 1755 struct ieee80211_vif *vif, 1756 struct ieee80211_sta *sta); 1757 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev, 1758 struct rtw89_sta *rtwsta); 1759 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif, 1760 struct rtw89_sta *rtwsta, const u8 *scan_mac_addr); 1761 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h); 1762 void rtw89_fw_c2h_work(struct work_struct *work); 1763 int rtw89_fw_h2c_vif_maintain(struct rtw89_dev *rtwdev, 1764 struct rtw89_vif *rtwvif, 1765 enum rtw89_upd_mode upd_mode); 1766 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1767 u8 dis_conn); 1768 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp, 1769 bool pause); 1770 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 1771 u8 ac, u32 val); 1772 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev); 1773 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi); 1774 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev); 1775 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev); 1776 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev); 1777 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev); 1778 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev, 1779 struct rtw89_fw_h2c_rf_reg_info *info, 1780 u16 len, u8 page); 1781 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, 1782 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, 1783 bool rack, bool dack); 1784 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len); 1785 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev); 1786 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev); 1787 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, u8 macid); 1788 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, bool valid, u8 macid, 1789 struct ieee80211_ampdu_params *params); 1790 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev, 1791 struct rtw89_lps_parm *lps_param); 1792 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(u32 len); 1793 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(u32 len); 1794 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev, 1795 struct rtw89_mac_h2c_info *h2c_info, 1796 struct rtw89_mac_c2h_info *c2h_info); 1797 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable); 1798 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev); 1799 1800 #endif 1801