1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_FW_H__ 6 #define __RTW89_FW_H__ 7 8 #include "core.h" 9 10 enum rtw89_fw_dl_status { 11 RTW89_FWDL_INITIAL_STATE = 0, 12 RTW89_FWDL_FWDL_ONGOING = 1, 13 RTW89_FWDL_CHECKSUM_FAIL = 2, 14 RTW89_FWDL_SECURITY_FAIL = 3, 15 RTW89_FWDL_CV_NOT_MATCH = 4, 16 RTW89_FWDL_RSVD0 = 5, 17 RTW89_FWDL_WCPU_FWDL_RDY = 6, 18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7 19 }; 20 21 struct rtw89_c2hreg_hdr { 22 u32 w0; 23 }; 24 25 #define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0) 26 #define RTW89_C2HREG_HDR_ACK BIT(7) 27 #define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8) 28 #define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12) 29 30 struct rtw89_c2hreg_phycap { 31 u32 w0; 32 u32 w1; 33 u32 w2; 34 u32 w3; 35 } __packed; 36 37 #define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0) 38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7) 39 #define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8) 40 #define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12) 41 #define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16) 42 #define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24) 43 #define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0) 44 #define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8) 45 #define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16) 46 #define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24) 47 #define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0) 48 #define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8) 49 #define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16) 50 51 struct rtw89_h2creg_hdr { 52 u32 w0; 53 }; 54 55 #define RTW89_H2CREG_HDR_FUNC_MASK GENMASK(6, 0) 56 #define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8) 57 58 struct rtw89_h2creg_sch_tx_en { 59 u32 w0; 60 u32 w1; 61 } __packed; 62 63 #define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16) 64 #define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0) 65 #define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16) 66 67 #define RTW89_H2CREG_MAX 4 68 #define RTW89_C2HREG_MAX 4 69 #define RTW89_C2HREG_HDR_LEN 2 70 #define RTW89_H2CREG_HDR_LEN 2 71 #define RTW89_C2H_TIMEOUT 1000000 72 struct rtw89_mac_c2h_info { 73 u8 id; 74 u8 content_len; 75 union { 76 u32 c2hreg[RTW89_C2HREG_MAX]; 77 struct rtw89_c2hreg_hdr hdr; 78 struct rtw89_c2hreg_phycap phycap; 79 } u; 80 }; 81 82 struct rtw89_mac_h2c_info { 83 u8 id; 84 u8 content_len; 85 union { 86 u32 h2creg[RTW89_H2CREG_MAX]; 87 struct rtw89_h2creg_hdr hdr; 88 struct rtw89_h2creg_sch_tx_en sch_tx_en; 89 } u; 90 }; 91 92 enum rtw89_mac_h2c_type { 93 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0, 94 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD, 95 RTW89_FWCMD_H2CREG_FUNC_FWERR, 96 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE, 97 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM, 98 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN 99 }; 100 101 enum rtw89_mac_c2h_type { 102 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0, 103 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT, 104 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG, 105 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP, 106 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT, 107 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF 108 }; 109 110 enum rtw89_fw_c2h_category { 111 RTW89_C2H_CAT_TEST, 112 RTW89_C2H_CAT_MAC, 113 RTW89_C2H_CAT_OUTSRC, 114 }; 115 116 enum rtw89_fw_log_level { 117 RTW89_FW_LOG_LEVEL_OFF, 118 RTW89_FW_LOG_LEVEL_CRT, 119 RTW89_FW_LOG_LEVEL_SER, 120 RTW89_FW_LOG_LEVEL_WARN, 121 RTW89_FW_LOG_LEVEL_LOUD, 122 RTW89_FW_LOG_LEVEL_TR, 123 }; 124 125 enum rtw89_fw_log_path { 126 RTW89_FW_LOG_LEVEL_UART, 127 RTW89_FW_LOG_LEVEL_C2H, 128 RTW89_FW_LOG_LEVEL_SNI, 129 }; 130 131 enum rtw89_fw_log_comp { 132 RTW89_FW_LOG_COMP_VER, 133 RTW89_FW_LOG_COMP_INIT, 134 RTW89_FW_LOG_COMP_TASK, 135 RTW89_FW_LOG_COMP_CNS, 136 RTW89_FW_LOG_COMP_H2C, 137 RTW89_FW_LOG_COMP_C2H, 138 RTW89_FW_LOG_COMP_TX, 139 RTW89_FW_LOG_COMP_RX, 140 RTW89_FW_LOG_COMP_IPSEC, 141 RTW89_FW_LOG_COMP_TIMER, 142 RTW89_FW_LOG_COMP_DBGPKT, 143 RTW89_FW_LOG_COMP_PS, 144 RTW89_FW_LOG_COMP_ERROR, 145 RTW89_FW_LOG_COMP_WOWLAN, 146 RTW89_FW_LOG_COMP_SECURE_BOOT, 147 RTW89_FW_LOG_COMP_BTC, 148 RTW89_FW_LOG_COMP_BB, 149 RTW89_FW_LOG_COMP_TWT, 150 RTW89_FW_LOG_COMP_RF, 151 RTW89_FW_LOG_COMP_MCC = 20, 152 }; 153 154 enum rtw89_pkt_offload_op { 155 RTW89_PKT_OFLD_OP_ADD, 156 RTW89_PKT_OFLD_OP_DEL, 157 RTW89_PKT_OFLD_OP_READ, 158 159 NUM_OF_RTW89_PKT_OFFLOAD_OP, 160 }; 161 162 #define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) \ 163 ((pkt_id) * NUM_OF_RTW89_PKT_OFFLOAD_OP + (pkt_op)) 164 165 enum rtw89_scanofld_notify_reason { 166 RTW89_SCAN_DWELL_NOTIFY, 167 RTW89_SCAN_PRE_TX_NOTIFY, 168 RTW89_SCAN_POST_TX_NOTIFY, 169 RTW89_SCAN_ENTER_CH_NOTIFY, 170 RTW89_SCAN_LEAVE_CH_NOTIFY, 171 RTW89_SCAN_END_SCAN_NOTIFY, 172 }; 173 174 enum rtw89_chan_type { 175 RTW89_CHAN_OPERATE = 0, 176 RTW89_CHAN_ACTIVE, 177 RTW89_CHAN_DFS, 178 }; 179 180 enum rtw89_p2pps_action { 181 RTW89_P2P_ACT_INIT = 0, 182 RTW89_P2P_ACT_UPDATE = 1, 183 RTW89_P2P_ACT_REMOVE = 2, 184 RTW89_P2P_ACT_TERMINATE = 3, 185 }; 186 187 enum rtw89_bcn_fltr_offload_mode { 188 RTW89_BCN_FLTR_OFFLOAD_MODE_0 = 0, 189 RTW89_BCN_FLTR_OFFLOAD_MODE_1, 190 RTW89_BCN_FLTR_OFFLOAD_MODE_2, 191 RTW89_BCN_FLTR_OFFLOAD_MODE_3, 192 193 RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT = RTW89_BCN_FLTR_OFFLOAD_MODE_0, 194 }; 195 196 enum rtw89_bcn_fltr_type { 197 RTW89_BCN_FLTR_BEACON_LOSS, 198 RTW89_BCN_FLTR_RSSI, 199 RTW89_BCN_FLTR_NOTIFY, 200 }; 201 202 enum rtw89_bcn_fltr_rssi_event { 203 RTW89_BCN_FLTR_RSSI_NOT_CHANGED, 204 RTW89_BCN_FLTR_RSSI_HIGH, 205 RTW89_BCN_FLTR_RSSI_LOW, 206 }; 207 208 #define FWDL_SECTION_MAX_NUM 10 209 #define FWDL_SECTION_CHKSUM_LEN 8 210 #define FWDL_SECTION_PER_PKT_LEN 2020 211 212 struct rtw89_fw_hdr_section_info { 213 u8 redl; 214 const u8 *addr; 215 u32 len; 216 u32 dladdr; 217 u32 mssc; 218 u8 type; 219 }; 220 221 struct rtw89_fw_bin_info { 222 u8 section_num; 223 u32 hdr_len; 224 bool dynamic_hdr_en; 225 u32 dynamic_hdr_len; 226 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM]; 227 }; 228 229 struct rtw89_fw_macid_pause_grp { 230 __le32 pause_grp[4]; 231 __le32 mask_grp[4]; 232 } __packed; 233 234 #define RTW89_H2C_MAX_SIZE 2048 235 #define RTW89_CHANNEL_TIME 45 236 #define RTW89_CHANNEL_TIME_6G 20 237 #define RTW89_DFS_CHAN_TIME 105 238 #define RTW89_OFF_CHAN_TIME 100 239 #define RTW89_DWELL_TIME 20 240 #define RTW89_DWELL_TIME_6G 10 241 #define RTW89_SCAN_WIDTH 0 242 #define RTW89_SCANOFLD_MAX_SSID 8 243 #define RTW89_SCANOFLD_MAX_IE_LEN 512 244 #define RTW89_SCANOFLD_PKT_NONE 0xFF 245 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F 246 #define RTW89_MAC_CHINFO_SIZE 28 247 #define RTW89_SCAN_LIST_GUARD 4 248 #define RTW89_SCAN_LIST_LIMIT \ 249 ((RTW89_H2C_MAX_SIZE / RTW89_MAC_CHINFO_SIZE) - RTW89_SCAN_LIST_GUARD) 250 251 #define RTW89_BCN_LOSS_CNT 10 252 253 struct rtw89_mac_chinfo { 254 u8 period; 255 u8 dwell_time; 256 u8 central_ch; 257 u8 pri_ch; 258 u8 bw:3; 259 u8 notify_action:5; 260 u8 num_pkt:4; 261 u8 tx_pkt:1; 262 u8 pause_data:1; 263 u8 ch_band:2; 264 u8 probe_id; 265 u8 dfs_ch:1; 266 u8 tx_null:1; 267 u8 rand_seq_num:1; 268 u8 cfg_tx_pwr:1; 269 u8 rsvd0: 4; 270 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID]; 271 u16 tx_pwr_idx; 272 u8 rsvd1; 273 struct list_head list; 274 bool is_psc; 275 }; 276 277 struct rtw89_scan_option { 278 bool enable; 279 bool target_ch_mode; 280 }; 281 282 struct rtw89_pktofld_info { 283 struct list_head list; 284 u8 id; 285 286 /* Below fields are for 6 GHz RNR use only */ 287 u8 ssid[IEEE80211_MAX_SSID_LEN]; 288 u8 ssid_len; 289 u8 bssid[ETH_ALEN]; 290 u16 channel_6ghz; 291 bool cancel; 292 }; 293 294 static inline void RTW89_SET_FWCMD_RA_IS_DIS(void *cmd, u32 val) 295 { 296 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(0)); 297 } 298 299 static inline void RTW89_SET_FWCMD_RA_MODE(void *cmd, u32 val) 300 { 301 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(5, 1)); 302 } 303 304 static inline void RTW89_SET_FWCMD_RA_BW_CAP(void *cmd, u32 val) 305 { 306 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 6)); 307 } 308 309 static inline void RTW89_SET_FWCMD_RA_MACID(void *cmd, u32 val) 310 { 311 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); 312 } 313 314 static inline void RTW89_SET_FWCMD_RA_DCM(void *cmd, u32 val) 315 { 316 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(16)); 317 } 318 319 static inline void RTW89_SET_FWCMD_RA_ER(void *cmd, u32 val) 320 { 321 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(17)); 322 } 323 324 static inline void RTW89_SET_FWCMD_RA_INIT_RATE_LV(void *cmd, u32 val) 325 { 326 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(19, 18)); 327 } 328 329 static inline void RTW89_SET_FWCMD_RA_UPD_ALL(void *cmd, u32 val) 330 { 331 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(20)); 332 } 333 334 static inline void RTW89_SET_FWCMD_RA_SGI(void *cmd, u32 val) 335 { 336 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(21)); 337 } 338 339 static inline void RTW89_SET_FWCMD_RA_LDPC(void *cmd, u32 val) 340 { 341 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(22)); 342 } 343 344 static inline void RTW89_SET_FWCMD_RA_STBC(void *cmd, u32 val) 345 { 346 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(23)); 347 } 348 349 static inline void RTW89_SET_FWCMD_RA_SS_NUM(void *cmd, u32 val) 350 { 351 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(26, 24)); 352 } 353 354 static inline void RTW89_SET_FWCMD_RA_GILTF(void *cmd, u32 val) 355 { 356 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(29, 27)); 357 } 358 359 static inline void RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(void *cmd, u32 val) 360 { 361 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(30)); 362 } 363 364 static inline void RTW89_SET_FWCMD_RA_UPD_MASK(void *cmd, u32 val) 365 { 366 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(31)); 367 } 368 369 static inline void RTW89_SET_FWCMD_RA_MASK_0(void *cmd, u32 val) 370 { 371 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(7, 0)); 372 } 373 374 static inline void RTW89_SET_FWCMD_RA_MASK_1(void *cmd, u32 val) 375 { 376 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(15, 8)); 377 } 378 379 static inline void RTW89_SET_FWCMD_RA_MASK_2(void *cmd, u32 val) 380 { 381 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(23, 16)); 382 } 383 384 static inline void RTW89_SET_FWCMD_RA_MASK_3(void *cmd, u32 val) 385 { 386 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 24)); 387 } 388 389 static inline void RTW89_SET_FWCMD_RA_MASK_4(void *cmd, u32 val) 390 { 391 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(7, 0)); 392 } 393 394 static inline void RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(void *cmd, u32 val) 395 { 396 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, BIT(31)); 397 } 398 399 static inline void RTW89_SET_FWCMD_RA_BAND_NUM(void *cmd, u32 val) 400 { 401 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(7, 0)); 402 } 403 404 static inline void RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(void *cmd, u32 val) 405 { 406 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(8)); 407 } 408 409 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(void *cmd, u32 val) 410 { 411 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(9)); 412 } 413 414 static inline void RTW89_SET_FWCMD_RA_CR_TBL_SEL(void *cmd, u32 val) 415 { 416 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(10)); 417 } 418 419 static inline void RTW89_SET_FWCMD_RA_FIX_GILTF_EN(void *cmd, u32 val) 420 { 421 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(11)); 422 } 423 424 static inline void RTW89_SET_FWCMD_RA_FIX_GILTF(void *cmd, u32 val) 425 { 426 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(14, 12)); 427 } 428 429 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(void *cmd, u32 val) 430 { 431 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(23, 16)); 432 } 433 434 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(void *cmd, u32 val) 435 { 436 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(25, 24)); 437 } 438 439 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(void *cmd, u32 val) 440 { 441 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(28, 26)); 442 } 443 444 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_BW(void *cmd, u32 val) 445 { 446 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 29)); 447 } 448 449 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val) 450 { 451 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)); 452 } 453 454 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val) 455 { 456 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); 457 } 458 459 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val) 460 { 461 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)); 462 } 463 464 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val) 465 { 466 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0)); 467 } 468 469 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val) 470 { 471 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4)); 472 } 473 474 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val) 475 { 476 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5)); 477 } 478 479 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val) 480 { 481 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0)); 482 } 483 484 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val) 485 { 486 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0)); 487 } 488 489 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val) 490 { 491 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0)); 492 } 493 494 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val) 495 { 496 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0)); 497 } 498 499 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val) 500 { 501 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0)); 502 } 503 504 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val) 505 { 506 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3)); 507 } 508 509 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val) 510 { 511 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4)); 512 } 513 514 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val) 515 { 516 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5)); 517 } 518 519 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val) 520 { 521 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0)); 522 } 523 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16) 524 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12) 525 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8) 526 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0) 527 528 #define FWDL_SECURITY_SECTION_TYPE 9 529 #define FWDL_SECURITY_SIGLEN 512 530 531 #define GET_FWSECTION_HDR_DL_ADDR(fwhdr) \ 532 le32_get_bits(*((const __le32 *)(fwhdr)), GENMASK(31, 0)) 533 #define GET_FWSECTION_HDR_SECTIONTYPE(fwhdr) \ 534 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(27, 24)) 535 #define GET_FWSECTION_HDR_SEC_SIZE(fwhdr) \ 536 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 0)) 537 #define GET_FWSECTION_HDR_CHECKSUM(fwhdr) \ 538 le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(28)) 539 #define GET_FWSECTION_HDR_REDL(fwhdr) \ 540 le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(29)) 541 #define GET_FWSECTION_HDR_MSSC(fwhdr) \ 542 le32_get_bits(*((const __le32 *)(fwhdr) + 2), GENMASK(31, 0)) 543 544 #define GET_FW_HDR_MAJOR_VERSION(fwhdr) \ 545 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(7, 0)) 546 #define GET_FW_HDR_MINOR_VERSION(fwhdr) \ 547 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(15, 8)) 548 #define GET_FW_HDR_SUBVERSION(fwhdr) \ 549 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 16)) 550 #define GET_FW_HDR_SUBINDEX(fwhdr) \ 551 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(31, 24)) 552 #define GET_FW_HDR_LEN(fwhdr) \ 553 le32_get_bits(*((const __le32 *)(fwhdr) + 3), GENMASK(23, 16)) 554 #define GET_FW_HDR_MONTH(fwhdr) \ 555 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(7, 0)) 556 #define GET_FW_HDR_DATE(fwhdr) \ 557 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(15, 8)) 558 #define GET_FW_HDR_HOUR(fwhdr) \ 559 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(23, 16)) 560 #define GET_FW_HDR_MIN(fwhdr) \ 561 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(31, 24)) 562 #define GET_FW_HDR_YEAR(fwhdr) \ 563 le32_get_bits(*((const __le32 *)(fwhdr) + 5), GENMASK(31, 0)) 564 #define GET_FW_HDR_SEC_NUM(fwhdr) \ 565 le32_get_bits(*((const __le32 *)(fwhdr) + 6), GENMASK(15, 8)) 566 #define GET_FW_HDR_DYN_HDR(fwhdr) \ 567 le32_get_bits(*((const __le32 *)(fwhdr) + 7), BIT(16)) 568 #define GET_FW_HDR_CMD_VERSERION(fwhdr) \ 569 le32_get_bits(*((const __le32 *)(fwhdr) + 7), GENMASK(31, 24)) 570 571 #define GET_FW_DYNHDR_LEN(fwdynhdr) \ 572 le32_get_bits(*((const __le32 *)(fwdynhdr)), GENMASK(31, 0)) 573 #define GET_FW_DYNHDR_COUNT(fwdynhdr) \ 574 le32_get_bits(*((const __le32 *)(fwdynhdr) + 1), GENMASK(31, 0)) 575 576 static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val) 577 { 578 le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0)); 579 } 580 581 static inline void SET_CTRL_INFO_MACID(void *table, u32 val) 582 { 583 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)); 584 } 585 586 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val) 587 { 588 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); 589 } 590 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0) 591 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val) 592 { 593 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0)); 594 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE, 595 GENMASK(8, 0)); 596 } 597 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0) 598 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val) 599 { 600 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9)); 601 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP, 602 BIT(9)); 603 } 604 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0) 605 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val) 606 { 607 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10)); 608 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW, 609 GENMASK(11, 10)); 610 } 611 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0) 612 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val) 613 { 614 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12)); 615 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF, 616 GENMASK(14, 12)); 617 } 618 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0) 619 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val) 620 { 621 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); 622 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX, 623 BIT(15)); 624 } 625 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0) 626 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val) 627 { 628 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16)); 629 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL, 630 GENMASK(19, 16)); 631 } 632 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0) 633 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val) 634 { 635 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20)); 636 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN, 637 BIT(20)); 638 } 639 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0) 640 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val) 641 { 642 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21)); 643 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN, 644 BIT(21)); 645 } 646 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0) 647 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val) 648 { 649 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22)); 650 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN, 651 BIT(22)); 652 } 653 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0) 654 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val) 655 { 656 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23)); 657 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN, 658 BIT(23)); 659 } 660 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0) 661 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val) 662 { 663 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25)); 664 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB, 665 BIT(25)); 666 } 667 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0) 668 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val) 669 { 670 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26)); 671 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB, 672 BIT(26)); 673 } 674 #define SET_CMC_TBL_MASK_TRYRATE BIT(0) 675 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val) 676 { 677 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27)); 678 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE, 679 BIT(27)); 680 } 681 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0) 682 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val) 683 { 684 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28)); 685 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY, 686 GENMASK(31, 28)); 687 } 688 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0) 689 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val) 690 { 691 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0)); 692 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE, 693 GENMASK(8, 0)); 694 } 695 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0) 696 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val) 697 { 698 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9)); 699 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL, 700 BIT(9)); 701 } 702 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0) 703 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val) 704 { 705 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10)); 706 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL, 707 BIT(10)); 708 } 709 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0) 710 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val) 711 { 712 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11)); 713 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL, 714 BIT(11)); 715 } 716 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0) 717 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val) 718 { 719 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12)); 720 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT, 721 GENMASK(15, 12)); 722 } 723 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0) 724 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val) 725 { 726 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16)); 727 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE, 728 GENMASK(24, 16)); 729 } 730 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0) 731 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val) 732 { 733 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27)); 734 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC, 735 BIT(27)); 736 } 737 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0) 738 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val) 739 { 740 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28)); 741 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE, 742 GENMASK(31, 28)); 743 } 744 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0) 745 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val) 746 { 747 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0)); 748 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT, 749 GENMASK(5, 0)); 750 } 751 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0) 752 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val) 753 { 754 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6)); 755 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL, 756 BIT(6)); 757 } 758 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0) 759 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val) 760 { 761 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7)); 762 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL, 763 BIT(7)); 764 } 765 #define SET_CMC_TBL_MASK_RTS_EN BIT(0) 766 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val) 767 { 768 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8)); 769 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN, 770 BIT(8)); 771 } 772 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0) 773 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val) 774 { 775 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9)); 776 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN, 777 BIT(9)); 778 } 779 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0) 780 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val) 781 { 782 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10)); 783 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS, 784 GENMASK(11, 10)); 785 } 786 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0) 787 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val) 788 { 789 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12)); 790 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN, 791 BIT(12)); 792 } 793 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0) 794 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val) 795 { 796 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13)); 797 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE, 798 GENMASK(14, 13)); 799 } 800 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0) 801 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val) 802 { 803 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16)); 804 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN, 805 GENMASK(26, 16)); 806 } 807 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0) 808 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val) 809 { 810 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); 811 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS, 812 BIT(27)); 813 } 814 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0) 815 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val) 816 { 817 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28)); 818 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME, 819 GENMASK(31, 28)); 820 } 821 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0) 822 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val) 823 { 824 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0)); 825 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM, 826 GENMASK(7, 0)); 827 } 828 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0) 829 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val) 830 { 831 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8)); 832 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP, 833 GENMASK(9, 8)); 834 } 835 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0) 836 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val) 837 { 838 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16)); 839 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL, 840 GENMASK(18, 16)); 841 } 842 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0) 843 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val) 844 { 845 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19)); 846 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL, 847 GENMASK(21, 19)); 848 } 849 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0) 850 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val) 851 { 852 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22)); 853 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL, 854 GENMASK(24, 22)); 855 } 856 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0) 857 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val) 858 { 859 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25)); 860 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL, 861 GENMASK(27, 25)); 862 } 863 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0) 864 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val) 865 { 866 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28)); 867 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE, 868 GENMASK(31, 28)); 869 } 870 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0) 871 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val) 872 { 873 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0)); 874 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID, 875 GENMASK(2, 0)); 876 } 877 #define SET_CMC_TBL_MASK_BMC BIT(0) 878 static inline void SET_CMC_TBL_BMC(void *table, u32 val) 879 { 880 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3)); 881 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC, 882 BIT(3)); 883 } 884 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0) 885 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val) 886 { 887 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4)); 888 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID, 889 GENMASK(7, 4)); 890 } 891 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0) 892 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val) 893 { 894 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); 895 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR, 896 BIT(8)); 897 } 898 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0) 899 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val) 900 { 901 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9)); 902 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE, 903 GENMASK(11, 9)); 904 } 905 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0) 906 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val) 907 { 908 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12)); 909 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM, 910 BIT(12)); 911 } 912 #define SET_CMC_TBL_MASK_DATA_ER BIT(0) 913 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val) 914 { 915 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13)); 916 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER, 917 BIT(13)); 918 } 919 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0) 920 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val) 921 { 922 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14)); 923 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC, 924 BIT(14)); 925 } 926 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0) 927 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val) 928 { 929 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); 930 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC, 931 BIT(15)); 932 } 933 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0) 934 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val) 935 { 936 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16)); 937 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR, 938 BIT(16)); 939 } 940 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0) 941 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val) 942 { 943 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17)); 944 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH, 945 BIT(17)); 946 } 947 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0) 948 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val) 949 { 950 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18)); 951 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR, 952 BIT(18)); 953 } 954 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0) 955 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val) 956 { 957 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19)); 958 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS, 959 BIT(19)); 960 } 961 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0) 962 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val) 963 { 964 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20)); 965 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER, 966 BIT(20)); 967 } 968 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0) 969 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val) 970 { 971 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21)); 972 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN, 973 BIT(21)); 974 } 975 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0) 976 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val) 977 { 978 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27)); 979 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD, 980 BIT(27)); 981 } 982 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0) 983 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val) 984 { 985 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28)); 986 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT, 987 GENMASK(31, 28)); 988 } 989 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0) 990 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val) 991 { 992 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0)); 993 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE, 994 GENMASK(8, 0)); 995 } 996 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0) 997 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val) 998 { 999 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12)); 1000 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT, 1001 BIT(12)); 1002 } 1003 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0) 1004 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val) 1005 { 1006 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13)); 1007 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT, 1008 BIT(13)); 1009 } 1010 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0) 1011 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val) 1012 { 1013 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16)); 1014 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN, 1015 GENMASK(19, 16)); 1016 } 1017 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0) 1018 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val) 1019 { 1020 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20)); 1021 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A, 1022 GENMASK(21, 20)); 1023 } 1024 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0) 1025 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val) 1026 { 1027 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22)); 1028 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B, 1029 GENMASK(23, 22)); 1030 } 1031 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0) 1032 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val) 1033 { 1034 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24)); 1035 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C, 1036 GENMASK(25, 24)); 1037 } 1038 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0) 1039 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val) 1040 { 1041 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26)); 1042 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D, 1043 GENMASK(27, 26)); 1044 } 1045 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0) 1046 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val) 1047 { 1048 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28)); 1049 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A, 1050 BIT(28)); 1051 } 1052 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0) 1053 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val) 1054 { 1055 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29)); 1056 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B, 1057 BIT(29)); 1058 } 1059 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0) 1060 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val) 1061 { 1062 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30)); 1063 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C, 1064 BIT(30)); 1065 } 1066 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0) 1067 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val) 1068 { 1069 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31)); 1070 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D, 1071 BIT(31)); 1072 } 1073 1074 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0) 1075 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val) 1076 { 1077 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0)); 1078 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1079 GENMASK(1, 0)); 1080 } 1081 1082 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val) 1083 { 1084 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2)); 1085 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1086 GENMASK(3, 2)); 1087 } 1088 1089 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val) 1090 { 1091 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4)); 1092 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1093 GENMASK(5, 4)); 1094 } 1095 1096 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val) 1097 { 1098 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6)); 1099 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1100 GENMASK(7, 6)); 1101 } 1102 1103 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0) 1104 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val) 1105 { 1106 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); 1107 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX, 1108 GENMASK(7, 0)); 1109 } 1110 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0) 1111 static inline void SET_CMC_TBL_PAID(void *table, u32 val) 1112 { 1113 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8)); 1114 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID, 1115 GENMASK(16, 8)); 1116 } 1117 #define SET_CMC_TBL_MASK_ULDL BIT(0) 1118 static inline void SET_CMC_TBL_ULDL(void *table, u32 val) 1119 { 1120 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17)); 1121 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL, 1122 BIT(17)); 1123 } 1124 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0) 1125 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val) 1126 { 1127 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18)); 1128 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL, 1129 GENMASK(19, 18)); 1130 } 1131 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val) 1132 { 1133 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20)); 1134 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1135 GENMASK(21, 20)); 1136 } 1137 1138 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val) 1139 { 1140 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22)); 1141 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1142 GENMASK(23, 22)); 1143 } 1144 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0) 1145 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val) 1146 { 1147 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24)); 1148 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE, 1149 GENMASK(27, 24)); 1150 } 1151 1152 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val) 1153 { 1154 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30)); 1155 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1156 GENMASK(31, 30)); 1157 } 1158 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0) 1159 static inline void SET_CMC_TBL_NC(void *table, u32 val) 1160 { 1161 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0)); 1162 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC, 1163 GENMASK(2, 0)); 1164 } 1165 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0) 1166 static inline void SET_CMC_TBL_NR(void *table, u32 val) 1167 { 1168 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3)); 1169 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR, 1170 GENMASK(5, 3)); 1171 } 1172 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0) 1173 static inline void SET_CMC_TBL_NG(void *table, u32 val) 1174 { 1175 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6)); 1176 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG, 1177 GENMASK(7, 6)); 1178 } 1179 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0) 1180 static inline void SET_CMC_TBL_CB(void *table, u32 val) 1181 { 1182 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8)); 1183 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB, 1184 GENMASK(9, 8)); 1185 } 1186 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0) 1187 static inline void SET_CMC_TBL_CS(void *table, u32 val) 1188 { 1189 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10)); 1190 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS, 1191 GENMASK(11, 10)); 1192 } 1193 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0) 1194 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val) 1195 { 1196 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12)); 1197 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN, 1198 BIT(12)); 1199 } 1200 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0) 1201 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val) 1202 { 1203 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13)); 1204 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN, 1205 BIT(13)); 1206 } 1207 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0) 1208 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val) 1209 { 1210 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14)); 1211 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN, 1212 BIT(14)); 1213 } 1214 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0) 1215 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val) 1216 { 1217 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15)); 1218 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN, 1219 BIT(15)); 1220 } 1221 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0) 1222 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val) 1223 { 1224 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16)); 1225 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE, 1226 GENMASK(24, 16)); 1227 } 1228 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0) 1229 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val) 1230 { 1231 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25)); 1232 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF, 1233 GENMASK(27, 25)); 1234 } 1235 1236 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val) 1237 { 1238 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28)); 1239 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1240 GENMASK(29, 28)); 1241 } 1242 1243 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0) 1244 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val) 1245 { 1246 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30)); 1247 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW, 1248 GENMASK(31, 30)); 1249 } 1250 1251 static inline void SET_DCTL_MACID_V1(void *table, u32 val) 1252 { 1253 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)); 1254 } 1255 1256 static inline void SET_DCTL_OPERATION_V1(void *table, u32 val) 1257 { 1258 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); 1259 } 1260 1261 #define SET_DCTL_MASK_QOS_FIELD_V1 GENMASK(7, 0) 1262 static inline void SET_DCTL_QOS_FIELD_V1(void *table, u32 val) 1263 { 1264 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(7, 0)); 1265 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_FIELD_V1, 1266 GENMASK(7, 0)); 1267 } 1268 1269 #define SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID GENMASK(6, 0) 1270 static inline void SET_DCTL_HW_EXSEQ_MACID_V1(void *table, u32 val) 1271 { 1272 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 8)); 1273 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID, 1274 GENMASK(14, 8)); 1275 } 1276 1277 #define SET_DCTL_MASK_QOS_DATA BIT(0) 1278 static inline void SET_DCTL_QOS_DATA_V1(void *table, u32 val) 1279 { 1280 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); 1281 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_DATA, 1282 BIT(15)); 1283 } 1284 1285 #define SET_DCTL_MASK_AES_IV_L GENMASK(15, 0) 1286 static inline void SET_DCTL_AES_IV_L_V1(void *table, u32 val) 1287 { 1288 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 16)); 1289 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_AES_IV_L, 1290 GENMASK(31, 16)); 1291 } 1292 1293 #define SET_DCTL_MASK_AES_IV_H GENMASK(31, 0) 1294 static inline void SET_DCTL_AES_IV_H_V1(void *table, u32 val) 1295 { 1296 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 0)); 1297 le32p_replace_bits((__le32 *)(table) + 10, SET_DCTL_MASK_AES_IV_H, 1298 GENMASK(31, 0)); 1299 } 1300 1301 #define SET_DCTL_MASK_SEQ0 GENMASK(11, 0) 1302 static inline void SET_DCTL_SEQ0_V1(void *table, u32 val) 1303 { 1304 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 0)); 1305 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ0, 1306 GENMASK(11, 0)); 1307 } 1308 1309 #define SET_DCTL_MASK_SEQ1 GENMASK(11, 0) 1310 static inline void SET_DCTL_SEQ1_V1(void *table, u32 val) 1311 { 1312 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(23, 12)); 1313 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ1, 1314 GENMASK(23, 12)); 1315 } 1316 1317 #define SET_DCTL_MASK_AMSDU_MAX_LEN GENMASK(2, 0) 1318 static inline void SET_DCTL_AMSDU_MAX_LEN_V1(void *table, u32 val) 1319 { 1320 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 24)); 1321 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_AMSDU_MAX_LEN, 1322 GENMASK(26, 24)); 1323 } 1324 1325 #define SET_DCTL_MASK_STA_AMSDU_EN BIT(0) 1326 static inline void SET_DCTL_STA_AMSDU_EN_V1(void *table, u32 val) 1327 { 1328 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); 1329 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_STA_AMSDU_EN, 1330 BIT(27)); 1331 } 1332 1333 #define SET_DCTL_MASK_CHKSUM_OFLD_EN BIT(0) 1334 static inline void SET_DCTL_CHKSUM_OFLD_EN_V1(void *table, u32 val) 1335 { 1336 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(28)); 1337 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_CHKSUM_OFLD_EN, 1338 BIT(28)); 1339 } 1340 1341 #define SET_DCTL_MASK_WITH_LLC BIT(0) 1342 static inline void SET_DCTL_WITH_LLC_V1(void *table, u32 val) 1343 { 1344 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(29)); 1345 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_WITH_LLC, 1346 BIT(29)); 1347 } 1348 1349 #define SET_DCTL_MASK_SEQ2 GENMASK(11, 0) 1350 static inline void SET_DCTL_SEQ2_V1(void *table, u32 val) 1351 { 1352 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(11, 0)); 1353 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ2, 1354 GENMASK(11, 0)); 1355 } 1356 1357 #define SET_DCTL_MASK_SEQ3 GENMASK(11, 0) 1358 static inline void SET_DCTL_SEQ3_V1(void *table, u32 val) 1359 { 1360 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(23, 12)); 1361 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ3, 1362 GENMASK(23, 12)); 1363 } 1364 1365 #define SET_DCTL_MASK_TGT_IND GENMASK(3, 0) 1366 static inline void SET_DCTL_TGT_IND_V1(void *table, u32 val) 1367 { 1368 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 24)); 1369 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND, 1370 GENMASK(27, 24)); 1371 } 1372 1373 #define SET_DCTL_MASK_TGT_IND_EN BIT(0) 1374 static inline void SET_DCTL_TGT_IND_EN_V1(void *table, u32 val) 1375 { 1376 le32p_replace_bits((__le32 *)(table) + 4, val, BIT(28)); 1377 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND_EN, 1378 BIT(28)); 1379 } 1380 1381 #define SET_DCTL_MASK_HTC_LB GENMASK(2, 0) 1382 static inline void SET_DCTL_HTC_LB_V1(void *table, u32 val) 1383 { 1384 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 29)); 1385 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_HTC_LB, 1386 GENMASK(31, 29)); 1387 } 1388 1389 #define SET_DCTL_MASK_MHDR_LEN GENMASK(4, 0) 1390 static inline void SET_DCTL_MHDR_LEN_V1(void *table, u32 val) 1391 { 1392 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(4, 0)); 1393 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_MHDR_LEN, 1394 GENMASK(4, 0)); 1395 } 1396 1397 #define SET_DCTL_MASK_VLAN_TAG_VALID BIT(0) 1398 static inline void SET_DCTL_VLAN_TAG_VALID_V1(void *table, u32 val) 1399 { 1400 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(5)); 1401 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_VALID, 1402 BIT(5)); 1403 } 1404 1405 #define SET_DCTL_MASK_VLAN_TAG_SEL GENMASK(1, 0) 1406 static inline void SET_DCTL_VLAN_TAG_SEL_V1(void *table, u32 val) 1407 { 1408 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 6)); 1409 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_SEL, 1410 GENMASK(7, 6)); 1411 } 1412 1413 #define SET_DCTL_MASK_HTC_ORDER BIT(0) 1414 static inline void SET_DCTL_HTC_ORDER_V1(void *table, u32 val) 1415 { 1416 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); 1417 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_HTC_ORDER, 1418 BIT(8)); 1419 } 1420 1421 #define SET_DCTL_MASK_SEC_KEY_ID GENMASK(1, 0) 1422 static inline void SET_DCTL_SEC_KEY_ID_V1(void *table, u32 val) 1423 { 1424 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(10, 9)); 1425 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_KEY_ID, 1426 GENMASK(10, 9)); 1427 } 1428 1429 #define SET_DCTL_MASK_WAPI BIT(0) 1430 static inline void SET_DCTL_WAPI_V1(void *table, u32 val) 1431 { 1432 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); 1433 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_WAPI, 1434 BIT(15)); 1435 } 1436 1437 #define SET_DCTL_MASK_SEC_ENT_MODE GENMASK(1, 0) 1438 static inline void SET_DCTL_SEC_ENT_MODE_V1(void *table, u32 val) 1439 { 1440 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(17, 16)); 1441 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENT_MODE, 1442 GENMASK(17, 16)); 1443 } 1444 1445 #define SET_DCTL_MASK_SEC_ENTX_KEYID GENMASK(1, 0) 1446 static inline void SET_DCTL_SEC_ENT0_KEYID_V1(void *table, u32 val) 1447 { 1448 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(19, 18)); 1449 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1450 GENMASK(19, 18)); 1451 } 1452 1453 static inline void SET_DCTL_SEC_ENT1_KEYID_V1(void *table, u32 val) 1454 { 1455 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(21, 20)); 1456 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1457 GENMASK(21, 20)); 1458 } 1459 1460 static inline void SET_DCTL_SEC_ENT2_KEYID_V1(void *table, u32 val) 1461 { 1462 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(23, 22)); 1463 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1464 GENMASK(23, 22)); 1465 } 1466 1467 static inline void SET_DCTL_SEC_ENT3_KEYID_V1(void *table, u32 val) 1468 { 1469 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(25, 24)); 1470 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1471 GENMASK(25, 24)); 1472 } 1473 1474 static inline void SET_DCTL_SEC_ENT4_KEYID_V1(void *table, u32 val) 1475 { 1476 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(27, 26)); 1477 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1478 GENMASK(27, 26)); 1479 } 1480 1481 static inline void SET_DCTL_SEC_ENT5_KEYID_V1(void *table, u32 val) 1482 { 1483 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(29, 28)); 1484 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1485 GENMASK(29, 28)); 1486 } 1487 1488 static inline void SET_DCTL_SEC_ENT6_KEYID_V1(void *table, u32 val) 1489 { 1490 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 30)); 1491 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1492 GENMASK(31, 30)); 1493 } 1494 1495 #define SET_DCTL_MASK_SEC_ENT_VALID GENMASK(7, 0) 1496 static inline void SET_DCTL_SEC_ENT_VALID_V1(void *table, u32 val) 1497 { 1498 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(7, 0)); 1499 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENT_VALID, 1500 GENMASK(7, 0)); 1501 } 1502 1503 #define SET_DCTL_MASK_SEC_ENTX GENMASK(7, 0) 1504 static inline void SET_DCTL_SEC_ENT0_V1(void *table, u32 val) 1505 { 1506 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(15, 8)); 1507 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1508 GENMASK(15, 8)); 1509 } 1510 1511 static inline void SET_DCTL_SEC_ENT1_V1(void *table, u32 val) 1512 { 1513 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 16)); 1514 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1515 GENMASK(23, 16)); 1516 } 1517 1518 static inline void SET_DCTL_SEC_ENT2_V1(void *table, u32 val) 1519 { 1520 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(31, 24)); 1521 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1522 GENMASK(31, 24)); 1523 } 1524 1525 static inline void SET_DCTL_SEC_ENT3_V1(void *table, u32 val) 1526 { 1527 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); 1528 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1529 GENMASK(7, 0)); 1530 } 1531 1532 static inline void SET_DCTL_SEC_ENT4_V1(void *table, u32 val) 1533 { 1534 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(15, 8)); 1535 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1536 GENMASK(15, 8)); 1537 } 1538 1539 static inline void SET_DCTL_SEC_ENT5_V1(void *table, u32 val) 1540 { 1541 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 16)); 1542 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1543 GENMASK(23, 16)); 1544 } 1545 1546 static inline void SET_DCTL_SEC_ENT6_V1(void *table, u32 val) 1547 { 1548 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 24)); 1549 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1550 GENMASK(31, 24)); 1551 } 1552 1553 static inline void SET_BCN_UPD_PORT(void *h2c, u32 val) 1554 { 1555 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1556 } 1557 1558 static inline void SET_BCN_UPD_MBSSID(void *h2c, u32 val) 1559 { 1560 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1561 } 1562 1563 static inline void SET_BCN_UPD_BAND(void *h2c, u32 val) 1564 { 1565 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1566 } 1567 1568 static inline void SET_BCN_UPD_GRP_IE_OFST(void *h2c, u32 val) 1569 { 1570 le32p_replace_bits((__le32 *)h2c, (val - 24) | BIT(7), GENMASK(31, 24)); 1571 } 1572 1573 static inline void SET_BCN_UPD_MACID(void *h2c, u32 val) 1574 { 1575 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1576 } 1577 1578 static inline void SET_BCN_UPD_SSN_SEL(void *h2c, u32 val) 1579 { 1580 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(9, 8)); 1581 } 1582 1583 static inline void SET_BCN_UPD_SSN_MODE(void *h2c, u32 val) 1584 { 1585 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(11, 10)); 1586 } 1587 1588 static inline void SET_BCN_UPD_RATE(void *h2c, u32 val) 1589 { 1590 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(20, 12)); 1591 } 1592 1593 static inline void SET_BCN_UPD_TXPWR(void *h2c, u32 val) 1594 { 1595 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(23, 21)); 1596 } 1597 1598 static inline void SET_BCN_UPD_TXINFO_CTRL_EN(void *h2c, u32 val) 1599 { 1600 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(0)); 1601 } 1602 1603 static inline void SET_BCN_UPD_NTX_PATH_EN(void *h2c, u32 val) 1604 { 1605 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(4, 1)); 1606 } 1607 1608 static inline void SET_BCN_UPD_PATH_MAP_A(void *h2c, u32 val) 1609 { 1610 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(6, 5)); 1611 } 1612 1613 static inline void SET_BCN_UPD_PATH_MAP_B(void *h2c, u32 val) 1614 { 1615 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(8, 7)); 1616 } 1617 1618 static inline void SET_BCN_UPD_PATH_MAP_C(void *h2c, u32 val) 1619 { 1620 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(10, 9)); 1621 } 1622 1623 static inline void SET_BCN_UPD_PATH_MAP_D(void *h2c, u32 val) 1624 { 1625 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(12, 11)); 1626 } 1627 1628 static inline void SET_BCN_UPD_PATH_ANTSEL_A(void *h2c, u32 val) 1629 { 1630 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(13)); 1631 } 1632 1633 static inline void SET_BCN_UPD_PATH_ANTSEL_B(void *h2c, u32 val) 1634 { 1635 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(14)); 1636 } 1637 1638 static inline void SET_BCN_UPD_PATH_ANTSEL_C(void *h2c, u32 val) 1639 { 1640 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(15)); 1641 } 1642 1643 static inline void SET_BCN_UPD_PATH_ANTSEL_D(void *h2c, u32 val) 1644 { 1645 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(16)); 1646 } 1647 1648 static inline void SET_BCN_UPD_CSA_OFST(void *h2c, u32 val) 1649 { 1650 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 17)); 1651 } 1652 1653 static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val) 1654 { 1655 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1656 } 1657 1658 static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val) 1659 { 1660 le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8)); 1661 } 1662 1663 static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val) 1664 { 1665 le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10)); 1666 } 1667 1668 static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val) 1669 { 1670 le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13)); 1671 } 1672 1673 static inline void SET_JOININFO_MACID(void *h2c, u32 val) 1674 { 1675 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1676 } 1677 1678 static inline void SET_JOININFO_OP(void *h2c, u32 val) 1679 { 1680 le32p_replace_bits((__le32 *)h2c, val, BIT(8)); 1681 } 1682 1683 static inline void SET_JOININFO_BAND(void *h2c, u32 val) 1684 { 1685 le32p_replace_bits((__le32 *)h2c, val, BIT(9)); 1686 } 1687 1688 static inline void SET_JOININFO_WMM(void *h2c, u32 val) 1689 { 1690 le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10)); 1691 } 1692 1693 static inline void SET_JOININFO_TGR(void *h2c, u32 val) 1694 { 1695 le32p_replace_bits((__le32 *)h2c, val, BIT(12)); 1696 } 1697 1698 static inline void SET_JOININFO_ISHESTA(void *h2c, u32 val) 1699 { 1700 le32p_replace_bits((__le32 *)h2c, val, BIT(13)); 1701 } 1702 1703 static inline void SET_JOININFO_DLBW(void *h2c, u32 val) 1704 { 1705 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14)); 1706 } 1707 1708 static inline void SET_JOININFO_TF_MAC_PAD(void *h2c, u32 val) 1709 { 1710 le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16)); 1711 } 1712 1713 static inline void SET_JOININFO_DL_T_PE(void *h2c, u32 val) 1714 { 1715 le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18)); 1716 } 1717 1718 static inline void SET_JOININFO_PORT_ID(void *h2c, u32 val) 1719 { 1720 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21)); 1721 } 1722 1723 static inline void SET_JOININFO_NET_TYPE(void *h2c, u32 val) 1724 { 1725 le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24)); 1726 } 1727 1728 static inline void SET_JOININFO_WIFI_ROLE(void *h2c, u32 val) 1729 { 1730 le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26)); 1731 } 1732 1733 static inline void SET_JOININFO_SELF_ROLE(void *h2c, u32 val) 1734 { 1735 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30)); 1736 } 1737 1738 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val) 1739 { 1740 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1741 } 1742 1743 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val) 1744 { 1745 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1746 } 1747 1748 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val) 1749 { 1750 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1751 } 1752 1753 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val) 1754 { 1755 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1756 } 1757 1758 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val) 1759 { 1760 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1761 } 1762 1763 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val) 1764 { 1765 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); 1766 } 1767 1768 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val) 1769 { 1770 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1771 } 1772 1773 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val) 1774 { 1775 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1776 } 1777 1778 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val) 1779 { 1780 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)); 1781 } 1782 1783 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val) 1784 { 1785 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0)); 1786 } 1787 1788 static inline void SET_BA_CAM_VALID(void *h2c, u32 val) 1789 { 1790 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 1791 } 1792 1793 static inline void SET_BA_CAM_INIT_REQ(void *h2c, u32 val) 1794 { 1795 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 1796 } 1797 1798 static inline void SET_BA_CAM_ENTRY_IDX(void *h2c, u32 val) 1799 { 1800 le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2)); 1801 } 1802 1803 static inline void SET_BA_CAM_TID(void *h2c, u32 val) 1804 { 1805 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4)); 1806 } 1807 1808 static inline void SET_BA_CAM_MACID(void *h2c, u32 val) 1809 { 1810 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1811 } 1812 1813 static inline void SET_BA_CAM_BMAP_SIZE(void *h2c, u32 val) 1814 { 1815 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); 1816 } 1817 1818 static inline void SET_BA_CAM_SSN(void *h2c, u32 val) 1819 { 1820 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20)); 1821 } 1822 1823 static inline void SET_BA_CAM_UID(void *h2c, u32 val) 1824 { 1825 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(7, 0)); 1826 } 1827 1828 static inline void SET_BA_CAM_STD_EN(void *h2c, u32 val) 1829 { 1830 le32p_replace_bits((__le32 *)h2c + 1, val, BIT(8)); 1831 } 1832 1833 static inline void SET_BA_CAM_BAND(void *h2c, u32 val) 1834 { 1835 le32p_replace_bits((__le32 *)h2c + 1, val, BIT(9)); 1836 } 1837 1838 static inline void SET_BA_CAM_ENTRY_IDX_V1(void *h2c, u32 val) 1839 { 1840 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 28)); 1841 } 1842 1843 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val) 1844 { 1845 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1846 } 1847 1848 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val) 1849 { 1850 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1851 } 1852 1853 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val) 1854 { 1855 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); 1856 } 1857 1858 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val) 1859 { 1860 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20)); 1861 } 1862 1863 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val) 1864 { 1865 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1866 } 1867 1868 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val) 1869 { 1870 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0)); 1871 } 1872 1873 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val) 1874 { 1875 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1)); 1876 } 1877 1878 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val) 1879 { 1880 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2)); 1881 } 1882 1883 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val) 1884 { 1885 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3)); 1886 } 1887 1888 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val) 1889 { 1890 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); 1891 } 1892 1893 static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val) 1894 { 1895 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0)); 1896 } 1897 1898 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val) 1899 { 1900 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 1901 } 1902 1903 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val) 1904 { 1905 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 1906 } 1907 1908 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val) 1909 { 1910 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 1911 } 1912 1913 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val) 1914 { 1915 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 1916 } 1917 1918 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val) 1919 { 1920 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0)); 1921 } 1922 1923 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val) 1924 { 1925 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8)); 1926 } 1927 1928 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val) 1929 { 1930 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 1931 } 1932 1933 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val) 1934 { 1935 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0)); 1936 } 1937 1938 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val) 1939 { 1940 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0)); 1941 } 1942 1943 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val) 1944 { 1945 le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0)); 1946 } 1947 1948 static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val) 1949 { 1950 le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0)); 1951 } 1952 1953 static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val) 1954 { 1955 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1956 } 1957 1958 static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val) 1959 { 1960 le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16)); 1961 } 1962 1963 static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val) 1964 { 1965 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1966 } 1967 1968 static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val) 1969 { 1970 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 1971 } 1972 1973 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val) 1974 { 1975 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 1976 } 1977 1978 static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val) 1979 { 1980 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); 1981 } 1982 1983 static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val) 1984 { 1985 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1986 } 1987 1988 static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val) 1989 { 1990 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1991 } 1992 1993 static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val) 1994 { 1995 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1996 } 1997 1998 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val) 1999 { 2000 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 2001 } 2002 2003 static inline void RTW89_SET_WOW_GLOBAL_ENABLE(void *h2c, u32 val) 2004 { 2005 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 2006 } 2007 2008 static inline void RTW89_SET_WOW_GLOBAL_DROP_ALL_PKT(void *h2c, u32 val) 2009 { 2010 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 2011 } 2012 2013 static inline void RTW89_SET_WOW_GLOBAL_RX_PARSE_AFTER_WAKE(void *h2c, u32 val) 2014 { 2015 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); 2016 } 2017 2018 static inline void RTW89_SET_WOW_GLOBAL_WAKE_BAR_PULLED(void *h2c, u32 val) 2019 { 2020 le32p_replace_bits((__le32 *)h2c, val, BIT(3)); 2021 } 2022 2023 static inline void RTW89_SET_WOW_GLOBAL_MAC_ID(void *h2c, u32 val) 2024 { 2025 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 2026 } 2027 2028 static inline void RTW89_SET_WOW_GLOBAL_PAIRWISE_SEC_ALGO(void *h2c, u32 val) 2029 { 2030 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 2031 } 2032 2033 static inline void RTW89_SET_WOW_GLOBAL_GROUP_SEC_ALGO(void *h2c, u32 val) 2034 { 2035 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 2036 } 2037 2038 static inline void RTW89_SET_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT(void *h2c, u32 val) 2039 { 2040 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)); 2041 } 2042 2043 static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val) 2044 { 2045 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 2046 } 2047 2048 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val) 2049 { 2050 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 2051 } 2052 2053 static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val) 2054 { 2055 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); 2056 } 2057 2058 static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val) 2059 { 2060 le32p_replace_bits((__le32 *)h2c, val, BIT(3)); 2061 } 2062 2063 static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val) 2064 { 2065 le32p_replace_bits((__le32 *)h2c, val, BIT(4)); 2066 } 2067 2068 static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val) 2069 { 2070 le32p_replace_bits((__le32 *)h2c, val, BIT(5)); 2071 } 2072 2073 static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val) 2074 { 2075 le32p_replace_bits((__le32 *)h2c, val, BIT(6)); 2076 } 2077 2078 static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val) 2079 { 2080 le32p_replace_bits((__le32 *)h2c, val, BIT(7)); 2081 } 2082 2083 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val) 2084 { 2085 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 2086 } 2087 2088 static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val) 2089 { 2090 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 2091 } 2092 2093 static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val) 2094 { 2095 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1)); 2096 } 2097 2098 static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val) 2099 { 2100 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0)); 2101 } 2102 2103 static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val) 2104 { 2105 le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0)); 2106 } 2107 2108 static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val) 2109 { 2110 le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0)); 2111 } 2112 2113 static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val) 2114 { 2115 le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0)); 2116 } 2117 2118 static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val) 2119 { 2120 le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0)); 2121 } 2122 2123 static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val) 2124 { 2125 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22)); 2126 } 2127 2128 static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val) 2129 { 2130 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23)); 2131 } 2132 2133 static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val) 2134 { 2135 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24)); 2136 } 2137 2138 static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val) 2139 { 2140 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25)); 2141 } 2142 2143 static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val) 2144 { 2145 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26)); 2146 } 2147 2148 static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val) 2149 { 2150 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31)); 2151 } 2152 2153 enum rtw89_btc_btf_h2c_class { 2154 BTFC_SET = 0x10, 2155 BTFC_GET = 0x11, 2156 BTFC_FW_EVENT = 0x12, 2157 }; 2158 2159 enum rtw89_btc_btf_set { 2160 SET_REPORT_EN = 0x0, 2161 SET_SLOT_TABLE, 2162 SET_MREG_TABLE, 2163 SET_CX_POLICY, 2164 SET_GPIO_DBG, 2165 SET_DRV_INFO, 2166 SET_DRV_EVENT, 2167 SET_BT_WREG_ADDR, 2168 SET_BT_WREG_VAL, 2169 SET_BT_RREG_ADDR, 2170 SET_BT_WL_CH_INFO, 2171 SET_BT_INFO_REPORT, 2172 SET_BT_IGNORE_WLAN_ACT, 2173 SET_BT_TX_PWR, 2174 SET_BT_LNA_CONSTRAIN, 2175 SET_BT_GOLDEN_RX_RANGE, 2176 SET_BT_PSD_REPORT, 2177 SET_H2C_TEST, 2178 SET_MAX1, 2179 }; 2180 2181 enum rtw89_btc_cxdrvinfo { 2182 CXDRVINFO_INIT = 0, 2183 CXDRVINFO_ROLE, 2184 CXDRVINFO_DBCC, 2185 CXDRVINFO_SMAP, 2186 CXDRVINFO_RFK, 2187 CXDRVINFO_RUN, 2188 CXDRVINFO_CTRL, 2189 CXDRVINFO_SCAN, 2190 CXDRVINFO_TRX, /* WL traffic to WL fw */ 2191 CXDRVINFO_MAX, 2192 }; 2193 2194 enum rtw89_scan_mode { 2195 RTW89_SCAN_IMMEDIATE, 2196 }; 2197 2198 enum rtw89_scan_type { 2199 RTW89_SCAN_ONCE, 2200 }; 2201 2202 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val) 2203 { 2204 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0)); 2205 } 2206 2207 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val) 2208 { 2209 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0)); 2210 } 2211 2212 struct rtw89_h2c_cxhdr { 2213 u8 type; 2214 u8 len; 2215 } __packed; 2216 2217 #define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr) 2218 2219 struct rtw89_h2c_cxinit { 2220 struct rtw89_h2c_cxhdr hdr; 2221 u8 ant_type; 2222 u8 ant_num; 2223 u8 ant_iso; 2224 u8 ant_info; 2225 u8 mod_rfe; 2226 u8 mod_cv; 2227 u8 mod_info; 2228 u8 mod_adie_kt; 2229 u8 wl_gch; 2230 u8 info; 2231 u8 rsvd; 2232 u8 rsvd1; 2233 } __packed; 2234 2235 #define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0) 2236 #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1) 2237 #define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2) 2238 #define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4) 2239 2240 #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0) 2241 #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1) 2242 #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2) 2243 #define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3) 2244 2245 #define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0) 2246 #define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1) 2247 #define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2) 2248 #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3) 2249 #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4) 2250 2251 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val) 2252 { 2253 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)); 2254 } 2255 2256 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val) 2257 { 2258 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)); 2259 } 2260 2261 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val) 2262 { 2263 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0)); 2264 } 2265 2266 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val) 2267 { 2268 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1)); 2269 } 2270 2271 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val) 2272 { 2273 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2)); 2274 } 2275 2276 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val) 2277 { 2278 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3)); 2279 } 2280 2281 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val) 2282 { 2283 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4)); 2284 } 2285 2286 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val) 2287 { 2288 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5)); 2289 } 2290 2291 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val) 2292 { 2293 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6)); 2294 } 2295 2296 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val) 2297 { 2298 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7)); 2299 } 2300 2301 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val) 2302 { 2303 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8)); 2304 } 2305 2306 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val) 2307 { 2308 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9)); 2309 } 2310 2311 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val) 2312 { 2313 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10)); 2314 } 2315 2316 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val) 2317 { 2318 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11)); 2319 } 2320 2321 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset) 2322 { 2323 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0)); 2324 } 2325 2326 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset) 2327 { 2328 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1)); 2329 } 2330 2331 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset) 2332 { 2333 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4)); 2334 } 2335 2336 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset) 2337 { 2338 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5)); 2339 } 2340 2341 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset) 2342 { 2343 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6)); 2344 } 2345 2346 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset) 2347 { 2348 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0)); 2349 } 2350 2351 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset) 2352 { 2353 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1)); 2354 } 2355 2356 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset) 2357 { 2358 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0)); 2359 } 2360 2361 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset) 2362 { 2363 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0)); 2364 } 2365 2366 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset) 2367 { 2368 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0)); 2369 } 2370 2371 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset) 2372 { 2373 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0)); 2374 } 2375 2376 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset) 2377 { 2378 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0)); 2379 } 2380 2381 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset) 2382 { 2383 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0)); 2384 } 2385 2386 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset) 2387 { 2388 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0)); 2389 } 2390 2391 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset) 2392 { 2393 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0)); 2394 } 2395 2396 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset) 2397 { 2398 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1)); 2399 } 2400 2401 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset) 2402 { 2403 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4)); 2404 } 2405 2406 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset) 2407 { 2408 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5)); 2409 } 2410 2411 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset) 2412 { 2413 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6)); 2414 } 2415 2416 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset) 2417 { 2418 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0)); 2419 } 2420 2421 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset) 2422 { 2423 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1)); 2424 } 2425 2426 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset) 2427 { 2428 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0)); 2429 } 2430 2431 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset) 2432 { 2433 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0)); 2434 } 2435 2436 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset) 2437 { 2438 le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0)); 2439 } 2440 2441 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset) 2442 { 2443 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0)); 2444 } 2445 2446 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset) 2447 { 2448 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0)); 2449 } 2450 2451 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset) 2452 { 2453 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0)); 2454 } 2455 2456 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset) 2457 { 2458 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1)); 2459 } 2460 2461 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset) 2462 { 2463 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2)); 2464 } 2465 2466 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset) 2467 { 2468 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4)); 2469 } 2470 2471 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val) 2472 { 2473 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0)); 2474 } 2475 2476 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val) 2477 { 2478 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1)); 2479 } 2480 2481 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val) 2482 { 2483 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2)); 2484 } 2485 2486 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val) 2487 { 2488 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3)); 2489 } 2490 2491 static inline void RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val) 2492 { 2493 u8p_replace_bits((u8 *)cmd + 2, val, GENMASK(7, 0)); 2494 } 2495 2496 static inline void RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val) 2497 { 2498 u8p_replace_bits((u8 *)cmd + 3, val, GENMASK(7, 0)); 2499 } 2500 2501 static inline void RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val) 2502 { 2503 u8p_replace_bits((u8 *)cmd + 4, val, GENMASK(7, 0)); 2504 } 2505 2506 static inline void RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val) 2507 { 2508 u8p_replace_bits((u8 *)cmd + 5, val, GENMASK(7, 0)); 2509 } 2510 2511 static inline void RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val) 2512 { 2513 u8p_replace_bits((u8 *)cmd + 6, val, GENMASK(7, 0)); 2514 } 2515 2516 static inline void RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val) 2517 { 2518 u8p_replace_bits((u8 *)cmd + 7, val, GENMASK(7, 0)); 2519 } 2520 2521 static inline void RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val) 2522 { 2523 u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0)); 2524 } 2525 2526 static inline void RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val) 2527 { 2528 u8p_replace_bits((u8 *)cmd + 9, val, GENMASK(7, 0)); 2529 } 2530 2531 static inline void RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val) 2532 { 2533 u8p_replace_bits((u8 *)cmd + 10, val, GENMASK(7, 0)); 2534 } 2535 2536 static inline void RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val) 2537 { 2538 u8p_replace_bits((u8 *)cmd + 11, val, GENMASK(7, 0)); 2539 } 2540 2541 static inline void RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val) 2542 { 2543 u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0)); 2544 } 2545 2546 static inline void RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val) 2547 { 2548 u8p_replace_bits((u8 *)cmd + 13, val, GENMASK(7, 0)); 2549 } 2550 2551 static inline void RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val) 2552 { 2553 le16p_replace_bits((__le16 *)((u8 *)cmd + 14), val, GENMASK(15, 0)); 2554 } 2555 2556 static inline void RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val) 2557 { 2558 le16p_replace_bits((__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0)); 2559 } 2560 2561 static inline void RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val) 2562 { 2563 le32p_replace_bits((__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0)); 2564 } 2565 2566 static inline void RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val) 2567 { 2568 le32p_replace_bits((__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0)); 2569 } 2570 2571 static inline void RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val) 2572 { 2573 le32p_replace_bits((__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0)); 2574 } 2575 2576 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val) 2577 { 2578 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0)); 2579 } 2580 2581 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val) 2582 { 2583 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2)); 2584 } 2585 2586 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val) 2587 { 2588 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6)); 2589 } 2590 2591 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val) 2592 { 2593 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8)); 2594 } 2595 2596 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val) 2597 { 2598 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10)); 2599 } 2600 2601 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val) 2602 { 2603 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2604 } 2605 2606 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val) 2607 { 2608 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8)); 2609 } 2610 2611 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val) 2612 { 2613 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16)); 2614 } 2615 2616 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_NUM(void *cmd, u32 val) 2617 { 2618 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2619 } 2620 2621 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_SIZE(void *cmd, u32 val) 2622 { 2623 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8)); 2624 } 2625 2626 static inline void RTW89_SET_FWCMD_CHINFO_PERIOD(void *cmd, u32 val) 2627 { 2628 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2629 } 2630 2631 static inline void RTW89_SET_FWCMD_CHINFO_DWELL(void *cmd, u32 val) 2632 { 2633 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8)); 2634 } 2635 2636 static inline void RTW89_SET_FWCMD_CHINFO_CENTER_CH(void *cmd, u32 val) 2637 { 2638 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 16)); 2639 } 2640 2641 static inline void RTW89_SET_FWCMD_CHINFO_PRI_CH(void *cmd, u32 val) 2642 { 2643 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 24)); 2644 } 2645 2646 static inline void RTW89_SET_FWCMD_CHINFO_BW(void *cmd, u32 val) 2647 { 2648 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(2, 0)); 2649 } 2650 2651 static inline void RTW89_SET_FWCMD_CHINFO_ACTION(void *cmd, u32 val) 2652 { 2653 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 3)); 2654 } 2655 2656 static inline void RTW89_SET_FWCMD_CHINFO_NUM_PKT(void *cmd, u32 val) 2657 { 2658 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(11, 8)); 2659 } 2660 2661 static inline void RTW89_SET_FWCMD_CHINFO_TX(void *cmd, u32 val) 2662 { 2663 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(12)); 2664 } 2665 2666 static inline void RTW89_SET_FWCMD_CHINFO_PAUSE_DATA(void *cmd, u32 val) 2667 { 2668 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(13)); 2669 } 2670 2671 static inline void RTW89_SET_FWCMD_CHINFO_BAND(void *cmd, u32 val) 2672 { 2673 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 14)); 2674 } 2675 2676 static inline void RTW89_SET_FWCMD_CHINFO_PKT_ID(void *cmd, u32 val) 2677 { 2678 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16)); 2679 } 2680 2681 static inline void RTW89_SET_FWCMD_CHINFO_DFS(void *cmd, u32 val) 2682 { 2683 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(24)); 2684 } 2685 2686 static inline void RTW89_SET_FWCMD_CHINFO_TX_NULL(void *cmd, u32 val) 2687 { 2688 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(25)); 2689 } 2690 2691 static inline void RTW89_SET_FWCMD_CHINFO_RANDOM(void *cmd, u32 val) 2692 { 2693 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(26)); 2694 } 2695 2696 static inline void RTW89_SET_FWCMD_CHINFO_CFG_TX(void *cmd, u32 val) 2697 { 2698 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(27)); 2699 } 2700 2701 static inline void RTW89_SET_FWCMD_CHINFO_PKT0(void *cmd, u32 val) 2702 { 2703 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(7, 0)); 2704 } 2705 2706 static inline void RTW89_SET_FWCMD_CHINFO_PKT1(void *cmd, u32 val) 2707 { 2708 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 8)); 2709 } 2710 2711 static inline void RTW89_SET_FWCMD_CHINFO_PKT2(void *cmd, u32 val) 2712 { 2713 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16)); 2714 } 2715 2716 static inline void RTW89_SET_FWCMD_CHINFO_PKT3(void *cmd, u32 val) 2717 { 2718 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(31, 24)); 2719 } 2720 2721 static inline void RTW89_SET_FWCMD_CHINFO_PKT4(void *cmd, u32 val) 2722 { 2723 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(7, 0)); 2724 } 2725 2726 static inline void RTW89_SET_FWCMD_CHINFO_PKT5(void *cmd, u32 val) 2727 { 2728 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(15, 8)); 2729 } 2730 2731 static inline void RTW89_SET_FWCMD_CHINFO_PKT6(void *cmd, u32 val) 2732 { 2733 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(23, 16)); 2734 } 2735 2736 static inline void RTW89_SET_FWCMD_CHINFO_PKT7(void *cmd, u32 val) 2737 { 2738 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 24)); 2739 } 2740 2741 static inline void RTW89_SET_FWCMD_CHINFO_POWER_IDX(void *cmd, u32 val) 2742 { 2743 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(15, 0)); 2744 } 2745 2746 struct rtw89_h2c_scanofld { 2747 __le32 w0; 2748 __le32 w1; 2749 __le32 w2; 2750 __le32 tsf_high; 2751 __le32 tsf_low; 2752 __le32 w5; 2753 __le32 w6; 2754 } __packed; 2755 2756 #define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0) 2757 #define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8) 2758 #define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16) 2759 #define RTW89_H2C_SCANOFLD_W0_BAND BIT(19) 2760 #define RTW89_H2C_SCANOFLD_W0_OPERATION GENMASK(21, 20) 2761 #define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND GENMASK(23, 22) 2762 #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0) 2763 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1) 2764 #define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2) 2765 #define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE GENMASK(4, 3) 2766 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5) 2767 #define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8) 2768 #define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16) 2769 #define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24) 2770 #define RTW89_H2C_SCANOFLD_W2_NORM_PD GENMASK(15, 0) 2771 #define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16) 2772 2773 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val) 2774 { 2775 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 2776 } 2777 2778 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val) 2779 { 2780 le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8)); 2781 } 2782 2783 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val) 2784 { 2785 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12)); 2786 } 2787 2788 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val) 2789 { 2790 le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16)); 2791 } 2792 2793 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val) 2794 { 2795 le32p_replace_bits((__le32 *)cmd, val, BIT(20)); 2796 } 2797 2798 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val) 2799 { 2800 le32p_replace_bits((__le32 *)cmd, val, BIT(21)); 2801 } 2802 2803 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val) 2804 { 2805 *((__le32 *)cmd + 1) = val; 2806 } 2807 2808 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val) 2809 { 2810 *((__le32 *)cmd + 2) = val; 2811 } 2812 2813 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val) 2814 { 2815 *((__le32 *)cmd + 3) = val; 2816 } 2817 2818 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val) 2819 { 2820 le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0)); 2821 } 2822 2823 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val) 2824 { 2825 u8 ctwnd; 2826 2827 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT)) 2828 return; 2829 ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val); 2830 le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8)); 2831 } 2832 2833 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val) 2834 { 2835 le32p_replace_bits((__le32 *)cmd, val, BIT(0)); 2836 } 2837 2838 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val) 2839 { 2840 le32p_replace_bits((__le32 *)cmd, val, BIT(1)); 2841 } 2842 2843 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val) 2844 { 2845 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2)); 2846 } 2847 2848 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val) 2849 { 2850 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16)); 2851 } 2852 2853 enum rtw89_fw_mcc_c2h_rpt_cfg { 2854 RTW89_FW_MCC_C2H_RPT_OFF = 0, 2855 RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1, 2856 RTW89_FW_MCC_C2H_RPT_ALL = 2, 2857 }; 2858 2859 struct rtw89_fw_mcc_add_req { 2860 u8 macid; 2861 u8 central_ch_seg0; 2862 u8 central_ch_seg1; 2863 u8 primary_ch; 2864 enum rtw89_bandwidth bandwidth: 4; 2865 u32 group: 2; 2866 u32 c2h_rpt: 2; 2867 u32 dis_tx_null: 1; 2868 u32 dis_sw_retry: 1; 2869 u32 in_curr_ch: 1; 2870 u32 sw_retry_count: 3; 2871 u32 tx_null_early: 4; 2872 u32 btc_in_2g: 1; 2873 u32 pta_en: 1; 2874 u32 rfk_by_pass: 1; 2875 u32 ch_band_type: 2; 2876 u32 rsvd0: 9; 2877 u32 duration; 2878 u8 courtesy_en; 2879 u8 courtesy_num; 2880 u8 courtesy_target; 2881 u8 rsvd1; 2882 }; 2883 2884 static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val) 2885 { 2886 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 2887 } 2888 2889 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val) 2890 { 2891 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 2892 } 2893 2894 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val) 2895 { 2896 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 2897 } 2898 2899 static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val) 2900 { 2901 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 2902 } 2903 2904 static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val) 2905 { 2906 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0)); 2907 } 2908 2909 static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val) 2910 { 2911 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4)); 2912 } 2913 2914 static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val) 2915 { 2916 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6)); 2917 } 2918 2919 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val) 2920 { 2921 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8)); 2922 } 2923 2924 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val) 2925 { 2926 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9)); 2927 } 2928 2929 static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val) 2930 { 2931 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10)); 2932 } 2933 2934 static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val) 2935 { 2936 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11)); 2937 } 2938 2939 static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val) 2940 { 2941 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14)); 2942 } 2943 2944 static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val) 2945 { 2946 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18)); 2947 } 2948 2949 static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val) 2950 { 2951 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19)); 2952 } 2953 2954 static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val) 2955 { 2956 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20)); 2957 } 2958 2959 static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val) 2960 { 2961 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21)); 2962 } 2963 2964 static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val) 2965 { 2966 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 2967 } 2968 2969 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val) 2970 { 2971 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0)); 2972 } 2973 2974 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val) 2975 { 2976 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8)); 2977 } 2978 2979 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val) 2980 { 2981 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16)); 2982 } 2983 2984 struct rtw89_fw_mcc_start_req { 2985 u32 group: 2; 2986 u32 btc_in_group: 1; 2987 u32 old_group_action: 2; 2988 u32 old_group: 2; 2989 u32 rsvd0: 9; 2990 u32 notify_cnt: 3; 2991 u32 rsvd1: 2; 2992 u32 notify_rxdbg_en: 1; 2993 u32 rsvd2: 2; 2994 u32 macid: 8; 2995 u32 tsf_low; 2996 u32 tsf_high; 2997 }; 2998 2999 static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val) 3000 { 3001 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3002 } 3003 3004 static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val) 3005 { 3006 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 3007 } 3008 3009 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val) 3010 { 3011 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3)); 3012 } 3013 3014 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val) 3015 { 3016 le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5)); 3017 } 3018 3019 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val) 3020 { 3021 le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16)); 3022 } 3023 3024 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val) 3025 { 3026 le32p_replace_bits((__le32 *)cmd, val, BIT(21)); 3027 } 3028 3029 static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val) 3030 { 3031 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 3032 } 3033 3034 static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val) 3035 { 3036 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0)); 3037 } 3038 3039 static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val) 3040 { 3041 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 3042 } 3043 3044 static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val) 3045 { 3046 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 3047 } 3048 3049 static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val) 3050 { 3051 le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8)); 3052 } 3053 3054 static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val) 3055 { 3056 le32p_replace_bits((__le32 *)cmd, val, BIT(10)); 3057 } 3058 3059 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val) 3060 { 3061 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3062 } 3063 3064 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val) 3065 { 3066 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 3067 } 3068 3069 static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val) 3070 { 3071 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3072 } 3073 3074 struct rtw89_fw_mcc_tsf_req { 3075 u8 group: 2; 3076 u8 rsvd0: 6; 3077 u8 macid_x; 3078 u8 macid_y; 3079 u8 rsvd1; 3080 }; 3081 3082 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val) 3083 { 3084 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3085 } 3086 3087 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val) 3088 { 3089 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3090 } 3091 3092 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val) 3093 { 3094 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3095 } 3096 3097 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val) 3098 { 3099 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3100 } 3101 3102 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val) 3103 { 3104 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3105 } 3106 3107 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val) 3108 { 3109 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3110 } 3111 3112 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd, 3113 u8 *bitmap, u8 len) 3114 { 3115 memcpy((__le32 *)cmd + 1, bitmap, len); 3116 } 3117 3118 static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val) 3119 { 3120 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3121 } 3122 3123 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val) 3124 { 3125 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3126 } 3127 3128 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val) 3129 { 3130 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3131 } 3132 3133 static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val) 3134 { 3135 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 3136 } 3137 3138 struct rtw89_fw_mcc_duration { 3139 u32 group: 2; 3140 u32 btc_in_group: 1; 3141 u32 rsvd0: 5; 3142 u32 start_macid: 8; 3143 u32 macid_x: 8; 3144 u32 macid_y: 8; 3145 u32 start_tsf_low; 3146 u32 start_tsf_high; 3147 u32 duration_x; 3148 u32 duration_y; 3149 }; 3150 3151 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val) 3152 { 3153 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3154 } 3155 3156 static 3157 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val) 3158 { 3159 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 3160 } 3161 3162 static 3163 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val) 3164 { 3165 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3166 } 3167 3168 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val) 3169 { 3170 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3171 } 3172 3173 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val) 3174 { 3175 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 3176 } 3177 3178 static 3179 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val) 3180 { 3181 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0)); 3182 } 3183 3184 static 3185 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val) 3186 { 3187 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 3188 } 3189 3190 static 3191 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val) 3192 { 3193 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0)); 3194 } 3195 3196 static 3197 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val) 3198 { 3199 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0)); 3200 } 3201 3202 #define RTW89_C2H_HEADER_LEN 8 3203 3204 #define RTW89_GET_C2H_CATEGORY(c2h) \ 3205 le32_get_bits(*((const __le32 *)c2h), GENMASK(1, 0)) 3206 #define RTW89_GET_C2H_CLASS(c2h) \ 3207 le32_get_bits(*((const __le32 *)c2h), GENMASK(7, 2)) 3208 #define RTW89_GET_C2H_FUNC(c2h) \ 3209 le32_get_bits(*((const __le32 *)c2h), GENMASK(15, 8)) 3210 #define RTW89_GET_C2H_LEN(c2h) \ 3211 le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(13, 0)) 3212 3213 struct rtw89_fw_c2h_attr { 3214 u8 category; 3215 u8 class; 3216 u8 func; 3217 u16 len; 3218 }; 3219 3220 static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb) 3221 { 3222 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr)); 3223 3224 return (struct rtw89_fw_c2h_attr *)skb->cb; 3225 } 3226 3227 #define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2) 3228 #define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN) 3229 3230 struct rtw89_c2h_done_ack { 3231 __le32 w0; 3232 __le32 w1; 3233 __le32 w2; 3234 } __packed; 3235 3236 #define RTW89_C2H_DONE_ACK_W2_CAT GENMASK(1, 0) 3237 #define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2) 3238 #define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8) 3239 #define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16) 3240 #define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24) 3241 3242 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \ 3243 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3244 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \ 3245 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 3246 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \ 3247 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3248 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \ 3249 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 3250 3251 struct rtw89_c2h_mac_bcnfltr_rpt { 3252 __le32 w0; 3253 __le32 w1; 3254 __le32 w2; 3255 } __packed; 3256 3257 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0) 3258 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8) 3259 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10) 3260 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16) 3261 3262 #define RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h) \ 3263 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 0)) 3264 #define RTW89_GET_PHY_C2H_RA_RPT_RETRY_RATIO(c2h) \ 3265 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 3266 #define RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h) \ 3267 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(6, 0)) 3268 #define RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h) \ 3269 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(9, 8)) 3270 #define RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h) \ 3271 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(12, 10)) 3272 #define RTW89_GET_PHY_C2H_RA_RPT_BW(c2h) \ 3273 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(14, 13)) 3274 3275 /* VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS 3276 * HT-new: [6:5]: NA, [4:0]: MCS 3277 */ 3278 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4) 3279 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0) 3280 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0) 3281 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \ 3282 FIELD_PREP(GENMASK(2, 0), mcs)) 3283 3284 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \ 3285 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 3286 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \ 3287 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8)) 3288 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \ 3289 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16)) 3290 3291 #define RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h) \ 3292 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 3293 #define RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h) \ 3294 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(19, 16)) 3295 #define RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h) \ 3296 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 20)) 3297 #define RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h) \ 3298 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24)) 3299 #define RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h) \ 3300 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(3, 0)) 3301 #define RTW89_GET_MAC_C2H_SCANOFLD_AIR_DENSITY(c2h) \ 3302 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(7, 4)) 3303 #define RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h) \ 3304 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(25, 24)) 3305 3306 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \ 3307 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3308 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \ 3309 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3310 3311 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \ 3312 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3313 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \ 3314 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 3315 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \ 3316 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3317 3318 struct rtw89_mac_mcc_tsf_rpt { 3319 u32 macid_x; 3320 u32 macid_y; 3321 u32 tsf_x_low; 3322 u32 tsf_x_high; 3323 u32 tsf_y_low; 3324 u32 tsf_y_high; 3325 }; 3326 3327 static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE); 3328 3329 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \ 3330 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 3331 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \ 3332 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3333 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \ 3334 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16)) 3335 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \ 3336 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0)) 3337 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \ 3338 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0)) 3339 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \ 3340 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0)) 3341 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \ 3342 le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0)) 3343 3344 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \ 3345 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0)) 3346 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \ 3347 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6)) 3348 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \ 3349 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3350 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \ 3351 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0)) 3352 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \ 3353 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0)) 3354 3355 struct rtw89_c2h_pkt_ofld_rsp { 3356 __le32 w0; 3357 __le32 w1; 3358 __le32 w2; 3359 } __packed; 3360 3361 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0) 3362 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8) 3363 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16) 3364 3365 struct rtw89_h2c_bcnfltr { 3366 __le32 w0; 3367 } __packed; 3368 3369 #define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0) 3370 #define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1) 3371 #define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2) 3372 #define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3) 3373 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT GENMASK(11, 8) 3374 #define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12) 3375 #define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16) 3376 #define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24) 3377 3378 struct rtw89_h2c_ofld_rssi { 3379 __le32 w0; 3380 __le32 w1; 3381 } __packed; 3382 3383 #define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0) 3384 #define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8) 3385 #define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0) 3386 3387 struct rtw89_h2c_ofld { 3388 __le32 w0; 3389 } __packed; 3390 3391 #define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0) 3392 #define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8) 3393 #define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18) 3394 3395 #define RTW89_FW_HDR_SIZE 32 3396 #define RTW89_FW_SECTION_HDR_SIZE 16 3397 3398 #define RTW89_MFW_SIG 0xFF 3399 3400 struct rtw89_mfw_info { 3401 u8 cv; 3402 u8 type; /* enum rtw89_fw_type */ 3403 u8 mp; 3404 u8 rsvd; 3405 __le32 shift; 3406 __le32 size; 3407 u8 rsvd2[4]; 3408 } __packed; 3409 3410 struct rtw89_mfw_hdr { 3411 u8 sig; /* RTW89_MFW_SIG */ 3412 u8 fw_nr; 3413 u8 rsvd0[2]; 3414 struct { 3415 u8 major; 3416 u8 minor; 3417 u8 sub; 3418 u8 idx; 3419 } ver; 3420 u8 rsvd1[8]; 3421 struct rtw89_mfw_info info[]; 3422 } __packed; 3423 3424 struct fwcmd_hdr { 3425 __le32 hdr0; 3426 __le32 hdr1; 3427 }; 3428 3429 union rtw89_compat_fw_hdr { 3430 struct rtw89_mfw_hdr mfw_hdr; 3431 u8 fw_hdr[RTW89_FW_HDR_SIZE]; 3432 }; 3433 3434 static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf) 3435 { 3436 const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf; 3437 3438 if (compat->mfw_hdr.sig == RTW89_MFW_SIG) 3439 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr); 3440 else 3441 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr); 3442 } 3443 3444 static inline void rtw89_fw_get_filename(char *buf, size_t size, 3445 const char *fw_basename, int fw_format) 3446 { 3447 if (fw_format <= 0) 3448 snprintf(buf, size, "%s.bin", fw_basename); 3449 else 3450 snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format); 3451 } 3452 3453 #define RTW89_H2C_RF_PAGE_SIZE 500 3454 #define RTW89_H2C_RF_PAGE_NUM 3 3455 struct rtw89_fw_h2c_rf_reg_info { 3456 enum rtw89_rf_path rf_path; 3457 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE]; 3458 u16 curr_idx; 3459 }; 3460 3461 #define H2C_SEC_CAM_LEN 24 3462 3463 #define H2C_HEADER_LEN 8 3464 #define H2C_HDR_CAT GENMASK(1, 0) 3465 #define H2C_HDR_CLASS GENMASK(7, 2) 3466 #define H2C_HDR_FUNC GENMASK(15, 8) 3467 #define H2C_HDR_DEL_TYPE GENMASK(19, 16) 3468 #define H2C_HDR_H2C_SEQ GENMASK(31, 24) 3469 #define H2C_HDR_TOTAL_LEN GENMASK(13, 0) 3470 #define H2C_HDR_REC_ACK BIT(14) 3471 #define H2C_HDR_DONE_ACK BIT(15) 3472 3473 #define FWCMD_TYPE_H2C 0 3474 3475 #define H2C_CAT_TEST 0x0 3476 3477 /* CLASS 5 - FW STATUS TEST */ 3478 #define H2C_CL_FW_STATUS_TEST 0x5 3479 #define H2C_FUNC_CPU_EXCEPTION 0x1 3480 3481 #define H2C_CAT_MAC 0x1 3482 3483 /* CLASS 0 - FW INFO */ 3484 #define H2C_CL_FW_INFO 0x0 3485 #define H2C_FUNC_LOG_CFG 0x0 3486 #define H2C_FUNC_MAC_GENERAL_PKT 0x1 3487 3488 /* CLASS 1 - WOW */ 3489 #define H2C_CL_MAC_WOW 0x1 3490 #define H2C_FUNC_KEEP_ALIVE 0x0 3491 #define H2C_FUNC_DISCONNECT_DETECT 0x1 3492 #define H2C_FUNC_WOW_GLOBAL 0x2 3493 #define H2C_FUNC_WAKEUP_CTRL 0x8 3494 #define H2C_FUNC_WOW_CAM_UPD 0xC 3495 3496 /* CLASS 2 - PS */ 3497 #define H2C_CL_MAC_PS 0x2 3498 #define H2C_FUNC_MAC_LPS_PARM 0x0 3499 #define H2C_FUNC_P2P_ACT 0x1 3500 3501 /* CLASS 3 - FW download */ 3502 #define H2C_CL_MAC_FWDL 0x3 3503 #define H2C_FUNC_MAC_FWHDR_DL 0x0 3504 3505 /* CLASS 5 - Frame Exchange */ 3506 #define H2C_CL_MAC_FR_EXCHG 0x5 3507 #define H2C_FUNC_MAC_CCTLINFO_UD 0x2 3508 #define H2C_FUNC_MAC_BCN_UPD 0x5 3509 #define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9 3510 #define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa 3511 3512 /* CLASS 6 - Address CAM */ 3513 #define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6 3514 #define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0 3515 3516 /* CLASS 8 - Media Status Report */ 3517 #define H2C_CL_MAC_MEDIA_RPT 0x8 3518 #define H2C_FUNC_MAC_JOININFO 0x0 3519 #define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4 3520 3521 /* CLASS 9 - FW offload */ 3522 #define H2C_CL_MAC_FW_OFLD 0x9 3523 enum rtw89_fw_ofld_h2c_func { 3524 H2C_FUNC_PACKET_OFLD = 0x1, 3525 H2C_FUNC_MAC_MACID_PAUSE = 0x8, 3526 H2C_FUNC_USR_EDCA = 0xF, 3527 H2C_FUNC_TSF32_TOGL = 0x10, 3528 H2C_FUNC_OFLD_CFG = 0x14, 3529 H2C_FUNC_ADD_SCANOFLD_CH = 0x16, 3530 H2C_FUNC_SCANOFLD = 0x17, 3531 H2C_FUNC_PKT_DROP = 0x1b, 3532 H2C_FUNC_CFG_BCNFLTR = 0x1e, 3533 H2C_FUNC_OFLD_RSSI = 0x1f, 3534 H2C_FUNC_OFLD_TP = 0x20, 3535 3536 NUM_OF_RTW89_FW_OFLD_H2C_FUNC, 3537 }; 3538 3539 #define RTW89_FW_OFLD_WAIT_COND(tag, func) \ 3540 ((tag) * NUM_OF_RTW89_FW_OFLD_H2C_FUNC + (func)) 3541 3542 #define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \ 3543 RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \ 3544 H2C_FUNC_PACKET_OFLD) 3545 3546 /* CLASS 10 - Security CAM */ 3547 #define H2C_CL_MAC_SEC_CAM 0xa 3548 #define H2C_FUNC_MAC_SEC_UPD 0x1 3549 3550 /* CLASS 12 - BA CAM */ 3551 #define H2C_CL_BA_CAM 0xc 3552 #define H2C_FUNC_MAC_BA_CAM 0x0 3553 3554 /* CLASS 14 - MCC */ 3555 #define H2C_CL_MCC 0xe 3556 enum rtw89_mcc_h2c_func { 3557 H2C_FUNC_ADD_MCC = 0x0, 3558 H2C_FUNC_START_MCC = 0x1, 3559 H2C_FUNC_STOP_MCC = 0x2, 3560 H2C_FUNC_DEL_MCC_GROUP = 0x3, 3561 H2C_FUNC_RESET_MCC_GROUP = 0x4, 3562 H2C_FUNC_MCC_REQ_TSF = 0x5, 3563 H2C_FUNC_MCC_MACID_BITMAP = 0x6, 3564 H2C_FUNC_MCC_SYNC = 0x7, 3565 H2C_FUNC_MCC_SET_DURATION = 0x8, 3566 3567 NUM_OF_RTW89_MCC_H2C_FUNC, 3568 }; 3569 3570 #define RTW89_MCC_WAIT_COND(group, func) \ 3571 ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func)) 3572 3573 #define H2C_CAT_OUTSRC 0x2 3574 3575 #define H2C_CL_OUTSRC_RA 0x1 3576 #define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0 3577 3578 #define H2C_CL_OUTSRC_RF_REG_A 0x8 3579 #define H2C_CL_OUTSRC_RF_REG_B 0x9 3580 #define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa 3581 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2 3582 3583 struct rtw89_fw_h2c_rf_get_mccch { 3584 __le32 ch_0; 3585 __le32 ch_1; 3586 __le32 band_0; 3587 __le32 band_1; 3588 __le32 current_channel; 3589 __le32 current_band_type; 3590 } __packed; 3591 3592 #define RTW89_FW_RSVD_PLE_SIZE 0x800 3593 3594 #define RTW89_WCPU_BASE_MASK GENMASK(27, 0) 3595 3596 #define RTW89_FW_BACKTRACE_INFO_SIZE 8 3597 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \ 3598 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0) 3599 3600 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */ 3601 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE 3602 3603 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev); 3604 int rtw89_fw_recognize(struct rtw89_dev *rtwdev); 3605 const struct firmware * 3606 rtw89_early_fw_feature_recognize(struct device *device, 3607 const struct rtw89_chip_info *chip, 3608 struct rtw89_fw_info *early_fw, 3609 int *used_fw_format); 3610 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type); 3611 void rtw89_load_firmware_work(struct work_struct *work); 3612 void rtw89_unload_firmware(struct rtw89_dev *rtwdev); 3613 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev); 3614 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb, 3615 u8 type, u8 cat, u8 class, u8 func, 3616 bool rack, bool dack, u32 len); 3617 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, 3618 struct rtw89_vif *rtwvif); 3619 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, 3620 struct ieee80211_vif *vif, 3621 struct ieee80211_sta *sta); 3622 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev, 3623 struct rtw89_sta *rtwsta); 3624 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev, 3625 struct rtw89_sta *rtwsta); 3626 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev, 3627 struct rtw89_vif *rtwvif); 3628 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif, 3629 struct rtw89_sta *rtwsta, const u8 *scan_mac_addr); 3630 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev, 3631 struct rtw89_vif *rtwvif, 3632 struct rtw89_sta *rtwsta); 3633 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h); 3634 void rtw89_fw_c2h_work(struct work_struct *work); 3635 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev, 3636 struct rtw89_vif *rtwvif, 3637 struct rtw89_sta *rtwsta, 3638 enum rtw89_upd_mode upd_mode); 3639 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3640 struct rtw89_sta *rtwsta, bool dis_conn); 3641 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp, 3642 bool pause); 3643 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3644 u8 ac, u32 val); 3645 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev); 3646 int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev, 3647 struct ieee80211_vif *vif, 3648 bool connect); 3649 int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev, 3650 struct rtw89_rx_phy_ppdu *phy_ppdu); 3651 int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 3652 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi); 3653 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev); 3654 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev); 3655 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev); 3656 int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev); 3657 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev); 3658 int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev); 3659 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev); 3660 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id); 3661 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id, 3662 struct sk_buff *skb_ofld); 3663 int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int len, 3664 struct list_head *chan_list); 3665 int rtw89_fw_h2c_scan_offload(struct rtw89_dev *rtwdev, 3666 struct rtw89_scan_option *opt, 3667 struct rtw89_vif *vif); 3668 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev, 3669 struct rtw89_fw_h2c_rf_reg_info *info, 3670 u16 len, u8 page); 3671 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev); 3672 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, 3673 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, 3674 bool rack, bool dack); 3675 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len); 3676 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev); 3677 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev); 3678 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3679 u8 macid); 3680 void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev, 3681 struct rtw89_vif *rtwvif, bool notify_fw); 3682 void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw); 3683 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 3684 bool valid, struct ieee80211_ampdu_params *params); 3685 void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev); 3686 3687 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev, 3688 struct rtw89_lps_parm *lps_param); 3689 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len); 3690 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len); 3691 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev, 3692 struct rtw89_mac_h2c_info *h2c_info, 3693 struct rtw89_mac_c2h_info *c2h_info); 3694 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable); 3695 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev); 3696 void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3697 struct ieee80211_scan_request *req); 3698 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3699 bool aborted); 3700 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3701 bool enable); 3702 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 3703 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev); 3704 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev, 3705 const struct rtw89_pkt_drop_params *params); 3706 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3707 struct ieee80211_p2p_noa_desc *desc, 3708 u8 act, u8 noa_id); 3709 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3710 bool en); 3711 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3712 bool enable); 3713 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev, 3714 struct rtw89_vif *rtwvif, bool enable); 3715 int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3716 bool enable); 3717 int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev, 3718 struct rtw89_vif *rtwvif, bool enable); 3719 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3720 bool enable); 3721 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev, 3722 struct rtw89_vif *rtwvif, bool enable); 3723 int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev, 3724 struct rtw89_wow_cam_info *cam_info); 3725 int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev, 3726 const struct rtw89_fw_mcc_add_req *p); 3727 int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev, 3728 const struct rtw89_fw_mcc_start_req *p); 3729 int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid, 3730 bool prev_groups); 3731 int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group, 3732 bool prev_groups); 3733 int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group); 3734 int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev, 3735 const struct rtw89_fw_mcc_tsf_req *req, 3736 struct rtw89_mac_mcc_tsf_rpt *rpt); 3737 int rtw89_fw_h2c_mcc_macid_bitamp(struct rtw89_dev *rtwdev, u8 group, u8 macid, 3738 u8 *bitmap); 3739 int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source, 3740 u8 target, u8 offset); 3741 int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev, 3742 const struct rtw89_fw_mcc_duration *p); 3743 3744 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev) 3745 { 3746 const struct rtw89_chip_info *chip = rtwdev->chip; 3747 3748 if (chip->bacam_ver == RTW89_BACAM_V0_EXT) 3749 rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev); 3750 } 3751 3752 #endif 3753