1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_FW_H__ 6 #define __RTW89_FW_H__ 7 8 #include "core.h" 9 10 enum rtw89_fw_dl_status { 11 RTW89_FWDL_INITIAL_STATE = 0, 12 RTW89_FWDL_FWDL_ONGOING = 1, 13 RTW89_FWDL_CHECKSUM_FAIL = 2, 14 RTW89_FWDL_SECURITY_FAIL = 3, 15 RTW89_FWDL_CV_NOT_MATCH = 4, 16 RTW89_FWDL_RSVD0 = 5, 17 RTW89_FWDL_WCPU_FWDL_RDY = 6, 18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7 19 }; 20 21 struct rtw89_c2hreg_hdr { 22 u32 w0; 23 }; 24 25 #define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0) 26 #define RTW89_C2HREG_HDR_ACK BIT(7) 27 #define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8) 28 #define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12) 29 30 struct rtw89_c2hreg_phycap { 31 u32 w0; 32 u32 w1; 33 u32 w2; 34 u32 w3; 35 } __packed; 36 37 #define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0) 38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7) 39 #define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8) 40 #define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12) 41 #define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16) 42 #define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24) 43 #define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0) 44 #define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8) 45 #define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16) 46 #define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24) 47 #define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0) 48 #define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8) 49 #define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16) 50 51 struct rtw89_h2creg_hdr { 52 u32 w0; 53 }; 54 55 #define RTW89_H2CREG_HDR_FUNC_MASK GENMASK(6, 0) 56 #define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8) 57 58 struct rtw89_h2creg_sch_tx_en { 59 u32 w0; 60 u32 w1; 61 } __packed; 62 63 #define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16) 64 #define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0) 65 #define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16) 66 67 #define RTW89_H2CREG_MAX 4 68 #define RTW89_C2HREG_MAX 4 69 #define RTW89_C2HREG_HDR_LEN 2 70 #define RTW89_H2CREG_HDR_LEN 2 71 #define RTW89_C2H_TIMEOUT 1000000 72 struct rtw89_mac_c2h_info { 73 u8 id; 74 u8 content_len; 75 union { 76 u32 c2hreg[RTW89_C2HREG_MAX]; 77 struct rtw89_c2hreg_hdr hdr; 78 struct rtw89_c2hreg_phycap phycap; 79 } u; 80 }; 81 82 struct rtw89_mac_h2c_info { 83 u8 id; 84 u8 content_len; 85 union { 86 u32 h2creg[RTW89_H2CREG_MAX]; 87 struct rtw89_h2creg_hdr hdr; 88 struct rtw89_h2creg_sch_tx_en sch_tx_en; 89 } u; 90 }; 91 92 enum rtw89_mac_h2c_type { 93 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0, 94 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD, 95 RTW89_FWCMD_H2CREG_FUNC_FWERR, 96 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE, 97 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM, 98 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN 99 }; 100 101 enum rtw89_mac_c2h_type { 102 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0, 103 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT, 104 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG, 105 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP, 106 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT, 107 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF 108 }; 109 110 enum rtw89_fw_c2h_category { 111 RTW89_C2H_CAT_TEST, 112 RTW89_C2H_CAT_MAC, 113 RTW89_C2H_CAT_OUTSRC, 114 }; 115 116 enum rtw89_fw_log_level { 117 RTW89_FW_LOG_LEVEL_OFF, 118 RTW89_FW_LOG_LEVEL_CRT, 119 RTW89_FW_LOG_LEVEL_SER, 120 RTW89_FW_LOG_LEVEL_WARN, 121 RTW89_FW_LOG_LEVEL_LOUD, 122 RTW89_FW_LOG_LEVEL_TR, 123 }; 124 125 enum rtw89_fw_log_path { 126 RTW89_FW_LOG_LEVEL_UART, 127 RTW89_FW_LOG_LEVEL_C2H, 128 RTW89_FW_LOG_LEVEL_SNI, 129 }; 130 131 enum rtw89_fw_log_comp { 132 RTW89_FW_LOG_COMP_VER, 133 RTW89_FW_LOG_COMP_INIT, 134 RTW89_FW_LOG_COMP_TASK, 135 RTW89_FW_LOG_COMP_CNS, 136 RTW89_FW_LOG_COMP_H2C, 137 RTW89_FW_LOG_COMP_C2H, 138 RTW89_FW_LOG_COMP_TX, 139 RTW89_FW_LOG_COMP_RX, 140 RTW89_FW_LOG_COMP_IPSEC, 141 RTW89_FW_LOG_COMP_TIMER, 142 RTW89_FW_LOG_COMP_DBGPKT, 143 RTW89_FW_LOG_COMP_PS, 144 RTW89_FW_LOG_COMP_ERROR, 145 RTW89_FW_LOG_COMP_WOWLAN, 146 RTW89_FW_LOG_COMP_SECURE_BOOT, 147 RTW89_FW_LOG_COMP_BTC, 148 RTW89_FW_LOG_COMP_BB, 149 RTW89_FW_LOG_COMP_TWT, 150 RTW89_FW_LOG_COMP_RF, 151 RTW89_FW_LOG_COMP_MCC = 20, 152 }; 153 154 enum rtw89_pkt_offload_op { 155 RTW89_PKT_OFLD_OP_ADD, 156 RTW89_PKT_OFLD_OP_DEL, 157 RTW89_PKT_OFLD_OP_READ, 158 159 NUM_OF_RTW89_PKT_OFFLOAD_OP, 160 }; 161 162 #define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) \ 163 ((pkt_id) * NUM_OF_RTW89_PKT_OFFLOAD_OP + (pkt_op)) 164 165 enum rtw89_scanofld_notify_reason { 166 RTW89_SCAN_DWELL_NOTIFY, 167 RTW89_SCAN_PRE_TX_NOTIFY, 168 RTW89_SCAN_POST_TX_NOTIFY, 169 RTW89_SCAN_ENTER_CH_NOTIFY, 170 RTW89_SCAN_LEAVE_CH_NOTIFY, 171 RTW89_SCAN_END_SCAN_NOTIFY, 172 }; 173 174 enum rtw89_chan_type { 175 RTW89_CHAN_OPERATE = 0, 176 RTW89_CHAN_ACTIVE, 177 RTW89_CHAN_DFS, 178 }; 179 180 enum rtw89_p2pps_action { 181 RTW89_P2P_ACT_INIT = 0, 182 RTW89_P2P_ACT_UPDATE = 1, 183 RTW89_P2P_ACT_REMOVE = 2, 184 RTW89_P2P_ACT_TERMINATE = 3, 185 }; 186 187 enum rtw89_bcn_fltr_offload_mode { 188 RTW89_BCN_FLTR_OFFLOAD_MODE_0 = 0, 189 RTW89_BCN_FLTR_OFFLOAD_MODE_1, 190 RTW89_BCN_FLTR_OFFLOAD_MODE_2, 191 RTW89_BCN_FLTR_OFFLOAD_MODE_3, 192 193 RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT = RTW89_BCN_FLTR_OFFLOAD_MODE_0, 194 }; 195 196 enum rtw89_bcn_fltr_type { 197 RTW89_BCN_FLTR_BEACON_LOSS, 198 RTW89_BCN_FLTR_RSSI, 199 RTW89_BCN_FLTR_NOTIFY, 200 }; 201 202 enum rtw89_bcn_fltr_rssi_event { 203 RTW89_BCN_FLTR_RSSI_NOT_CHANGED, 204 RTW89_BCN_FLTR_RSSI_HIGH, 205 RTW89_BCN_FLTR_RSSI_LOW, 206 }; 207 208 #define FWDL_SECTION_MAX_NUM 10 209 #define FWDL_SECTION_CHKSUM_LEN 8 210 #define FWDL_SECTION_PER_PKT_LEN 2020 211 212 struct rtw89_fw_hdr_section_info { 213 u8 redl; 214 const u8 *addr; 215 u32 len; 216 u32 dladdr; 217 u32 mssc; 218 u8 type; 219 }; 220 221 struct rtw89_fw_bin_info { 222 u8 section_num; 223 u32 hdr_len; 224 bool dynamic_hdr_en; 225 u32 dynamic_hdr_len; 226 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM]; 227 }; 228 229 struct rtw89_fw_macid_pause_grp { 230 __le32 pause_grp[4]; 231 __le32 mask_grp[4]; 232 } __packed; 233 234 #define RTW89_H2C_MAX_SIZE 2048 235 #define RTW89_CHANNEL_TIME 45 236 #define RTW89_CHANNEL_TIME_6G 20 237 #define RTW89_DFS_CHAN_TIME 105 238 #define RTW89_OFF_CHAN_TIME 100 239 #define RTW89_DWELL_TIME 20 240 #define RTW89_DWELL_TIME_6G 10 241 #define RTW89_SCAN_WIDTH 0 242 #define RTW89_SCANOFLD_MAX_SSID 8 243 #define RTW89_SCANOFLD_MAX_IE_LEN 512 244 #define RTW89_SCANOFLD_PKT_NONE 0xFF 245 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F 246 #define RTW89_MAC_CHINFO_SIZE 28 247 #define RTW89_SCAN_LIST_GUARD 4 248 #define RTW89_SCAN_LIST_LIMIT \ 249 ((RTW89_H2C_MAX_SIZE / RTW89_MAC_CHINFO_SIZE) - RTW89_SCAN_LIST_GUARD) 250 251 #define RTW89_BCN_LOSS_CNT 10 252 253 struct rtw89_mac_chinfo { 254 u8 period; 255 u8 dwell_time; 256 u8 central_ch; 257 u8 pri_ch; 258 u8 bw:3; 259 u8 notify_action:5; 260 u8 num_pkt:4; 261 u8 tx_pkt:1; 262 u8 pause_data:1; 263 u8 ch_band:2; 264 u8 probe_id; 265 u8 dfs_ch:1; 266 u8 tx_null:1; 267 u8 rand_seq_num:1; 268 u8 cfg_tx_pwr:1; 269 u8 rsvd0: 4; 270 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID]; 271 u16 tx_pwr_idx; 272 u8 rsvd1; 273 struct list_head list; 274 bool is_psc; 275 }; 276 277 struct rtw89_scan_option { 278 bool enable; 279 bool target_ch_mode; 280 }; 281 282 struct rtw89_pktofld_info { 283 struct list_head list; 284 u8 id; 285 286 /* Below fields are for 6 GHz RNR use only */ 287 u8 ssid[IEEE80211_MAX_SSID_LEN]; 288 u8 ssid_len; 289 u8 bssid[ETH_ALEN]; 290 u16 channel_6ghz; 291 bool cancel; 292 }; 293 294 static inline void RTW89_SET_FWCMD_RA_IS_DIS(void *cmd, u32 val) 295 { 296 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(0)); 297 } 298 299 static inline void RTW89_SET_FWCMD_RA_MODE(void *cmd, u32 val) 300 { 301 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(5, 1)); 302 } 303 304 static inline void RTW89_SET_FWCMD_RA_BW_CAP(void *cmd, u32 val) 305 { 306 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 6)); 307 } 308 309 static inline void RTW89_SET_FWCMD_RA_MACID(void *cmd, u32 val) 310 { 311 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); 312 } 313 314 static inline void RTW89_SET_FWCMD_RA_DCM(void *cmd, u32 val) 315 { 316 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(16)); 317 } 318 319 static inline void RTW89_SET_FWCMD_RA_ER(void *cmd, u32 val) 320 { 321 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(17)); 322 } 323 324 static inline void RTW89_SET_FWCMD_RA_INIT_RATE_LV(void *cmd, u32 val) 325 { 326 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(19, 18)); 327 } 328 329 static inline void RTW89_SET_FWCMD_RA_UPD_ALL(void *cmd, u32 val) 330 { 331 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(20)); 332 } 333 334 static inline void RTW89_SET_FWCMD_RA_SGI(void *cmd, u32 val) 335 { 336 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(21)); 337 } 338 339 static inline void RTW89_SET_FWCMD_RA_LDPC(void *cmd, u32 val) 340 { 341 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(22)); 342 } 343 344 static inline void RTW89_SET_FWCMD_RA_STBC(void *cmd, u32 val) 345 { 346 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(23)); 347 } 348 349 static inline void RTW89_SET_FWCMD_RA_SS_NUM(void *cmd, u32 val) 350 { 351 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(26, 24)); 352 } 353 354 static inline void RTW89_SET_FWCMD_RA_GILTF(void *cmd, u32 val) 355 { 356 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(29, 27)); 357 } 358 359 static inline void RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(void *cmd, u32 val) 360 { 361 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(30)); 362 } 363 364 static inline void RTW89_SET_FWCMD_RA_UPD_MASK(void *cmd, u32 val) 365 { 366 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(31)); 367 } 368 369 static inline void RTW89_SET_FWCMD_RA_MASK_0(void *cmd, u32 val) 370 { 371 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(7, 0)); 372 } 373 374 static inline void RTW89_SET_FWCMD_RA_MASK_1(void *cmd, u32 val) 375 { 376 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(15, 8)); 377 } 378 379 static inline void RTW89_SET_FWCMD_RA_MASK_2(void *cmd, u32 val) 380 { 381 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(23, 16)); 382 } 383 384 static inline void RTW89_SET_FWCMD_RA_MASK_3(void *cmd, u32 val) 385 { 386 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 24)); 387 } 388 389 static inline void RTW89_SET_FWCMD_RA_MASK_4(void *cmd, u32 val) 390 { 391 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(7, 0)); 392 } 393 394 static inline void RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(void *cmd, u32 val) 395 { 396 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, BIT(31)); 397 } 398 399 static inline void RTW89_SET_FWCMD_RA_BAND_NUM(void *cmd, u32 val) 400 { 401 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(7, 0)); 402 } 403 404 static inline void RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(void *cmd, u32 val) 405 { 406 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(8)); 407 } 408 409 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(void *cmd, u32 val) 410 { 411 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(9)); 412 } 413 414 static inline void RTW89_SET_FWCMD_RA_CR_TBL_SEL(void *cmd, u32 val) 415 { 416 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(10)); 417 } 418 419 static inline void RTW89_SET_FWCMD_RA_FIX_GILTF_EN(void *cmd, u32 val) 420 { 421 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(11)); 422 } 423 424 static inline void RTW89_SET_FWCMD_RA_FIX_GILTF(void *cmd, u32 val) 425 { 426 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(14, 12)); 427 } 428 429 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(void *cmd, u32 val) 430 { 431 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(23, 16)); 432 } 433 434 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(void *cmd, u32 val) 435 { 436 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(25, 24)); 437 } 438 439 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(void *cmd, u32 val) 440 { 441 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(28, 26)); 442 } 443 444 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_BW(void *cmd, u32 val) 445 { 446 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 29)); 447 } 448 449 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val) 450 { 451 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)); 452 } 453 454 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val) 455 { 456 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); 457 } 458 459 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val) 460 { 461 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)); 462 } 463 464 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val) 465 { 466 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0)); 467 } 468 469 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val) 470 { 471 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4)); 472 } 473 474 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val) 475 { 476 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5)); 477 } 478 479 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val) 480 { 481 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0)); 482 } 483 484 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val) 485 { 486 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0)); 487 } 488 489 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val) 490 { 491 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0)); 492 } 493 494 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val) 495 { 496 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0)); 497 } 498 499 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val) 500 { 501 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0)); 502 } 503 504 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val) 505 { 506 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3)); 507 } 508 509 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val) 510 { 511 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4)); 512 } 513 514 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val) 515 { 516 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5)); 517 } 518 519 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val) 520 { 521 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0)); 522 } 523 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16) 524 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12) 525 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8) 526 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0) 527 528 #define FWDL_SECURITY_SECTION_TYPE 9 529 #define FWDL_SECURITY_SIGLEN 512 530 531 struct rtw89_fw_dynhdr_sec { 532 __le32 w0; 533 u8 content[]; 534 } __packed; 535 536 struct rtw89_fw_dynhdr_hdr { 537 __le32 hdr_len; 538 __le32 setcion_count; 539 /* struct rtw89_fw_dynhdr_sec (nested flexible structures) */ 540 } __packed; 541 542 struct rtw89_fw_hdr_section { 543 __le32 w0; 544 __le32 w1; 545 __le32 w2; 546 __le32 w3; 547 } __packed; 548 549 #define FWSECTION_HDR_W0_DL_ADDR GENMASK(31, 0) 550 #define FWSECTION_HDR_W1_METADATA GENMASK(31, 24) 551 #define FWSECTION_HDR_W1_SECTIONTYPE GENMASK(27, 24) 552 #define FWSECTION_HDR_W1_SEC_SIZE GENMASK(23, 0) 553 #define FWSECTION_HDR_W1_CHECKSUM BIT(28) 554 #define FWSECTION_HDR_W1_REDL BIT(29) 555 #define FWSECTION_HDR_W2_MSSC GENMASK(31, 0) 556 557 struct rtw89_fw_hdr { 558 __le32 w0; 559 __le32 w1; 560 __le32 w2; 561 __le32 w3; 562 __le32 w4; 563 __le32 w5; 564 __le32 w6; 565 __le32 w7; 566 struct rtw89_fw_hdr_section sections[]; 567 /* struct rtw89_fw_dynhdr_hdr (optional) */ 568 } __packed; 569 570 #define FW_HDR_W1_MAJOR_VERSION GENMASK(7, 0) 571 #define FW_HDR_W1_MINOR_VERSION GENMASK(15, 8) 572 #define FW_HDR_W1_SUBVERSION GENMASK(23, 16) 573 #define FW_HDR_W1_SUBINDEX GENMASK(31, 24) 574 #define FW_HDR_W3_LEN GENMASK(23, 16) 575 #define FW_HDR_W4_MONTH GENMASK(7, 0) 576 #define FW_HDR_W4_DATE GENMASK(15, 8) 577 #define FW_HDR_W4_HOUR GENMASK(23, 16) 578 #define FW_HDR_W4_MIN GENMASK(31, 24) 579 #define FW_HDR_W5_YEAR GENMASK(31, 0) 580 #define FW_HDR_W6_SEC_NUM GENMASK(15, 8) 581 #define FW_HDR_W7_DYN_HDR BIT(16) 582 #define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24) 583 584 static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val) 585 { 586 le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0)); 587 } 588 589 static inline void SET_CTRL_INFO_MACID(void *table, u32 val) 590 { 591 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)); 592 } 593 594 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val) 595 { 596 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); 597 } 598 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0) 599 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val) 600 { 601 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0)); 602 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE, 603 GENMASK(8, 0)); 604 } 605 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0) 606 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val) 607 { 608 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9)); 609 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP, 610 BIT(9)); 611 } 612 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0) 613 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val) 614 { 615 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10)); 616 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW, 617 GENMASK(11, 10)); 618 } 619 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0) 620 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val) 621 { 622 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12)); 623 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF, 624 GENMASK(14, 12)); 625 } 626 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0) 627 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val) 628 { 629 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); 630 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX, 631 BIT(15)); 632 } 633 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0) 634 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val) 635 { 636 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16)); 637 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL, 638 GENMASK(19, 16)); 639 } 640 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0) 641 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val) 642 { 643 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20)); 644 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN, 645 BIT(20)); 646 } 647 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0) 648 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val) 649 { 650 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21)); 651 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN, 652 BIT(21)); 653 } 654 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0) 655 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val) 656 { 657 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22)); 658 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN, 659 BIT(22)); 660 } 661 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0) 662 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val) 663 { 664 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23)); 665 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN, 666 BIT(23)); 667 } 668 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0) 669 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val) 670 { 671 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25)); 672 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB, 673 BIT(25)); 674 } 675 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0) 676 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val) 677 { 678 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26)); 679 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB, 680 BIT(26)); 681 } 682 #define SET_CMC_TBL_MASK_TRYRATE BIT(0) 683 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val) 684 { 685 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27)); 686 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE, 687 BIT(27)); 688 } 689 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0) 690 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val) 691 { 692 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28)); 693 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY, 694 GENMASK(31, 28)); 695 } 696 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0) 697 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val) 698 { 699 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0)); 700 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE, 701 GENMASK(8, 0)); 702 } 703 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0) 704 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val) 705 { 706 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9)); 707 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL, 708 BIT(9)); 709 } 710 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0) 711 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val) 712 { 713 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10)); 714 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL, 715 BIT(10)); 716 } 717 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0) 718 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val) 719 { 720 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11)); 721 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL, 722 BIT(11)); 723 } 724 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0) 725 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val) 726 { 727 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12)); 728 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT, 729 GENMASK(15, 12)); 730 } 731 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0) 732 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val) 733 { 734 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16)); 735 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE, 736 GENMASK(24, 16)); 737 } 738 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0) 739 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val) 740 { 741 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27)); 742 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC, 743 BIT(27)); 744 } 745 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0) 746 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val) 747 { 748 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28)); 749 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE, 750 GENMASK(31, 28)); 751 } 752 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0) 753 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val) 754 { 755 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0)); 756 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT, 757 GENMASK(5, 0)); 758 } 759 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0) 760 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val) 761 { 762 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6)); 763 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL, 764 BIT(6)); 765 } 766 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0) 767 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val) 768 { 769 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7)); 770 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL, 771 BIT(7)); 772 } 773 #define SET_CMC_TBL_MASK_RTS_EN BIT(0) 774 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val) 775 { 776 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8)); 777 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN, 778 BIT(8)); 779 } 780 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0) 781 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val) 782 { 783 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9)); 784 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN, 785 BIT(9)); 786 } 787 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0) 788 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val) 789 { 790 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10)); 791 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS, 792 GENMASK(11, 10)); 793 } 794 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0) 795 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val) 796 { 797 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12)); 798 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN, 799 BIT(12)); 800 } 801 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0) 802 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val) 803 { 804 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13)); 805 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE, 806 GENMASK(14, 13)); 807 } 808 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0) 809 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val) 810 { 811 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16)); 812 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN, 813 GENMASK(26, 16)); 814 } 815 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0) 816 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val) 817 { 818 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); 819 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS, 820 BIT(27)); 821 } 822 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0) 823 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val) 824 { 825 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28)); 826 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME, 827 GENMASK(31, 28)); 828 } 829 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0) 830 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val) 831 { 832 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0)); 833 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM, 834 GENMASK(7, 0)); 835 } 836 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0) 837 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val) 838 { 839 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8)); 840 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP, 841 GENMASK(9, 8)); 842 } 843 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0) 844 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val) 845 { 846 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16)); 847 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL, 848 GENMASK(18, 16)); 849 } 850 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0) 851 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val) 852 { 853 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19)); 854 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL, 855 GENMASK(21, 19)); 856 } 857 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0) 858 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val) 859 { 860 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22)); 861 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL, 862 GENMASK(24, 22)); 863 } 864 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0) 865 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val) 866 { 867 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25)); 868 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL, 869 GENMASK(27, 25)); 870 } 871 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0) 872 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val) 873 { 874 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28)); 875 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE, 876 GENMASK(31, 28)); 877 } 878 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0) 879 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val) 880 { 881 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0)); 882 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID, 883 GENMASK(2, 0)); 884 } 885 #define SET_CMC_TBL_MASK_BMC BIT(0) 886 static inline void SET_CMC_TBL_BMC(void *table, u32 val) 887 { 888 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3)); 889 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC, 890 BIT(3)); 891 } 892 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0) 893 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val) 894 { 895 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4)); 896 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID, 897 GENMASK(7, 4)); 898 } 899 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0) 900 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val) 901 { 902 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); 903 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR, 904 BIT(8)); 905 } 906 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0) 907 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val) 908 { 909 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9)); 910 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE, 911 GENMASK(11, 9)); 912 } 913 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0) 914 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val) 915 { 916 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12)); 917 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM, 918 BIT(12)); 919 } 920 #define SET_CMC_TBL_MASK_DATA_ER BIT(0) 921 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val) 922 { 923 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13)); 924 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER, 925 BIT(13)); 926 } 927 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0) 928 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val) 929 { 930 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14)); 931 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC, 932 BIT(14)); 933 } 934 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0) 935 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val) 936 { 937 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); 938 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC, 939 BIT(15)); 940 } 941 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0) 942 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val) 943 { 944 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16)); 945 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR, 946 BIT(16)); 947 } 948 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0) 949 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val) 950 { 951 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17)); 952 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH, 953 BIT(17)); 954 } 955 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0) 956 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val) 957 { 958 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18)); 959 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR, 960 BIT(18)); 961 } 962 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0) 963 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val) 964 { 965 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19)); 966 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS, 967 BIT(19)); 968 } 969 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0) 970 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val) 971 { 972 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20)); 973 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER, 974 BIT(20)); 975 } 976 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0) 977 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val) 978 { 979 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21)); 980 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN, 981 BIT(21)); 982 } 983 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0) 984 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val) 985 { 986 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27)); 987 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD, 988 BIT(27)); 989 } 990 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0) 991 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val) 992 { 993 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28)); 994 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT, 995 GENMASK(31, 28)); 996 } 997 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0) 998 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val) 999 { 1000 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0)); 1001 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE, 1002 GENMASK(8, 0)); 1003 } 1004 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0) 1005 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val) 1006 { 1007 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12)); 1008 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT, 1009 BIT(12)); 1010 } 1011 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0) 1012 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val) 1013 { 1014 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13)); 1015 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT, 1016 BIT(13)); 1017 } 1018 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0) 1019 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val) 1020 { 1021 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16)); 1022 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN, 1023 GENMASK(19, 16)); 1024 } 1025 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0) 1026 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val) 1027 { 1028 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20)); 1029 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A, 1030 GENMASK(21, 20)); 1031 } 1032 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0) 1033 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val) 1034 { 1035 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22)); 1036 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B, 1037 GENMASK(23, 22)); 1038 } 1039 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0) 1040 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val) 1041 { 1042 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24)); 1043 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C, 1044 GENMASK(25, 24)); 1045 } 1046 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0) 1047 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val) 1048 { 1049 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26)); 1050 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D, 1051 GENMASK(27, 26)); 1052 } 1053 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0) 1054 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val) 1055 { 1056 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28)); 1057 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A, 1058 BIT(28)); 1059 } 1060 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0) 1061 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val) 1062 { 1063 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29)); 1064 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B, 1065 BIT(29)); 1066 } 1067 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0) 1068 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val) 1069 { 1070 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30)); 1071 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C, 1072 BIT(30)); 1073 } 1074 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0) 1075 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val) 1076 { 1077 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31)); 1078 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D, 1079 BIT(31)); 1080 } 1081 1082 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0) 1083 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val) 1084 { 1085 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0)); 1086 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1087 GENMASK(1, 0)); 1088 } 1089 1090 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val) 1091 { 1092 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2)); 1093 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1094 GENMASK(3, 2)); 1095 } 1096 1097 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val) 1098 { 1099 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4)); 1100 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1101 GENMASK(5, 4)); 1102 } 1103 1104 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val) 1105 { 1106 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6)); 1107 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1108 GENMASK(7, 6)); 1109 } 1110 1111 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0) 1112 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val) 1113 { 1114 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); 1115 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX, 1116 GENMASK(7, 0)); 1117 } 1118 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0) 1119 static inline void SET_CMC_TBL_PAID(void *table, u32 val) 1120 { 1121 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8)); 1122 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID, 1123 GENMASK(16, 8)); 1124 } 1125 #define SET_CMC_TBL_MASK_ULDL BIT(0) 1126 static inline void SET_CMC_TBL_ULDL(void *table, u32 val) 1127 { 1128 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17)); 1129 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL, 1130 BIT(17)); 1131 } 1132 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0) 1133 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val) 1134 { 1135 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18)); 1136 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL, 1137 GENMASK(19, 18)); 1138 } 1139 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val) 1140 { 1141 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20)); 1142 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1143 GENMASK(21, 20)); 1144 } 1145 1146 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val) 1147 { 1148 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22)); 1149 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1150 GENMASK(23, 22)); 1151 } 1152 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0) 1153 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val) 1154 { 1155 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24)); 1156 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE, 1157 GENMASK(27, 24)); 1158 } 1159 1160 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val) 1161 { 1162 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30)); 1163 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1164 GENMASK(31, 30)); 1165 } 1166 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0) 1167 static inline void SET_CMC_TBL_NC(void *table, u32 val) 1168 { 1169 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0)); 1170 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC, 1171 GENMASK(2, 0)); 1172 } 1173 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0) 1174 static inline void SET_CMC_TBL_NR(void *table, u32 val) 1175 { 1176 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3)); 1177 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR, 1178 GENMASK(5, 3)); 1179 } 1180 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0) 1181 static inline void SET_CMC_TBL_NG(void *table, u32 val) 1182 { 1183 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6)); 1184 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG, 1185 GENMASK(7, 6)); 1186 } 1187 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0) 1188 static inline void SET_CMC_TBL_CB(void *table, u32 val) 1189 { 1190 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8)); 1191 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB, 1192 GENMASK(9, 8)); 1193 } 1194 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0) 1195 static inline void SET_CMC_TBL_CS(void *table, u32 val) 1196 { 1197 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10)); 1198 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS, 1199 GENMASK(11, 10)); 1200 } 1201 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0) 1202 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val) 1203 { 1204 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12)); 1205 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN, 1206 BIT(12)); 1207 } 1208 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0) 1209 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val) 1210 { 1211 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13)); 1212 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN, 1213 BIT(13)); 1214 } 1215 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0) 1216 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val) 1217 { 1218 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14)); 1219 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN, 1220 BIT(14)); 1221 } 1222 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0) 1223 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val) 1224 { 1225 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15)); 1226 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN, 1227 BIT(15)); 1228 } 1229 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0) 1230 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val) 1231 { 1232 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16)); 1233 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE, 1234 GENMASK(24, 16)); 1235 } 1236 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0) 1237 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val) 1238 { 1239 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25)); 1240 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF, 1241 GENMASK(27, 25)); 1242 } 1243 1244 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val) 1245 { 1246 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28)); 1247 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1248 GENMASK(29, 28)); 1249 } 1250 1251 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0) 1252 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val) 1253 { 1254 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30)); 1255 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW, 1256 GENMASK(31, 30)); 1257 } 1258 1259 static inline void SET_DCTL_MACID_V1(void *table, u32 val) 1260 { 1261 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)); 1262 } 1263 1264 static inline void SET_DCTL_OPERATION_V1(void *table, u32 val) 1265 { 1266 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); 1267 } 1268 1269 #define SET_DCTL_MASK_QOS_FIELD_V1 GENMASK(7, 0) 1270 static inline void SET_DCTL_QOS_FIELD_V1(void *table, u32 val) 1271 { 1272 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(7, 0)); 1273 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_FIELD_V1, 1274 GENMASK(7, 0)); 1275 } 1276 1277 #define SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID GENMASK(6, 0) 1278 static inline void SET_DCTL_HW_EXSEQ_MACID_V1(void *table, u32 val) 1279 { 1280 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 8)); 1281 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID, 1282 GENMASK(14, 8)); 1283 } 1284 1285 #define SET_DCTL_MASK_QOS_DATA BIT(0) 1286 static inline void SET_DCTL_QOS_DATA_V1(void *table, u32 val) 1287 { 1288 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); 1289 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_DATA, 1290 BIT(15)); 1291 } 1292 1293 #define SET_DCTL_MASK_AES_IV_L GENMASK(15, 0) 1294 static inline void SET_DCTL_AES_IV_L_V1(void *table, u32 val) 1295 { 1296 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 16)); 1297 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_AES_IV_L, 1298 GENMASK(31, 16)); 1299 } 1300 1301 #define SET_DCTL_MASK_AES_IV_H GENMASK(31, 0) 1302 static inline void SET_DCTL_AES_IV_H_V1(void *table, u32 val) 1303 { 1304 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 0)); 1305 le32p_replace_bits((__le32 *)(table) + 10, SET_DCTL_MASK_AES_IV_H, 1306 GENMASK(31, 0)); 1307 } 1308 1309 #define SET_DCTL_MASK_SEQ0 GENMASK(11, 0) 1310 static inline void SET_DCTL_SEQ0_V1(void *table, u32 val) 1311 { 1312 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 0)); 1313 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ0, 1314 GENMASK(11, 0)); 1315 } 1316 1317 #define SET_DCTL_MASK_SEQ1 GENMASK(11, 0) 1318 static inline void SET_DCTL_SEQ1_V1(void *table, u32 val) 1319 { 1320 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(23, 12)); 1321 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ1, 1322 GENMASK(23, 12)); 1323 } 1324 1325 #define SET_DCTL_MASK_AMSDU_MAX_LEN GENMASK(2, 0) 1326 static inline void SET_DCTL_AMSDU_MAX_LEN_V1(void *table, u32 val) 1327 { 1328 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 24)); 1329 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_AMSDU_MAX_LEN, 1330 GENMASK(26, 24)); 1331 } 1332 1333 #define SET_DCTL_MASK_STA_AMSDU_EN BIT(0) 1334 static inline void SET_DCTL_STA_AMSDU_EN_V1(void *table, u32 val) 1335 { 1336 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); 1337 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_STA_AMSDU_EN, 1338 BIT(27)); 1339 } 1340 1341 #define SET_DCTL_MASK_CHKSUM_OFLD_EN BIT(0) 1342 static inline void SET_DCTL_CHKSUM_OFLD_EN_V1(void *table, u32 val) 1343 { 1344 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(28)); 1345 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_CHKSUM_OFLD_EN, 1346 BIT(28)); 1347 } 1348 1349 #define SET_DCTL_MASK_WITH_LLC BIT(0) 1350 static inline void SET_DCTL_WITH_LLC_V1(void *table, u32 val) 1351 { 1352 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(29)); 1353 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_WITH_LLC, 1354 BIT(29)); 1355 } 1356 1357 #define SET_DCTL_MASK_SEQ2 GENMASK(11, 0) 1358 static inline void SET_DCTL_SEQ2_V1(void *table, u32 val) 1359 { 1360 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(11, 0)); 1361 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ2, 1362 GENMASK(11, 0)); 1363 } 1364 1365 #define SET_DCTL_MASK_SEQ3 GENMASK(11, 0) 1366 static inline void SET_DCTL_SEQ3_V1(void *table, u32 val) 1367 { 1368 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(23, 12)); 1369 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ3, 1370 GENMASK(23, 12)); 1371 } 1372 1373 #define SET_DCTL_MASK_TGT_IND GENMASK(3, 0) 1374 static inline void SET_DCTL_TGT_IND_V1(void *table, u32 val) 1375 { 1376 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 24)); 1377 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND, 1378 GENMASK(27, 24)); 1379 } 1380 1381 #define SET_DCTL_MASK_TGT_IND_EN BIT(0) 1382 static inline void SET_DCTL_TGT_IND_EN_V1(void *table, u32 val) 1383 { 1384 le32p_replace_bits((__le32 *)(table) + 4, val, BIT(28)); 1385 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND_EN, 1386 BIT(28)); 1387 } 1388 1389 #define SET_DCTL_MASK_HTC_LB GENMASK(2, 0) 1390 static inline void SET_DCTL_HTC_LB_V1(void *table, u32 val) 1391 { 1392 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 29)); 1393 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_HTC_LB, 1394 GENMASK(31, 29)); 1395 } 1396 1397 #define SET_DCTL_MASK_MHDR_LEN GENMASK(4, 0) 1398 static inline void SET_DCTL_MHDR_LEN_V1(void *table, u32 val) 1399 { 1400 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(4, 0)); 1401 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_MHDR_LEN, 1402 GENMASK(4, 0)); 1403 } 1404 1405 #define SET_DCTL_MASK_VLAN_TAG_VALID BIT(0) 1406 static inline void SET_DCTL_VLAN_TAG_VALID_V1(void *table, u32 val) 1407 { 1408 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(5)); 1409 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_VALID, 1410 BIT(5)); 1411 } 1412 1413 #define SET_DCTL_MASK_VLAN_TAG_SEL GENMASK(1, 0) 1414 static inline void SET_DCTL_VLAN_TAG_SEL_V1(void *table, u32 val) 1415 { 1416 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 6)); 1417 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_SEL, 1418 GENMASK(7, 6)); 1419 } 1420 1421 #define SET_DCTL_MASK_HTC_ORDER BIT(0) 1422 static inline void SET_DCTL_HTC_ORDER_V1(void *table, u32 val) 1423 { 1424 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); 1425 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_HTC_ORDER, 1426 BIT(8)); 1427 } 1428 1429 #define SET_DCTL_MASK_SEC_KEY_ID GENMASK(1, 0) 1430 static inline void SET_DCTL_SEC_KEY_ID_V1(void *table, u32 val) 1431 { 1432 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(10, 9)); 1433 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_KEY_ID, 1434 GENMASK(10, 9)); 1435 } 1436 1437 #define SET_DCTL_MASK_WAPI BIT(0) 1438 static inline void SET_DCTL_WAPI_V1(void *table, u32 val) 1439 { 1440 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); 1441 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_WAPI, 1442 BIT(15)); 1443 } 1444 1445 #define SET_DCTL_MASK_SEC_ENT_MODE GENMASK(1, 0) 1446 static inline void SET_DCTL_SEC_ENT_MODE_V1(void *table, u32 val) 1447 { 1448 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(17, 16)); 1449 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENT_MODE, 1450 GENMASK(17, 16)); 1451 } 1452 1453 #define SET_DCTL_MASK_SEC_ENTX_KEYID GENMASK(1, 0) 1454 static inline void SET_DCTL_SEC_ENT0_KEYID_V1(void *table, u32 val) 1455 { 1456 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(19, 18)); 1457 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1458 GENMASK(19, 18)); 1459 } 1460 1461 static inline void SET_DCTL_SEC_ENT1_KEYID_V1(void *table, u32 val) 1462 { 1463 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(21, 20)); 1464 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1465 GENMASK(21, 20)); 1466 } 1467 1468 static inline void SET_DCTL_SEC_ENT2_KEYID_V1(void *table, u32 val) 1469 { 1470 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(23, 22)); 1471 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1472 GENMASK(23, 22)); 1473 } 1474 1475 static inline void SET_DCTL_SEC_ENT3_KEYID_V1(void *table, u32 val) 1476 { 1477 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(25, 24)); 1478 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1479 GENMASK(25, 24)); 1480 } 1481 1482 static inline void SET_DCTL_SEC_ENT4_KEYID_V1(void *table, u32 val) 1483 { 1484 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(27, 26)); 1485 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1486 GENMASK(27, 26)); 1487 } 1488 1489 static inline void SET_DCTL_SEC_ENT5_KEYID_V1(void *table, u32 val) 1490 { 1491 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(29, 28)); 1492 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1493 GENMASK(29, 28)); 1494 } 1495 1496 static inline void SET_DCTL_SEC_ENT6_KEYID_V1(void *table, u32 val) 1497 { 1498 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 30)); 1499 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1500 GENMASK(31, 30)); 1501 } 1502 1503 #define SET_DCTL_MASK_SEC_ENT_VALID GENMASK(7, 0) 1504 static inline void SET_DCTL_SEC_ENT_VALID_V1(void *table, u32 val) 1505 { 1506 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(7, 0)); 1507 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENT_VALID, 1508 GENMASK(7, 0)); 1509 } 1510 1511 #define SET_DCTL_MASK_SEC_ENTX GENMASK(7, 0) 1512 static inline void SET_DCTL_SEC_ENT0_V1(void *table, u32 val) 1513 { 1514 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(15, 8)); 1515 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1516 GENMASK(15, 8)); 1517 } 1518 1519 static inline void SET_DCTL_SEC_ENT1_V1(void *table, u32 val) 1520 { 1521 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 16)); 1522 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1523 GENMASK(23, 16)); 1524 } 1525 1526 static inline void SET_DCTL_SEC_ENT2_V1(void *table, u32 val) 1527 { 1528 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(31, 24)); 1529 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1530 GENMASK(31, 24)); 1531 } 1532 1533 static inline void SET_DCTL_SEC_ENT3_V1(void *table, u32 val) 1534 { 1535 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); 1536 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1537 GENMASK(7, 0)); 1538 } 1539 1540 static inline void SET_DCTL_SEC_ENT4_V1(void *table, u32 val) 1541 { 1542 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(15, 8)); 1543 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1544 GENMASK(15, 8)); 1545 } 1546 1547 static inline void SET_DCTL_SEC_ENT5_V1(void *table, u32 val) 1548 { 1549 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 16)); 1550 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1551 GENMASK(23, 16)); 1552 } 1553 1554 static inline void SET_DCTL_SEC_ENT6_V1(void *table, u32 val) 1555 { 1556 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 24)); 1557 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1558 GENMASK(31, 24)); 1559 } 1560 1561 static inline void SET_BCN_UPD_PORT(void *h2c, u32 val) 1562 { 1563 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1564 } 1565 1566 static inline void SET_BCN_UPD_MBSSID(void *h2c, u32 val) 1567 { 1568 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1569 } 1570 1571 static inline void SET_BCN_UPD_BAND(void *h2c, u32 val) 1572 { 1573 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1574 } 1575 1576 static inline void SET_BCN_UPD_GRP_IE_OFST(void *h2c, u32 val) 1577 { 1578 le32p_replace_bits((__le32 *)h2c, (val - 24) | BIT(7), GENMASK(31, 24)); 1579 } 1580 1581 static inline void SET_BCN_UPD_MACID(void *h2c, u32 val) 1582 { 1583 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1584 } 1585 1586 static inline void SET_BCN_UPD_SSN_SEL(void *h2c, u32 val) 1587 { 1588 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(9, 8)); 1589 } 1590 1591 static inline void SET_BCN_UPD_SSN_MODE(void *h2c, u32 val) 1592 { 1593 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(11, 10)); 1594 } 1595 1596 static inline void SET_BCN_UPD_RATE(void *h2c, u32 val) 1597 { 1598 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(20, 12)); 1599 } 1600 1601 static inline void SET_BCN_UPD_TXPWR(void *h2c, u32 val) 1602 { 1603 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(23, 21)); 1604 } 1605 1606 static inline void SET_BCN_UPD_TXINFO_CTRL_EN(void *h2c, u32 val) 1607 { 1608 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(0)); 1609 } 1610 1611 static inline void SET_BCN_UPD_NTX_PATH_EN(void *h2c, u32 val) 1612 { 1613 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(4, 1)); 1614 } 1615 1616 static inline void SET_BCN_UPD_PATH_MAP_A(void *h2c, u32 val) 1617 { 1618 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(6, 5)); 1619 } 1620 1621 static inline void SET_BCN_UPD_PATH_MAP_B(void *h2c, u32 val) 1622 { 1623 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(8, 7)); 1624 } 1625 1626 static inline void SET_BCN_UPD_PATH_MAP_C(void *h2c, u32 val) 1627 { 1628 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(10, 9)); 1629 } 1630 1631 static inline void SET_BCN_UPD_PATH_MAP_D(void *h2c, u32 val) 1632 { 1633 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(12, 11)); 1634 } 1635 1636 static inline void SET_BCN_UPD_PATH_ANTSEL_A(void *h2c, u32 val) 1637 { 1638 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(13)); 1639 } 1640 1641 static inline void SET_BCN_UPD_PATH_ANTSEL_B(void *h2c, u32 val) 1642 { 1643 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(14)); 1644 } 1645 1646 static inline void SET_BCN_UPD_PATH_ANTSEL_C(void *h2c, u32 val) 1647 { 1648 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(15)); 1649 } 1650 1651 static inline void SET_BCN_UPD_PATH_ANTSEL_D(void *h2c, u32 val) 1652 { 1653 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(16)); 1654 } 1655 1656 static inline void SET_BCN_UPD_CSA_OFST(void *h2c, u32 val) 1657 { 1658 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 17)); 1659 } 1660 1661 static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val) 1662 { 1663 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1664 } 1665 1666 static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val) 1667 { 1668 le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8)); 1669 } 1670 1671 static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val) 1672 { 1673 le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10)); 1674 } 1675 1676 static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val) 1677 { 1678 le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13)); 1679 } 1680 1681 static inline void SET_JOININFO_MACID(void *h2c, u32 val) 1682 { 1683 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1684 } 1685 1686 static inline void SET_JOININFO_OP(void *h2c, u32 val) 1687 { 1688 le32p_replace_bits((__le32 *)h2c, val, BIT(8)); 1689 } 1690 1691 static inline void SET_JOININFO_BAND(void *h2c, u32 val) 1692 { 1693 le32p_replace_bits((__le32 *)h2c, val, BIT(9)); 1694 } 1695 1696 static inline void SET_JOININFO_WMM(void *h2c, u32 val) 1697 { 1698 le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10)); 1699 } 1700 1701 static inline void SET_JOININFO_TGR(void *h2c, u32 val) 1702 { 1703 le32p_replace_bits((__le32 *)h2c, val, BIT(12)); 1704 } 1705 1706 static inline void SET_JOININFO_ISHESTA(void *h2c, u32 val) 1707 { 1708 le32p_replace_bits((__le32 *)h2c, val, BIT(13)); 1709 } 1710 1711 static inline void SET_JOININFO_DLBW(void *h2c, u32 val) 1712 { 1713 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14)); 1714 } 1715 1716 static inline void SET_JOININFO_TF_MAC_PAD(void *h2c, u32 val) 1717 { 1718 le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16)); 1719 } 1720 1721 static inline void SET_JOININFO_DL_T_PE(void *h2c, u32 val) 1722 { 1723 le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18)); 1724 } 1725 1726 static inline void SET_JOININFO_PORT_ID(void *h2c, u32 val) 1727 { 1728 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21)); 1729 } 1730 1731 static inline void SET_JOININFO_NET_TYPE(void *h2c, u32 val) 1732 { 1733 le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24)); 1734 } 1735 1736 static inline void SET_JOININFO_WIFI_ROLE(void *h2c, u32 val) 1737 { 1738 le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26)); 1739 } 1740 1741 static inline void SET_JOININFO_SELF_ROLE(void *h2c, u32 val) 1742 { 1743 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30)); 1744 } 1745 1746 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val) 1747 { 1748 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1749 } 1750 1751 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val) 1752 { 1753 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1754 } 1755 1756 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val) 1757 { 1758 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1759 } 1760 1761 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val) 1762 { 1763 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1764 } 1765 1766 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val) 1767 { 1768 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1769 } 1770 1771 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val) 1772 { 1773 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); 1774 } 1775 1776 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val) 1777 { 1778 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1779 } 1780 1781 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val) 1782 { 1783 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1784 } 1785 1786 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val) 1787 { 1788 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)); 1789 } 1790 1791 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val) 1792 { 1793 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0)); 1794 } 1795 1796 static inline void SET_BA_CAM_VALID(void *h2c, u32 val) 1797 { 1798 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 1799 } 1800 1801 static inline void SET_BA_CAM_INIT_REQ(void *h2c, u32 val) 1802 { 1803 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 1804 } 1805 1806 static inline void SET_BA_CAM_ENTRY_IDX(void *h2c, u32 val) 1807 { 1808 le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2)); 1809 } 1810 1811 static inline void SET_BA_CAM_TID(void *h2c, u32 val) 1812 { 1813 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4)); 1814 } 1815 1816 static inline void SET_BA_CAM_MACID(void *h2c, u32 val) 1817 { 1818 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1819 } 1820 1821 static inline void SET_BA_CAM_BMAP_SIZE(void *h2c, u32 val) 1822 { 1823 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); 1824 } 1825 1826 static inline void SET_BA_CAM_SSN(void *h2c, u32 val) 1827 { 1828 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20)); 1829 } 1830 1831 static inline void SET_BA_CAM_UID(void *h2c, u32 val) 1832 { 1833 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(7, 0)); 1834 } 1835 1836 static inline void SET_BA_CAM_STD_EN(void *h2c, u32 val) 1837 { 1838 le32p_replace_bits((__le32 *)h2c + 1, val, BIT(8)); 1839 } 1840 1841 static inline void SET_BA_CAM_BAND(void *h2c, u32 val) 1842 { 1843 le32p_replace_bits((__le32 *)h2c + 1, val, BIT(9)); 1844 } 1845 1846 static inline void SET_BA_CAM_ENTRY_IDX_V1(void *h2c, u32 val) 1847 { 1848 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 28)); 1849 } 1850 1851 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val) 1852 { 1853 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1854 } 1855 1856 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val) 1857 { 1858 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1859 } 1860 1861 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val) 1862 { 1863 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); 1864 } 1865 1866 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val) 1867 { 1868 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20)); 1869 } 1870 1871 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val) 1872 { 1873 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1874 } 1875 1876 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val) 1877 { 1878 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0)); 1879 } 1880 1881 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val) 1882 { 1883 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1)); 1884 } 1885 1886 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val) 1887 { 1888 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2)); 1889 } 1890 1891 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val) 1892 { 1893 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3)); 1894 } 1895 1896 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val) 1897 { 1898 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); 1899 } 1900 1901 static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val) 1902 { 1903 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0)); 1904 } 1905 1906 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val) 1907 { 1908 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 1909 } 1910 1911 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val) 1912 { 1913 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 1914 } 1915 1916 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val) 1917 { 1918 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 1919 } 1920 1921 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val) 1922 { 1923 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 1924 } 1925 1926 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val) 1927 { 1928 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0)); 1929 } 1930 1931 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val) 1932 { 1933 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8)); 1934 } 1935 1936 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val) 1937 { 1938 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 1939 } 1940 1941 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val) 1942 { 1943 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0)); 1944 } 1945 1946 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val) 1947 { 1948 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0)); 1949 } 1950 1951 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val) 1952 { 1953 le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0)); 1954 } 1955 1956 static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val) 1957 { 1958 le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0)); 1959 } 1960 1961 static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val) 1962 { 1963 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1964 } 1965 1966 static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val) 1967 { 1968 le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16)); 1969 } 1970 1971 static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val) 1972 { 1973 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1974 } 1975 1976 static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val) 1977 { 1978 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 1979 } 1980 1981 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val) 1982 { 1983 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 1984 } 1985 1986 static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val) 1987 { 1988 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); 1989 } 1990 1991 static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val) 1992 { 1993 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1994 } 1995 1996 static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val) 1997 { 1998 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1999 } 2000 2001 static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val) 2002 { 2003 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 2004 } 2005 2006 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val) 2007 { 2008 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 2009 } 2010 2011 static inline void RTW89_SET_WOW_GLOBAL_ENABLE(void *h2c, u32 val) 2012 { 2013 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 2014 } 2015 2016 static inline void RTW89_SET_WOW_GLOBAL_DROP_ALL_PKT(void *h2c, u32 val) 2017 { 2018 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 2019 } 2020 2021 static inline void RTW89_SET_WOW_GLOBAL_RX_PARSE_AFTER_WAKE(void *h2c, u32 val) 2022 { 2023 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); 2024 } 2025 2026 static inline void RTW89_SET_WOW_GLOBAL_WAKE_BAR_PULLED(void *h2c, u32 val) 2027 { 2028 le32p_replace_bits((__le32 *)h2c, val, BIT(3)); 2029 } 2030 2031 static inline void RTW89_SET_WOW_GLOBAL_MAC_ID(void *h2c, u32 val) 2032 { 2033 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 2034 } 2035 2036 static inline void RTW89_SET_WOW_GLOBAL_PAIRWISE_SEC_ALGO(void *h2c, u32 val) 2037 { 2038 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 2039 } 2040 2041 static inline void RTW89_SET_WOW_GLOBAL_GROUP_SEC_ALGO(void *h2c, u32 val) 2042 { 2043 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 2044 } 2045 2046 static inline void RTW89_SET_WOW_GLOBAL_REMOTECTRL_INFO_CONTENT(void *h2c, u32 val) 2047 { 2048 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)); 2049 } 2050 2051 static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val) 2052 { 2053 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 2054 } 2055 2056 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val) 2057 { 2058 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 2059 } 2060 2061 static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val) 2062 { 2063 le32p_replace_bits((__le32 *)h2c, val, BIT(2)); 2064 } 2065 2066 static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val) 2067 { 2068 le32p_replace_bits((__le32 *)h2c, val, BIT(3)); 2069 } 2070 2071 static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val) 2072 { 2073 le32p_replace_bits((__le32 *)h2c, val, BIT(4)); 2074 } 2075 2076 static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val) 2077 { 2078 le32p_replace_bits((__le32 *)h2c, val, BIT(5)); 2079 } 2080 2081 static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val) 2082 { 2083 le32p_replace_bits((__le32 *)h2c, val, BIT(6)); 2084 } 2085 2086 static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val) 2087 { 2088 le32p_replace_bits((__le32 *)h2c, val, BIT(7)); 2089 } 2090 2091 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val) 2092 { 2093 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 2094 } 2095 2096 static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val) 2097 { 2098 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 2099 } 2100 2101 static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val) 2102 { 2103 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1)); 2104 } 2105 2106 static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val) 2107 { 2108 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0)); 2109 } 2110 2111 static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val) 2112 { 2113 le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0)); 2114 } 2115 2116 static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val) 2117 { 2118 le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0)); 2119 } 2120 2121 static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val) 2122 { 2123 le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0)); 2124 } 2125 2126 static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val) 2127 { 2128 le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0)); 2129 } 2130 2131 static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val) 2132 { 2133 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22)); 2134 } 2135 2136 static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val) 2137 { 2138 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23)); 2139 } 2140 2141 static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val) 2142 { 2143 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24)); 2144 } 2145 2146 static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val) 2147 { 2148 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25)); 2149 } 2150 2151 static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val) 2152 { 2153 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26)); 2154 } 2155 2156 static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val) 2157 { 2158 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31)); 2159 } 2160 2161 enum rtw89_btc_btf_h2c_class { 2162 BTFC_SET = 0x10, 2163 BTFC_GET = 0x11, 2164 BTFC_FW_EVENT = 0x12, 2165 }; 2166 2167 enum rtw89_btc_btf_set { 2168 SET_REPORT_EN = 0x0, 2169 SET_SLOT_TABLE, 2170 SET_MREG_TABLE, 2171 SET_CX_POLICY, 2172 SET_GPIO_DBG, 2173 SET_DRV_INFO, 2174 SET_DRV_EVENT, 2175 SET_BT_WREG_ADDR, 2176 SET_BT_WREG_VAL, 2177 SET_BT_RREG_ADDR, 2178 SET_BT_WL_CH_INFO, 2179 SET_BT_INFO_REPORT, 2180 SET_BT_IGNORE_WLAN_ACT, 2181 SET_BT_TX_PWR, 2182 SET_BT_LNA_CONSTRAIN, 2183 SET_BT_GOLDEN_RX_RANGE, 2184 SET_BT_PSD_REPORT, 2185 SET_H2C_TEST, 2186 SET_MAX1, 2187 }; 2188 2189 enum rtw89_btc_cxdrvinfo { 2190 CXDRVINFO_INIT = 0, 2191 CXDRVINFO_ROLE, 2192 CXDRVINFO_DBCC, 2193 CXDRVINFO_SMAP, 2194 CXDRVINFO_RFK, 2195 CXDRVINFO_RUN, 2196 CXDRVINFO_CTRL, 2197 CXDRVINFO_SCAN, 2198 CXDRVINFO_TRX, /* WL traffic to WL fw */ 2199 CXDRVINFO_MAX, 2200 }; 2201 2202 enum rtw89_scan_mode { 2203 RTW89_SCAN_IMMEDIATE, 2204 }; 2205 2206 enum rtw89_scan_type { 2207 RTW89_SCAN_ONCE, 2208 }; 2209 2210 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val) 2211 { 2212 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0)); 2213 } 2214 2215 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val) 2216 { 2217 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0)); 2218 } 2219 2220 struct rtw89_h2c_cxhdr { 2221 u8 type; 2222 u8 len; 2223 } __packed; 2224 2225 #define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr) 2226 2227 struct rtw89_h2c_cxinit { 2228 struct rtw89_h2c_cxhdr hdr; 2229 u8 ant_type; 2230 u8 ant_num; 2231 u8 ant_iso; 2232 u8 ant_info; 2233 u8 mod_rfe; 2234 u8 mod_cv; 2235 u8 mod_info; 2236 u8 mod_adie_kt; 2237 u8 wl_gch; 2238 u8 info; 2239 u8 rsvd; 2240 u8 rsvd1; 2241 } __packed; 2242 2243 #define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0) 2244 #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1) 2245 #define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2) 2246 #define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4) 2247 2248 #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0) 2249 #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1) 2250 #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2) 2251 #define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3) 2252 2253 #define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0) 2254 #define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1) 2255 #define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2) 2256 #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3) 2257 #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4) 2258 2259 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val) 2260 { 2261 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)); 2262 } 2263 2264 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val) 2265 { 2266 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)); 2267 } 2268 2269 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val) 2270 { 2271 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0)); 2272 } 2273 2274 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val) 2275 { 2276 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1)); 2277 } 2278 2279 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val) 2280 { 2281 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2)); 2282 } 2283 2284 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val) 2285 { 2286 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3)); 2287 } 2288 2289 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val) 2290 { 2291 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4)); 2292 } 2293 2294 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val) 2295 { 2296 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5)); 2297 } 2298 2299 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val) 2300 { 2301 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6)); 2302 } 2303 2304 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val) 2305 { 2306 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7)); 2307 } 2308 2309 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val) 2310 { 2311 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8)); 2312 } 2313 2314 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val) 2315 { 2316 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9)); 2317 } 2318 2319 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val) 2320 { 2321 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10)); 2322 } 2323 2324 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val) 2325 { 2326 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11)); 2327 } 2328 2329 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset) 2330 { 2331 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0)); 2332 } 2333 2334 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset) 2335 { 2336 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1)); 2337 } 2338 2339 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset) 2340 { 2341 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4)); 2342 } 2343 2344 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset) 2345 { 2346 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5)); 2347 } 2348 2349 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset) 2350 { 2351 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6)); 2352 } 2353 2354 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset) 2355 { 2356 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0)); 2357 } 2358 2359 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset) 2360 { 2361 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1)); 2362 } 2363 2364 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset) 2365 { 2366 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0)); 2367 } 2368 2369 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset) 2370 { 2371 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0)); 2372 } 2373 2374 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset) 2375 { 2376 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0)); 2377 } 2378 2379 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset) 2380 { 2381 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0)); 2382 } 2383 2384 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset) 2385 { 2386 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0)); 2387 } 2388 2389 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset) 2390 { 2391 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0)); 2392 } 2393 2394 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset) 2395 { 2396 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0)); 2397 } 2398 2399 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset) 2400 { 2401 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0)); 2402 } 2403 2404 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset) 2405 { 2406 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1)); 2407 } 2408 2409 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset) 2410 { 2411 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4)); 2412 } 2413 2414 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset) 2415 { 2416 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5)); 2417 } 2418 2419 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset) 2420 { 2421 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6)); 2422 } 2423 2424 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset) 2425 { 2426 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0)); 2427 } 2428 2429 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset) 2430 { 2431 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1)); 2432 } 2433 2434 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset) 2435 { 2436 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0)); 2437 } 2438 2439 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset) 2440 { 2441 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0)); 2442 } 2443 2444 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset) 2445 { 2446 le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0)); 2447 } 2448 2449 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset) 2450 { 2451 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0)); 2452 } 2453 2454 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset) 2455 { 2456 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0)); 2457 } 2458 2459 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset) 2460 { 2461 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0)); 2462 } 2463 2464 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset) 2465 { 2466 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1)); 2467 } 2468 2469 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset) 2470 { 2471 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2)); 2472 } 2473 2474 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset) 2475 { 2476 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4)); 2477 } 2478 2479 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val) 2480 { 2481 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0)); 2482 } 2483 2484 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val) 2485 { 2486 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1)); 2487 } 2488 2489 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val) 2490 { 2491 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2)); 2492 } 2493 2494 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val) 2495 { 2496 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3)); 2497 } 2498 2499 static inline void RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val) 2500 { 2501 u8p_replace_bits((u8 *)cmd + 2, val, GENMASK(7, 0)); 2502 } 2503 2504 static inline void RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val) 2505 { 2506 u8p_replace_bits((u8 *)cmd + 3, val, GENMASK(7, 0)); 2507 } 2508 2509 static inline void RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val) 2510 { 2511 u8p_replace_bits((u8 *)cmd + 4, val, GENMASK(7, 0)); 2512 } 2513 2514 static inline void RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val) 2515 { 2516 u8p_replace_bits((u8 *)cmd + 5, val, GENMASK(7, 0)); 2517 } 2518 2519 static inline void RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val) 2520 { 2521 u8p_replace_bits((u8 *)cmd + 6, val, GENMASK(7, 0)); 2522 } 2523 2524 static inline void RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val) 2525 { 2526 u8p_replace_bits((u8 *)cmd + 7, val, GENMASK(7, 0)); 2527 } 2528 2529 static inline void RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val) 2530 { 2531 u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0)); 2532 } 2533 2534 static inline void RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val) 2535 { 2536 u8p_replace_bits((u8 *)cmd + 9, val, GENMASK(7, 0)); 2537 } 2538 2539 static inline void RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val) 2540 { 2541 u8p_replace_bits((u8 *)cmd + 10, val, GENMASK(7, 0)); 2542 } 2543 2544 static inline void RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val) 2545 { 2546 u8p_replace_bits((u8 *)cmd + 11, val, GENMASK(7, 0)); 2547 } 2548 2549 static inline void RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val) 2550 { 2551 u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0)); 2552 } 2553 2554 static inline void RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val) 2555 { 2556 u8p_replace_bits((u8 *)cmd + 13, val, GENMASK(7, 0)); 2557 } 2558 2559 static inline void RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val) 2560 { 2561 le16p_replace_bits((__le16 *)((u8 *)cmd + 14), val, GENMASK(15, 0)); 2562 } 2563 2564 static inline void RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val) 2565 { 2566 le16p_replace_bits((__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0)); 2567 } 2568 2569 static inline void RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val) 2570 { 2571 le32p_replace_bits((__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0)); 2572 } 2573 2574 static inline void RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val) 2575 { 2576 le32p_replace_bits((__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0)); 2577 } 2578 2579 static inline void RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val) 2580 { 2581 le32p_replace_bits((__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0)); 2582 } 2583 2584 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val) 2585 { 2586 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0)); 2587 } 2588 2589 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val) 2590 { 2591 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2)); 2592 } 2593 2594 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val) 2595 { 2596 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6)); 2597 } 2598 2599 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val) 2600 { 2601 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8)); 2602 } 2603 2604 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val) 2605 { 2606 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10)); 2607 } 2608 2609 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val) 2610 { 2611 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2612 } 2613 2614 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val) 2615 { 2616 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8)); 2617 } 2618 2619 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val) 2620 { 2621 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16)); 2622 } 2623 2624 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_NUM(void *cmd, u32 val) 2625 { 2626 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2627 } 2628 2629 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_SIZE(void *cmd, u32 val) 2630 { 2631 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8)); 2632 } 2633 2634 static inline void RTW89_SET_FWCMD_CHINFO_PERIOD(void *cmd, u32 val) 2635 { 2636 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2637 } 2638 2639 static inline void RTW89_SET_FWCMD_CHINFO_DWELL(void *cmd, u32 val) 2640 { 2641 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8)); 2642 } 2643 2644 static inline void RTW89_SET_FWCMD_CHINFO_CENTER_CH(void *cmd, u32 val) 2645 { 2646 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 16)); 2647 } 2648 2649 static inline void RTW89_SET_FWCMD_CHINFO_PRI_CH(void *cmd, u32 val) 2650 { 2651 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 24)); 2652 } 2653 2654 static inline void RTW89_SET_FWCMD_CHINFO_BW(void *cmd, u32 val) 2655 { 2656 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(2, 0)); 2657 } 2658 2659 static inline void RTW89_SET_FWCMD_CHINFO_ACTION(void *cmd, u32 val) 2660 { 2661 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 3)); 2662 } 2663 2664 static inline void RTW89_SET_FWCMD_CHINFO_NUM_PKT(void *cmd, u32 val) 2665 { 2666 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(11, 8)); 2667 } 2668 2669 static inline void RTW89_SET_FWCMD_CHINFO_TX(void *cmd, u32 val) 2670 { 2671 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(12)); 2672 } 2673 2674 static inline void RTW89_SET_FWCMD_CHINFO_PAUSE_DATA(void *cmd, u32 val) 2675 { 2676 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(13)); 2677 } 2678 2679 static inline void RTW89_SET_FWCMD_CHINFO_BAND(void *cmd, u32 val) 2680 { 2681 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 14)); 2682 } 2683 2684 static inline void RTW89_SET_FWCMD_CHINFO_PKT_ID(void *cmd, u32 val) 2685 { 2686 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16)); 2687 } 2688 2689 static inline void RTW89_SET_FWCMD_CHINFO_DFS(void *cmd, u32 val) 2690 { 2691 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(24)); 2692 } 2693 2694 static inline void RTW89_SET_FWCMD_CHINFO_TX_NULL(void *cmd, u32 val) 2695 { 2696 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(25)); 2697 } 2698 2699 static inline void RTW89_SET_FWCMD_CHINFO_RANDOM(void *cmd, u32 val) 2700 { 2701 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(26)); 2702 } 2703 2704 static inline void RTW89_SET_FWCMD_CHINFO_CFG_TX(void *cmd, u32 val) 2705 { 2706 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(27)); 2707 } 2708 2709 static inline void RTW89_SET_FWCMD_CHINFO_PKT0(void *cmd, u32 val) 2710 { 2711 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(7, 0)); 2712 } 2713 2714 static inline void RTW89_SET_FWCMD_CHINFO_PKT1(void *cmd, u32 val) 2715 { 2716 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 8)); 2717 } 2718 2719 static inline void RTW89_SET_FWCMD_CHINFO_PKT2(void *cmd, u32 val) 2720 { 2721 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16)); 2722 } 2723 2724 static inline void RTW89_SET_FWCMD_CHINFO_PKT3(void *cmd, u32 val) 2725 { 2726 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(31, 24)); 2727 } 2728 2729 static inline void RTW89_SET_FWCMD_CHINFO_PKT4(void *cmd, u32 val) 2730 { 2731 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(7, 0)); 2732 } 2733 2734 static inline void RTW89_SET_FWCMD_CHINFO_PKT5(void *cmd, u32 val) 2735 { 2736 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(15, 8)); 2737 } 2738 2739 static inline void RTW89_SET_FWCMD_CHINFO_PKT6(void *cmd, u32 val) 2740 { 2741 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(23, 16)); 2742 } 2743 2744 static inline void RTW89_SET_FWCMD_CHINFO_PKT7(void *cmd, u32 val) 2745 { 2746 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 24)); 2747 } 2748 2749 static inline void RTW89_SET_FWCMD_CHINFO_POWER_IDX(void *cmd, u32 val) 2750 { 2751 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(15, 0)); 2752 } 2753 2754 struct rtw89_h2c_scanofld { 2755 __le32 w0; 2756 __le32 w1; 2757 __le32 w2; 2758 __le32 tsf_high; 2759 __le32 tsf_low; 2760 __le32 w5; 2761 __le32 w6; 2762 } __packed; 2763 2764 #define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0) 2765 #define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8) 2766 #define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16) 2767 #define RTW89_H2C_SCANOFLD_W0_BAND BIT(19) 2768 #define RTW89_H2C_SCANOFLD_W0_OPERATION GENMASK(21, 20) 2769 #define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND GENMASK(23, 22) 2770 #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0) 2771 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1) 2772 #define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2) 2773 #define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE GENMASK(4, 3) 2774 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5) 2775 #define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8) 2776 #define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16) 2777 #define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24) 2778 #define RTW89_H2C_SCANOFLD_W2_NORM_PD GENMASK(15, 0) 2779 #define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16) 2780 2781 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val) 2782 { 2783 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 2784 } 2785 2786 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val) 2787 { 2788 le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8)); 2789 } 2790 2791 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val) 2792 { 2793 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12)); 2794 } 2795 2796 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val) 2797 { 2798 le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16)); 2799 } 2800 2801 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val) 2802 { 2803 le32p_replace_bits((__le32 *)cmd, val, BIT(20)); 2804 } 2805 2806 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val) 2807 { 2808 le32p_replace_bits((__le32 *)cmd, val, BIT(21)); 2809 } 2810 2811 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val) 2812 { 2813 *((__le32 *)cmd + 1) = val; 2814 } 2815 2816 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val) 2817 { 2818 *((__le32 *)cmd + 2) = val; 2819 } 2820 2821 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val) 2822 { 2823 *((__le32 *)cmd + 3) = val; 2824 } 2825 2826 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val) 2827 { 2828 le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0)); 2829 } 2830 2831 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val) 2832 { 2833 u8 ctwnd; 2834 2835 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT)) 2836 return; 2837 ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val); 2838 le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8)); 2839 } 2840 2841 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val) 2842 { 2843 le32p_replace_bits((__le32 *)cmd, val, BIT(0)); 2844 } 2845 2846 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val) 2847 { 2848 le32p_replace_bits((__le32 *)cmd, val, BIT(1)); 2849 } 2850 2851 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val) 2852 { 2853 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2)); 2854 } 2855 2856 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val) 2857 { 2858 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16)); 2859 } 2860 2861 enum rtw89_fw_mcc_c2h_rpt_cfg { 2862 RTW89_FW_MCC_C2H_RPT_OFF = 0, 2863 RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1, 2864 RTW89_FW_MCC_C2H_RPT_ALL = 2, 2865 }; 2866 2867 struct rtw89_fw_mcc_add_req { 2868 u8 macid; 2869 u8 central_ch_seg0; 2870 u8 central_ch_seg1; 2871 u8 primary_ch; 2872 enum rtw89_bandwidth bandwidth: 4; 2873 u32 group: 2; 2874 u32 c2h_rpt: 2; 2875 u32 dis_tx_null: 1; 2876 u32 dis_sw_retry: 1; 2877 u32 in_curr_ch: 1; 2878 u32 sw_retry_count: 3; 2879 u32 tx_null_early: 4; 2880 u32 btc_in_2g: 1; 2881 u32 pta_en: 1; 2882 u32 rfk_by_pass: 1; 2883 u32 ch_band_type: 2; 2884 u32 rsvd0: 9; 2885 u32 duration; 2886 u8 courtesy_en; 2887 u8 courtesy_num; 2888 u8 courtesy_target; 2889 u8 rsvd1; 2890 }; 2891 2892 static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val) 2893 { 2894 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 2895 } 2896 2897 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val) 2898 { 2899 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 2900 } 2901 2902 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val) 2903 { 2904 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 2905 } 2906 2907 static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val) 2908 { 2909 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 2910 } 2911 2912 static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val) 2913 { 2914 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0)); 2915 } 2916 2917 static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val) 2918 { 2919 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4)); 2920 } 2921 2922 static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val) 2923 { 2924 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6)); 2925 } 2926 2927 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val) 2928 { 2929 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8)); 2930 } 2931 2932 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val) 2933 { 2934 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9)); 2935 } 2936 2937 static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val) 2938 { 2939 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10)); 2940 } 2941 2942 static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val) 2943 { 2944 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11)); 2945 } 2946 2947 static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val) 2948 { 2949 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14)); 2950 } 2951 2952 static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val) 2953 { 2954 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18)); 2955 } 2956 2957 static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val) 2958 { 2959 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19)); 2960 } 2961 2962 static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val) 2963 { 2964 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20)); 2965 } 2966 2967 static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val) 2968 { 2969 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21)); 2970 } 2971 2972 static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val) 2973 { 2974 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 2975 } 2976 2977 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val) 2978 { 2979 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0)); 2980 } 2981 2982 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val) 2983 { 2984 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8)); 2985 } 2986 2987 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val) 2988 { 2989 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16)); 2990 } 2991 2992 struct rtw89_fw_mcc_start_req { 2993 u32 group: 2; 2994 u32 btc_in_group: 1; 2995 u32 old_group_action: 2; 2996 u32 old_group: 2; 2997 u32 rsvd0: 9; 2998 u32 notify_cnt: 3; 2999 u32 rsvd1: 2; 3000 u32 notify_rxdbg_en: 1; 3001 u32 rsvd2: 2; 3002 u32 macid: 8; 3003 u32 tsf_low; 3004 u32 tsf_high; 3005 }; 3006 3007 static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val) 3008 { 3009 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3010 } 3011 3012 static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val) 3013 { 3014 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 3015 } 3016 3017 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val) 3018 { 3019 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3)); 3020 } 3021 3022 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val) 3023 { 3024 le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5)); 3025 } 3026 3027 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val) 3028 { 3029 le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16)); 3030 } 3031 3032 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val) 3033 { 3034 le32p_replace_bits((__le32 *)cmd, val, BIT(21)); 3035 } 3036 3037 static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val) 3038 { 3039 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 3040 } 3041 3042 static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val) 3043 { 3044 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0)); 3045 } 3046 3047 static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val) 3048 { 3049 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 3050 } 3051 3052 static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val) 3053 { 3054 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0)); 3055 } 3056 3057 static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val) 3058 { 3059 le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8)); 3060 } 3061 3062 static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val) 3063 { 3064 le32p_replace_bits((__le32 *)cmd, val, BIT(10)); 3065 } 3066 3067 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val) 3068 { 3069 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3070 } 3071 3072 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val) 3073 { 3074 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 3075 } 3076 3077 static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val) 3078 { 3079 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3080 } 3081 3082 struct rtw89_fw_mcc_tsf_req { 3083 u8 group: 2; 3084 u8 rsvd0: 6; 3085 u8 macid_x; 3086 u8 macid_y; 3087 u8 rsvd1; 3088 }; 3089 3090 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val) 3091 { 3092 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3093 } 3094 3095 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val) 3096 { 3097 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3098 } 3099 3100 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val) 3101 { 3102 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3103 } 3104 3105 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val) 3106 { 3107 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3108 } 3109 3110 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val) 3111 { 3112 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3113 } 3114 3115 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val) 3116 { 3117 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3118 } 3119 3120 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd, 3121 u8 *bitmap, u8 len) 3122 { 3123 memcpy((__le32 *)cmd + 1, bitmap, len); 3124 } 3125 3126 static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val) 3127 { 3128 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3129 } 3130 3131 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val) 3132 { 3133 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3134 } 3135 3136 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val) 3137 { 3138 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3139 } 3140 3141 static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val) 3142 { 3143 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 3144 } 3145 3146 struct rtw89_fw_mcc_duration { 3147 u32 group: 2; 3148 u32 btc_in_group: 1; 3149 u32 rsvd0: 5; 3150 u32 start_macid: 8; 3151 u32 macid_x: 8; 3152 u32 macid_y: 8; 3153 u32 start_tsf_low; 3154 u32 start_tsf_high; 3155 u32 duration_x; 3156 u32 duration_y; 3157 }; 3158 3159 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val) 3160 { 3161 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0)); 3162 } 3163 3164 static 3165 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val) 3166 { 3167 le32p_replace_bits((__le32 *)cmd, val, BIT(2)); 3168 } 3169 3170 static 3171 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val) 3172 { 3173 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8)); 3174 } 3175 3176 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val) 3177 { 3178 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16)); 3179 } 3180 3181 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val) 3182 { 3183 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24)); 3184 } 3185 3186 static 3187 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val) 3188 { 3189 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0)); 3190 } 3191 3192 static 3193 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val) 3194 { 3195 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0)); 3196 } 3197 3198 static 3199 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val) 3200 { 3201 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0)); 3202 } 3203 3204 static 3205 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val) 3206 { 3207 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0)); 3208 } 3209 3210 #define RTW89_C2H_HEADER_LEN 8 3211 3212 #define RTW89_GET_C2H_CATEGORY(c2h) \ 3213 le32_get_bits(*((const __le32 *)c2h), GENMASK(1, 0)) 3214 #define RTW89_GET_C2H_CLASS(c2h) \ 3215 le32_get_bits(*((const __le32 *)c2h), GENMASK(7, 2)) 3216 #define RTW89_GET_C2H_FUNC(c2h) \ 3217 le32_get_bits(*((const __le32 *)c2h), GENMASK(15, 8)) 3218 #define RTW89_GET_C2H_LEN(c2h) \ 3219 le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(13, 0)) 3220 3221 struct rtw89_fw_c2h_attr { 3222 u8 category; 3223 u8 class; 3224 u8 func; 3225 u16 len; 3226 }; 3227 3228 static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb) 3229 { 3230 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr)); 3231 3232 return (struct rtw89_fw_c2h_attr *)skb->cb; 3233 } 3234 3235 #define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2) 3236 #define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN) 3237 3238 struct rtw89_c2h_done_ack { 3239 __le32 w0; 3240 __le32 w1; 3241 __le32 w2; 3242 } __packed; 3243 3244 #define RTW89_C2H_DONE_ACK_W2_CAT GENMASK(1, 0) 3245 #define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2) 3246 #define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8) 3247 #define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16) 3248 #define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24) 3249 3250 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \ 3251 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3252 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \ 3253 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 3254 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \ 3255 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3256 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \ 3257 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 3258 3259 struct rtw89_c2h_mac_bcnfltr_rpt { 3260 __le32 w0; 3261 __le32 w1; 3262 __le32 w2; 3263 } __packed; 3264 3265 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0) 3266 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8) 3267 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10) 3268 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16) 3269 3270 #define RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h) \ 3271 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 0)) 3272 #define RTW89_GET_PHY_C2H_RA_RPT_RETRY_RATIO(c2h) \ 3273 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 3274 #define RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h) \ 3275 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(6, 0)) 3276 #define RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h) \ 3277 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(9, 8)) 3278 #define RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h) \ 3279 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(12, 10)) 3280 #define RTW89_GET_PHY_C2H_RA_RPT_BW(c2h) \ 3281 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(14, 13)) 3282 3283 /* VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS 3284 * HT-new: [6:5]: NA, [4:0]: MCS 3285 */ 3286 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4) 3287 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0) 3288 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0) 3289 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \ 3290 FIELD_PREP(GENMASK(2, 0), mcs)) 3291 3292 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \ 3293 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 3294 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \ 3295 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8)) 3296 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \ 3297 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16)) 3298 3299 #define RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h) \ 3300 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 3301 #define RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h) \ 3302 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(19, 16)) 3303 #define RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h) \ 3304 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 20)) 3305 #define RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h) \ 3306 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24)) 3307 #define RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h) \ 3308 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(3, 0)) 3309 #define RTW89_GET_MAC_C2H_SCANOFLD_AIR_DENSITY(c2h) \ 3310 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(7, 4)) 3311 #define RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h) \ 3312 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(25, 24)) 3313 3314 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \ 3315 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3316 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \ 3317 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3318 3319 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \ 3320 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 3321 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \ 3322 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 3323 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \ 3324 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3325 3326 struct rtw89_mac_mcc_tsf_rpt { 3327 u32 macid_x; 3328 u32 macid_y; 3329 u32 tsf_x_low; 3330 u32 tsf_x_high; 3331 u32 tsf_y_low; 3332 u32 tsf_y_high; 3333 }; 3334 3335 static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE); 3336 3337 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \ 3338 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 3339 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \ 3340 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3341 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \ 3342 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16)) 3343 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \ 3344 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0)) 3345 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \ 3346 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0)) 3347 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \ 3348 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0)) 3349 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \ 3350 le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0)) 3351 3352 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \ 3353 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0)) 3354 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \ 3355 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6)) 3356 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \ 3357 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 3358 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \ 3359 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0)) 3360 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \ 3361 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0)) 3362 3363 struct rtw89_c2h_pkt_ofld_rsp { 3364 __le32 w0; 3365 __le32 w1; 3366 __le32 w2; 3367 } __packed; 3368 3369 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0) 3370 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8) 3371 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16) 3372 3373 struct rtw89_h2c_bcnfltr { 3374 __le32 w0; 3375 } __packed; 3376 3377 #define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0) 3378 #define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1) 3379 #define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2) 3380 #define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3) 3381 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT GENMASK(11, 8) 3382 #define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12) 3383 #define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16) 3384 #define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24) 3385 3386 struct rtw89_h2c_ofld_rssi { 3387 __le32 w0; 3388 __le32 w1; 3389 } __packed; 3390 3391 #define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0) 3392 #define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8) 3393 #define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0) 3394 3395 struct rtw89_h2c_ofld { 3396 __le32 w0; 3397 } __packed; 3398 3399 #define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0) 3400 #define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8) 3401 #define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18) 3402 3403 #define RTW89_MFW_SIG 0xFF 3404 3405 struct rtw89_mfw_info { 3406 u8 cv; 3407 u8 type; /* enum rtw89_fw_type */ 3408 u8 mp; 3409 u8 rsvd; 3410 __le32 shift; 3411 __le32 size; 3412 u8 rsvd2[4]; 3413 } __packed; 3414 3415 struct rtw89_mfw_hdr { 3416 u8 sig; /* RTW89_MFW_SIG */ 3417 u8 fw_nr; 3418 u8 rsvd0[2]; 3419 struct { 3420 u8 major; 3421 u8 minor; 3422 u8 sub; 3423 u8 idx; 3424 } ver; 3425 u8 rsvd1[8]; 3426 struct rtw89_mfw_info info[]; 3427 } __packed; 3428 3429 struct fwcmd_hdr { 3430 __le32 hdr0; 3431 __le32 hdr1; 3432 }; 3433 3434 union rtw89_compat_fw_hdr { 3435 struct rtw89_mfw_hdr mfw_hdr; 3436 struct rtw89_fw_hdr fw_hdr; 3437 }; 3438 3439 static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf) 3440 { 3441 const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf; 3442 3443 if (compat->mfw_hdr.sig == RTW89_MFW_SIG) 3444 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr); 3445 else 3446 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr); 3447 } 3448 3449 static inline void rtw89_fw_get_filename(char *buf, size_t size, 3450 const char *fw_basename, int fw_format) 3451 { 3452 if (fw_format <= 0) 3453 snprintf(buf, size, "%s.bin", fw_basename); 3454 else 3455 snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format); 3456 } 3457 3458 #define RTW89_H2C_RF_PAGE_SIZE 500 3459 #define RTW89_H2C_RF_PAGE_NUM 3 3460 struct rtw89_fw_h2c_rf_reg_info { 3461 enum rtw89_rf_path rf_path; 3462 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE]; 3463 u16 curr_idx; 3464 }; 3465 3466 #define H2C_SEC_CAM_LEN 24 3467 3468 #define H2C_HEADER_LEN 8 3469 #define H2C_HDR_CAT GENMASK(1, 0) 3470 #define H2C_HDR_CLASS GENMASK(7, 2) 3471 #define H2C_HDR_FUNC GENMASK(15, 8) 3472 #define H2C_HDR_DEL_TYPE GENMASK(19, 16) 3473 #define H2C_HDR_H2C_SEQ GENMASK(31, 24) 3474 #define H2C_HDR_TOTAL_LEN GENMASK(13, 0) 3475 #define H2C_HDR_REC_ACK BIT(14) 3476 #define H2C_HDR_DONE_ACK BIT(15) 3477 3478 #define FWCMD_TYPE_H2C 0 3479 3480 #define H2C_CAT_TEST 0x0 3481 3482 /* CLASS 5 - FW STATUS TEST */ 3483 #define H2C_CL_FW_STATUS_TEST 0x5 3484 #define H2C_FUNC_CPU_EXCEPTION 0x1 3485 3486 #define H2C_CAT_MAC 0x1 3487 3488 /* CLASS 0 - FW INFO */ 3489 #define H2C_CL_FW_INFO 0x0 3490 #define H2C_FUNC_LOG_CFG 0x0 3491 #define H2C_FUNC_MAC_GENERAL_PKT 0x1 3492 3493 /* CLASS 1 - WOW */ 3494 #define H2C_CL_MAC_WOW 0x1 3495 #define H2C_FUNC_KEEP_ALIVE 0x0 3496 #define H2C_FUNC_DISCONNECT_DETECT 0x1 3497 #define H2C_FUNC_WOW_GLOBAL 0x2 3498 #define H2C_FUNC_WAKEUP_CTRL 0x8 3499 #define H2C_FUNC_WOW_CAM_UPD 0xC 3500 3501 /* CLASS 2 - PS */ 3502 #define H2C_CL_MAC_PS 0x2 3503 #define H2C_FUNC_MAC_LPS_PARM 0x0 3504 #define H2C_FUNC_P2P_ACT 0x1 3505 3506 /* CLASS 3 - FW download */ 3507 #define H2C_CL_MAC_FWDL 0x3 3508 #define H2C_FUNC_MAC_FWHDR_DL 0x0 3509 3510 /* CLASS 5 - Frame Exchange */ 3511 #define H2C_CL_MAC_FR_EXCHG 0x5 3512 #define H2C_FUNC_MAC_CCTLINFO_UD 0x2 3513 #define H2C_FUNC_MAC_BCN_UPD 0x5 3514 #define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9 3515 #define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa 3516 3517 /* CLASS 6 - Address CAM */ 3518 #define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6 3519 #define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0 3520 3521 /* CLASS 8 - Media Status Report */ 3522 #define H2C_CL_MAC_MEDIA_RPT 0x8 3523 #define H2C_FUNC_MAC_JOININFO 0x0 3524 #define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4 3525 3526 /* CLASS 9 - FW offload */ 3527 #define H2C_CL_MAC_FW_OFLD 0x9 3528 enum rtw89_fw_ofld_h2c_func { 3529 H2C_FUNC_PACKET_OFLD = 0x1, 3530 H2C_FUNC_MAC_MACID_PAUSE = 0x8, 3531 H2C_FUNC_USR_EDCA = 0xF, 3532 H2C_FUNC_TSF32_TOGL = 0x10, 3533 H2C_FUNC_OFLD_CFG = 0x14, 3534 H2C_FUNC_ADD_SCANOFLD_CH = 0x16, 3535 H2C_FUNC_SCANOFLD = 0x17, 3536 H2C_FUNC_PKT_DROP = 0x1b, 3537 H2C_FUNC_CFG_BCNFLTR = 0x1e, 3538 H2C_FUNC_OFLD_RSSI = 0x1f, 3539 H2C_FUNC_OFLD_TP = 0x20, 3540 3541 NUM_OF_RTW89_FW_OFLD_H2C_FUNC, 3542 }; 3543 3544 #define RTW89_FW_OFLD_WAIT_COND(tag, func) \ 3545 ((tag) * NUM_OF_RTW89_FW_OFLD_H2C_FUNC + (func)) 3546 3547 #define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \ 3548 RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \ 3549 H2C_FUNC_PACKET_OFLD) 3550 3551 /* CLASS 10 - Security CAM */ 3552 #define H2C_CL_MAC_SEC_CAM 0xa 3553 #define H2C_FUNC_MAC_SEC_UPD 0x1 3554 3555 /* CLASS 12 - BA CAM */ 3556 #define H2C_CL_BA_CAM 0xc 3557 #define H2C_FUNC_MAC_BA_CAM 0x0 3558 3559 /* CLASS 14 - MCC */ 3560 #define H2C_CL_MCC 0xe 3561 enum rtw89_mcc_h2c_func { 3562 H2C_FUNC_ADD_MCC = 0x0, 3563 H2C_FUNC_START_MCC = 0x1, 3564 H2C_FUNC_STOP_MCC = 0x2, 3565 H2C_FUNC_DEL_MCC_GROUP = 0x3, 3566 H2C_FUNC_RESET_MCC_GROUP = 0x4, 3567 H2C_FUNC_MCC_REQ_TSF = 0x5, 3568 H2C_FUNC_MCC_MACID_BITMAP = 0x6, 3569 H2C_FUNC_MCC_SYNC = 0x7, 3570 H2C_FUNC_MCC_SET_DURATION = 0x8, 3571 3572 NUM_OF_RTW89_MCC_H2C_FUNC, 3573 }; 3574 3575 #define RTW89_MCC_WAIT_COND(group, func) \ 3576 ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func)) 3577 3578 #define H2C_CAT_OUTSRC 0x2 3579 3580 #define H2C_CL_OUTSRC_RA 0x1 3581 #define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0 3582 3583 #define H2C_CL_OUTSRC_RF_REG_A 0x8 3584 #define H2C_CL_OUTSRC_RF_REG_B 0x9 3585 #define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa 3586 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2 3587 3588 struct rtw89_fw_h2c_rf_get_mccch { 3589 __le32 ch_0; 3590 __le32 ch_1; 3591 __le32 band_0; 3592 __le32 band_1; 3593 __le32 current_channel; 3594 __le32 current_band_type; 3595 } __packed; 3596 3597 #define RTW89_FW_RSVD_PLE_SIZE 0x800 3598 3599 #define RTW89_WCPU_BASE_MASK GENMASK(27, 0) 3600 3601 #define RTW89_FW_BACKTRACE_INFO_SIZE 8 3602 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \ 3603 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0) 3604 3605 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */ 3606 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE 3607 3608 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev); 3609 int rtw89_fw_recognize(struct rtw89_dev *rtwdev); 3610 const struct firmware * 3611 rtw89_early_fw_feature_recognize(struct device *device, 3612 const struct rtw89_chip_info *chip, 3613 struct rtw89_fw_info *early_fw, 3614 int *used_fw_format); 3615 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type); 3616 void rtw89_load_firmware_work(struct work_struct *work); 3617 void rtw89_unload_firmware(struct rtw89_dev *rtwdev); 3618 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev); 3619 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb, 3620 u8 type, u8 cat, u8 class, u8 func, 3621 bool rack, bool dack, u32 len); 3622 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, 3623 struct rtw89_vif *rtwvif); 3624 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, 3625 struct ieee80211_vif *vif, 3626 struct ieee80211_sta *sta); 3627 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev, 3628 struct rtw89_sta *rtwsta); 3629 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev, 3630 struct rtw89_sta *rtwsta); 3631 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev, 3632 struct rtw89_vif *rtwvif); 3633 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif, 3634 struct rtw89_sta *rtwsta, const u8 *scan_mac_addr); 3635 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev, 3636 struct rtw89_vif *rtwvif, 3637 struct rtw89_sta *rtwsta); 3638 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h); 3639 void rtw89_fw_c2h_work(struct work_struct *work); 3640 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev, 3641 struct rtw89_vif *rtwvif, 3642 struct rtw89_sta *rtwsta, 3643 enum rtw89_upd_mode upd_mode); 3644 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3645 struct rtw89_sta *rtwsta, bool dis_conn); 3646 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp, 3647 bool pause); 3648 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3649 u8 ac, u32 val); 3650 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev); 3651 int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev, 3652 struct ieee80211_vif *vif, 3653 bool connect); 3654 int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev, 3655 struct rtw89_rx_phy_ppdu *phy_ppdu); 3656 int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 3657 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi); 3658 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev); 3659 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev); 3660 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev); 3661 int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev); 3662 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev); 3663 int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev); 3664 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev); 3665 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id); 3666 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id, 3667 struct sk_buff *skb_ofld); 3668 int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int len, 3669 struct list_head *chan_list); 3670 int rtw89_fw_h2c_scan_offload(struct rtw89_dev *rtwdev, 3671 struct rtw89_scan_option *opt, 3672 struct rtw89_vif *vif); 3673 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev, 3674 struct rtw89_fw_h2c_rf_reg_info *info, 3675 u16 len, u8 page); 3676 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev); 3677 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, 3678 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, 3679 bool rack, bool dack); 3680 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len); 3681 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev); 3682 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev); 3683 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3684 u8 macid); 3685 void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev, 3686 struct rtw89_vif *rtwvif, bool notify_fw); 3687 void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw); 3688 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 3689 bool valid, struct ieee80211_ampdu_params *params); 3690 void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev); 3691 3692 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev, 3693 struct rtw89_lps_parm *lps_param); 3694 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len); 3695 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len); 3696 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev, 3697 struct rtw89_mac_h2c_info *h2c_info, 3698 struct rtw89_mac_c2h_info *c2h_info); 3699 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable); 3700 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev); 3701 void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3702 struct ieee80211_scan_request *req); 3703 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3704 bool aborted); 3705 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3706 bool enable); 3707 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 3708 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev); 3709 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev, 3710 const struct rtw89_pkt_drop_params *params); 3711 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3712 struct ieee80211_p2p_noa_desc *desc, 3713 u8 act, u8 noa_id); 3714 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3715 bool en); 3716 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3717 bool enable); 3718 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev, 3719 struct rtw89_vif *rtwvif, bool enable); 3720 int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3721 bool enable); 3722 int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev, 3723 struct rtw89_vif *rtwvif, bool enable); 3724 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3725 bool enable); 3726 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev, 3727 struct rtw89_vif *rtwvif, bool enable); 3728 int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev, 3729 struct rtw89_wow_cam_info *cam_info); 3730 int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev, 3731 const struct rtw89_fw_mcc_add_req *p); 3732 int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev, 3733 const struct rtw89_fw_mcc_start_req *p); 3734 int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid, 3735 bool prev_groups); 3736 int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group, 3737 bool prev_groups); 3738 int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group); 3739 int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev, 3740 const struct rtw89_fw_mcc_tsf_req *req, 3741 struct rtw89_mac_mcc_tsf_rpt *rpt); 3742 int rtw89_fw_h2c_mcc_macid_bitamp(struct rtw89_dev *rtwdev, u8 group, u8 macid, 3743 u8 *bitmap); 3744 int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source, 3745 u8 target, u8 offset); 3746 int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev, 3747 const struct rtw89_fw_mcc_duration *p); 3748 3749 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev) 3750 { 3751 const struct rtw89_chip_info *chip = rtwdev->chip; 3752 3753 if (chip->bacam_ver == RTW89_BACAM_V0_EXT) 3754 rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev); 3755 } 3756 3757 #endif 3758