1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include <linux/vmalloc.h> 6 7 #include "coex.h" 8 #include "debug.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "ps.h" 12 #include "reg.h" 13 #include "sar.h" 14 15 #ifdef CONFIG_RTW89_DEBUGMSG 16 unsigned int rtw89_debug_mask; 17 EXPORT_SYMBOL(rtw89_debug_mask); 18 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 19 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 20 #endif 21 22 #ifdef CONFIG_RTW89_DEBUGFS 23 struct rtw89_debugfs_priv { 24 struct rtw89_dev *rtwdev; 25 int (*cb_read)(struct seq_file *m, void *v); 26 ssize_t (*cb_write)(struct file *filp, const char __user *buffer, 27 size_t count, loff_t *loff); 28 union { 29 u32 cb_data; 30 struct { 31 u32 addr; 32 u8 len; 33 } read_reg; 34 struct { 35 u32 addr; 36 u32 mask; 37 u8 path; 38 } read_rf; 39 struct { 40 u8 ss_dbg:1; 41 u8 dle_dbg:1; 42 u8 dmac_dbg:1; 43 u8 cmac_dbg:1; 44 u8 dbg_port:1; 45 } dbgpkg_en; 46 struct { 47 u32 start; 48 u32 len; 49 u8 sel; 50 } mac_mem; 51 }; 52 }; 53 54 static int rtw89_debugfs_single_show(struct seq_file *m, void *v) 55 { 56 struct rtw89_debugfs_priv *debugfs_priv = m->private; 57 58 return debugfs_priv->cb_read(m, v); 59 } 60 61 static ssize_t rtw89_debugfs_single_write(struct file *filp, 62 const char __user *buffer, 63 size_t count, loff_t *loff) 64 { 65 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 66 67 return debugfs_priv->cb_write(filp, buffer, count, loff); 68 } 69 70 static ssize_t rtw89_debugfs_seq_file_write(struct file *filp, 71 const char __user *buffer, 72 size_t count, loff_t *loff) 73 { 74 struct seq_file *seqpriv = (struct seq_file *)filp->private_data; 75 struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private; 76 77 return debugfs_priv->cb_write(filp, buffer, count, loff); 78 } 79 80 static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp) 81 { 82 return single_open(filp, rtw89_debugfs_single_show, inode->i_private); 83 } 84 85 static int rtw89_debugfs_close(struct inode *inode, struct file *filp) 86 { 87 return 0; 88 } 89 90 static const struct file_operations file_ops_single_r = { 91 .owner = THIS_MODULE, 92 .open = rtw89_debugfs_single_open, 93 .read = seq_read, 94 .llseek = seq_lseek, 95 .release = single_release, 96 }; 97 98 static const struct file_operations file_ops_common_rw = { 99 .owner = THIS_MODULE, 100 .open = rtw89_debugfs_single_open, 101 .release = single_release, 102 .read = seq_read, 103 .llseek = seq_lseek, 104 .write = rtw89_debugfs_seq_file_write, 105 }; 106 107 static const struct file_operations file_ops_single_w = { 108 .owner = THIS_MODULE, 109 .write = rtw89_debugfs_single_write, 110 .open = simple_open, 111 .release = rtw89_debugfs_close, 112 }; 113 114 static ssize_t 115 rtw89_debug_priv_read_reg_select(struct file *filp, 116 const char __user *user_buf, 117 size_t count, loff_t *loff) 118 { 119 struct seq_file *m = (struct seq_file *)filp->private_data; 120 struct rtw89_debugfs_priv *debugfs_priv = m->private; 121 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 122 char buf[32]; 123 size_t buf_size; 124 u32 addr, len; 125 int num; 126 127 buf_size = min(count, sizeof(buf) - 1); 128 if (copy_from_user(buf, user_buf, buf_size)) 129 return -EFAULT; 130 131 buf[buf_size] = '\0'; 132 num = sscanf(buf, "%x %x", &addr, &len); 133 if (num != 2) { 134 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 135 return -EINVAL; 136 } 137 138 debugfs_priv->read_reg.addr = addr; 139 debugfs_priv->read_reg.len = len; 140 141 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 142 143 return count; 144 } 145 146 static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v) 147 { 148 struct rtw89_debugfs_priv *debugfs_priv = m->private; 149 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 150 u32 addr, data; 151 u8 len; 152 153 len = debugfs_priv->read_reg.len; 154 addr = debugfs_priv->read_reg.addr; 155 156 switch (len) { 157 case 1: 158 data = rtw89_read8(rtwdev, addr); 159 break; 160 case 2: 161 data = rtw89_read16(rtwdev, addr); 162 break; 163 case 4: 164 data = rtw89_read32(rtwdev, addr); 165 break; 166 default: 167 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 168 return -EINVAL; 169 } 170 171 seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data); 172 173 return 0; 174 } 175 176 static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp, 177 const char __user *user_buf, 178 size_t count, loff_t *loff) 179 { 180 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 181 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 182 char buf[32]; 183 size_t buf_size; 184 u32 addr, val, len; 185 int num; 186 187 buf_size = min(count, sizeof(buf) - 1); 188 if (copy_from_user(buf, user_buf, buf_size)) 189 return -EFAULT; 190 191 buf[buf_size] = '\0'; 192 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 193 if (num != 3) { 194 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 195 return -EINVAL; 196 } 197 198 switch (len) { 199 case 1: 200 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 201 rtw89_write8(rtwdev, addr, (u8)val); 202 break; 203 case 2: 204 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 205 rtw89_write16(rtwdev, addr, (u16)val); 206 break; 207 case 4: 208 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 209 rtw89_write32(rtwdev, addr, (u32)val); 210 break; 211 default: 212 rtw89_info(rtwdev, "invalid read write len %d\n", len); 213 break; 214 } 215 216 return count; 217 } 218 219 static ssize_t 220 rtw89_debug_priv_read_rf_select(struct file *filp, 221 const char __user *user_buf, 222 size_t count, loff_t *loff) 223 { 224 struct seq_file *m = (struct seq_file *)filp->private_data; 225 struct rtw89_debugfs_priv *debugfs_priv = m->private; 226 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 227 char buf[32]; 228 size_t buf_size; 229 u32 addr, mask; 230 u8 path; 231 int num; 232 233 buf_size = min(count, sizeof(buf) - 1); 234 if (copy_from_user(buf, user_buf, buf_size)) 235 return -EFAULT; 236 237 buf[buf_size] = '\0'; 238 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 239 if (num != 3) { 240 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 241 return -EINVAL; 242 } 243 244 if (path >= rtwdev->chip->rf_path_num) { 245 rtw89_info(rtwdev, "wrong rf path\n"); 246 return -EINVAL; 247 } 248 debugfs_priv->read_rf.addr = addr; 249 debugfs_priv->read_rf.mask = mask; 250 debugfs_priv->read_rf.path = path; 251 252 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 253 254 return count; 255 } 256 257 static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v) 258 { 259 struct rtw89_debugfs_priv *debugfs_priv = m->private; 260 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 261 u32 addr, data, mask; 262 u8 path; 263 264 addr = debugfs_priv->read_rf.addr; 265 mask = debugfs_priv->read_rf.mask; 266 path = debugfs_priv->read_rf.path; 267 268 data = rtw89_read_rf(rtwdev, path, addr, mask); 269 270 seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data); 271 272 return 0; 273 } 274 275 static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp, 276 const char __user *user_buf, 277 size_t count, loff_t *loff) 278 { 279 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 280 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 281 char buf[32]; 282 size_t buf_size; 283 u32 addr, val, mask; 284 u8 path; 285 int num; 286 287 buf_size = min(count, sizeof(buf) - 1); 288 if (copy_from_user(buf, user_buf, buf_size)) 289 return -EFAULT; 290 291 buf[buf_size] = '\0'; 292 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 293 if (num != 4) { 294 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 295 return -EINVAL; 296 } 297 298 if (path >= rtwdev->chip->rf_path_num) { 299 rtw89_info(rtwdev, "wrong rf path\n"); 300 return -EINVAL; 301 } 302 303 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 304 path, addr, val, mask); 305 rtw89_write_rf(rtwdev, path, addr, mask, val); 306 307 return count; 308 } 309 310 static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v) 311 { 312 struct rtw89_debugfs_priv *debugfs_priv = m->private; 313 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 314 const struct rtw89_chip_info *chip = rtwdev->chip; 315 u32 addr, offset, data; 316 u8 path; 317 318 for (path = 0; path < chip->rf_path_num; path++) { 319 seq_printf(m, "RF path %d:\n\n", path); 320 for (addr = 0; addr < 0x100; addr += 4) { 321 seq_printf(m, "0x%08x: ", addr); 322 for (offset = 0; offset < 4; offset++) { 323 data = rtw89_read_rf(rtwdev, path, 324 addr + offset, RFREG_MASK); 325 seq_printf(m, "0x%05x ", data); 326 } 327 seq_puts(m, "\n"); 328 } 329 seq_puts(m, "\n"); 330 } 331 332 return 0; 333 } 334 335 struct txpwr_ent { 336 const char *txt; 337 u8 len; 338 }; 339 340 struct txpwr_map { 341 const struct txpwr_ent *ent; 342 u8 size; 343 u32 addr_from; 344 u32 addr_to; 345 }; 346 347 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 348 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 349 350 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 351 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 352 353 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 354 { .len = 8, .txt = _t "\t- " \ 355 _e0 " " _e1 " " _e2 " " _e3 " " \ 356 _e4 " " _e5 " " _e6 " " _e7 } 357 358 static const struct txpwr_ent __txpwr_ent_byr[] = { 359 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 360 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 361 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 362 /* 1NSS */ 363 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 364 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 365 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 366 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 367 /* 2NSS */ 368 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 369 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 370 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 371 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 372 }; 373 374 static_assert((ARRAY_SIZE(__txpwr_ent_byr) * 4) == 375 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 376 377 static const struct txpwr_map __txpwr_map_byr = { 378 .ent = __txpwr_ent_byr, 379 .size = ARRAY_SIZE(__txpwr_ent_byr), 380 .addr_from = R_AX_PWR_BY_RATE, 381 .addr_to = R_AX_PWR_BY_RATE_MAX, 382 }; 383 384 static const struct txpwr_ent __txpwr_ent_lmt[] = { 385 /* 1TX */ 386 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 387 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 388 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 389 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 390 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 391 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 392 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 393 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 394 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 395 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 396 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 397 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 398 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 399 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 400 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 401 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 402 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 403 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 404 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 405 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 406 /* 2TX */ 407 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 408 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 409 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 410 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 411 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 412 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 413 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 414 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 415 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 416 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 417 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 418 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 419 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 420 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 421 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 422 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 423 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 424 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 425 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 426 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 427 }; 428 429 static_assert((ARRAY_SIZE(__txpwr_ent_lmt) * 2) == 430 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 431 432 static const struct txpwr_map __txpwr_map_lmt = { 433 .ent = __txpwr_ent_lmt, 434 .size = ARRAY_SIZE(__txpwr_ent_lmt), 435 .addr_from = R_AX_PWR_LMT, 436 .addr_to = R_AX_PWR_LMT_MAX, 437 }; 438 439 static const struct txpwr_ent __txpwr_ent_lmt_ru[] = { 440 /* 1TX */ 441 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 442 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 443 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 444 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 445 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 446 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 447 /* 2TX */ 448 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 449 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 450 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 451 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 452 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 453 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 454 }; 455 456 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru) * 8) == 457 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 458 459 static const struct txpwr_map __txpwr_map_lmt_ru = { 460 .ent = __txpwr_ent_lmt_ru, 461 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru), 462 .addr_from = R_AX_PWR_RU_LMT, 463 .addr_to = R_AX_PWR_RU_LMT_MAX, 464 }; 465 466 static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent, 467 const u8 *buf, const u8 cur) 468 { 469 char *fmt; 470 471 switch (ent->len) { 472 case 2: 473 fmt = "%s\t| %3d, %3d,\tdBm\n"; 474 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]); 475 return 2; 476 case 4: 477 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 478 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 479 buf[cur + 2], buf[cur + 3]); 480 return 4; 481 case 8: 482 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 483 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 484 buf[cur + 2], buf[cur + 3], buf[cur + 4], 485 buf[cur + 5], buf[cur + 6], buf[cur + 7]); 486 return 8; 487 default: 488 return 0; 489 } 490 } 491 492 static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev, 493 const struct txpwr_map *map) 494 { 495 u8 fct = rtwdev->chip->txpwr_factor_mac; 496 u8 *buf, cur, i; 497 u32 val, addr; 498 int ret; 499 500 buf = vzalloc(map->addr_to - map->addr_from + 4); 501 if (!buf) 502 return -ENOMEM; 503 504 for (addr = map->addr_from; addr <= map->addr_to; addr += 4) { 505 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 506 if (ret) 507 val = MASKDWORD; 508 509 cur = addr - map->addr_from; 510 for (i = 0; i < 4; i++, val >>= 8) 511 buf[cur + i] = FIELD_GET(MASKBYTE0, val) >> fct; 512 } 513 514 for (cur = 0, i = 0; i < map->size; i++) 515 cur += __print_txpwr_ent(m, &map->ent[i], buf, cur); 516 517 vfree(buf); 518 return 0; 519 } 520 521 #define case_REGD(_regd) \ 522 case RTW89_ ## _regd: \ 523 seq_puts(m, #_regd "\n"); \ 524 break 525 526 static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev) 527 { 528 u8 band = rtwdev->hal.current_band_type; 529 u8 regd = rtw89_regd_get(rtwdev, band); 530 531 switch (regd) { 532 default: 533 seq_printf(m, "UNKNOWN: %d\n", regd); 534 break; 535 case_REGD(WW); 536 case_REGD(ETSI); 537 case_REGD(FCC); 538 case_REGD(MKK); 539 case_REGD(NA); 540 case_REGD(IC); 541 case_REGD(KCC); 542 case_REGD(NCC); 543 case_REGD(CHILE); 544 case_REGD(ACMA); 545 case_REGD(MEXICO); 546 case_REGD(UKRAINE); 547 case_REGD(CN); 548 } 549 } 550 551 #undef case_REGD 552 553 static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v) 554 { 555 struct rtw89_debugfs_priv *debugfs_priv = m->private; 556 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 557 int ret = 0; 558 559 mutex_lock(&rtwdev->mutex); 560 rtw89_leave_ps_mode(rtwdev); 561 562 seq_puts(m, "[Regulatory] "); 563 __print_regd(m, rtwdev); 564 565 seq_puts(m, "[SAR]\n"); 566 rtw89_print_sar(m, rtwdev); 567 568 seq_puts(m, "\n[TX power byrate]\n"); 569 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_byr); 570 if (ret) 571 goto err; 572 573 seq_puts(m, "\n[TX power limit]\n"); 574 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt); 575 if (ret) 576 goto err; 577 578 seq_puts(m, "\n[TX power limit_ru]\n"); 579 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt_ru); 580 if (ret) 581 goto err; 582 583 err: 584 mutex_unlock(&rtwdev->mutex); 585 return ret; 586 } 587 588 static ssize_t 589 rtw89_debug_priv_mac_reg_dump_select(struct file *filp, 590 const char __user *user_buf, 591 size_t count, loff_t *loff) 592 { 593 struct seq_file *m = (struct seq_file *)filp->private_data; 594 struct rtw89_debugfs_priv *debugfs_priv = m->private; 595 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 596 char buf[32]; 597 size_t buf_size; 598 int sel; 599 int ret; 600 601 buf_size = min(count, sizeof(buf) - 1); 602 if (copy_from_user(buf, user_buf, buf_size)) 603 return -EFAULT; 604 605 buf[buf_size] = '\0'; 606 ret = kstrtoint(buf, 0, &sel); 607 if (ret) 608 return ret; 609 610 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 611 rtw89_info(rtwdev, "invalid args: %d\n", sel); 612 return -EINVAL; 613 } 614 615 debugfs_priv->cb_data = sel; 616 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 617 618 return count; 619 } 620 621 #define RTW89_MAC_PAGE_SIZE 0x100 622 623 static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v) 624 { 625 struct rtw89_debugfs_priv *debugfs_priv = m->private; 626 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 627 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 628 u32 start, end; 629 u32 i, j, k, page; 630 u32 val; 631 632 switch (reg_sel) { 633 case RTW89_DBG_SEL_MAC_00: 634 seq_puts(m, "Debug selected MAC page 0x00\n"); 635 start = 0x000; 636 end = 0x014; 637 break; 638 case RTW89_DBG_SEL_MAC_40: 639 seq_puts(m, "Debug selected MAC page 0x40\n"); 640 start = 0x040; 641 end = 0x07f; 642 break; 643 case RTW89_DBG_SEL_MAC_80: 644 seq_puts(m, "Debug selected MAC page 0x80\n"); 645 start = 0x080; 646 end = 0x09f; 647 break; 648 case RTW89_DBG_SEL_MAC_C0: 649 seq_puts(m, "Debug selected MAC page 0xc0\n"); 650 start = 0x0c0; 651 end = 0x0df; 652 break; 653 case RTW89_DBG_SEL_MAC_E0: 654 seq_puts(m, "Debug selected MAC page 0xe0\n"); 655 start = 0x0e0; 656 end = 0x0ff; 657 break; 658 case RTW89_DBG_SEL_BB: 659 seq_puts(m, "Debug selected BB register\n"); 660 start = 0x100; 661 end = 0x17f; 662 break; 663 case RTW89_DBG_SEL_IQK: 664 seq_puts(m, "Debug selected IQK register\n"); 665 start = 0x180; 666 end = 0x1bf; 667 break; 668 case RTW89_DBG_SEL_RFC: 669 seq_puts(m, "Debug selected RFC register\n"); 670 start = 0x1c0; 671 end = 0x1ff; 672 break; 673 default: 674 seq_puts(m, "Selected invalid register page\n"); 675 return -EINVAL; 676 } 677 678 for (i = start; i <= end; i++) { 679 page = i << 8; 680 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 681 seq_printf(m, "%08xh : ", 0x18600000 + j); 682 for (k = 0; k < 4; k++) { 683 val = rtw89_read32(rtwdev, j + (k << 2)); 684 seq_printf(m, "%08x ", val); 685 } 686 seq_puts(m, "\n"); 687 } 688 } 689 690 return 0; 691 } 692 693 static ssize_t 694 rtw89_debug_priv_mac_mem_dump_select(struct file *filp, 695 const char __user *user_buf, 696 size_t count, loff_t *loff) 697 { 698 struct seq_file *m = (struct seq_file *)filp->private_data; 699 struct rtw89_debugfs_priv *debugfs_priv = m->private; 700 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 701 char buf[32]; 702 size_t buf_size; 703 u32 sel, start_addr, len; 704 int num; 705 706 buf_size = min(count, sizeof(buf) - 1); 707 if (copy_from_user(buf, user_buf, buf_size)) 708 return -EFAULT; 709 710 buf[buf_size] = '\0'; 711 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 712 if (num != 3) { 713 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 714 return -EINVAL; 715 } 716 717 debugfs_priv->mac_mem.sel = sel; 718 debugfs_priv->mac_mem.start = start_addr; 719 debugfs_priv->mac_mem.len = len; 720 721 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 722 sel, start_addr, len); 723 724 return count; 725 } 726 727 static void rtw89_debug_dump_mac_mem(struct seq_file *m, 728 struct rtw89_dev *rtwdev, 729 u8 sel, u32 start_addr, u32 len) 730 { 731 u32 base_addr, start_page, residue; 732 u32 i, j, p, pages; 733 u32 dump_len, remain; 734 u32 val; 735 736 remain = len; 737 pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1; 738 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE; 739 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE; 740 base_addr = rtw89_mac_mem_base_addrs[sel]; 741 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE; 742 743 for (p = 0; p < pages; p++) { 744 dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE); 745 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, base_addr); 746 for (i = R_AX_INDIR_ACCESS_ENTRY + residue; 747 i < R_AX_INDIR_ACCESS_ENTRY + dump_len;) { 748 seq_printf(m, "%08xh:", i); 749 for (j = 0; 750 j < 4 && i < R_AX_INDIR_ACCESS_ENTRY + dump_len; 751 j++, i += 4) { 752 val = rtw89_read32(rtwdev, i); 753 seq_printf(m, " %08x", val); 754 remain -= 4; 755 } 756 seq_puts(m, "\n"); 757 } 758 base_addr += MAC_MEM_DUMP_PAGE_SIZE; 759 } 760 } 761 762 static int 763 rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v) 764 { 765 struct rtw89_debugfs_priv *debugfs_priv = m->private; 766 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 767 768 mutex_lock(&rtwdev->mutex); 769 rtw89_leave_ps_mode(rtwdev); 770 rtw89_debug_dump_mac_mem(m, rtwdev, 771 debugfs_priv->mac_mem.sel, 772 debugfs_priv->mac_mem.start, 773 debugfs_priv->mac_mem.len); 774 mutex_unlock(&rtwdev->mutex); 775 776 return 0; 777 } 778 779 static ssize_t 780 rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp, 781 const char __user *user_buf, 782 size_t count, loff_t *loff) 783 { 784 struct seq_file *m = (struct seq_file *)filp->private_data; 785 struct rtw89_debugfs_priv *debugfs_priv = m->private; 786 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 787 char buf[32]; 788 size_t buf_size; 789 int sel, set; 790 int num; 791 bool enable; 792 793 buf_size = min(count, sizeof(buf) - 1); 794 if (copy_from_user(buf, user_buf, buf_size)) 795 return -EFAULT; 796 797 buf[buf_size] = '\0'; 798 num = sscanf(buf, "%d %d", &sel, &set); 799 if (num != 2) { 800 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 801 return -EINVAL; 802 } 803 804 enable = set != 0; 805 switch (sel) { 806 case 0: 807 debugfs_priv->dbgpkg_en.ss_dbg = enable; 808 break; 809 case 1: 810 debugfs_priv->dbgpkg_en.dle_dbg = enable; 811 break; 812 case 2: 813 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 814 break; 815 case 3: 816 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 817 break; 818 case 4: 819 debugfs_priv->dbgpkg_en.dbg_port = enable; 820 break; 821 default: 822 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 823 return -EINVAL; 824 } 825 826 rtw89_info(rtwdev, "%s debug port dump %d\n", 827 enable ? "Enable" : "Disable", sel); 828 829 return count; 830 } 831 832 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 833 struct seq_file *m) 834 { 835 return 0; 836 } 837 838 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 839 struct seq_file *m) 840 { 841 #define DLE_DFI_DUMP(__type, __target, __sel) \ 842 ({ \ 843 u32 __ctrl; \ 844 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 845 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 846 u32 __data, __val32; \ 847 int __ret; \ 848 \ 849 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 850 DLE_DFI_TYPE_##__target) | \ 851 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 852 B_AX_WDE_DFI_ACTIVE; \ 853 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 854 __ret = read_poll_timeout(rtw89_read32, __val32, \ 855 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 856 1000, 50000, false, \ 857 rtwdev, __reg_ctrl); \ 858 if (__ret) { \ 859 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 860 #__type, #__target, __sel); \ 861 return __ret; \ 862 } \ 863 \ 864 __data = rtw89_read32(rtwdev, __reg_data); \ 865 __data; \ 866 }) 867 868 #define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \ 869 ({ \ 870 u32 __freepg, __pubpg; \ 871 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 872 \ 873 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 874 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 875 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 876 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 877 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 878 seq_printf(__m, "[%s] freepg head: %d\n", \ 879 #__type, __freepg_head); \ 880 seq_printf(__m, "[%s] freepg tail: %d\n", \ 881 #__type, __freepg_tail); \ 882 seq_printf(__m, "[%s] pubpg num : %d\n", \ 883 #__type, __pubpg_num); \ 884 }) 885 886 #define case_QUOTA(__m, __type, __id) \ 887 case __type##_QTAID_##__id: \ 888 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 889 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 890 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 891 seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \ 892 #__type, #__id, rsv_pgnum); \ 893 seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \ 894 #__type, #__id, use_pgnum); \ 895 break 896 u32 quota_id; 897 u32 val32; 898 u16 rsv_pgnum, use_pgnum; 899 int ret; 900 901 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 902 if (ret) { 903 seq_puts(m, "[DLE] : DMAC not enabled\n"); 904 return ret; 905 } 906 907 DLE_DFI_FREE_PAGE_DUMP(m, WDE); 908 DLE_DFI_FREE_PAGE_DUMP(m, PLE); 909 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 910 switch (quota_id) { 911 case_QUOTA(m, WDE, HOST_IF); 912 case_QUOTA(m, WDE, WLAN_CPU); 913 case_QUOTA(m, WDE, DATA_CPU); 914 case_QUOTA(m, WDE, PKTIN); 915 case_QUOTA(m, WDE, CPUIO); 916 } 917 } 918 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 919 switch (quota_id) { 920 case_QUOTA(m, PLE, B0_TXPL); 921 case_QUOTA(m, PLE, B1_TXPL); 922 case_QUOTA(m, PLE, C2H); 923 case_QUOTA(m, PLE, H2C); 924 case_QUOTA(m, PLE, WLAN_CPU); 925 case_QUOTA(m, PLE, MPDU); 926 case_QUOTA(m, PLE, CMAC0_RX); 927 case_QUOTA(m, PLE, CMAC1_RX); 928 case_QUOTA(m, PLE, CMAC1_BBRPT); 929 case_QUOTA(m, PLE, WDRLS); 930 case_QUOTA(m, PLE, CPUIO); 931 } 932 } 933 934 return 0; 935 936 #undef case_QUOTA 937 #undef DLE_DFI_DUMP 938 #undef DLE_DFI_FREE_PAGE_DUMP 939 } 940 941 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 942 struct seq_file *m) 943 { 944 int ret; 945 946 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 947 if (ret) { 948 seq_puts(m, "[DMAC] : DMAC not enabled\n"); 949 return ret; 950 } 951 952 seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n", 953 rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR)); 954 seq_printf(m, "[0]R_AX_WDRLS_ERR_ISR=0x%08x\n", 955 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 956 seq_printf(m, "[1]R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 957 rtw89_read32(rtwdev, R_AX_SEC_ERR_IMR_ISR)); 958 seq_printf(m, "[2.1]R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 959 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 960 seq_printf(m, "[2.2]R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 961 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 962 seq_printf(m, "[3]R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 963 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 964 seq_printf(m, "[4]R_AX_WDE_ERR_ISR=0x%08x\n", 965 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 966 seq_printf(m, "[5.1]R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 967 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 968 seq_printf(m, "[5.2]R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 969 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 970 seq_printf(m, "[6]R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 971 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 972 seq_printf(m, "[7]R_AX_PKTIN_ERR_ISR=0x%08x\n", 973 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 974 seq_printf(m, "[8.1]R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 975 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 976 seq_printf(m, "[8.2]R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 977 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 978 seq_printf(m, "[8.3]R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 979 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 980 seq_printf(m, "[10]R_AX_CPUIO_ERR_ISR=0x%08x\n", 981 rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR)); 982 seq_printf(m, "[11.1]R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 983 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 984 seq_printf(m, "[11.2]R_AX_BBRPT_CHINFO_ERR_IMR_ISR=0x%08x\n", 985 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR_ISR)); 986 seq_printf(m, "[11.3]R_AX_BBRPT_DFS_ERR_IMR_ISR=0x%08x\n", 987 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR_ISR)); 988 seq_printf(m, "[11.4]R_AX_LA_ERRFLAG=0x%08x\n", 989 rtw89_read32(rtwdev, R_AX_LA_ERRFLAG)); 990 991 return 0; 992 } 993 994 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 995 struct seq_file *m) 996 { 997 int ret; 998 999 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL); 1000 if (ret) { 1001 seq_puts(m, "[CMAC] : CMAC 0 not enabled\n"); 1002 return ret; 1003 } 1004 1005 seq_printf(m, "R_AX_CMAC_ERR_ISR=0x%08x\n", 1006 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR)); 1007 seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR=0x%08x\n", 1008 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR)); 1009 seq_printf(m, "[1]R_AX_PTCL_ISR0=0x%08x\n", 1010 rtw89_read32(rtwdev, R_AX_PTCL_ISR0)); 1011 seq_printf(m, "[3]R_AX_DLE_CTRL=0x%08x\n", 1012 rtw89_read32(rtwdev, R_AX_DLE_CTRL)); 1013 seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR=0x%08x\n", 1014 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR)); 1015 seq_printf(m, "[5]R_AX_TXPWR_ISR=0x%08x\n", 1016 rtw89_read32(rtwdev, R_AX_TXPWR_ISR)); 1017 seq_printf(m, "[6]R_AX_RMAC_ERR_ISR=0x%08x\n", 1018 rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR)); 1019 seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR=0x%08x\n", 1020 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR)); 1021 1022 ret = rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL); 1023 if (ret) { 1024 seq_puts(m, "[CMAC] : CMAC 1 not enabled\n"); 1025 return ret; 1026 } 1027 1028 seq_printf(m, "R_AX_CMAC_ERR_ISR_C1=0x%08x\n", 1029 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR_C1)); 1030 seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR_C1=0x%08x\n", 1031 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR_C1)); 1032 seq_printf(m, "[1]R_AX_PTCL_ISR0_C1=0x%08x\n", 1033 rtw89_read32(rtwdev, R_AX_PTCL_ISR0_C1)); 1034 seq_printf(m, "[3]R_AX_DLE_CTRL_C1=0x%08x\n", 1035 rtw89_read32(rtwdev, R_AX_DLE_CTRL_C1)); 1036 seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR_C1=0x%02x\n", 1037 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR_C1)); 1038 seq_printf(m, "[5]R_AX_TXPWR_ISR_C1=0x%08x\n", 1039 rtw89_read32(rtwdev, R_AX_TXPWR_ISR_C1)); 1040 seq_printf(m, "[6]R_AX_RMAC_ERR_ISR_C1=0x%08x\n", 1041 rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR_C1)); 1042 seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR_C1=0x%08x\n", 1043 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR_C1)); 1044 1045 return 0; 1046 } 1047 1048 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1049 .sel_addr = R_AX_PTCL_DBG, 1050 .sel_byte = 1, 1051 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1052 .srt = 0x00, 1053 .end = 0x3F, 1054 .rd_addr = R_AX_PTCL_DBG_INFO, 1055 .rd_byte = 4, 1056 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1057 }; 1058 1059 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1060 .sel_addr = R_AX_PTCL_DBG_C1, 1061 .sel_byte = 1, 1062 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1063 .srt = 0x00, 1064 .end = 0x3F, 1065 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1066 .rd_byte = 4, 1067 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1068 }; 1069 1070 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 1071 .sel_addr = R_AX_SCH_DBG_SEL, 1072 .sel_byte = 1, 1073 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1074 .srt = 0x00, 1075 .end = 0x2F, 1076 .rd_addr = R_AX_SCH_DBG, 1077 .rd_byte = 4, 1078 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1079 }; 1080 1081 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 1082 .sel_addr = R_AX_SCH_DBG_SEL_C1, 1083 .sel_byte = 1, 1084 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1085 .srt = 0x00, 1086 .end = 0x2F, 1087 .rd_addr = R_AX_SCH_DBG_C1, 1088 .rd_byte = 4, 1089 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1090 }; 1091 1092 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 1093 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 1094 .sel_byte = 1, 1095 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1096 .srt = 0x00, 1097 .end = 0x19, 1098 .rd_addr = R_AX_DBG_PORT_SEL, 1099 .rd_byte = 4, 1100 .rd_msk = B_AX_DEBUG_ST_MASK 1101 }; 1102 1103 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 1104 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 1105 .sel_byte = 1, 1106 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1107 .srt = 0x00, 1108 .end = 0x19, 1109 .rd_addr = R_AX_DBG_PORT_SEL, 1110 .rd_byte = 4, 1111 .rd_msk = B_AX_DEBUG_ST_MASK 1112 }; 1113 1114 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 1115 .sel_addr = R_AX_RX_DEBUG_SELECT, 1116 .sel_byte = 1, 1117 .sel_msk = B_AX_DEBUG_SEL_MASK, 1118 .srt = 0x00, 1119 .end = 0x58, 1120 .rd_addr = R_AX_DBG_PORT_SEL, 1121 .rd_byte = 4, 1122 .rd_msk = B_AX_DEBUG_ST_MASK 1123 }; 1124 1125 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 1126 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 1127 .sel_byte = 1, 1128 .sel_msk = B_AX_DEBUG_SEL_MASK, 1129 .srt = 0x00, 1130 .end = 0x58, 1131 .rd_addr = R_AX_DBG_PORT_SEL, 1132 .rd_byte = 4, 1133 .rd_msk = B_AX_DEBUG_ST_MASK 1134 }; 1135 1136 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 1137 .sel_addr = R_AX_RX_STATE_MONITOR, 1138 .sel_byte = 1, 1139 .sel_msk = B_AX_STATE_SEL_MASK, 1140 .srt = 0x00, 1141 .end = 0x17, 1142 .rd_addr = R_AX_RX_STATE_MONITOR, 1143 .rd_byte = 4, 1144 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 1145 }; 1146 1147 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 1148 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 1149 .sel_byte = 1, 1150 .sel_msk = B_AX_STATE_SEL_MASK, 1151 .srt = 0x00, 1152 .end = 0x17, 1153 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 1154 .rd_byte = 4, 1155 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 1156 }; 1157 1158 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 1159 .sel_addr = R_AX_RMAC_PLCP_MON, 1160 .sel_byte = 4, 1161 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 1162 .srt = 0x0, 1163 .end = 0xF, 1164 .rd_addr = R_AX_RMAC_PLCP_MON, 1165 .rd_byte = 4, 1166 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 1167 }; 1168 1169 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 1170 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 1171 .sel_byte = 4, 1172 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 1173 .srt = 0x0, 1174 .end = 0xF, 1175 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 1176 .rd_byte = 4, 1177 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 1178 }; 1179 1180 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 1181 .sel_addr = R_AX_DBGSEL_TRXPTCL, 1182 .sel_byte = 1, 1183 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 1184 .srt = 0x08, 1185 .end = 0x10, 1186 .rd_addr = R_AX_DBG_PORT_SEL, 1187 .rd_byte = 4, 1188 .rd_msk = B_AX_DEBUG_ST_MASK 1189 }; 1190 1191 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 1192 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 1193 .sel_byte = 1, 1194 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 1195 .srt = 0x08, 1196 .end = 0x10, 1197 .rd_addr = R_AX_DBG_PORT_SEL, 1198 .rd_byte = 4, 1199 .rd_msk = B_AX_DEBUG_ST_MASK 1200 }; 1201 1202 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 1203 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 1204 .sel_byte = 1, 1205 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1206 .srt = 0x00, 1207 .end = 0x07, 1208 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 1209 .rd_byte = 4, 1210 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 1211 }; 1212 1213 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 1214 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 1215 .sel_byte = 1, 1216 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1217 .srt = 0x00, 1218 .end = 0x07, 1219 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 1220 .rd_byte = 4, 1221 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 1222 }; 1223 1224 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 1225 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 1226 .sel_byte = 1, 1227 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1228 .srt = 0x00, 1229 .end = 0x07, 1230 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 1231 .rd_byte = 4, 1232 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 1233 }; 1234 1235 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 1236 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 1237 .sel_byte = 1, 1238 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1239 .srt = 0x00, 1240 .end = 0x07, 1241 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 1242 .rd_byte = 4, 1243 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 1244 }; 1245 1246 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 1247 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 1248 .sel_byte = 1, 1249 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1250 .srt = 0x00, 1251 .end = 0x04, 1252 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 1253 .rd_byte = 4, 1254 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 1255 }; 1256 1257 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 1258 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 1259 .sel_byte = 1, 1260 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1261 .srt = 0x00, 1262 .end = 0x04, 1263 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 1264 .rd_byte = 4, 1265 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 1266 }; 1267 1268 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 1269 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 1270 .sel_byte = 1, 1271 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1272 .srt = 0x00, 1273 .end = 0x04, 1274 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 1275 .rd_byte = 4, 1276 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 1277 }; 1278 1279 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 1280 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 1281 .sel_byte = 1, 1282 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1283 .srt = 0x00, 1284 .end = 0x04, 1285 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 1286 .rd_byte = 4, 1287 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 1288 }; 1289 1290 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 1291 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1292 .sel_byte = 4, 1293 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1294 .srt = 0x80000000, 1295 .end = 0x80000001, 1296 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1297 .rd_byte = 4, 1298 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1299 }; 1300 1301 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 1302 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1303 .sel_byte = 4, 1304 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1305 .srt = 0x80010000, 1306 .end = 0x80010004, 1307 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1308 .rd_byte = 4, 1309 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1310 }; 1311 1312 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 1313 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1314 .sel_byte = 4, 1315 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1316 .srt = 0x80020000, 1317 .end = 0x80020FFF, 1318 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1319 .rd_byte = 4, 1320 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1321 }; 1322 1323 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 1324 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1325 .sel_byte = 4, 1326 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1327 .srt = 0x80030000, 1328 .end = 0x80030FFF, 1329 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1330 .rd_byte = 4, 1331 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1332 }; 1333 1334 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 1335 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1336 .sel_byte = 4, 1337 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1338 .srt = 0x80040000, 1339 .end = 0x80040FFF, 1340 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1341 .rd_byte = 4, 1342 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1343 }; 1344 1345 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 1346 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1347 .sel_byte = 4, 1348 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1349 .srt = 0x80050000, 1350 .end = 0x80050FFF, 1351 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1352 .rd_byte = 4, 1353 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1354 }; 1355 1356 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 1357 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1358 .sel_byte = 4, 1359 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1360 .srt = 0x80060000, 1361 .end = 0x80060453, 1362 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1363 .rd_byte = 4, 1364 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1365 }; 1366 1367 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 1368 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1369 .sel_byte = 4, 1370 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1371 .srt = 0x80070000, 1372 .end = 0x80070011, 1373 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1374 .rd_byte = 4, 1375 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1376 }; 1377 1378 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 1379 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1380 .sel_byte = 4, 1381 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1382 .srt = 0x80000000, 1383 .end = 0x80000001, 1384 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1385 .rd_byte = 4, 1386 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1387 }; 1388 1389 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 1390 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1391 .sel_byte = 4, 1392 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1393 .srt = 0x80010000, 1394 .end = 0x8001000A, 1395 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1396 .rd_byte = 4, 1397 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1398 }; 1399 1400 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 1401 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1402 .sel_byte = 4, 1403 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1404 .srt = 0x80020000, 1405 .end = 0x80020DBF, 1406 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1407 .rd_byte = 4, 1408 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1409 }; 1410 1411 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 1412 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1413 .sel_byte = 4, 1414 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1415 .srt = 0x80030000, 1416 .end = 0x80030DBF, 1417 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1418 .rd_byte = 4, 1419 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1420 }; 1421 1422 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 1423 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1424 .sel_byte = 4, 1425 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1426 .srt = 0x80040000, 1427 .end = 0x80040DBF, 1428 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1429 .rd_byte = 4, 1430 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1431 }; 1432 1433 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 1434 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1435 .sel_byte = 4, 1436 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1437 .srt = 0x80050000, 1438 .end = 0x80050DBF, 1439 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1440 .rd_byte = 4, 1441 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1442 }; 1443 1444 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 1445 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1446 .sel_byte = 4, 1447 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1448 .srt = 0x80060000, 1449 .end = 0x80060041, 1450 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1451 .rd_byte = 4, 1452 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1453 }; 1454 1455 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 1456 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1457 .sel_byte = 4, 1458 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1459 .srt = 0x80070000, 1460 .end = 0x80070001, 1461 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1462 .rd_byte = 4, 1463 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1464 }; 1465 1466 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 1467 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 1468 .sel_byte = 4, 1469 .sel_msk = B_AX_DFI_DATA_MASK, 1470 .srt = 0x80000000, 1471 .end = 0x8000017f, 1472 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 1473 .rd_byte = 4, 1474 .rd_msk = B_AX_DFI_DATA_MASK 1475 }; 1476 1477 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 1478 .sel_addr = R_AX_PCIE_DBG_CTRL, 1479 .sel_byte = 2, 1480 .sel_msk = B_AX_DBG_SEL_MASK, 1481 .srt = 0x00, 1482 .end = 0x03, 1483 .rd_addr = R_AX_DBG_PORT_SEL, 1484 .rd_byte = 4, 1485 .rd_msk = B_AX_DEBUG_ST_MASK 1486 }; 1487 1488 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 1489 .sel_addr = R_AX_PCIE_DBG_CTRL, 1490 .sel_byte = 2, 1491 .sel_msk = B_AX_DBG_SEL_MASK, 1492 .srt = 0x00, 1493 .end = 0x04, 1494 .rd_addr = R_AX_DBG_PORT_SEL, 1495 .rd_byte = 4, 1496 .rd_msk = B_AX_DEBUG_ST_MASK 1497 }; 1498 1499 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 1500 .sel_addr = R_AX_PCIE_DBG_CTRL, 1501 .sel_byte = 2, 1502 .sel_msk = B_AX_DBG_SEL_MASK, 1503 .srt = 0x00, 1504 .end = 0x01, 1505 .rd_addr = R_AX_DBG_PORT_SEL, 1506 .rd_byte = 4, 1507 .rd_msk = B_AX_DEBUG_ST_MASK 1508 }; 1509 1510 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 1511 .sel_addr = R_AX_PCIE_DBG_CTRL, 1512 .sel_byte = 2, 1513 .sel_msk = B_AX_DBG_SEL_MASK, 1514 .srt = 0x00, 1515 .end = 0x05, 1516 .rd_addr = R_AX_DBG_PORT_SEL, 1517 .rd_byte = 4, 1518 .rd_msk = B_AX_DEBUG_ST_MASK 1519 }; 1520 1521 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 1522 .sel_addr = R_AX_PCIE_DBG_CTRL, 1523 .sel_byte = 2, 1524 .sel_msk = B_AX_DBG_SEL_MASK, 1525 .srt = 0x00, 1526 .end = 0x05, 1527 .rd_addr = R_AX_DBG_PORT_SEL, 1528 .rd_byte = 4, 1529 .rd_msk = B_AX_DEBUG_ST_MASK 1530 }; 1531 1532 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 1533 .sel_addr = R_AX_PCIE_DBG_CTRL, 1534 .sel_byte = 2, 1535 .sel_msk = B_AX_DBG_SEL_MASK, 1536 .srt = 0x00, 1537 .end = 0x06, 1538 .rd_addr = R_AX_DBG_PORT_SEL, 1539 .rd_byte = 4, 1540 .rd_msk = B_AX_DEBUG_ST_MASK 1541 }; 1542 1543 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 1544 .sel_addr = R_AX_DBG_CTRL, 1545 .sel_byte = 1, 1546 .sel_msk = B_AX_DBG_SEL0, 1547 .srt = 0x34, 1548 .end = 0x3C, 1549 .rd_addr = R_AX_DBG_PORT_SEL, 1550 .rd_byte = 4, 1551 .rd_msk = B_AX_DEBUG_ST_MASK 1552 }; 1553 1554 static const struct rtw89_mac_dbg_port_info * 1555 rtw89_debug_mac_dbg_port_sel(struct seq_file *m, 1556 struct rtw89_dev *rtwdev, u32 sel) 1557 { 1558 const struct rtw89_mac_dbg_port_info *info; 1559 u32 val32; 1560 u16 val16; 1561 u8 val8; 1562 1563 switch (sel) { 1564 case RTW89_DBG_PORT_SEL_PTCL_C0: 1565 info = &dbg_port_ptcl_c0; 1566 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 1567 val16 |= B_AX_PTCL_DBG_EN; 1568 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 1569 seq_puts(m, "Enable PTCL C0 dbgport.\n"); 1570 break; 1571 case RTW89_DBG_PORT_SEL_PTCL_C1: 1572 info = &dbg_port_ptcl_c1; 1573 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 1574 val16 |= B_AX_PTCL_DBG_EN; 1575 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 1576 seq_puts(m, "Enable PTCL C1 dbgport.\n"); 1577 break; 1578 case RTW89_DBG_PORT_SEL_SCH_C0: 1579 info = &dbg_port_sch_c0; 1580 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 1581 val32 |= B_AX_SCH_DBG_EN; 1582 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 1583 seq_puts(m, "Enable SCH C0 dbgport.\n"); 1584 break; 1585 case RTW89_DBG_PORT_SEL_SCH_C1: 1586 info = &dbg_port_sch_c1; 1587 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 1588 val32 |= B_AX_SCH_DBG_EN; 1589 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 1590 seq_puts(m, "Enable SCH C1 dbgport.\n"); 1591 break; 1592 case RTW89_DBG_PORT_SEL_TMAC_C0: 1593 info = &dbg_port_tmac_c0; 1594 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 1595 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 1596 B_AX_DBGSEL_TRXPTCL_MASK); 1597 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 1598 1599 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1600 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 1601 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 1602 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1603 1604 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1605 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1606 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1607 seq_puts(m, "Enable TMAC C0 dbgport.\n"); 1608 break; 1609 case RTW89_DBG_PORT_SEL_TMAC_C1: 1610 info = &dbg_port_tmac_c1; 1611 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 1612 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 1613 B_AX_DBGSEL_TRXPTCL_MASK); 1614 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 1615 1616 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1617 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 1618 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 1619 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1620 1621 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1622 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1623 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1624 seq_puts(m, "Enable TMAC C1 dbgport.\n"); 1625 break; 1626 case RTW89_DBG_PORT_SEL_RMAC_C0: 1627 info = &dbg_port_rmac_c0; 1628 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 1629 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 1630 B_AX_DBGSEL_TRXPTCL_MASK); 1631 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 1632 1633 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1634 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 1635 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 1636 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1637 1638 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1639 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1640 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1641 1642 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 1643 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 1644 B_AX_DBGSEL_TRXPTCL_MASK); 1645 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 1646 seq_puts(m, "Enable RMAC C0 dbgport.\n"); 1647 break; 1648 case RTW89_DBG_PORT_SEL_RMAC_C1: 1649 info = &dbg_port_rmac_c1; 1650 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 1651 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 1652 B_AX_DBGSEL_TRXPTCL_MASK); 1653 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 1654 1655 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1656 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 1657 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 1658 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1659 1660 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1661 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1662 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1663 1664 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 1665 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 1666 B_AX_DBGSEL_TRXPTCL_MASK); 1667 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 1668 seq_puts(m, "Enable RMAC C1 dbgport.\n"); 1669 break; 1670 case RTW89_DBG_PORT_SEL_RMACST_C0: 1671 info = &dbg_port_rmacst_c0; 1672 seq_puts(m, "Enable RMAC state C0 dbgport.\n"); 1673 break; 1674 case RTW89_DBG_PORT_SEL_RMACST_C1: 1675 info = &dbg_port_rmacst_c1; 1676 seq_puts(m, "Enable RMAC state C1 dbgport.\n"); 1677 break; 1678 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 1679 info = &dbg_port_rmac_plcp_c0; 1680 seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n"); 1681 break; 1682 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 1683 info = &dbg_port_rmac_plcp_c1; 1684 seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n"); 1685 break; 1686 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 1687 info = &dbg_port_trxptcl_c0; 1688 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1689 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 1690 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 1691 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1692 1693 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1694 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1695 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1696 seq_puts(m, "Enable TRXPTCL C0 dbgport.\n"); 1697 break; 1698 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 1699 info = &dbg_port_trxptcl_c1; 1700 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1701 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 1702 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 1703 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1704 1705 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1706 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1707 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1708 seq_puts(m, "Enable TRXPTCL C1 dbgport.\n"); 1709 break; 1710 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 1711 info = &dbg_port_tx_infol_c0; 1712 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1713 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1714 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1715 seq_puts(m, "Enable tx infol dump.\n"); 1716 break; 1717 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 1718 info = &dbg_port_tx_infoh_c0; 1719 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1720 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1721 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1722 seq_puts(m, "Enable tx infoh dump.\n"); 1723 break; 1724 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 1725 info = &dbg_port_tx_infol_c1; 1726 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1727 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1728 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1729 seq_puts(m, "Enable tx infol dump.\n"); 1730 break; 1731 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 1732 info = &dbg_port_tx_infoh_c1; 1733 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1734 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1735 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1736 seq_puts(m, "Enable tx infoh dump.\n"); 1737 break; 1738 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 1739 info = &dbg_port_txtf_infol_c0; 1740 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1741 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1742 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1743 seq_puts(m, "Enable tx tf infol dump.\n"); 1744 break; 1745 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 1746 info = &dbg_port_txtf_infoh_c0; 1747 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1748 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1749 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1750 seq_puts(m, "Enable tx tf infoh dump.\n"); 1751 break; 1752 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 1753 info = &dbg_port_txtf_infol_c1; 1754 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1755 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1756 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1757 seq_puts(m, "Enable tx tf infol dump.\n"); 1758 break; 1759 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 1760 info = &dbg_port_txtf_infoh_c1; 1761 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1762 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1763 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1764 seq_puts(m, "Enable tx tf infoh dump.\n"); 1765 break; 1766 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 1767 info = &dbg_port_wde_bufmgn_freepg; 1768 seq_puts(m, "Enable wde bufmgn freepg dump.\n"); 1769 break; 1770 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 1771 info = &dbg_port_wde_bufmgn_quota; 1772 seq_puts(m, "Enable wde bufmgn quota dump.\n"); 1773 break; 1774 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 1775 info = &dbg_port_wde_bufmgn_pagellt; 1776 seq_puts(m, "Enable wde bufmgn pagellt dump.\n"); 1777 break; 1778 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 1779 info = &dbg_port_wde_bufmgn_pktinfo; 1780 seq_puts(m, "Enable wde bufmgn pktinfo dump.\n"); 1781 break; 1782 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 1783 info = &dbg_port_wde_quemgn_prepkt; 1784 seq_puts(m, "Enable wde quemgn prepkt dump.\n"); 1785 break; 1786 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 1787 info = &dbg_port_wde_quemgn_nxtpkt; 1788 seq_puts(m, "Enable wde quemgn nxtpkt dump.\n"); 1789 break; 1790 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 1791 info = &dbg_port_wde_quemgn_qlnktbl; 1792 seq_puts(m, "Enable wde quemgn qlnktbl dump.\n"); 1793 break; 1794 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 1795 info = &dbg_port_wde_quemgn_qempty; 1796 seq_puts(m, "Enable wde quemgn qempty dump.\n"); 1797 break; 1798 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 1799 info = &dbg_port_ple_bufmgn_freepg; 1800 seq_puts(m, "Enable ple bufmgn freepg dump.\n"); 1801 break; 1802 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 1803 info = &dbg_port_ple_bufmgn_quota; 1804 seq_puts(m, "Enable ple bufmgn quota dump.\n"); 1805 break; 1806 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 1807 info = &dbg_port_ple_bufmgn_pagellt; 1808 seq_puts(m, "Enable ple bufmgn pagellt dump.\n"); 1809 break; 1810 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 1811 info = &dbg_port_ple_bufmgn_pktinfo; 1812 seq_puts(m, "Enable ple bufmgn pktinfo dump.\n"); 1813 break; 1814 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 1815 info = &dbg_port_ple_quemgn_prepkt; 1816 seq_puts(m, "Enable ple quemgn prepkt dump.\n"); 1817 break; 1818 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 1819 info = &dbg_port_ple_quemgn_nxtpkt; 1820 seq_puts(m, "Enable ple quemgn nxtpkt dump.\n"); 1821 break; 1822 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 1823 info = &dbg_port_ple_quemgn_qlnktbl; 1824 seq_puts(m, "Enable ple quemgn qlnktbl dump.\n"); 1825 break; 1826 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 1827 info = &dbg_port_ple_quemgn_qempty; 1828 seq_puts(m, "Enable ple quemgn qempty dump.\n"); 1829 break; 1830 case RTW89_DBG_PORT_SEL_PKTINFO: 1831 info = &dbg_port_pktinfo; 1832 seq_puts(m, "Enable pktinfo dump.\n"); 1833 break; 1834 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 1835 info = &dbg_port_pcie_txdma; 1836 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1837 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 1838 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 1839 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1840 seq_puts(m, "Enable pcie txdma dump.\n"); 1841 break; 1842 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 1843 info = &dbg_port_pcie_rxdma; 1844 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1845 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 1846 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 1847 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1848 seq_puts(m, "Enable pcie rxdma dump.\n"); 1849 break; 1850 case RTW89_DBG_PORT_SEL_PCIE_CVT: 1851 info = &dbg_port_pcie_cvt; 1852 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1853 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 1854 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 1855 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1856 seq_puts(m, "Enable pcie cvt dump.\n"); 1857 break; 1858 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 1859 info = &dbg_port_pcie_cxpl; 1860 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1861 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 1862 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 1863 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1864 seq_puts(m, "Enable pcie cxpl dump.\n"); 1865 break; 1866 case RTW89_DBG_PORT_SEL_PCIE_IO: 1867 info = &dbg_port_pcie_io; 1868 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1869 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 1870 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 1871 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1872 seq_puts(m, "Enable pcie io dump.\n"); 1873 break; 1874 case RTW89_DBG_PORT_SEL_PCIE_MISC: 1875 info = &dbg_port_pcie_misc; 1876 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1877 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 1878 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 1879 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1880 seq_puts(m, "Enable pcie misc dump.\n"); 1881 break; 1882 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 1883 info = &dbg_port_pcie_misc2; 1884 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 1885 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 1886 B_AX_DBG_SEL_MASK); 1887 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 1888 seq_puts(m, "Enable pcie misc2 dump.\n"); 1889 break; 1890 default: 1891 seq_puts(m, "Dbg port select err\n"); 1892 return NULL; 1893 } 1894 1895 return info; 1896 } 1897 1898 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 1899 { 1900 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 1901 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 1902 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 1903 return false; 1904 if (rtwdev->chip->chip_id == RTL8852B && 1905 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 1906 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 1907 return false; 1908 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 1909 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 1910 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 1911 return false; 1912 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 1913 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 1914 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 1915 return false; 1916 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 1917 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 1918 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 1919 return false; 1920 1921 return true; 1922 } 1923 1924 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 1925 struct seq_file *m, u32 sel) 1926 { 1927 const struct rtw89_mac_dbg_port_info *info; 1928 u8 val8; 1929 u16 val16; 1930 u32 val32; 1931 u32 i; 1932 1933 info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel); 1934 if (!info) { 1935 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 1936 return -EINVAL; 1937 } 1938 1939 #define case_DBG_SEL(__sel) \ 1940 case RTW89_DBG_PORT_SEL_##__sel: \ 1941 seq_puts(m, "Dump debug port " #__sel ":\n"); \ 1942 break 1943 1944 switch (sel) { 1945 case_DBG_SEL(PTCL_C0); 1946 case_DBG_SEL(PTCL_C1); 1947 case_DBG_SEL(SCH_C0); 1948 case_DBG_SEL(SCH_C1); 1949 case_DBG_SEL(TMAC_C0); 1950 case_DBG_SEL(TMAC_C1); 1951 case_DBG_SEL(RMAC_C0); 1952 case_DBG_SEL(RMAC_C1); 1953 case_DBG_SEL(RMACST_C0); 1954 case_DBG_SEL(RMACST_C1); 1955 case_DBG_SEL(TRXPTCL_C0); 1956 case_DBG_SEL(TRXPTCL_C1); 1957 case_DBG_SEL(TX_INFOL_C0); 1958 case_DBG_SEL(TX_INFOH_C0); 1959 case_DBG_SEL(TX_INFOL_C1); 1960 case_DBG_SEL(TX_INFOH_C1); 1961 case_DBG_SEL(TXTF_INFOL_C0); 1962 case_DBG_SEL(TXTF_INFOH_C0); 1963 case_DBG_SEL(TXTF_INFOL_C1); 1964 case_DBG_SEL(TXTF_INFOH_C1); 1965 case_DBG_SEL(WDE_BUFMGN_FREEPG); 1966 case_DBG_SEL(WDE_BUFMGN_QUOTA); 1967 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 1968 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 1969 case_DBG_SEL(WDE_QUEMGN_PREPKT); 1970 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 1971 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 1972 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 1973 case_DBG_SEL(PLE_BUFMGN_FREEPG); 1974 case_DBG_SEL(PLE_BUFMGN_QUOTA); 1975 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 1976 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 1977 case_DBG_SEL(PLE_QUEMGN_PREPKT); 1978 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 1979 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 1980 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 1981 case_DBG_SEL(PKTINFO); 1982 case_DBG_SEL(PCIE_TXDMA); 1983 case_DBG_SEL(PCIE_RXDMA); 1984 case_DBG_SEL(PCIE_CVT); 1985 case_DBG_SEL(PCIE_CXPL); 1986 case_DBG_SEL(PCIE_IO); 1987 case_DBG_SEL(PCIE_MISC); 1988 case_DBG_SEL(PCIE_MISC2); 1989 } 1990 1991 #undef case_DBG_SEL 1992 1993 seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr); 1994 seq_printf(m, "Read addr = 0x%X\n", info->rd_addr); 1995 1996 for (i = info->srt; i <= info->end; i++) { 1997 switch (info->sel_byte) { 1998 case 1: 1999 default: 2000 rtw89_write8_mask(rtwdev, info->sel_addr, 2001 info->sel_msk, i); 2002 seq_printf(m, "0x%02X: ", i); 2003 break; 2004 case 2: 2005 rtw89_write16_mask(rtwdev, info->sel_addr, 2006 info->sel_msk, i); 2007 seq_printf(m, "0x%04X: ", i); 2008 break; 2009 case 4: 2010 rtw89_write32_mask(rtwdev, info->sel_addr, 2011 info->sel_msk, i); 2012 seq_printf(m, "0x%04X: ", i); 2013 break; 2014 } 2015 2016 udelay(10); 2017 2018 switch (info->rd_byte) { 2019 case 1: 2020 default: 2021 val8 = rtw89_read8_mask(rtwdev, 2022 info->rd_addr, info->rd_msk); 2023 seq_printf(m, "0x%02X\n", val8); 2024 break; 2025 case 2: 2026 val16 = rtw89_read16_mask(rtwdev, 2027 info->rd_addr, info->rd_msk); 2028 seq_printf(m, "0x%04X\n", val16); 2029 break; 2030 case 4: 2031 val32 = rtw89_read32_mask(rtwdev, 2032 info->rd_addr, info->rd_msk); 2033 seq_printf(m, "0x%08X\n", val32); 2034 break; 2035 } 2036 } 2037 2038 return 0; 2039 } 2040 2041 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 2042 struct seq_file *m) 2043 { 2044 u32 sel; 2045 int ret = 0; 2046 2047 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 2048 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 2049 if (!is_dbg_port_valid(rtwdev, sel)) 2050 continue; 2051 ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel); 2052 if (ret) { 2053 rtw89_err(rtwdev, 2054 "failed to dump debug port %d\n", sel); 2055 break; 2056 } 2057 } 2058 2059 return ret; 2060 } 2061 2062 static int 2063 rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v) 2064 { 2065 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2066 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2067 2068 if (debugfs_priv->dbgpkg_en.ss_dbg) 2069 rtw89_debug_mac_dump_ss_dbg(rtwdev, m); 2070 if (debugfs_priv->dbgpkg_en.dle_dbg) 2071 rtw89_debug_mac_dump_dle_dbg(rtwdev, m); 2072 if (debugfs_priv->dbgpkg_en.dmac_dbg) 2073 rtw89_debug_mac_dump_dmac_dbg(rtwdev, m); 2074 if (debugfs_priv->dbgpkg_en.cmac_dbg) 2075 rtw89_debug_mac_dump_cmac_dbg(rtwdev, m); 2076 if (debugfs_priv->dbgpkg_en.dbg_port) 2077 rtw89_debug_mac_dump_dbg_port(rtwdev, m); 2078 2079 return 0; 2080 }; 2081 2082 static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev, 2083 const char __user *user_buf, size_t count) 2084 { 2085 char *buf; 2086 u8 *bin; 2087 int num; 2088 int err = 0; 2089 2090 buf = memdup_user(user_buf, count); 2091 if (IS_ERR(buf)) 2092 return buf; 2093 2094 num = count / 2; 2095 bin = kmalloc(num, GFP_KERNEL); 2096 if (!bin) { 2097 err = -EFAULT; 2098 goto out; 2099 } 2100 2101 if (hex2bin(bin, buf, num)) { 2102 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 2103 kfree(bin); 2104 err = -EINVAL; 2105 } 2106 2107 out: 2108 kfree(buf); 2109 2110 return err ? ERR_PTR(err) : bin; 2111 } 2112 2113 static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp, 2114 const char __user *user_buf, 2115 size_t count, loff_t *loff) 2116 { 2117 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 2118 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2119 u8 *h2c; 2120 u16 h2c_len = count / 2; 2121 2122 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 2123 if (IS_ERR(h2c)) 2124 return -EFAULT; 2125 2126 rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 2127 2128 kfree(h2c); 2129 2130 return count; 2131 } 2132 2133 static int 2134 rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v) 2135 { 2136 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2137 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2138 struct rtw89_early_h2c *early_h2c; 2139 int seq = 0; 2140 2141 mutex_lock(&rtwdev->mutex); 2142 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 2143 seq_printf(m, "%d: %*ph\n", ++seq, early_h2c->h2c_len, early_h2c->h2c); 2144 mutex_unlock(&rtwdev->mutex); 2145 2146 return 0; 2147 } 2148 2149 static ssize_t 2150 rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf, 2151 size_t count, loff_t *loff) 2152 { 2153 struct seq_file *m = (struct seq_file *)filp->private_data; 2154 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2155 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2156 struct rtw89_early_h2c *early_h2c; 2157 u8 *h2c; 2158 u16 h2c_len = count / 2; 2159 2160 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 2161 if (IS_ERR(h2c)) 2162 return -EFAULT; 2163 2164 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 2165 kfree(h2c); 2166 rtw89_fw_free_all_early_h2c(rtwdev); 2167 goto out; 2168 } 2169 2170 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL); 2171 if (!early_h2c) { 2172 kfree(h2c); 2173 return -EFAULT; 2174 } 2175 2176 early_h2c->h2c = h2c; 2177 early_h2c->h2c_len = h2c_len; 2178 2179 mutex_lock(&rtwdev->mutex); 2180 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 2181 mutex_unlock(&rtwdev->mutex); 2182 2183 out: 2184 return count; 2185 } 2186 2187 static int 2188 rtw89_debug_priv_fw_crash_get(struct seq_file *m, void *v) 2189 { 2190 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2191 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2192 2193 seq_printf(m, "%d\n", 2194 test_bit(RTW89_FLAG_RESTART_TRIGGER, rtwdev->flags)); 2195 return 0; 2196 } 2197 2198 static ssize_t 2199 rtw89_debug_priv_fw_crash_set(struct file *filp, const char __user *user_buf, 2200 size_t count, loff_t *loff) 2201 { 2202 struct seq_file *m = (struct seq_file *)filp->private_data; 2203 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2204 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2205 bool fw_crash; 2206 int ret; 2207 2208 if (!RTW89_CHK_FW_FEATURE(CRASH_TRIGGER, &rtwdev->fw)) 2209 return -EOPNOTSUPP; 2210 2211 ret = kstrtobool_from_user(user_buf, count, &fw_crash); 2212 if (ret) 2213 return -EINVAL; 2214 2215 if (!fw_crash) 2216 return -EINVAL; 2217 2218 mutex_lock(&rtwdev->mutex); 2219 set_bit(RTW89_FLAG_RESTART_TRIGGER, rtwdev->flags); 2220 ret = rtw89_fw_h2c_trigger_cpu_exception(rtwdev); 2221 mutex_unlock(&rtwdev->mutex); 2222 2223 if (ret) 2224 return ret; 2225 2226 return count; 2227 } 2228 2229 static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v) 2230 { 2231 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2232 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2233 2234 rtw89_btc_dump_info(rtwdev, m); 2235 2236 return 0; 2237 } 2238 2239 static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp, 2240 const char __user *user_buf, 2241 size_t count, loff_t *loff) 2242 { 2243 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 2244 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2245 struct rtw89_btc *btc = &rtwdev->btc; 2246 bool btc_manual; 2247 2248 if (kstrtobool_from_user(user_buf, count, &btc_manual)) 2249 goto out; 2250 2251 btc->ctrl.manual = btc_manual; 2252 out: 2253 return count; 2254 } 2255 2256 static ssize_t rtw89_debug_fw_log_btc_manual_set(struct file *filp, 2257 const char __user *user_buf, 2258 size_t count, loff_t *loff) 2259 { 2260 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 2261 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2262 struct rtw89_fw_info *fw_info = &rtwdev->fw; 2263 bool fw_log_manual; 2264 2265 if (kstrtobool_from_user(user_buf, count, &fw_log_manual)) 2266 goto out; 2267 2268 mutex_lock(&rtwdev->mutex); 2269 fw_info->fw_log_enable = fw_log_manual; 2270 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 2271 mutex_unlock(&rtwdev->mutex); 2272 out: 2273 return count; 2274 } 2275 2276 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 2277 { 2278 static const char * const he_gi_str[] = { 2279 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 2280 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 2281 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 2282 }; 2283 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2284 struct rate_info *rate = &rtwsta->ra_report.txrate; 2285 struct ieee80211_rx_status *status = &rtwsta->rx_status; 2286 struct seq_file *m = (struct seq_file *)data; 2287 u8 rssi; 2288 2289 seq_printf(m, "TX rate [%d]: ", rtwsta->mac_id); 2290 2291 if (rate->flags & RATE_INFO_FLAGS_MCS) 2292 seq_printf(m, "HT MCS-%d%s", rate->mcs, 2293 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 2294 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 2295 seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs, 2296 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 2297 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 2298 seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs, 2299 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 2300 he_gi_str[rate->he_gi] : "N/A"); 2301 else 2302 seq_printf(m, "Legacy %d", rate->legacy); 2303 seq_printf(m, "\t(hw_rate=0x%x)", rtwsta->ra_report.hw_rate); 2304 seq_printf(m, "\t==> agg_wait=%d (%d)\n", rtwsta->max_agg_wait, 2305 sta->max_rc_amsdu_len); 2306 2307 seq_printf(m, "RX rate [%d]: ", rtwsta->mac_id); 2308 2309 switch (status->encoding) { 2310 case RX_ENC_LEGACY: 2311 seq_printf(m, "Legacy %d", status->rate_idx + 2312 (status->band != NL80211_BAND_2GHZ ? 4 : 0)); 2313 break; 2314 case RX_ENC_HT: 2315 seq_printf(m, "HT MCS-%d%s", status->rate_idx, 2316 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 2317 break; 2318 case RX_ENC_VHT: 2319 seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx, 2320 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 2321 break; 2322 case RX_ENC_HE: 2323 seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx, 2324 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 2325 he_gi_str[rate->he_gi] : "N/A"); 2326 break; 2327 } 2328 seq_printf(m, "\t(hw_rate=0x%x)\n", rtwsta->rx_hw_rate); 2329 2330 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 2331 seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d)\n", 2332 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta->prev_rssi); 2333 } 2334 2335 static void 2336 rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat, 2337 enum rtw89_hw_rate first_rate, int len) 2338 { 2339 int i; 2340 2341 for (i = 0; i < len; i++) 2342 seq_printf(m, "%s%u", i == 0 ? "" : ", ", 2343 pkt_stat->rx_rate_cnt[first_rate + i]); 2344 } 2345 2346 static const struct rtw89_rx_rate_cnt_info { 2347 enum rtw89_hw_rate first_rate; 2348 int len; 2349 int ext; 2350 const char *rate_mode; 2351 } rtw89_rx_rate_cnt_infos[] = { 2352 {RTW89_HW_RATE_CCK1, 4, 0, "Legacy:"}, 2353 {RTW89_HW_RATE_OFDM6, 8, 0, "OFDM:"}, 2354 {RTW89_HW_RATE_MCS0, 8, 0, "HT 0:"}, 2355 {RTW89_HW_RATE_MCS8, 8, 0, "HT 1:"}, 2356 {RTW89_HW_RATE_VHT_NSS1_MCS0, 10, 2, "VHT 1SS:"}, 2357 {RTW89_HW_RATE_VHT_NSS2_MCS0, 10, 2, "VHT 2SS:"}, 2358 {RTW89_HW_RATE_HE_NSS1_MCS0, 12, 0, "HE 1SS:"}, 2359 {RTW89_HW_RATE_HE_NSS2_MCS0, 12, 0, "HE 2ss:"}, 2360 }; 2361 2362 static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v) 2363 { 2364 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2365 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2366 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2367 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 2368 const struct rtw89_rx_rate_cnt_info *info; 2369 int i; 2370 2371 seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d), RX: %u [%u] Mbps (lv: %d)\n", 2372 stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv, 2373 stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv); 2374 seq_printf(m, "Beacon: %u\n", pkt_stat->beacon_nr); 2375 seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len, 2376 stats->rx_avg_len); 2377 2378 seq_puts(m, "RX count:\n"); 2379 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 2380 info = &rtw89_rx_rate_cnt_infos[i]; 2381 seq_printf(m, "%10s [", info->rate_mode); 2382 rtw89_debug_append_rx_rate(m, pkt_stat, 2383 info->first_rate, info->len); 2384 if (info->ext) { 2385 seq_puts(m, "]["); 2386 rtw89_debug_append_rx_rate(m, pkt_stat, 2387 info->first_rate + info->len, info->ext); 2388 } 2389 seq_puts(m, "]\n"); 2390 } 2391 2392 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m); 2393 2394 return 0; 2395 } 2396 2397 static void rtw89_dump_addr_cam(struct seq_file *m, 2398 struct rtw89_addr_cam_entry *addr_cam) 2399 { 2400 struct rtw89_sec_cam_entry *sec_entry; 2401 int i; 2402 2403 seq_printf(m, "\taddr_cam_idx=%u\n", addr_cam->addr_cam_idx); 2404 seq_printf(m, "\t-> bssid_cam_idx=%u\n", addr_cam->bssid_cam_idx); 2405 seq_printf(m, "\tsec_cam_bitmap=%*ph\n", (int)sizeof(addr_cam->sec_cam_map), 2406 addr_cam->sec_cam_map); 2407 for (i = 0; i < RTW89_SEC_CAM_IN_ADDR_CAM; i++) { 2408 sec_entry = addr_cam->sec_entries[i]; 2409 if (!sec_entry) 2410 continue; 2411 seq_printf(m, "\tsec[%d]: sec_cam_idx %u", i, sec_entry->sec_cam_idx); 2412 if (sec_entry->ext_key) 2413 seq_printf(m, ", %u", sec_entry->sec_cam_idx + 1); 2414 seq_puts(m, "\n"); 2415 } 2416 } 2417 2418 static 2419 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 2420 { 2421 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2422 struct seq_file *m = (struct seq_file *)data; 2423 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam; 2424 2425 seq_printf(m, "VIF [%d] %pM\n", rtwvif->mac_id, rtwvif->mac_addr); 2426 seq_printf(m, "\tbssid_cam_idx=%u\n", bssid_cam->bssid_cam_idx); 2427 rtw89_dump_addr_cam(m, &rtwvif->addr_cam); 2428 } 2429 2430 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta) 2431 { 2432 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2433 struct seq_file *m = (struct seq_file *)data; 2434 2435 seq_printf(m, "STA [%d] %pM\n", rtwsta->mac_id, sta->addr); 2436 rtw89_dump_addr_cam(m, &rtwsta->addr_cam); 2437 } 2438 2439 static int rtw89_debug_priv_stations_get(struct seq_file *m, void *v) 2440 { 2441 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2442 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2443 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 2444 2445 seq_puts(m, "map:\n"); 2446 seq_printf(m, "\tmac_id: %*ph\n", (int)sizeof(rtwdev->mac_id_map), 2447 rtwdev->mac_id_map); 2448 seq_printf(m, "\taddr_cam: %*ph\n", (int)sizeof(cam_info->addr_cam_map), 2449 cam_info->addr_cam_map); 2450 seq_printf(m, "\tbssid_cam: %*ph\n", (int)sizeof(cam_info->bssid_cam_map), 2451 cam_info->bssid_cam_map); 2452 seq_printf(m, "\tsec_cam: %*ph\n", (int)sizeof(cam_info->sec_cam_map), 2453 cam_info->sec_cam_map); 2454 2455 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw, 2456 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, m); 2457 2458 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, m); 2459 2460 return 0; 2461 } 2462 2463 static struct rtw89_debugfs_priv rtw89_debug_priv_read_reg = { 2464 .cb_read = rtw89_debug_priv_read_reg_get, 2465 .cb_write = rtw89_debug_priv_read_reg_select, 2466 }; 2467 2468 static struct rtw89_debugfs_priv rtw89_debug_priv_write_reg = { 2469 .cb_write = rtw89_debug_priv_write_reg_set, 2470 }; 2471 2472 static struct rtw89_debugfs_priv rtw89_debug_priv_read_rf = { 2473 .cb_read = rtw89_debug_priv_read_rf_get, 2474 .cb_write = rtw89_debug_priv_read_rf_select, 2475 }; 2476 2477 static struct rtw89_debugfs_priv rtw89_debug_priv_write_rf = { 2478 .cb_write = rtw89_debug_priv_write_rf_set, 2479 }; 2480 2481 static struct rtw89_debugfs_priv rtw89_debug_priv_rf_reg_dump = { 2482 .cb_read = rtw89_debug_priv_rf_reg_dump_get, 2483 }; 2484 2485 static struct rtw89_debugfs_priv rtw89_debug_priv_txpwr_table = { 2486 .cb_read = rtw89_debug_priv_txpwr_table_get, 2487 }; 2488 2489 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_reg_dump = { 2490 .cb_read = rtw89_debug_priv_mac_reg_dump_get, 2491 .cb_write = rtw89_debug_priv_mac_reg_dump_select, 2492 }; 2493 2494 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_mem_dump = { 2495 .cb_read = rtw89_debug_priv_mac_mem_dump_get, 2496 .cb_write = rtw89_debug_priv_mac_mem_dump_select, 2497 }; 2498 2499 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_dbg_port_dump = { 2500 .cb_read = rtw89_debug_priv_mac_dbg_port_dump_get, 2501 .cb_write = rtw89_debug_priv_mac_dbg_port_dump_select, 2502 }; 2503 2504 static struct rtw89_debugfs_priv rtw89_debug_priv_send_h2c = { 2505 .cb_write = rtw89_debug_priv_send_h2c_set, 2506 }; 2507 2508 static struct rtw89_debugfs_priv rtw89_debug_priv_early_h2c = { 2509 .cb_read = rtw89_debug_priv_early_h2c_get, 2510 .cb_write = rtw89_debug_priv_early_h2c_set, 2511 }; 2512 2513 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_crash = { 2514 .cb_read = rtw89_debug_priv_fw_crash_get, 2515 .cb_write = rtw89_debug_priv_fw_crash_set, 2516 }; 2517 2518 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_info = { 2519 .cb_read = rtw89_debug_priv_btc_info_get, 2520 }; 2521 2522 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_manual = { 2523 .cb_write = rtw89_debug_priv_btc_manual_set, 2524 }; 2525 2526 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_log_manual = { 2527 .cb_write = rtw89_debug_fw_log_btc_manual_set, 2528 }; 2529 2530 static struct rtw89_debugfs_priv rtw89_debug_priv_phy_info = { 2531 .cb_read = rtw89_debug_priv_phy_info_get, 2532 }; 2533 2534 static struct rtw89_debugfs_priv rtw89_debug_priv_stations = { 2535 .cb_read = rtw89_debug_priv_stations_get, 2536 }; 2537 2538 #define rtw89_debugfs_add(name, mode, fopname, parent) \ 2539 do { \ 2540 rtw89_debug_priv_ ##name.rtwdev = rtwdev; \ 2541 if (!debugfs_create_file(#name, mode, \ 2542 parent, &rtw89_debug_priv_ ##name, \ 2543 &file_ops_ ##fopname)) \ 2544 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 2545 } while (0) 2546 2547 #define rtw89_debugfs_add_w(name) \ 2548 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 2549 #define rtw89_debugfs_add_rw(name) \ 2550 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 2551 #define rtw89_debugfs_add_r(name) \ 2552 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 2553 2554 void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 2555 { 2556 struct dentry *debugfs_topdir; 2557 2558 debugfs_topdir = debugfs_create_dir("rtw89", 2559 rtwdev->hw->wiphy->debugfsdir); 2560 2561 rtw89_debugfs_add_rw(read_reg); 2562 rtw89_debugfs_add_w(write_reg); 2563 rtw89_debugfs_add_rw(read_rf); 2564 rtw89_debugfs_add_w(write_rf); 2565 rtw89_debugfs_add_r(rf_reg_dump); 2566 rtw89_debugfs_add_r(txpwr_table); 2567 rtw89_debugfs_add_rw(mac_reg_dump); 2568 rtw89_debugfs_add_rw(mac_mem_dump); 2569 rtw89_debugfs_add_rw(mac_dbg_port_dump); 2570 rtw89_debugfs_add_w(send_h2c); 2571 rtw89_debugfs_add_rw(early_h2c); 2572 rtw89_debugfs_add_rw(fw_crash); 2573 rtw89_debugfs_add_r(btc_info); 2574 rtw89_debugfs_add_w(btc_manual); 2575 rtw89_debugfs_add_w(fw_log_manual); 2576 rtw89_debugfs_add_r(phy_info); 2577 rtw89_debugfs_add_r(stations); 2578 } 2579 #endif 2580 2581 #ifdef CONFIG_RTW89_DEBUGMSG 2582 void __rtw89_debug(struct rtw89_dev *rtwdev, 2583 enum rtw89_debug_mask mask, 2584 const char *fmt, ...) 2585 { 2586 struct va_format vaf = { 2587 .fmt = fmt, 2588 }; 2589 2590 va_list args; 2591 2592 va_start(args, fmt); 2593 vaf.va = &args; 2594 2595 if (rtw89_debug_mask & mask) 2596 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 2597 2598 va_end(args); 2599 } 2600 EXPORT_SYMBOL(__rtw89_debug); 2601 #endif 2602