1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include <linux/vmalloc.h> 6 7 #include "coex.h" 8 #include "debug.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "ps.h" 12 #include "reg.h" 13 #include "sar.h" 14 15 #ifdef CONFIG_RTW89_DEBUGMSG 16 unsigned int rtw89_debug_mask; 17 EXPORT_SYMBOL(rtw89_debug_mask); 18 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 19 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 20 #endif 21 22 #ifdef CONFIG_RTW89_DEBUGFS 23 struct rtw89_debugfs_priv { 24 struct rtw89_dev *rtwdev; 25 int (*cb_read)(struct seq_file *m, void *v); 26 ssize_t (*cb_write)(struct file *filp, const char __user *buffer, 27 size_t count, loff_t *loff); 28 union { 29 u32 cb_data; 30 struct { 31 u32 addr; 32 u8 len; 33 } read_reg; 34 struct { 35 u32 addr; 36 u32 mask; 37 u8 path; 38 } read_rf; 39 struct { 40 u8 ss_dbg:1; 41 u8 dle_dbg:1; 42 u8 dmac_dbg:1; 43 u8 cmac_dbg:1; 44 u8 dbg_port:1; 45 } dbgpkg_en; 46 struct { 47 u32 start; 48 u32 len; 49 u8 sel; 50 } mac_mem; 51 }; 52 }; 53 54 static int rtw89_debugfs_single_show(struct seq_file *m, void *v) 55 { 56 struct rtw89_debugfs_priv *debugfs_priv = m->private; 57 58 return debugfs_priv->cb_read(m, v); 59 } 60 61 static ssize_t rtw89_debugfs_single_write(struct file *filp, 62 const char __user *buffer, 63 size_t count, loff_t *loff) 64 { 65 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 66 67 return debugfs_priv->cb_write(filp, buffer, count, loff); 68 } 69 70 static ssize_t rtw89_debugfs_seq_file_write(struct file *filp, 71 const char __user *buffer, 72 size_t count, loff_t *loff) 73 { 74 struct seq_file *seqpriv = (struct seq_file *)filp->private_data; 75 struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private; 76 77 return debugfs_priv->cb_write(filp, buffer, count, loff); 78 } 79 80 static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp) 81 { 82 return single_open(filp, rtw89_debugfs_single_show, inode->i_private); 83 } 84 85 static int rtw89_debugfs_close(struct inode *inode, struct file *filp) 86 { 87 return 0; 88 } 89 90 static const struct file_operations file_ops_single_r = { 91 .owner = THIS_MODULE, 92 .open = rtw89_debugfs_single_open, 93 .read = seq_read, 94 .llseek = seq_lseek, 95 .release = single_release, 96 }; 97 98 static const struct file_operations file_ops_common_rw = { 99 .owner = THIS_MODULE, 100 .open = rtw89_debugfs_single_open, 101 .release = single_release, 102 .read = seq_read, 103 .llseek = seq_lseek, 104 .write = rtw89_debugfs_seq_file_write, 105 }; 106 107 static const struct file_operations file_ops_single_w = { 108 .owner = THIS_MODULE, 109 .write = rtw89_debugfs_single_write, 110 .open = simple_open, 111 .release = rtw89_debugfs_close, 112 }; 113 114 static ssize_t 115 rtw89_debug_priv_read_reg_select(struct file *filp, 116 const char __user *user_buf, 117 size_t count, loff_t *loff) 118 { 119 struct seq_file *m = (struct seq_file *)filp->private_data; 120 struct rtw89_debugfs_priv *debugfs_priv = m->private; 121 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 122 char buf[32]; 123 size_t buf_size; 124 u32 addr, len; 125 int num; 126 127 buf_size = min(count, sizeof(buf) - 1); 128 if (copy_from_user(buf, user_buf, buf_size)) 129 return -EFAULT; 130 131 buf[buf_size] = '\0'; 132 num = sscanf(buf, "%x %x", &addr, &len); 133 if (num != 2) { 134 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 135 return -EINVAL; 136 } 137 138 debugfs_priv->read_reg.addr = addr; 139 debugfs_priv->read_reg.len = len; 140 141 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 142 143 return count; 144 } 145 146 static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v) 147 { 148 struct rtw89_debugfs_priv *debugfs_priv = m->private; 149 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 150 u32 addr, data; 151 u8 len; 152 153 len = debugfs_priv->read_reg.len; 154 addr = debugfs_priv->read_reg.addr; 155 156 switch (len) { 157 case 1: 158 data = rtw89_read8(rtwdev, addr); 159 break; 160 case 2: 161 data = rtw89_read16(rtwdev, addr); 162 break; 163 case 4: 164 data = rtw89_read32(rtwdev, addr); 165 break; 166 default: 167 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 168 return -EINVAL; 169 } 170 171 seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data); 172 173 return 0; 174 } 175 176 static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp, 177 const char __user *user_buf, 178 size_t count, loff_t *loff) 179 { 180 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 181 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 182 char buf[32]; 183 size_t buf_size; 184 u32 addr, val, len; 185 int num; 186 187 buf_size = min(count, sizeof(buf) - 1); 188 if (copy_from_user(buf, user_buf, buf_size)) 189 return -EFAULT; 190 191 buf[buf_size] = '\0'; 192 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 193 if (num != 3) { 194 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 195 return -EINVAL; 196 } 197 198 switch (len) { 199 case 1: 200 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 201 rtw89_write8(rtwdev, addr, (u8)val); 202 break; 203 case 2: 204 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 205 rtw89_write16(rtwdev, addr, (u16)val); 206 break; 207 case 4: 208 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 209 rtw89_write32(rtwdev, addr, (u32)val); 210 break; 211 default: 212 rtw89_info(rtwdev, "invalid read write len %d\n", len); 213 break; 214 } 215 216 return count; 217 } 218 219 static ssize_t 220 rtw89_debug_priv_read_rf_select(struct file *filp, 221 const char __user *user_buf, 222 size_t count, loff_t *loff) 223 { 224 struct seq_file *m = (struct seq_file *)filp->private_data; 225 struct rtw89_debugfs_priv *debugfs_priv = m->private; 226 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 227 char buf[32]; 228 size_t buf_size; 229 u32 addr, mask; 230 u8 path; 231 int num; 232 233 buf_size = min(count, sizeof(buf) - 1); 234 if (copy_from_user(buf, user_buf, buf_size)) 235 return -EFAULT; 236 237 buf[buf_size] = '\0'; 238 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 239 if (num != 3) { 240 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 241 return -EINVAL; 242 } 243 244 if (path >= rtwdev->chip->rf_path_num) { 245 rtw89_info(rtwdev, "wrong rf path\n"); 246 return -EINVAL; 247 } 248 debugfs_priv->read_rf.addr = addr; 249 debugfs_priv->read_rf.mask = mask; 250 debugfs_priv->read_rf.path = path; 251 252 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 253 254 return count; 255 } 256 257 static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v) 258 { 259 struct rtw89_debugfs_priv *debugfs_priv = m->private; 260 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 261 u32 addr, data, mask; 262 u8 path; 263 264 addr = debugfs_priv->read_rf.addr; 265 mask = debugfs_priv->read_rf.mask; 266 path = debugfs_priv->read_rf.path; 267 268 data = rtw89_read_rf(rtwdev, path, addr, mask); 269 270 seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data); 271 272 return 0; 273 } 274 275 static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp, 276 const char __user *user_buf, 277 size_t count, loff_t *loff) 278 { 279 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 280 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 281 char buf[32]; 282 size_t buf_size; 283 u32 addr, val, mask; 284 u8 path; 285 int num; 286 287 buf_size = min(count, sizeof(buf) - 1); 288 if (copy_from_user(buf, user_buf, buf_size)) 289 return -EFAULT; 290 291 buf[buf_size] = '\0'; 292 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 293 if (num != 4) { 294 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 295 return -EINVAL; 296 } 297 298 if (path >= rtwdev->chip->rf_path_num) { 299 rtw89_info(rtwdev, "wrong rf path\n"); 300 return -EINVAL; 301 } 302 303 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 304 path, addr, val, mask); 305 rtw89_write_rf(rtwdev, path, addr, mask, val); 306 307 return count; 308 } 309 310 static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v) 311 { 312 struct rtw89_debugfs_priv *debugfs_priv = m->private; 313 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 314 const struct rtw89_chip_info *chip = rtwdev->chip; 315 u32 addr, offset, data; 316 u8 path; 317 318 for (path = 0; path < chip->rf_path_num; path++) { 319 seq_printf(m, "RF path %d:\n\n", path); 320 for (addr = 0; addr < 0x100; addr += 4) { 321 seq_printf(m, "0x%08x: ", addr); 322 for (offset = 0; offset < 4; offset++) { 323 data = rtw89_read_rf(rtwdev, path, 324 addr + offset, RFREG_MASK); 325 seq_printf(m, "0x%05x ", data); 326 } 327 seq_puts(m, "\n"); 328 } 329 seq_puts(m, "\n"); 330 } 331 332 return 0; 333 } 334 335 struct txpwr_ent { 336 const char *txt; 337 u8 len; 338 }; 339 340 struct txpwr_map { 341 const struct txpwr_ent *ent; 342 u8 size; 343 u32 addr_from; 344 u32 addr_to; 345 }; 346 347 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 348 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 349 350 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 351 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 352 353 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 354 { .len = 8, .txt = _t "\t- " \ 355 _e0 " " _e1 " " _e2 " " _e3 " " \ 356 _e4 " " _e5 " " _e6 " " _e7 } 357 358 static const struct txpwr_ent __txpwr_ent_byr[] = { 359 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 360 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 361 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 362 /* 1NSS */ 363 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 364 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 365 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 366 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 367 /* 2NSS */ 368 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 369 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 370 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 371 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 372 }; 373 374 static_assert((ARRAY_SIZE(__txpwr_ent_byr) * 4) == 375 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 376 377 static const struct txpwr_map __txpwr_map_byr = { 378 .ent = __txpwr_ent_byr, 379 .size = ARRAY_SIZE(__txpwr_ent_byr), 380 .addr_from = R_AX_PWR_BY_RATE, 381 .addr_to = R_AX_PWR_BY_RATE_MAX, 382 }; 383 384 static const struct txpwr_ent __txpwr_ent_lmt[] = { 385 /* 1TX */ 386 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 387 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 388 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 389 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 390 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 391 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 392 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 393 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 394 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 395 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 396 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 397 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 398 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 399 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 400 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 401 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 402 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 403 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 404 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 405 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 406 /* 2TX */ 407 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 408 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 409 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 410 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 411 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 412 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 413 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 414 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 415 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 416 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 417 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 418 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 419 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 420 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 421 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 422 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 423 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 424 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 425 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 426 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 427 }; 428 429 static_assert((ARRAY_SIZE(__txpwr_ent_lmt) * 2) == 430 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 431 432 static const struct txpwr_map __txpwr_map_lmt = { 433 .ent = __txpwr_ent_lmt, 434 .size = ARRAY_SIZE(__txpwr_ent_lmt), 435 .addr_from = R_AX_PWR_LMT, 436 .addr_to = R_AX_PWR_LMT_MAX, 437 }; 438 439 static const struct txpwr_ent __txpwr_ent_lmt_ru[] = { 440 /* 1TX */ 441 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 442 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 443 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 444 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 445 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 446 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 447 /* 2TX */ 448 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 449 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 450 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 451 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 452 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 453 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 454 }; 455 456 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru) * 8) == 457 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 458 459 static const struct txpwr_map __txpwr_map_lmt_ru = { 460 .ent = __txpwr_ent_lmt_ru, 461 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru), 462 .addr_from = R_AX_PWR_RU_LMT, 463 .addr_to = R_AX_PWR_RU_LMT_MAX, 464 }; 465 466 static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent, 467 const s8 *buf, const u8 cur) 468 { 469 char *fmt; 470 471 switch (ent->len) { 472 case 2: 473 fmt = "%s\t| %3d, %3d,\tdBm\n"; 474 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]); 475 return 2; 476 case 4: 477 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 478 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 479 buf[cur + 2], buf[cur + 3]); 480 return 4; 481 case 8: 482 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 483 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 484 buf[cur + 2], buf[cur + 3], buf[cur + 4], 485 buf[cur + 5], buf[cur + 6], buf[cur + 7]); 486 return 8; 487 default: 488 return 0; 489 } 490 } 491 492 static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev, 493 const struct txpwr_map *map) 494 { 495 u8 fct = rtwdev->chip->txpwr_factor_mac; 496 u32 val, addr; 497 s8 *buf, tmp; 498 u8 cur, i; 499 int ret; 500 501 buf = vzalloc(map->addr_to - map->addr_from + 4); 502 if (!buf) 503 return -ENOMEM; 504 505 for (addr = map->addr_from; addr <= map->addr_to; addr += 4) { 506 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 507 if (ret) 508 val = MASKDWORD; 509 510 cur = addr - map->addr_from; 511 for (i = 0; i < 4; i++, val >>= 8) { 512 /* signed 7 bits, and reserved BIT(7) */ 513 tmp = sign_extend32(val, 6); 514 buf[cur + i] = tmp >> fct; 515 } 516 } 517 518 for (cur = 0, i = 0; i < map->size; i++) 519 cur += __print_txpwr_ent(m, &map->ent[i], buf, cur); 520 521 vfree(buf); 522 return 0; 523 } 524 525 #define case_REGD(_regd) \ 526 case RTW89_ ## _regd: \ 527 seq_puts(m, #_regd "\n"); \ 528 break 529 530 static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev) 531 { 532 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 533 u8 band = chan->band_type; 534 u8 regd = rtw89_regd_get(rtwdev, band); 535 536 switch (regd) { 537 default: 538 seq_printf(m, "UNKNOWN: %d\n", regd); 539 break; 540 case_REGD(WW); 541 case_REGD(ETSI); 542 case_REGD(FCC); 543 case_REGD(MKK); 544 case_REGD(NA); 545 case_REGD(IC); 546 case_REGD(KCC); 547 case_REGD(NCC); 548 case_REGD(CHILE); 549 case_REGD(ACMA); 550 case_REGD(MEXICO); 551 case_REGD(UKRAINE); 552 case_REGD(CN); 553 } 554 } 555 556 #undef case_REGD 557 558 static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v) 559 { 560 struct rtw89_debugfs_priv *debugfs_priv = m->private; 561 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 562 int ret = 0; 563 564 mutex_lock(&rtwdev->mutex); 565 rtw89_leave_ps_mode(rtwdev); 566 567 seq_puts(m, "[Regulatory] "); 568 __print_regd(m, rtwdev); 569 570 seq_puts(m, "[SAR]\n"); 571 rtw89_print_sar(m, rtwdev); 572 573 seq_puts(m, "\n[TX power byrate]\n"); 574 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_byr); 575 if (ret) 576 goto err; 577 578 seq_puts(m, "\n[TX power limit]\n"); 579 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt); 580 if (ret) 581 goto err; 582 583 seq_puts(m, "\n[TX power limit_ru]\n"); 584 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt_ru); 585 if (ret) 586 goto err; 587 588 err: 589 mutex_unlock(&rtwdev->mutex); 590 return ret; 591 } 592 593 static ssize_t 594 rtw89_debug_priv_mac_reg_dump_select(struct file *filp, 595 const char __user *user_buf, 596 size_t count, loff_t *loff) 597 { 598 struct seq_file *m = (struct seq_file *)filp->private_data; 599 struct rtw89_debugfs_priv *debugfs_priv = m->private; 600 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 601 char buf[32]; 602 size_t buf_size; 603 int sel; 604 int ret; 605 606 buf_size = min(count, sizeof(buf) - 1); 607 if (copy_from_user(buf, user_buf, buf_size)) 608 return -EFAULT; 609 610 buf[buf_size] = '\0'; 611 ret = kstrtoint(buf, 0, &sel); 612 if (ret) 613 return ret; 614 615 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 616 rtw89_info(rtwdev, "invalid args: %d\n", sel); 617 return -EINVAL; 618 } 619 620 debugfs_priv->cb_data = sel; 621 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 622 623 return count; 624 } 625 626 #define RTW89_MAC_PAGE_SIZE 0x100 627 628 static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v) 629 { 630 struct rtw89_debugfs_priv *debugfs_priv = m->private; 631 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 632 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 633 u32 start, end; 634 u32 i, j, k, page; 635 u32 val; 636 637 switch (reg_sel) { 638 case RTW89_DBG_SEL_MAC_00: 639 seq_puts(m, "Debug selected MAC page 0x00\n"); 640 start = 0x000; 641 end = 0x014; 642 break; 643 case RTW89_DBG_SEL_MAC_30: 644 seq_puts(m, "Debug selected MAC page 0x30\n"); 645 start = 0x030; 646 end = 0x033; 647 break; 648 case RTW89_DBG_SEL_MAC_40: 649 seq_puts(m, "Debug selected MAC page 0x40\n"); 650 start = 0x040; 651 end = 0x07f; 652 break; 653 case RTW89_DBG_SEL_MAC_80: 654 seq_puts(m, "Debug selected MAC page 0x80\n"); 655 start = 0x080; 656 end = 0x09f; 657 break; 658 case RTW89_DBG_SEL_MAC_C0: 659 seq_puts(m, "Debug selected MAC page 0xc0\n"); 660 start = 0x0c0; 661 end = 0x0df; 662 break; 663 case RTW89_DBG_SEL_MAC_E0: 664 seq_puts(m, "Debug selected MAC page 0xe0\n"); 665 start = 0x0e0; 666 end = 0x0ff; 667 break; 668 case RTW89_DBG_SEL_BB: 669 seq_puts(m, "Debug selected BB register\n"); 670 start = 0x100; 671 end = 0x17f; 672 break; 673 case RTW89_DBG_SEL_IQK: 674 seq_puts(m, "Debug selected IQK register\n"); 675 start = 0x180; 676 end = 0x1bf; 677 break; 678 case RTW89_DBG_SEL_RFC: 679 seq_puts(m, "Debug selected RFC register\n"); 680 start = 0x1c0; 681 end = 0x1ff; 682 break; 683 default: 684 seq_puts(m, "Selected invalid register page\n"); 685 return -EINVAL; 686 } 687 688 for (i = start; i <= end; i++) { 689 page = i << 8; 690 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 691 seq_printf(m, "%08xh : ", 0x18600000 + j); 692 for (k = 0; k < 4; k++) { 693 val = rtw89_read32(rtwdev, j + (k << 2)); 694 seq_printf(m, "%08x ", val); 695 } 696 seq_puts(m, "\n"); 697 } 698 } 699 700 return 0; 701 } 702 703 static ssize_t 704 rtw89_debug_priv_mac_mem_dump_select(struct file *filp, 705 const char __user *user_buf, 706 size_t count, loff_t *loff) 707 { 708 struct seq_file *m = (struct seq_file *)filp->private_data; 709 struct rtw89_debugfs_priv *debugfs_priv = m->private; 710 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 711 char buf[32]; 712 size_t buf_size; 713 u32 sel, start_addr, len; 714 int num; 715 716 buf_size = min(count, sizeof(buf) - 1); 717 if (copy_from_user(buf, user_buf, buf_size)) 718 return -EFAULT; 719 720 buf[buf_size] = '\0'; 721 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 722 if (num != 3) { 723 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 724 return -EINVAL; 725 } 726 727 debugfs_priv->mac_mem.sel = sel; 728 debugfs_priv->mac_mem.start = start_addr; 729 debugfs_priv->mac_mem.len = len; 730 731 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 732 sel, start_addr, len); 733 734 return count; 735 } 736 737 static void rtw89_debug_dump_mac_mem(struct seq_file *m, 738 struct rtw89_dev *rtwdev, 739 u8 sel, u32 start_addr, u32 len) 740 { 741 u32 base_addr, start_page, residue; 742 u32 i, j, p, pages; 743 u32 dump_len, remain; 744 u32 val; 745 746 remain = len; 747 pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1; 748 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE; 749 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE; 750 base_addr = rtw89_mac_mem_base_addrs[sel]; 751 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE; 752 753 for (p = 0; p < pages; p++) { 754 dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE); 755 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, base_addr); 756 for (i = R_AX_INDIR_ACCESS_ENTRY + residue; 757 i < R_AX_INDIR_ACCESS_ENTRY + dump_len;) { 758 seq_printf(m, "%08xh:", i); 759 for (j = 0; 760 j < 4 && i < R_AX_INDIR_ACCESS_ENTRY + dump_len; 761 j++, i += 4) { 762 val = rtw89_read32(rtwdev, i); 763 seq_printf(m, " %08x", val); 764 remain -= 4; 765 } 766 seq_puts(m, "\n"); 767 } 768 base_addr += MAC_MEM_DUMP_PAGE_SIZE; 769 } 770 } 771 772 static int 773 rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v) 774 { 775 struct rtw89_debugfs_priv *debugfs_priv = m->private; 776 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 777 bool grant_read = false; 778 779 if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM) 780 return -ENOENT; 781 782 if (rtwdev->chip->chip_id == RTL8852C) { 783 switch (debugfs_priv->mac_mem.sel) { 784 case RTW89_MAC_MEM_TXD_FIFO_0_V1: 785 case RTW89_MAC_MEM_TXD_FIFO_1_V1: 786 case RTW89_MAC_MEM_TXDATA_FIFO_0: 787 case RTW89_MAC_MEM_TXDATA_FIFO_1: 788 grant_read = true; 789 break; 790 default: 791 break; 792 } 793 } 794 795 mutex_lock(&rtwdev->mutex); 796 rtw89_leave_ps_mode(rtwdev); 797 if (grant_read) 798 rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 799 rtw89_debug_dump_mac_mem(m, rtwdev, 800 debugfs_priv->mac_mem.sel, 801 debugfs_priv->mac_mem.start, 802 debugfs_priv->mac_mem.len); 803 if (grant_read) 804 rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 805 mutex_unlock(&rtwdev->mutex); 806 807 return 0; 808 } 809 810 static ssize_t 811 rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp, 812 const char __user *user_buf, 813 size_t count, loff_t *loff) 814 { 815 struct seq_file *m = (struct seq_file *)filp->private_data; 816 struct rtw89_debugfs_priv *debugfs_priv = m->private; 817 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 818 char buf[32]; 819 size_t buf_size; 820 int sel, set; 821 int num; 822 bool enable; 823 824 buf_size = min(count, sizeof(buf) - 1); 825 if (copy_from_user(buf, user_buf, buf_size)) 826 return -EFAULT; 827 828 buf[buf_size] = '\0'; 829 num = sscanf(buf, "%d %d", &sel, &set); 830 if (num != 2) { 831 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 832 return -EINVAL; 833 } 834 835 enable = set != 0; 836 switch (sel) { 837 case 0: 838 debugfs_priv->dbgpkg_en.ss_dbg = enable; 839 break; 840 case 1: 841 debugfs_priv->dbgpkg_en.dle_dbg = enable; 842 break; 843 case 2: 844 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 845 break; 846 case 3: 847 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 848 break; 849 case 4: 850 debugfs_priv->dbgpkg_en.dbg_port = enable; 851 break; 852 default: 853 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 854 return -EINVAL; 855 } 856 857 rtw89_info(rtwdev, "%s debug port dump %d\n", 858 enable ? "Enable" : "Disable", sel); 859 860 return count; 861 } 862 863 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 864 struct seq_file *m) 865 { 866 return 0; 867 } 868 869 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 870 struct seq_file *m) 871 { 872 #define DLE_DFI_DUMP(__type, __target, __sel) \ 873 ({ \ 874 u32 __ctrl; \ 875 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 876 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 877 u32 __data, __val32; \ 878 int __ret; \ 879 \ 880 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 881 DLE_DFI_TYPE_##__target) | \ 882 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 883 B_AX_WDE_DFI_ACTIVE; \ 884 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 885 __ret = read_poll_timeout(rtw89_read32, __val32, \ 886 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 887 1000, 50000, false, \ 888 rtwdev, __reg_ctrl); \ 889 if (__ret) { \ 890 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 891 #__type, #__target, __sel); \ 892 return __ret; \ 893 } \ 894 \ 895 __data = rtw89_read32(rtwdev, __reg_data); \ 896 __data; \ 897 }) 898 899 #define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \ 900 ({ \ 901 u32 __freepg, __pubpg; \ 902 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 903 \ 904 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 905 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 906 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 907 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 908 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 909 seq_printf(__m, "[%s] freepg head: %d\n", \ 910 #__type, __freepg_head); \ 911 seq_printf(__m, "[%s] freepg tail: %d\n", \ 912 #__type, __freepg_tail); \ 913 seq_printf(__m, "[%s] pubpg num : %d\n", \ 914 #__type, __pubpg_num); \ 915 }) 916 917 #define case_QUOTA(__m, __type, __id) \ 918 case __type##_QTAID_##__id: \ 919 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 920 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 921 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 922 seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \ 923 #__type, #__id, rsv_pgnum); \ 924 seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \ 925 #__type, #__id, use_pgnum); \ 926 break 927 u32 quota_id; 928 u32 val32; 929 u16 rsv_pgnum, use_pgnum; 930 int ret; 931 932 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 933 if (ret) { 934 seq_puts(m, "[DLE] : DMAC not enabled\n"); 935 return ret; 936 } 937 938 DLE_DFI_FREE_PAGE_DUMP(m, WDE); 939 DLE_DFI_FREE_PAGE_DUMP(m, PLE); 940 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 941 switch (quota_id) { 942 case_QUOTA(m, WDE, HOST_IF); 943 case_QUOTA(m, WDE, WLAN_CPU); 944 case_QUOTA(m, WDE, DATA_CPU); 945 case_QUOTA(m, WDE, PKTIN); 946 case_QUOTA(m, WDE, CPUIO); 947 } 948 } 949 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 950 switch (quota_id) { 951 case_QUOTA(m, PLE, B0_TXPL); 952 case_QUOTA(m, PLE, B1_TXPL); 953 case_QUOTA(m, PLE, C2H); 954 case_QUOTA(m, PLE, H2C); 955 case_QUOTA(m, PLE, WLAN_CPU); 956 case_QUOTA(m, PLE, MPDU); 957 case_QUOTA(m, PLE, CMAC0_RX); 958 case_QUOTA(m, PLE, CMAC1_RX); 959 case_QUOTA(m, PLE, CMAC1_BBRPT); 960 case_QUOTA(m, PLE, WDRLS); 961 case_QUOTA(m, PLE, CPUIO); 962 } 963 } 964 965 return 0; 966 967 #undef case_QUOTA 968 #undef DLE_DFI_DUMP 969 #undef DLE_DFI_FREE_PAGE_DUMP 970 } 971 972 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 973 struct seq_file *m) 974 { 975 int ret; 976 977 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 978 if (ret) { 979 seq_puts(m, "[DMAC] : DMAC not enabled\n"); 980 return ret; 981 } 982 983 seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n", 984 rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR)); 985 seq_printf(m, "[0]R_AX_WDRLS_ERR_ISR=0x%08x\n", 986 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 987 seq_printf(m, "[1]R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 988 rtw89_read32(rtwdev, R_AX_SEC_ERR_IMR_ISR)); 989 seq_printf(m, "[2.1]R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 990 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 991 seq_printf(m, "[2.2]R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 992 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 993 seq_printf(m, "[3]R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 994 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 995 seq_printf(m, "[4]R_AX_WDE_ERR_ISR=0x%08x\n", 996 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 997 seq_printf(m, "[5.1]R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 998 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 999 seq_printf(m, "[5.2]R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 1000 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 1001 seq_printf(m, "[6]R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1002 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1003 seq_printf(m, "[7]R_AX_PKTIN_ERR_ISR=0x%08x\n", 1004 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 1005 seq_printf(m, "[8.1]R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 1006 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 1007 seq_printf(m, "[8.2]R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 1008 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 1009 seq_printf(m, "[8.3]R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 1010 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 1011 seq_printf(m, "[10]R_AX_CPUIO_ERR_ISR=0x%08x\n", 1012 rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR)); 1013 seq_printf(m, "[11.1]R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 1014 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 1015 seq_printf(m, "[11.2]R_AX_BBRPT_CHINFO_ERR_IMR_ISR=0x%08x\n", 1016 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR_ISR)); 1017 seq_printf(m, "[11.3]R_AX_BBRPT_DFS_ERR_IMR_ISR=0x%08x\n", 1018 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR_ISR)); 1019 seq_printf(m, "[11.4]R_AX_LA_ERRFLAG=0x%08x\n", 1020 rtw89_read32(rtwdev, R_AX_LA_ERRFLAG)); 1021 1022 return 0; 1023 } 1024 1025 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 1026 struct seq_file *m) 1027 { 1028 int ret; 1029 1030 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL); 1031 if (ret) { 1032 seq_puts(m, "[CMAC] : CMAC 0 not enabled\n"); 1033 return ret; 1034 } 1035 1036 seq_printf(m, "R_AX_CMAC_ERR_ISR=0x%08x\n", 1037 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR)); 1038 seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR=0x%08x\n", 1039 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR)); 1040 seq_printf(m, "[1]R_AX_PTCL_ISR0=0x%08x\n", 1041 rtw89_read32(rtwdev, R_AX_PTCL_ISR0)); 1042 seq_printf(m, "[3]R_AX_DLE_CTRL=0x%08x\n", 1043 rtw89_read32(rtwdev, R_AX_DLE_CTRL)); 1044 seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR=0x%08x\n", 1045 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR)); 1046 seq_printf(m, "[5]R_AX_TXPWR_ISR=0x%08x\n", 1047 rtw89_read32(rtwdev, R_AX_TXPWR_ISR)); 1048 seq_printf(m, "[6]R_AX_RMAC_ERR_ISR=0x%08x\n", 1049 rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR)); 1050 seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR=0x%08x\n", 1051 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR)); 1052 1053 ret = rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL); 1054 if (ret) { 1055 seq_puts(m, "[CMAC] : CMAC 1 not enabled\n"); 1056 return ret; 1057 } 1058 1059 seq_printf(m, "R_AX_CMAC_ERR_ISR_C1=0x%08x\n", 1060 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR_C1)); 1061 seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR_C1=0x%08x\n", 1062 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR_C1)); 1063 seq_printf(m, "[1]R_AX_PTCL_ISR0_C1=0x%08x\n", 1064 rtw89_read32(rtwdev, R_AX_PTCL_ISR0_C1)); 1065 seq_printf(m, "[3]R_AX_DLE_CTRL_C1=0x%08x\n", 1066 rtw89_read32(rtwdev, R_AX_DLE_CTRL_C1)); 1067 seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR_C1=0x%02x\n", 1068 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR_C1)); 1069 seq_printf(m, "[5]R_AX_TXPWR_ISR_C1=0x%08x\n", 1070 rtw89_read32(rtwdev, R_AX_TXPWR_ISR_C1)); 1071 seq_printf(m, "[6]R_AX_RMAC_ERR_ISR_C1=0x%08x\n", 1072 rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR_C1)); 1073 seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR_C1=0x%08x\n", 1074 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR_C1)); 1075 1076 return 0; 1077 } 1078 1079 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1080 .sel_addr = R_AX_PTCL_DBG, 1081 .sel_byte = 1, 1082 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1083 .srt = 0x00, 1084 .end = 0x3F, 1085 .rd_addr = R_AX_PTCL_DBG_INFO, 1086 .rd_byte = 4, 1087 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1088 }; 1089 1090 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1091 .sel_addr = R_AX_PTCL_DBG_C1, 1092 .sel_byte = 1, 1093 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1094 .srt = 0x00, 1095 .end = 0x3F, 1096 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1097 .rd_byte = 4, 1098 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1099 }; 1100 1101 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 1102 .sel_addr = R_AX_SCH_DBG_SEL, 1103 .sel_byte = 1, 1104 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1105 .srt = 0x00, 1106 .end = 0x2F, 1107 .rd_addr = R_AX_SCH_DBG, 1108 .rd_byte = 4, 1109 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1110 }; 1111 1112 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 1113 .sel_addr = R_AX_SCH_DBG_SEL_C1, 1114 .sel_byte = 1, 1115 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1116 .srt = 0x00, 1117 .end = 0x2F, 1118 .rd_addr = R_AX_SCH_DBG_C1, 1119 .rd_byte = 4, 1120 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1121 }; 1122 1123 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 1124 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 1125 .sel_byte = 1, 1126 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1127 .srt = 0x00, 1128 .end = 0x19, 1129 .rd_addr = R_AX_DBG_PORT_SEL, 1130 .rd_byte = 4, 1131 .rd_msk = B_AX_DEBUG_ST_MASK 1132 }; 1133 1134 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 1135 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 1136 .sel_byte = 1, 1137 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1138 .srt = 0x00, 1139 .end = 0x19, 1140 .rd_addr = R_AX_DBG_PORT_SEL, 1141 .rd_byte = 4, 1142 .rd_msk = B_AX_DEBUG_ST_MASK 1143 }; 1144 1145 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 1146 .sel_addr = R_AX_RX_DEBUG_SELECT, 1147 .sel_byte = 1, 1148 .sel_msk = B_AX_DEBUG_SEL_MASK, 1149 .srt = 0x00, 1150 .end = 0x58, 1151 .rd_addr = R_AX_DBG_PORT_SEL, 1152 .rd_byte = 4, 1153 .rd_msk = B_AX_DEBUG_ST_MASK 1154 }; 1155 1156 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 1157 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 1158 .sel_byte = 1, 1159 .sel_msk = B_AX_DEBUG_SEL_MASK, 1160 .srt = 0x00, 1161 .end = 0x58, 1162 .rd_addr = R_AX_DBG_PORT_SEL, 1163 .rd_byte = 4, 1164 .rd_msk = B_AX_DEBUG_ST_MASK 1165 }; 1166 1167 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 1168 .sel_addr = R_AX_RX_STATE_MONITOR, 1169 .sel_byte = 1, 1170 .sel_msk = B_AX_STATE_SEL_MASK, 1171 .srt = 0x00, 1172 .end = 0x17, 1173 .rd_addr = R_AX_RX_STATE_MONITOR, 1174 .rd_byte = 4, 1175 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 1176 }; 1177 1178 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 1179 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 1180 .sel_byte = 1, 1181 .sel_msk = B_AX_STATE_SEL_MASK, 1182 .srt = 0x00, 1183 .end = 0x17, 1184 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 1185 .rd_byte = 4, 1186 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 1187 }; 1188 1189 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 1190 .sel_addr = R_AX_RMAC_PLCP_MON, 1191 .sel_byte = 4, 1192 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 1193 .srt = 0x0, 1194 .end = 0xF, 1195 .rd_addr = R_AX_RMAC_PLCP_MON, 1196 .rd_byte = 4, 1197 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 1198 }; 1199 1200 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 1201 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 1202 .sel_byte = 4, 1203 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 1204 .srt = 0x0, 1205 .end = 0xF, 1206 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 1207 .rd_byte = 4, 1208 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 1209 }; 1210 1211 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 1212 .sel_addr = R_AX_DBGSEL_TRXPTCL, 1213 .sel_byte = 1, 1214 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 1215 .srt = 0x08, 1216 .end = 0x10, 1217 .rd_addr = R_AX_DBG_PORT_SEL, 1218 .rd_byte = 4, 1219 .rd_msk = B_AX_DEBUG_ST_MASK 1220 }; 1221 1222 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 1223 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 1224 .sel_byte = 1, 1225 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 1226 .srt = 0x08, 1227 .end = 0x10, 1228 .rd_addr = R_AX_DBG_PORT_SEL, 1229 .rd_byte = 4, 1230 .rd_msk = B_AX_DEBUG_ST_MASK 1231 }; 1232 1233 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 1234 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 1235 .sel_byte = 1, 1236 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1237 .srt = 0x00, 1238 .end = 0x07, 1239 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 1240 .rd_byte = 4, 1241 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 1242 }; 1243 1244 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 1245 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 1246 .sel_byte = 1, 1247 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1248 .srt = 0x00, 1249 .end = 0x07, 1250 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 1251 .rd_byte = 4, 1252 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 1253 }; 1254 1255 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 1256 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 1257 .sel_byte = 1, 1258 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1259 .srt = 0x00, 1260 .end = 0x07, 1261 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 1262 .rd_byte = 4, 1263 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 1264 }; 1265 1266 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 1267 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 1268 .sel_byte = 1, 1269 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1270 .srt = 0x00, 1271 .end = 0x07, 1272 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 1273 .rd_byte = 4, 1274 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 1275 }; 1276 1277 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 1278 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 1279 .sel_byte = 1, 1280 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1281 .srt = 0x00, 1282 .end = 0x04, 1283 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 1284 .rd_byte = 4, 1285 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 1286 }; 1287 1288 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 1289 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 1290 .sel_byte = 1, 1291 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1292 .srt = 0x00, 1293 .end = 0x04, 1294 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 1295 .rd_byte = 4, 1296 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 1297 }; 1298 1299 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 1300 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 1301 .sel_byte = 1, 1302 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1303 .srt = 0x00, 1304 .end = 0x04, 1305 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 1306 .rd_byte = 4, 1307 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 1308 }; 1309 1310 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 1311 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 1312 .sel_byte = 1, 1313 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1314 .srt = 0x00, 1315 .end = 0x04, 1316 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 1317 .rd_byte = 4, 1318 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 1319 }; 1320 1321 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 1322 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1323 .sel_byte = 4, 1324 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1325 .srt = 0x80000000, 1326 .end = 0x80000001, 1327 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1328 .rd_byte = 4, 1329 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1330 }; 1331 1332 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 1333 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1334 .sel_byte = 4, 1335 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1336 .srt = 0x80010000, 1337 .end = 0x80010004, 1338 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1339 .rd_byte = 4, 1340 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1341 }; 1342 1343 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 1344 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1345 .sel_byte = 4, 1346 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1347 .srt = 0x80020000, 1348 .end = 0x80020FFF, 1349 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1350 .rd_byte = 4, 1351 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1352 }; 1353 1354 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 1355 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1356 .sel_byte = 4, 1357 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1358 .srt = 0x80030000, 1359 .end = 0x80030FFF, 1360 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1361 .rd_byte = 4, 1362 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1363 }; 1364 1365 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 1366 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1367 .sel_byte = 4, 1368 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1369 .srt = 0x80040000, 1370 .end = 0x80040FFF, 1371 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1372 .rd_byte = 4, 1373 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1374 }; 1375 1376 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 1377 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1378 .sel_byte = 4, 1379 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1380 .srt = 0x80050000, 1381 .end = 0x80050FFF, 1382 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1383 .rd_byte = 4, 1384 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1385 }; 1386 1387 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 1388 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1389 .sel_byte = 4, 1390 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1391 .srt = 0x80060000, 1392 .end = 0x80060453, 1393 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1394 .rd_byte = 4, 1395 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1396 }; 1397 1398 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 1399 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1400 .sel_byte = 4, 1401 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1402 .srt = 0x80070000, 1403 .end = 0x80070011, 1404 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1405 .rd_byte = 4, 1406 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1407 }; 1408 1409 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 1410 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1411 .sel_byte = 4, 1412 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1413 .srt = 0x80000000, 1414 .end = 0x80000001, 1415 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1416 .rd_byte = 4, 1417 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1418 }; 1419 1420 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 1421 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1422 .sel_byte = 4, 1423 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1424 .srt = 0x80010000, 1425 .end = 0x8001000A, 1426 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1427 .rd_byte = 4, 1428 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1429 }; 1430 1431 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 1432 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1433 .sel_byte = 4, 1434 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1435 .srt = 0x80020000, 1436 .end = 0x80020DBF, 1437 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1438 .rd_byte = 4, 1439 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1440 }; 1441 1442 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 1443 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1444 .sel_byte = 4, 1445 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1446 .srt = 0x80030000, 1447 .end = 0x80030DBF, 1448 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1449 .rd_byte = 4, 1450 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1451 }; 1452 1453 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 1454 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1455 .sel_byte = 4, 1456 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1457 .srt = 0x80040000, 1458 .end = 0x80040DBF, 1459 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1460 .rd_byte = 4, 1461 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1462 }; 1463 1464 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 1465 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1466 .sel_byte = 4, 1467 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1468 .srt = 0x80050000, 1469 .end = 0x80050DBF, 1470 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1471 .rd_byte = 4, 1472 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1473 }; 1474 1475 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 1476 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1477 .sel_byte = 4, 1478 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1479 .srt = 0x80060000, 1480 .end = 0x80060041, 1481 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1482 .rd_byte = 4, 1483 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1484 }; 1485 1486 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 1487 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1488 .sel_byte = 4, 1489 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1490 .srt = 0x80070000, 1491 .end = 0x80070001, 1492 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1493 .rd_byte = 4, 1494 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1495 }; 1496 1497 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 1498 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 1499 .sel_byte = 4, 1500 .sel_msk = B_AX_DFI_DATA_MASK, 1501 .srt = 0x80000000, 1502 .end = 0x8000017f, 1503 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 1504 .rd_byte = 4, 1505 .rd_msk = B_AX_DFI_DATA_MASK 1506 }; 1507 1508 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 1509 .sel_addr = R_AX_PCIE_DBG_CTRL, 1510 .sel_byte = 2, 1511 .sel_msk = B_AX_DBG_SEL_MASK, 1512 .srt = 0x00, 1513 .end = 0x03, 1514 .rd_addr = R_AX_DBG_PORT_SEL, 1515 .rd_byte = 4, 1516 .rd_msk = B_AX_DEBUG_ST_MASK 1517 }; 1518 1519 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 1520 .sel_addr = R_AX_PCIE_DBG_CTRL, 1521 .sel_byte = 2, 1522 .sel_msk = B_AX_DBG_SEL_MASK, 1523 .srt = 0x00, 1524 .end = 0x04, 1525 .rd_addr = R_AX_DBG_PORT_SEL, 1526 .rd_byte = 4, 1527 .rd_msk = B_AX_DEBUG_ST_MASK 1528 }; 1529 1530 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 1531 .sel_addr = R_AX_PCIE_DBG_CTRL, 1532 .sel_byte = 2, 1533 .sel_msk = B_AX_DBG_SEL_MASK, 1534 .srt = 0x00, 1535 .end = 0x01, 1536 .rd_addr = R_AX_DBG_PORT_SEL, 1537 .rd_byte = 4, 1538 .rd_msk = B_AX_DEBUG_ST_MASK 1539 }; 1540 1541 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 1542 .sel_addr = R_AX_PCIE_DBG_CTRL, 1543 .sel_byte = 2, 1544 .sel_msk = B_AX_DBG_SEL_MASK, 1545 .srt = 0x00, 1546 .end = 0x05, 1547 .rd_addr = R_AX_DBG_PORT_SEL, 1548 .rd_byte = 4, 1549 .rd_msk = B_AX_DEBUG_ST_MASK 1550 }; 1551 1552 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 1553 .sel_addr = R_AX_PCIE_DBG_CTRL, 1554 .sel_byte = 2, 1555 .sel_msk = B_AX_DBG_SEL_MASK, 1556 .srt = 0x00, 1557 .end = 0x05, 1558 .rd_addr = R_AX_DBG_PORT_SEL, 1559 .rd_byte = 4, 1560 .rd_msk = B_AX_DEBUG_ST_MASK 1561 }; 1562 1563 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 1564 .sel_addr = R_AX_PCIE_DBG_CTRL, 1565 .sel_byte = 2, 1566 .sel_msk = B_AX_DBG_SEL_MASK, 1567 .srt = 0x00, 1568 .end = 0x06, 1569 .rd_addr = R_AX_DBG_PORT_SEL, 1570 .rd_byte = 4, 1571 .rd_msk = B_AX_DEBUG_ST_MASK 1572 }; 1573 1574 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 1575 .sel_addr = R_AX_DBG_CTRL, 1576 .sel_byte = 1, 1577 .sel_msk = B_AX_DBG_SEL0, 1578 .srt = 0x34, 1579 .end = 0x3C, 1580 .rd_addr = R_AX_DBG_PORT_SEL, 1581 .rd_byte = 4, 1582 .rd_msk = B_AX_DEBUG_ST_MASK 1583 }; 1584 1585 static const struct rtw89_mac_dbg_port_info * 1586 rtw89_debug_mac_dbg_port_sel(struct seq_file *m, 1587 struct rtw89_dev *rtwdev, u32 sel) 1588 { 1589 const struct rtw89_mac_dbg_port_info *info; 1590 u32 val32; 1591 u16 val16; 1592 u8 val8; 1593 1594 switch (sel) { 1595 case RTW89_DBG_PORT_SEL_PTCL_C0: 1596 info = &dbg_port_ptcl_c0; 1597 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 1598 val16 |= B_AX_PTCL_DBG_EN; 1599 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 1600 seq_puts(m, "Enable PTCL C0 dbgport.\n"); 1601 break; 1602 case RTW89_DBG_PORT_SEL_PTCL_C1: 1603 info = &dbg_port_ptcl_c1; 1604 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 1605 val16 |= B_AX_PTCL_DBG_EN; 1606 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 1607 seq_puts(m, "Enable PTCL C1 dbgport.\n"); 1608 break; 1609 case RTW89_DBG_PORT_SEL_SCH_C0: 1610 info = &dbg_port_sch_c0; 1611 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 1612 val32 |= B_AX_SCH_DBG_EN; 1613 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 1614 seq_puts(m, "Enable SCH C0 dbgport.\n"); 1615 break; 1616 case RTW89_DBG_PORT_SEL_SCH_C1: 1617 info = &dbg_port_sch_c1; 1618 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 1619 val32 |= B_AX_SCH_DBG_EN; 1620 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 1621 seq_puts(m, "Enable SCH C1 dbgport.\n"); 1622 break; 1623 case RTW89_DBG_PORT_SEL_TMAC_C0: 1624 info = &dbg_port_tmac_c0; 1625 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 1626 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 1627 B_AX_DBGSEL_TRXPTCL_MASK); 1628 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 1629 1630 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1631 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 1632 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 1633 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1634 1635 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1636 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1637 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1638 seq_puts(m, "Enable TMAC C0 dbgport.\n"); 1639 break; 1640 case RTW89_DBG_PORT_SEL_TMAC_C1: 1641 info = &dbg_port_tmac_c1; 1642 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 1643 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 1644 B_AX_DBGSEL_TRXPTCL_MASK); 1645 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 1646 1647 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1648 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 1649 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 1650 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1651 1652 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1653 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1654 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1655 seq_puts(m, "Enable TMAC C1 dbgport.\n"); 1656 break; 1657 case RTW89_DBG_PORT_SEL_RMAC_C0: 1658 info = &dbg_port_rmac_c0; 1659 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 1660 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 1661 B_AX_DBGSEL_TRXPTCL_MASK); 1662 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 1663 1664 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1665 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 1666 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 1667 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1668 1669 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1670 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1671 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1672 1673 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 1674 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 1675 B_AX_DBGSEL_TRXPTCL_MASK); 1676 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 1677 seq_puts(m, "Enable RMAC C0 dbgport.\n"); 1678 break; 1679 case RTW89_DBG_PORT_SEL_RMAC_C1: 1680 info = &dbg_port_rmac_c1; 1681 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 1682 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 1683 B_AX_DBGSEL_TRXPTCL_MASK); 1684 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 1685 1686 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1687 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 1688 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 1689 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1690 1691 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1692 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1693 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1694 1695 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 1696 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 1697 B_AX_DBGSEL_TRXPTCL_MASK); 1698 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 1699 seq_puts(m, "Enable RMAC C1 dbgport.\n"); 1700 break; 1701 case RTW89_DBG_PORT_SEL_RMACST_C0: 1702 info = &dbg_port_rmacst_c0; 1703 seq_puts(m, "Enable RMAC state C0 dbgport.\n"); 1704 break; 1705 case RTW89_DBG_PORT_SEL_RMACST_C1: 1706 info = &dbg_port_rmacst_c1; 1707 seq_puts(m, "Enable RMAC state C1 dbgport.\n"); 1708 break; 1709 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 1710 info = &dbg_port_rmac_plcp_c0; 1711 seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n"); 1712 break; 1713 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 1714 info = &dbg_port_rmac_plcp_c1; 1715 seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n"); 1716 break; 1717 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 1718 info = &dbg_port_trxptcl_c0; 1719 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1720 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 1721 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 1722 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1723 1724 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1725 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1726 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1727 seq_puts(m, "Enable TRXPTCL C0 dbgport.\n"); 1728 break; 1729 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 1730 info = &dbg_port_trxptcl_c1; 1731 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1732 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 1733 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 1734 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1735 1736 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1737 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1738 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1739 seq_puts(m, "Enable TRXPTCL C1 dbgport.\n"); 1740 break; 1741 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 1742 info = &dbg_port_tx_infol_c0; 1743 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1744 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1745 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1746 seq_puts(m, "Enable tx infol dump.\n"); 1747 break; 1748 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 1749 info = &dbg_port_tx_infoh_c0; 1750 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1751 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1752 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1753 seq_puts(m, "Enable tx infoh dump.\n"); 1754 break; 1755 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 1756 info = &dbg_port_tx_infol_c1; 1757 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1758 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1759 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1760 seq_puts(m, "Enable tx infol dump.\n"); 1761 break; 1762 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 1763 info = &dbg_port_tx_infoh_c1; 1764 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1765 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1766 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1767 seq_puts(m, "Enable tx infoh dump.\n"); 1768 break; 1769 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 1770 info = &dbg_port_txtf_infol_c0; 1771 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1772 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1773 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1774 seq_puts(m, "Enable tx tf infol dump.\n"); 1775 break; 1776 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 1777 info = &dbg_port_txtf_infoh_c0; 1778 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1779 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1780 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1781 seq_puts(m, "Enable tx tf infoh dump.\n"); 1782 break; 1783 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 1784 info = &dbg_port_txtf_infol_c1; 1785 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1786 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1787 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1788 seq_puts(m, "Enable tx tf infol dump.\n"); 1789 break; 1790 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 1791 info = &dbg_port_txtf_infoh_c1; 1792 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1793 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1794 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1795 seq_puts(m, "Enable tx tf infoh dump.\n"); 1796 break; 1797 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 1798 info = &dbg_port_wde_bufmgn_freepg; 1799 seq_puts(m, "Enable wde bufmgn freepg dump.\n"); 1800 break; 1801 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 1802 info = &dbg_port_wde_bufmgn_quota; 1803 seq_puts(m, "Enable wde bufmgn quota dump.\n"); 1804 break; 1805 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 1806 info = &dbg_port_wde_bufmgn_pagellt; 1807 seq_puts(m, "Enable wde bufmgn pagellt dump.\n"); 1808 break; 1809 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 1810 info = &dbg_port_wde_bufmgn_pktinfo; 1811 seq_puts(m, "Enable wde bufmgn pktinfo dump.\n"); 1812 break; 1813 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 1814 info = &dbg_port_wde_quemgn_prepkt; 1815 seq_puts(m, "Enable wde quemgn prepkt dump.\n"); 1816 break; 1817 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 1818 info = &dbg_port_wde_quemgn_nxtpkt; 1819 seq_puts(m, "Enable wde quemgn nxtpkt dump.\n"); 1820 break; 1821 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 1822 info = &dbg_port_wde_quemgn_qlnktbl; 1823 seq_puts(m, "Enable wde quemgn qlnktbl dump.\n"); 1824 break; 1825 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 1826 info = &dbg_port_wde_quemgn_qempty; 1827 seq_puts(m, "Enable wde quemgn qempty dump.\n"); 1828 break; 1829 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 1830 info = &dbg_port_ple_bufmgn_freepg; 1831 seq_puts(m, "Enable ple bufmgn freepg dump.\n"); 1832 break; 1833 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 1834 info = &dbg_port_ple_bufmgn_quota; 1835 seq_puts(m, "Enable ple bufmgn quota dump.\n"); 1836 break; 1837 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 1838 info = &dbg_port_ple_bufmgn_pagellt; 1839 seq_puts(m, "Enable ple bufmgn pagellt dump.\n"); 1840 break; 1841 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 1842 info = &dbg_port_ple_bufmgn_pktinfo; 1843 seq_puts(m, "Enable ple bufmgn pktinfo dump.\n"); 1844 break; 1845 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 1846 info = &dbg_port_ple_quemgn_prepkt; 1847 seq_puts(m, "Enable ple quemgn prepkt dump.\n"); 1848 break; 1849 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 1850 info = &dbg_port_ple_quemgn_nxtpkt; 1851 seq_puts(m, "Enable ple quemgn nxtpkt dump.\n"); 1852 break; 1853 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 1854 info = &dbg_port_ple_quemgn_qlnktbl; 1855 seq_puts(m, "Enable ple quemgn qlnktbl dump.\n"); 1856 break; 1857 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 1858 info = &dbg_port_ple_quemgn_qempty; 1859 seq_puts(m, "Enable ple quemgn qempty dump.\n"); 1860 break; 1861 case RTW89_DBG_PORT_SEL_PKTINFO: 1862 info = &dbg_port_pktinfo; 1863 seq_puts(m, "Enable pktinfo dump.\n"); 1864 break; 1865 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 1866 info = &dbg_port_pcie_txdma; 1867 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1868 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 1869 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 1870 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1871 seq_puts(m, "Enable pcie txdma dump.\n"); 1872 break; 1873 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 1874 info = &dbg_port_pcie_rxdma; 1875 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1876 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 1877 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 1878 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1879 seq_puts(m, "Enable pcie rxdma dump.\n"); 1880 break; 1881 case RTW89_DBG_PORT_SEL_PCIE_CVT: 1882 info = &dbg_port_pcie_cvt; 1883 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1884 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 1885 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 1886 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1887 seq_puts(m, "Enable pcie cvt dump.\n"); 1888 break; 1889 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 1890 info = &dbg_port_pcie_cxpl; 1891 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1892 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 1893 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 1894 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1895 seq_puts(m, "Enable pcie cxpl dump.\n"); 1896 break; 1897 case RTW89_DBG_PORT_SEL_PCIE_IO: 1898 info = &dbg_port_pcie_io; 1899 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1900 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 1901 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 1902 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1903 seq_puts(m, "Enable pcie io dump.\n"); 1904 break; 1905 case RTW89_DBG_PORT_SEL_PCIE_MISC: 1906 info = &dbg_port_pcie_misc; 1907 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1908 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 1909 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 1910 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1911 seq_puts(m, "Enable pcie misc dump.\n"); 1912 break; 1913 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 1914 info = &dbg_port_pcie_misc2; 1915 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 1916 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 1917 B_AX_DBG_SEL_MASK); 1918 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 1919 seq_puts(m, "Enable pcie misc2 dump.\n"); 1920 break; 1921 default: 1922 seq_puts(m, "Dbg port select err\n"); 1923 return NULL; 1924 } 1925 1926 return info; 1927 } 1928 1929 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 1930 { 1931 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 1932 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 1933 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 1934 return false; 1935 if (rtwdev->chip->chip_id == RTL8852B && 1936 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 1937 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 1938 return false; 1939 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 1940 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 1941 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 1942 return false; 1943 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 1944 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 1945 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 1946 return false; 1947 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 1948 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 1949 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 1950 return false; 1951 1952 return true; 1953 } 1954 1955 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 1956 struct seq_file *m, u32 sel) 1957 { 1958 const struct rtw89_mac_dbg_port_info *info; 1959 u8 val8; 1960 u16 val16; 1961 u32 val32; 1962 u32 i; 1963 1964 info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel); 1965 if (!info) { 1966 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 1967 return -EINVAL; 1968 } 1969 1970 #define case_DBG_SEL(__sel) \ 1971 case RTW89_DBG_PORT_SEL_##__sel: \ 1972 seq_puts(m, "Dump debug port " #__sel ":\n"); \ 1973 break 1974 1975 switch (sel) { 1976 case_DBG_SEL(PTCL_C0); 1977 case_DBG_SEL(PTCL_C1); 1978 case_DBG_SEL(SCH_C0); 1979 case_DBG_SEL(SCH_C1); 1980 case_DBG_SEL(TMAC_C0); 1981 case_DBG_SEL(TMAC_C1); 1982 case_DBG_SEL(RMAC_C0); 1983 case_DBG_SEL(RMAC_C1); 1984 case_DBG_SEL(RMACST_C0); 1985 case_DBG_SEL(RMACST_C1); 1986 case_DBG_SEL(TRXPTCL_C0); 1987 case_DBG_SEL(TRXPTCL_C1); 1988 case_DBG_SEL(TX_INFOL_C0); 1989 case_DBG_SEL(TX_INFOH_C0); 1990 case_DBG_SEL(TX_INFOL_C1); 1991 case_DBG_SEL(TX_INFOH_C1); 1992 case_DBG_SEL(TXTF_INFOL_C0); 1993 case_DBG_SEL(TXTF_INFOH_C0); 1994 case_DBG_SEL(TXTF_INFOL_C1); 1995 case_DBG_SEL(TXTF_INFOH_C1); 1996 case_DBG_SEL(WDE_BUFMGN_FREEPG); 1997 case_DBG_SEL(WDE_BUFMGN_QUOTA); 1998 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 1999 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 2000 case_DBG_SEL(WDE_QUEMGN_PREPKT); 2001 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 2002 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 2003 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 2004 case_DBG_SEL(PLE_BUFMGN_FREEPG); 2005 case_DBG_SEL(PLE_BUFMGN_QUOTA); 2006 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 2007 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 2008 case_DBG_SEL(PLE_QUEMGN_PREPKT); 2009 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 2010 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 2011 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 2012 case_DBG_SEL(PKTINFO); 2013 case_DBG_SEL(PCIE_TXDMA); 2014 case_DBG_SEL(PCIE_RXDMA); 2015 case_DBG_SEL(PCIE_CVT); 2016 case_DBG_SEL(PCIE_CXPL); 2017 case_DBG_SEL(PCIE_IO); 2018 case_DBG_SEL(PCIE_MISC); 2019 case_DBG_SEL(PCIE_MISC2); 2020 } 2021 2022 #undef case_DBG_SEL 2023 2024 seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr); 2025 seq_printf(m, "Read addr = 0x%X\n", info->rd_addr); 2026 2027 for (i = info->srt; i <= info->end; i++) { 2028 switch (info->sel_byte) { 2029 case 1: 2030 default: 2031 rtw89_write8_mask(rtwdev, info->sel_addr, 2032 info->sel_msk, i); 2033 seq_printf(m, "0x%02X: ", i); 2034 break; 2035 case 2: 2036 rtw89_write16_mask(rtwdev, info->sel_addr, 2037 info->sel_msk, i); 2038 seq_printf(m, "0x%04X: ", i); 2039 break; 2040 case 4: 2041 rtw89_write32_mask(rtwdev, info->sel_addr, 2042 info->sel_msk, i); 2043 seq_printf(m, "0x%04X: ", i); 2044 break; 2045 } 2046 2047 udelay(10); 2048 2049 switch (info->rd_byte) { 2050 case 1: 2051 default: 2052 val8 = rtw89_read8_mask(rtwdev, 2053 info->rd_addr, info->rd_msk); 2054 seq_printf(m, "0x%02X\n", val8); 2055 break; 2056 case 2: 2057 val16 = rtw89_read16_mask(rtwdev, 2058 info->rd_addr, info->rd_msk); 2059 seq_printf(m, "0x%04X\n", val16); 2060 break; 2061 case 4: 2062 val32 = rtw89_read32_mask(rtwdev, 2063 info->rd_addr, info->rd_msk); 2064 seq_printf(m, "0x%08X\n", val32); 2065 break; 2066 } 2067 } 2068 2069 return 0; 2070 } 2071 2072 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 2073 struct seq_file *m) 2074 { 2075 u32 sel; 2076 int ret = 0; 2077 2078 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 2079 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 2080 if (!is_dbg_port_valid(rtwdev, sel)) 2081 continue; 2082 ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel); 2083 if (ret) { 2084 rtw89_err(rtwdev, 2085 "failed to dump debug port %d\n", sel); 2086 break; 2087 } 2088 } 2089 2090 return ret; 2091 } 2092 2093 static int 2094 rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v) 2095 { 2096 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2097 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2098 2099 if (debugfs_priv->dbgpkg_en.ss_dbg) 2100 rtw89_debug_mac_dump_ss_dbg(rtwdev, m); 2101 if (debugfs_priv->dbgpkg_en.dle_dbg) 2102 rtw89_debug_mac_dump_dle_dbg(rtwdev, m); 2103 if (debugfs_priv->dbgpkg_en.dmac_dbg) 2104 rtw89_debug_mac_dump_dmac_dbg(rtwdev, m); 2105 if (debugfs_priv->dbgpkg_en.cmac_dbg) 2106 rtw89_debug_mac_dump_cmac_dbg(rtwdev, m); 2107 if (debugfs_priv->dbgpkg_en.dbg_port) 2108 rtw89_debug_mac_dump_dbg_port(rtwdev, m); 2109 2110 return 0; 2111 }; 2112 2113 static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev, 2114 const char __user *user_buf, size_t count) 2115 { 2116 char *buf; 2117 u8 *bin; 2118 int num; 2119 int err = 0; 2120 2121 buf = memdup_user(user_buf, count); 2122 if (IS_ERR(buf)) 2123 return buf; 2124 2125 num = count / 2; 2126 bin = kmalloc(num, GFP_KERNEL); 2127 if (!bin) { 2128 err = -EFAULT; 2129 goto out; 2130 } 2131 2132 if (hex2bin(bin, buf, num)) { 2133 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 2134 kfree(bin); 2135 err = -EINVAL; 2136 } 2137 2138 out: 2139 kfree(buf); 2140 2141 return err ? ERR_PTR(err) : bin; 2142 } 2143 2144 static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp, 2145 const char __user *user_buf, 2146 size_t count, loff_t *loff) 2147 { 2148 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 2149 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2150 u8 *h2c; 2151 u16 h2c_len = count / 2; 2152 2153 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 2154 if (IS_ERR(h2c)) 2155 return -EFAULT; 2156 2157 rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 2158 2159 kfree(h2c); 2160 2161 return count; 2162 } 2163 2164 static int 2165 rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v) 2166 { 2167 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2168 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2169 struct rtw89_early_h2c *early_h2c; 2170 int seq = 0; 2171 2172 mutex_lock(&rtwdev->mutex); 2173 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 2174 seq_printf(m, "%d: %*ph\n", ++seq, early_h2c->h2c_len, early_h2c->h2c); 2175 mutex_unlock(&rtwdev->mutex); 2176 2177 return 0; 2178 } 2179 2180 static ssize_t 2181 rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf, 2182 size_t count, loff_t *loff) 2183 { 2184 struct seq_file *m = (struct seq_file *)filp->private_data; 2185 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2186 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2187 struct rtw89_early_h2c *early_h2c; 2188 u8 *h2c; 2189 u16 h2c_len = count / 2; 2190 2191 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 2192 if (IS_ERR(h2c)) 2193 return -EFAULT; 2194 2195 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 2196 kfree(h2c); 2197 rtw89_fw_free_all_early_h2c(rtwdev); 2198 goto out; 2199 } 2200 2201 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL); 2202 if (!early_h2c) { 2203 kfree(h2c); 2204 return -EFAULT; 2205 } 2206 2207 early_h2c->h2c = h2c; 2208 early_h2c->h2c_len = h2c_len; 2209 2210 mutex_lock(&rtwdev->mutex); 2211 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 2212 mutex_unlock(&rtwdev->mutex); 2213 2214 out: 2215 return count; 2216 } 2217 2218 static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev) 2219 { 2220 struct rtw89_cpuio_ctrl ctrl_para = {0}; 2221 u16 pkt_id; 2222 2223 rtw89_leave_ps_mode(rtwdev); 2224 2225 pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, true); 2226 switch (pkt_id) { 2227 case 0xffff: 2228 return -ETIMEDOUT; 2229 case 0xfff: 2230 return -ENOMEM; 2231 default: 2232 break; 2233 } 2234 2235 /* intentionally, enqueue two pkt, but has only one pkt id */ 2236 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 2237 ctrl_para.start_pktid = pkt_id; 2238 ctrl_para.end_pktid = pkt_id; 2239 ctrl_para.pkt_num = 1; /* start from 0 */ 2240 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 2241 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 2242 2243 if (rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true)) 2244 return -EFAULT; 2245 2246 return 0; 2247 } 2248 2249 static int 2250 rtw89_debug_priv_fw_crash_get(struct seq_file *m, void *v) 2251 { 2252 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2253 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2254 2255 seq_printf(m, "%d\n", 2256 test_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags)); 2257 return 0; 2258 } 2259 2260 enum rtw89_dbg_crash_simulation_type { 2261 RTW89_DBG_SIM_CPU_EXCEPTION = 1, 2262 RTW89_DBG_SIM_CTRL_ERROR = 2, 2263 }; 2264 2265 static ssize_t 2266 rtw89_debug_priv_fw_crash_set(struct file *filp, const char __user *user_buf, 2267 size_t count, loff_t *loff) 2268 { 2269 struct seq_file *m = (struct seq_file *)filp->private_data; 2270 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2271 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2272 int (*sim)(struct rtw89_dev *rtwdev); 2273 u8 crash_type; 2274 int ret; 2275 2276 ret = kstrtou8_from_user(user_buf, count, 0, &crash_type); 2277 if (ret) 2278 return -EINVAL; 2279 2280 switch (crash_type) { 2281 case RTW89_DBG_SIM_CPU_EXCEPTION: 2282 if (!RTW89_CHK_FW_FEATURE(CRASH_TRIGGER, &rtwdev->fw)) 2283 return -EOPNOTSUPP; 2284 sim = rtw89_fw_h2c_trigger_cpu_exception; 2285 break; 2286 case RTW89_DBG_SIM_CTRL_ERROR: 2287 sim = rtw89_dbg_trigger_ctrl_error; 2288 break; 2289 default: 2290 return -EINVAL; 2291 } 2292 2293 mutex_lock(&rtwdev->mutex); 2294 set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags); 2295 ret = sim(rtwdev); 2296 mutex_unlock(&rtwdev->mutex); 2297 2298 if (ret) 2299 return ret; 2300 2301 return count; 2302 } 2303 2304 static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v) 2305 { 2306 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2307 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2308 2309 rtw89_btc_dump_info(rtwdev, m); 2310 2311 return 0; 2312 } 2313 2314 static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp, 2315 const char __user *user_buf, 2316 size_t count, loff_t *loff) 2317 { 2318 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 2319 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2320 struct rtw89_btc *btc = &rtwdev->btc; 2321 bool btc_manual; 2322 2323 if (kstrtobool_from_user(user_buf, count, &btc_manual)) 2324 goto out; 2325 2326 btc->ctrl.manual = btc_manual; 2327 out: 2328 return count; 2329 } 2330 2331 static ssize_t rtw89_debug_fw_log_btc_manual_set(struct file *filp, 2332 const char __user *user_buf, 2333 size_t count, loff_t *loff) 2334 { 2335 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 2336 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2337 struct rtw89_fw_info *fw_info = &rtwdev->fw; 2338 bool fw_log_manual; 2339 2340 if (kstrtobool_from_user(user_buf, count, &fw_log_manual)) 2341 goto out; 2342 2343 mutex_lock(&rtwdev->mutex); 2344 fw_info->fw_log_enable = fw_log_manual; 2345 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 2346 mutex_unlock(&rtwdev->mutex); 2347 out: 2348 return count; 2349 } 2350 2351 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 2352 { 2353 static const char * const he_gi_str[] = { 2354 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 2355 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 2356 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 2357 }; 2358 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2359 struct rate_info *rate = &rtwsta->ra_report.txrate; 2360 struct ieee80211_rx_status *status = &rtwsta->rx_status; 2361 struct seq_file *m = (struct seq_file *)data; 2362 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 2363 struct rtw89_hal *hal = &rtwdev->hal; 2364 u8 rssi; 2365 int i; 2366 2367 seq_printf(m, "TX rate [%d]: ", rtwsta->mac_id); 2368 2369 if (rate->flags & RATE_INFO_FLAGS_MCS) 2370 seq_printf(m, "HT MCS-%d%s", rate->mcs, 2371 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 2372 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 2373 seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs, 2374 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 2375 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 2376 seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs, 2377 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 2378 he_gi_str[rate->he_gi] : "N/A"); 2379 else 2380 seq_printf(m, "Legacy %d", rate->legacy); 2381 seq_printf(m, "%s", rtwsta->ra_report.might_fallback_legacy ? " FB_G" : ""); 2382 seq_printf(m, "\t(hw_rate=0x%x)", rtwsta->ra_report.hw_rate); 2383 seq_printf(m, "\t==> agg_wait=%d (%d)\n", rtwsta->max_agg_wait, 2384 sta->deflink.agg.max_rc_amsdu_len); 2385 2386 seq_printf(m, "RX rate [%d]: ", rtwsta->mac_id); 2387 2388 switch (status->encoding) { 2389 case RX_ENC_LEGACY: 2390 seq_printf(m, "Legacy %d", status->rate_idx + 2391 (status->band != NL80211_BAND_2GHZ ? 4 : 0)); 2392 break; 2393 case RX_ENC_HT: 2394 seq_printf(m, "HT MCS-%d%s", status->rate_idx, 2395 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 2396 break; 2397 case RX_ENC_VHT: 2398 seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx, 2399 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 2400 break; 2401 case RX_ENC_HE: 2402 seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx, 2403 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 2404 he_gi_str[rate->he_gi] : "N/A"); 2405 break; 2406 } 2407 seq_printf(m, "\t(hw_rate=0x%x)\n", rtwsta->rx_hw_rate); 2408 2409 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 2410 seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d) [", 2411 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta->prev_rssi); 2412 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 2413 rssi = ewma_rssi_read(&rtwsta->rssi[i]); 2414 seq_printf(m, "%d%s%s", RTW89_RSSI_RAW_TO_DBM(rssi), 2415 hal->tx_path_diversity && (hal->antenna_tx & BIT(i)) ? "*" : "", 2416 i + 1 == rtwdev->chip->rf_path_num ? "" : ", "); 2417 } 2418 seq_puts(m, "]\n"); 2419 } 2420 2421 static void 2422 rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat, 2423 enum rtw89_hw_rate first_rate, int len) 2424 { 2425 int i; 2426 2427 for (i = 0; i < len; i++) 2428 seq_printf(m, "%s%u", i == 0 ? "" : ", ", 2429 pkt_stat->rx_rate_cnt[first_rate + i]); 2430 } 2431 2432 static const struct rtw89_rx_rate_cnt_info { 2433 enum rtw89_hw_rate first_rate; 2434 int len; 2435 int ext; 2436 const char *rate_mode; 2437 } rtw89_rx_rate_cnt_infos[] = { 2438 {RTW89_HW_RATE_CCK1, 4, 0, "Legacy:"}, 2439 {RTW89_HW_RATE_OFDM6, 8, 0, "OFDM:"}, 2440 {RTW89_HW_RATE_MCS0, 8, 0, "HT 0:"}, 2441 {RTW89_HW_RATE_MCS8, 8, 0, "HT 1:"}, 2442 {RTW89_HW_RATE_VHT_NSS1_MCS0, 10, 2, "VHT 1SS:"}, 2443 {RTW89_HW_RATE_VHT_NSS2_MCS0, 10, 2, "VHT 2SS:"}, 2444 {RTW89_HW_RATE_HE_NSS1_MCS0, 12, 0, "HE 1SS:"}, 2445 {RTW89_HW_RATE_HE_NSS2_MCS0, 12, 0, "HE 2ss:"}, 2446 }; 2447 2448 static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v) 2449 { 2450 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2451 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2452 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2453 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 2454 const struct rtw89_rx_rate_cnt_info *info; 2455 int i; 2456 2457 seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d), RX: %u [%u] Mbps (lv: %d)\n", 2458 stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv, 2459 stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv); 2460 seq_printf(m, "Beacon: %u, TF: %u\n", pkt_stat->beacon_nr, 2461 stats->rx_tf_periodic); 2462 seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len, 2463 stats->rx_avg_len); 2464 2465 seq_puts(m, "RX count:\n"); 2466 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 2467 info = &rtw89_rx_rate_cnt_infos[i]; 2468 seq_printf(m, "%10s [", info->rate_mode); 2469 rtw89_debug_append_rx_rate(m, pkt_stat, 2470 info->first_rate, info->len); 2471 if (info->ext) { 2472 seq_puts(m, "]["); 2473 rtw89_debug_append_rx_rate(m, pkt_stat, 2474 info->first_rate + info->len, info->ext); 2475 } 2476 seq_puts(m, "]\n"); 2477 } 2478 2479 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m); 2480 2481 return 0; 2482 } 2483 2484 static void rtw89_dump_addr_cam(struct seq_file *m, 2485 struct rtw89_addr_cam_entry *addr_cam) 2486 { 2487 struct rtw89_sec_cam_entry *sec_entry; 2488 int i; 2489 2490 seq_printf(m, "\taddr_cam_idx=%u\n", addr_cam->addr_cam_idx); 2491 seq_printf(m, "\t-> bssid_cam_idx=%u\n", addr_cam->bssid_cam_idx); 2492 seq_printf(m, "\tsec_cam_bitmap=%*ph\n", (int)sizeof(addr_cam->sec_cam_map), 2493 addr_cam->sec_cam_map); 2494 for (i = 0; i < RTW89_SEC_CAM_IN_ADDR_CAM; i++) { 2495 sec_entry = addr_cam->sec_entries[i]; 2496 if (!sec_entry) 2497 continue; 2498 seq_printf(m, "\tsec[%d]: sec_cam_idx %u", i, sec_entry->sec_cam_idx); 2499 if (sec_entry->ext_key) 2500 seq_printf(m, ", %u", sec_entry->sec_cam_idx + 1); 2501 seq_puts(m, "\n"); 2502 } 2503 } 2504 2505 static 2506 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 2507 { 2508 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2509 struct seq_file *m = (struct seq_file *)data; 2510 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam; 2511 2512 seq_printf(m, "VIF [%d] %pM\n", rtwvif->mac_id, rtwvif->mac_addr); 2513 seq_printf(m, "\tbssid_cam_idx=%u\n", bssid_cam->bssid_cam_idx); 2514 rtw89_dump_addr_cam(m, &rtwvif->addr_cam); 2515 } 2516 2517 static void rtw89_dump_ba_cam(struct seq_file *m, struct rtw89_sta *rtwsta) 2518 { 2519 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 2520 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 2521 struct rtw89_ba_cam_entry *entry; 2522 bool first = true; 2523 2524 list_for_each_entry(entry, &rtwsta->ba_cam_list, list) { 2525 if (first) { 2526 seq_puts(m, "\tba_cam "); 2527 first = false; 2528 } else { 2529 seq_puts(m, ", "); 2530 } 2531 seq_printf(m, "tid[%u]=%d", entry->tid, 2532 (int)(entry - rtwdev->cam_info.ba_cam_entry)); 2533 } 2534 seq_puts(m, "\n"); 2535 } 2536 2537 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta) 2538 { 2539 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2540 struct seq_file *m = (struct seq_file *)data; 2541 2542 seq_printf(m, "STA [%d] %pM %s\n", rtwsta->mac_id, sta->addr, 2543 sta->tdls ? "(TDLS)" : ""); 2544 rtw89_dump_addr_cam(m, &rtwsta->addr_cam); 2545 rtw89_dump_ba_cam(m, rtwsta); 2546 } 2547 2548 static int rtw89_debug_priv_stations_get(struct seq_file *m, void *v) 2549 { 2550 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2551 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2552 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 2553 2554 mutex_lock(&rtwdev->mutex); 2555 2556 seq_puts(m, "map:\n"); 2557 seq_printf(m, "\tmac_id: %*ph\n", (int)sizeof(rtwdev->mac_id_map), 2558 rtwdev->mac_id_map); 2559 seq_printf(m, "\taddr_cam: %*ph\n", (int)sizeof(cam_info->addr_cam_map), 2560 cam_info->addr_cam_map); 2561 seq_printf(m, "\tbssid_cam: %*ph\n", (int)sizeof(cam_info->bssid_cam_map), 2562 cam_info->bssid_cam_map); 2563 seq_printf(m, "\tsec_cam: %*ph\n", (int)sizeof(cam_info->sec_cam_map), 2564 cam_info->sec_cam_map); 2565 seq_printf(m, "\tba_cam: %*ph\n", (int)sizeof(cam_info->ba_cam_map), 2566 cam_info->ba_cam_map); 2567 2568 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw, 2569 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, m); 2570 2571 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, m); 2572 2573 mutex_unlock(&rtwdev->mutex); 2574 2575 return 0; 2576 } 2577 2578 static struct rtw89_debugfs_priv rtw89_debug_priv_read_reg = { 2579 .cb_read = rtw89_debug_priv_read_reg_get, 2580 .cb_write = rtw89_debug_priv_read_reg_select, 2581 }; 2582 2583 static struct rtw89_debugfs_priv rtw89_debug_priv_write_reg = { 2584 .cb_write = rtw89_debug_priv_write_reg_set, 2585 }; 2586 2587 static struct rtw89_debugfs_priv rtw89_debug_priv_read_rf = { 2588 .cb_read = rtw89_debug_priv_read_rf_get, 2589 .cb_write = rtw89_debug_priv_read_rf_select, 2590 }; 2591 2592 static struct rtw89_debugfs_priv rtw89_debug_priv_write_rf = { 2593 .cb_write = rtw89_debug_priv_write_rf_set, 2594 }; 2595 2596 static struct rtw89_debugfs_priv rtw89_debug_priv_rf_reg_dump = { 2597 .cb_read = rtw89_debug_priv_rf_reg_dump_get, 2598 }; 2599 2600 static struct rtw89_debugfs_priv rtw89_debug_priv_txpwr_table = { 2601 .cb_read = rtw89_debug_priv_txpwr_table_get, 2602 }; 2603 2604 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_reg_dump = { 2605 .cb_read = rtw89_debug_priv_mac_reg_dump_get, 2606 .cb_write = rtw89_debug_priv_mac_reg_dump_select, 2607 }; 2608 2609 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_mem_dump = { 2610 .cb_read = rtw89_debug_priv_mac_mem_dump_get, 2611 .cb_write = rtw89_debug_priv_mac_mem_dump_select, 2612 }; 2613 2614 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_dbg_port_dump = { 2615 .cb_read = rtw89_debug_priv_mac_dbg_port_dump_get, 2616 .cb_write = rtw89_debug_priv_mac_dbg_port_dump_select, 2617 }; 2618 2619 static struct rtw89_debugfs_priv rtw89_debug_priv_send_h2c = { 2620 .cb_write = rtw89_debug_priv_send_h2c_set, 2621 }; 2622 2623 static struct rtw89_debugfs_priv rtw89_debug_priv_early_h2c = { 2624 .cb_read = rtw89_debug_priv_early_h2c_get, 2625 .cb_write = rtw89_debug_priv_early_h2c_set, 2626 }; 2627 2628 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_crash = { 2629 .cb_read = rtw89_debug_priv_fw_crash_get, 2630 .cb_write = rtw89_debug_priv_fw_crash_set, 2631 }; 2632 2633 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_info = { 2634 .cb_read = rtw89_debug_priv_btc_info_get, 2635 }; 2636 2637 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_manual = { 2638 .cb_write = rtw89_debug_priv_btc_manual_set, 2639 }; 2640 2641 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_log_manual = { 2642 .cb_write = rtw89_debug_fw_log_btc_manual_set, 2643 }; 2644 2645 static struct rtw89_debugfs_priv rtw89_debug_priv_phy_info = { 2646 .cb_read = rtw89_debug_priv_phy_info_get, 2647 }; 2648 2649 static struct rtw89_debugfs_priv rtw89_debug_priv_stations = { 2650 .cb_read = rtw89_debug_priv_stations_get, 2651 }; 2652 2653 #define rtw89_debugfs_add(name, mode, fopname, parent) \ 2654 do { \ 2655 rtw89_debug_priv_ ##name.rtwdev = rtwdev; \ 2656 if (!debugfs_create_file(#name, mode, \ 2657 parent, &rtw89_debug_priv_ ##name, \ 2658 &file_ops_ ##fopname)) \ 2659 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 2660 } while (0) 2661 2662 #define rtw89_debugfs_add_w(name) \ 2663 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 2664 #define rtw89_debugfs_add_rw(name) \ 2665 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 2666 #define rtw89_debugfs_add_r(name) \ 2667 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 2668 2669 void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 2670 { 2671 struct dentry *debugfs_topdir; 2672 2673 debugfs_topdir = debugfs_create_dir("rtw89", 2674 rtwdev->hw->wiphy->debugfsdir); 2675 2676 rtw89_debugfs_add_rw(read_reg); 2677 rtw89_debugfs_add_w(write_reg); 2678 rtw89_debugfs_add_rw(read_rf); 2679 rtw89_debugfs_add_w(write_rf); 2680 rtw89_debugfs_add_r(rf_reg_dump); 2681 rtw89_debugfs_add_r(txpwr_table); 2682 rtw89_debugfs_add_rw(mac_reg_dump); 2683 rtw89_debugfs_add_rw(mac_mem_dump); 2684 rtw89_debugfs_add_rw(mac_dbg_port_dump); 2685 rtw89_debugfs_add_w(send_h2c); 2686 rtw89_debugfs_add_rw(early_h2c); 2687 rtw89_debugfs_add_rw(fw_crash); 2688 rtw89_debugfs_add_r(btc_info); 2689 rtw89_debugfs_add_w(btc_manual); 2690 rtw89_debugfs_add_w(fw_log_manual); 2691 rtw89_debugfs_add_r(phy_info); 2692 rtw89_debugfs_add_r(stations); 2693 } 2694 #endif 2695 2696 #ifdef CONFIG_RTW89_DEBUGMSG 2697 void __rtw89_debug(struct rtw89_dev *rtwdev, 2698 enum rtw89_debug_mask mask, 2699 const char *fmt, ...) 2700 { 2701 struct va_format vaf = { 2702 .fmt = fmt, 2703 }; 2704 2705 va_list args; 2706 2707 va_start(args, fmt); 2708 vaf.va = &args; 2709 2710 if (rtw89_debug_mask & mask) 2711 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 2712 2713 va_end(args); 2714 } 2715 EXPORT_SYMBOL(__rtw89_debug); 2716 #endif 2717