1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include <linux/vmalloc.h> 6 7 #include "coex.h" 8 #include "debug.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "ps.h" 13 #include "reg.h" 14 #include "sar.h" 15 16 #ifdef CONFIG_RTW89_DEBUGMSG 17 unsigned int rtw89_debug_mask; 18 EXPORT_SYMBOL(rtw89_debug_mask); 19 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 20 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 21 #endif 22 23 #ifdef CONFIG_RTW89_DEBUGFS 24 struct rtw89_debugfs_priv { 25 struct rtw89_dev *rtwdev; 26 int (*cb_read)(struct seq_file *m, void *v); 27 ssize_t (*cb_write)(struct file *filp, const char __user *buffer, 28 size_t count, loff_t *loff); 29 union { 30 u32 cb_data; 31 struct { 32 u32 addr; 33 u8 len; 34 } read_reg; 35 struct { 36 u32 addr; 37 u32 mask; 38 u8 path; 39 } read_rf; 40 struct { 41 u8 ss_dbg:1; 42 u8 dle_dbg:1; 43 u8 dmac_dbg:1; 44 u8 cmac_dbg:1; 45 u8 dbg_port:1; 46 } dbgpkg_en; 47 struct { 48 u32 start; 49 u32 len; 50 u8 sel; 51 } mac_mem; 52 }; 53 }; 54 55 static const u16 rtw89_rate_info_bw_to_mhz_map[] = { 56 [RATE_INFO_BW_20] = 20, 57 [RATE_INFO_BW_40] = 40, 58 [RATE_INFO_BW_80] = 80, 59 [RATE_INFO_BW_160] = 160, 60 [RATE_INFO_BW_320] = 320, 61 }; 62 63 static u16 rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw) 64 { 65 if (bw < ARRAY_SIZE(rtw89_rate_info_bw_to_mhz_map)) 66 return rtw89_rate_info_bw_to_mhz_map[bw]; 67 68 return 0; 69 } 70 71 static int rtw89_debugfs_single_show(struct seq_file *m, void *v) 72 { 73 struct rtw89_debugfs_priv *debugfs_priv = m->private; 74 75 return debugfs_priv->cb_read(m, v); 76 } 77 78 static ssize_t rtw89_debugfs_single_write(struct file *filp, 79 const char __user *buffer, 80 size_t count, loff_t *loff) 81 { 82 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 83 84 return debugfs_priv->cb_write(filp, buffer, count, loff); 85 } 86 87 static ssize_t rtw89_debugfs_seq_file_write(struct file *filp, 88 const char __user *buffer, 89 size_t count, loff_t *loff) 90 { 91 struct seq_file *seqpriv = (struct seq_file *)filp->private_data; 92 struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private; 93 94 return debugfs_priv->cb_write(filp, buffer, count, loff); 95 } 96 97 static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp) 98 { 99 return single_open(filp, rtw89_debugfs_single_show, inode->i_private); 100 } 101 102 static int rtw89_debugfs_close(struct inode *inode, struct file *filp) 103 { 104 return 0; 105 } 106 107 static const struct file_operations file_ops_single_r = { 108 .owner = THIS_MODULE, 109 .open = rtw89_debugfs_single_open, 110 .read = seq_read, 111 .llseek = seq_lseek, 112 .release = single_release, 113 }; 114 115 static const struct file_operations file_ops_common_rw = { 116 .owner = THIS_MODULE, 117 .open = rtw89_debugfs_single_open, 118 .release = single_release, 119 .read = seq_read, 120 .llseek = seq_lseek, 121 .write = rtw89_debugfs_seq_file_write, 122 }; 123 124 static const struct file_operations file_ops_single_w = { 125 .owner = THIS_MODULE, 126 .write = rtw89_debugfs_single_write, 127 .open = simple_open, 128 .release = rtw89_debugfs_close, 129 }; 130 131 static ssize_t 132 rtw89_debug_priv_read_reg_select(struct file *filp, 133 const char __user *user_buf, 134 size_t count, loff_t *loff) 135 { 136 struct seq_file *m = (struct seq_file *)filp->private_data; 137 struct rtw89_debugfs_priv *debugfs_priv = m->private; 138 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 139 char buf[32]; 140 size_t buf_size; 141 u32 addr, len; 142 int num; 143 144 buf_size = min(count, sizeof(buf) - 1); 145 if (copy_from_user(buf, user_buf, buf_size)) 146 return -EFAULT; 147 148 buf[buf_size] = '\0'; 149 num = sscanf(buf, "%x %x", &addr, &len); 150 if (num != 2) { 151 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 152 return -EINVAL; 153 } 154 155 debugfs_priv->read_reg.addr = addr; 156 debugfs_priv->read_reg.len = len; 157 158 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 159 160 return count; 161 } 162 163 static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v) 164 { 165 struct rtw89_debugfs_priv *debugfs_priv = m->private; 166 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 167 u32 addr, data; 168 u8 len; 169 170 len = debugfs_priv->read_reg.len; 171 addr = debugfs_priv->read_reg.addr; 172 173 switch (len) { 174 case 1: 175 data = rtw89_read8(rtwdev, addr); 176 break; 177 case 2: 178 data = rtw89_read16(rtwdev, addr); 179 break; 180 case 4: 181 data = rtw89_read32(rtwdev, addr); 182 break; 183 default: 184 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 185 return -EINVAL; 186 } 187 188 seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data); 189 190 return 0; 191 } 192 193 static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp, 194 const char __user *user_buf, 195 size_t count, loff_t *loff) 196 { 197 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 198 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 199 char buf[32]; 200 size_t buf_size; 201 u32 addr, val, len; 202 int num; 203 204 buf_size = min(count, sizeof(buf) - 1); 205 if (copy_from_user(buf, user_buf, buf_size)) 206 return -EFAULT; 207 208 buf[buf_size] = '\0'; 209 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 210 if (num != 3) { 211 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 212 return -EINVAL; 213 } 214 215 switch (len) { 216 case 1: 217 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 218 rtw89_write8(rtwdev, addr, (u8)val); 219 break; 220 case 2: 221 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 222 rtw89_write16(rtwdev, addr, (u16)val); 223 break; 224 case 4: 225 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 226 rtw89_write32(rtwdev, addr, (u32)val); 227 break; 228 default: 229 rtw89_info(rtwdev, "invalid read write len %d\n", len); 230 break; 231 } 232 233 return count; 234 } 235 236 static ssize_t 237 rtw89_debug_priv_read_rf_select(struct file *filp, 238 const char __user *user_buf, 239 size_t count, loff_t *loff) 240 { 241 struct seq_file *m = (struct seq_file *)filp->private_data; 242 struct rtw89_debugfs_priv *debugfs_priv = m->private; 243 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 244 char buf[32]; 245 size_t buf_size; 246 u32 addr, mask; 247 u8 path; 248 int num; 249 250 buf_size = min(count, sizeof(buf) - 1); 251 if (copy_from_user(buf, user_buf, buf_size)) 252 return -EFAULT; 253 254 buf[buf_size] = '\0'; 255 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 256 if (num != 3) { 257 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 258 return -EINVAL; 259 } 260 261 if (path >= rtwdev->chip->rf_path_num) { 262 rtw89_info(rtwdev, "wrong rf path\n"); 263 return -EINVAL; 264 } 265 debugfs_priv->read_rf.addr = addr; 266 debugfs_priv->read_rf.mask = mask; 267 debugfs_priv->read_rf.path = path; 268 269 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 270 271 return count; 272 } 273 274 static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v) 275 { 276 struct rtw89_debugfs_priv *debugfs_priv = m->private; 277 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 278 u32 addr, data, mask; 279 u8 path; 280 281 addr = debugfs_priv->read_rf.addr; 282 mask = debugfs_priv->read_rf.mask; 283 path = debugfs_priv->read_rf.path; 284 285 data = rtw89_read_rf(rtwdev, path, addr, mask); 286 287 seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data); 288 289 return 0; 290 } 291 292 static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp, 293 const char __user *user_buf, 294 size_t count, loff_t *loff) 295 { 296 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 297 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 298 char buf[32]; 299 size_t buf_size; 300 u32 addr, val, mask; 301 u8 path; 302 int num; 303 304 buf_size = min(count, sizeof(buf) - 1); 305 if (copy_from_user(buf, user_buf, buf_size)) 306 return -EFAULT; 307 308 buf[buf_size] = '\0'; 309 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 310 if (num != 4) { 311 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 312 return -EINVAL; 313 } 314 315 if (path >= rtwdev->chip->rf_path_num) { 316 rtw89_info(rtwdev, "wrong rf path\n"); 317 return -EINVAL; 318 } 319 320 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 321 path, addr, val, mask); 322 rtw89_write_rf(rtwdev, path, addr, mask, val); 323 324 return count; 325 } 326 327 static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v) 328 { 329 struct rtw89_debugfs_priv *debugfs_priv = m->private; 330 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 331 const struct rtw89_chip_info *chip = rtwdev->chip; 332 u32 addr, offset, data; 333 u8 path; 334 335 for (path = 0; path < chip->rf_path_num; path++) { 336 seq_printf(m, "RF path %d:\n\n", path); 337 for (addr = 0; addr < 0x100; addr += 4) { 338 seq_printf(m, "0x%08x: ", addr); 339 for (offset = 0; offset < 4; offset++) { 340 data = rtw89_read_rf(rtwdev, path, 341 addr + offset, RFREG_MASK); 342 seq_printf(m, "0x%05x ", data); 343 } 344 seq_puts(m, "\n"); 345 } 346 seq_puts(m, "\n"); 347 } 348 349 return 0; 350 } 351 352 struct txpwr_ent { 353 const char *txt; 354 u8 len; 355 }; 356 357 struct txpwr_map { 358 const struct txpwr_ent *ent; 359 u8 size; 360 u32 addr_from; 361 u32 addr_to; 362 }; 363 364 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 365 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 366 367 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 368 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 369 370 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 371 { .len = 8, .txt = _t "\t- " \ 372 _e0 " " _e1 " " _e2 " " _e3 " " \ 373 _e4 " " _e5 " " _e6 " " _e7 } 374 375 static const struct txpwr_ent __txpwr_ent_byr[] = { 376 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 377 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 378 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 379 /* 1NSS */ 380 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 381 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 382 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 383 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 384 /* 2NSS */ 385 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 386 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 387 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 388 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 389 }; 390 391 static_assert((ARRAY_SIZE(__txpwr_ent_byr) * 4) == 392 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 393 394 static const struct txpwr_map __txpwr_map_byr = { 395 .ent = __txpwr_ent_byr, 396 .size = ARRAY_SIZE(__txpwr_ent_byr), 397 .addr_from = R_AX_PWR_BY_RATE, 398 .addr_to = R_AX_PWR_BY_RATE_MAX, 399 }; 400 401 static const struct txpwr_ent __txpwr_ent_lmt[] = { 402 /* 1TX */ 403 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 404 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 405 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 406 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 407 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 408 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 409 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 410 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 411 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 412 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 413 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 414 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 415 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 416 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 417 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 418 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 419 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 420 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 421 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 422 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 423 /* 2TX */ 424 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 425 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 426 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 427 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 428 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 429 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 430 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 431 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 432 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 433 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 434 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 435 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 436 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 437 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 438 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 439 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 440 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 441 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 442 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 443 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 444 }; 445 446 static_assert((ARRAY_SIZE(__txpwr_ent_lmt) * 2) == 447 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 448 449 static const struct txpwr_map __txpwr_map_lmt = { 450 .ent = __txpwr_ent_lmt, 451 .size = ARRAY_SIZE(__txpwr_ent_lmt), 452 .addr_from = R_AX_PWR_LMT, 453 .addr_to = R_AX_PWR_LMT_MAX, 454 }; 455 456 static const struct txpwr_ent __txpwr_ent_lmt_ru[] = { 457 /* 1TX */ 458 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 459 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 460 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 461 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 462 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 463 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 464 /* 2TX */ 465 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 466 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 467 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 468 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 469 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 470 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 471 }; 472 473 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru) * 8) == 474 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 475 476 static const struct txpwr_map __txpwr_map_lmt_ru = { 477 .ent = __txpwr_ent_lmt_ru, 478 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru), 479 .addr_from = R_AX_PWR_RU_LMT, 480 .addr_to = R_AX_PWR_RU_LMT_MAX, 481 }; 482 483 static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent, 484 const s8 *buf, const u8 cur) 485 { 486 char *fmt; 487 488 switch (ent->len) { 489 case 2: 490 fmt = "%s\t| %3d, %3d,\tdBm\n"; 491 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]); 492 return 2; 493 case 4: 494 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 495 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 496 buf[cur + 2], buf[cur + 3]); 497 return 4; 498 case 8: 499 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 500 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 501 buf[cur + 2], buf[cur + 3], buf[cur + 4], 502 buf[cur + 5], buf[cur + 6], buf[cur + 7]); 503 return 8; 504 default: 505 return 0; 506 } 507 } 508 509 static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev, 510 const struct txpwr_map *map) 511 { 512 u8 fct = rtwdev->chip->txpwr_factor_mac; 513 u32 val, addr; 514 s8 *buf, tmp; 515 u8 cur, i; 516 int ret; 517 518 buf = vzalloc(map->addr_to - map->addr_from + 4); 519 if (!buf) 520 return -ENOMEM; 521 522 for (addr = map->addr_from; addr <= map->addr_to; addr += 4) { 523 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 524 if (ret) 525 val = MASKDWORD; 526 527 cur = addr - map->addr_from; 528 for (i = 0; i < 4; i++, val >>= 8) { 529 /* signed 7 bits, and reserved BIT(7) */ 530 tmp = sign_extend32(val, 6); 531 buf[cur + i] = tmp >> fct; 532 } 533 } 534 535 for (cur = 0, i = 0; i < map->size; i++) 536 cur += __print_txpwr_ent(m, &map->ent[i], buf, cur); 537 538 vfree(buf); 539 return 0; 540 } 541 542 #define case_REGD(_regd) \ 543 case RTW89_ ## _regd: \ 544 seq_puts(m, #_regd "\n"); \ 545 break 546 547 static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev) 548 { 549 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 550 u8 band = chan->band_type; 551 u8 regd = rtw89_regd_get(rtwdev, band); 552 553 switch (regd) { 554 default: 555 seq_printf(m, "UNKNOWN: %d\n", regd); 556 break; 557 case_REGD(WW); 558 case_REGD(ETSI); 559 case_REGD(FCC); 560 case_REGD(MKK); 561 case_REGD(NA); 562 case_REGD(IC); 563 case_REGD(KCC); 564 case_REGD(NCC); 565 case_REGD(CHILE); 566 case_REGD(ACMA); 567 case_REGD(MEXICO); 568 case_REGD(UKRAINE); 569 case_REGD(CN); 570 } 571 } 572 573 #undef case_REGD 574 575 static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v) 576 { 577 struct rtw89_debugfs_priv *debugfs_priv = m->private; 578 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 579 int ret = 0; 580 581 mutex_lock(&rtwdev->mutex); 582 rtw89_leave_ps_mode(rtwdev); 583 584 seq_puts(m, "[Regulatory] "); 585 __print_regd(m, rtwdev); 586 587 seq_puts(m, "[SAR]\n"); 588 rtw89_print_sar(m, rtwdev); 589 590 seq_puts(m, "\n[TX power byrate]\n"); 591 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_byr); 592 if (ret) 593 goto err; 594 595 seq_puts(m, "\n[TX power limit]\n"); 596 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt); 597 if (ret) 598 goto err; 599 600 seq_puts(m, "\n[TX power limit_ru]\n"); 601 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt_ru); 602 if (ret) 603 goto err; 604 605 err: 606 mutex_unlock(&rtwdev->mutex); 607 return ret; 608 } 609 610 static ssize_t 611 rtw89_debug_priv_mac_reg_dump_select(struct file *filp, 612 const char __user *user_buf, 613 size_t count, loff_t *loff) 614 { 615 struct seq_file *m = (struct seq_file *)filp->private_data; 616 struct rtw89_debugfs_priv *debugfs_priv = m->private; 617 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 618 char buf[32]; 619 size_t buf_size; 620 int sel; 621 int ret; 622 623 buf_size = min(count, sizeof(buf) - 1); 624 if (copy_from_user(buf, user_buf, buf_size)) 625 return -EFAULT; 626 627 buf[buf_size] = '\0'; 628 ret = kstrtoint(buf, 0, &sel); 629 if (ret) 630 return ret; 631 632 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 633 rtw89_info(rtwdev, "invalid args: %d\n", sel); 634 return -EINVAL; 635 } 636 637 debugfs_priv->cb_data = sel; 638 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 639 640 return count; 641 } 642 643 #define RTW89_MAC_PAGE_SIZE 0x100 644 645 static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v) 646 { 647 struct rtw89_debugfs_priv *debugfs_priv = m->private; 648 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 649 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 650 u32 start, end; 651 u32 i, j, k, page; 652 u32 val; 653 654 switch (reg_sel) { 655 case RTW89_DBG_SEL_MAC_00: 656 seq_puts(m, "Debug selected MAC page 0x00\n"); 657 start = 0x000; 658 end = 0x014; 659 break; 660 case RTW89_DBG_SEL_MAC_30: 661 seq_puts(m, "Debug selected MAC page 0x30\n"); 662 start = 0x030; 663 end = 0x033; 664 break; 665 case RTW89_DBG_SEL_MAC_40: 666 seq_puts(m, "Debug selected MAC page 0x40\n"); 667 start = 0x040; 668 end = 0x07f; 669 break; 670 case RTW89_DBG_SEL_MAC_80: 671 seq_puts(m, "Debug selected MAC page 0x80\n"); 672 start = 0x080; 673 end = 0x09f; 674 break; 675 case RTW89_DBG_SEL_MAC_C0: 676 seq_puts(m, "Debug selected MAC page 0xc0\n"); 677 start = 0x0c0; 678 end = 0x0df; 679 break; 680 case RTW89_DBG_SEL_MAC_E0: 681 seq_puts(m, "Debug selected MAC page 0xe0\n"); 682 start = 0x0e0; 683 end = 0x0ff; 684 break; 685 case RTW89_DBG_SEL_BB: 686 seq_puts(m, "Debug selected BB register\n"); 687 start = 0x100; 688 end = 0x17f; 689 break; 690 case RTW89_DBG_SEL_IQK: 691 seq_puts(m, "Debug selected IQK register\n"); 692 start = 0x180; 693 end = 0x1bf; 694 break; 695 case RTW89_DBG_SEL_RFC: 696 seq_puts(m, "Debug selected RFC register\n"); 697 start = 0x1c0; 698 end = 0x1ff; 699 break; 700 default: 701 seq_puts(m, "Selected invalid register page\n"); 702 return -EINVAL; 703 } 704 705 for (i = start; i <= end; i++) { 706 page = i << 8; 707 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 708 seq_printf(m, "%08xh : ", 0x18600000 + j); 709 for (k = 0; k < 4; k++) { 710 val = rtw89_read32(rtwdev, j + (k << 2)); 711 seq_printf(m, "%08x ", val); 712 } 713 seq_puts(m, "\n"); 714 } 715 } 716 717 return 0; 718 } 719 720 static ssize_t 721 rtw89_debug_priv_mac_mem_dump_select(struct file *filp, 722 const char __user *user_buf, 723 size_t count, loff_t *loff) 724 { 725 struct seq_file *m = (struct seq_file *)filp->private_data; 726 struct rtw89_debugfs_priv *debugfs_priv = m->private; 727 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 728 char buf[32]; 729 size_t buf_size; 730 u32 sel, start_addr, len; 731 int num; 732 733 buf_size = min(count, sizeof(buf) - 1); 734 if (copy_from_user(buf, user_buf, buf_size)) 735 return -EFAULT; 736 737 buf[buf_size] = '\0'; 738 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 739 if (num != 3) { 740 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 741 return -EINVAL; 742 } 743 744 debugfs_priv->mac_mem.sel = sel; 745 debugfs_priv->mac_mem.start = start_addr; 746 debugfs_priv->mac_mem.len = len; 747 748 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 749 sel, start_addr, len); 750 751 return count; 752 } 753 754 static void rtw89_debug_dump_mac_mem(struct seq_file *m, 755 struct rtw89_dev *rtwdev, 756 u8 sel, u32 start_addr, u32 len) 757 { 758 u32 base_addr, start_page, residue; 759 u32 i, j, p, pages; 760 u32 dump_len, remain; 761 u32 val; 762 763 remain = len; 764 pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1; 765 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE; 766 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE; 767 base_addr = rtw89_mac_mem_base_addrs[sel]; 768 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE; 769 770 for (p = 0; p < pages; p++) { 771 dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE); 772 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, base_addr); 773 for (i = R_AX_INDIR_ACCESS_ENTRY + residue; 774 i < R_AX_INDIR_ACCESS_ENTRY + dump_len;) { 775 seq_printf(m, "%08xh:", i); 776 for (j = 0; 777 j < 4 && i < R_AX_INDIR_ACCESS_ENTRY + dump_len; 778 j++, i += 4) { 779 val = rtw89_read32(rtwdev, i); 780 seq_printf(m, " %08x", val); 781 remain -= 4; 782 } 783 seq_puts(m, "\n"); 784 } 785 base_addr += MAC_MEM_DUMP_PAGE_SIZE; 786 } 787 } 788 789 static int 790 rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v) 791 { 792 struct rtw89_debugfs_priv *debugfs_priv = m->private; 793 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 794 bool grant_read = false; 795 796 if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM) 797 return -ENOENT; 798 799 if (rtwdev->chip->chip_id == RTL8852C) { 800 switch (debugfs_priv->mac_mem.sel) { 801 case RTW89_MAC_MEM_TXD_FIFO_0_V1: 802 case RTW89_MAC_MEM_TXD_FIFO_1_V1: 803 case RTW89_MAC_MEM_TXDATA_FIFO_0: 804 case RTW89_MAC_MEM_TXDATA_FIFO_1: 805 grant_read = true; 806 break; 807 default: 808 break; 809 } 810 } 811 812 mutex_lock(&rtwdev->mutex); 813 rtw89_leave_ps_mode(rtwdev); 814 if (grant_read) 815 rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 816 rtw89_debug_dump_mac_mem(m, rtwdev, 817 debugfs_priv->mac_mem.sel, 818 debugfs_priv->mac_mem.start, 819 debugfs_priv->mac_mem.len); 820 if (grant_read) 821 rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 822 mutex_unlock(&rtwdev->mutex); 823 824 return 0; 825 } 826 827 static ssize_t 828 rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp, 829 const char __user *user_buf, 830 size_t count, loff_t *loff) 831 { 832 struct seq_file *m = (struct seq_file *)filp->private_data; 833 struct rtw89_debugfs_priv *debugfs_priv = m->private; 834 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 835 char buf[32]; 836 size_t buf_size; 837 int sel, set; 838 int num; 839 bool enable; 840 841 buf_size = min(count, sizeof(buf) - 1); 842 if (copy_from_user(buf, user_buf, buf_size)) 843 return -EFAULT; 844 845 buf[buf_size] = '\0'; 846 num = sscanf(buf, "%d %d", &sel, &set); 847 if (num != 2) { 848 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 849 return -EINVAL; 850 } 851 852 enable = set != 0; 853 switch (sel) { 854 case 0: 855 debugfs_priv->dbgpkg_en.ss_dbg = enable; 856 break; 857 case 1: 858 debugfs_priv->dbgpkg_en.dle_dbg = enable; 859 break; 860 case 2: 861 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 862 break; 863 case 3: 864 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 865 break; 866 case 4: 867 debugfs_priv->dbgpkg_en.dbg_port = enable; 868 break; 869 default: 870 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 871 return -EINVAL; 872 } 873 874 rtw89_info(rtwdev, "%s debug port dump %d\n", 875 enable ? "Enable" : "Disable", sel); 876 877 return count; 878 } 879 880 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 881 struct seq_file *m) 882 { 883 return 0; 884 } 885 886 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 887 struct seq_file *m) 888 { 889 #define DLE_DFI_DUMP(__type, __target, __sel) \ 890 ({ \ 891 u32 __ctrl; \ 892 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 893 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 894 u32 __data, __val32; \ 895 int __ret; \ 896 \ 897 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 898 DLE_DFI_TYPE_##__target) | \ 899 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 900 B_AX_WDE_DFI_ACTIVE; \ 901 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 902 __ret = read_poll_timeout(rtw89_read32, __val32, \ 903 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 904 1000, 50000, false, \ 905 rtwdev, __reg_ctrl); \ 906 if (__ret) { \ 907 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 908 #__type, #__target, __sel); \ 909 return __ret; \ 910 } \ 911 \ 912 __data = rtw89_read32(rtwdev, __reg_data); \ 913 __data; \ 914 }) 915 916 #define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \ 917 ({ \ 918 u32 __freepg, __pubpg; \ 919 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 920 \ 921 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 922 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 923 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 924 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 925 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 926 seq_printf(__m, "[%s] freepg head: %d\n", \ 927 #__type, __freepg_head); \ 928 seq_printf(__m, "[%s] freepg tail: %d\n", \ 929 #__type, __freepg_tail); \ 930 seq_printf(__m, "[%s] pubpg num : %d\n", \ 931 #__type, __pubpg_num); \ 932 }) 933 934 #define case_QUOTA(__m, __type, __id) \ 935 case __type##_QTAID_##__id: \ 936 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 937 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 938 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 939 seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \ 940 #__type, #__id, rsv_pgnum); \ 941 seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \ 942 #__type, #__id, use_pgnum); \ 943 break 944 u32 quota_id; 945 u32 val32; 946 u16 rsv_pgnum, use_pgnum; 947 int ret; 948 949 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 950 if (ret) { 951 seq_puts(m, "[DLE] : DMAC not enabled\n"); 952 return ret; 953 } 954 955 DLE_DFI_FREE_PAGE_DUMP(m, WDE); 956 DLE_DFI_FREE_PAGE_DUMP(m, PLE); 957 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 958 switch (quota_id) { 959 case_QUOTA(m, WDE, HOST_IF); 960 case_QUOTA(m, WDE, WLAN_CPU); 961 case_QUOTA(m, WDE, DATA_CPU); 962 case_QUOTA(m, WDE, PKTIN); 963 case_QUOTA(m, WDE, CPUIO); 964 } 965 } 966 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 967 switch (quota_id) { 968 case_QUOTA(m, PLE, B0_TXPL); 969 case_QUOTA(m, PLE, B1_TXPL); 970 case_QUOTA(m, PLE, C2H); 971 case_QUOTA(m, PLE, H2C); 972 case_QUOTA(m, PLE, WLAN_CPU); 973 case_QUOTA(m, PLE, MPDU); 974 case_QUOTA(m, PLE, CMAC0_RX); 975 case_QUOTA(m, PLE, CMAC1_RX); 976 case_QUOTA(m, PLE, CMAC1_BBRPT); 977 case_QUOTA(m, PLE, WDRLS); 978 case_QUOTA(m, PLE, CPUIO); 979 } 980 } 981 982 return 0; 983 984 #undef case_QUOTA 985 #undef DLE_DFI_DUMP 986 #undef DLE_DFI_FREE_PAGE_DUMP 987 } 988 989 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 990 struct seq_file *m) 991 { 992 const struct rtw89_chip_info *chip = rtwdev->chip; 993 u32 dmac_err; 994 int i, ret; 995 996 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 997 if (ret) { 998 seq_puts(m, "[DMAC] : DMAC not enabled\n"); 999 return ret; 1000 } 1001 1002 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 1003 seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 1004 seq_printf(m, "R_AX_DMAC_ERR_IMR=0x%08x\n", 1005 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 1006 1007 if (dmac_err) { 1008 seq_printf(m, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 1009 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 1010 seq_printf(m, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 1011 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 1012 if (chip->chip_id == RTL8852C) { 1013 seq_printf(m, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 1014 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 1015 seq_printf(m, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 1016 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 1017 seq_printf(m, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 1018 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 1019 seq_printf(m, "R_AX_PLE_DBGERR_STS=0x%08x\n", 1020 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 1021 } 1022 } 1023 1024 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 1025 seq_printf(m, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 1026 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 1027 seq_printf(m, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 1028 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 1029 if (chip->chip_id == RTL8852C) 1030 seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1031 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 1032 else 1033 seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1034 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 1035 } 1036 1037 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 1038 if (chip->chip_id == RTL8852C) { 1039 seq_printf(m, "R_AX_SEC_ERR_IMR=0x%08x\n", 1040 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 1041 seq_printf(m, "R_AX_SEC_ERR_ISR=0x%08x\n", 1042 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 1043 seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n", 1044 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1045 seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n", 1046 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1047 seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1048 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1049 seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n", 1050 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1051 seq_printf(m, "R_AX_SEC_DEBUG1=0x%08x\n", 1052 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 1053 seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n", 1054 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1055 seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n", 1056 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1057 1058 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1059 B_AX_DBG_SEL0, 0x8B); 1060 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1061 B_AX_DBG_SEL1, 0x8B); 1062 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 1063 B_AX_SEL_0XC0_MASK, 1); 1064 for (i = 0; i < 0x10; i++) { 1065 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 1066 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 1067 seq_printf(m, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 1068 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 1069 } 1070 } else { 1071 seq_printf(m, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 1072 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 1073 seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n", 1074 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1075 seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n", 1076 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1077 seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1078 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1079 seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n", 1080 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1081 seq_printf(m, "R_AX_SEC_CAM_WDATA=0x%08x\n", 1082 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 1083 seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n", 1084 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1085 seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n", 1086 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1087 seq_printf(m, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 1088 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 1089 seq_printf(m, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 1090 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 1091 } 1092 } 1093 1094 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 1095 seq_printf(m, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 1096 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 1097 seq_printf(m, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 1098 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 1099 seq_printf(m, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 1100 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 1101 seq_printf(m, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 1102 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 1103 } 1104 1105 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 1106 seq_printf(m, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 1107 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 1108 seq_printf(m, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 1109 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 1110 } 1111 1112 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 1113 seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n", 1114 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1115 seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n", 1116 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1117 seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n", 1118 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1119 seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1120 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1121 } 1122 1123 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 1124 if (chip->chip_id == RTL8852C) { 1125 seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 1126 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 1127 seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 1128 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 1129 seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 1130 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 1131 seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 1132 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 1133 } else { 1134 seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 1135 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 1136 seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 1137 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 1138 } 1139 } 1140 1141 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 1142 seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n", 1143 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1144 seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n", 1145 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1146 seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n", 1147 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1148 seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1149 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1150 seq_printf(m, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 1151 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 1152 seq_printf(m, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 1153 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 1154 seq_printf(m, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 1155 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 1156 seq_printf(m, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 1157 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 1158 seq_printf(m, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 1159 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 1160 seq_printf(m, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 1161 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 1162 seq_printf(m, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 1163 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 1164 seq_printf(m, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 1165 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 1166 if (chip->chip_id == RTL8852C) { 1167 seq_printf(m, "R_AX_RX_CTRL0=0x%08x\n", 1168 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 1169 seq_printf(m, "R_AX_RX_CTRL1=0x%08x\n", 1170 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 1171 seq_printf(m, "R_AX_RX_CTRL2=0x%08x\n", 1172 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 1173 } else { 1174 seq_printf(m, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 1175 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 1176 seq_printf(m, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 1177 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 1178 seq_printf(m, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 1179 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 1180 } 1181 } 1182 1183 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 1184 seq_printf(m, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 1185 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 1186 seq_printf(m, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 1187 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 1188 } 1189 1190 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 1191 seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 1192 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 1193 seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 1194 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 1195 seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 1196 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 1197 seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 1198 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 1199 seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 1200 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 1201 seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 1202 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 1203 } 1204 1205 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 1206 if (chip->chip_id == RTL8852C) { 1207 seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 1208 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 1209 seq_printf(m, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 1210 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 1211 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1212 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1213 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1214 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1215 seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1216 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1217 seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1218 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1219 } else { 1220 seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 1221 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 1222 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1223 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1224 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1225 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1226 seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1227 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1228 seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1229 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1230 } 1231 } 1232 1233 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 1234 seq_printf(m, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 1235 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 1236 seq_printf(m, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 1237 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 1238 } 1239 1240 return 0; 1241 } 1242 1243 static int rtw89_debug_mac_dump_cmac_err(struct rtw89_dev *rtwdev, 1244 struct seq_file *m, 1245 enum rtw89_mac_idx band) 1246 { 1247 const struct rtw89_chip_info *chip = rtwdev->chip; 1248 u32 offset = 0; 1249 u32 cmac_err; 1250 int ret; 1251 1252 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 1253 if (ret) { 1254 if (band) 1255 seq_puts(m, "[CMAC] : CMAC1 not enabled\n"); 1256 else 1257 seq_puts(m, "[CMAC] : CMAC0 not enabled\n"); 1258 return ret; 1259 } 1260 1261 if (band) 1262 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 1263 1264 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 1265 seq_printf(m, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 1266 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 1267 seq_printf(m, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 1268 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 1269 seq_printf(m, "R_AX_CK_EN [%d]=0x%08x\n", band, 1270 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 1271 1272 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 1273 seq_printf(m, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 1274 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 1275 seq_printf(m, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 1276 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 1277 } 1278 1279 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 1280 seq_printf(m, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 1281 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 1282 seq_printf(m, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 1283 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 1284 } 1285 1286 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 1287 if (chip->chip_id == RTL8852C) { 1288 seq_printf(m, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 1289 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 1290 seq_printf(m, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 1291 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 1292 } else { 1293 seq_printf(m, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 1294 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 1295 } 1296 } 1297 1298 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 1299 if (chip->chip_id == RTL8852C) { 1300 seq_printf(m, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 1301 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 1302 seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 1303 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1304 } else { 1305 seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 1306 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1307 } 1308 } 1309 1310 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 1311 seq_printf(m, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 1312 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 1313 seq_printf(m, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 1314 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 1315 } 1316 1317 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 1318 if (chip->chip_id == RTL8852C) { 1319 seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 1320 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 1321 seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 1322 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 1323 } else { 1324 seq_printf(m, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 1325 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 1326 } 1327 seq_printf(m, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 1328 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 1329 } 1330 1331 seq_printf(m, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 1332 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 1333 1334 return 0; 1335 } 1336 1337 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 1338 struct seq_file *m) 1339 { 1340 rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_0); 1341 if (rtwdev->dbcc_en) 1342 rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_1); 1343 1344 return 0; 1345 } 1346 1347 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1348 .sel_addr = R_AX_PTCL_DBG, 1349 .sel_byte = 1, 1350 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1351 .srt = 0x00, 1352 .end = 0x3F, 1353 .rd_addr = R_AX_PTCL_DBG_INFO, 1354 .rd_byte = 4, 1355 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1356 }; 1357 1358 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1359 .sel_addr = R_AX_PTCL_DBG_C1, 1360 .sel_byte = 1, 1361 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1362 .srt = 0x00, 1363 .end = 0x3F, 1364 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1365 .rd_byte = 4, 1366 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1367 }; 1368 1369 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx0_5 = { 1370 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1371 .sel_byte = 2, 1372 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1373 .srt = 0x0, 1374 .end = 0xD, 1375 .rd_addr = R_AX_DBG_PORT_SEL, 1376 .rd_byte = 4, 1377 .rd_msk = B_AX_DEBUG_ST_MASK 1378 }; 1379 1380 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx6 = { 1381 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1382 .sel_byte = 2, 1383 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1384 .srt = 0x0, 1385 .end = 0x5, 1386 .rd_addr = R_AX_DBG_PORT_SEL, 1387 .rd_byte = 4, 1388 .rd_msk = B_AX_DEBUG_ST_MASK 1389 }; 1390 1391 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx7 = { 1392 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1393 .sel_byte = 2, 1394 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1395 .srt = 0x0, 1396 .end = 0x9, 1397 .rd_addr = R_AX_DBG_PORT_SEL, 1398 .rd_byte = 4, 1399 .rd_msk = B_AX_DEBUG_ST_MASK 1400 }; 1401 1402 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx8 = { 1403 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1404 .sel_byte = 2, 1405 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1406 .srt = 0x0, 1407 .end = 0x3, 1408 .rd_addr = R_AX_DBG_PORT_SEL, 1409 .rd_byte = 4, 1410 .rd_msk = B_AX_DEBUG_ST_MASK 1411 }; 1412 1413 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx9_C = { 1414 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1415 .sel_byte = 2, 1416 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1417 .srt = 0x0, 1418 .end = 0x1, 1419 .rd_addr = R_AX_DBG_PORT_SEL, 1420 .rd_byte = 4, 1421 .rd_msk = B_AX_DEBUG_ST_MASK 1422 }; 1423 1424 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_txD = { 1425 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1426 .sel_byte = 2, 1427 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1428 .srt = 0x0, 1429 .end = 0x0, 1430 .rd_addr = R_AX_DBG_PORT_SEL, 1431 .rd_byte = 4, 1432 .rd_msk = B_AX_DEBUG_ST_MASK 1433 }; 1434 1435 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx0 = { 1436 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1437 .sel_byte = 2, 1438 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1439 .srt = 0x0, 1440 .end = 0xB, 1441 .rd_addr = R_AX_DBG_PORT_SEL, 1442 .rd_byte = 4, 1443 .rd_msk = B_AX_DEBUG_ST_MASK 1444 }; 1445 1446 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx1 = { 1447 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1448 .sel_byte = 2, 1449 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1450 .srt = 0x0, 1451 .end = 0x4, 1452 .rd_addr = R_AX_DBG_PORT_SEL, 1453 .rd_byte = 4, 1454 .rd_msk = B_AX_DEBUG_ST_MASK 1455 }; 1456 1457 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx3 = { 1458 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1459 .sel_byte = 2, 1460 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1461 .srt = 0x0, 1462 .end = 0x8, 1463 .rd_addr = R_AX_DBG_PORT_SEL, 1464 .rd_byte = 4, 1465 .rd_msk = B_AX_DEBUG_ST_MASK 1466 }; 1467 1468 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx4 = { 1469 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1470 .sel_byte = 2, 1471 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1472 .srt = 0x0, 1473 .end = 0x7, 1474 .rd_addr = R_AX_DBG_PORT_SEL, 1475 .rd_byte = 4, 1476 .rd_msk = B_AX_DEBUG_ST_MASK 1477 }; 1478 1479 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx5_8 = { 1480 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1481 .sel_byte = 2, 1482 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1483 .srt = 0x0, 1484 .end = 0x1, 1485 .rd_addr = R_AX_DBG_PORT_SEL, 1486 .rd_byte = 4, 1487 .rd_msk = B_AX_DEBUG_ST_MASK 1488 }; 1489 1490 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx9 = { 1491 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1492 .sel_byte = 2, 1493 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1494 .srt = 0x0, 1495 .end = 0x3, 1496 .rd_addr = R_AX_DBG_PORT_SEL, 1497 .rd_byte = 4, 1498 .rd_msk = B_AX_DEBUG_ST_MASK 1499 }; 1500 1501 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_txA_C = { 1502 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1503 .sel_byte = 2, 1504 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1505 .srt = 0x0, 1506 .end = 0x0, 1507 .rd_addr = R_AX_DBG_PORT_SEL, 1508 .rd_byte = 4, 1509 .rd_msk = B_AX_DEBUG_ST_MASK 1510 }; 1511 1512 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx0 = { 1513 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1514 .sel_byte = 2, 1515 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1516 .srt = 0x0, 1517 .end = 0x8, 1518 .rd_addr = R_AX_DBG_PORT_SEL, 1519 .rd_byte = 4, 1520 .rd_msk = B_AX_DEBUG_ST_MASK 1521 }; 1522 1523 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx1_2 = { 1524 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1525 .sel_byte = 2, 1526 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1527 .srt = 0x0, 1528 .end = 0x0, 1529 .rd_addr = R_AX_DBG_PORT_SEL, 1530 .rd_byte = 4, 1531 .rd_msk = B_AX_DEBUG_ST_MASK 1532 }; 1533 1534 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx3 = { 1535 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1536 .sel_byte = 2, 1537 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1538 .srt = 0x0, 1539 .end = 0x6, 1540 .rd_addr = R_AX_DBG_PORT_SEL, 1541 .rd_byte = 4, 1542 .rd_msk = B_AX_DEBUG_ST_MASK 1543 }; 1544 1545 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx4 = { 1546 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1547 .sel_byte = 2, 1548 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1549 .srt = 0x0, 1550 .end = 0x0, 1551 .rd_addr = R_AX_DBG_PORT_SEL, 1552 .rd_byte = 4, 1553 .rd_msk = B_AX_DEBUG_ST_MASK 1554 }; 1555 1556 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx5 = { 1557 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1558 .sel_byte = 2, 1559 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1560 .srt = 0x0, 1561 .end = 0x0, 1562 .rd_addr = R_AX_DBG_PORT_SEL, 1563 .rd_byte = 4, 1564 .rd_msk = B_AX_DEBUG_ST_MASK 1565 }; 1566 1567 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_0 = { 1568 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1569 .sel_byte = 1, 1570 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1571 .srt = 0x0, 1572 .end = 0x3, 1573 .rd_addr = R_AX_DBG_PORT_SEL, 1574 .rd_byte = 4, 1575 .rd_msk = B_AX_DEBUG_ST_MASK 1576 }; 1577 1578 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_1 = { 1579 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1580 .sel_byte = 1, 1581 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1582 .srt = 0x0, 1583 .end = 0x6, 1584 .rd_addr = R_AX_DBG_PORT_SEL, 1585 .rd_byte = 4, 1586 .rd_msk = B_AX_DEBUG_ST_MASK 1587 }; 1588 1589 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_2 = { 1590 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1591 .sel_byte = 1, 1592 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1593 .srt = 0x0, 1594 .end = 0x0, 1595 .rd_addr = R_AX_DBG_PORT_SEL, 1596 .rd_byte = 4, 1597 .rd_msk = B_AX_DEBUG_ST_MASK 1598 }; 1599 1600 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p1 = { 1601 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1602 .sel_byte = 1, 1603 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1604 .srt = 0x8, 1605 .end = 0xE, 1606 .rd_addr = R_AX_DBG_PORT_SEL, 1607 .rd_byte = 4, 1608 .rd_msk = B_AX_DEBUG_ST_MASK 1609 }; 1610 1611 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_stf_ctrl = { 1612 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1613 .sel_byte = 1, 1614 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1615 .srt = 0x0, 1616 .end = 0x5, 1617 .rd_addr = R_AX_DBG_PORT_SEL, 1618 .rd_byte = 4, 1619 .rd_msk = B_AX_DEBUG_ST_MASK 1620 }; 1621 1622 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_addr_ctrl = { 1623 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1624 .sel_byte = 1, 1625 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1626 .srt = 0x0, 1627 .end = 0x6, 1628 .rd_addr = R_AX_DBG_PORT_SEL, 1629 .rd_byte = 4, 1630 .rd_msk = B_AX_DEBUG_ST_MASK 1631 }; 1632 1633 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_wde_intf = { 1634 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1635 .sel_byte = 1, 1636 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1637 .srt = 0x0, 1638 .end = 0xF, 1639 .rd_addr = R_AX_DBG_PORT_SEL, 1640 .rd_byte = 4, 1641 .rd_msk = B_AX_DEBUG_ST_MASK 1642 }; 1643 1644 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_ple_intf = { 1645 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1646 .sel_byte = 1, 1647 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1648 .srt = 0x0, 1649 .end = 0x9, 1650 .rd_addr = R_AX_DBG_PORT_SEL, 1651 .rd_byte = 4, 1652 .rd_msk = B_AX_DEBUG_ST_MASK 1653 }; 1654 1655 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_flow_ctrl = { 1656 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1657 .sel_byte = 1, 1658 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1659 .srt = 0x0, 1660 .end = 0x3, 1661 .rd_addr = R_AX_DBG_PORT_SEL, 1662 .rd_byte = 4, 1663 .rd_msk = B_AX_DEBUG_ST_MASK 1664 }; 1665 1666 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 1667 .sel_addr = R_AX_SCH_DBG_SEL, 1668 .sel_byte = 1, 1669 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1670 .srt = 0x00, 1671 .end = 0x2F, 1672 .rd_addr = R_AX_SCH_DBG, 1673 .rd_byte = 4, 1674 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1675 }; 1676 1677 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 1678 .sel_addr = R_AX_SCH_DBG_SEL_C1, 1679 .sel_byte = 1, 1680 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1681 .srt = 0x00, 1682 .end = 0x2F, 1683 .rd_addr = R_AX_SCH_DBG_C1, 1684 .rd_byte = 4, 1685 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1686 }; 1687 1688 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 1689 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 1690 .sel_byte = 1, 1691 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1692 .srt = 0x00, 1693 .end = 0x19, 1694 .rd_addr = R_AX_DBG_PORT_SEL, 1695 .rd_byte = 4, 1696 .rd_msk = B_AX_DEBUG_ST_MASK 1697 }; 1698 1699 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 1700 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 1701 .sel_byte = 1, 1702 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1703 .srt = 0x00, 1704 .end = 0x19, 1705 .rd_addr = R_AX_DBG_PORT_SEL, 1706 .rd_byte = 4, 1707 .rd_msk = B_AX_DEBUG_ST_MASK 1708 }; 1709 1710 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 1711 .sel_addr = R_AX_RX_DEBUG_SELECT, 1712 .sel_byte = 1, 1713 .sel_msk = B_AX_DEBUG_SEL_MASK, 1714 .srt = 0x00, 1715 .end = 0x58, 1716 .rd_addr = R_AX_DBG_PORT_SEL, 1717 .rd_byte = 4, 1718 .rd_msk = B_AX_DEBUG_ST_MASK 1719 }; 1720 1721 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 1722 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 1723 .sel_byte = 1, 1724 .sel_msk = B_AX_DEBUG_SEL_MASK, 1725 .srt = 0x00, 1726 .end = 0x58, 1727 .rd_addr = R_AX_DBG_PORT_SEL, 1728 .rd_byte = 4, 1729 .rd_msk = B_AX_DEBUG_ST_MASK 1730 }; 1731 1732 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 1733 .sel_addr = R_AX_RX_STATE_MONITOR, 1734 .sel_byte = 1, 1735 .sel_msk = B_AX_STATE_SEL_MASK, 1736 .srt = 0x00, 1737 .end = 0x17, 1738 .rd_addr = R_AX_RX_STATE_MONITOR, 1739 .rd_byte = 4, 1740 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 1741 }; 1742 1743 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 1744 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 1745 .sel_byte = 1, 1746 .sel_msk = B_AX_STATE_SEL_MASK, 1747 .srt = 0x00, 1748 .end = 0x17, 1749 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 1750 .rd_byte = 4, 1751 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 1752 }; 1753 1754 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 1755 .sel_addr = R_AX_RMAC_PLCP_MON, 1756 .sel_byte = 4, 1757 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 1758 .srt = 0x0, 1759 .end = 0xF, 1760 .rd_addr = R_AX_RMAC_PLCP_MON, 1761 .rd_byte = 4, 1762 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 1763 }; 1764 1765 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 1766 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 1767 .sel_byte = 4, 1768 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 1769 .srt = 0x0, 1770 .end = 0xF, 1771 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 1772 .rd_byte = 4, 1773 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 1774 }; 1775 1776 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 1777 .sel_addr = R_AX_DBGSEL_TRXPTCL, 1778 .sel_byte = 1, 1779 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 1780 .srt = 0x08, 1781 .end = 0x10, 1782 .rd_addr = R_AX_DBG_PORT_SEL, 1783 .rd_byte = 4, 1784 .rd_msk = B_AX_DEBUG_ST_MASK 1785 }; 1786 1787 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 1788 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 1789 .sel_byte = 1, 1790 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 1791 .srt = 0x08, 1792 .end = 0x10, 1793 .rd_addr = R_AX_DBG_PORT_SEL, 1794 .rd_byte = 4, 1795 .rd_msk = B_AX_DEBUG_ST_MASK 1796 }; 1797 1798 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 1799 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 1800 .sel_byte = 1, 1801 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1802 .srt = 0x00, 1803 .end = 0x07, 1804 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 1805 .rd_byte = 4, 1806 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 1807 }; 1808 1809 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 1810 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 1811 .sel_byte = 1, 1812 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1813 .srt = 0x00, 1814 .end = 0x07, 1815 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 1816 .rd_byte = 4, 1817 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 1818 }; 1819 1820 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 1821 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 1822 .sel_byte = 1, 1823 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1824 .srt = 0x00, 1825 .end = 0x07, 1826 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 1827 .rd_byte = 4, 1828 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 1829 }; 1830 1831 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 1832 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 1833 .sel_byte = 1, 1834 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1835 .srt = 0x00, 1836 .end = 0x07, 1837 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 1838 .rd_byte = 4, 1839 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 1840 }; 1841 1842 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 1843 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 1844 .sel_byte = 1, 1845 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1846 .srt = 0x00, 1847 .end = 0x04, 1848 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 1849 .rd_byte = 4, 1850 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 1851 }; 1852 1853 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 1854 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 1855 .sel_byte = 1, 1856 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1857 .srt = 0x00, 1858 .end = 0x04, 1859 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 1860 .rd_byte = 4, 1861 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 1862 }; 1863 1864 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 1865 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 1866 .sel_byte = 1, 1867 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1868 .srt = 0x00, 1869 .end = 0x04, 1870 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 1871 .rd_byte = 4, 1872 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 1873 }; 1874 1875 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 1876 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 1877 .sel_byte = 1, 1878 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1879 .srt = 0x00, 1880 .end = 0x04, 1881 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 1882 .rd_byte = 4, 1883 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 1884 }; 1885 1886 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 1887 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1888 .sel_byte = 4, 1889 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1890 .srt = 0x80000000, 1891 .end = 0x80000001, 1892 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1893 .rd_byte = 4, 1894 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1895 }; 1896 1897 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 1898 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1899 .sel_byte = 4, 1900 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1901 .srt = 0x80010000, 1902 .end = 0x80010004, 1903 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1904 .rd_byte = 4, 1905 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1906 }; 1907 1908 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 1909 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1910 .sel_byte = 4, 1911 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1912 .srt = 0x80020000, 1913 .end = 0x80020FFF, 1914 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1915 .rd_byte = 4, 1916 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1917 }; 1918 1919 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 1920 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1921 .sel_byte = 4, 1922 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1923 .srt = 0x80030000, 1924 .end = 0x80030FFF, 1925 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1926 .rd_byte = 4, 1927 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1928 }; 1929 1930 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 1931 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1932 .sel_byte = 4, 1933 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1934 .srt = 0x80040000, 1935 .end = 0x80040FFF, 1936 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1937 .rd_byte = 4, 1938 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1939 }; 1940 1941 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 1942 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1943 .sel_byte = 4, 1944 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1945 .srt = 0x80050000, 1946 .end = 0x80050FFF, 1947 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1948 .rd_byte = 4, 1949 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1950 }; 1951 1952 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 1953 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1954 .sel_byte = 4, 1955 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1956 .srt = 0x80060000, 1957 .end = 0x80060453, 1958 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1959 .rd_byte = 4, 1960 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1961 }; 1962 1963 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 1964 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1965 .sel_byte = 4, 1966 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1967 .srt = 0x80070000, 1968 .end = 0x80070011, 1969 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1970 .rd_byte = 4, 1971 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1972 }; 1973 1974 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 1975 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1976 .sel_byte = 4, 1977 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1978 .srt = 0x80000000, 1979 .end = 0x80000001, 1980 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1981 .rd_byte = 4, 1982 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1983 }; 1984 1985 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 1986 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1987 .sel_byte = 4, 1988 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1989 .srt = 0x80010000, 1990 .end = 0x8001000A, 1991 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1992 .rd_byte = 4, 1993 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1994 }; 1995 1996 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 1997 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1998 .sel_byte = 4, 1999 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2000 .srt = 0x80020000, 2001 .end = 0x80020DBF, 2002 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2003 .rd_byte = 4, 2004 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2005 }; 2006 2007 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 2008 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2009 .sel_byte = 4, 2010 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2011 .srt = 0x80030000, 2012 .end = 0x80030DBF, 2013 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2014 .rd_byte = 4, 2015 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2016 }; 2017 2018 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 2019 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2020 .sel_byte = 4, 2021 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2022 .srt = 0x80040000, 2023 .end = 0x80040DBF, 2024 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2025 .rd_byte = 4, 2026 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2027 }; 2028 2029 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 2030 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2031 .sel_byte = 4, 2032 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2033 .srt = 0x80050000, 2034 .end = 0x80050DBF, 2035 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2036 .rd_byte = 4, 2037 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2038 }; 2039 2040 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 2041 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2042 .sel_byte = 4, 2043 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2044 .srt = 0x80060000, 2045 .end = 0x80060041, 2046 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2047 .rd_byte = 4, 2048 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2049 }; 2050 2051 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 2052 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2053 .sel_byte = 4, 2054 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2055 .srt = 0x80070000, 2056 .end = 0x80070001, 2057 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2058 .rd_byte = 4, 2059 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2060 }; 2061 2062 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 2063 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 2064 .sel_byte = 4, 2065 .sel_msk = B_AX_DFI_DATA_MASK, 2066 .srt = 0x80000000, 2067 .end = 0x8000017f, 2068 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 2069 .rd_byte = 4, 2070 .rd_msk = B_AX_DFI_DATA_MASK 2071 }; 2072 2073 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 2074 .sel_addr = R_AX_PCIE_DBG_CTRL, 2075 .sel_byte = 2, 2076 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2077 .srt = 0x00, 2078 .end = 0x03, 2079 .rd_addr = R_AX_DBG_PORT_SEL, 2080 .rd_byte = 4, 2081 .rd_msk = B_AX_DEBUG_ST_MASK 2082 }; 2083 2084 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 2085 .sel_addr = R_AX_PCIE_DBG_CTRL, 2086 .sel_byte = 2, 2087 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2088 .srt = 0x00, 2089 .end = 0x04, 2090 .rd_addr = R_AX_DBG_PORT_SEL, 2091 .rd_byte = 4, 2092 .rd_msk = B_AX_DEBUG_ST_MASK 2093 }; 2094 2095 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 2096 .sel_addr = R_AX_PCIE_DBG_CTRL, 2097 .sel_byte = 2, 2098 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2099 .srt = 0x00, 2100 .end = 0x01, 2101 .rd_addr = R_AX_DBG_PORT_SEL, 2102 .rd_byte = 4, 2103 .rd_msk = B_AX_DEBUG_ST_MASK 2104 }; 2105 2106 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 2107 .sel_addr = R_AX_PCIE_DBG_CTRL, 2108 .sel_byte = 2, 2109 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2110 .srt = 0x00, 2111 .end = 0x05, 2112 .rd_addr = R_AX_DBG_PORT_SEL, 2113 .rd_byte = 4, 2114 .rd_msk = B_AX_DEBUG_ST_MASK 2115 }; 2116 2117 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 2118 .sel_addr = R_AX_PCIE_DBG_CTRL, 2119 .sel_byte = 2, 2120 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2121 .srt = 0x00, 2122 .end = 0x05, 2123 .rd_addr = R_AX_DBG_PORT_SEL, 2124 .rd_byte = 4, 2125 .rd_msk = B_AX_DEBUG_ST_MASK 2126 }; 2127 2128 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 2129 .sel_addr = R_AX_PCIE_DBG_CTRL, 2130 .sel_byte = 2, 2131 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2132 .srt = 0x00, 2133 .end = 0x06, 2134 .rd_addr = R_AX_DBG_PORT_SEL, 2135 .rd_byte = 4, 2136 .rd_msk = B_AX_DEBUG_ST_MASK 2137 }; 2138 2139 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 2140 .sel_addr = R_AX_DBG_CTRL, 2141 .sel_byte = 1, 2142 .sel_msk = B_AX_DBG_SEL0, 2143 .srt = 0x34, 2144 .end = 0x3C, 2145 .rd_addr = R_AX_DBG_PORT_SEL, 2146 .rd_byte = 4, 2147 .rd_msk = B_AX_DEBUG_ST_MASK 2148 }; 2149 2150 static const struct rtw89_mac_dbg_port_info * 2151 rtw89_debug_mac_dbg_port_sel(struct seq_file *m, 2152 struct rtw89_dev *rtwdev, u32 sel) 2153 { 2154 const struct rtw89_mac_dbg_port_info *info; 2155 u32 index; 2156 u32 val32; 2157 u16 val16; 2158 u8 val8; 2159 2160 switch (sel) { 2161 case RTW89_DBG_PORT_SEL_PTCL_C0: 2162 info = &dbg_port_ptcl_c0; 2163 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 2164 val16 |= B_AX_PTCL_DBG_EN; 2165 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 2166 seq_puts(m, "Enable PTCL C0 dbgport.\n"); 2167 break; 2168 case RTW89_DBG_PORT_SEL_PTCL_C1: 2169 info = &dbg_port_ptcl_c1; 2170 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 2171 val16 |= B_AX_PTCL_DBG_EN; 2172 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 2173 seq_puts(m, "Enable PTCL C1 dbgport.\n"); 2174 break; 2175 case RTW89_DBG_PORT_SEL_SCH_C0: 2176 info = &dbg_port_sch_c0; 2177 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 2178 val32 |= B_AX_SCH_DBG_EN; 2179 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 2180 seq_puts(m, "Enable SCH C0 dbgport.\n"); 2181 break; 2182 case RTW89_DBG_PORT_SEL_SCH_C1: 2183 info = &dbg_port_sch_c1; 2184 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 2185 val32 |= B_AX_SCH_DBG_EN; 2186 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 2187 seq_puts(m, "Enable SCH C1 dbgport.\n"); 2188 break; 2189 case RTW89_DBG_PORT_SEL_TMAC_C0: 2190 info = &dbg_port_tmac_c0; 2191 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2192 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2193 B_AX_DBGSEL_TRXPTCL_MASK); 2194 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2195 2196 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2197 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2198 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2199 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2200 2201 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2202 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2203 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2204 seq_puts(m, "Enable TMAC C0 dbgport.\n"); 2205 break; 2206 case RTW89_DBG_PORT_SEL_TMAC_C1: 2207 info = &dbg_port_tmac_c1; 2208 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2209 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2210 B_AX_DBGSEL_TRXPTCL_MASK); 2211 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2212 2213 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2214 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2215 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2216 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2217 2218 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2219 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2220 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2221 seq_puts(m, "Enable TMAC C1 dbgport.\n"); 2222 break; 2223 case RTW89_DBG_PORT_SEL_RMAC_C0: 2224 info = &dbg_port_rmac_c0; 2225 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2226 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2227 B_AX_DBGSEL_TRXPTCL_MASK); 2228 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2229 2230 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2231 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2232 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2233 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2234 2235 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2236 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2237 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2238 2239 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 2240 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2241 B_AX_DBGSEL_TRXPTCL_MASK); 2242 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 2243 seq_puts(m, "Enable RMAC C0 dbgport.\n"); 2244 break; 2245 case RTW89_DBG_PORT_SEL_RMAC_C1: 2246 info = &dbg_port_rmac_c1; 2247 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2248 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2249 B_AX_DBGSEL_TRXPTCL_MASK); 2250 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2251 2252 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2253 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2254 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2255 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2256 2257 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2258 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2259 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2260 2261 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2262 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2263 B_AX_DBGSEL_TRXPTCL_MASK); 2264 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 2265 seq_puts(m, "Enable RMAC C1 dbgport.\n"); 2266 break; 2267 case RTW89_DBG_PORT_SEL_RMACST_C0: 2268 info = &dbg_port_rmacst_c0; 2269 seq_puts(m, "Enable RMAC state C0 dbgport.\n"); 2270 break; 2271 case RTW89_DBG_PORT_SEL_RMACST_C1: 2272 info = &dbg_port_rmacst_c1; 2273 seq_puts(m, "Enable RMAC state C1 dbgport.\n"); 2274 break; 2275 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 2276 info = &dbg_port_rmac_plcp_c0; 2277 seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n"); 2278 break; 2279 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 2280 info = &dbg_port_rmac_plcp_c1; 2281 seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n"); 2282 break; 2283 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 2284 info = &dbg_port_trxptcl_c0; 2285 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2286 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 2287 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 2288 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2289 2290 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2291 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2292 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2293 seq_puts(m, "Enable TRXPTCL C0 dbgport.\n"); 2294 break; 2295 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 2296 info = &dbg_port_trxptcl_c1; 2297 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2298 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 2299 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 2300 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2301 2302 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2303 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2304 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2305 seq_puts(m, "Enable TRXPTCL C1 dbgport.\n"); 2306 break; 2307 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 2308 info = &dbg_port_tx_infol_c0; 2309 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2310 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2311 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2312 seq_puts(m, "Enable tx infol dump.\n"); 2313 break; 2314 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 2315 info = &dbg_port_tx_infoh_c0; 2316 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2317 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2318 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2319 seq_puts(m, "Enable tx infoh dump.\n"); 2320 break; 2321 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 2322 info = &dbg_port_tx_infol_c1; 2323 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2324 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2325 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2326 seq_puts(m, "Enable tx infol dump.\n"); 2327 break; 2328 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 2329 info = &dbg_port_tx_infoh_c1; 2330 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2331 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2332 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2333 seq_puts(m, "Enable tx infoh dump.\n"); 2334 break; 2335 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 2336 info = &dbg_port_txtf_infol_c0; 2337 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2338 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2339 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2340 seq_puts(m, "Enable tx tf infol dump.\n"); 2341 break; 2342 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 2343 info = &dbg_port_txtf_infoh_c0; 2344 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2345 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2346 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2347 seq_puts(m, "Enable tx tf infoh dump.\n"); 2348 break; 2349 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 2350 info = &dbg_port_txtf_infol_c1; 2351 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2352 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2353 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2354 seq_puts(m, "Enable tx tf infol dump.\n"); 2355 break; 2356 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 2357 info = &dbg_port_txtf_infoh_c1; 2358 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2359 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2360 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2361 seq_puts(m, "Enable tx tf infoh dump.\n"); 2362 break; 2363 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 2364 info = &dbg_port_wde_bufmgn_freepg; 2365 seq_puts(m, "Enable wde bufmgn freepg dump.\n"); 2366 break; 2367 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 2368 info = &dbg_port_wde_bufmgn_quota; 2369 seq_puts(m, "Enable wde bufmgn quota dump.\n"); 2370 break; 2371 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 2372 info = &dbg_port_wde_bufmgn_pagellt; 2373 seq_puts(m, "Enable wde bufmgn pagellt dump.\n"); 2374 break; 2375 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 2376 info = &dbg_port_wde_bufmgn_pktinfo; 2377 seq_puts(m, "Enable wde bufmgn pktinfo dump.\n"); 2378 break; 2379 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 2380 info = &dbg_port_wde_quemgn_prepkt; 2381 seq_puts(m, "Enable wde quemgn prepkt dump.\n"); 2382 break; 2383 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 2384 info = &dbg_port_wde_quemgn_nxtpkt; 2385 seq_puts(m, "Enable wde quemgn nxtpkt dump.\n"); 2386 break; 2387 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 2388 info = &dbg_port_wde_quemgn_qlnktbl; 2389 seq_puts(m, "Enable wde quemgn qlnktbl dump.\n"); 2390 break; 2391 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 2392 info = &dbg_port_wde_quemgn_qempty; 2393 seq_puts(m, "Enable wde quemgn qempty dump.\n"); 2394 break; 2395 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 2396 info = &dbg_port_ple_bufmgn_freepg; 2397 seq_puts(m, "Enable ple bufmgn freepg dump.\n"); 2398 break; 2399 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 2400 info = &dbg_port_ple_bufmgn_quota; 2401 seq_puts(m, "Enable ple bufmgn quota dump.\n"); 2402 break; 2403 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 2404 info = &dbg_port_ple_bufmgn_pagellt; 2405 seq_puts(m, "Enable ple bufmgn pagellt dump.\n"); 2406 break; 2407 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 2408 info = &dbg_port_ple_bufmgn_pktinfo; 2409 seq_puts(m, "Enable ple bufmgn pktinfo dump.\n"); 2410 break; 2411 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 2412 info = &dbg_port_ple_quemgn_prepkt; 2413 seq_puts(m, "Enable ple quemgn prepkt dump.\n"); 2414 break; 2415 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 2416 info = &dbg_port_ple_quemgn_nxtpkt; 2417 seq_puts(m, "Enable ple quemgn nxtpkt dump.\n"); 2418 break; 2419 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 2420 info = &dbg_port_ple_quemgn_qlnktbl; 2421 seq_puts(m, "Enable ple quemgn qlnktbl dump.\n"); 2422 break; 2423 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 2424 info = &dbg_port_ple_quemgn_qempty; 2425 seq_puts(m, "Enable ple quemgn qempty dump.\n"); 2426 break; 2427 case RTW89_DBG_PORT_SEL_PKTINFO: 2428 info = &dbg_port_pktinfo; 2429 seq_puts(m, "Enable pktinfo dump.\n"); 2430 break; 2431 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX0: 2432 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 2433 B_AX_DBG_SEL0, 0x80); 2434 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 2435 B_AX_SEL_0XC0_MASK, 1); 2436 fallthrough; 2437 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX1: 2438 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX2: 2439 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX3: 2440 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX4: 2441 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX5: 2442 info = &dbg_port_dspt_hdt_tx0_5; 2443 index = sel - RTW89_DBG_PORT_SEL_DSPT_HDT_TX0; 2444 rtw89_write16_mask(rtwdev, info->sel_addr, 2445 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2446 rtw89_write16_mask(rtwdev, info->sel_addr, 2447 B_AX_DISPATCHER_CH_SEL_MASK, index); 2448 seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index); 2449 break; 2450 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX6: 2451 info = &dbg_port_dspt_hdt_tx6; 2452 rtw89_write16_mask(rtwdev, info->sel_addr, 2453 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2454 rtw89_write16_mask(rtwdev, info->sel_addr, 2455 B_AX_DISPATCHER_CH_SEL_MASK, 6); 2456 seq_puts(m, "Enable Dispatcher hdt tx6 dump.\n"); 2457 break; 2458 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX7: 2459 info = &dbg_port_dspt_hdt_tx7; 2460 rtw89_write16_mask(rtwdev, info->sel_addr, 2461 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2462 rtw89_write16_mask(rtwdev, info->sel_addr, 2463 B_AX_DISPATCHER_CH_SEL_MASK, 7); 2464 seq_puts(m, "Enable Dispatcher hdt tx7 dump.\n"); 2465 break; 2466 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX8: 2467 info = &dbg_port_dspt_hdt_tx8; 2468 rtw89_write16_mask(rtwdev, info->sel_addr, 2469 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2470 rtw89_write16_mask(rtwdev, info->sel_addr, 2471 B_AX_DISPATCHER_CH_SEL_MASK, 8); 2472 seq_puts(m, "Enable Dispatcher hdt tx8 dump.\n"); 2473 break; 2474 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX9: 2475 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXA: 2476 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXB: 2477 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXC: 2478 info = &dbg_port_dspt_hdt_tx9_C; 2479 index = sel + 9 - RTW89_DBG_PORT_SEL_DSPT_HDT_TX9; 2480 rtw89_write16_mask(rtwdev, info->sel_addr, 2481 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2482 rtw89_write16_mask(rtwdev, info->sel_addr, 2483 B_AX_DISPATCHER_CH_SEL_MASK, index); 2484 seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index); 2485 break; 2486 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXD: 2487 info = &dbg_port_dspt_hdt_txD; 2488 rtw89_write16_mask(rtwdev, info->sel_addr, 2489 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2490 rtw89_write16_mask(rtwdev, info->sel_addr, 2491 B_AX_DISPATCHER_CH_SEL_MASK, 0xD); 2492 seq_puts(m, "Enable Dispatcher hdt txD dump.\n"); 2493 break; 2494 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX0: 2495 info = &dbg_port_dspt_cdt_tx0; 2496 rtw89_write16_mask(rtwdev, info->sel_addr, 2497 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2498 rtw89_write16_mask(rtwdev, info->sel_addr, 2499 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2500 seq_puts(m, "Enable Dispatcher cdt tx0 dump.\n"); 2501 break; 2502 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX1: 2503 info = &dbg_port_dspt_cdt_tx1; 2504 rtw89_write16_mask(rtwdev, info->sel_addr, 2505 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2506 rtw89_write16_mask(rtwdev, info->sel_addr, 2507 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2508 seq_puts(m, "Enable Dispatcher cdt tx1 dump.\n"); 2509 break; 2510 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX3: 2511 info = &dbg_port_dspt_cdt_tx3; 2512 rtw89_write16_mask(rtwdev, info->sel_addr, 2513 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2514 rtw89_write16_mask(rtwdev, info->sel_addr, 2515 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2516 seq_puts(m, "Enable Dispatcher cdt tx3 dump.\n"); 2517 break; 2518 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX4: 2519 info = &dbg_port_dspt_cdt_tx4; 2520 rtw89_write16_mask(rtwdev, info->sel_addr, 2521 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2522 rtw89_write16_mask(rtwdev, info->sel_addr, 2523 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2524 seq_puts(m, "Enable Dispatcher cdt tx4 dump.\n"); 2525 break; 2526 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX5: 2527 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX6: 2528 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX7: 2529 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX8: 2530 info = &dbg_port_dspt_cdt_tx5_8; 2531 index = sel + 5 - RTW89_DBG_PORT_SEL_DSPT_CDT_TX5; 2532 rtw89_write16_mask(rtwdev, info->sel_addr, 2533 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2534 rtw89_write16_mask(rtwdev, info->sel_addr, 2535 B_AX_DISPATCHER_CH_SEL_MASK, index); 2536 seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index); 2537 break; 2538 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX9: 2539 info = &dbg_port_dspt_cdt_tx9; 2540 rtw89_write16_mask(rtwdev, info->sel_addr, 2541 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2542 rtw89_write16_mask(rtwdev, info->sel_addr, 2543 B_AX_DISPATCHER_CH_SEL_MASK, 9); 2544 seq_puts(m, "Enable Dispatcher cdt tx9 dump.\n"); 2545 break; 2546 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXA: 2547 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXB: 2548 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXC: 2549 info = &dbg_port_dspt_cdt_txA_C; 2550 index = sel + 0xA - RTW89_DBG_PORT_SEL_DSPT_CDT_TXA; 2551 rtw89_write16_mask(rtwdev, info->sel_addr, 2552 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2553 rtw89_write16_mask(rtwdev, info->sel_addr, 2554 B_AX_DISPATCHER_CH_SEL_MASK, index); 2555 seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index); 2556 break; 2557 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX0: 2558 info = &dbg_port_dspt_hdt_rx0; 2559 rtw89_write16_mask(rtwdev, info->sel_addr, 2560 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2561 rtw89_write16_mask(rtwdev, info->sel_addr, 2562 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2563 seq_puts(m, "Enable Dispatcher hdt rx0 dump.\n"); 2564 break; 2565 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX1: 2566 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX2: 2567 info = &dbg_port_dspt_hdt_rx1_2; 2568 index = sel + 1 - RTW89_DBG_PORT_SEL_DSPT_HDT_RX1; 2569 rtw89_write16_mask(rtwdev, info->sel_addr, 2570 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2571 rtw89_write16_mask(rtwdev, info->sel_addr, 2572 B_AX_DISPATCHER_CH_SEL_MASK, index); 2573 seq_printf(m, "Enable Dispatcher hdt rx%x dump.\n", index); 2574 break; 2575 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX3: 2576 info = &dbg_port_dspt_hdt_rx3; 2577 rtw89_write16_mask(rtwdev, info->sel_addr, 2578 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2579 rtw89_write16_mask(rtwdev, info->sel_addr, 2580 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2581 seq_puts(m, "Enable Dispatcher hdt rx3 dump.\n"); 2582 break; 2583 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX4: 2584 info = &dbg_port_dspt_hdt_rx4; 2585 rtw89_write16_mask(rtwdev, info->sel_addr, 2586 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2587 rtw89_write16_mask(rtwdev, info->sel_addr, 2588 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2589 seq_puts(m, "Enable Dispatcher hdt rx4 dump.\n"); 2590 break; 2591 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX5: 2592 info = &dbg_port_dspt_hdt_rx5; 2593 rtw89_write16_mask(rtwdev, info->sel_addr, 2594 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2595 rtw89_write16_mask(rtwdev, info->sel_addr, 2596 B_AX_DISPATCHER_CH_SEL_MASK, 5); 2597 seq_puts(m, "Enable Dispatcher hdt rx5 dump.\n"); 2598 break; 2599 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0: 2600 info = &dbg_port_dspt_cdt_rx_p0_0; 2601 rtw89_write16_mask(rtwdev, info->sel_addr, 2602 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2603 rtw89_write16_mask(rtwdev, info->sel_addr, 2604 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2605 seq_puts(m, "Enable Dispatcher cdt rx part0 0 dump.\n"); 2606 break; 2607 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0: 2608 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1: 2609 info = &dbg_port_dspt_cdt_rx_p0_1; 2610 rtw89_write16_mask(rtwdev, info->sel_addr, 2611 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2612 rtw89_write16_mask(rtwdev, info->sel_addr, 2613 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2614 seq_puts(m, "Enable Dispatcher cdt rx part0 1 dump.\n"); 2615 break; 2616 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2: 2617 info = &dbg_port_dspt_cdt_rx_p0_2; 2618 rtw89_write16_mask(rtwdev, info->sel_addr, 2619 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2620 rtw89_write16_mask(rtwdev, info->sel_addr, 2621 B_AX_DISPATCHER_CH_SEL_MASK, 2); 2622 seq_puts(m, "Enable Dispatcher cdt rx part0 2 dump.\n"); 2623 break; 2624 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1: 2625 info = &dbg_port_dspt_cdt_rx_p1; 2626 rtw89_write8_mask(rtwdev, info->sel_addr, 2627 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2628 seq_puts(m, "Enable Dispatcher cdt rx part1 dump.\n"); 2629 break; 2630 case RTW89_DBG_PORT_SEL_DSPT_STF_CTRL: 2631 info = &dbg_port_dspt_stf_ctrl; 2632 rtw89_write8_mask(rtwdev, info->sel_addr, 2633 B_AX_DISPATCHER_INTN_SEL_MASK, 4); 2634 seq_puts(m, "Enable Dispatcher stf control dump.\n"); 2635 break; 2636 case RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL: 2637 info = &dbg_port_dspt_addr_ctrl; 2638 rtw89_write8_mask(rtwdev, info->sel_addr, 2639 B_AX_DISPATCHER_INTN_SEL_MASK, 5); 2640 seq_puts(m, "Enable Dispatcher addr control dump.\n"); 2641 break; 2642 case RTW89_DBG_PORT_SEL_DSPT_WDE_INTF: 2643 info = &dbg_port_dspt_wde_intf; 2644 rtw89_write8_mask(rtwdev, info->sel_addr, 2645 B_AX_DISPATCHER_INTN_SEL_MASK, 6); 2646 seq_puts(m, "Enable Dispatcher wde interface dump.\n"); 2647 break; 2648 case RTW89_DBG_PORT_SEL_DSPT_PLE_INTF: 2649 info = &dbg_port_dspt_ple_intf; 2650 rtw89_write8_mask(rtwdev, info->sel_addr, 2651 B_AX_DISPATCHER_INTN_SEL_MASK, 7); 2652 seq_puts(m, "Enable Dispatcher ple interface dump.\n"); 2653 break; 2654 case RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL: 2655 info = &dbg_port_dspt_flow_ctrl; 2656 rtw89_write8_mask(rtwdev, info->sel_addr, 2657 B_AX_DISPATCHER_INTN_SEL_MASK, 8); 2658 seq_puts(m, "Enable Dispatcher flow control dump.\n"); 2659 break; 2660 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 2661 info = &dbg_port_pcie_txdma; 2662 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2663 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 2664 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 2665 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2666 seq_puts(m, "Enable pcie txdma dump.\n"); 2667 break; 2668 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 2669 info = &dbg_port_pcie_rxdma; 2670 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2671 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 2672 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 2673 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2674 seq_puts(m, "Enable pcie rxdma dump.\n"); 2675 break; 2676 case RTW89_DBG_PORT_SEL_PCIE_CVT: 2677 info = &dbg_port_pcie_cvt; 2678 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2679 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 2680 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 2681 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2682 seq_puts(m, "Enable pcie cvt dump.\n"); 2683 break; 2684 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 2685 info = &dbg_port_pcie_cxpl; 2686 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2687 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 2688 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 2689 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2690 seq_puts(m, "Enable pcie cxpl dump.\n"); 2691 break; 2692 case RTW89_DBG_PORT_SEL_PCIE_IO: 2693 info = &dbg_port_pcie_io; 2694 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2695 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 2696 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 2697 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2698 seq_puts(m, "Enable pcie io dump.\n"); 2699 break; 2700 case RTW89_DBG_PORT_SEL_PCIE_MISC: 2701 info = &dbg_port_pcie_misc; 2702 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2703 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 2704 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 2705 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2706 seq_puts(m, "Enable pcie misc dump.\n"); 2707 break; 2708 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 2709 info = &dbg_port_pcie_misc2; 2710 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 2711 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 2712 B_AX_PCIE_DBG_SEL_MASK); 2713 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 2714 seq_puts(m, "Enable pcie misc2 dump.\n"); 2715 break; 2716 default: 2717 seq_puts(m, "Dbg port select err\n"); 2718 return NULL; 2719 } 2720 2721 return info; 2722 } 2723 2724 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 2725 { 2726 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 2727 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 2728 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 2729 return false; 2730 if (rtwdev->chip->chip_id == RTL8852B && 2731 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 2732 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 2733 return false; 2734 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 2735 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 2736 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 2737 return false; 2738 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 2739 sel >= RTW89_DBG_PORT_SEL_DSPT_HDT_TX0 && 2740 sel <= RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL) 2741 return false; 2742 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 2743 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 2744 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 2745 return false; 2746 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 2747 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 2748 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 2749 return false; 2750 2751 return true; 2752 } 2753 2754 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 2755 struct seq_file *m, u32 sel) 2756 { 2757 const struct rtw89_mac_dbg_port_info *info; 2758 u8 val8; 2759 u16 val16; 2760 u32 val32; 2761 u32 i; 2762 2763 info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel); 2764 if (!info) { 2765 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 2766 return -EINVAL; 2767 } 2768 2769 #define case_DBG_SEL(__sel) \ 2770 case RTW89_DBG_PORT_SEL_##__sel: \ 2771 seq_puts(m, "Dump debug port " #__sel ":\n"); \ 2772 break 2773 2774 switch (sel) { 2775 case_DBG_SEL(PTCL_C0); 2776 case_DBG_SEL(PTCL_C1); 2777 case_DBG_SEL(SCH_C0); 2778 case_DBG_SEL(SCH_C1); 2779 case_DBG_SEL(TMAC_C0); 2780 case_DBG_SEL(TMAC_C1); 2781 case_DBG_SEL(RMAC_C0); 2782 case_DBG_SEL(RMAC_C1); 2783 case_DBG_SEL(RMACST_C0); 2784 case_DBG_SEL(RMACST_C1); 2785 case_DBG_SEL(TRXPTCL_C0); 2786 case_DBG_SEL(TRXPTCL_C1); 2787 case_DBG_SEL(TX_INFOL_C0); 2788 case_DBG_SEL(TX_INFOH_C0); 2789 case_DBG_SEL(TX_INFOL_C1); 2790 case_DBG_SEL(TX_INFOH_C1); 2791 case_DBG_SEL(TXTF_INFOL_C0); 2792 case_DBG_SEL(TXTF_INFOH_C0); 2793 case_DBG_SEL(TXTF_INFOL_C1); 2794 case_DBG_SEL(TXTF_INFOH_C1); 2795 case_DBG_SEL(WDE_BUFMGN_FREEPG); 2796 case_DBG_SEL(WDE_BUFMGN_QUOTA); 2797 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 2798 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 2799 case_DBG_SEL(WDE_QUEMGN_PREPKT); 2800 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 2801 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 2802 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 2803 case_DBG_SEL(PLE_BUFMGN_FREEPG); 2804 case_DBG_SEL(PLE_BUFMGN_QUOTA); 2805 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 2806 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 2807 case_DBG_SEL(PLE_QUEMGN_PREPKT); 2808 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 2809 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 2810 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 2811 case_DBG_SEL(PKTINFO); 2812 case_DBG_SEL(DSPT_HDT_TX0); 2813 case_DBG_SEL(DSPT_HDT_TX1); 2814 case_DBG_SEL(DSPT_HDT_TX2); 2815 case_DBG_SEL(DSPT_HDT_TX3); 2816 case_DBG_SEL(DSPT_HDT_TX4); 2817 case_DBG_SEL(DSPT_HDT_TX5); 2818 case_DBG_SEL(DSPT_HDT_TX6); 2819 case_DBG_SEL(DSPT_HDT_TX7); 2820 case_DBG_SEL(DSPT_HDT_TX8); 2821 case_DBG_SEL(DSPT_HDT_TX9); 2822 case_DBG_SEL(DSPT_HDT_TXA); 2823 case_DBG_SEL(DSPT_HDT_TXB); 2824 case_DBG_SEL(DSPT_HDT_TXC); 2825 case_DBG_SEL(DSPT_HDT_TXD); 2826 case_DBG_SEL(DSPT_HDT_TXE); 2827 case_DBG_SEL(DSPT_HDT_TXF); 2828 case_DBG_SEL(DSPT_CDT_TX0); 2829 case_DBG_SEL(DSPT_CDT_TX1); 2830 case_DBG_SEL(DSPT_CDT_TX3); 2831 case_DBG_SEL(DSPT_CDT_TX4); 2832 case_DBG_SEL(DSPT_CDT_TX5); 2833 case_DBG_SEL(DSPT_CDT_TX6); 2834 case_DBG_SEL(DSPT_CDT_TX7); 2835 case_DBG_SEL(DSPT_CDT_TX8); 2836 case_DBG_SEL(DSPT_CDT_TX9); 2837 case_DBG_SEL(DSPT_CDT_TXA); 2838 case_DBG_SEL(DSPT_CDT_TXB); 2839 case_DBG_SEL(DSPT_CDT_TXC); 2840 case_DBG_SEL(DSPT_HDT_RX0); 2841 case_DBG_SEL(DSPT_HDT_RX1); 2842 case_DBG_SEL(DSPT_HDT_RX2); 2843 case_DBG_SEL(DSPT_HDT_RX3); 2844 case_DBG_SEL(DSPT_HDT_RX4); 2845 case_DBG_SEL(DSPT_HDT_RX5); 2846 case_DBG_SEL(DSPT_CDT_RX_P0); 2847 case_DBG_SEL(DSPT_CDT_RX_P0_0); 2848 case_DBG_SEL(DSPT_CDT_RX_P0_1); 2849 case_DBG_SEL(DSPT_CDT_RX_P0_2); 2850 case_DBG_SEL(DSPT_CDT_RX_P1); 2851 case_DBG_SEL(DSPT_STF_CTRL); 2852 case_DBG_SEL(DSPT_ADDR_CTRL); 2853 case_DBG_SEL(DSPT_WDE_INTF); 2854 case_DBG_SEL(DSPT_PLE_INTF); 2855 case_DBG_SEL(DSPT_FLOW_CTRL); 2856 case_DBG_SEL(PCIE_TXDMA); 2857 case_DBG_SEL(PCIE_RXDMA); 2858 case_DBG_SEL(PCIE_CVT); 2859 case_DBG_SEL(PCIE_CXPL); 2860 case_DBG_SEL(PCIE_IO); 2861 case_DBG_SEL(PCIE_MISC); 2862 case_DBG_SEL(PCIE_MISC2); 2863 } 2864 2865 #undef case_DBG_SEL 2866 2867 seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr); 2868 seq_printf(m, "Read addr = 0x%X\n", info->rd_addr); 2869 2870 for (i = info->srt; i <= info->end; i++) { 2871 switch (info->sel_byte) { 2872 case 1: 2873 default: 2874 rtw89_write8_mask(rtwdev, info->sel_addr, 2875 info->sel_msk, i); 2876 seq_printf(m, "0x%02X: ", i); 2877 break; 2878 case 2: 2879 rtw89_write16_mask(rtwdev, info->sel_addr, 2880 info->sel_msk, i); 2881 seq_printf(m, "0x%04X: ", i); 2882 break; 2883 case 4: 2884 rtw89_write32_mask(rtwdev, info->sel_addr, 2885 info->sel_msk, i); 2886 seq_printf(m, "0x%04X: ", i); 2887 break; 2888 } 2889 2890 udelay(10); 2891 2892 switch (info->rd_byte) { 2893 case 1: 2894 default: 2895 val8 = rtw89_read8_mask(rtwdev, 2896 info->rd_addr, info->rd_msk); 2897 seq_printf(m, "0x%02X\n", val8); 2898 break; 2899 case 2: 2900 val16 = rtw89_read16_mask(rtwdev, 2901 info->rd_addr, info->rd_msk); 2902 seq_printf(m, "0x%04X\n", val16); 2903 break; 2904 case 4: 2905 val32 = rtw89_read32_mask(rtwdev, 2906 info->rd_addr, info->rd_msk); 2907 seq_printf(m, "0x%08X\n", val32); 2908 break; 2909 } 2910 } 2911 2912 return 0; 2913 } 2914 2915 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 2916 struct seq_file *m) 2917 { 2918 u32 sel; 2919 int ret = 0; 2920 2921 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 2922 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 2923 if (!is_dbg_port_valid(rtwdev, sel)) 2924 continue; 2925 ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel); 2926 if (ret) { 2927 rtw89_err(rtwdev, 2928 "failed to dump debug port %d\n", sel); 2929 break; 2930 } 2931 } 2932 2933 return ret; 2934 } 2935 2936 static int 2937 rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v) 2938 { 2939 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2940 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2941 2942 if (debugfs_priv->dbgpkg_en.ss_dbg) 2943 rtw89_debug_mac_dump_ss_dbg(rtwdev, m); 2944 if (debugfs_priv->dbgpkg_en.dle_dbg) 2945 rtw89_debug_mac_dump_dle_dbg(rtwdev, m); 2946 if (debugfs_priv->dbgpkg_en.dmac_dbg) 2947 rtw89_debug_mac_dump_dmac_dbg(rtwdev, m); 2948 if (debugfs_priv->dbgpkg_en.cmac_dbg) 2949 rtw89_debug_mac_dump_cmac_dbg(rtwdev, m); 2950 if (debugfs_priv->dbgpkg_en.dbg_port) 2951 rtw89_debug_mac_dump_dbg_port(rtwdev, m); 2952 2953 return 0; 2954 }; 2955 2956 static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev, 2957 const char __user *user_buf, size_t count) 2958 { 2959 char *buf; 2960 u8 *bin; 2961 int num; 2962 int err = 0; 2963 2964 buf = memdup_user(user_buf, count); 2965 if (IS_ERR(buf)) 2966 return buf; 2967 2968 num = count / 2; 2969 bin = kmalloc(num, GFP_KERNEL); 2970 if (!bin) { 2971 err = -EFAULT; 2972 goto out; 2973 } 2974 2975 if (hex2bin(bin, buf, num)) { 2976 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 2977 kfree(bin); 2978 err = -EINVAL; 2979 } 2980 2981 out: 2982 kfree(buf); 2983 2984 return err ? ERR_PTR(err) : bin; 2985 } 2986 2987 static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp, 2988 const char __user *user_buf, 2989 size_t count, loff_t *loff) 2990 { 2991 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 2992 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2993 u8 *h2c; 2994 u16 h2c_len = count / 2; 2995 2996 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 2997 if (IS_ERR(h2c)) 2998 return -EFAULT; 2999 3000 rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 3001 3002 kfree(h2c); 3003 3004 return count; 3005 } 3006 3007 static int 3008 rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v) 3009 { 3010 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3011 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3012 struct rtw89_early_h2c *early_h2c; 3013 int seq = 0; 3014 3015 mutex_lock(&rtwdev->mutex); 3016 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 3017 seq_printf(m, "%d: %*ph\n", ++seq, early_h2c->h2c_len, early_h2c->h2c); 3018 mutex_unlock(&rtwdev->mutex); 3019 3020 return 0; 3021 } 3022 3023 static ssize_t 3024 rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf, 3025 size_t count, loff_t *loff) 3026 { 3027 struct seq_file *m = (struct seq_file *)filp->private_data; 3028 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3029 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3030 struct rtw89_early_h2c *early_h2c; 3031 u8 *h2c; 3032 u16 h2c_len = count / 2; 3033 3034 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 3035 if (IS_ERR(h2c)) 3036 return -EFAULT; 3037 3038 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 3039 kfree(h2c); 3040 rtw89_fw_free_all_early_h2c(rtwdev); 3041 goto out; 3042 } 3043 3044 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL); 3045 if (!early_h2c) { 3046 kfree(h2c); 3047 return -EFAULT; 3048 } 3049 3050 early_h2c->h2c = h2c; 3051 early_h2c->h2c_len = h2c_len; 3052 3053 mutex_lock(&rtwdev->mutex); 3054 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 3055 mutex_unlock(&rtwdev->mutex); 3056 3057 out: 3058 return count; 3059 } 3060 3061 static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev) 3062 { 3063 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3064 u16 pkt_id; 3065 3066 rtw89_leave_ps_mode(rtwdev); 3067 3068 pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, true); 3069 switch (pkt_id) { 3070 case 0xffff: 3071 return -ETIMEDOUT; 3072 case 0xfff: 3073 return -ENOMEM; 3074 default: 3075 break; 3076 } 3077 3078 /* intentionally, enqueue two pkt, but has only one pkt id */ 3079 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3080 ctrl_para.start_pktid = pkt_id; 3081 ctrl_para.end_pktid = pkt_id; 3082 ctrl_para.pkt_num = 1; /* start from 0 */ 3083 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3084 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3085 3086 if (rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true)) 3087 return -EFAULT; 3088 3089 return 0; 3090 } 3091 3092 static int 3093 rtw89_debug_priv_fw_crash_get(struct seq_file *m, void *v) 3094 { 3095 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3096 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3097 3098 seq_printf(m, "%d\n", 3099 test_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags)); 3100 return 0; 3101 } 3102 3103 enum rtw89_dbg_crash_simulation_type { 3104 RTW89_DBG_SIM_CPU_EXCEPTION = 1, 3105 RTW89_DBG_SIM_CTRL_ERROR = 2, 3106 }; 3107 3108 static ssize_t 3109 rtw89_debug_priv_fw_crash_set(struct file *filp, const char __user *user_buf, 3110 size_t count, loff_t *loff) 3111 { 3112 struct seq_file *m = (struct seq_file *)filp->private_data; 3113 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3114 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3115 int (*sim)(struct rtw89_dev *rtwdev); 3116 u8 crash_type; 3117 int ret; 3118 3119 ret = kstrtou8_from_user(user_buf, count, 0, &crash_type); 3120 if (ret) 3121 return -EINVAL; 3122 3123 switch (crash_type) { 3124 case RTW89_DBG_SIM_CPU_EXCEPTION: 3125 if (!RTW89_CHK_FW_FEATURE(CRASH_TRIGGER, &rtwdev->fw)) 3126 return -EOPNOTSUPP; 3127 sim = rtw89_fw_h2c_trigger_cpu_exception; 3128 break; 3129 case RTW89_DBG_SIM_CTRL_ERROR: 3130 sim = rtw89_dbg_trigger_ctrl_error; 3131 break; 3132 default: 3133 return -EINVAL; 3134 } 3135 3136 mutex_lock(&rtwdev->mutex); 3137 set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags); 3138 ret = sim(rtwdev); 3139 mutex_unlock(&rtwdev->mutex); 3140 3141 if (ret) 3142 return ret; 3143 3144 return count; 3145 } 3146 3147 static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v) 3148 { 3149 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3150 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3151 3152 rtw89_btc_dump_info(rtwdev, m); 3153 3154 return 0; 3155 } 3156 3157 static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp, 3158 const char __user *user_buf, 3159 size_t count, loff_t *loff) 3160 { 3161 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3162 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3163 struct rtw89_btc *btc = &rtwdev->btc; 3164 bool btc_manual; 3165 3166 if (kstrtobool_from_user(user_buf, count, &btc_manual)) 3167 goto out; 3168 3169 btc->ctrl.manual = btc_manual; 3170 out: 3171 return count; 3172 } 3173 3174 static ssize_t rtw89_debug_fw_log_btc_manual_set(struct file *filp, 3175 const char __user *user_buf, 3176 size_t count, loff_t *loff) 3177 { 3178 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3179 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3180 struct rtw89_fw_info *fw_info = &rtwdev->fw; 3181 bool fw_log_manual; 3182 3183 if (kstrtobool_from_user(user_buf, count, &fw_log_manual)) 3184 goto out; 3185 3186 mutex_lock(&rtwdev->mutex); 3187 fw_info->fw_log_enable = fw_log_manual; 3188 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 3189 mutex_unlock(&rtwdev->mutex); 3190 out: 3191 return count; 3192 } 3193 3194 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 3195 { 3196 static const char * const he_gi_str[] = { 3197 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 3198 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 3199 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 3200 }; 3201 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3202 struct rate_info *rate = &rtwsta->ra_report.txrate; 3203 struct ieee80211_rx_status *status = &rtwsta->rx_status; 3204 struct seq_file *m = (struct seq_file *)data; 3205 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3206 struct rtw89_hal *hal = &rtwdev->hal; 3207 u8 rssi; 3208 int i; 3209 3210 seq_printf(m, "TX rate [%d]: ", rtwsta->mac_id); 3211 3212 if (rate->flags & RATE_INFO_FLAGS_MCS) 3213 seq_printf(m, "HT MCS-%d%s", rate->mcs, 3214 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3215 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 3216 seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs, 3217 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3218 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 3219 seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs, 3220 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3221 he_gi_str[rate->he_gi] : "N/A"); 3222 else 3223 seq_printf(m, "Legacy %d", rate->legacy); 3224 seq_printf(m, "%s", rtwsta->ra_report.might_fallback_legacy ? " FB_G" : ""); 3225 seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(rate->bw)); 3226 seq_printf(m, "\t(hw_rate=0x%x)", rtwsta->ra_report.hw_rate); 3227 seq_printf(m, "\t==> agg_wait=%d (%d)\n", rtwsta->max_agg_wait, 3228 sta->deflink.agg.max_rc_amsdu_len); 3229 3230 seq_printf(m, "RX rate [%d]: ", rtwsta->mac_id); 3231 3232 switch (status->encoding) { 3233 case RX_ENC_LEGACY: 3234 seq_printf(m, "Legacy %d", status->rate_idx + 3235 (status->band != NL80211_BAND_2GHZ ? 4 : 0)); 3236 break; 3237 case RX_ENC_HT: 3238 seq_printf(m, "HT MCS-%d%s", status->rate_idx, 3239 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3240 break; 3241 case RX_ENC_VHT: 3242 seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx, 3243 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3244 break; 3245 case RX_ENC_HE: 3246 seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx, 3247 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3248 he_gi_str[rate->he_gi] : "N/A"); 3249 break; 3250 } 3251 seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(status->bw)); 3252 seq_printf(m, "\t(hw_rate=0x%x)\n", rtwsta->rx_hw_rate); 3253 3254 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 3255 seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d) [", 3256 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta->prev_rssi); 3257 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 3258 rssi = ewma_rssi_read(&rtwsta->rssi[i]); 3259 seq_printf(m, "%d%s%s", RTW89_RSSI_RAW_TO_DBM(rssi), 3260 hal->tx_path_diversity && (hal->antenna_tx & BIT(i)) ? "*" : "", 3261 i + 1 == rtwdev->chip->rf_path_num ? "" : ", "); 3262 } 3263 seq_puts(m, "]\n"); 3264 } 3265 3266 static void 3267 rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat, 3268 enum rtw89_hw_rate first_rate, int len) 3269 { 3270 int i; 3271 3272 for (i = 0; i < len; i++) 3273 seq_printf(m, "%s%u", i == 0 ? "" : ", ", 3274 pkt_stat->rx_rate_cnt[first_rate + i]); 3275 } 3276 3277 static const struct rtw89_rx_rate_cnt_info { 3278 enum rtw89_hw_rate first_rate; 3279 int len; 3280 int ext; 3281 const char *rate_mode; 3282 } rtw89_rx_rate_cnt_infos[] = { 3283 {RTW89_HW_RATE_CCK1, 4, 0, "Legacy:"}, 3284 {RTW89_HW_RATE_OFDM6, 8, 0, "OFDM:"}, 3285 {RTW89_HW_RATE_MCS0, 8, 0, "HT 0:"}, 3286 {RTW89_HW_RATE_MCS8, 8, 0, "HT 1:"}, 3287 {RTW89_HW_RATE_VHT_NSS1_MCS0, 10, 2, "VHT 1SS:"}, 3288 {RTW89_HW_RATE_VHT_NSS2_MCS0, 10, 2, "VHT 2SS:"}, 3289 {RTW89_HW_RATE_HE_NSS1_MCS0, 12, 0, "HE 1SS:"}, 3290 {RTW89_HW_RATE_HE_NSS2_MCS0, 12, 0, "HE 2ss:"}, 3291 }; 3292 3293 static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v) 3294 { 3295 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3296 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3297 struct rtw89_traffic_stats *stats = &rtwdev->stats; 3298 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 3299 const struct rtw89_rx_rate_cnt_info *info; 3300 int i; 3301 3302 seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d), RX: %u [%u] Mbps (lv: %d)\n", 3303 stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv, 3304 stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv); 3305 seq_printf(m, "Beacon: %u, TF: %u\n", pkt_stat->beacon_nr, 3306 stats->rx_tf_periodic); 3307 seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len, 3308 stats->rx_avg_len); 3309 3310 seq_puts(m, "RX count:\n"); 3311 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 3312 info = &rtw89_rx_rate_cnt_infos[i]; 3313 seq_printf(m, "%10s [", info->rate_mode); 3314 rtw89_debug_append_rx_rate(m, pkt_stat, 3315 info->first_rate, info->len); 3316 if (info->ext) { 3317 seq_puts(m, "]["); 3318 rtw89_debug_append_rx_rate(m, pkt_stat, 3319 info->first_rate + info->len, info->ext); 3320 } 3321 seq_puts(m, "]\n"); 3322 } 3323 3324 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m); 3325 3326 return 0; 3327 } 3328 3329 static void rtw89_dump_addr_cam(struct seq_file *m, 3330 struct rtw89_addr_cam_entry *addr_cam) 3331 { 3332 struct rtw89_sec_cam_entry *sec_entry; 3333 int i; 3334 3335 seq_printf(m, "\taddr_cam_idx=%u\n", addr_cam->addr_cam_idx); 3336 seq_printf(m, "\t-> bssid_cam_idx=%u\n", addr_cam->bssid_cam_idx); 3337 seq_printf(m, "\tsec_cam_bitmap=%*ph\n", (int)sizeof(addr_cam->sec_cam_map), 3338 addr_cam->sec_cam_map); 3339 for (i = 0; i < RTW89_SEC_CAM_IN_ADDR_CAM; i++) { 3340 sec_entry = addr_cam->sec_entries[i]; 3341 if (!sec_entry) 3342 continue; 3343 seq_printf(m, "\tsec[%d]: sec_cam_idx %u", i, sec_entry->sec_cam_idx); 3344 if (sec_entry->ext_key) 3345 seq_printf(m, ", %u", sec_entry->sec_cam_idx + 1); 3346 seq_puts(m, "\n"); 3347 } 3348 } 3349 3350 static 3351 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 3352 { 3353 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3354 struct seq_file *m = (struct seq_file *)data; 3355 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam; 3356 3357 seq_printf(m, "VIF [%d] %pM\n", rtwvif->mac_id, rtwvif->mac_addr); 3358 seq_printf(m, "\tbssid_cam_idx=%u\n", bssid_cam->bssid_cam_idx); 3359 rtw89_dump_addr_cam(m, &rtwvif->addr_cam); 3360 } 3361 3362 static void rtw89_dump_ba_cam(struct seq_file *m, struct rtw89_sta *rtwsta) 3363 { 3364 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 3365 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 3366 struct rtw89_ba_cam_entry *entry; 3367 bool first = true; 3368 3369 list_for_each_entry(entry, &rtwsta->ba_cam_list, list) { 3370 if (first) { 3371 seq_puts(m, "\tba_cam "); 3372 first = false; 3373 } else { 3374 seq_puts(m, ", "); 3375 } 3376 seq_printf(m, "tid[%u]=%d", entry->tid, 3377 (int)(entry - rtwdev->cam_info.ba_cam_entry)); 3378 } 3379 seq_puts(m, "\n"); 3380 } 3381 3382 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta) 3383 { 3384 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3385 struct seq_file *m = (struct seq_file *)data; 3386 3387 seq_printf(m, "STA [%d] %pM %s\n", rtwsta->mac_id, sta->addr, 3388 sta->tdls ? "(TDLS)" : ""); 3389 rtw89_dump_addr_cam(m, &rtwsta->addr_cam); 3390 rtw89_dump_ba_cam(m, rtwsta); 3391 } 3392 3393 static int rtw89_debug_priv_stations_get(struct seq_file *m, void *v) 3394 { 3395 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3396 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3397 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3398 3399 mutex_lock(&rtwdev->mutex); 3400 3401 seq_puts(m, "map:\n"); 3402 seq_printf(m, "\tmac_id: %*ph\n", (int)sizeof(rtwdev->mac_id_map), 3403 rtwdev->mac_id_map); 3404 seq_printf(m, "\taddr_cam: %*ph\n", (int)sizeof(cam_info->addr_cam_map), 3405 cam_info->addr_cam_map); 3406 seq_printf(m, "\tbssid_cam: %*ph\n", (int)sizeof(cam_info->bssid_cam_map), 3407 cam_info->bssid_cam_map); 3408 seq_printf(m, "\tsec_cam: %*ph\n", (int)sizeof(cam_info->sec_cam_map), 3409 cam_info->sec_cam_map); 3410 seq_printf(m, "\tba_cam: %*ph\n", (int)sizeof(cam_info->ba_cam_map), 3411 cam_info->ba_cam_map); 3412 3413 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw, 3414 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, m); 3415 3416 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, m); 3417 3418 mutex_unlock(&rtwdev->mutex); 3419 3420 return 0; 3421 } 3422 3423 static struct rtw89_debugfs_priv rtw89_debug_priv_read_reg = { 3424 .cb_read = rtw89_debug_priv_read_reg_get, 3425 .cb_write = rtw89_debug_priv_read_reg_select, 3426 }; 3427 3428 static struct rtw89_debugfs_priv rtw89_debug_priv_write_reg = { 3429 .cb_write = rtw89_debug_priv_write_reg_set, 3430 }; 3431 3432 static struct rtw89_debugfs_priv rtw89_debug_priv_read_rf = { 3433 .cb_read = rtw89_debug_priv_read_rf_get, 3434 .cb_write = rtw89_debug_priv_read_rf_select, 3435 }; 3436 3437 static struct rtw89_debugfs_priv rtw89_debug_priv_write_rf = { 3438 .cb_write = rtw89_debug_priv_write_rf_set, 3439 }; 3440 3441 static struct rtw89_debugfs_priv rtw89_debug_priv_rf_reg_dump = { 3442 .cb_read = rtw89_debug_priv_rf_reg_dump_get, 3443 }; 3444 3445 static struct rtw89_debugfs_priv rtw89_debug_priv_txpwr_table = { 3446 .cb_read = rtw89_debug_priv_txpwr_table_get, 3447 }; 3448 3449 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_reg_dump = { 3450 .cb_read = rtw89_debug_priv_mac_reg_dump_get, 3451 .cb_write = rtw89_debug_priv_mac_reg_dump_select, 3452 }; 3453 3454 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_mem_dump = { 3455 .cb_read = rtw89_debug_priv_mac_mem_dump_get, 3456 .cb_write = rtw89_debug_priv_mac_mem_dump_select, 3457 }; 3458 3459 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_dbg_port_dump = { 3460 .cb_read = rtw89_debug_priv_mac_dbg_port_dump_get, 3461 .cb_write = rtw89_debug_priv_mac_dbg_port_dump_select, 3462 }; 3463 3464 static struct rtw89_debugfs_priv rtw89_debug_priv_send_h2c = { 3465 .cb_write = rtw89_debug_priv_send_h2c_set, 3466 }; 3467 3468 static struct rtw89_debugfs_priv rtw89_debug_priv_early_h2c = { 3469 .cb_read = rtw89_debug_priv_early_h2c_get, 3470 .cb_write = rtw89_debug_priv_early_h2c_set, 3471 }; 3472 3473 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_crash = { 3474 .cb_read = rtw89_debug_priv_fw_crash_get, 3475 .cb_write = rtw89_debug_priv_fw_crash_set, 3476 }; 3477 3478 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_info = { 3479 .cb_read = rtw89_debug_priv_btc_info_get, 3480 }; 3481 3482 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_manual = { 3483 .cb_write = rtw89_debug_priv_btc_manual_set, 3484 }; 3485 3486 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_log_manual = { 3487 .cb_write = rtw89_debug_fw_log_btc_manual_set, 3488 }; 3489 3490 static struct rtw89_debugfs_priv rtw89_debug_priv_phy_info = { 3491 .cb_read = rtw89_debug_priv_phy_info_get, 3492 }; 3493 3494 static struct rtw89_debugfs_priv rtw89_debug_priv_stations = { 3495 .cb_read = rtw89_debug_priv_stations_get, 3496 }; 3497 3498 #define rtw89_debugfs_add(name, mode, fopname, parent) \ 3499 do { \ 3500 rtw89_debug_priv_ ##name.rtwdev = rtwdev; \ 3501 if (!debugfs_create_file(#name, mode, \ 3502 parent, &rtw89_debug_priv_ ##name, \ 3503 &file_ops_ ##fopname)) \ 3504 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 3505 } while (0) 3506 3507 #define rtw89_debugfs_add_w(name) \ 3508 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 3509 #define rtw89_debugfs_add_rw(name) \ 3510 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 3511 #define rtw89_debugfs_add_r(name) \ 3512 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 3513 3514 void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 3515 { 3516 struct dentry *debugfs_topdir; 3517 3518 debugfs_topdir = debugfs_create_dir("rtw89", 3519 rtwdev->hw->wiphy->debugfsdir); 3520 3521 rtw89_debugfs_add_rw(read_reg); 3522 rtw89_debugfs_add_w(write_reg); 3523 rtw89_debugfs_add_rw(read_rf); 3524 rtw89_debugfs_add_w(write_rf); 3525 rtw89_debugfs_add_r(rf_reg_dump); 3526 rtw89_debugfs_add_r(txpwr_table); 3527 rtw89_debugfs_add_rw(mac_reg_dump); 3528 rtw89_debugfs_add_rw(mac_mem_dump); 3529 rtw89_debugfs_add_rw(mac_dbg_port_dump); 3530 rtw89_debugfs_add_w(send_h2c); 3531 rtw89_debugfs_add_rw(early_h2c); 3532 rtw89_debugfs_add_rw(fw_crash); 3533 rtw89_debugfs_add_r(btc_info); 3534 rtw89_debugfs_add_w(btc_manual); 3535 rtw89_debugfs_add_w(fw_log_manual); 3536 rtw89_debugfs_add_r(phy_info); 3537 rtw89_debugfs_add_r(stations); 3538 } 3539 #endif 3540 3541 #ifdef CONFIG_RTW89_DEBUGMSG 3542 void __rtw89_debug(struct rtw89_dev *rtwdev, 3543 enum rtw89_debug_mask mask, 3544 const char *fmt, ...) 3545 { 3546 struct va_format vaf = { 3547 .fmt = fmt, 3548 }; 3549 3550 va_list args; 3551 3552 va_start(args, fmt); 3553 vaf.va = &args; 3554 3555 if (rtw89_debug_mask & mask) 3556 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 3557 3558 va_end(args); 3559 } 3560 EXPORT_SYMBOL(__rtw89_debug); 3561 #endif 3562