1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "debug.h" 7 #include "fw.h" 8 #include "mac.h" 9 #include "ps.h" 10 #include "reg.h" 11 #include "sar.h" 12 13 #ifdef CONFIG_RTW89_DEBUGMSG 14 unsigned int rtw89_debug_mask; 15 EXPORT_SYMBOL(rtw89_debug_mask); 16 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 17 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 18 #endif 19 20 #ifdef CONFIG_RTW89_DEBUGFS 21 struct rtw89_debugfs_priv { 22 struct rtw89_dev *rtwdev; 23 int (*cb_read)(struct seq_file *m, void *v); 24 ssize_t (*cb_write)(struct file *filp, const char __user *buffer, 25 size_t count, loff_t *loff); 26 union { 27 u32 cb_data; 28 struct { 29 u32 addr; 30 u8 len; 31 } read_reg; 32 struct { 33 u32 addr; 34 u32 mask; 35 u8 path; 36 } read_rf; 37 struct { 38 u8 ss_dbg:1; 39 u8 dle_dbg:1; 40 u8 dmac_dbg:1; 41 u8 cmac_dbg:1; 42 u8 dbg_port:1; 43 } dbgpkg_en; 44 struct { 45 u32 start; 46 u32 len; 47 u8 sel; 48 } mac_mem; 49 }; 50 }; 51 52 static int rtw89_debugfs_single_show(struct seq_file *m, void *v) 53 { 54 struct rtw89_debugfs_priv *debugfs_priv = m->private; 55 56 return debugfs_priv->cb_read(m, v); 57 } 58 59 static ssize_t rtw89_debugfs_single_write(struct file *filp, 60 const char __user *buffer, 61 size_t count, loff_t *loff) 62 { 63 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 64 65 return debugfs_priv->cb_write(filp, buffer, count, loff); 66 } 67 68 static ssize_t rtw89_debugfs_seq_file_write(struct file *filp, 69 const char __user *buffer, 70 size_t count, loff_t *loff) 71 { 72 struct seq_file *seqpriv = (struct seq_file *)filp->private_data; 73 struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private; 74 75 return debugfs_priv->cb_write(filp, buffer, count, loff); 76 } 77 78 static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp) 79 { 80 return single_open(filp, rtw89_debugfs_single_show, inode->i_private); 81 } 82 83 static int rtw89_debugfs_close(struct inode *inode, struct file *filp) 84 { 85 return 0; 86 } 87 88 static const struct file_operations file_ops_single_r = { 89 .owner = THIS_MODULE, 90 .open = rtw89_debugfs_single_open, 91 .read = seq_read, 92 .llseek = seq_lseek, 93 .release = single_release, 94 }; 95 96 static const struct file_operations file_ops_common_rw = { 97 .owner = THIS_MODULE, 98 .open = rtw89_debugfs_single_open, 99 .release = single_release, 100 .read = seq_read, 101 .llseek = seq_lseek, 102 .write = rtw89_debugfs_seq_file_write, 103 }; 104 105 static const struct file_operations file_ops_single_w = { 106 .owner = THIS_MODULE, 107 .write = rtw89_debugfs_single_write, 108 .open = simple_open, 109 .release = rtw89_debugfs_close, 110 }; 111 112 static ssize_t 113 rtw89_debug_priv_read_reg_select(struct file *filp, 114 const char __user *user_buf, 115 size_t count, loff_t *loff) 116 { 117 struct seq_file *m = (struct seq_file *)filp->private_data; 118 struct rtw89_debugfs_priv *debugfs_priv = m->private; 119 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 120 char buf[32]; 121 size_t buf_size; 122 u32 addr, len; 123 int num; 124 125 buf_size = min(count, sizeof(buf) - 1); 126 if (copy_from_user(buf, user_buf, buf_size)) 127 return -EFAULT; 128 129 buf[buf_size] = '\0'; 130 num = sscanf(buf, "%x %x", &addr, &len); 131 if (num != 2) { 132 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 133 return -EINVAL; 134 } 135 136 debugfs_priv->read_reg.addr = addr; 137 debugfs_priv->read_reg.len = len; 138 139 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 140 141 return count; 142 } 143 144 static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v) 145 { 146 struct rtw89_debugfs_priv *debugfs_priv = m->private; 147 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 148 u32 addr, data; 149 u8 len; 150 151 len = debugfs_priv->read_reg.len; 152 addr = debugfs_priv->read_reg.addr; 153 154 switch (len) { 155 case 1: 156 data = rtw89_read8(rtwdev, addr); 157 break; 158 case 2: 159 data = rtw89_read16(rtwdev, addr); 160 break; 161 case 4: 162 data = rtw89_read32(rtwdev, addr); 163 break; 164 default: 165 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 166 return -EINVAL; 167 } 168 169 seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data); 170 171 return 0; 172 } 173 174 static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp, 175 const char __user *user_buf, 176 size_t count, loff_t *loff) 177 { 178 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 179 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 180 char buf[32]; 181 size_t buf_size; 182 u32 addr, val, len; 183 int num; 184 185 buf_size = min(count, sizeof(buf) - 1); 186 if (copy_from_user(buf, user_buf, buf_size)) 187 return -EFAULT; 188 189 buf[buf_size] = '\0'; 190 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 191 if (num != 3) { 192 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 193 return -EINVAL; 194 } 195 196 switch (len) { 197 case 1: 198 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 199 rtw89_write8(rtwdev, addr, (u8)val); 200 break; 201 case 2: 202 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 203 rtw89_write16(rtwdev, addr, (u16)val); 204 break; 205 case 4: 206 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 207 rtw89_write32(rtwdev, addr, (u32)val); 208 break; 209 default: 210 rtw89_info(rtwdev, "invalid read write len %d\n", len); 211 break; 212 } 213 214 return count; 215 } 216 217 static ssize_t 218 rtw89_debug_priv_read_rf_select(struct file *filp, 219 const char __user *user_buf, 220 size_t count, loff_t *loff) 221 { 222 struct seq_file *m = (struct seq_file *)filp->private_data; 223 struct rtw89_debugfs_priv *debugfs_priv = m->private; 224 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 225 char buf[32]; 226 size_t buf_size; 227 u32 addr, mask; 228 u8 path; 229 int num; 230 231 buf_size = min(count, sizeof(buf) - 1); 232 if (copy_from_user(buf, user_buf, buf_size)) 233 return -EFAULT; 234 235 buf[buf_size] = '\0'; 236 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 237 if (num != 3) { 238 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 239 return -EINVAL; 240 } 241 242 if (path >= rtwdev->chip->rf_path_num) { 243 rtw89_info(rtwdev, "wrong rf path\n"); 244 return -EINVAL; 245 } 246 debugfs_priv->read_rf.addr = addr; 247 debugfs_priv->read_rf.mask = mask; 248 debugfs_priv->read_rf.path = path; 249 250 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 251 252 return count; 253 } 254 255 static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v) 256 { 257 struct rtw89_debugfs_priv *debugfs_priv = m->private; 258 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 259 u32 addr, data, mask; 260 u8 path; 261 262 addr = debugfs_priv->read_rf.addr; 263 mask = debugfs_priv->read_rf.mask; 264 path = debugfs_priv->read_rf.path; 265 266 data = rtw89_read_rf(rtwdev, path, addr, mask); 267 268 seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data); 269 270 return 0; 271 } 272 273 static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp, 274 const char __user *user_buf, 275 size_t count, loff_t *loff) 276 { 277 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 278 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 279 char buf[32]; 280 size_t buf_size; 281 u32 addr, val, mask; 282 u8 path; 283 int num; 284 285 buf_size = min(count, sizeof(buf) - 1); 286 if (copy_from_user(buf, user_buf, buf_size)) 287 return -EFAULT; 288 289 buf[buf_size] = '\0'; 290 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 291 if (num != 4) { 292 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 293 return -EINVAL; 294 } 295 296 if (path >= rtwdev->chip->rf_path_num) { 297 rtw89_info(rtwdev, "wrong rf path\n"); 298 return -EINVAL; 299 } 300 301 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 302 path, addr, val, mask); 303 rtw89_write_rf(rtwdev, path, addr, mask, val); 304 305 return count; 306 } 307 308 static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v) 309 { 310 struct rtw89_debugfs_priv *debugfs_priv = m->private; 311 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 312 const struct rtw89_chip_info *chip = rtwdev->chip; 313 u32 addr, offset, data; 314 u8 path; 315 316 for (path = 0; path < chip->rf_path_num; path++) { 317 seq_printf(m, "RF path %d:\n\n", path); 318 for (addr = 0; addr < 0x100; addr += 4) { 319 seq_printf(m, "0x%08x: ", addr); 320 for (offset = 0; offset < 4; offset++) { 321 data = rtw89_read_rf(rtwdev, path, 322 addr + offset, RFREG_MASK); 323 seq_printf(m, "0x%05x ", data); 324 } 325 seq_puts(m, "\n"); 326 } 327 seq_puts(m, "\n"); 328 } 329 330 return 0; 331 } 332 333 struct txpwr_ent { 334 const char *txt; 335 u8 len; 336 }; 337 338 struct txpwr_map { 339 const struct txpwr_ent *ent; 340 u8 size; 341 u32 addr_from; 342 u32 addr_to; 343 }; 344 345 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 346 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 347 348 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 349 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 350 351 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 352 { .len = 8, .txt = _t "\t- " \ 353 _e0 " " _e1 " " _e2 " " _e3 " " \ 354 _e4 " " _e5 " " _e6 " " _e7 } 355 356 static const struct txpwr_ent __txpwr_ent_byr[] = { 357 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 358 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 359 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 360 /* 1NSS */ 361 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 362 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 363 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 364 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 365 /* 2NSS */ 366 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 367 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 368 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 369 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 370 }; 371 372 static_assert((ARRAY_SIZE(__txpwr_ent_byr) * 4) == 373 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 374 375 static const struct txpwr_map __txpwr_map_byr = { 376 .ent = __txpwr_ent_byr, 377 .size = ARRAY_SIZE(__txpwr_ent_byr), 378 .addr_from = R_AX_PWR_BY_RATE, 379 .addr_to = R_AX_PWR_BY_RATE_MAX, 380 }; 381 382 static const struct txpwr_ent __txpwr_ent_lmt[] = { 383 /* 1TX */ 384 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 385 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 386 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 387 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 388 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 389 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 390 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 391 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 392 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 393 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 394 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 395 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 396 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 397 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 398 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 399 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 400 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 401 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 402 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 403 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 404 /* 2TX */ 405 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 406 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 407 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 408 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 409 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 410 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 411 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 412 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 413 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 414 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 415 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 416 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 417 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 418 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 419 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 420 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 421 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 422 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 423 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 424 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 425 }; 426 427 static_assert((ARRAY_SIZE(__txpwr_ent_lmt) * 2) == 428 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 429 430 static const struct txpwr_map __txpwr_map_lmt = { 431 .ent = __txpwr_ent_lmt, 432 .size = ARRAY_SIZE(__txpwr_ent_lmt), 433 .addr_from = R_AX_PWR_LMT, 434 .addr_to = R_AX_PWR_LMT_MAX, 435 }; 436 437 static const struct txpwr_ent __txpwr_ent_lmt_ru[] = { 438 /* 1TX */ 439 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 440 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 441 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 442 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 443 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 444 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 445 /* 2TX */ 446 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 447 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 448 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 449 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 450 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 451 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 452 }; 453 454 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru) * 8) == 455 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 456 457 static const struct txpwr_map __txpwr_map_lmt_ru = { 458 .ent = __txpwr_ent_lmt_ru, 459 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru), 460 .addr_from = R_AX_PWR_RU_LMT, 461 .addr_to = R_AX_PWR_RU_LMT_MAX, 462 }; 463 464 static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent, 465 const u8 *buf, const u8 cur) 466 { 467 char *fmt; 468 469 switch (ent->len) { 470 case 2: 471 fmt = "%s\t| %3d, %3d,\tdBm\n"; 472 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]); 473 return 2; 474 case 4: 475 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 476 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 477 buf[cur + 2], buf[cur + 3]); 478 return 4; 479 case 8: 480 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 481 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 482 buf[cur + 2], buf[cur + 3], buf[cur + 4], 483 buf[cur + 5], buf[cur + 6], buf[cur + 7]); 484 return 8; 485 default: 486 return 0; 487 } 488 } 489 490 static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev, 491 const struct txpwr_map *map) 492 { 493 u8 fct = rtwdev->chip->txpwr_factor_mac; 494 u8 *buf, cur, i; 495 u32 val, addr; 496 int ret; 497 498 buf = vzalloc(map->addr_to - map->addr_from + 4); 499 if (!buf) 500 return -ENOMEM; 501 502 for (addr = map->addr_from; addr <= map->addr_to; addr += 4) { 503 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 504 if (ret) 505 val = MASKDWORD; 506 507 cur = addr - map->addr_from; 508 for (i = 0; i < 4; i++, val >>= 8) 509 buf[cur + i] = FIELD_GET(MASKBYTE0, val) >> fct; 510 } 511 512 for (cur = 0, i = 0; i < map->size; i++) 513 cur += __print_txpwr_ent(m, &map->ent[i], buf, cur); 514 515 vfree(buf); 516 return 0; 517 } 518 519 #define case_REGD(_regd) \ 520 case RTW89_ ## _regd: \ 521 seq_puts(m, #_regd "\n"); \ 522 break 523 524 static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev) 525 { 526 u8 band = rtwdev->hal.current_band_type; 527 u8 regd = rtw89_regd_get(rtwdev, band); 528 529 switch (regd) { 530 default: 531 seq_printf(m, "UNKNOWN: %d\n", regd); 532 break; 533 case_REGD(WW); 534 case_REGD(ETSI); 535 case_REGD(FCC); 536 case_REGD(MKK); 537 case_REGD(NA); 538 case_REGD(IC); 539 case_REGD(KCC); 540 case_REGD(NCC); 541 case_REGD(CHILE); 542 case_REGD(ACMA); 543 case_REGD(MEXICO); 544 case_REGD(UKRAINE); 545 case_REGD(CN); 546 } 547 } 548 549 #undef case_REGD 550 551 static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v) 552 { 553 struct rtw89_debugfs_priv *debugfs_priv = m->private; 554 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 555 int ret = 0; 556 557 mutex_lock(&rtwdev->mutex); 558 rtw89_leave_ps_mode(rtwdev); 559 560 seq_puts(m, "[Regulatory] "); 561 __print_regd(m, rtwdev); 562 563 seq_puts(m, "[SAR]\n"); 564 rtw89_print_sar(m, rtwdev); 565 566 seq_puts(m, "\n[TX power byrate]\n"); 567 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_byr); 568 if (ret) 569 goto err; 570 571 seq_puts(m, "\n[TX power limit]\n"); 572 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt); 573 if (ret) 574 goto err; 575 576 seq_puts(m, "\n[TX power limit_ru]\n"); 577 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt_ru); 578 if (ret) 579 goto err; 580 581 err: 582 mutex_unlock(&rtwdev->mutex); 583 return ret; 584 } 585 586 static ssize_t 587 rtw89_debug_priv_mac_reg_dump_select(struct file *filp, 588 const char __user *user_buf, 589 size_t count, loff_t *loff) 590 { 591 struct seq_file *m = (struct seq_file *)filp->private_data; 592 struct rtw89_debugfs_priv *debugfs_priv = m->private; 593 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 594 char buf[32]; 595 size_t buf_size; 596 int sel; 597 int ret; 598 599 buf_size = min(count, sizeof(buf) - 1); 600 if (copy_from_user(buf, user_buf, buf_size)) 601 return -EFAULT; 602 603 buf[buf_size] = '\0'; 604 ret = kstrtoint(buf, 0, &sel); 605 if (ret) 606 return ret; 607 608 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 609 rtw89_info(rtwdev, "invalid args: %d\n", sel); 610 return -EINVAL; 611 } 612 613 debugfs_priv->cb_data = sel; 614 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 615 616 return count; 617 } 618 619 #define RTW89_MAC_PAGE_SIZE 0x100 620 621 static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v) 622 { 623 struct rtw89_debugfs_priv *debugfs_priv = m->private; 624 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 625 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 626 u32 start, end; 627 u32 i, j, k, page; 628 u32 val; 629 630 switch (reg_sel) { 631 case RTW89_DBG_SEL_MAC_00: 632 seq_puts(m, "Debug selected MAC page 0x00\n"); 633 start = 0x000; 634 end = 0x014; 635 break; 636 case RTW89_DBG_SEL_MAC_40: 637 seq_puts(m, "Debug selected MAC page 0x40\n"); 638 start = 0x040; 639 end = 0x07f; 640 break; 641 case RTW89_DBG_SEL_MAC_80: 642 seq_puts(m, "Debug selected MAC page 0x80\n"); 643 start = 0x080; 644 end = 0x09f; 645 break; 646 case RTW89_DBG_SEL_MAC_C0: 647 seq_puts(m, "Debug selected MAC page 0xc0\n"); 648 start = 0x0c0; 649 end = 0x0df; 650 break; 651 case RTW89_DBG_SEL_MAC_E0: 652 seq_puts(m, "Debug selected MAC page 0xe0\n"); 653 start = 0x0e0; 654 end = 0x0ff; 655 break; 656 case RTW89_DBG_SEL_BB: 657 seq_puts(m, "Debug selected BB register\n"); 658 start = 0x100; 659 end = 0x17f; 660 break; 661 case RTW89_DBG_SEL_IQK: 662 seq_puts(m, "Debug selected IQK register\n"); 663 start = 0x180; 664 end = 0x1bf; 665 break; 666 case RTW89_DBG_SEL_RFC: 667 seq_puts(m, "Debug selected RFC register\n"); 668 start = 0x1c0; 669 end = 0x1ff; 670 break; 671 default: 672 seq_puts(m, "Selected invalid register page\n"); 673 return -EINVAL; 674 } 675 676 for (i = start; i <= end; i++) { 677 page = i << 8; 678 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 679 seq_printf(m, "%08xh : ", 0x18600000 + j); 680 for (k = 0; k < 4; k++) { 681 val = rtw89_read32(rtwdev, j + (k << 2)); 682 seq_printf(m, "%08x ", val); 683 } 684 seq_puts(m, "\n"); 685 } 686 } 687 688 return 0; 689 } 690 691 static ssize_t 692 rtw89_debug_priv_mac_mem_dump_select(struct file *filp, 693 const char __user *user_buf, 694 size_t count, loff_t *loff) 695 { 696 struct seq_file *m = (struct seq_file *)filp->private_data; 697 struct rtw89_debugfs_priv *debugfs_priv = m->private; 698 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 699 char buf[32]; 700 size_t buf_size; 701 u32 sel, start_addr, len; 702 int num; 703 704 buf_size = min(count, sizeof(buf) - 1); 705 if (copy_from_user(buf, user_buf, buf_size)) 706 return -EFAULT; 707 708 buf[buf_size] = '\0'; 709 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 710 if (num != 3) { 711 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 712 return -EINVAL; 713 } 714 715 debugfs_priv->mac_mem.sel = sel; 716 debugfs_priv->mac_mem.start = start_addr; 717 debugfs_priv->mac_mem.len = len; 718 719 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 720 sel, start_addr, len); 721 722 return count; 723 } 724 725 static const u32 mac_mem_base_addr_table[RTW89_MAC_MEM_MAX] = { 726 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 727 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 728 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 729 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 730 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 731 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 732 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 733 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 734 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 735 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 736 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 737 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 738 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 739 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 740 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 741 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 742 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 743 }; 744 745 static void rtw89_debug_dump_mac_mem(struct seq_file *m, 746 struct rtw89_dev *rtwdev, 747 u8 sel, u32 start_addr, u32 len) 748 { 749 u32 base_addr, start_page, residue; 750 u32 i, j, p, pages; 751 u32 dump_len, remain; 752 u32 val; 753 754 remain = len; 755 pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1; 756 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE; 757 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE; 758 base_addr = mac_mem_base_addr_table[sel]; 759 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE; 760 761 for (p = 0; p < pages; p++) { 762 dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE); 763 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, base_addr); 764 for (i = R_AX_INDIR_ACCESS_ENTRY + residue; 765 i < R_AX_INDIR_ACCESS_ENTRY + dump_len;) { 766 seq_printf(m, "%08xh:", i); 767 for (j = 0; 768 j < 4 && i < R_AX_INDIR_ACCESS_ENTRY + dump_len; 769 j++, i += 4) { 770 val = rtw89_read32(rtwdev, i); 771 seq_printf(m, " %08x", val); 772 remain -= 4; 773 } 774 seq_puts(m, "\n"); 775 } 776 base_addr += MAC_MEM_DUMP_PAGE_SIZE; 777 } 778 } 779 780 static int 781 rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v) 782 { 783 struct rtw89_debugfs_priv *debugfs_priv = m->private; 784 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 785 786 mutex_lock(&rtwdev->mutex); 787 rtw89_leave_ps_mode(rtwdev); 788 rtw89_debug_dump_mac_mem(m, rtwdev, 789 debugfs_priv->mac_mem.sel, 790 debugfs_priv->mac_mem.start, 791 debugfs_priv->mac_mem.len); 792 mutex_unlock(&rtwdev->mutex); 793 794 return 0; 795 } 796 797 static ssize_t 798 rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp, 799 const char __user *user_buf, 800 size_t count, loff_t *loff) 801 { 802 struct seq_file *m = (struct seq_file *)filp->private_data; 803 struct rtw89_debugfs_priv *debugfs_priv = m->private; 804 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 805 char buf[32]; 806 size_t buf_size; 807 int sel, set; 808 int num; 809 bool enable; 810 811 buf_size = min(count, sizeof(buf) - 1); 812 if (copy_from_user(buf, user_buf, buf_size)) 813 return -EFAULT; 814 815 buf[buf_size] = '\0'; 816 num = sscanf(buf, "%d %d", &sel, &set); 817 if (num != 2) { 818 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 819 return -EINVAL; 820 } 821 822 enable = set != 0; 823 switch (sel) { 824 case 0: 825 debugfs_priv->dbgpkg_en.ss_dbg = enable; 826 break; 827 case 1: 828 debugfs_priv->dbgpkg_en.dle_dbg = enable; 829 break; 830 case 2: 831 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 832 break; 833 case 3: 834 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 835 break; 836 case 4: 837 debugfs_priv->dbgpkg_en.dbg_port = enable; 838 break; 839 default: 840 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 841 return -EINVAL; 842 } 843 844 rtw89_info(rtwdev, "%s debug port dump %d\n", 845 enable ? "Enable" : "Disable", sel); 846 847 return count; 848 } 849 850 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 851 struct seq_file *m) 852 { 853 return 0; 854 } 855 856 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 857 struct seq_file *m) 858 { 859 #define DLE_DFI_DUMP(__type, __target, __sel) \ 860 ({ \ 861 u32 __ctrl; \ 862 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 863 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 864 u32 __data, __val32; \ 865 int __ret; \ 866 \ 867 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 868 DLE_DFI_TYPE_##__target) | \ 869 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 870 B_AX_WDE_DFI_ACTIVE; \ 871 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 872 __ret = read_poll_timeout(rtw89_read32, __val32, \ 873 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 874 1000, 50000, false, \ 875 rtwdev, __reg_ctrl); \ 876 if (__ret) { \ 877 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 878 #__type, #__target, __sel); \ 879 return __ret; \ 880 } \ 881 \ 882 __data = rtw89_read32(rtwdev, __reg_data); \ 883 __data; \ 884 }) 885 886 #define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \ 887 ({ \ 888 u32 __freepg, __pubpg; \ 889 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 890 \ 891 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 892 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 893 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 894 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 895 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 896 seq_printf(__m, "[%s] freepg head: %d\n", \ 897 #__type, __freepg_head); \ 898 seq_printf(__m, "[%s] freepg tail: %d\n", \ 899 #__type, __freepg_tail); \ 900 seq_printf(__m, "[%s] pubpg num : %d\n", \ 901 #__type, __pubpg_num); \ 902 }) 903 904 #define case_QUOTA(__m, __type, __id) \ 905 case __type##_QTAID_##__id: \ 906 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 907 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 908 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 909 seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \ 910 #__type, #__id, rsv_pgnum); \ 911 seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \ 912 #__type, #__id, use_pgnum); \ 913 break 914 u32 quota_id; 915 u32 val32; 916 u16 rsv_pgnum, use_pgnum; 917 int ret; 918 919 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 920 if (ret) { 921 seq_puts(m, "[DLE] : DMAC not enabled\n"); 922 return ret; 923 } 924 925 DLE_DFI_FREE_PAGE_DUMP(m, WDE); 926 DLE_DFI_FREE_PAGE_DUMP(m, PLE); 927 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 928 switch (quota_id) { 929 case_QUOTA(m, WDE, HOST_IF); 930 case_QUOTA(m, WDE, WLAN_CPU); 931 case_QUOTA(m, WDE, DATA_CPU); 932 case_QUOTA(m, WDE, PKTIN); 933 case_QUOTA(m, WDE, CPUIO); 934 } 935 } 936 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 937 switch (quota_id) { 938 case_QUOTA(m, PLE, B0_TXPL); 939 case_QUOTA(m, PLE, B1_TXPL); 940 case_QUOTA(m, PLE, C2H); 941 case_QUOTA(m, PLE, H2C); 942 case_QUOTA(m, PLE, WLAN_CPU); 943 case_QUOTA(m, PLE, MPDU); 944 case_QUOTA(m, PLE, CMAC0_RX); 945 case_QUOTA(m, PLE, CMAC1_RX); 946 case_QUOTA(m, PLE, CMAC1_BBRPT); 947 case_QUOTA(m, PLE, WDRLS); 948 case_QUOTA(m, PLE, CPUIO); 949 } 950 } 951 952 return 0; 953 954 #undef case_QUOTA 955 #undef DLE_DFI_DUMP 956 #undef DLE_DFI_FREE_PAGE_DUMP 957 } 958 959 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 960 struct seq_file *m) 961 { 962 int ret; 963 964 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 965 if (ret) { 966 seq_puts(m, "[DMAC] : DMAC not enabled\n"); 967 return ret; 968 } 969 970 seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n", 971 rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR)); 972 seq_printf(m, "[0]R_AX_WDRLS_ERR_ISR=0x%08x\n", 973 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 974 seq_printf(m, "[1]R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 975 rtw89_read32(rtwdev, R_AX_SEC_ERR_IMR_ISR)); 976 seq_printf(m, "[2.1]R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 977 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 978 seq_printf(m, "[2.2]R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 979 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 980 seq_printf(m, "[3]R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 981 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 982 seq_printf(m, "[4]R_AX_WDE_ERR_ISR=0x%08x\n", 983 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 984 seq_printf(m, "[5.1]R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 985 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 986 seq_printf(m, "[5.2]R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 987 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 988 seq_printf(m, "[6]R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 989 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 990 seq_printf(m, "[7]R_AX_PKTIN_ERR_ISR=0x%08x\n", 991 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 992 seq_printf(m, "[8.1]R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 993 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 994 seq_printf(m, "[8.2]R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 995 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 996 seq_printf(m, "[8.3]R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 997 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 998 seq_printf(m, "[10]R_AX_CPUIO_ERR_ISR=0x%08x\n", 999 rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR)); 1000 seq_printf(m, "[11.1]R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 1001 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 1002 seq_printf(m, "[11.2]R_AX_BBRPT_CHINFO_ERR_IMR_ISR=0x%08x\n", 1003 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR_ISR)); 1004 seq_printf(m, "[11.3]R_AX_BBRPT_DFS_ERR_IMR_ISR=0x%08x\n", 1005 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR_ISR)); 1006 seq_printf(m, "[11.4]R_AX_LA_ERRFLAG=0x%08x\n", 1007 rtw89_read32(rtwdev, R_AX_LA_ERRFLAG)); 1008 1009 return 0; 1010 } 1011 1012 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 1013 struct seq_file *m) 1014 { 1015 int ret; 1016 1017 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL); 1018 if (ret) { 1019 seq_puts(m, "[CMAC] : CMAC 0 not enabled\n"); 1020 return ret; 1021 } 1022 1023 seq_printf(m, "R_AX_CMAC_ERR_ISR=0x%08x\n", 1024 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR)); 1025 seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR=0x%08x\n", 1026 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR)); 1027 seq_printf(m, "[1]R_AX_PTCL_ISR0=0x%08x\n", 1028 rtw89_read32(rtwdev, R_AX_PTCL_ISR0)); 1029 seq_printf(m, "[3]R_AX_DLE_CTRL=0x%08x\n", 1030 rtw89_read32(rtwdev, R_AX_DLE_CTRL)); 1031 seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR=0x%08x\n", 1032 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR)); 1033 seq_printf(m, "[5]R_AX_TXPWR_ISR=0x%08x\n", 1034 rtw89_read32(rtwdev, R_AX_TXPWR_ISR)); 1035 seq_printf(m, "[6]R_AX_RMAC_ERR_ISR=0x%08x\n", 1036 rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR)); 1037 seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR=0x%08x\n", 1038 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR)); 1039 1040 ret = rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL); 1041 if (ret) { 1042 seq_puts(m, "[CMAC] : CMAC 1 not enabled\n"); 1043 return ret; 1044 } 1045 1046 seq_printf(m, "R_AX_CMAC_ERR_ISR_C1=0x%08x\n", 1047 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR_C1)); 1048 seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR_C1=0x%08x\n", 1049 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR_C1)); 1050 seq_printf(m, "[1]R_AX_PTCL_ISR0_C1=0x%08x\n", 1051 rtw89_read32(rtwdev, R_AX_PTCL_ISR0_C1)); 1052 seq_printf(m, "[3]R_AX_DLE_CTRL_C1=0x%08x\n", 1053 rtw89_read32(rtwdev, R_AX_DLE_CTRL_C1)); 1054 seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR_C1=0x%02x\n", 1055 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR_C1)); 1056 seq_printf(m, "[5]R_AX_TXPWR_ISR_C1=0x%08x\n", 1057 rtw89_read32(rtwdev, R_AX_TXPWR_ISR_C1)); 1058 seq_printf(m, "[6]R_AX_RMAC_ERR_ISR_C1=0x%08x\n", 1059 rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR_C1)); 1060 seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR_C1=0x%08x\n", 1061 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR_C1)); 1062 1063 return 0; 1064 } 1065 1066 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1067 .sel_addr = R_AX_PTCL_DBG, 1068 .sel_byte = 1, 1069 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1070 .srt = 0x00, 1071 .end = 0x3F, 1072 .rd_addr = R_AX_PTCL_DBG_INFO, 1073 .rd_byte = 4, 1074 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1075 }; 1076 1077 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1078 .sel_addr = R_AX_PTCL_DBG_C1, 1079 .sel_byte = 1, 1080 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1081 .srt = 0x00, 1082 .end = 0x3F, 1083 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1084 .rd_byte = 4, 1085 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1086 }; 1087 1088 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 1089 .sel_addr = R_AX_SCH_DBG_SEL, 1090 .sel_byte = 1, 1091 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1092 .srt = 0x00, 1093 .end = 0x2F, 1094 .rd_addr = R_AX_SCH_DBG, 1095 .rd_byte = 4, 1096 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1097 }; 1098 1099 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 1100 .sel_addr = R_AX_SCH_DBG_SEL_C1, 1101 .sel_byte = 1, 1102 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1103 .srt = 0x00, 1104 .end = 0x2F, 1105 .rd_addr = R_AX_SCH_DBG_C1, 1106 .rd_byte = 4, 1107 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1108 }; 1109 1110 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 1111 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 1112 .sel_byte = 1, 1113 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1114 .srt = 0x00, 1115 .end = 0x19, 1116 .rd_addr = R_AX_DBG_PORT_SEL, 1117 .rd_byte = 4, 1118 .rd_msk = B_AX_DEBUG_ST_MASK 1119 }; 1120 1121 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 1122 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 1123 .sel_byte = 1, 1124 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1125 .srt = 0x00, 1126 .end = 0x19, 1127 .rd_addr = R_AX_DBG_PORT_SEL, 1128 .rd_byte = 4, 1129 .rd_msk = B_AX_DEBUG_ST_MASK 1130 }; 1131 1132 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 1133 .sel_addr = R_AX_RX_DEBUG_SELECT, 1134 .sel_byte = 1, 1135 .sel_msk = B_AX_DEBUG_SEL_MASK, 1136 .srt = 0x00, 1137 .end = 0x58, 1138 .rd_addr = R_AX_DBG_PORT_SEL, 1139 .rd_byte = 4, 1140 .rd_msk = B_AX_DEBUG_ST_MASK 1141 }; 1142 1143 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 1144 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 1145 .sel_byte = 1, 1146 .sel_msk = B_AX_DEBUG_SEL_MASK, 1147 .srt = 0x00, 1148 .end = 0x58, 1149 .rd_addr = R_AX_DBG_PORT_SEL, 1150 .rd_byte = 4, 1151 .rd_msk = B_AX_DEBUG_ST_MASK 1152 }; 1153 1154 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 1155 .sel_addr = R_AX_RX_STATE_MONITOR, 1156 .sel_byte = 1, 1157 .sel_msk = B_AX_STATE_SEL_MASK, 1158 .srt = 0x00, 1159 .end = 0x17, 1160 .rd_addr = R_AX_RX_STATE_MONITOR, 1161 .rd_byte = 4, 1162 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 1163 }; 1164 1165 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 1166 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 1167 .sel_byte = 1, 1168 .sel_msk = B_AX_STATE_SEL_MASK, 1169 .srt = 0x00, 1170 .end = 0x17, 1171 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 1172 .rd_byte = 4, 1173 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 1174 }; 1175 1176 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 1177 .sel_addr = R_AX_RMAC_PLCP_MON, 1178 .sel_byte = 4, 1179 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 1180 .srt = 0x0, 1181 .end = 0xF, 1182 .rd_addr = R_AX_RMAC_PLCP_MON, 1183 .rd_byte = 4, 1184 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 1185 }; 1186 1187 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 1188 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 1189 .sel_byte = 4, 1190 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 1191 .srt = 0x0, 1192 .end = 0xF, 1193 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 1194 .rd_byte = 4, 1195 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 1196 }; 1197 1198 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 1199 .sel_addr = R_AX_DBGSEL_TRXPTCL, 1200 .sel_byte = 1, 1201 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 1202 .srt = 0x08, 1203 .end = 0x10, 1204 .rd_addr = R_AX_DBG_PORT_SEL, 1205 .rd_byte = 4, 1206 .rd_msk = B_AX_DEBUG_ST_MASK 1207 }; 1208 1209 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 1210 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 1211 .sel_byte = 1, 1212 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 1213 .srt = 0x08, 1214 .end = 0x10, 1215 .rd_addr = R_AX_DBG_PORT_SEL, 1216 .rd_byte = 4, 1217 .rd_msk = B_AX_DEBUG_ST_MASK 1218 }; 1219 1220 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 1221 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 1222 .sel_byte = 1, 1223 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1224 .srt = 0x00, 1225 .end = 0x07, 1226 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 1227 .rd_byte = 4, 1228 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 1229 }; 1230 1231 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 1232 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 1233 .sel_byte = 1, 1234 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1235 .srt = 0x00, 1236 .end = 0x07, 1237 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 1238 .rd_byte = 4, 1239 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 1240 }; 1241 1242 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 1243 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 1244 .sel_byte = 1, 1245 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1246 .srt = 0x00, 1247 .end = 0x07, 1248 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 1249 .rd_byte = 4, 1250 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 1251 }; 1252 1253 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 1254 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 1255 .sel_byte = 1, 1256 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1257 .srt = 0x00, 1258 .end = 0x07, 1259 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 1260 .rd_byte = 4, 1261 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 1262 }; 1263 1264 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 1265 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 1266 .sel_byte = 1, 1267 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1268 .srt = 0x00, 1269 .end = 0x04, 1270 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 1271 .rd_byte = 4, 1272 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 1273 }; 1274 1275 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 1276 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 1277 .sel_byte = 1, 1278 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1279 .srt = 0x00, 1280 .end = 0x04, 1281 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 1282 .rd_byte = 4, 1283 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 1284 }; 1285 1286 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 1287 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 1288 .sel_byte = 1, 1289 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1290 .srt = 0x00, 1291 .end = 0x04, 1292 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 1293 .rd_byte = 4, 1294 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 1295 }; 1296 1297 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 1298 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 1299 .sel_byte = 1, 1300 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1301 .srt = 0x00, 1302 .end = 0x04, 1303 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 1304 .rd_byte = 4, 1305 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 1306 }; 1307 1308 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 1309 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1310 .sel_byte = 4, 1311 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1312 .srt = 0x80000000, 1313 .end = 0x80000001, 1314 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1315 .rd_byte = 4, 1316 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1317 }; 1318 1319 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 1320 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1321 .sel_byte = 4, 1322 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1323 .srt = 0x80010000, 1324 .end = 0x80010004, 1325 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1326 .rd_byte = 4, 1327 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1328 }; 1329 1330 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 1331 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1332 .sel_byte = 4, 1333 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1334 .srt = 0x80020000, 1335 .end = 0x80020FFF, 1336 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1337 .rd_byte = 4, 1338 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1339 }; 1340 1341 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 1342 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1343 .sel_byte = 4, 1344 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1345 .srt = 0x80030000, 1346 .end = 0x80030FFF, 1347 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1348 .rd_byte = 4, 1349 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1350 }; 1351 1352 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 1353 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1354 .sel_byte = 4, 1355 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1356 .srt = 0x80040000, 1357 .end = 0x80040FFF, 1358 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1359 .rd_byte = 4, 1360 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1361 }; 1362 1363 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 1364 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1365 .sel_byte = 4, 1366 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1367 .srt = 0x80050000, 1368 .end = 0x80050FFF, 1369 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1370 .rd_byte = 4, 1371 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1372 }; 1373 1374 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 1375 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1376 .sel_byte = 4, 1377 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1378 .srt = 0x80060000, 1379 .end = 0x80060453, 1380 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1381 .rd_byte = 4, 1382 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1383 }; 1384 1385 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 1386 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1387 .sel_byte = 4, 1388 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1389 .srt = 0x80070000, 1390 .end = 0x80070011, 1391 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1392 .rd_byte = 4, 1393 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1394 }; 1395 1396 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 1397 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1398 .sel_byte = 4, 1399 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1400 .srt = 0x80000000, 1401 .end = 0x80000001, 1402 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1403 .rd_byte = 4, 1404 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1405 }; 1406 1407 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 1408 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1409 .sel_byte = 4, 1410 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1411 .srt = 0x80010000, 1412 .end = 0x8001000A, 1413 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1414 .rd_byte = 4, 1415 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1416 }; 1417 1418 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 1419 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1420 .sel_byte = 4, 1421 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1422 .srt = 0x80020000, 1423 .end = 0x80020DBF, 1424 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1425 .rd_byte = 4, 1426 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1427 }; 1428 1429 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 1430 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1431 .sel_byte = 4, 1432 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1433 .srt = 0x80030000, 1434 .end = 0x80030DBF, 1435 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1436 .rd_byte = 4, 1437 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1438 }; 1439 1440 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 1441 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1442 .sel_byte = 4, 1443 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1444 .srt = 0x80040000, 1445 .end = 0x80040DBF, 1446 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1447 .rd_byte = 4, 1448 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1449 }; 1450 1451 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 1452 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1453 .sel_byte = 4, 1454 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1455 .srt = 0x80050000, 1456 .end = 0x80050DBF, 1457 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1458 .rd_byte = 4, 1459 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1460 }; 1461 1462 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 1463 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1464 .sel_byte = 4, 1465 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1466 .srt = 0x80060000, 1467 .end = 0x80060041, 1468 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1469 .rd_byte = 4, 1470 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1471 }; 1472 1473 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 1474 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1475 .sel_byte = 4, 1476 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1477 .srt = 0x80070000, 1478 .end = 0x80070001, 1479 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1480 .rd_byte = 4, 1481 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1482 }; 1483 1484 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 1485 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 1486 .sel_byte = 4, 1487 .sel_msk = B_AX_DFI_DATA_MASK, 1488 .srt = 0x80000000, 1489 .end = 0x8000017f, 1490 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 1491 .rd_byte = 4, 1492 .rd_msk = B_AX_DFI_DATA_MASK 1493 }; 1494 1495 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 1496 .sel_addr = R_AX_PCIE_DBG_CTRL, 1497 .sel_byte = 2, 1498 .sel_msk = B_AX_DBG_SEL_MASK, 1499 .srt = 0x00, 1500 .end = 0x03, 1501 .rd_addr = R_AX_DBG_PORT_SEL, 1502 .rd_byte = 4, 1503 .rd_msk = B_AX_DEBUG_ST_MASK 1504 }; 1505 1506 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 1507 .sel_addr = R_AX_PCIE_DBG_CTRL, 1508 .sel_byte = 2, 1509 .sel_msk = B_AX_DBG_SEL_MASK, 1510 .srt = 0x00, 1511 .end = 0x04, 1512 .rd_addr = R_AX_DBG_PORT_SEL, 1513 .rd_byte = 4, 1514 .rd_msk = B_AX_DEBUG_ST_MASK 1515 }; 1516 1517 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 1518 .sel_addr = R_AX_PCIE_DBG_CTRL, 1519 .sel_byte = 2, 1520 .sel_msk = B_AX_DBG_SEL_MASK, 1521 .srt = 0x00, 1522 .end = 0x01, 1523 .rd_addr = R_AX_DBG_PORT_SEL, 1524 .rd_byte = 4, 1525 .rd_msk = B_AX_DEBUG_ST_MASK 1526 }; 1527 1528 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 1529 .sel_addr = R_AX_PCIE_DBG_CTRL, 1530 .sel_byte = 2, 1531 .sel_msk = B_AX_DBG_SEL_MASK, 1532 .srt = 0x00, 1533 .end = 0x05, 1534 .rd_addr = R_AX_DBG_PORT_SEL, 1535 .rd_byte = 4, 1536 .rd_msk = B_AX_DEBUG_ST_MASK 1537 }; 1538 1539 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 1540 .sel_addr = R_AX_PCIE_DBG_CTRL, 1541 .sel_byte = 2, 1542 .sel_msk = B_AX_DBG_SEL_MASK, 1543 .srt = 0x00, 1544 .end = 0x05, 1545 .rd_addr = R_AX_DBG_PORT_SEL, 1546 .rd_byte = 4, 1547 .rd_msk = B_AX_DEBUG_ST_MASK 1548 }; 1549 1550 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 1551 .sel_addr = R_AX_PCIE_DBG_CTRL, 1552 .sel_byte = 2, 1553 .sel_msk = B_AX_DBG_SEL_MASK, 1554 .srt = 0x00, 1555 .end = 0x06, 1556 .rd_addr = R_AX_DBG_PORT_SEL, 1557 .rd_byte = 4, 1558 .rd_msk = B_AX_DEBUG_ST_MASK 1559 }; 1560 1561 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 1562 .sel_addr = R_AX_DBG_CTRL, 1563 .sel_byte = 1, 1564 .sel_msk = B_AX_DBG_SEL0, 1565 .srt = 0x34, 1566 .end = 0x3C, 1567 .rd_addr = R_AX_DBG_PORT_SEL, 1568 .rd_byte = 4, 1569 .rd_msk = B_AX_DEBUG_ST_MASK 1570 }; 1571 1572 static const struct rtw89_mac_dbg_port_info * 1573 rtw89_debug_mac_dbg_port_sel(struct seq_file *m, 1574 struct rtw89_dev *rtwdev, u32 sel) 1575 { 1576 const struct rtw89_mac_dbg_port_info *info; 1577 u32 val32; 1578 u16 val16; 1579 u8 val8; 1580 1581 switch (sel) { 1582 case RTW89_DBG_PORT_SEL_PTCL_C0: 1583 info = &dbg_port_ptcl_c0; 1584 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 1585 val16 |= B_AX_PTCL_DBG_EN; 1586 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 1587 seq_puts(m, "Enable PTCL C0 dbgport.\n"); 1588 break; 1589 case RTW89_DBG_PORT_SEL_PTCL_C1: 1590 info = &dbg_port_ptcl_c1; 1591 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 1592 val16 |= B_AX_PTCL_DBG_EN; 1593 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 1594 seq_puts(m, "Enable PTCL C1 dbgport.\n"); 1595 break; 1596 case RTW89_DBG_PORT_SEL_SCH_C0: 1597 info = &dbg_port_sch_c0; 1598 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 1599 val32 |= B_AX_SCH_DBG_EN; 1600 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 1601 seq_puts(m, "Enable SCH C0 dbgport.\n"); 1602 break; 1603 case RTW89_DBG_PORT_SEL_SCH_C1: 1604 info = &dbg_port_sch_c1; 1605 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 1606 val32 |= B_AX_SCH_DBG_EN; 1607 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 1608 seq_puts(m, "Enable SCH C1 dbgport.\n"); 1609 break; 1610 case RTW89_DBG_PORT_SEL_TMAC_C0: 1611 info = &dbg_port_tmac_c0; 1612 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 1613 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 1614 B_AX_DBGSEL_TRXPTCL_MASK); 1615 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 1616 1617 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1618 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 1619 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 1620 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1621 1622 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1623 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1624 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1625 seq_puts(m, "Enable TMAC C0 dbgport.\n"); 1626 break; 1627 case RTW89_DBG_PORT_SEL_TMAC_C1: 1628 info = &dbg_port_tmac_c1; 1629 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 1630 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 1631 B_AX_DBGSEL_TRXPTCL_MASK); 1632 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 1633 1634 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1635 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 1636 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 1637 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1638 1639 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1640 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1641 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1642 seq_puts(m, "Enable TMAC C1 dbgport.\n"); 1643 break; 1644 case RTW89_DBG_PORT_SEL_RMAC_C0: 1645 info = &dbg_port_rmac_c0; 1646 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 1647 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 1648 B_AX_DBGSEL_TRXPTCL_MASK); 1649 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 1650 1651 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1652 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 1653 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 1654 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1655 1656 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1657 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1658 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1659 1660 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 1661 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 1662 B_AX_DBGSEL_TRXPTCL_MASK); 1663 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 1664 seq_puts(m, "Enable RMAC C0 dbgport.\n"); 1665 break; 1666 case RTW89_DBG_PORT_SEL_RMAC_C1: 1667 info = &dbg_port_rmac_c1; 1668 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 1669 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 1670 B_AX_DBGSEL_TRXPTCL_MASK); 1671 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 1672 1673 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1674 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 1675 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 1676 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1677 1678 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1679 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1680 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1681 1682 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 1683 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 1684 B_AX_DBGSEL_TRXPTCL_MASK); 1685 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 1686 seq_puts(m, "Enable RMAC C1 dbgport.\n"); 1687 break; 1688 case RTW89_DBG_PORT_SEL_RMACST_C0: 1689 info = &dbg_port_rmacst_c0; 1690 seq_puts(m, "Enable RMAC state C0 dbgport.\n"); 1691 break; 1692 case RTW89_DBG_PORT_SEL_RMACST_C1: 1693 info = &dbg_port_rmacst_c1; 1694 seq_puts(m, "Enable RMAC state C1 dbgport.\n"); 1695 break; 1696 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 1697 info = &dbg_port_rmac_plcp_c0; 1698 seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n"); 1699 break; 1700 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 1701 info = &dbg_port_rmac_plcp_c1; 1702 seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n"); 1703 break; 1704 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 1705 info = &dbg_port_trxptcl_c0; 1706 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1707 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 1708 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 1709 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1710 1711 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1712 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1713 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1714 seq_puts(m, "Enable TRXPTCL C0 dbgport.\n"); 1715 break; 1716 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 1717 info = &dbg_port_trxptcl_c1; 1718 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1719 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 1720 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 1721 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1722 1723 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1724 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1725 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1726 seq_puts(m, "Enable TRXPTCL C1 dbgport.\n"); 1727 break; 1728 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 1729 info = &dbg_port_tx_infol_c0; 1730 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1731 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1732 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1733 seq_puts(m, "Enable tx infol dump.\n"); 1734 break; 1735 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 1736 info = &dbg_port_tx_infoh_c0; 1737 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1738 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1739 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1740 seq_puts(m, "Enable tx infoh dump.\n"); 1741 break; 1742 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 1743 info = &dbg_port_tx_infol_c1; 1744 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1745 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1746 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1747 seq_puts(m, "Enable tx infol dump.\n"); 1748 break; 1749 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 1750 info = &dbg_port_tx_infoh_c1; 1751 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1752 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1753 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1754 seq_puts(m, "Enable tx infoh dump.\n"); 1755 break; 1756 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 1757 info = &dbg_port_txtf_infol_c0; 1758 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1759 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1760 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1761 seq_puts(m, "Enable tx tf infol dump.\n"); 1762 break; 1763 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 1764 info = &dbg_port_txtf_infoh_c0; 1765 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1766 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1767 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1768 seq_puts(m, "Enable tx tf infoh dump.\n"); 1769 break; 1770 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 1771 info = &dbg_port_txtf_infol_c1; 1772 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1773 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1774 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1775 seq_puts(m, "Enable tx tf infol dump.\n"); 1776 break; 1777 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 1778 info = &dbg_port_txtf_infoh_c1; 1779 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1780 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1781 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1782 seq_puts(m, "Enable tx tf infoh dump.\n"); 1783 break; 1784 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 1785 info = &dbg_port_wde_bufmgn_freepg; 1786 seq_puts(m, "Enable wde bufmgn freepg dump.\n"); 1787 break; 1788 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 1789 info = &dbg_port_wde_bufmgn_quota; 1790 seq_puts(m, "Enable wde bufmgn quota dump.\n"); 1791 break; 1792 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 1793 info = &dbg_port_wde_bufmgn_pagellt; 1794 seq_puts(m, "Enable wde bufmgn pagellt dump.\n"); 1795 break; 1796 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 1797 info = &dbg_port_wde_bufmgn_pktinfo; 1798 seq_puts(m, "Enable wde bufmgn pktinfo dump.\n"); 1799 break; 1800 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 1801 info = &dbg_port_wde_quemgn_prepkt; 1802 seq_puts(m, "Enable wde quemgn prepkt dump.\n"); 1803 break; 1804 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 1805 info = &dbg_port_wde_quemgn_nxtpkt; 1806 seq_puts(m, "Enable wde quemgn nxtpkt dump.\n"); 1807 break; 1808 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 1809 info = &dbg_port_wde_quemgn_qlnktbl; 1810 seq_puts(m, "Enable wde quemgn qlnktbl dump.\n"); 1811 break; 1812 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 1813 info = &dbg_port_wde_quemgn_qempty; 1814 seq_puts(m, "Enable wde quemgn qempty dump.\n"); 1815 break; 1816 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 1817 info = &dbg_port_ple_bufmgn_freepg; 1818 seq_puts(m, "Enable ple bufmgn freepg dump.\n"); 1819 break; 1820 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 1821 info = &dbg_port_ple_bufmgn_quota; 1822 seq_puts(m, "Enable ple bufmgn quota dump.\n"); 1823 break; 1824 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 1825 info = &dbg_port_ple_bufmgn_pagellt; 1826 seq_puts(m, "Enable ple bufmgn pagellt dump.\n"); 1827 break; 1828 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 1829 info = &dbg_port_ple_bufmgn_pktinfo; 1830 seq_puts(m, "Enable ple bufmgn pktinfo dump.\n"); 1831 break; 1832 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 1833 info = &dbg_port_ple_quemgn_prepkt; 1834 seq_puts(m, "Enable ple quemgn prepkt dump.\n"); 1835 break; 1836 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 1837 info = &dbg_port_ple_quemgn_nxtpkt; 1838 seq_puts(m, "Enable ple quemgn nxtpkt dump.\n"); 1839 break; 1840 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 1841 info = &dbg_port_ple_quemgn_qlnktbl; 1842 seq_puts(m, "Enable ple quemgn qlnktbl dump.\n"); 1843 break; 1844 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 1845 info = &dbg_port_ple_quemgn_qempty; 1846 seq_puts(m, "Enable ple quemgn qempty dump.\n"); 1847 break; 1848 case RTW89_DBG_PORT_SEL_PKTINFO: 1849 info = &dbg_port_pktinfo; 1850 seq_puts(m, "Enable pktinfo dump.\n"); 1851 break; 1852 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 1853 info = &dbg_port_pcie_txdma; 1854 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1855 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 1856 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 1857 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1858 seq_puts(m, "Enable pcie txdma dump.\n"); 1859 break; 1860 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 1861 info = &dbg_port_pcie_rxdma; 1862 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1863 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 1864 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 1865 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1866 seq_puts(m, "Enable pcie rxdma dump.\n"); 1867 break; 1868 case RTW89_DBG_PORT_SEL_PCIE_CVT: 1869 info = &dbg_port_pcie_cvt; 1870 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1871 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 1872 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 1873 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1874 seq_puts(m, "Enable pcie cvt dump.\n"); 1875 break; 1876 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 1877 info = &dbg_port_pcie_cxpl; 1878 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1879 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 1880 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 1881 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1882 seq_puts(m, "Enable pcie cxpl dump.\n"); 1883 break; 1884 case RTW89_DBG_PORT_SEL_PCIE_IO: 1885 info = &dbg_port_pcie_io; 1886 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1887 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 1888 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 1889 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1890 seq_puts(m, "Enable pcie io dump.\n"); 1891 break; 1892 case RTW89_DBG_PORT_SEL_PCIE_MISC: 1893 info = &dbg_port_pcie_misc; 1894 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1895 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 1896 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 1897 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1898 seq_puts(m, "Enable pcie misc dump.\n"); 1899 break; 1900 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 1901 info = &dbg_port_pcie_misc2; 1902 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 1903 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 1904 B_AX_DBG_SEL_MASK); 1905 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 1906 seq_puts(m, "Enable pcie misc2 dump.\n"); 1907 break; 1908 default: 1909 seq_puts(m, "Dbg port select err\n"); 1910 return NULL; 1911 } 1912 1913 return info; 1914 } 1915 1916 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 1917 { 1918 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 1919 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 1920 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 1921 return false; 1922 if (rtwdev->chip->chip_id == RTL8852B && 1923 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 1924 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 1925 return false; 1926 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 1927 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 1928 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 1929 return false; 1930 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 1931 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 1932 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 1933 return false; 1934 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 1935 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 1936 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 1937 return false; 1938 1939 return true; 1940 } 1941 1942 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 1943 struct seq_file *m, u32 sel) 1944 { 1945 const struct rtw89_mac_dbg_port_info *info; 1946 u8 val8; 1947 u16 val16; 1948 u32 val32; 1949 u32 i; 1950 1951 info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel); 1952 if (!info) { 1953 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 1954 return -EINVAL; 1955 } 1956 1957 #define case_DBG_SEL(__sel) \ 1958 case RTW89_DBG_PORT_SEL_##__sel: \ 1959 seq_puts(m, "Dump debug port " #__sel ":\n"); \ 1960 break 1961 1962 switch (sel) { 1963 case_DBG_SEL(PTCL_C0); 1964 case_DBG_SEL(PTCL_C1); 1965 case_DBG_SEL(SCH_C0); 1966 case_DBG_SEL(SCH_C1); 1967 case_DBG_SEL(TMAC_C0); 1968 case_DBG_SEL(TMAC_C1); 1969 case_DBG_SEL(RMAC_C0); 1970 case_DBG_SEL(RMAC_C1); 1971 case_DBG_SEL(RMACST_C0); 1972 case_DBG_SEL(RMACST_C1); 1973 case_DBG_SEL(TRXPTCL_C0); 1974 case_DBG_SEL(TRXPTCL_C1); 1975 case_DBG_SEL(TX_INFOL_C0); 1976 case_DBG_SEL(TX_INFOH_C0); 1977 case_DBG_SEL(TX_INFOL_C1); 1978 case_DBG_SEL(TX_INFOH_C1); 1979 case_DBG_SEL(TXTF_INFOL_C0); 1980 case_DBG_SEL(TXTF_INFOH_C0); 1981 case_DBG_SEL(TXTF_INFOL_C1); 1982 case_DBG_SEL(TXTF_INFOH_C1); 1983 case_DBG_SEL(WDE_BUFMGN_FREEPG); 1984 case_DBG_SEL(WDE_BUFMGN_QUOTA); 1985 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 1986 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 1987 case_DBG_SEL(WDE_QUEMGN_PREPKT); 1988 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 1989 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 1990 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 1991 case_DBG_SEL(PLE_BUFMGN_FREEPG); 1992 case_DBG_SEL(PLE_BUFMGN_QUOTA); 1993 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 1994 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 1995 case_DBG_SEL(PLE_QUEMGN_PREPKT); 1996 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 1997 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 1998 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 1999 case_DBG_SEL(PKTINFO); 2000 case_DBG_SEL(PCIE_TXDMA); 2001 case_DBG_SEL(PCIE_RXDMA); 2002 case_DBG_SEL(PCIE_CVT); 2003 case_DBG_SEL(PCIE_CXPL); 2004 case_DBG_SEL(PCIE_IO); 2005 case_DBG_SEL(PCIE_MISC); 2006 case_DBG_SEL(PCIE_MISC2); 2007 } 2008 2009 #undef case_DBG_SEL 2010 2011 seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr); 2012 seq_printf(m, "Read addr = 0x%X\n", info->rd_addr); 2013 2014 for (i = info->srt; i <= info->end; i++) { 2015 switch (info->sel_byte) { 2016 case 1: 2017 default: 2018 rtw89_write8_mask(rtwdev, info->sel_addr, 2019 info->sel_msk, i); 2020 seq_printf(m, "0x%02X: ", i); 2021 break; 2022 case 2: 2023 rtw89_write16_mask(rtwdev, info->sel_addr, 2024 info->sel_msk, i); 2025 seq_printf(m, "0x%04X: ", i); 2026 break; 2027 case 4: 2028 rtw89_write32_mask(rtwdev, info->sel_addr, 2029 info->sel_msk, i); 2030 seq_printf(m, "0x%04X: ", i); 2031 break; 2032 } 2033 2034 udelay(10); 2035 2036 switch (info->rd_byte) { 2037 case 1: 2038 default: 2039 val8 = rtw89_read8_mask(rtwdev, 2040 info->rd_addr, info->rd_msk); 2041 seq_printf(m, "0x%02X\n", val8); 2042 break; 2043 case 2: 2044 val16 = rtw89_read16_mask(rtwdev, 2045 info->rd_addr, info->rd_msk); 2046 seq_printf(m, "0x%04X\n", val16); 2047 break; 2048 case 4: 2049 val32 = rtw89_read32_mask(rtwdev, 2050 info->rd_addr, info->rd_msk); 2051 seq_printf(m, "0x%08X\n", val32); 2052 break; 2053 } 2054 } 2055 2056 return 0; 2057 } 2058 2059 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 2060 struct seq_file *m) 2061 { 2062 u32 sel; 2063 int ret = 0; 2064 2065 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 2066 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 2067 if (!is_dbg_port_valid(rtwdev, sel)) 2068 continue; 2069 ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel); 2070 if (ret) { 2071 rtw89_err(rtwdev, 2072 "failed to dump debug port %d\n", sel); 2073 break; 2074 } 2075 } 2076 2077 return ret; 2078 } 2079 2080 static int 2081 rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v) 2082 { 2083 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2084 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2085 2086 if (debugfs_priv->dbgpkg_en.ss_dbg) 2087 rtw89_debug_mac_dump_ss_dbg(rtwdev, m); 2088 if (debugfs_priv->dbgpkg_en.dle_dbg) 2089 rtw89_debug_mac_dump_dle_dbg(rtwdev, m); 2090 if (debugfs_priv->dbgpkg_en.dmac_dbg) 2091 rtw89_debug_mac_dump_dmac_dbg(rtwdev, m); 2092 if (debugfs_priv->dbgpkg_en.cmac_dbg) 2093 rtw89_debug_mac_dump_cmac_dbg(rtwdev, m); 2094 if (debugfs_priv->dbgpkg_en.dbg_port) 2095 rtw89_debug_mac_dump_dbg_port(rtwdev, m); 2096 2097 return 0; 2098 }; 2099 2100 static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev, 2101 const char __user *user_buf, size_t count) 2102 { 2103 char *buf; 2104 u8 *bin; 2105 int num; 2106 int err = 0; 2107 2108 buf = memdup_user(user_buf, count); 2109 if (IS_ERR(buf)) 2110 return buf; 2111 2112 num = count / 2; 2113 bin = kmalloc(num, GFP_KERNEL); 2114 if (!bin) { 2115 err = -EFAULT; 2116 goto out; 2117 } 2118 2119 if (hex2bin(bin, buf, num)) { 2120 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 2121 kfree(bin); 2122 err = -EINVAL; 2123 } 2124 2125 out: 2126 kfree(buf); 2127 2128 return err ? ERR_PTR(err) : bin; 2129 } 2130 2131 static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp, 2132 const char __user *user_buf, 2133 size_t count, loff_t *loff) 2134 { 2135 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 2136 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2137 u8 *h2c; 2138 u16 h2c_len = count / 2; 2139 2140 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 2141 if (IS_ERR(h2c)) 2142 return -EFAULT; 2143 2144 rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 2145 2146 kfree(h2c); 2147 2148 return count; 2149 } 2150 2151 static int 2152 rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v) 2153 { 2154 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2155 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2156 struct rtw89_early_h2c *early_h2c; 2157 int seq = 0; 2158 2159 mutex_lock(&rtwdev->mutex); 2160 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 2161 seq_printf(m, "%d: %*ph\n", ++seq, early_h2c->h2c_len, early_h2c->h2c); 2162 mutex_unlock(&rtwdev->mutex); 2163 2164 return 0; 2165 } 2166 2167 static ssize_t 2168 rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf, 2169 size_t count, loff_t *loff) 2170 { 2171 struct seq_file *m = (struct seq_file *)filp->private_data; 2172 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2173 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2174 struct rtw89_early_h2c *early_h2c; 2175 u8 *h2c; 2176 u16 h2c_len = count / 2; 2177 2178 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 2179 if (IS_ERR(h2c)) 2180 return -EFAULT; 2181 2182 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 2183 kfree(h2c); 2184 rtw89_fw_free_all_early_h2c(rtwdev); 2185 goto out; 2186 } 2187 2188 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL); 2189 if (!early_h2c) { 2190 kfree(h2c); 2191 return -EFAULT; 2192 } 2193 2194 early_h2c->h2c = h2c; 2195 early_h2c->h2c_len = h2c_len; 2196 2197 mutex_lock(&rtwdev->mutex); 2198 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 2199 mutex_unlock(&rtwdev->mutex); 2200 2201 out: 2202 return count; 2203 } 2204 2205 static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v) 2206 { 2207 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2208 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2209 2210 rtw89_btc_dump_info(rtwdev, m); 2211 2212 return 0; 2213 } 2214 2215 static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp, 2216 const char __user *user_buf, 2217 size_t count, loff_t *loff) 2218 { 2219 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 2220 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2221 struct rtw89_btc *btc = &rtwdev->btc; 2222 bool btc_manual; 2223 2224 if (kstrtobool_from_user(user_buf, count, &btc_manual)) 2225 goto out; 2226 2227 btc->ctrl.manual = btc_manual; 2228 out: 2229 return count; 2230 } 2231 2232 static ssize_t rtw89_debug_fw_log_btc_manual_set(struct file *filp, 2233 const char __user *user_buf, 2234 size_t count, loff_t *loff) 2235 { 2236 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 2237 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2238 struct rtw89_fw_info *fw_info = &rtwdev->fw; 2239 bool fw_log_manual; 2240 2241 if (kstrtobool_from_user(user_buf, count, &fw_log_manual)) 2242 goto out; 2243 2244 mutex_lock(&rtwdev->mutex); 2245 fw_info->fw_log_enable = fw_log_manual; 2246 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 2247 mutex_unlock(&rtwdev->mutex); 2248 out: 2249 return count; 2250 } 2251 2252 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 2253 { 2254 static const char * const he_gi_str[] = { 2255 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 2256 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 2257 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 2258 }; 2259 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2260 struct rate_info *rate = &rtwsta->ra_report.txrate; 2261 struct ieee80211_rx_status *status = &rtwsta->rx_status; 2262 struct seq_file *m = (struct seq_file *)data; 2263 u8 rssi; 2264 2265 seq_printf(m, "TX rate [%d]: ", rtwsta->mac_id); 2266 2267 if (rate->flags & RATE_INFO_FLAGS_MCS) 2268 seq_printf(m, "HT MCS-%d%s", rate->mcs, 2269 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 2270 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 2271 seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs, 2272 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 2273 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 2274 seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs, 2275 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 2276 he_gi_str[rate->he_gi] : "N/A"); 2277 else 2278 seq_printf(m, "Legacy %d", rate->legacy); 2279 seq_printf(m, "\t(hw_rate=0x%x)", rtwsta->ra_report.hw_rate); 2280 seq_printf(m, "\t==> agg_wait=%d (%d)\n", rtwsta->max_agg_wait, 2281 sta->max_rc_amsdu_len); 2282 2283 seq_printf(m, "RX rate [%d]: ", rtwsta->mac_id); 2284 2285 switch (status->encoding) { 2286 case RX_ENC_LEGACY: 2287 seq_printf(m, "Legacy %d", status->rate_idx + 2288 (status->band == NL80211_BAND_5GHZ ? 4 : 0)); 2289 break; 2290 case RX_ENC_HT: 2291 seq_printf(m, "HT MCS-%d%s", status->rate_idx, 2292 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 2293 break; 2294 case RX_ENC_VHT: 2295 seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx, 2296 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 2297 break; 2298 case RX_ENC_HE: 2299 seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx, 2300 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 2301 he_gi_str[rate->he_gi] : "N/A"); 2302 break; 2303 } 2304 seq_printf(m, "\t(hw_rate=0x%x)\n", rtwsta->rx_hw_rate); 2305 2306 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 2307 seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d)\n", 2308 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta->prev_rssi); 2309 } 2310 2311 static void 2312 rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat, 2313 enum rtw89_hw_rate first_rate, int len) 2314 { 2315 int i; 2316 2317 for (i = 0; i < len; i++) 2318 seq_printf(m, "%s%u", i == 0 ? "" : ", ", 2319 pkt_stat->rx_rate_cnt[first_rate + i]); 2320 } 2321 2322 static const struct rtw89_rx_rate_cnt_info { 2323 enum rtw89_hw_rate first_rate; 2324 int len; 2325 const char *rate_mode; 2326 } rtw89_rx_rate_cnt_infos[] = { 2327 {RTW89_HW_RATE_CCK1, 4, "Legacy:"}, 2328 {RTW89_HW_RATE_OFDM6, 8, "OFDM:"}, 2329 {RTW89_HW_RATE_MCS0, 8, "HT 0:"}, 2330 {RTW89_HW_RATE_MCS8, 8, "HT 1:"}, 2331 {RTW89_HW_RATE_VHT_NSS1_MCS0, 10, "VHT 1SS:"}, 2332 {RTW89_HW_RATE_VHT_NSS2_MCS0, 10, "VHT 2SS:"}, 2333 {RTW89_HW_RATE_HE_NSS1_MCS0, 12, "HE 1SS:"}, 2334 {RTW89_HW_RATE_HE_NSS2_MCS0, 12, "HE 2ss:"}, 2335 }; 2336 2337 static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v) 2338 { 2339 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2340 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2341 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2342 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 2343 const struct rtw89_rx_rate_cnt_info *info; 2344 int i; 2345 2346 seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d), RX: %u [%u] Mbps (lv: %d)\n", 2347 stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv, 2348 stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv); 2349 seq_printf(m, "Beacon: %u\n", pkt_stat->beacon_nr); 2350 seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len, 2351 stats->rx_avg_len); 2352 2353 seq_puts(m, "RX count:\n"); 2354 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 2355 info = &rtw89_rx_rate_cnt_infos[i]; 2356 seq_printf(m, "%10s [", info->rate_mode); 2357 rtw89_debug_append_rx_rate(m, pkt_stat, 2358 info->first_rate, info->len); 2359 seq_puts(m, "]\n"); 2360 } 2361 2362 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m); 2363 2364 return 0; 2365 } 2366 2367 static struct rtw89_debugfs_priv rtw89_debug_priv_read_reg = { 2368 .cb_read = rtw89_debug_priv_read_reg_get, 2369 .cb_write = rtw89_debug_priv_read_reg_select, 2370 }; 2371 2372 static struct rtw89_debugfs_priv rtw89_debug_priv_write_reg = { 2373 .cb_write = rtw89_debug_priv_write_reg_set, 2374 }; 2375 2376 static struct rtw89_debugfs_priv rtw89_debug_priv_read_rf = { 2377 .cb_read = rtw89_debug_priv_read_rf_get, 2378 .cb_write = rtw89_debug_priv_read_rf_select, 2379 }; 2380 2381 static struct rtw89_debugfs_priv rtw89_debug_priv_write_rf = { 2382 .cb_write = rtw89_debug_priv_write_rf_set, 2383 }; 2384 2385 static struct rtw89_debugfs_priv rtw89_debug_priv_rf_reg_dump = { 2386 .cb_read = rtw89_debug_priv_rf_reg_dump_get, 2387 }; 2388 2389 static struct rtw89_debugfs_priv rtw89_debug_priv_txpwr_table = { 2390 .cb_read = rtw89_debug_priv_txpwr_table_get, 2391 }; 2392 2393 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_reg_dump = { 2394 .cb_read = rtw89_debug_priv_mac_reg_dump_get, 2395 .cb_write = rtw89_debug_priv_mac_reg_dump_select, 2396 }; 2397 2398 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_mem_dump = { 2399 .cb_read = rtw89_debug_priv_mac_mem_dump_get, 2400 .cb_write = rtw89_debug_priv_mac_mem_dump_select, 2401 }; 2402 2403 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_dbg_port_dump = { 2404 .cb_read = rtw89_debug_priv_mac_dbg_port_dump_get, 2405 .cb_write = rtw89_debug_priv_mac_dbg_port_dump_select, 2406 }; 2407 2408 static struct rtw89_debugfs_priv rtw89_debug_priv_send_h2c = { 2409 .cb_write = rtw89_debug_priv_send_h2c_set, 2410 }; 2411 2412 static struct rtw89_debugfs_priv rtw89_debug_priv_early_h2c = { 2413 .cb_read = rtw89_debug_priv_early_h2c_get, 2414 .cb_write = rtw89_debug_priv_early_h2c_set, 2415 }; 2416 2417 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_info = { 2418 .cb_read = rtw89_debug_priv_btc_info_get, 2419 }; 2420 2421 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_manual = { 2422 .cb_write = rtw89_debug_priv_btc_manual_set, 2423 }; 2424 2425 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_log_manual = { 2426 .cb_write = rtw89_debug_fw_log_btc_manual_set, 2427 }; 2428 2429 static struct rtw89_debugfs_priv rtw89_debug_priv_phy_info = { 2430 .cb_read = rtw89_debug_priv_phy_info_get, 2431 }; 2432 2433 #define rtw89_debugfs_add(name, mode, fopname, parent) \ 2434 do { \ 2435 rtw89_debug_priv_ ##name.rtwdev = rtwdev; \ 2436 if (!debugfs_create_file(#name, mode, \ 2437 parent, &rtw89_debug_priv_ ##name, \ 2438 &file_ops_ ##fopname)) \ 2439 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 2440 } while (0) 2441 2442 #define rtw89_debugfs_add_w(name) \ 2443 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 2444 #define rtw89_debugfs_add_rw(name) \ 2445 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 2446 #define rtw89_debugfs_add_r(name) \ 2447 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 2448 2449 void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 2450 { 2451 struct dentry *debugfs_topdir; 2452 2453 debugfs_topdir = debugfs_create_dir("rtw89", 2454 rtwdev->hw->wiphy->debugfsdir); 2455 2456 rtw89_debugfs_add_rw(read_reg); 2457 rtw89_debugfs_add_w(write_reg); 2458 rtw89_debugfs_add_rw(read_rf); 2459 rtw89_debugfs_add_w(write_rf); 2460 rtw89_debugfs_add_r(rf_reg_dump); 2461 rtw89_debugfs_add_r(txpwr_table); 2462 rtw89_debugfs_add_rw(mac_reg_dump); 2463 rtw89_debugfs_add_rw(mac_mem_dump); 2464 rtw89_debugfs_add_rw(mac_dbg_port_dump); 2465 rtw89_debugfs_add_w(send_h2c); 2466 rtw89_debugfs_add_rw(early_h2c); 2467 rtw89_debugfs_add_r(btc_info); 2468 rtw89_debugfs_add_w(btc_manual); 2469 rtw89_debugfs_add_w(fw_log_manual); 2470 rtw89_debugfs_add_r(phy_info); 2471 } 2472 #endif 2473 2474 #ifdef CONFIG_RTW89_DEBUGMSG 2475 void __rtw89_debug(struct rtw89_dev *rtwdev, 2476 enum rtw89_debug_mask mask, 2477 const char *fmt, ...) 2478 { 2479 struct va_format vaf = { 2480 .fmt = fmt, 2481 }; 2482 2483 va_list args; 2484 2485 va_start(args, fmt); 2486 vaf.va = &args; 2487 2488 if (rtw89_debug_mask & mask) 2489 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 2490 2491 va_end(args); 2492 } 2493 EXPORT_SYMBOL(__rtw89_debug); 2494 #endif 2495