1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include <linux/vmalloc.h> 6 7 #include "coex.h" 8 #include "debug.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "ps.h" 13 #include "reg.h" 14 #include "sar.h" 15 16 #ifdef CONFIG_RTW89_DEBUGMSG 17 unsigned int rtw89_debug_mask; 18 EXPORT_SYMBOL(rtw89_debug_mask); 19 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 20 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 21 #endif 22 23 #ifdef CONFIG_RTW89_DEBUGFS 24 struct rtw89_debugfs_priv { 25 struct rtw89_dev *rtwdev; 26 int (*cb_read)(struct seq_file *m, void *v); 27 ssize_t (*cb_write)(struct file *filp, const char __user *buffer, 28 size_t count, loff_t *loff); 29 union { 30 u32 cb_data; 31 struct { 32 u32 addr; 33 u8 len; 34 } read_reg; 35 struct { 36 u32 addr; 37 u32 mask; 38 u8 path; 39 } read_rf; 40 struct { 41 u8 ss_dbg:1; 42 u8 dle_dbg:1; 43 u8 dmac_dbg:1; 44 u8 cmac_dbg:1; 45 u8 dbg_port:1; 46 } dbgpkg_en; 47 struct { 48 u32 start; 49 u32 len; 50 u8 sel; 51 } mac_mem; 52 }; 53 }; 54 55 static const u16 rtw89_rate_info_bw_to_mhz_map[] = { 56 [RATE_INFO_BW_20] = 20, 57 [RATE_INFO_BW_40] = 40, 58 [RATE_INFO_BW_80] = 80, 59 [RATE_INFO_BW_160] = 160, 60 [RATE_INFO_BW_320] = 320, 61 }; 62 63 static u16 rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw) 64 { 65 if (bw < ARRAY_SIZE(rtw89_rate_info_bw_to_mhz_map)) 66 return rtw89_rate_info_bw_to_mhz_map[bw]; 67 68 return 0; 69 } 70 71 static int rtw89_debugfs_single_show(struct seq_file *m, void *v) 72 { 73 struct rtw89_debugfs_priv *debugfs_priv = m->private; 74 75 return debugfs_priv->cb_read(m, v); 76 } 77 78 static ssize_t rtw89_debugfs_single_write(struct file *filp, 79 const char __user *buffer, 80 size_t count, loff_t *loff) 81 { 82 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 83 84 return debugfs_priv->cb_write(filp, buffer, count, loff); 85 } 86 87 static ssize_t rtw89_debugfs_seq_file_write(struct file *filp, 88 const char __user *buffer, 89 size_t count, loff_t *loff) 90 { 91 struct seq_file *seqpriv = (struct seq_file *)filp->private_data; 92 struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private; 93 94 return debugfs_priv->cb_write(filp, buffer, count, loff); 95 } 96 97 static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp) 98 { 99 return single_open(filp, rtw89_debugfs_single_show, inode->i_private); 100 } 101 102 static int rtw89_debugfs_close(struct inode *inode, struct file *filp) 103 { 104 return 0; 105 } 106 107 static const struct file_operations file_ops_single_r = { 108 .owner = THIS_MODULE, 109 .open = rtw89_debugfs_single_open, 110 .read = seq_read, 111 .llseek = seq_lseek, 112 .release = single_release, 113 }; 114 115 static const struct file_operations file_ops_common_rw = { 116 .owner = THIS_MODULE, 117 .open = rtw89_debugfs_single_open, 118 .release = single_release, 119 .read = seq_read, 120 .llseek = seq_lseek, 121 .write = rtw89_debugfs_seq_file_write, 122 }; 123 124 static const struct file_operations file_ops_single_w = { 125 .owner = THIS_MODULE, 126 .write = rtw89_debugfs_single_write, 127 .open = simple_open, 128 .release = rtw89_debugfs_close, 129 }; 130 131 static ssize_t 132 rtw89_debug_priv_read_reg_select(struct file *filp, 133 const char __user *user_buf, 134 size_t count, loff_t *loff) 135 { 136 struct seq_file *m = (struct seq_file *)filp->private_data; 137 struct rtw89_debugfs_priv *debugfs_priv = m->private; 138 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 139 char buf[32]; 140 size_t buf_size; 141 u32 addr, len; 142 int num; 143 144 buf_size = min(count, sizeof(buf) - 1); 145 if (copy_from_user(buf, user_buf, buf_size)) 146 return -EFAULT; 147 148 buf[buf_size] = '\0'; 149 num = sscanf(buf, "%x %x", &addr, &len); 150 if (num != 2) { 151 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 152 return -EINVAL; 153 } 154 155 debugfs_priv->read_reg.addr = addr; 156 debugfs_priv->read_reg.len = len; 157 158 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 159 160 return count; 161 } 162 163 static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v) 164 { 165 struct rtw89_debugfs_priv *debugfs_priv = m->private; 166 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 167 u32 addr, data; 168 u8 len; 169 170 len = debugfs_priv->read_reg.len; 171 addr = debugfs_priv->read_reg.addr; 172 173 switch (len) { 174 case 1: 175 data = rtw89_read8(rtwdev, addr); 176 break; 177 case 2: 178 data = rtw89_read16(rtwdev, addr); 179 break; 180 case 4: 181 data = rtw89_read32(rtwdev, addr); 182 break; 183 default: 184 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 185 return -EINVAL; 186 } 187 188 seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data); 189 190 return 0; 191 } 192 193 static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp, 194 const char __user *user_buf, 195 size_t count, loff_t *loff) 196 { 197 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 198 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 199 char buf[32]; 200 size_t buf_size; 201 u32 addr, val, len; 202 int num; 203 204 buf_size = min(count, sizeof(buf) - 1); 205 if (copy_from_user(buf, user_buf, buf_size)) 206 return -EFAULT; 207 208 buf[buf_size] = '\0'; 209 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 210 if (num != 3) { 211 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 212 return -EINVAL; 213 } 214 215 switch (len) { 216 case 1: 217 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 218 rtw89_write8(rtwdev, addr, (u8)val); 219 break; 220 case 2: 221 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 222 rtw89_write16(rtwdev, addr, (u16)val); 223 break; 224 case 4: 225 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 226 rtw89_write32(rtwdev, addr, (u32)val); 227 break; 228 default: 229 rtw89_info(rtwdev, "invalid read write len %d\n", len); 230 break; 231 } 232 233 return count; 234 } 235 236 static ssize_t 237 rtw89_debug_priv_read_rf_select(struct file *filp, 238 const char __user *user_buf, 239 size_t count, loff_t *loff) 240 { 241 struct seq_file *m = (struct seq_file *)filp->private_data; 242 struct rtw89_debugfs_priv *debugfs_priv = m->private; 243 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 244 char buf[32]; 245 size_t buf_size; 246 u32 addr, mask; 247 u8 path; 248 int num; 249 250 buf_size = min(count, sizeof(buf) - 1); 251 if (copy_from_user(buf, user_buf, buf_size)) 252 return -EFAULT; 253 254 buf[buf_size] = '\0'; 255 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 256 if (num != 3) { 257 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 258 return -EINVAL; 259 } 260 261 if (path >= rtwdev->chip->rf_path_num) { 262 rtw89_info(rtwdev, "wrong rf path\n"); 263 return -EINVAL; 264 } 265 debugfs_priv->read_rf.addr = addr; 266 debugfs_priv->read_rf.mask = mask; 267 debugfs_priv->read_rf.path = path; 268 269 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 270 271 return count; 272 } 273 274 static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v) 275 { 276 struct rtw89_debugfs_priv *debugfs_priv = m->private; 277 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 278 u32 addr, data, mask; 279 u8 path; 280 281 addr = debugfs_priv->read_rf.addr; 282 mask = debugfs_priv->read_rf.mask; 283 path = debugfs_priv->read_rf.path; 284 285 data = rtw89_read_rf(rtwdev, path, addr, mask); 286 287 seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data); 288 289 return 0; 290 } 291 292 static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp, 293 const char __user *user_buf, 294 size_t count, loff_t *loff) 295 { 296 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 297 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 298 char buf[32]; 299 size_t buf_size; 300 u32 addr, val, mask; 301 u8 path; 302 int num; 303 304 buf_size = min(count, sizeof(buf) - 1); 305 if (copy_from_user(buf, user_buf, buf_size)) 306 return -EFAULT; 307 308 buf[buf_size] = '\0'; 309 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 310 if (num != 4) { 311 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 312 return -EINVAL; 313 } 314 315 if (path >= rtwdev->chip->rf_path_num) { 316 rtw89_info(rtwdev, "wrong rf path\n"); 317 return -EINVAL; 318 } 319 320 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 321 path, addr, val, mask); 322 rtw89_write_rf(rtwdev, path, addr, mask, val); 323 324 return count; 325 } 326 327 static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v) 328 { 329 struct rtw89_debugfs_priv *debugfs_priv = m->private; 330 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 331 const struct rtw89_chip_info *chip = rtwdev->chip; 332 u32 addr, offset, data; 333 u8 path; 334 335 for (path = 0; path < chip->rf_path_num; path++) { 336 seq_printf(m, "RF path %d:\n\n", path); 337 for (addr = 0; addr < 0x100; addr += 4) { 338 seq_printf(m, "0x%08x: ", addr); 339 for (offset = 0; offset < 4; offset++) { 340 data = rtw89_read_rf(rtwdev, path, 341 addr + offset, RFREG_MASK); 342 seq_printf(m, "0x%05x ", data); 343 } 344 seq_puts(m, "\n"); 345 } 346 seq_puts(m, "\n"); 347 } 348 349 return 0; 350 } 351 352 struct txpwr_ent { 353 const char *txt; 354 u8 len; 355 }; 356 357 struct txpwr_map { 358 const struct txpwr_ent *ent; 359 u8 size; 360 u32 addr_from; 361 u32 addr_to; 362 }; 363 364 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 365 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 366 367 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 368 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 369 370 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 371 { .len = 8, .txt = _t "\t- " \ 372 _e0 " " _e1 " " _e2 " " _e3 " " \ 373 _e4 " " _e5 " " _e6 " " _e7 } 374 375 static const struct txpwr_ent __txpwr_ent_byr[] = { 376 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 377 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 378 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 379 /* 1NSS */ 380 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 381 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 382 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 383 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 384 /* 2NSS */ 385 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 386 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 387 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 388 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 389 }; 390 391 static_assert((ARRAY_SIZE(__txpwr_ent_byr) * 4) == 392 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 393 394 static const struct txpwr_map __txpwr_map_byr = { 395 .ent = __txpwr_ent_byr, 396 .size = ARRAY_SIZE(__txpwr_ent_byr), 397 .addr_from = R_AX_PWR_BY_RATE, 398 .addr_to = R_AX_PWR_BY_RATE_MAX, 399 }; 400 401 static const struct txpwr_ent __txpwr_ent_lmt[] = { 402 /* 1TX */ 403 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 404 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 405 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 406 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 407 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 408 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 409 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 410 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 411 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 412 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 413 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 414 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 415 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 416 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 417 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 418 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 419 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 420 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 421 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 422 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 423 /* 2TX */ 424 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 425 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 426 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 427 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 428 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 429 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 430 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 431 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 432 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 433 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 434 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 435 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 436 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 437 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 438 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 439 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 440 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 441 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 442 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 443 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 444 }; 445 446 static_assert((ARRAY_SIZE(__txpwr_ent_lmt) * 2) == 447 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 448 449 static const struct txpwr_map __txpwr_map_lmt = { 450 .ent = __txpwr_ent_lmt, 451 .size = ARRAY_SIZE(__txpwr_ent_lmt), 452 .addr_from = R_AX_PWR_LMT, 453 .addr_to = R_AX_PWR_LMT_MAX, 454 }; 455 456 static const struct txpwr_ent __txpwr_ent_lmt_ru[] = { 457 /* 1TX */ 458 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 459 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 460 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 461 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 462 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 463 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 464 /* 2TX */ 465 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 466 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 467 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 468 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 469 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 470 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 471 }; 472 473 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru) * 8) == 474 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 475 476 static const struct txpwr_map __txpwr_map_lmt_ru = { 477 .ent = __txpwr_ent_lmt_ru, 478 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru), 479 .addr_from = R_AX_PWR_RU_LMT, 480 .addr_to = R_AX_PWR_RU_LMT_MAX, 481 }; 482 483 static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent, 484 const s8 *buf, const u8 cur) 485 { 486 char *fmt; 487 488 switch (ent->len) { 489 case 2: 490 fmt = "%s\t| %3d, %3d,\tdBm\n"; 491 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]); 492 return 2; 493 case 4: 494 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 495 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 496 buf[cur + 2], buf[cur + 3]); 497 return 4; 498 case 8: 499 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 500 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 501 buf[cur + 2], buf[cur + 3], buf[cur + 4], 502 buf[cur + 5], buf[cur + 6], buf[cur + 7]); 503 return 8; 504 default: 505 return 0; 506 } 507 } 508 509 static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev, 510 const struct txpwr_map *map) 511 { 512 u8 fct = rtwdev->chip->txpwr_factor_mac; 513 u32 val, addr; 514 s8 *buf, tmp; 515 u8 cur, i; 516 int ret; 517 518 buf = vzalloc(map->addr_to - map->addr_from + 4); 519 if (!buf) 520 return -ENOMEM; 521 522 for (addr = map->addr_from; addr <= map->addr_to; addr += 4) { 523 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 524 if (ret) 525 val = MASKDWORD; 526 527 cur = addr - map->addr_from; 528 for (i = 0; i < 4; i++, val >>= 8) { 529 /* signed 7 bits, and reserved BIT(7) */ 530 tmp = sign_extend32(val, 6); 531 buf[cur + i] = tmp >> fct; 532 } 533 } 534 535 for (cur = 0, i = 0; i < map->size; i++) 536 cur += __print_txpwr_ent(m, &map->ent[i], buf, cur); 537 538 vfree(buf); 539 return 0; 540 } 541 542 #define case_REGD(_regd) \ 543 case RTW89_ ## _regd: \ 544 seq_puts(m, #_regd "\n"); \ 545 break 546 547 static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev) 548 { 549 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 550 u8 band = chan->band_type; 551 u8 regd = rtw89_regd_get(rtwdev, band); 552 553 switch (regd) { 554 default: 555 seq_printf(m, "UNKNOWN: %d\n", regd); 556 break; 557 case_REGD(WW); 558 case_REGD(ETSI); 559 case_REGD(FCC); 560 case_REGD(MKK); 561 case_REGD(NA); 562 case_REGD(IC); 563 case_REGD(KCC); 564 case_REGD(NCC); 565 case_REGD(CHILE); 566 case_REGD(ACMA); 567 case_REGD(MEXICO); 568 case_REGD(UKRAINE); 569 case_REGD(CN); 570 } 571 } 572 573 #undef case_REGD 574 575 static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v) 576 { 577 struct rtw89_debugfs_priv *debugfs_priv = m->private; 578 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 579 int ret = 0; 580 581 mutex_lock(&rtwdev->mutex); 582 rtw89_leave_ps_mode(rtwdev); 583 584 seq_puts(m, "[Regulatory] "); 585 __print_regd(m, rtwdev); 586 587 seq_puts(m, "[SAR]\n"); 588 rtw89_print_sar(m, rtwdev); 589 590 seq_puts(m, "\n[TX power byrate]\n"); 591 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_byr); 592 if (ret) 593 goto err; 594 595 seq_puts(m, "\n[TX power limit]\n"); 596 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt); 597 if (ret) 598 goto err; 599 600 seq_puts(m, "\n[TX power limit_ru]\n"); 601 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt_ru); 602 if (ret) 603 goto err; 604 605 err: 606 mutex_unlock(&rtwdev->mutex); 607 return ret; 608 } 609 610 static ssize_t 611 rtw89_debug_priv_mac_reg_dump_select(struct file *filp, 612 const char __user *user_buf, 613 size_t count, loff_t *loff) 614 { 615 struct seq_file *m = (struct seq_file *)filp->private_data; 616 struct rtw89_debugfs_priv *debugfs_priv = m->private; 617 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 618 const struct rtw89_chip_info *chip = rtwdev->chip; 619 char buf[32]; 620 size_t buf_size; 621 int sel; 622 int ret; 623 624 buf_size = min(count, sizeof(buf) - 1); 625 if (copy_from_user(buf, user_buf, buf_size)) 626 return -EFAULT; 627 628 buf[buf_size] = '\0'; 629 ret = kstrtoint(buf, 0, &sel); 630 if (ret) 631 return ret; 632 633 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 634 rtw89_info(rtwdev, "invalid args: %d\n", sel); 635 return -EINVAL; 636 } 637 638 if (sel == RTW89_DBG_SEL_MAC_30 && chip->chip_id != RTL8852C) { 639 rtw89_info(rtwdev, "sel %d is address hole on chip %d\n", sel, 640 chip->chip_id); 641 return -EINVAL; 642 } 643 644 debugfs_priv->cb_data = sel; 645 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 646 647 return count; 648 } 649 650 #define RTW89_MAC_PAGE_SIZE 0x100 651 652 static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v) 653 { 654 struct rtw89_debugfs_priv *debugfs_priv = m->private; 655 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 656 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 657 u32 start, end; 658 u32 i, j, k, page; 659 u32 val; 660 661 switch (reg_sel) { 662 case RTW89_DBG_SEL_MAC_00: 663 seq_puts(m, "Debug selected MAC page 0x00\n"); 664 start = 0x000; 665 end = 0x014; 666 break; 667 case RTW89_DBG_SEL_MAC_30: 668 seq_puts(m, "Debug selected MAC page 0x30\n"); 669 start = 0x030; 670 end = 0x033; 671 break; 672 case RTW89_DBG_SEL_MAC_40: 673 seq_puts(m, "Debug selected MAC page 0x40\n"); 674 start = 0x040; 675 end = 0x07f; 676 break; 677 case RTW89_DBG_SEL_MAC_80: 678 seq_puts(m, "Debug selected MAC page 0x80\n"); 679 start = 0x080; 680 end = 0x09f; 681 break; 682 case RTW89_DBG_SEL_MAC_C0: 683 seq_puts(m, "Debug selected MAC page 0xc0\n"); 684 start = 0x0c0; 685 end = 0x0df; 686 break; 687 case RTW89_DBG_SEL_MAC_E0: 688 seq_puts(m, "Debug selected MAC page 0xe0\n"); 689 start = 0x0e0; 690 end = 0x0ff; 691 break; 692 case RTW89_DBG_SEL_BB: 693 seq_puts(m, "Debug selected BB register\n"); 694 start = 0x100; 695 end = 0x17f; 696 break; 697 case RTW89_DBG_SEL_IQK: 698 seq_puts(m, "Debug selected IQK register\n"); 699 start = 0x180; 700 end = 0x1bf; 701 break; 702 case RTW89_DBG_SEL_RFC: 703 seq_puts(m, "Debug selected RFC register\n"); 704 start = 0x1c0; 705 end = 0x1ff; 706 break; 707 default: 708 seq_puts(m, "Selected invalid register page\n"); 709 return -EINVAL; 710 } 711 712 for (i = start; i <= end; i++) { 713 page = i << 8; 714 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 715 seq_printf(m, "%08xh : ", 0x18600000 + j); 716 for (k = 0; k < 4; k++) { 717 val = rtw89_read32(rtwdev, j + (k << 2)); 718 seq_printf(m, "%08x ", val); 719 } 720 seq_puts(m, "\n"); 721 } 722 } 723 724 return 0; 725 } 726 727 static ssize_t 728 rtw89_debug_priv_mac_mem_dump_select(struct file *filp, 729 const char __user *user_buf, 730 size_t count, loff_t *loff) 731 { 732 struct seq_file *m = (struct seq_file *)filp->private_data; 733 struct rtw89_debugfs_priv *debugfs_priv = m->private; 734 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 735 char buf[32]; 736 size_t buf_size; 737 u32 sel, start_addr, len; 738 int num; 739 740 buf_size = min(count, sizeof(buf) - 1); 741 if (copy_from_user(buf, user_buf, buf_size)) 742 return -EFAULT; 743 744 buf[buf_size] = '\0'; 745 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 746 if (num != 3) { 747 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 748 return -EINVAL; 749 } 750 751 debugfs_priv->mac_mem.sel = sel; 752 debugfs_priv->mac_mem.start = start_addr; 753 debugfs_priv->mac_mem.len = len; 754 755 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 756 sel, start_addr, len); 757 758 return count; 759 } 760 761 static void rtw89_debug_dump_mac_mem(struct seq_file *m, 762 struct rtw89_dev *rtwdev, 763 u8 sel, u32 start_addr, u32 len) 764 { 765 u32 base_addr, start_page, residue; 766 u32 i, j, p, pages; 767 u32 dump_len, remain; 768 u32 val; 769 770 remain = len; 771 pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1; 772 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE; 773 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE; 774 base_addr = rtw89_mac_mem_base_addrs[sel]; 775 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE; 776 777 for (p = 0; p < pages; p++) { 778 dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE); 779 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, base_addr); 780 for (i = R_AX_INDIR_ACCESS_ENTRY + residue; 781 i < R_AX_INDIR_ACCESS_ENTRY + dump_len;) { 782 seq_printf(m, "%08xh:", i); 783 for (j = 0; 784 j < 4 && i < R_AX_INDIR_ACCESS_ENTRY + dump_len; 785 j++, i += 4) { 786 val = rtw89_read32(rtwdev, i); 787 seq_printf(m, " %08x", val); 788 remain -= 4; 789 } 790 seq_puts(m, "\n"); 791 } 792 base_addr += MAC_MEM_DUMP_PAGE_SIZE; 793 } 794 } 795 796 static int 797 rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v) 798 { 799 struct rtw89_debugfs_priv *debugfs_priv = m->private; 800 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 801 bool grant_read = false; 802 803 if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM) 804 return -ENOENT; 805 806 if (rtwdev->chip->chip_id == RTL8852C) { 807 switch (debugfs_priv->mac_mem.sel) { 808 case RTW89_MAC_MEM_TXD_FIFO_0_V1: 809 case RTW89_MAC_MEM_TXD_FIFO_1_V1: 810 case RTW89_MAC_MEM_TXDATA_FIFO_0: 811 case RTW89_MAC_MEM_TXDATA_FIFO_1: 812 grant_read = true; 813 break; 814 default: 815 break; 816 } 817 } 818 819 mutex_lock(&rtwdev->mutex); 820 rtw89_leave_ps_mode(rtwdev); 821 if (grant_read) 822 rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 823 rtw89_debug_dump_mac_mem(m, rtwdev, 824 debugfs_priv->mac_mem.sel, 825 debugfs_priv->mac_mem.start, 826 debugfs_priv->mac_mem.len); 827 if (grant_read) 828 rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 829 mutex_unlock(&rtwdev->mutex); 830 831 return 0; 832 } 833 834 static ssize_t 835 rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp, 836 const char __user *user_buf, 837 size_t count, loff_t *loff) 838 { 839 struct seq_file *m = (struct seq_file *)filp->private_data; 840 struct rtw89_debugfs_priv *debugfs_priv = m->private; 841 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 842 char buf[32]; 843 size_t buf_size; 844 int sel, set; 845 int num; 846 bool enable; 847 848 buf_size = min(count, sizeof(buf) - 1); 849 if (copy_from_user(buf, user_buf, buf_size)) 850 return -EFAULT; 851 852 buf[buf_size] = '\0'; 853 num = sscanf(buf, "%d %d", &sel, &set); 854 if (num != 2) { 855 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 856 return -EINVAL; 857 } 858 859 enable = set != 0; 860 switch (sel) { 861 case 0: 862 debugfs_priv->dbgpkg_en.ss_dbg = enable; 863 break; 864 case 1: 865 debugfs_priv->dbgpkg_en.dle_dbg = enable; 866 break; 867 case 2: 868 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 869 break; 870 case 3: 871 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 872 break; 873 case 4: 874 debugfs_priv->dbgpkg_en.dbg_port = enable; 875 break; 876 default: 877 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 878 return -EINVAL; 879 } 880 881 rtw89_info(rtwdev, "%s debug port dump %d\n", 882 enable ? "Enable" : "Disable", sel); 883 884 return count; 885 } 886 887 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 888 struct seq_file *m) 889 { 890 return 0; 891 } 892 893 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 894 struct seq_file *m) 895 { 896 #define DLE_DFI_DUMP(__type, __target, __sel) \ 897 ({ \ 898 u32 __ctrl; \ 899 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 900 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 901 u32 __data, __val32; \ 902 int __ret; \ 903 \ 904 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 905 DLE_DFI_TYPE_##__target) | \ 906 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 907 B_AX_WDE_DFI_ACTIVE; \ 908 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 909 __ret = read_poll_timeout(rtw89_read32, __val32, \ 910 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 911 1000, 50000, false, \ 912 rtwdev, __reg_ctrl); \ 913 if (__ret) { \ 914 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 915 #__type, #__target, __sel); \ 916 return __ret; \ 917 } \ 918 \ 919 __data = rtw89_read32(rtwdev, __reg_data); \ 920 __data; \ 921 }) 922 923 #define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \ 924 ({ \ 925 u32 __freepg, __pubpg; \ 926 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 927 \ 928 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 929 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 930 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 931 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 932 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 933 seq_printf(__m, "[%s] freepg head: %d\n", \ 934 #__type, __freepg_head); \ 935 seq_printf(__m, "[%s] freepg tail: %d\n", \ 936 #__type, __freepg_tail); \ 937 seq_printf(__m, "[%s] pubpg num : %d\n", \ 938 #__type, __pubpg_num); \ 939 }) 940 941 #define case_QUOTA(__m, __type, __id) \ 942 case __type##_QTAID_##__id: \ 943 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 944 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 945 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 946 seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \ 947 #__type, #__id, rsv_pgnum); \ 948 seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \ 949 #__type, #__id, use_pgnum); \ 950 break 951 u32 quota_id; 952 u32 val32; 953 u16 rsv_pgnum, use_pgnum; 954 int ret; 955 956 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 957 if (ret) { 958 seq_puts(m, "[DLE] : DMAC not enabled\n"); 959 return ret; 960 } 961 962 DLE_DFI_FREE_PAGE_DUMP(m, WDE); 963 DLE_DFI_FREE_PAGE_DUMP(m, PLE); 964 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 965 switch (quota_id) { 966 case_QUOTA(m, WDE, HOST_IF); 967 case_QUOTA(m, WDE, WLAN_CPU); 968 case_QUOTA(m, WDE, DATA_CPU); 969 case_QUOTA(m, WDE, PKTIN); 970 case_QUOTA(m, WDE, CPUIO); 971 } 972 } 973 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 974 switch (quota_id) { 975 case_QUOTA(m, PLE, B0_TXPL); 976 case_QUOTA(m, PLE, B1_TXPL); 977 case_QUOTA(m, PLE, C2H); 978 case_QUOTA(m, PLE, H2C); 979 case_QUOTA(m, PLE, WLAN_CPU); 980 case_QUOTA(m, PLE, MPDU); 981 case_QUOTA(m, PLE, CMAC0_RX); 982 case_QUOTA(m, PLE, CMAC1_RX); 983 case_QUOTA(m, PLE, CMAC1_BBRPT); 984 case_QUOTA(m, PLE, WDRLS); 985 case_QUOTA(m, PLE, CPUIO); 986 } 987 } 988 989 return 0; 990 991 #undef case_QUOTA 992 #undef DLE_DFI_DUMP 993 #undef DLE_DFI_FREE_PAGE_DUMP 994 } 995 996 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 997 struct seq_file *m) 998 { 999 const struct rtw89_chip_info *chip = rtwdev->chip; 1000 u32 dmac_err; 1001 int i, ret; 1002 1003 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1004 if (ret) { 1005 seq_puts(m, "[DMAC] : DMAC not enabled\n"); 1006 return ret; 1007 } 1008 1009 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 1010 seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 1011 seq_printf(m, "R_AX_DMAC_ERR_IMR=0x%08x\n", 1012 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 1013 1014 if (dmac_err) { 1015 seq_printf(m, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 1016 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 1017 seq_printf(m, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 1018 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 1019 if (chip->chip_id == RTL8852C) { 1020 seq_printf(m, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 1021 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 1022 seq_printf(m, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 1023 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 1024 seq_printf(m, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 1025 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 1026 seq_printf(m, "R_AX_PLE_DBGERR_STS=0x%08x\n", 1027 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 1028 } 1029 } 1030 1031 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 1032 seq_printf(m, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 1033 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 1034 seq_printf(m, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 1035 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 1036 if (chip->chip_id == RTL8852C) 1037 seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1038 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 1039 else 1040 seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1041 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 1042 } 1043 1044 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 1045 if (chip->chip_id == RTL8852C) { 1046 seq_printf(m, "R_AX_SEC_ERR_IMR=0x%08x\n", 1047 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 1048 seq_printf(m, "R_AX_SEC_ERR_ISR=0x%08x\n", 1049 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 1050 seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n", 1051 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1052 seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n", 1053 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1054 seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1055 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1056 seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n", 1057 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1058 seq_printf(m, "R_AX_SEC_DEBUG1=0x%08x\n", 1059 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 1060 seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n", 1061 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1062 seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n", 1063 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1064 1065 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1066 B_AX_DBG_SEL0, 0x8B); 1067 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1068 B_AX_DBG_SEL1, 0x8B); 1069 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 1070 B_AX_SEL_0XC0_MASK, 1); 1071 for (i = 0; i < 0x10; i++) { 1072 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 1073 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 1074 seq_printf(m, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 1075 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 1076 } 1077 } else { 1078 seq_printf(m, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 1079 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 1080 seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n", 1081 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1082 seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n", 1083 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1084 seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1085 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1086 seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n", 1087 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1088 seq_printf(m, "R_AX_SEC_CAM_WDATA=0x%08x\n", 1089 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 1090 seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n", 1091 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1092 seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n", 1093 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1094 seq_printf(m, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 1095 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 1096 seq_printf(m, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 1097 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 1098 } 1099 } 1100 1101 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 1102 seq_printf(m, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 1103 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 1104 seq_printf(m, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 1105 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 1106 seq_printf(m, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 1107 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 1108 seq_printf(m, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 1109 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 1110 } 1111 1112 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 1113 seq_printf(m, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 1114 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 1115 seq_printf(m, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 1116 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 1117 } 1118 1119 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 1120 seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n", 1121 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1122 seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n", 1123 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1124 seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n", 1125 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1126 seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1127 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1128 } 1129 1130 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 1131 if (chip->chip_id == RTL8852C) { 1132 seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 1133 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 1134 seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 1135 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 1136 seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 1137 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 1138 seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 1139 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 1140 } else { 1141 seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 1142 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 1143 seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 1144 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 1145 } 1146 } 1147 1148 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 1149 seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n", 1150 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1151 seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n", 1152 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1153 seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n", 1154 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1155 seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1156 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1157 seq_printf(m, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 1158 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 1159 seq_printf(m, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 1160 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 1161 seq_printf(m, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 1162 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 1163 seq_printf(m, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 1164 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 1165 seq_printf(m, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 1166 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 1167 seq_printf(m, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 1168 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 1169 seq_printf(m, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 1170 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 1171 seq_printf(m, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 1172 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 1173 if (chip->chip_id == RTL8852C) { 1174 seq_printf(m, "R_AX_RX_CTRL0=0x%08x\n", 1175 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 1176 seq_printf(m, "R_AX_RX_CTRL1=0x%08x\n", 1177 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 1178 seq_printf(m, "R_AX_RX_CTRL2=0x%08x\n", 1179 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 1180 } else { 1181 seq_printf(m, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 1182 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 1183 seq_printf(m, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 1184 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 1185 seq_printf(m, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 1186 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 1187 } 1188 } 1189 1190 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 1191 seq_printf(m, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 1192 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 1193 seq_printf(m, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 1194 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 1195 } 1196 1197 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 1198 seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 1199 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 1200 seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 1201 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 1202 seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 1203 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 1204 seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 1205 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 1206 seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 1207 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 1208 seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 1209 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 1210 } 1211 1212 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 1213 if (chip->chip_id == RTL8852C) { 1214 seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 1215 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 1216 seq_printf(m, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 1217 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 1218 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1219 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1220 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1221 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1222 seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1223 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1224 seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1225 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1226 } else { 1227 seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 1228 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 1229 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1230 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1231 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1232 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1233 seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1234 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1235 seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1236 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1237 } 1238 } 1239 1240 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 1241 seq_printf(m, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 1242 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 1243 seq_printf(m, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 1244 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 1245 } 1246 1247 return 0; 1248 } 1249 1250 static int rtw89_debug_mac_dump_cmac_err(struct rtw89_dev *rtwdev, 1251 struct seq_file *m, 1252 enum rtw89_mac_idx band) 1253 { 1254 const struct rtw89_chip_info *chip = rtwdev->chip; 1255 u32 offset = 0; 1256 u32 cmac_err; 1257 int ret; 1258 1259 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 1260 if (ret) { 1261 if (band) 1262 seq_puts(m, "[CMAC] : CMAC1 not enabled\n"); 1263 else 1264 seq_puts(m, "[CMAC] : CMAC0 not enabled\n"); 1265 return ret; 1266 } 1267 1268 if (band) 1269 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 1270 1271 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 1272 seq_printf(m, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 1273 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 1274 seq_printf(m, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 1275 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 1276 seq_printf(m, "R_AX_CK_EN [%d]=0x%08x\n", band, 1277 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 1278 1279 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 1280 seq_printf(m, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 1281 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 1282 seq_printf(m, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 1283 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 1284 } 1285 1286 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 1287 seq_printf(m, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 1288 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 1289 seq_printf(m, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 1290 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 1291 } 1292 1293 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 1294 if (chip->chip_id == RTL8852C) { 1295 seq_printf(m, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 1296 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 1297 seq_printf(m, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 1298 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 1299 } else { 1300 seq_printf(m, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 1301 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 1302 } 1303 } 1304 1305 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 1306 if (chip->chip_id == RTL8852C) { 1307 seq_printf(m, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 1308 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 1309 seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 1310 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1311 } else { 1312 seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 1313 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1314 } 1315 } 1316 1317 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 1318 seq_printf(m, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 1319 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 1320 seq_printf(m, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 1321 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 1322 } 1323 1324 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 1325 if (chip->chip_id == RTL8852C) { 1326 seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 1327 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 1328 seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 1329 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 1330 } else { 1331 seq_printf(m, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 1332 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 1333 } 1334 seq_printf(m, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 1335 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 1336 } 1337 1338 seq_printf(m, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 1339 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 1340 1341 return 0; 1342 } 1343 1344 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 1345 struct seq_file *m) 1346 { 1347 rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_0); 1348 if (rtwdev->dbcc_en) 1349 rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_1); 1350 1351 return 0; 1352 } 1353 1354 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1355 .sel_addr = R_AX_PTCL_DBG, 1356 .sel_byte = 1, 1357 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1358 .srt = 0x00, 1359 .end = 0x3F, 1360 .rd_addr = R_AX_PTCL_DBG_INFO, 1361 .rd_byte = 4, 1362 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1363 }; 1364 1365 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1366 .sel_addr = R_AX_PTCL_DBG_C1, 1367 .sel_byte = 1, 1368 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1369 .srt = 0x00, 1370 .end = 0x3F, 1371 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1372 .rd_byte = 4, 1373 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1374 }; 1375 1376 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx0_5 = { 1377 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1378 .sel_byte = 2, 1379 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1380 .srt = 0x0, 1381 .end = 0xD, 1382 .rd_addr = R_AX_DBG_PORT_SEL, 1383 .rd_byte = 4, 1384 .rd_msk = B_AX_DEBUG_ST_MASK 1385 }; 1386 1387 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx6 = { 1388 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1389 .sel_byte = 2, 1390 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1391 .srt = 0x0, 1392 .end = 0x5, 1393 .rd_addr = R_AX_DBG_PORT_SEL, 1394 .rd_byte = 4, 1395 .rd_msk = B_AX_DEBUG_ST_MASK 1396 }; 1397 1398 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx7 = { 1399 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1400 .sel_byte = 2, 1401 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1402 .srt = 0x0, 1403 .end = 0x9, 1404 .rd_addr = R_AX_DBG_PORT_SEL, 1405 .rd_byte = 4, 1406 .rd_msk = B_AX_DEBUG_ST_MASK 1407 }; 1408 1409 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx8 = { 1410 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1411 .sel_byte = 2, 1412 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1413 .srt = 0x0, 1414 .end = 0x3, 1415 .rd_addr = R_AX_DBG_PORT_SEL, 1416 .rd_byte = 4, 1417 .rd_msk = B_AX_DEBUG_ST_MASK 1418 }; 1419 1420 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx9_C = { 1421 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1422 .sel_byte = 2, 1423 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1424 .srt = 0x0, 1425 .end = 0x1, 1426 .rd_addr = R_AX_DBG_PORT_SEL, 1427 .rd_byte = 4, 1428 .rd_msk = B_AX_DEBUG_ST_MASK 1429 }; 1430 1431 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_txD = { 1432 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1433 .sel_byte = 2, 1434 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1435 .srt = 0x0, 1436 .end = 0x0, 1437 .rd_addr = R_AX_DBG_PORT_SEL, 1438 .rd_byte = 4, 1439 .rd_msk = B_AX_DEBUG_ST_MASK 1440 }; 1441 1442 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx0 = { 1443 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1444 .sel_byte = 2, 1445 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1446 .srt = 0x0, 1447 .end = 0xB, 1448 .rd_addr = R_AX_DBG_PORT_SEL, 1449 .rd_byte = 4, 1450 .rd_msk = B_AX_DEBUG_ST_MASK 1451 }; 1452 1453 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx1 = { 1454 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1455 .sel_byte = 2, 1456 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1457 .srt = 0x0, 1458 .end = 0x4, 1459 .rd_addr = R_AX_DBG_PORT_SEL, 1460 .rd_byte = 4, 1461 .rd_msk = B_AX_DEBUG_ST_MASK 1462 }; 1463 1464 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx3 = { 1465 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1466 .sel_byte = 2, 1467 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1468 .srt = 0x0, 1469 .end = 0x8, 1470 .rd_addr = R_AX_DBG_PORT_SEL, 1471 .rd_byte = 4, 1472 .rd_msk = B_AX_DEBUG_ST_MASK 1473 }; 1474 1475 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx4 = { 1476 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1477 .sel_byte = 2, 1478 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1479 .srt = 0x0, 1480 .end = 0x7, 1481 .rd_addr = R_AX_DBG_PORT_SEL, 1482 .rd_byte = 4, 1483 .rd_msk = B_AX_DEBUG_ST_MASK 1484 }; 1485 1486 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx5_8 = { 1487 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1488 .sel_byte = 2, 1489 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1490 .srt = 0x0, 1491 .end = 0x1, 1492 .rd_addr = R_AX_DBG_PORT_SEL, 1493 .rd_byte = 4, 1494 .rd_msk = B_AX_DEBUG_ST_MASK 1495 }; 1496 1497 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx9 = { 1498 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1499 .sel_byte = 2, 1500 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1501 .srt = 0x0, 1502 .end = 0x3, 1503 .rd_addr = R_AX_DBG_PORT_SEL, 1504 .rd_byte = 4, 1505 .rd_msk = B_AX_DEBUG_ST_MASK 1506 }; 1507 1508 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_txA_C = { 1509 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1510 .sel_byte = 2, 1511 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1512 .srt = 0x0, 1513 .end = 0x0, 1514 .rd_addr = R_AX_DBG_PORT_SEL, 1515 .rd_byte = 4, 1516 .rd_msk = B_AX_DEBUG_ST_MASK 1517 }; 1518 1519 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx0 = { 1520 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1521 .sel_byte = 2, 1522 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1523 .srt = 0x0, 1524 .end = 0x8, 1525 .rd_addr = R_AX_DBG_PORT_SEL, 1526 .rd_byte = 4, 1527 .rd_msk = B_AX_DEBUG_ST_MASK 1528 }; 1529 1530 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx1_2 = { 1531 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1532 .sel_byte = 2, 1533 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1534 .srt = 0x0, 1535 .end = 0x0, 1536 .rd_addr = R_AX_DBG_PORT_SEL, 1537 .rd_byte = 4, 1538 .rd_msk = B_AX_DEBUG_ST_MASK 1539 }; 1540 1541 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx3 = { 1542 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1543 .sel_byte = 2, 1544 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1545 .srt = 0x0, 1546 .end = 0x6, 1547 .rd_addr = R_AX_DBG_PORT_SEL, 1548 .rd_byte = 4, 1549 .rd_msk = B_AX_DEBUG_ST_MASK 1550 }; 1551 1552 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx4 = { 1553 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1554 .sel_byte = 2, 1555 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1556 .srt = 0x0, 1557 .end = 0x0, 1558 .rd_addr = R_AX_DBG_PORT_SEL, 1559 .rd_byte = 4, 1560 .rd_msk = B_AX_DEBUG_ST_MASK 1561 }; 1562 1563 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx5 = { 1564 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1565 .sel_byte = 2, 1566 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1567 .srt = 0x0, 1568 .end = 0x0, 1569 .rd_addr = R_AX_DBG_PORT_SEL, 1570 .rd_byte = 4, 1571 .rd_msk = B_AX_DEBUG_ST_MASK 1572 }; 1573 1574 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_0 = { 1575 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1576 .sel_byte = 1, 1577 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1578 .srt = 0x0, 1579 .end = 0x3, 1580 .rd_addr = R_AX_DBG_PORT_SEL, 1581 .rd_byte = 4, 1582 .rd_msk = B_AX_DEBUG_ST_MASK 1583 }; 1584 1585 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_1 = { 1586 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1587 .sel_byte = 1, 1588 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1589 .srt = 0x0, 1590 .end = 0x6, 1591 .rd_addr = R_AX_DBG_PORT_SEL, 1592 .rd_byte = 4, 1593 .rd_msk = B_AX_DEBUG_ST_MASK 1594 }; 1595 1596 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_2 = { 1597 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1598 .sel_byte = 1, 1599 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1600 .srt = 0x0, 1601 .end = 0x0, 1602 .rd_addr = R_AX_DBG_PORT_SEL, 1603 .rd_byte = 4, 1604 .rd_msk = B_AX_DEBUG_ST_MASK 1605 }; 1606 1607 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p1 = { 1608 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1609 .sel_byte = 1, 1610 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1611 .srt = 0x8, 1612 .end = 0xE, 1613 .rd_addr = R_AX_DBG_PORT_SEL, 1614 .rd_byte = 4, 1615 .rd_msk = B_AX_DEBUG_ST_MASK 1616 }; 1617 1618 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_stf_ctrl = { 1619 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1620 .sel_byte = 1, 1621 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1622 .srt = 0x0, 1623 .end = 0x5, 1624 .rd_addr = R_AX_DBG_PORT_SEL, 1625 .rd_byte = 4, 1626 .rd_msk = B_AX_DEBUG_ST_MASK 1627 }; 1628 1629 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_addr_ctrl = { 1630 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1631 .sel_byte = 1, 1632 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1633 .srt = 0x0, 1634 .end = 0x6, 1635 .rd_addr = R_AX_DBG_PORT_SEL, 1636 .rd_byte = 4, 1637 .rd_msk = B_AX_DEBUG_ST_MASK 1638 }; 1639 1640 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_wde_intf = { 1641 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1642 .sel_byte = 1, 1643 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1644 .srt = 0x0, 1645 .end = 0xF, 1646 .rd_addr = R_AX_DBG_PORT_SEL, 1647 .rd_byte = 4, 1648 .rd_msk = B_AX_DEBUG_ST_MASK 1649 }; 1650 1651 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_ple_intf = { 1652 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1653 .sel_byte = 1, 1654 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1655 .srt = 0x0, 1656 .end = 0x9, 1657 .rd_addr = R_AX_DBG_PORT_SEL, 1658 .rd_byte = 4, 1659 .rd_msk = B_AX_DEBUG_ST_MASK 1660 }; 1661 1662 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_flow_ctrl = { 1663 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1664 .sel_byte = 1, 1665 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1666 .srt = 0x0, 1667 .end = 0x3, 1668 .rd_addr = R_AX_DBG_PORT_SEL, 1669 .rd_byte = 4, 1670 .rd_msk = B_AX_DEBUG_ST_MASK 1671 }; 1672 1673 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 1674 .sel_addr = R_AX_SCH_DBG_SEL, 1675 .sel_byte = 1, 1676 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1677 .srt = 0x00, 1678 .end = 0x2F, 1679 .rd_addr = R_AX_SCH_DBG, 1680 .rd_byte = 4, 1681 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1682 }; 1683 1684 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 1685 .sel_addr = R_AX_SCH_DBG_SEL_C1, 1686 .sel_byte = 1, 1687 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1688 .srt = 0x00, 1689 .end = 0x2F, 1690 .rd_addr = R_AX_SCH_DBG_C1, 1691 .rd_byte = 4, 1692 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1693 }; 1694 1695 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 1696 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 1697 .sel_byte = 1, 1698 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1699 .srt = 0x00, 1700 .end = 0x19, 1701 .rd_addr = R_AX_DBG_PORT_SEL, 1702 .rd_byte = 4, 1703 .rd_msk = B_AX_DEBUG_ST_MASK 1704 }; 1705 1706 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 1707 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 1708 .sel_byte = 1, 1709 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1710 .srt = 0x00, 1711 .end = 0x19, 1712 .rd_addr = R_AX_DBG_PORT_SEL, 1713 .rd_byte = 4, 1714 .rd_msk = B_AX_DEBUG_ST_MASK 1715 }; 1716 1717 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 1718 .sel_addr = R_AX_RX_DEBUG_SELECT, 1719 .sel_byte = 1, 1720 .sel_msk = B_AX_DEBUG_SEL_MASK, 1721 .srt = 0x00, 1722 .end = 0x58, 1723 .rd_addr = R_AX_DBG_PORT_SEL, 1724 .rd_byte = 4, 1725 .rd_msk = B_AX_DEBUG_ST_MASK 1726 }; 1727 1728 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 1729 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 1730 .sel_byte = 1, 1731 .sel_msk = B_AX_DEBUG_SEL_MASK, 1732 .srt = 0x00, 1733 .end = 0x58, 1734 .rd_addr = R_AX_DBG_PORT_SEL, 1735 .rd_byte = 4, 1736 .rd_msk = B_AX_DEBUG_ST_MASK 1737 }; 1738 1739 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 1740 .sel_addr = R_AX_RX_STATE_MONITOR, 1741 .sel_byte = 1, 1742 .sel_msk = B_AX_STATE_SEL_MASK, 1743 .srt = 0x00, 1744 .end = 0x17, 1745 .rd_addr = R_AX_RX_STATE_MONITOR, 1746 .rd_byte = 4, 1747 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 1748 }; 1749 1750 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 1751 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 1752 .sel_byte = 1, 1753 .sel_msk = B_AX_STATE_SEL_MASK, 1754 .srt = 0x00, 1755 .end = 0x17, 1756 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 1757 .rd_byte = 4, 1758 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 1759 }; 1760 1761 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 1762 .sel_addr = R_AX_RMAC_PLCP_MON, 1763 .sel_byte = 4, 1764 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 1765 .srt = 0x0, 1766 .end = 0xF, 1767 .rd_addr = R_AX_RMAC_PLCP_MON, 1768 .rd_byte = 4, 1769 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 1770 }; 1771 1772 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 1773 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 1774 .sel_byte = 4, 1775 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 1776 .srt = 0x0, 1777 .end = 0xF, 1778 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 1779 .rd_byte = 4, 1780 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 1781 }; 1782 1783 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 1784 .sel_addr = R_AX_DBGSEL_TRXPTCL, 1785 .sel_byte = 1, 1786 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 1787 .srt = 0x08, 1788 .end = 0x10, 1789 .rd_addr = R_AX_DBG_PORT_SEL, 1790 .rd_byte = 4, 1791 .rd_msk = B_AX_DEBUG_ST_MASK 1792 }; 1793 1794 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 1795 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 1796 .sel_byte = 1, 1797 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 1798 .srt = 0x08, 1799 .end = 0x10, 1800 .rd_addr = R_AX_DBG_PORT_SEL, 1801 .rd_byte = 4, 1802 .rd_msk = B_AX_DEBUG_ST_MASK 1803 }; 1804 1805 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 1806 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 1807 .sel_byte = 1, 1808 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1809 .srt = 0x00, 1810 .end = 0x07, 1811 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 1812 .rd_byte = 4, 1813 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 1814 }; 1815 1816 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 1817 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 1818 .sel_byte = 1, 1819 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1820 .srt = 0x00, 1821 .end = 0x07, 1822 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 1823 .rd_byte = 4, 1824 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 1825 }; 1826 1827 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 1828 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 1829 .sel_byte = 1, 1830 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1831 .srt = 0x00, 1832 .end = 0x07, 1833 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 1834 .rd_byte = 4, 1835 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 1836 }; 1837 1838 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 1839 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 1840 .sel_byte = 1, 1841 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1842 .srt = 0x00, 1843 .end = 0x07, 1844 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 1845 .rd_byte = 4, 1846 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 1847 }; 1848 1849 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 1850 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 1851 .sel_byte = 1, 1852 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1853 .srt = 0x00, 1854 .end = 0x04, 1855 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 1856 .rd_byte = 4, 1857 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 1858 }; 1859 1860 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 1861 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 1862 .sel_byte = 1, 1863 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1864 .srt = 0x00, 1865 .end = 0x04, 1866 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 1867 .rd_byte = 4, 1868 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 1869 }; 1870 1871 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 1872 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 1873 .sel_byte = 1, 1874 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1875 .srt = 0x00, 1876 .end = 0x04, 1877 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 1878 .rd_byte = 4, 1879 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 1880 }; 1881 1882 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 1883 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 1884 .sel_byte = 1, 1885 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1886 .srt = 0x00, 1887 .end = 0x04, 1888 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 1889 .rd_byte = 4, 1890 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 1891 }; 1892 1893 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 1894 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1895 .sel_byte = 4, 1896 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1897 .srt = 0x80000000, 1898 .end = 0x80000001, 1899 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1900 .rd_byte = 4, 1901 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1902 }; 1903 1904 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 1905 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1906 .sel_byte = 4, 1907 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1908 .srt = 0x80010000, 1909 .end = 0x80010004, 1910 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1911 .rd_byte = 4, 1912 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1913 }; 1914 1915 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 1916 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1917 .sel_byte = 4, 1918 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1919 .srt = 0x80020000, 1920 .end = 0x80020FFF, 1921 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1922 .rd_byte = 4, 1923 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1924 }; 1925 1926 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 1927 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1928 .sel_byte = 4, 1929 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1930 .srt = 0x80030000, 1931 .end = 0x80030FFF, 1932 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1933 .rd_byte = 4, 1934 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1935 }; 1936 1937 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 1938 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1939 .sel_byte = 4, 1940 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1941 .srt = 0x80040000, 1942 .end = 0x80040FFF, 1943 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1944 .rd_byte = 4, 1945 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1946 }; 1947 1948 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 1949 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1950 .sel_byte = 4, 1951 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1952 .srt = 0x80050000, 1953 .end = 0x80050FFF, 1954 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1955 .rd_byte = 4, 1956 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1957 }; 1958 1959 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 1960 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1961 .sel_byte = 4, 1962 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1963 .srt = 0x80060000, 1964 .end = 0x80060453, 1965 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1966 .rd_byte = 4, 1967 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1968 }; 1969 1970 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 1971 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1972 .sel_byte = 4, 1973 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1974 .srt = 0x80070000, 1975 .end = 0x80070011, 1976 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1977 .rd_byte = 4, 1978 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1979 }; 1980 1981 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 1982 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1983 .sel_byte = 4, 1984 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1985 .srt = 0x80000000, 1986 .end = 0x80000001, 1987 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1988 .rd_byte = 4, 1989 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1990 }; 1991 1992 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 1993 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1994 .sel_byte = 4, 1995 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1996 .srt = 0x80010000, 1997 .end = 0x8001000A, 1998 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1999 .rd_byte = 4, 2000 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2001 }; 2002 2003 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 2004 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2005 .sel_byte = 4, 2006 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2007 .srt = 0x80020000, 2008 .end = 0x80020DBF, 2009 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2010 .rd_byte = 4, 2011 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2012 }; 2013 2014 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 2015 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2016 .sel_byte = 4, 2017 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2018 .srt = 0x80030000, 2019 .end = 0x80030DBF, 2020 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2021 .rd_byte = 4, 2022 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2023 }; 2024 2025 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 2026 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2027 .sel_byte = 4, 2028 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2029 .srt = 0x80040000, 2030 .end = 0x80040DBF, 2031 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2032 .rd_byte = 4, 2033 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2034 }; 2035 2036 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 2037 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2038 .sel_byte = 4, 2039 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2040 .srt = 0x80050000, 2041 .end = 0x80050DBF, 2042 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2043 .rd_byte = 4, 2044 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2045 }; 2046 2047 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 2048 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2049 .sel_byte = 4, 2050 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2051 .srt = 0x80060000, 2052 .end = 0x80060041, 2053 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2054 .rd_byte = 4, 2055 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2056 }; 2057 2058 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 2059 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2060 .sel_byte = 4, 2061 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2062 .srt = 0x80070000, 2063 .end = 0x80070001, 2064 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2065 .rd_byte = 4, 2066 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2067 }; 2068 2069 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 2070 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 2071 .sel_byte = 4, 2072 .sel_msk = B_AX_DFI_DATA_MASK, 2073 .srt = 0x80000000, 2074 .end = 0x8000017f, 2075 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 2076 .rd_byte = 4, 2077 .rd_msk = B_AX_DFI_DATA_MASK 2078 }; 2079 2080 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 2081 .sel_addr = R_AX_PCIE_DBG_CTRL, 2082 .sel_byte = 2, 2083 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2084 .srt = 0x00, 2085 .end = 0x03, 2086 .rd_addr = R_AX_DBG_PORT_SEL, 2087 .rd_byte = 4, 2088 .rd_msk = B_AX_DEBUG_ST_MASK 2089 }; 2090 2091 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 2092 .sel_addr = R_AX_PCIE_DBG_CTRL, 2093 .sel_byte = 2, 2094 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2095 .srt = 0x00, 2096 .end = 0x04, 2097 .rd_addr = R_AX_DBG_PORT_SEL, 2098 .rd_byte = 4, 2099 .rd_msk = B_AX_DEBUG_ST_MASK 2100 }; 2101 2102 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 2103 .sel_addr = R_AX_PCIE_DBG_CTRL, 2104 .sel_byte = 2, 2105 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2106 .srt = 0x00, 2107 .end = 0x01, 2108 .rd_addr = R_AX_DBG_PORT_SEL, 2109 .rd_byte = 4, 2110 .rd_msk = B_AX_DEBUG_ST_MASK 2111 }; 2112 2113 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 2114 .sel_addr = R_AX_PCIE_DBG_CTRL, 2115 .sel_byte = 2, 2116 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2117 .srt = 0x00, 2118 .end = 0x05, 2119 .rd_addr = R_AX_DBG_PORT_SEL, 2120 .rd_byte = 4, 2121 .rd_msk = B_AX_DEBUG_ST_MASK 2122 }; 2123 2124 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 2125 .sel_addr = R_AX_PCIE_DBG_CTRL, 2126 .sel_byte = 2, 2127 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2128 .srt = 0x00, 2129 .end = 0x05, 2130 .rd_addr = R_AX_DBG_PORT_SEL, 2131 .rd_byte = 4, 2132 .rd_msk = B_AX_DEBUG_ST_MASK 2133 }; 2134 2135 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 2136 .sel_addr = R_AX_PCIE_DBG_CTRL, 2137 .sel_byte = 2, 2138 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2139 .srt = 0x00, 2140 .end = 0x06, 2141 .rd_addr = R_AX_DBG_PORT_SEL, 2142 .rd_byte = 4, 2143 .rd_msk = B_AX_DEBUG_ST_MASK 2144 }; 2145 2146 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 2147 .sel_addr = R_AX_DBG_CTRL, 2148 .sel_byte = 1, 2149 .sel_msk = B_AX_DBG_SEL0, 2150 .srt = 0x34, 2151 .end = 0x3C, 2152 .rd_addr = R_AX_DBG_PORT_SEL, 2153 .rd_byte = 4, 2154 .rd_msk = B_AX_DEBUG_ST_MASK 2155 }; 2156 2157 static const struct rtw89_mac_dbg_port_info * 2158 rtw89_debug_mac_dbg_port_sel(struct seq_file *m, 2159 struct rtw89_dev *rtwdev, u32 sel) 2160 { 2161 const struct rtw89_mac_dbg_port_info *info; 2162 u32 index; 2163 u32 val32; 2164 u16 val16; 2165 u8 val8; 2166 2167 switch (sel) { 2168 case RTW89_DBG_PORT_SEL_PTCL_C0: 2169 info = &dbg_port_ptcl_c0; 2170 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 2171 val16 |= B_AX_PTCL_DBG_EN; 2172 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 2173 seq_puts(m, "Enable PTCL C0 dbgport.\n"); 2174 break; 2175 case RTW89_DBG_PORT_SEL_PTCL_C1: 2176 info = &dbg_port_ptcl_c1; 2177 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 2178 val16 |= B_AX_PTCL_DBG_EN; 2179 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 2180 seq_puts(m, "Enable PTCL C1 dbgport.\n"); 2181 break; 2182 case RTW89_DBG_PORT_SEL_SCH_C0: 2183 info = &dbg_port_sch_c0; 2184 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 2185 val32 |= B_AX_SCH_DBG_EN; 2186 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 2187 seq_puts(m, "Enable SCH C0 dbgport.\n"); 2188 break; 2189 case RTW89_DBG_PORT_SEL_SCH_C1: 2190 info = &dbg_port_sch_c1; 2191 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 2192 val32 |= B_AX_SCH_DBG_EN; 2193 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 2194 seq_puts(m, "Enable SCH C1 dbgport.\n"); 2195 break; 2196 case RTW89_DBG_PORT_SEL_TMAC_C0: 2197 info = &dbg_port_tmac_c0; 2198 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2199 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2200 B_AX_DBGSEL_TRXPTCL_MASK); 2201 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2202 2203 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2204 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2205 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2206 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2207 2208 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2209 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2210 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2211 seq_puts(m, "Enable TMAC C0 dbgport.\n"); 2212 break; 2213 case RTW89_DBG_PORT_SEL_TMAC_C1: 2214 info = &dbg_port_tmac_c1; 2215 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2216 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2217 B_AX_DBGSEL_TRXPTCL_MASK); 2218 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2219 2220 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2221 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2222 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2223 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2224 2225 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2226 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2227 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2228 seq_puts(m, "Enable TMAC C1 dbgport.\n"); 2229 break; 2230 case RTW89_DBG_PORT_SEL_RMAC_C0: 2231 info = &dbg_port_rmac_c0; 2232 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2233 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2234 B_AX_DBGSEL_TRXPTCL_MASK); 2235 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2236 2237 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2238 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2239 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2240 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2241 2242 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2243 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2244 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2245 2246 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 2247 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2248 B_AX_DBGSEL_TRXPTCL_MASK); 2249 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 2250 seq_puts(m, "Enable RMAC C0 dbgport.\n"); 2251 break; 2252 case RTW89_DBG_PORT_SEL_RMAC_C1: 2253 info = &dbg_port_rmac_c1; 2254 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2255 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2256 B_AX_DBGSEL_TRXPTCL_MASK); 2257 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2258 2259 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2260 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2261 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2262 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2263 2264 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2265 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2266 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2267 2268 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2269 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2270 B_AX_DBGSEL_TRXPTCL_MASK); 2271 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 2272 seq_puts(m, "Enable RMAC C1 dbgport.\n"); 2273 break; 2274 case RTW89_DBG_PORT_SEL_RMACST_C0: 2275 info = &dbg_port_rmacst_c0; 2276 seq_puts(m, "Enable RMAC state C0 dbgport.\n"); 2277 break; 2278 case RTW89_DBG_PORT_SEL_RMACST_C1: 2279 info = &dbg_port_rmacst_c1; 2280 seq_puts(m, "Enable RMAC state C1 dbgport.\n"); 2281 break; 2282 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 2283 info = &dbg_port_rmac_plcp_c0; 2284 seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n"); 2285 break; 2286 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 2287 info = &dbg_port_rmac_plcp_c1; 2288 seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n"); 2289 break; 2290 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 2291 info = &dbg_port_trxptcl_c0; 2292 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2293 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 2294 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 2295 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2296 2297 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2298 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2299 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2300 seq_puts(m, "Enable TRXPTCL C0 dbgport.\n"); 2301 break; 2302 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 2303 info = &dbg_port_trxptcl_c1; 2304 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2305 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 2306 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 2307 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2308 2309 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2310 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2311 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2312 seq_puts(m, "Enable TRXPTCL C1 dbgport.\n"); 2313 break; 2314 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 2315 info = &dbg_port_tx_infol_c0; 2316 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2317 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2318 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2319 seq_puts(m, "Enable tx infol dump.\n"); 2320 break; 2321 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 2322 info = &dbg_port_tx_infoh_c0; 2323 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2324 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2325 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2326 seq_puts(m, "Enable tx infoh dump.\n"); 2327 break; 2328 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 2329 info = &dbg_port_tx_infol_c1; 2330 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2331 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2332 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2333 seq_puts(m, "Enable tx infol dump.\n"); 2334 break; 2335 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 2336 info = &dbg_port_tx_infoh_c1; 2337 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2338 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2339 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2340 seq_puts(m, "Enable tx infoh dump.\n"); 2341 break; 2342 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 2343 info = &dbg_port_txtf_infol_c0; 2344 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2345 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2346 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2347 seq_puts(m, "Enable tx tf infol dump.\n"); 2348 break; 2349 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 2350 info = &dbg_port_txtf_infoh_c0; 2351 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2352 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2353 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2354 seq_puts(m, "Enable tx tf infoh dump.\n"); 2355 break; 2356 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 2357 info = &dbg_port_txtf_infol_c1; 2358 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2359 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2360 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2361 seq_puts(m, "Enable tx tf infol dump.\n"); 2362 break; 2363 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 2364 info = &dbg_port_txtf_infoh_c1; 2365 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2366 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2367 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2368 seq_puts(m, "Enable tx tf infoh dump.\n"); 2369 break; 2370 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 2371 info = &dbg_port_wde_bufmgn_freepg; 2372 seq_puts(m, "Enable wde bufmgn freepg dump.\n"); 2373 break; 2374 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 2375 info = &dbg_port_wde_bufmgn_quota; 2376 seq_puts(m, "Enable wde bufmgn quota dump.\n"); 2377 break; 2378 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 2379 info = &dbg_port_wde_bufmgn_pagellt; 2380 seq_puts(m, "Enable wde bufmgn pagellt dump.\n"); 2381 break; 2382 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 2383 info = &dbg_port_wde_bufmgn_pktinfo; 2384 seq_puts(m, "Enable wde bufmgn pktinfo dump.\n"); 2385 break; 2386 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 2387 info = &dbg_port_wde_quemgn_prepkt; 2388 seq_puts(m, "Enable wde quemgn prepkt dump.\n"); 2389 break; 2390 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 2391 info = &dbg_port_wde_quemgn_nxtpkt; 2392 seq_puts(m, "Enable wde quemgn nxtpkt dump.\n"); 2393 break; 2394 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 2395 info = &dbg_port_wde_quemgn_qlnktbl; 2396 seq_puts(m, "Enable wde quemgn qlnktbl dump.\n"); 2397 break; 2398 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 2399 info = &dbg_port_wde_quemgn_qempty; 2400 seq_puts(m, "Enable wde quemgn qempty dump.\n"); 2401 break; 2402 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 2403 info = &dbg_port_ple_bufmgn_freepg; 2404 seq_puts(m, "Enable ple bufmgn freepg dump.\n"); 2405 break; 2406 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 2407 info = &dbg_port_ple_bufmgn_quota; 2408 seq_puts(m, "Enable ple bufmgn quota dump.\n"); 2409 break; 2410 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 2411 info = &dbg_port_ple_bufmgn_pagellt; 2412 seq_puts(m, "Enable ple bufmgn pagellt dump.\n"); 2413 break; 2414 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 2415 info = &dbg_port_ple_bufmgn_pktinfo; 2416 seq_puts(m, "Enable ple bufmgn pktinfo dump.\n"); 2417 break; 2418 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 2419 info = &dbg_port_ple_quemgn_prepkt; 2420 seq_puts(m, "Enable ple quemgn prepkt dump.\n"); 2421 break; 2422 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 2423 info = &dbg_port_ple_quemgn_nxtpkt; 2424 seq_puts(m, "Enable ple quemgn nxtpkt dump.\n"); 2425 break; 2426 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 2427 info = &dbg_port_ple_quemgn_qlnktbl; 2428 seq_puts(m, "Enable ple quemgn qlnktbl dump.\n"); 2429 break; 2430 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 2431 info = &dbg_port_ple_quemgn_qempty; 2432 seq_puts(m, "Enable ple quemgn qempty dump.\n"); 2433 break; 2434 case RTW89_DBG_PORT_SEL_PKTINFO: 2435 info = &dbg_port_pktinfo; 2436 seq_puts(m, "Enable pktinfo dump.\n"); 2437 break; 2438 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX0: 2439 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 2440 B_AX_DBG_SEL0, 0x80); 2441 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 2442 B_AX_SEL_0XC0_MASK, 1); 2443 fallthrough; 2444 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX1: 2445 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX2: 2446 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX3: 2447 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX4: 2448 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX5: 2449 info = &dbg_port_dspt_hdt_tx0_5; 2450 index = sel - RTW89_DBG_PORT_SEL_DSPT_HDT_TX0; 2451 rtw89_write16_mask(rtwdev, info->sel_addr, 2452 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2453 rtw89_write16_mask(rtwdev, info->sel_addr, 2454 B_AX_DISPATCHER_CH_SEL_MASK, index); 2455 seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index); 2456 break; 2457 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX6: 2458 info = &dbg_port_dspt_hdt_tx6; 2459 rtw89_write16_mask(rtwdev, info->sel_addr, 2460 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2461 rtw89_write16_mask(rtwdev, info->sel_addr, 2462 B_AX_DISPATCHER_CH_SEL_MASK, 6); 2463 seq_puts(m, "Enable Dispatcher hdt tx6 dump.\n"); 2464 break; 2465 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX7: 2466 info = &dbg_port_dspt_hdt_tx7; 2467 rtw89_write16_mask(rtwdev, info->sel_addr, 2468 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2469 rtw89_write16_mask(rtwdev, info->sel_addr, 2470 B_AX_DISPATCHER_CH_SEL_MASK, 7); 2471 seq_puts(m, "Enable Dispatcher hdt tx7 dump.\n"); 2472 break; 2473 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX8: 2474 info = &dbg_port_dspt_hdt_tx8; 2475 rtw89_write16_mask(rtwdev, info->sel_addr, 2476 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2477 rtw89_write16_mask(rtwdev, info->sel_addr, 2478 B_AX_DISPATCHER_CH_SEL_MASK, 8); 2479 seq_puts(m, "Enable Dispatcher hdt tx8 dump.\n"); 2480 break; 2481 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX9: 2482 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXA: 2483 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXB: 2484 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXC: 2485 info = &dbg_port_dspt_hdt_tx9_C; 2486 index = sel + 9 - RTW89_DBG_PORT_SEL_DSPT_HDT_TX9; 2487 rtw89_write16_mask(rtwdev, info->sel_addr, 2488 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2489 rtw89_write16_mask(rtwdev, info->sel_addr, 2490 B_AX_DISPATCHER_CH_SEL_MASK, index); 2491 seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index); 2492 break; 2493 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXD: 2494 info = &dbg_port_dspt_hdt_txD; 2495 rtw89_write16_mask(rtwdev, info->sel_addr, 2496 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2497 rtw89_write16_mask(rtwdev, info->sel_addr, 2498 B_AX_DISPATCHER_CH_SEL_MASK, 0xD); 2499 seq_puts(m, "Enable Dispatcher hdt txD dump.\n"); 2500 break; 2501 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX0: 2502 info = &dbg_port_dspt_cdt_tx0; 2503 rtw89_write16_mask(rtwdev, info->sel_addr, 2504 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2505 rtw89_write16_mask(rtwdev, info->sel_addr, 2506 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2507 seq_puts(m, "Enable Dispatcher cdt tx0 dump.\n"); 2508 break; 2509 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX1: 2510 info = &dbg_port_dspt_cdt_tx1; 2511 rtw89_write16_mask(rtwdev, info->sel_addr, 2512 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2513 rtw89_write16_mask(rtwdev, info->sel_addr, 2514 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2515 seq_puts(m, "Enable Dispatcher cdt tx1 dump.\n"); 2516 break; 2517 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX3: 2518 info = &dbg_port_dspt_cdt_tx3; 2519 rtw89_write16_mask(rtwdev, info->sel_addr, 2520 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2521 rtw89_write16_mask(rtwdev, info->sel_addr, 2522 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2523 seq_puts(m, "Enable Dispatcher cdt tx3 dump.\n"); 2524 break; 2525 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX4: 2526 info = &dbg_port_dspt_cdt_tx4; 2527 rtw89_write16_mask(rtwdev, info->sel_addr, 2528 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2529 rtw89_write16_mask(rtwdev, info->sel_addr, 2530 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2531 seq_puts(m, "Enable Dispatcher cdt tx4 dump.\n"); 2532 break; 2533 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX5: 2534 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX6: 2535 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX7: 2536 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX8: 2537 info = &dbg_port_dspt_cdt_tx5_8; 2538 index = sel + 5 - RTW89_DBG_PORT_SEL_DSPT_CDT_TX5; 2539 rtw89_write16_mask(rtwdev, info->sel_addr, 2540 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2541 rtw89_write16_mask(rtwdev, info->sel_addr, 2542 B_AX_DISPATCHER_CH_SEL_MASK, index); 2543 seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index); 2544 break; 2545 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX9: 2546 info = &dbg_port_dspt_cdt_tx9; 2547 rtw89_write16_mask(rtwdev, info->sel_addr, 2548 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2549 rtw89_write16_mask(rtwdev, info->sel_addr, 2550 B_AX_DISPATCHER_CH_SEL_MASK, 9); 2551 seq_puts(m, "Enable Dispatcher cdt tx9 dump.\n"); 2552 break; 2553 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXA: 2554 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXB: 2555 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXC: 2556 info = &dbg_port_dspt_cdt_txA_C; 2557 index = sel + 0xA - RTW89_DBG_PORT_SEL_DSPT_CDT_TXA; 2558 rtw89_write16_mask(rtwdev, info->sel_addr, 2559 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2560 rtw89_write16_mask(rtwdev, info->sel_addr, 2561 B_AX_DISPATCHER_CH_SEL_MASK, index); 2562 seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index); 2563 break; 2564 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX0: 2565 info = &dbg_port_dspt_hdt_rx0; 2566 rtw89_write16_mask(rtwdev, info->sel_addr, 2567 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2568 rtw89_write16_mask(rtwdev, info->sel_addr, 2569 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2570 seq_puts(m, "Enable Dispatcher hdt rx0 dump.\n"); 2571 break; 2572 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX1: 2573 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX2: 2574 info = &dbg_port_dspt_hdt_rx1_2; 2575 index = sel + 1 - RTW89_DBG_PORT_SEL_DSPT_HDT_RX1; 2576 rtw89_write16_mask(rtwdev, info->sel_addr, 2577 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2578 rtw89_write16_mask(rtwdev, info->sel_addr, 2579 B_AX_DISPATCHER_CH_SEL_MASK, index); 2580 seq_printf(m, "Enable Dispatcher hdt rx%x dump.\n", index); 2581 break; 2582 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX3: 2583 info = &dbg_port_dspt_hdt_rx3; 2584 rtw89_write16_mask(rtwdev, info->sel_addr, 2585 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2586 rtw89_write16_mask(rtwdev, info->sel_addr, 2587 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2588 seq_puts(m, "Enable Dispatcher hdt rx3 dump.\n"); 2589 break; 2590 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX4: 2591 info = &dbg_port_dspt_hdt_rx4; 2592 rtw89_write16_mask(rtwdev, info->sel_addr, 2593 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2594 rtw89_write16_mask(rtwdev, info->sel_addr, 2595 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2596 seq_puts(m, "Enable Dispatcher hdt rx4 dump.\n"); 2597 break; 2598 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX5: 2599 info = &dbg_port_dspt_hdt_rx5; 2600 rtw89_write16_mask(rtwdev, info->sel_addr, 2601 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2602 rtw89_write16_mask(rtwdev, info->sel_addr, 2603 B_AX_DISPATCHER_CH_SEL_MASK, 5); 2604 seq_puts(m, "Enable Dispatcher hdt rx5 dump.\n"); 2605 break; 2606 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0: 2607 info = &dbg_port_dspt_cdt_rx_p0_0; 2608 rtw89_write16_mask(rtwdev, info->sel_addr, 2609 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2610 rtw89_write16_mask(rtwdev, info->sel_addr, 2611 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2612 seq_puts(m, "Enable Dispatcher cdt rx part0 0 dump.\n"); 2613 break; 2614 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0: 2615 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1: 2616 info = &dbg_port_dspt_cdt_rx_p0_1; 2617 rtw89_write16_mask(rtwdev, info->sel_addr, 2618 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2619 rtw89_write16_mask(rtwdev, info->sel_addr, 2620 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2621 seq_puts(m, "Enable Dispatcher cdt rx part0 1 dump.\n"); 2622 break; 2623 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2: 2624 info = &dbg_port_dspt_cdt_rx_p0_2; 2625 rtw89_write16_mask(rtwdev, info->sel_addr, 2626 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2627 rtw89_write16_mask(rtwdev, info->sel_addr, 2628 B_AX_DISPATCHER_CH_SEL_MASK, 2); 2629 seq_puts(m, "Enable Dispatcher cdt rx part0 2 dump.\n"); 2630 break; 2631 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1: 2632 info = &dbg_port_dspt_cdt_rx_p1; 2633 rtw89_write8_mask(rtwdev, info->sel_addr, 2634 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2635 seq_puts(m, "Enable Dispatcher cdt rx part1 dump.\n"); 2636 break; 2637 case RTW89_DBG_PORT_SEL_DSPT_STF_CTRL: 2638 info = &dbg_port_dspt_stf_ctrl; 2639 rtw89_write8_mask(rtwdev, info->sel_addr, 2640 B_AX_DISPATCHER_INTN_SEL_MASK, 4); 2641 seq_puts(m, "Enable Dispatcher stf control dump.\n"); 2642 break; 2643 case RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL: 2644 info = &dbg_port_dspt_addr_ctrl; 2645 rtw89_write8_mask(rtwdev, info->sel_addr, 2646 B_AX_DISPATCHER_INTN_SEL_MASK, 5); 2647 seq_puts(m, "Enable Dispatcher addr control dump.\n"); 2648 break; 2649 case RTW89_DBG_PORT_SEL_DSPT_WDE_INTF: 2650 info = &dbg_port_dspt_wde_intf; 2651 rtw89_write8_mask(rtwdev, info->sel_addr, 2652 B_AX_DISPATCHER_INTN_SEL_MASK, 6); 2653 seq_puts(m, "Enable Dispatcher wde interface dump.\n"); 2654 break; 2655 case RTW89_DBG_PORT_SEL_DSPT_PLE_INTF: 2656 info = &dbg_port_dspt_ple_intf; 2657 rtw89_write8_mask(rtwdev, info->sel_addr, 2658 B_AX_DISPATCHER_INTN_SEL_MASK, 7); 2659 seq_puts(m, "Enable Dispatcher ple interface dump.\n"); 2660 break; 2661 case RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL: 2662 info = &dbg_port_dspt_flow_ctrl; 2663 rtw89_write8_mask(rtwdev, info->sel_addr, 2664 B_AX_DISPATCHER_INTN_SEL_MASK, 8); 2665 seq_puts(m, "Enable Dispatcher flow control dump.\n"); 2666 break; 2667 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 2668 info = &dbg_port_pcie_txdma; 2669 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2670 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 2671 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 2672 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2673 seq_puts(m, "Enable pcie txdma dump.\n"); 2674 break; 2675 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 2676 info = &dbg_port_pcie_rxdma; 2677 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2678 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 2679 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 2680 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2681 seq_puts(m, "Enable pcie rxdma dump.\n"); 2682 break; 2683 case RTW89_DBG_PORT_SEL_PCIE_CVT: 2684 info = &dbg_port_pcie_cvt; 2685 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2686 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 2687 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 2688 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2689 seq_puts(m, "Enable pcie cvt dump.\n"); 2690 break; 2691 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 2692 info = &dbg_port_pcie_cxpl; 2693 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2694 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 2695 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 2696 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2697 seq_puts(m, "Enable pcie cxpl dump.\n"); 2698 break; 2699 case RTW89_DBG_PORT_SEL_PCIE_IO: 2700 info = &dbg_port_pcie_io; 2701 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2702 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 2703 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 2704 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2705 seq_puts(m, "Enable pcie io dump.\n"); 2706 break; 2707 case RTW89_DBG_PORT_SEL_PCIE_MISC: 2708 info = &dbg_port_pcie_misc; 2709 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2710 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 2711 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 2712 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2713 seq_puts(m, "Enable pcie misc dump.\n"); 2714 break; 2715 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 2716 info = &dbg_port_pcie_misc2; 2717 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 2718 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 2719 B_AX_PCIE_DBG_SEL_MASK); 2720 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 2721 seq_puts(m, "Enable pcie misc2 dump.\n"); 2722 break; 2723 default: 2724 seq_puts(m, "Dbg port select err\n"); 2725 return NULL; 2726 } 2727 2728 return info; 2729 } 2730 2731 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 2732 { 2733 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 2734 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 2735 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 2736 return false; 2737 if (rtwdev->chip->chip_id == RTL8852B && 2738 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 2739 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 2740 return false; 2741 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 2742 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 2743 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 2744 return false; 2745 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 2746 sel >= RTW89_DBG_PORT_SEL_DSPT_HDT_TX0 && 2747 sel <= RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL) 2748 return false; 2749 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 2750 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 2751 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 2752 return false; 2753 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 2754 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 2755 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 2756 return false; 2757 2758 return true; 2759 } 2760 2761 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 2762 struct seq_file *m, u32 sel) 2763 { 2764 const struct rtw89_mac_dbg_port_info *info; 2765 u8 val8; 2766 u16 val16; 2767 u32 val32; 2768 u32 i; 2769 2770 info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel); 2771 if (!info) { 2772 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 2773 return -EINVAL; 2774 } 2775 2776 #define case_DBG_SEL(__sel) \ 2777 case RTW89_DBG_PORT_SEL_##__sel: \ 2778 seq_puts(m, "Dump debug port " #__sel ":\n"); \ 2779 break 2780 2781 switch (sel) { 2782 case_DBG_SEL(PTCL_C0); 2783 case_DBG_SEL(PTCL_C1); 2784 case_DBG_SEL(SCH_C0); 2785 case_DBG_SEL(SCH_C1); 2786 case_DBG_SEL(TMAC_C0); 2787 case_DBG_SEL(TMAC_C1); 2788 case_DBG_SEL(RMAC_C0); 2789 case_DBG_SEL(RMAC_C1); 2790 case_DBG_SEL(RMACST_C0); 2791 case_DBG_SEL(RMACST_C1); 2792 case_DBG_SEL(TRXPTCL_C0); 2793 case_DBG_SEL(TRXPTCL_C1); 2794 case_DBG_SEL(TX_INFOL_C0); 2795 case_DBG_SEL(TX_INFOH_C0); 2796 case_DBG_SEL(TX_INFOL_C1); 2797 case_DBG_SEL(TX_INFOH_C1); 2798 case_DBG_SEL(TXTF_INFOL_C0); 2799 case_DBG_SEL(TXTF_INFOH_C0); 2800 case_DBG_SEL(TXTF_INFOL_C1); 2801 case_DBG_SEL(TXTF_INFOH_C1); 2802 case_DBG_SEL(WDE_BUFMGN_FREEPG); 2803 case_DBG_SEL(WDE_BUFMGN_QUOTA); 2804 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 2805 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 2806 case_DBG_SEL(WDE_QUEMGN_PREPKT); 2807 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 2808 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 2809 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 2810 case_DBG_SEL(PLE_BUFMGN_FREEPG); 2811 case_DBG_SEL(PLE_BUFMGN_QUOTA); 2812 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 2813 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 2814 case_DBG_SEL(PLE_QUEMGN_PREPKT); 2815 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 2816 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 2817 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 2818 case_DBG_SEL(PKTINFO); 2819 case_DBG_SEL(DSPT_HDT_TX0); 2820 case_DBG_SEL(DSPT_HDT_TX1); 2821 case_DBG_SEL(DSPT_HDT_TX2); 2822 case_DBG_SEL(DSPT_HDT_TX3); 2823 case_DBG_SEL(DSPT_HDT_TX4); 2824 case_DBG_SEL(DSPT_HDT_TX5); 2825 case_DBG_SEL(DSPT_HDT_TX6); 2826 case_DBG_SEL(DSPT_HDT_TX7); 2827 case_DBG_SEL(DSPT_HDT_TX8); 2828 case_DBG_SEL(DSPT_HDT_TX9); 2829 case_DBG_SEL(DSPT_HDT_TXA); 2830 case_DBG_SEL(DSPT_HDT_TXB); 2831 case_DBG_SEL(DSPT_HDT_TXC); 2832 case_DBG_SEL(DSPT_HDT_TXD); 2833 case_DBG_SEL(DSPT_HDT_TXE); 2834 case_DBG_SEL(DSPT_HDT_TXF); 2835 case_DBG_SEL(DSPT_CDT_TX0); 2836 case_DBG_SEL(DSPT_CDT_TX1); 2837 case_DBG_SEL(DSPT_CDT_TX3); 2838 case_DBG_SEL(DSPT_CDT_TX4); 2839 case_DBG_SEL(DSPT_CDT_TX5); 2840 case_DBG_SEL(DSPT_CDT_TX6); 2841 case_DBG_SEL(DSPT_CDT_TX7); 2842 case_DBG_SEL(DSPT_CDT_TX8); 2843 case_DBG_SEL(DSPT_CDT_TX9); 2844 case_DBG_SEL(DSPT_CDT_TXA); 2845 case_DBG_SEL(DSPT_CDT_TXB); 2846 case_DBG_SEL(DSPT_CDT_TXC); 2847 case_DBG_SEL(DSPT_HDT_RX0); 2848 case_DBG_SEL(DSPT_HDT_RX1); 2849 case_DBG_SEL(DSPT_HDT_RX2); 2850 case_DBG_SEL(DSPT_HDT_RX3); 2851 case_DBG_SEL(DSPT_HDT_RX4); 2852 case_DBG_SEL(DSPT_HDT_RX5); 2853 case_DBG_SEL(DSPT_CDT_RX_P0); 2854 case_DBG_SEL(DSPT_CDT_RX_P0_0); 2855 case_DBG_SEL(DSPT_CDT_RX_P0_1); 2856 case_DBG_SEL(DSPT_CDT_RX_P0_2); 2857 case_DBG_SEL(DSPT_CDT_RX_P1); 2858 case_DBG_SEL(DSPT_STF_CTRL); 2859 case_DBG_SEL(DSPT_ADDR_CTRL); 2860 case_DBG_SEL(DSPT_WDE_INTF); 2861 case_DBG_SEL(DSPT_PLE_INTF); 2862 case_DBG_SEL(DSPT_FLOW_CTRL); 2863 case_DBG_SEL(PCIE_TXDMA); 2864 case_DBG_SEL(PCIE_RXDMA); 2865 case_DBG_SEL(PCIE_CVT); 2866 case_DBG_SEL(PCIE_CXPL); 2867 case_DBG_SEL(PCIE_IO); 2868 case_DBG_SEL(PCIE_MISC); 2869 case_DBG_SEL(PCIE_MISC2); 2870 } 2871 2872 #undef case_DBG_SEL 2873 2874 seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr); 2875 seq_printf(m, "Read addr = 0x%X\n", info->rd_addr); 2876 2877 for (i = info->srt; i <= info->end; i++) { 2878 switch (info->sel_byte) { 2879 case 1: 2880 default: 2881 rtw89_write8_mask(rtwdev, info->sel_addr, 2882 info->sel_msk, i); 2883 seq_printf(m, "0x%02X: ", i); 2884 break; 2885 case 2: 2886 rtw89_write16_mask(rtwdev, info->sel_addr, 2887 info->sel_msk, i); 2888 seq_printf(m, "0x%04X: ", i); 2889 break; 2890 case 4: 2891 rtw89_write32_mask(rtwdev, info->sel_addr, 2892 info->sel_msk, i); 2893 seq_printf(m, "0x%04X: ", i); 2894 break; 2895 } 2896 2897 udelay(10); 2898 2899 switch (info->rd_byte) { 2900 case 1: 2901 default: 2902 val8 = rtw89_read8_mask(rtwdev, 2903 info->rd_addr, info->rd_msk); 2904 seq_printf(m, "0x%02X\n", val8); 2905 break; 2906 case 2: 2907 val16 = rtw89_read16_mask(rtwdev, 2908 info->rd_addr, info->rd_msk); 2909 seq_printf(m, "0x%04X\n", val16); 2910 break; 2911 case 4: 2912 val32 = rtw89_read32_mask(rtwdev, 2913 info->rd_addr, info->rd_msk); 2914 seq_printf(m, "0x%08X\n", val32); 2915 break; 2916 } 2917 } 2918 2919 return 0; 2920 } 2921 2922 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 2923 struct seq_file *m) 2924 { 2925 u32 sel; 2926 int ret = 0; 2927 2928 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 2929 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 2930 if (!is_dbg_port_valid(rtwdev, sel)) 2931 continue; 2932 ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel); 2933 if (ret) { 2934 rtw89_err(rtwdev, 2935 "failed to dump debug port %d\n", sel); 2936 break; 2937 } 2938 } 2939 2940 return ret; 2941 } 2942 2943 static int 2944 rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v) 2945 { 2946 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2947 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2948 2949 if (debugfs_priv->dbgpkg_en.ss_dbg) 2950 rtw89_debug_mac_dump_ss_dbg(rtwdev, m); 2951 if (debugfs_priv->dbgpkg_en.dle_dbg) 2952 rtw89_debug_mac_dump_dle_dbg(rtwdev, m); 2953 if (debugfs_priv->dbgpkg_en.dmac_dbg) 2954 rtw89_debug_mac_dump_dmac_dbg(rtwdev, m); 2955 if (debugfs_priv->dbgpkg_en.cmac_dbg) 2956 rtw89_debug_mac_dump_cmac_dbg(rtwdev, m); 2957 if (debugfs_priv->dbgpkg_en.dbg_port) 2958 rtw89_debug_mac_dump_dbg_port(rtwdev, m); 2959 2960 return 0; 2961 }; 2962 2963 static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev, 2964 const char __user *user_buf, size_t count) 2965 { 2966 char *buf; 2967 u8 *bin; 2968 int num; 2969 int err = 0; 2970 2971 buf = memdup_user(user_buf, count); 2972 if (IS_ERR(buf)) 2973 return buf; 2974 2975 num = count / 2; 2976 bin = kmalloc(num, GFP_KERNEL); 2977 if (!bin) { 2978 err = -EFAULT; 2979 goto out; 2980 } 2981 2982 if (hex2bin(bin, buf, num)) { 2983 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 2984 kfree(bin); 2985 err = -EINVAL; 2986 } 2987 2988 out: 2989 kfree(buf); 2990 2991 return err ? ERR_PTR(err) : bin; 2992 } 2993 2994 static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp, 2995 const char __user *user_buf, 2996 size_t count, loff_t *loff) 2997 { 2998 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 2999 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3000 u8 *h2c; 3001 u16 h2c_len = count / 2; 3002 3003 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 3004 if (IS_ERR(h2c)) 3005 return -EFAULT; 3006 3007 rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 3008 3009 kfree(h2c); 3010 3011 return count; 3012 } 3013 3014 static int 3015 rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v) 3016 { 3017 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3018 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3019 struct rtw89_early_h2c *early_h2c; 3020 int seq = 0; 3021 3022 mutex_lock(&rtwdev->mutex); 3023 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 3024 seq_printf(m, "%d: %*ph\n", ++seq, early_h2c->h2c_len, early_h2c->h2c); 3025 mutex_unlock(&rtwdev->mutex); 3026 3027 return 0; 3028 } 3029 3030 static ssize_t 3031 rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf, 3032 size_t count, loff_t *loff) 3033 { 3034 struct seq_file *m = (struct seq_file *)filp->private_data; 3035 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3036 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3037 struct rtw89_early_h2c *early_h2c; 3038 u8 *h2c; 3039 u16 h2c_len = count / 2; 3040 3041 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 3042 if (IS_ERR(h2c)) 3043 return -EFAULT; 3044 3045 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 3046 kfree(h2c); 3047 rtw89_fw_free_all_early_h2c(rtwdev); 3048 goto out; 3049 } 3050 3051 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL); 3052 if (!early_h2c) { 3053 kfree(h2c); 3054 return -EFAULT; 3055 } 3056 3057 early_h2c->h2c = h2c; 3058 early_h2c->h2c_len = h2c_len; 3059 3060 mutex_lock(&rtwdev->mutex); 3061 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 3062 mutex_unlock(&rtwdev->mutex); 3063 3064 out: 3065 return count; 3066 } 3067 3068 static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev) 3069 { 3070 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3071 u16 pkt_id; 3072 int ret; 3073 3074 rtw89_leave_ps_mode(rtwdev); 3075 3076 ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3077 if (ret) 3078 return ret; 3079 3080 /* intentionally, enqueue two pkt, but has only one pkt id */ 3081 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3082 ctrl_para.start_pktid = pkt_id; 3083 ctrl_para.end_pktid = pkt_id; 3084 ctrl_para.pkt_num = 1; /* start from 0 */ 3085 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3086 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3087 3088 if (rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true)) 3089 return -EFAULT; 3090 3091 return 0; 3092 } 3093 3094 static int 3095 rtw89_debug_priv_fw_crash_get(struct seq_file *m, void *v) 3096 { 3097 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3098 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3099 3100 seq_printf(m, "%d\n", 3101 test_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags)); 3102 return 0; 3103 } 3104 3105 enum rtw89_dbg_crash_simulation_type { 3106 RTW89_DBG_SIM_CPU_EXCEPTION = 1, 3107 RTW89_DBG_SIM_CTRL_ERROR = 2, 3108 }; 3109 3110 static ssize_t 3111 rtw89_debug_priv_fw_crash_set(struct file *filp, const char __user *user_buf, 3112 size_t count, loff_t *loff) 3113 { 3114 struct seq_file *m = (struct seq_file *)filp->private_data; 3115 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3116 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3117 int (*sim)(struct rtw89_dev *rtwdev); 3118 u8 crash_type; 3119 int ret; 3120 3121 ret = kstrtou8_from_user(user_buf, count, 0, &crash_type); 3122 if (ret) 3123 return -EINVAL; 3124 3125 switch (crash_type) { 3126 case RTW89_DBG_SIM_CPU_EXCEPTION: 3127 if (!RTW89_CHK_FW_FEATURE(CRASH_TRIGGER, &rtwdev->fw)) 3128 return -EOPNOTSUPP; 3129 sim = rtw89_fw_h2c_trigger_cpu_exception; 3130 break; 3131 case RTW89_DBG_SIM_CTRL_ERROR: 3132 sim = rtw89_dbg_trigger_ctrl_error; 3133 break; 3134 default: 3135 return -EINVAL; 3136 } 3137 3138 mutex_lock(&rtwdev->mutex); 3139 set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags); 3140 ret = sim(rtwdev); 3141 mutex_unlock(&rtwdev->mutex); 3142 3143 if (ret) 3144 return ret; 3145 3146 return count; 3147 } 3148 3149 static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v) 3150 { 3151 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3152 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3153 3154 rtw89_btc_dump_info(rtwdev, m); 3155 3156 return 0; 3157 } 3158 3159 static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp, 3160 const char __user *user_buf, 3161 size_t count, loff_t *loff) 3162 { 3163 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3164 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3165 struct rtw89_btc *btc = &rtwdev->btc; 3166 bool btc_manual; 3167 3168 if (kstrtobool_from_user(user_buf, count, &btc_manual)) 3169 goto out; 3170 3171 btc->ctrl.manual = btc_manual; 3172 out: 3173 return count; 3174 } 3175 3176 static ssize_t rtw89_debug_fw_log_btc_manual_set(struct file *filp, 3177 const char __user *user_buf, 3178 size_t count, loff_t *loff) 3179 { 3180 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3181 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3182 struct rtw89_fw_info *fw_info = &rtwdev->fw; 3183 bool fw_log_manual; 3184 3185 if (kstrtobool_from_user(user_buf, count, &fw_log_manual)) 3186 goto out; 3187 3188 mutex_lock(&rtwdev->mutex); 3189 fw_info->fw_log_enable = fw_log_manual; 3190 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 3191 mutex_unlock(&rtwdev->mutex); 3192 out: 3193 return count; 3194 } 3195 3196 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 3197 { 3198 static const char * const he_gi_str[] = { 3199 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 3200 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 3201 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 3202 }; 3203 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3204 struct rate_info *rate = &rtwsta->ra_report.txrate; 3205 struct ieee80211_rx_status *status = &rtwsta->rx_status; 3206 struct seq_file *m = (struct seq_file *)data; 3207 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3208 struct rtw89_hal *hal = &rtwdev->hal; 3209 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3210 bool ant_asterisk = hal->tx_path_diversity || hal->ant_diversity; 3211 u8 evm_min, evm_max; 3212 u8 rssi; 3213 u8 snr; 3214 int i; 3215 3216 seq_printf(m, "TX rate [%d]: ", rtwsta->mac_id); 3217 3218 if (rate->flags & RATE_INFO_FLAGS_MCS) 3219 seq_printf(m, "HT MCS-%d%s", rate->mcs, 3220 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3221 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 3222 seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs, 3223 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3224 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 3225 seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs, 3226 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3227 he_gi_str[rate->he_gi] : "N/A"); 3228 else 3229 seq_printf(m, "Legacy %d", rate->legacy); 3230 seq_printf(m, "%s", rtwsta->ra_report.might_fallback_legacy ? " FB_G" : ""); 3231 seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(rate->bw)); 3232 seq_printf(m, "\t(hw_rate=0x%x)", rtwsta->ra_report.hw_rate); 3233 seq_printf(m, "\t==> agg_wait=%d (%d)\n", rtwsta->max_agg_wait, 3234 sta->deflink.agg.max_rc_amsdu_len); 3235 3236 seq_printf(m, "RX rate [%d]: ", rtwsta->mac_id); 3237 3238 switch (status->encoding) { 3239 case RX_ENC_LEGACY: 3240 seq_printf(m, "Legacy %d", status->rate_idx + 3241 (status->band != NL80211_BAND_2GHZ ? 4 : 0)); 3242 break; 3243 case RX_ENC_HT: 3244 seq_printf(m, "HT MCS-%d%s", status->rate_idx, 3245 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3246 break; 3247 case RX_ENC_VHT: 3248 seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx, 3249 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3250 break; 3251 case RX_ENC_HE: 3252 seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx, 3253 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3254 he_gi_str[rate->he_gi] : "N/A"); 3255 break; 3256 } 3257 seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(status->bw)); 3258 seq_printf(m, "\t(hw_rate=0x%x)\n", rtwsta->rx_hw_rate); 3259 3260 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 3261 seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d) [", 3262 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta->prev_rssi); 3263 for (i = 0; i < ant_num; i++) { 3264 rssi = ewma_rssi_read(&rtwsta->rssi[i]); 3265 seq_printf(m, "%d%s%s", RTW89_RSSI_RAW_TO_DBM(rssi), 3266 ant_asterisk && (hal->antenna_tx & BIT(i)) ? "*" : "", 3267 i + 1 == ant_num ? "" : ", "); 3268 } 3269 seq_puts(m, "]\n"); 3270 3271 seq_puts(m, "EVM: ["); 3272 for (i = 0; i < (hal->ant_diversity ? 2 : 1); i++) { 3273 evm_min = ewma_evm_read(&rtwsta->evm_min[i]); 3274 evm_max = ewma_evm_read(&rtwsta->evm_max[i]); 3275 3276 seq_printf(m, "%s(%2u.%02u, %2u.%02u)", i == 0 ? "" : " ", 3277 evm_min >> 2, (evm_min & 0x3) * 25, 3278 evm_max >> 2, (evm_max & 0x3) * 25); 3279 } 3280 seq_puts(m, "]\t"); 3281 3282 snr = ewma_snr_read(&rtwsta->avg_snr); 3283 seq_printf(m, "SNR: %u\n", snr); 3284 } 3285 3286 static void 3287 rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat, 3288 enum rtw89_hw_rate first_rate, int len) 3289 { 3290 int i; 3291 3292 for (i = 0; i < len; i++) 3293 seq_printf(m, "%s%u", i == 0 ? "" : ", ", 3294 pkt_stat->rx_rate_cnt[first_rate + i]); 3295 } 3296 3297 static const struct rtw89_rx_rate_cnt_info { 3298 enum rtw89_hw_rate first_rate; 3299 int len; 3300 int ext; 3301 const char *rate_mode; 3302 } rtw89_rx_rate_cnt_infos[] = { 3303 {RTW89_HW_RATE_CCK1, 4, 0, "Legacy:"}, 3304 {RTW89_HW_RATE_OFDM6, 8, 0, "OFDM:"}, 3305 {RTW89_HW_RATE_MCS0, 8, 0, "HT 0:"}, 3306 {RTW89_HW_RATE_MCS8, 8, 0, "HT 1:"}, 3307 {RTW89_HW_RATE_VHT_NSS1_MCS0, 10, 2, "VHT 1SS:"}, 3308 {RTW89_HW_RATE_VHT_NSS2_MCS0, 10, 2, "VHT 2SS:"}, 3309 {RTW89_HW_RATE_HE_NSS1_MCS0, 12, 0, "HE 1SS:"}, 3310 {RTW89_HW_RATE_HE_NSS2_MCS0, 12, 0, "HE 2ss:"}, 3311 }; 3312 3313 static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v) 3314 { 3315 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3316 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3317 struct rtw89_traffic_stats *stats = &rtwdev->stats; 3318 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 3319 const struct rtw89_rx_rate_cnt_info *info; 3320 int i; 3321 3322 seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d), RX: %u [%u] Mbps (lv: %d)\n", 3323 stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv, 3324 stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv); 3325 seq_printf(m, "Beacon: %u, TF: %u\n", pkt_stat->beacon_nr, 3326 stats->rx_tf_periodic); 3327 seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len, 3328 stats->rx_avg_len); 3329 3330 seq_puts(m, "RX count:\n"); 3331 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 3332 info = &rtw89_rx_rate_cnt_infos[i]; 3333 seq_printf(m, "%10s [", info->rate_mode); 3334 rtw89_debug_append_rx_rate(m, pkt_stat, 3335 info->first_rate, info->len); 3336 if (info->ext) { 3337 seq_puts(m, "]["); 3338 rtw89_debug_append_rx_rate(m, pkt_stat, 3339 info->first_rate + info->len, info->ext); 3340 } 3341 seq_puts(m, "]\n"); 3342 } 3343 3344 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m); 3345 3346 return 0; 3347 } 3348 3349 static void rtw89_dump_addr_cam(struct seq_file *m, 3350 struct rtw89_addr_cam_entry *addr_cam) 3351 { 3352 struct rtw89_sec_cam_entry *sec_entry; 3353 int i; 3354 3355 seq_printf(m, "\taddr_cam_idx=%u\n", addr_cam->addr_cam_idx); 3356 seq_printf(m, "\t-> bssid_cam_idx=%u\n", addr_cam->bssid_cam_idx); 3357 seq_printf(m, "\tsec_cam_bitmap=%*ph\n", (int)sizeof(addr_cam->sec_cam_map), 3358 addr_cam->sec_cam_map); 3359 for (i = 0; i < RTW89_SEC_CAM_IN_ADDR_CAM; i++) { 3360 sec_entry = addr_cam->sec_entries[i]; 3361 if (!sec_entry) 3362 continue; 3363 seq_printf(m, "\tsec[%d]: sec_cam_idx %u", i, sec_entry->sec_cam_idx); 3364 if (sec_entry->ext_key) 3365 seq_printf(m, ", %u", sec_entry->sec_cam_idx + 1); 3366 seq_puts(m, "\n"); 3367 } 3368 } 3369 3370 __printf(3, 4) 3371 static void rtw89_dump_pkt_offload(struct seq_file *m, struct list_head *pkt_list, 3372 const char *fmt, ...) 3373 { 3374 struct rtw89_pktofld_info *info; 3375 struct va_format vaf; 3376 va_list args; 3377 3378 if (list_empty(pkt_list)) 3379 return; 3380 3381 va_start(args, fmt); 3382 vaf.va = &args; 3383 vaf.fmt = fmt; 3384 3385 seq_printf(m, "%pV", &vaf); 3386 3387 va_end(args); 3388 3389 list_for_each_entry(info, pkt_list, list) 3390 seq_printf(m, "%d ", info->id); 3391 3392 seq_puts(m, "\n"); 3393 } 3394 3395 static 3396 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 3397 { 3398 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3399 struct seq_file *m = (struct seq_file *)data; 3400 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam; 3401 3402 seq_printf(m, "VIF [%d] %pM\n", rtwvif->mac_id, rtwvif->mac_addr); 3403 seq_printf(m, "\tbssid_cam_idx=%u\n", bssid_cam->bssid_cam_idx); 3404 rtw89_dump_addr_cam(m, &rtwvif->addr_cam); 3405 rtw89_dump_pkt_offload(m, &rtwvif->general_pkt_list, "\tpkt_ofld[GENERAL]: "); 3406 } 3407 3408 static void rtw89_dump_ba_cam(struct seq_file *m, struct rtw89_sta *rtwsta) 3409 { 3410 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 3411 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 3412 struct rtw89_ba_cam_entry *entry; 3413 bool first = true; 3414 3415 list_for_each_entry(entry, &rtwsta->ba_cam_list, list) { 3416 if (first) { 3417 seq_puts(m, "\tba_cam "); 3418 first = false; 3419 } else { 3420 seq_puts(m, ", "); 3421 } 3422 seq_printf(m, "tid[%u]=%d", entry->tid, 3423 (int)(entry - rtwdev->cam_info.ba_cam_entry)); 3424 } 3425 seq_puts(m, "\n"); 3426 } 3427 3428 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta) 3429 { 3430 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3431 struct seq_file *m = (struct seq_file *)data; 3432 3433 seq_printf(m, "STA [%d] %pM %s\n", rtwsta->mac_id, sta->addr, 3434 sta->tdls ? "(TDLS)" : ""); 3435 rtw89_dump_addr_cam(m, &rtwsta->addr_cam); 3436 rtw89_dump_ba_cam(m, rtwsta); 3437 } 3438 3439 static int rtw89_debug_priv_stations_get(struct seq_file *m, void *v) 3440 { 3441 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3442 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3443 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3444 u8 idx; 3445 3446 mutex_lock(&rtwdev->mutex); 3447 3448 seq_puts(m, "map:\n"); 3449 seq_printf(m, "\tmac_id: %*ph\n", (int)sizeof(rtwdev->mac_id_map), 3450 rtwdev->mac_id_map); 3451 seq_printf(m, "\taddr_cam: %*ph\n", (int)sizeof(cam_info->addr_cam_map), 3452 cam_info->addr_cam_map); 3453 seq_printf(m, "\tbssid_cam: %*ph\n", (int)sizeof(cam_info->bssid_cam_map), 3454 cam_info->bssid_cam_map); 3455 seq_printf(m, "\tsec_cam: %*ph\n", (int)sizeof(cam_info->sec_cam_map), 3456 cam_info->sec_cam_map); 3457 seq_printf(m, "\tba_cam: %*ph\n", (int)sizeof(cam_info->ba_cam_map), 3458 cam_info->ba_cam_map); 3459 seq_printf(m, "\tpkt_ofld: %*ph\n", (int)sizeof(rtwdev->pkt_offload), 3460 rtwdev->pkt_offload); 3461 3462 for (idx = NL80211_BAND_2GHZ; idx < NUM_NL80211_BANDS; idx++) { 3463 if (!(rtwdev->chip->support_bands & BIT(idx))) 3464 continue; 3465 rtw89_dump_pkt_offload(m, &rtwdev->scan_info.pkt_list[idx], 3466 "\t\t[SCAN %u]: ", idx); 3467 } 3468 3469 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw, 3470 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, m); 3471 3472 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, m); 3473 3474 mutex_unlock(&rtwdev->mutex); 3475 3476 return 0; 3477 } 3478 3479 static struct rtw89_debugfs_priv rtw89_debug_priv_read_reg = { 3480 .cb_read = rtw89_debug_priv_read_reg_get, 3481 .cb_write = rtw89_debug_priv_read_reg_select, 3482 }; 3483 3484 static struct rtw89_debugfs_priv rtw89_debug_priv_write_reg = { 3485 .cb_write = rtw89_debug_priv_write_reg_set, 3486 }; 3487 3488 static struct rtw89_debugfs_priv rtw89_debug_priv_read_rf = { 3489 .cb_read = rtw89_debug_priv_read_rf_get, 3490 .cb_write = rtw89_debug_priv_read_rf_select, 3491 }; 3492 3493 static struct rtw89_debugfs_priv rtw89_debug_priv_write_rf = { 3494 .cb_write = rtw89_debug_priv_write_rf_set, 3495 }; 3496 3497 static struct rtw89_debugfs_priv rtw89_debug_priv_rf_reg_dump = { 3498 .cb_read = rtw89_debug_priv_rf_reg_dump_get, 3499 }; 3500 3501 static struct rtw89_debugfs_priv rtw89_debug_priv_txpwr_table = { 3502 .cb_read = rtw89_debug_priv_txpwr_table_get, 3503 }; 3504 3505 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_reg_dump = { 3506 .cb_read = rtw89_debug_priv_mac_reg_dump_get, 3507 .cb_write = rtw89_debug_priv_mac_reg_dump_select, 3508 }; 3509 3510 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_mem_dump = { 3511 .cb_read = rtw89_debug_priv_mac_mem_dump_get, 3512 .cb_write = rtw89_debug_priv_mac_mem_dump_select, 3513 }; 3514 3515 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_dbg_port_dump = { 3516 .cb_read = rtw89_debug_priv_mac_dbg_port_dump_get, 3517 .cb_write = rtw89_debug_priv_mac_dbg_port_dump_select, 3518 }; 3519 3520 static struct rtw89_debugfs_priv rtw89_debug_priv_send_h2c = { 3521 .cb_write = rtw89_debug_priv_send_h2c_set, 3522 }; 3523 3524 static struct rtw89_debugfs_priv rtw89_debug_priv_early_h2c = { 3525 .cb_read = rtw89_debug_priv_early_h2c_get, 3526 .cb_write = rtw89_debug_priv_early_h2c_set, 3527 }; 3528 3529 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_crash = { 3530 .cb_read = rtw89_debug_priv_fw_crash_get, 3531 .cb_write = rtw89_debug_priv_fw_crash_set, 3532 }; 3533 3534 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_info = { 3535 .cb_read = rtw89_debug_priv_btc_info_get, 3536 }; 3537 3538 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_manual = { 3539 .cb_write = rtw89_debug_priv_btc_manual_set, 3540 }; 3541 3542 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_log_manual = { 3543 .cb_write = rtw89_debug_fw_log_btc_manual_set, 3544 }; 3545 3546 static struct rtw89_debugfs_priv rtw89_debug_priv_phy_info = { 3547 .cb_read = rtw89_debug_priv_phy_info_get, 3548 }; 3549 3550 static struct rtw89_debugfs_priv rtw89_debug_priv_stations = { 3551 .cb_read = rtw89_debug_priv_stations_get, 3552 }; 3553 3554 #define rtw89_debugfs_add(name, mode, fopname, parent) \ 3555 do { \ 3556 rtw89_debug_priv_ ##name.rtwdev = rtwdev; \ 3557 if (!debugfs_create_file(#name, mode, \ 3558 parent, &rtw89_debug_priv_ ##name, \ 3559 &file_ops_ ##fopname)) \ 3560 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 3561 } while (0) 3562 3563 #define rtw89_debugfs_add_w(name) \ 3564 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 3565 #define rtw89_debugfs_add_rw(name) \ 3566 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 3567 #define rtw89_debugfs_add_r(name) \ 3568 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 3569 3570 void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 3571 { 3572 struct dentry *debugfs_topdir; 3573 3574 debugfs_topdir = debugfs_create_dir("rtw89", 3575 rtwdev->hw->wiphy->debugfsdir); 3576 3577 rtw89_debugfs_add_rw(read_reg); 3578 rtw89_debugfs_add_w(write_reg); 3579 rtw89_debugfs_add_rw(read_rf); 3580 rtw89_debugfs_add_w(write_rf); 3581 rtw89_debugfs_add_r(rf_reg_dump); 3582 rtw89_debugfs_add_r(txpwr_table); 3583 rtw89_debugfs_add_rw(mac_reg_dump); 3584 rtw89_debugfs_add_rw(mac_mem_dump); 3585 rtw89_debugfs_add_rw(mac_dbg_port_dump); 3586 rtw89_debugfs_add_w(send_h2c); 3587 rtw89_debugfs_add_rw(early_h2c); 3588 rtw89_debugfs_add_rw(fw_crash); 3589 rtw89_debugfs_add_r(btc_info); 3590 rtw89_debugfs_add_w(btc_manual); 3591 rtw89_debugfs_add_w(fw_log_manual); 3592 rtw89_debugfs_add_r(phy_info); 3593 rtw89_debugfs_add_r(stations); 3594 } 3595 #endif 3596 3597 #ifdef CONFIG_RTW89_DEBUGMSG 3598 void __rtw89_debug(struct rtw89_dev *rtwdev, 3599 enum rtw89_debug_mask mask, 3600 const char *fmt, ...) 3601 { 3602 struct va_format vaf = { 3603 .fmt = fmt, 3604 }; 3605 3606 va_list args; 3607 3608 va_start(args, fmt); 3609 vaf.va = &args; 3610 3611 if (rtw89_debug_mask & mask) 3612 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 3613 3614 va_end(args); 3615 } 3616 EXPORT_SYMBOL(__rtw89_debug); 3617 #endif 3618