1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "debug.h" 7 #include "fw.h" 8 #include "mac.h" 9 #include "ps.h" 10 #include "reg.h" 11 #include "sar.h" 12 13 #ifdef CONFIG_RTW89_DEBUGMSG 14 unsigned int rtw89_debug_mask; 15 EXPORT_SYMBOL(rtw89_debug_mask); 16 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 17 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 18 #endif 19 20 #ifdef CONFIG_RTW89_DEBUGFS 21 struct rtw89_debugfs_priv { 22 struct rtw89_dev *rtwdev; 23 int (*cb_read)(struct seq_file *m, void *v); 24 ssize_t (*cb_write)(struct file *filp, const char __user *buffer, 25 size_t count, loff_t *loff); 26 union { 27 u32 cb_data; 28 struct { 29 u32 addr; 30 u8 len; 31 } read_reg; 32 struct { 33 u32 addr; 34 u32 mask; 35 u8 path; 36 } read_rf; 37 struct { 38 u8 ss_dbg:1; 39 u8 dle_dbg:1; 40 u8 dmac_dbg:1; 41 u8 cmac_dbg:1; 42 u8 dbg_port:1; 43 } dbgpkg_en; 44 struct { 45 u32 start; 46 u32 len; 47 u8 sel; 48 } mac_mem; 49 }; 50 }; 51 52 static int rtw89_debugfs_single_show(struct seq_file *m, void *v) 53 { 54 struct rtw89_debugfs_priv *debugfs_priv = m->private; 55 56 return debugfs_priv->cb_read(m, v); 57 } 58 59 static ssize_t rtw89_debugfs_single_write(struct file *filp, 60 const char __user *buffer, 61 size_t count, loff_t *loff) 62 { 63 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 64 65 return debugfs_priv->cb_write(filp, buffer, count, loff); 66 } 67 68 static ssize_t rtw89_debugfs_seq_file_write(struct file *filp, 69 const char __user *buffer, 70 size_t count, loff_t *loff) 71 { 72 struct seq_file *seqpriv = (struct seq_file *)filp->private_data; 73 struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private; 74 75 return debugfs_priv->cb_write(filp, buffer, count, loff); 76 } 77 78 static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp) 79 { 80 return single_open(filp, rtw89_debugfs_single_show, inode->i_private); 81 } 82 83 static int rtw89_debugfs_close(struct inode *inode, struct file *filp) 84 { 85 return 0; 86 } 87 88 static const struct file_operations file_ops_single_r = { 89 .owner = THIS_MODULE, 90 .open = rtw89_debugfs_single_open, 91 .read = seq_read, 92 .llseek = seq_lseek, 93 .release = single_release, 94 }; 95 96 static const struct file_operations file_ops_common_rw = { 97 .owner = THIS_MODULE, 98 .open = rtw89_debugfs_single_open, 99 .release = single_release, 100 .read = seq_read, 101 .llseek = seq_lseek, 102 .write = rtw89_debugfs_seq_file_write, 103 }; 104 105 static const struct file_operations file_ops_single_w = { 106 .owner = THIS_MODULE, 107 .write = rtw89_debugfs_single_write, 108 .open = simple_open, 109 .release = rtw89_debugfs_close, 110 }; 111 112 static ssize_t 113 rtw89_debug_priv_read_reg_select(struct file *filp, 114 const char __user *user_buf, 115 size_t count, loff_t *loff) 116 { 117 struct seq_file *m = (struct seq_file *)filp->private_data; 118 struct rtw89_debugfs_priv *debugfs_priv = m->private; 119 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 120 char buf[32]; 121 size_t buf_size; 122 u32 addr, len; 123 int num; 124 125 buf_size = min(count, sizeof(buf) - 1); 126 if (copy_from_user(buf, user_buf, buf_size)) 127 return -EFAULT; 128 129 buf[buf_size] = '\0'; 130 num = sscanf(buf, "%x %x", &addr, &len); 131 if (num != 2) { 132 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 133 return -EINVAL; 134 } 135 136 debugfs_priv->read_reg.addr = addr; 137 debugfs_priv->read_reg.len = len; 138 139 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 140 141 return count; 142 } 143 144 static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v) 145 { 146 struct rtw89_debugfs_priv *debugfs_priv = m->private; 147 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 148 u32 addr, data; 149 u8 len; 150 151 len = debugfs_priv->read_reg.len; 152 addr = debugfs_priv->read_reg.addr; 153 154 switch (len) { 155 case 1: 156 data = rtw89_read8(rtwdev, addr); 157 break; 158 case 2: 159 data = rtw89_read16(rtwdev, addr); 160 break; 161 case 4: 162 data = rtw89_read32(rtwdev, addr); 163 break; 164 default: 165 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 166 return -EINVAL; 167 } 168 169 seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data); 170 171 return 0; 172 } 173 174 static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp, 175 const char __user *user_buf, 176 size_t count, loff_t *loff) 177 { 178 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 179 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 180 char buf[32]; 181 size_t buf_size; 182 u32 addr, val, len; 183 int num; 184 185 buf_size = min(count, sizeof(buf) - 1); 186 if (copy_from_user(buf, user_buf, buf_size)) 187 return -EFAULT; 188 189 buf[buf_size] = '\0'; 190 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 191 if (num != 3) { 192 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 193 return -EINVAL; 194 } 195 196 switch (len) { 197 case 1: 198 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 199 rtw89_write8(rtwdev, addr, (u8)val); 200 break; 201 case 2: 202 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 203 rtw89_write16(rtwdev, addr, (u16)val); 204 break; 205 case 4: 206 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 207 rtw89_write32(rtwdev, addr, (u32)val); 208 break; 209 default: 210 rtw89_info(rtwdev, "invalid read write len %d\n", len); 211 break; 212 } 213 214 return count; 215 } 216 217 static ssize_t 218 rtw89_debug_priv_read_rf_select(struct file *filp, 219 const char __user *user_buf, 220 size_t count, loff_t *loff) 221 { 222 struct seq_file *m = (struct seq_file *)filp->private_data; 223 struct rtw89_debugfs_priv *debugfs_priv = m->private; 224 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 225 char buf[32]; 226 size_t buf_size; 227 u32 addr, mask; 228 u8 path; 229 int num; 230 231 buf_size = min(count, sizeof(buf) - 1); 232 if (copy_from_user(buf, user_buf, buf_size)) 233 return -EFAULT; 234 235 buf[buf_size] = '\0'; 236 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 237 if (num != 3) { 238 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 239 return -EINVAL; 240 } 241 242 if (path >= rtwdev->chip->rf_path_num) { 243 rtw89_info(rtwdev, "wrong rf path\n"); 244 return -EINVAL; 245 } 246 debugfs_priv->read_rf.addr = addr; 247 debugfs_priv->read_rf.mask = mask; 248 debugfs_priv->read_rf.path = path; 249 250 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 251 252 return count; 253 } 254 255 static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v) 256 { 257 struct rtw89_debugfs_priv *debugfs_priv = m->private; 258 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 259 u32 addr, data, mask; 260 u8 path; 261 262 addr = debugfs_priv->read_rf.addr; 263 mask = debugfs_priv->read_rf.mask; 264 path = debugfs_priv->read_rf.path; 265 266 data = rtw89_read_rf(rtwdev, path, addr, mask); 267 268 seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data); 269 270 return 0; 271 } 272 273 static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp, 274 const char __user *user_buf, 275 size_t count, loff_t *loff) 276 { 277 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 278 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 279 char buf[32]; 280 size_t buf_size; 281 u32 addr, val, mask; 282 u8 path; 283 int num; 284 285 buf_size = min(count, sizeof(buf) - 1); 286 if (copy_from_user(buf, user_buf, buf_size)) 287 return -EFAULT; 288 289 buf[buf_size] = '\0'; 290 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 291 if (num != 4) { 292 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 293 return -EINVAL; 294 } 295 296 if (path >= rtwdev->chip->rf_path_num) { 297 rtw89_info(rtwdev, "wrong rf path\n"); 298 return -EINVAL; 299 } 300 301 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 302 path, addr, val, mask); 303 rtw89_write_rf(rtwdev, path, addr, mask, val); 304 305 return count; 306 } 307 308 static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v) 309 { 310 struct rtw89_debugfs_priv *debugfs_priv = m->private; 311 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 312 const struct rtw89_chip_info *chip = rtwdev->chip; 313 u32 addr, offset, data; 314 u8 path; 315 316 for (path = 0; path < chip->rf_path_num; path++) { 317 seq_printf(m, "RF path %d:\n\n", path); 318 for (addr = 0; addr < 0x100; addr += 4) { 319 seq_printf(m, "0x%08x: ", addr); 320 for (offset = 0; offset < 4; offset++) { 321 data = rtw89_read_rf(rtwdev, path, 322 addr + offset, RFREG_MASK); 323 seq_printf(m, "0x%05x ", data); 324 } 325 seq_puts(m, "\n"); 326 } 327 seq_puts(m, "\n"); 328 } 329 330 return 0; 331 } 332 333 struct txpwr_ent { 334 const char *txt; 335 u8 len; 336 }; 337 338 struct txpwr_map { 339 const struct txpwr_ent *ent; 340 u8 size; 341 u32 addr_from; 342 u32 addr_to; 343 }; 344 345 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 346 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 347 348 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 349 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 350 351 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 352 { .len = 8, .txt = _t "\t- " \ 353 _e0 " " _e1 " " _e2 " " _e3 " " \ 354 _e4 " " _e5 " " _e6 " " _e7 } 355 356 static const struct txpwr_ent __txpwr_ent_byr[] = { 357 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 358 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 359 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 360 /* 1NSS */ 361 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 362 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 363 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 364 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 365 /* 2NSS */ 366 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 367 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 368 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 369 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 370 }; 371 372 static_assert((ARRAY_SIZE(__txpwr_ent_byr) * 4) == 373 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 374 375 static const struct txpwr_map __txpwr_map_byr = { 376 .ent = __txpwr_ent_byr, 377 .size = ARRAY_SIZE(__txpwr_ent_byr), 378 .addr_from = R_AX_PWR_BY_RATE, 379 .addr_to = R_AX_PWR_BY_RATE_MAX, 380 }; 381 382 static const struct txpwr_ent __txpwr_ent_lmt[] = { 383 /* 1TX */ 384 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 385 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 386 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 387 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 388 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 389 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 390 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 391 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 392 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 393 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 394 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 395 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 396 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 397 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 398 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 399 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 400 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 401 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 402 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 403 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 404 /* 2TX */ 405 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 406 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 407 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 408 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 409 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 410 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 411 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 412 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 413 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 414 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 415 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 416 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 417 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 418 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 419 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 420 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 421 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 422 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 423 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 424 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 425 }; 426 427 static_assert((ARRAY_SIZE(__txpwr_ent_lmt) * 2) == 428 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 429 430 static const struct txpwr_map __txpwr_map_lmt = { 431 .ent = __txpwr_ent_lmt, 432 .size = ARRAY_SIZE(__txpwr_ent_lmt), 433 .addr_from = R_AX_PWR_LMT, 434 .addr_to = R_AX_PWR_LMT_MAX, 435 }; 436 437 static const struct txpwr_ent __txpwr_ent_lmt_ru[] = { 438 /* 1TX */ 439 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 440 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 441 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 442 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 443 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 444 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 445 /* 2TX */ 446 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 447 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 448 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 449 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 450 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 451 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 452 }; 453 454 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru) * 8) == 455 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 456 457 static const struct txpwr_map __txpwr_map_lmt_ru = { 458 .ent = __txpwr_ent_lmt_ru, 459 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru), 460 .addr_from = R_AX_PWR_RU_LMT, 461 .addr_to = R_AX_PWR_RU_LMT_MAX, 462 }; 463 464 static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent, 465 const u8 *buf, const u8 cur) 466 { 467 char *fmt; 468 469 switch (ent->len) { 470 case 2: 471 fmt = "%s\t| %3d, %3d,\tdBm\n"; 472 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]); 473 return 2; 474 case 4: 475 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 476 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 477 buf[cur + 2], buf[cur + 3]); 478 return 4; 479 case 8: 480 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 481 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 482 buf[cur + 2], buf[cur + 3], buf[cur + 4], 483 buf[cur + 5], buf[cur + 6], buf[cur + 7]); 484 return 8; 485 default: 486 return 0; 487 } 488 } 489 490 static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev, 491 const struct txpwr_map *map) 492 { 493 u8 fct = rtwdev->chip->txpwr_factor_mac; 494 u8 *buf, cur, i; 495 u32 val, addr; 496 int ret; 497 498 buf = vzalloc(map->addr_to - map->addr_from + 4); 499 if (!buf) 500 return -ENOMEM; 501 502 for (addr = map->addr_from; addr <= map->addr_to; addr += 4) { 503 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 504 if (ret) 505 val = MASKDWORD; 506 507 cur = addr - map->addr_from; 508 for (i = 0; i < 4; i++, val >>= 8) 509 buf[cur + i] = FIELD_GET(MASKBYTE0, val) >> fct; 510 } 511 512 for (cur = 0, i = 0; i < map->size; i++) 513 cur += __print_txpwr_ent(m, &map->ent[i], buf, cur); 514 515 vfree(buf); 516 return 0; 517 } 518 519 #define case_REGD(_regd) \ 520 case RTW89_ ## _regd: \ 521 seq_puts(m, #_regd "\n"); \ 522 break 523 524 static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev) 525 { 526 u8 band = rtwdev->hal.current_band_type; 527 u8 regd = rtw89_regd_get(rtwdev, band); 528 529 switch (regd) { 530 default: 531 seq_printf(m, "UNKNOWN: %d\n", regd); 532 break; 533 case_REGD(WW); 534 case_REGD(ETSI); 535 case_REGD(FCC); 536 case_REGD(MKK); 537 case_REGD(NA); 538 case_REGD(IC); 539 case_REGD(KCC); 540 case_REGD(NCC); 541 case_REGD(CHILE); 542 case_REGD(ACMA); 543 case_REGD(MEXICO); 544 case_REGD(UKRAINE); 545 case_REGD(CN); 546 } 547 } 548 549 #undef case_REGD 550 551 static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v) 552 { 553 struct rtw89_debugfs_priv *debugfs_priv = m->private; 554 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 555 int ret = 0; 556 557 mutex_lock(&rtwdev->mutex); 558 rtw89_leave_ps_mode(rtwdev); 559 560 seq_puts(m, "[Regulatory] "); 561 __print_regd(m, rtwdev); 562 563 seq_puts(m, "[SAR]\n"); 564 rtw89_print_sar(m, rtwdev); 565 566 seq_puts(m, "\n[TX power byrate]\n"); 567 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_byr); 568 if (ret) 569 goto err; 570 571 seq_puts(m, "\n[TX power limit]\n"); 572 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt); 573 if (ret) 574 goto err; 575 576 seq_puts(m, "\n[TX power limit_ru]\n"); 577 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt_ru); 578 if (ret) 579 goto err; 580 581 err: 582 mutex_unlock(&rtwdev->mutex); 583 return ret; 584 } 585 586 static ssize_t 587 rtw89_debug_priv_mac_reg_dump_select(struct file *filp, 588 const char __user *user_buf, 589 size_t count, loff_t *loff) 590 { 591 struct seq_file *m = (struct seq_file *)filp->private_data; 592 struct rtw89_debugfs_priv *debugfs_priv = m->private; 593 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 594 char buf[32]; 595 size_t buf_size; 596 int sel; 597 int ret; 598 599 buf_size = min(count, sizeof(buf) - 1); 600 if (copy_from_user(buf, user_buf, buf_size)) 601 return -EFAULT; 602 603 buf[buf_size] = '\0'; 604 ret = kstrtoint(buf, 0, &sel); 605 if (ret) 606 return ret; 607 608 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 609 rtw89_info(rtwdev, "invalid args: %d\n", sel); 610 return -EINVAL; 611 } 612 613 debugfs_priv->cb_data = sel; 614 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 615 616 return count; 617 } 618 619 #define RTW89_MAC_PAGE_SIZE 0x100 620 621 static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v) 622 { 623 struct rtw89_debugfs_priv *debugfs_priv = m->private; 624 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 625 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 626 u32 start, end; 627 u32 i, j, k, page; 628 u32 val; 629 630 switch (reg_sel) { 631 case RTW89_DBG_SEL_MAC_00: 632 seq_puts(m, "Debug selected MAC page 0x00\n"); 633 start = 0x000; 634 end = 0x014; 635 break; 636 case RTW89_DBG_SEL_MAC_40: 637 seq_puts(m, "Debug selected MAC page 0x40\n"); 638 start = 0x040; 639 end = 0x07f; 640 break; 641 case RTW89_DBG_SEL_MAC_80: 642 seq_puts(m, "Debug selected MAC page 0x80\n"); 643 start = 0x080; 644 end = 0x09f; 645 break; 646 case RTW89_DBG_SEL_MAC_C0: 647 seq_puts(m, "Debug selected MAC page 0xc0\n"); 648 start = 0x0c0; 649 end = 0x0df; 650 break; 651 case RTW89_DBG_SEL_MAC_E0: 652 seq_puts(m, "Debug selected MAC page 0xe0\n"); 653 start = 0x0e0; 654 end = 0x0ff; 655 break; 656 case RTW89_DBG_SEL_BB: 657 seq_puts(m, "Debug selected BB register\n"); 658 start = 0x100; 659 end = 0x17f; 660 break; 661 case RTW89_DBG_SEL_IQK: 662 seq_puts(m, "Debug selected IQK register\n"); 663 start = 0x180; 664 end = 0x1bf; 665 break; 666 case RTW89_DBG_SEL_RFC: 667 seq_puts(m, "Debug selected RFC register\n"); 668 start = 0x1c0; 669 end = 0x1ff; 670 break; 671 default: 672 seq_puts(m, "Selected invalid register page\n"); 673 return -EINVAL; 674 } 675 676 for (i = start; i <= end; i++) { 677 page = i << 8; 678 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 679 seq_printf(m, "%08xh : ", 0x18600000 + j); 680 for (k = 0; k < 4; k++) { 681 val = rtw89_read32(rtwdev, j + (k << 2)); 682 seq_printf(m, "%08x ", val); 683 } 684 seq_puts(m, "\n"); 685 } 686 } 687 688 return 0; 689 } 690 691 static ssize_t 692 rtw89_debug_priv_mac_mem_dump_select(struct file *filp, 693 const char __user *user_buf, 694 size_t count, loff_t *loff) 695 { 696 struct seq_file *m = (struct seq_file *)filp->private_data; 697 struct rtw89_debugfs_priv *debugfs_priv = m->private; 698 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 699 char buf[32]; 700 size_t buf_size; 701 u32 sel, start_addr, len; 702 int num; 703 704 buf_size = min(count, sizeof(buf) - 1); 705 if (copy_from_user(buf, user_buf, buf_size)) 706 return -EFAULT; 707 708 buf[buf_size] = '\0'; 709 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 710 if (num != 3) { 711 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 712 return -EINVAL; 713 } 714 715 debugfs_priv->mac_mem.sel = sel; 716 debugfs_priv->mac_mem.start = start_addr; 717 debugfs_priv->mac_mem.len = len; 718 719 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 720 sel, start_addr, len); 721 722 return count; 723 } 724 725 static const u32 mac_mem_base_addr_table[RTW89_MAC_MEM_MAX] = { 726 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 727 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 728 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 729 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 730 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 731 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 732 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 733 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 734 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 735 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 736 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 737 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 738 }; 739 740 static void rtw89_debug_dump_mac_mem(struct seq_file *m, 741 struct rtw89_dev *rtwdev, 742 u8 sel, u32 start_addr, u32 len) 743 { 744 u32 base_addr, start_page, residue; 745 u32 i, j, p, pages; 746 u32 dump_len, remain; 747 u32 val; 748 749 remain = len; 750 pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1; 751 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE; 752 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE; 753 base_addr = mac_mem_base_addr_table[sel]; 754 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE; 755 756 for (p = 0; p < pages; p++) { 757 dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE); 758 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, base_addr); 759 for (i = R_AX_INDIR_ACCESS_ENTRY + residue; 760 i < R_AX_INDIR_ACCESS_ENTRY + dump_len;) { 761 seq_printf(m, "%08xh:", i); 762 for (j = 0; 763 j < 4 && i < R_AX_INDIR_ACCESS_ENTRY + dump_len; 764 j++, i += 4) { 765 val = rtw89_read32(rtwdev, i); 766 seq_printf(m, " %08x", val); 767 remain -= 4; 768 } 769 seq_puts(m, "\n"); 770 } 771 base_addr += MAC_MEM_DUMP_PAGE_SIZE; 772 } 773 } 774 775 static int 776 rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v) 777 { 778 struct rtw89_debugfs_priv *debugfs_priv = m->private; 779 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 780 781 mutex_lock(&rtwdev->mutex); 782 rtw89_leave_ps_mode(rtwdev); 783 rtw89_debug_dump_mac_mem(m, rtwdev, 784 debugfs_priv->mac_mem.sel, 785 debugfs_priv->mac_mem.start, 786 debugfs_priv->mac_mem.len); 787 mutex_unlock(&rtwdev->mutex); 788 789 return 0; 790 } 791 792 static ssize_t 793 rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp, 794 const char __user *user_buf, 795 size_t count, loff_t *loff) 796 { 797 struct seq_file *m = (struct seq_file *)filp->private_data; 798 struct rtw89_debugfs_priv *debugfs_priv = m->private; 799 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 800 char buf[32]; 801 size_t buf_size; 802 int sel, set; 803 int num; 804 bool enable; 805 806 buf_size = min(count, sizeof(buf) - 1); 807 if (copy_from_user(buf, user_buf, buf_size)) 808 return -EFAULT; 809 810 buf[buf_size] = '\0'; 811 num = sscanf(buf, "%d %d", &sel, &set); 812 if (num != 2) { 813 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 814 return -EINVAL; 815 } 816 817 enable = set == 0 ? false : true; 818 switch (sel) { 819 case 0: 820 debugfs_priv->dbgpkg_en.ss_dbg = enable; 821 break; 822 case 1: 823 debugfs_priv->dbgpkg_en.dle_dbg = enable; 824 break; 825 case 2: 826 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 827 break; 828 case 3: 829 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 830 break; 831 case 4: 832 debugfs_priv->dbgpkg_en.dbg_port = enable; 833 break; 834 default: 835 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 836 return -EINVAL; 837 } 838 839 rtw89_info(rtwdev, "%s debug port dump %d\n", 840 enable ? "Enable" : "Disable", sel); 841 842 return count; 843 } 844 845 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 846 struct seq_file *m) 847 { 848 return 0; 849 } 850 851 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 852 struct seq_file *m) 853 { 854 #define DLE_DFI_DUMP(__type, __target, __sel) \ 855 ({ \ 856 u32 __ctrl; \ 857 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 858 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 859 u32 __data, __val32; \ 860 int __ret; \ 861 \ 862 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 863 DLE_DFI_TYPE_##__target) | \ 864 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 865 B_AX_WDE_DFI_ACTIVE; \ 866 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 867 __ret = read_poll_timeout(rtw89_read32, __val32, \ 868 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 869 1000, 50000, false, \ 870 rtwdev, __reg_ctrl); \ 871 if (__ret) { \ 872 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 873 #__type, #__target, __sel); \ 874 return __ret; \ 875 } \ 876 \ 877 __data = rtw89_read32(rtwdev, __reg_data); \ 878 __data; \ 879 }) 880 881 #define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \ 882 ({ \ 883 u32 __freepg, __pubpg; \ 884 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 885 \ 886 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 887 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 888 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 889 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 890 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 891 seq_printf(__m, "[%s] freepg head: %d\n", \ 892 #__type, __freepg_head); \ 893 seq_printf(__m, "[%s] freepg tail: %d\n", \ 894 #__type, __freepg_tail); \ 895 seq_printf(__m, "[%s] pubpg num : %d\n", \ 896 #__type, __pubpg_num); \ 897 }) 898 899 #define case_QUOTA(__m, __type, __id) \ 900 case __type##_QTAID_##__id: \ 901 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 902 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 903 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 904 seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \ 905 #__type, #__id, rsv_pgnum); \ 906 seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \ 907 #__type, #__id, use_pgnum); \ 908 break 909 u32 quota_id; 910 u32 val32; 911 u16 rsv_pgnum, use_pgnum; 912 int ret; 913 914 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 915 if (ret) { 916 seq_puts(m, "[DLE] : DMAC not enabled\n"); 917 return ret; 918 } 919 920 DLE_DFI_FREE_PAGE_DUMP(m, WDE); 921 DLE_DFI_FREE_PAGE_DUMP(m, PLE); 922 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 923 switch (quota_id) { 924 case_QUOTA(m, WDE, HOST_IF); 925 case_QUOTA(m, WDE, WLAN_CPU); 926 case_QUOTA(m, WDE, DATA_CPU); 927 case_QUOTA(m, WDE, PKTIN); 928 case_QUOTA(m, WDE, CPUIO); 929 } 930 } 931 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 932 switch (quota_id) { 933 case_QUOTA(m, PLE, B0_TXPL); 934 case_QUOTA(m, PLE, B1_TXPL); 935 case_QUOTA(m, PLE, C2H); 936 case_QUOTA(m, PLE, H2C); 937 case_QUOTA(m, PLE, WLAN_CPU); 938 case_QUOTA(m, PLE, MPDU); 939 case_QUOTA(m, PLE, CMAC0_RX); 940 case_QUOTA(m, PLE, CMAC1_RX); 941 case_QUOTA(m, PLE, CMAC1_BBRPT); 942 case_QUOTA(m, PLE, WDRLS); 943 case_QUOTA(m, PLE, CPUIO); 944 } 945 } 946 947 return 0; 948 949 #undef case_QUOTA 950 #undef DLE_DFI_DUMP 951 #undef DLE_DFI_FREE_PAGE_DUMP 952 } 953 954 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 955 struct seq_file *m) 956 { 957 int ret; 958 959 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 960 if (ret) { 961 seq_puts(m, "[DMAC] : DMAC not enabled\n"); 962 return ret; 963 } 964 965 seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n", 966 rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR)); 967 seq_printf(m, "[0]R_AX_WDRLS_ERR_ISR=0x%08x\n", 968 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 969 seq_printf(m, "[1]R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 970 rtw89_read32(rtwdev, R_AX_SEC_ERR_IMR_ISR)); 971 seq_printf(m, "[2.1]R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 972 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 973 seq_printf(m, "[2.2]R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 974 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 975 seq_printf(m, "[3]R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 976 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 977 seq_printf(m, "[4]R_AX_WDE_ERR_ISR=0x%08x\n", 978 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 979 seq_printf(m, "[5.1]R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 980 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 981 seq_printf(m, "[5.2]R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 982 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 983 seq_printf(m, "[6]R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 984 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 985 seq_printf(m, "[7]R_AX_PKTIN_ERR_ISR=0x%08x\n", 986 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 987 seq_printf(m, "[8.1]R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 988 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 989 seq_printf(m, "[8.2]R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 990 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 991 seq_printf(m, "[8.3]R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 992 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 993 seq_printf(m, "[10]R_AX_CPUIO_ERR_ISR=0x%08x\n", 994 rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR)); 995 seq_printf(m, "[11.1]R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 996 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 997 seq_printf(m, "[11.2]R_AX_BBRPT_CHINFO_ERR_IMR_ISR=0x%08x\n", 998 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR_ISR)); 999 seq_printf(m, "[11.3]R_AX_BBRPT_DFS_ERR_IMR_ISR=0x%08x\n", 1000 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR_ISR)); 1001 seq_printf(m, "[11.4]R_AX_LA_ERRFLAG=0x%08x\n", 1002 rtw89_read32(rtwdev, R_AX_LA_ERRFLAG)); 1003 1004 return 0; 1005 } 1006 1007 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 1008 struct seq_file *m) 1009 { 1010 int ret; 1011 1012 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL); 1013 if (ret) { 1014 seq_puts(m, "[CMAC] : CMAC 0 not enabled\n"); 1015 return ret; 1016 } 1017 1018 seq_printf(m, "R_AX_CMAC_ERR_ISR=0x%08x\n", 1019 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR)); 1020 seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR=0x%08x\n", 1021 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR)); 1022 seq_printf(m, "[1]R_AX_PTCL_ISR0=0x%08x\n", 1023 rtw89_read32(rtwdev, R_AX_PTCL_ISR0)); 1024 seq_printf(m, "[3]R_AX_DLE_CTRL=0x%08x\n", 1025 rtw89_read32(rtwdev, R_AX_DLE_CTRL)); 1026 seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR=0x%08x\n", 1027 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR)); 1028 seq_printf(m, "[5]R_AX_TXPWR_ISR=0x%08x\n", 1029 rtw89_read32(rtwdev, R_AX_TXPWR_ISR)); 1030 seq_printf(m, "[6]R_AX_RMAC_ERR_ISR=0x%08x\n", 1031 rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR)); 1032 seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR=0x%08x\n", 1033 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR)); 1034 1035 ret = rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL); 1036 if (ret) { 1037 seq_puts(m, "[CMAC] : CMAC 1 not enabled\n"); 1038 return ret; 1039 } 1040 1041 seq_printf(m, "R_AX_CMAC_ERR_ISR_C1=0x%08x\n", 1042 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR_C1)); 1043 seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR_C1=0x%08x\n", 1044 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR_C1)); 1045 seq_printf(m, "[1]R_AX_PTCL_ISR0_C1=0x%08x\n", 1046 rtw89_read32(rtwdev, R_AX_PTCL_ISR0_C1)); 1047 seq_printf(m, "[3]R_AX_DLE_CTRL_C1=0x%08x\n", 1048 rtw89_read32(rtwdev, R_AX_DLE_CTRL_C1)); 1049 seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR_C1=0x%02x\n", 1050 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR_C1)); 1051 seq_printf(m, "[5]R_AX_TXPWR_ISR_C1=0x%08x\n", 1052 rtw89_read32(rtwdev, R_AX_TXPWR_ISR_C1)); 1053 seq_printf(m, "[6]R_AX_RMAC_ERR_ISR_C1=0x%08x\n", 1054 rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR_C1)); 1055 seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR_C1=0x%08x\n", 1056 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR_C1)); 1057 1058 return 0; 1059 } 1060 1061 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1062 .sel_addr = R_AX_PTCL_DBG, 1063 .sel_byte = 1, 1064 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1065 .srt = 0x00, 1066 .end = 0x3F, 1067 .rd_addr = R_AX_PTCL_DBG_INFO, 1068 .rd_byte = 4, 1069 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1070 }; 1071 1072 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1073 .sel_addr = R_AX_PTCL_DBG_C1, 1074 .sel_byte = 1, 1075 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1076 .srt = 0x00, 1077 .end = 0x3F, 1078 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1079 .rd_byte = 4, 1080 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1081 }; 1082 1083 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 1084 .sel_addr = R_AX_SCH_DBG_SEL, 1085 .sel_byte = 1, 1086 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1087 .srt = 0x00, 1088 .end = 0x2F, 1089 .rd_addr = R_AX_SCH_DBG, 1090 .rd_byte = 4, 1091 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1092 }; 1093 1094 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 1095 .sel_addr = R_AX_SCH_DBG_SEL_C1, 1096 .sel_byte = 1, 1097 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1098 .srt = 0x00, 1099 .end = 0x2F, 1100 .rd_addr = R_AX_SCH_DBG_C1, 1101 .rd_byte = 4, 1102 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1103 }; 1104 1105 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 1106 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 1107 .sel_byte = 1, 1108 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1109 .srt = 0x00, 1110 .end = 0x19, 1111 .rd_addr = R_AX_DBG_PORT_SEL, 1112 .rd_byte = 4, 1113 .rd_msk = B_AX_DEBUG_ST_MASK 1114 }; 1115 1116 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 1117 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 1118 .sel_byte = 1, 1119 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1120 .srt = 0x00, 1121 .end = 0x19, 1122 .rd_addr = R_AX_DBG_PORT_SEL, 1123 .rd_byte = 4, 1124 .rd_msk = B_AX_DEBUG_ST_MASK 1125 }; 1126 1127 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 1128 .sel_addr = R_AX_RX_DEBUG_SELECT, 1129 .sel_byte = 1, 1130 .sel_msk = B_AX_DEBUG_SEL_MASK, 1131 .srt = 0x00, 1132 .end = 0x58, 1133 .rd_addr = R_AX_DBG_PORT_SEL, 1134 .rd_byte = 4, 1135 .rd_msk = B_AX_DEBUG_ST_MASK 1136 }; 1137 1138 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 1139 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 1140 .sel_byte = 1, 1141 .sel_msk = B_AX_DEBUG_SEL_MASK, 1142 .srt = 0x00, 1143 .end = 0x58, 1144 .rd_addr = R_AX_DBG_PORT_SEL, 1145 .rd_byte = 4, 1146 .rd_msk = B_AX_DEBUG_ST_MASK 1147 }; 1148 1149 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 1150 .sel_addr = R_AX_RX_STATE_MONITOR, 1151 .sel_byte = 1, 1152 .sel_msk = B_AX_STATE_SEL_MASK, 1153 .srt = 0x00, 1154 .end = 0x17, 1155 .rd_addr = R_AX_RX_STATE_MONITOR, 1156 .rd_byte = 4, 1157 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 1158 }; 1159 1160 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 1161 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 1162 .sel_byte = 1, 1163 .sel_msk = B_AX_STATE_SEL_MASK, 1164 .srt = 0x00, 1165 .end = 0x17, 1166 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 1167 .rd_byte = 4, 1168 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 1169 }; 1170 1171 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 1172 .sel_addr = R_AX_RMAC_PLCP_MON, 1173 .sel_byte = 4, 1174 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 1175 .srt = 0x0, 1176 .end = 0xF, 1177 .rd_addr = R_AX_RMAC_PLCP_MON, 1178 .rd_byte = 4, 1179 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 1180 }; 1181 1182 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 1183 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 1184 .sel_byte = 4, 1185 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 1186 .srt = 0x0, 1187 .end = 0xF, 1188 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 1189 .rd_byte = 4, 1190 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 1191 }; 1192 1193 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 1194 .sel_addr = R_AX_DBGSEL_TRXPTCL, 1195 .sel_byte = 1, 1196 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 1197 .srt = 0x08, 1198 .end = 0x10, 1199 .rd_addr = R_AX_DBG_PORT_SEL, 1200 .rd_byte = 4, 1201 .rd_msk = B_AX_DEBUG_ST_MASK 1202 }; 1203 1204 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 1205 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 1206 .sel_byte = 1, 1207 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 1208 .srt = 0x08, 1209 .end = 0x10, 1210 .rd_addr = R_AX_DBG_PORT_SEL, 1211 .rd_byte = 4, 1212 .rd_msk = B_AX_DEBUG_ST_MASK 1213 }; 1214 1215 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 1216 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 1217 .sel_byte = 1, 1218 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1219 .srt = 0x00, 1220 .end = 0x07, 1221 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 1222 .rd_byte = 4, 1223 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 1224 }; 1225 1226 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 1227 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 1228 .sel_byte = 1, 1229 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1230 .srt = 0x00, 1231 .end = 0x07, 1232 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 1233 .rd_byte = 4, 1234 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 1235 }; 1236 1237 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 1238 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 1239 .sel_byte = 1, 1240 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1241 .srt = 0x00, 1242 .end = 0x07, 1243 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 1244 .rd_byte = 4, 1245 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 1246 }; 1247 1248 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 1249 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 1250 .sel_byte = 1, 1251 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1252 .srt = 0x00, 1253 .end = 0x07, 1254 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 1255 .rd_byte = 4, 1256 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 1257 }; 1258 1259 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 1260 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 1261 .sel_byte = 1, 1262 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1263 .srt = 0x00, 1264 .end = 0x04, 1265 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 1266 .rd_byte = 4, 1267 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 1268 }; 1269 1270 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 1271 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 1272 .sel_byte = 1, 1273 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1274 .srt = 0x00, 1275 .end = 0x04, 1276 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 1277 .rd_byte = 4, 1278 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 1279 }; 1280 1281 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 1282 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 1283 .sel_byte = 1, 1284 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1285 .srt = 0x00, 1286 .end = 0x04, 1287 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 1288 .rd_byte = 4, 1289 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 1290 }; 1291 1292 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 1293 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 1294 .sel_byte = 1, 1295 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1296 .srt = 0x00, 1297 .end = 0x04, 1298 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 1299 .rd_byte = 4, 1300 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 1301 }; 1302 1303 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 1304 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1305 .sel_byte = 4, 1306 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1307 .srt = 0x80000000, 1308 .end = 0x80000001, 1309 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1310 .rd_byte = 4, 1311 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1312 }; 1313 1314 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 1315 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1316 .sel_byte = 4, 1317 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1318 .srt = 0x80010000, 1319 .end = 0x80010004, 1320 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1321 .rd_byte = 4, 1322 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1323 }; 1324 1325 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 1326 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1327 .sel_byte = 4, 1328 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1329 .srt = 0x80020000, 1330 .end = 0x80020FFF, 1331 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1332 .rd_byte = 4, 1333 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1334 }; 1335 1336 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 1337 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1338 .sel_byte = 4, 1339 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1340 .srt = 0x80030000, 1341 .end = 0x80030FFF, 1342 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1343 .rd_byte = 4, 1344 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1345 }; 1346 1347 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 1348 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1349 .sel_byte = 4, 1350 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1351 .srt = 0x80040000, 1352 .end = 0x80040FFF, 1353 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1354 .rd_byte = 4, 1355 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1356 }; 1357 1358 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 1359 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1360 .sel_byte = 4, 1361 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1362 .srt = 0x80050000, 1363 .end = 0x80050FFF, 1364 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1365 .rd_byte = 4, 1366 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1367 }; 1368 1369 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 1370 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1371 .sel_byte = 4, 1372 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1373 .srt = 0x80060000, 1374 .end = 0x80060453, 1375 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1376 .rd_byte = 4, 1377 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1378 }; 1379 1380 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 1381 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1382 .sel_byte = 4, 1383 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1384 .srt = 0x80070000, 1385 .end = 0x80070011, 1386 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1387 .rd_byte = 4, 1388 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1389 }; 1390 1391 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 1392 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1393 .sel_byte = 4, 1394 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1395 .srt = 0x80000000, 1396 .end = 0x80000001, 1397 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1398 .rd_byte = 4, 1399 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1400 }; 1401 1402 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 1403 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1404 .sel_byte = 4, 1405 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1406 .srt = 0x80010000, 1407 .end = 0x8001000A, 1408 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1409 .rd_byte = 4, 1410 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1411 }; 1412 1413 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 1414 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1415 .sel_byte = 4, 1416 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1417 .srt = 0x80020000, 1418 .end = 0x80020DBF, 1419 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1420 .rd_byte = 4, 1421 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1422 }; 1423 1424 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 1425 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1426 .sel_byte = 4, 1427 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1428 .srt = 0x80030000, 1429 .end = 0x80030DBF, 1430 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1431 .rd_byte = 4, 1432 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1433 }; 1434 1435 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 1436 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1437 .sel_byte = 4, 1438 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1439 .srt = 0x80040000, 1440 .end = 0x80040DBF, 1441 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1442 .rd_byte = 4, 1443 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1444 }; 1445 1446 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 1447 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1448 .sel_byte = 4, 1449 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1450 .srt = 0x80050000, 1451 .end = 0x80050DBF, 1452 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1453 .rd_byte = 4, 1454 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1455 }; 1456 1457 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 1458 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1459 .sel_byte = 4, 1460 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1461 .srt = 0x80060000, 1462 .end = 0x80060041, 1463 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1464 .rd_byte = 4, 1465 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1466 }; 1467 1468 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 1469 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1470 .sel_byte = 4, 1471 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1472 .srt = 0x80070000, 1473 .end = 0x80070001, 1474 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1475 .rd_byte = 4, 1476 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1477 }; 1478 1479 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 1480 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 1481 .sel_byte = 4, 1482 .sel_msk = B_AX_DFI_DATA_MASK, 1483 .srt = 0x80000000, 1484 .end = 0x8000017f, 1485 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 1486 .rd_byte = 4, 1487 .rd_msk = B_AX_DFI_DATA_MASK 1488 }; 1489 1490 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 1491 .sel_addr = R_AX_PCIE_DBG_CTRL, 1492 .sel_byte = 2, 1493 .sel_msk = B_AX_DBG_SEL_MASK, 1494 .srt = 0x00, 1495 .end = 0x03, 1496 .rd_addr = R_AX_DBG_PORT_SEL, 1497 .rd_byte = 4, 1498 .rd_msk = B_AX_DEBUG_ST_MASK 1499 }; 1500 1501 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 1502 .sel_addr = R_AX_PCIE_DBG_CTRL, 1503 .sel_byte = 2, 1504 .sel_msk = B_AX_DBG_SEL_MASK, 1505 .srt = 0x00, 1506 .end = 0x04, 1507 .rd_addr = R_AX_DBG_PORT_SEL, 1508 .rd_byte = 4, 1509 .rd_msk = B_AX_DEBUG_ST_MASK 1510 }; 1511 1512 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 1513 .sel_addr = R_AX_PCIE_DBG_CTRL, 1514 .sel_byte = 2, 1515 .sel_msk = B_AX_DBG_SEL_MASK, 1516 .srt = 0x00, 1517 .end = 0x01, 1518 .rd_addr = R_AX_DBG_PORT_SEL, 1519 .rd_byte = 4, 1520 .rd_msk = B_AX_DEBUG_ST_MASK 1521 }; 1522 1523 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 1524 .sel_addr = R_AX_PCIE_DBG_CTRL, 1525 .sel_byte = 2, 1526 .sel_msk = B_AX_DBG_SEL_MASK, 1527 .srt = 0x00, 1528 .end = 0x05, 1529 .rd_addr = R_AX_DBG_PORT_SEL, 1530 .rd_byte = 4, 1531 .rd_msk = B_AX_DEBUG_ST_MASK 1532 }; 1533 1534 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 1535 .sel_addr = R_AX_PCIE_DBG_CTRL, 1536 .sel_byte = 2, 1537 .sel_msk = B_AX_DBG_SEL_MASK, 1538 .srt = 0x00, 1539 .end = 0x05, 1540 .rd_addr = R_AX_DBG_PORT_SEL, 1541 .rd_byte = 4, 1542 .rd_msk = B_AX_DEBUG_ST_MASK 1543 }; 1544 1545 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 1546 .sel_addr = R_AX_PCIE_DBG_CTRL, 1547 .sel_byte = 2, 1548 .sel_msk = B_AX_DBG_SEL_MASK, 1549 .srt = 0x00, 1550 .end = 0x06, 1551 .rd_addr = R_AX_DBG_PORT_SEL, 1552 .rd_byte = 4, 1553 .rd_msk = B_AX_DEBUG_ST_MASK 1554 }; 1555 1556 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 1557 .sel_addr = R_AX_DBG_CTRL, 1558 .sel_byte = 1, 1559 .sel_msk = B_AX_DBG_SEL0, 1560 .srt = 0x34, 1561 .end = 0x3C, 1562 .rd_addr = R_AX_DBG_PORT_SEL, 1563 .rd_byte = 4, 1564 .rd_msk = B_AX_DEBUG_ST_MASK 1565 }; 1566 1567 static const struct rtw89_mac_dbg_port_info * 1568 rtw89_debug_mac_dbg_port_sel(struct seq_file *m, 1569 struct rtw89_dev *rtwdev, u32 sel) 1570 { 1571 const struct rtw89_mac_dbg_port_info *info; 1572 u32 val32; 1573 u16 val16; 1574 u8 val8; 1575 1576 switch (sel) { 1577 case RTW89_DBG_PORT_SEL_PTCL_C0: 1578 info = &dbg_port_ptcl_c0; 1579 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 1580 val16 |= B_AX_PTCL_DBG_EN; 1581 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 1582 seq_puts(m, "Enable PTCL C0 dbgport.\n"); 1583 break; 1584 case RTW89_DBG_PORT_SEL_PTCL_C1: 1585 info = &dbg_port_ptcl_c1; 1586 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 1587 val16 |= B_AX_PTCL_DBG_EN; 1588 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 1589 seq_puts(m, "Enable PTCL C1 dbgport.\n"); 1590 break; 1591 case RTW89_DBG_PORT_SEL_SCH_C0: 1592 info = &dbg_port_sch_c0; 1593 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 1594 val32 |= B_AX_SCH_DBG_EN; 1595 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 1596 seq_puts(m, "Enable SCH C0 dbgport.\n"); 1597 break; 1598 case RTW89_DBG_PORT_SEL_SCH_C1: 1599 info = &dbg_port_sch_c1; 1600 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 1601 val32 |= B_AX_SCH_DBG_EN; 1602 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 1603 seq_puts(m, "Enable SCH C1 dbgport.\n"); 1604 break; 1605 case RTW89_DBG_PORT_SEL_TMAC_C0: 1606 info = &dbg_port_tmac_c0; 1607 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 1608 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 1609 B_AX_DBGSEL_TRXPTCL_MASK); 1610 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 1611 1612 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1613 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 1614 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 1615 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1616 1617 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1618 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1619 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1620 seq_puts(m, "Enable TMAC C0 dbgport.\n"); 1621 break; 1622 case RTW89_DBG_PORT_SEL_TMAC_C1: 1623 info = &dbg_port_tmac_c1; 1624 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 1625 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 1626 B_AX_DBGSEL_TRXPTCL_MASK); 1627 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 1628 1629 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1630 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 1631 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 1632 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1633 1634 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1635 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1636 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1637 seq_puts(m, "Enable TMAC C1 dbgport.\n"); 1638 break; 1639 case RTW89_DBG_PORT_SEL_RMAC_C0: 1640 info = &dbg_port_rmac_c0; 1641 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 1642 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 1643 B_AX_DBGSEL_TRXPTCL_MASK); 1644 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 1645 1646 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1647 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 1648 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 1649 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1650 1651 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1652 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1653 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1654 1655 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 1656 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 1657 B_AX_DBGSEL_TRXPTCL_MASK); 1658 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 1659 seq_puts(m, "Enable RMAC C0 dbgport.\n"); 1660 break; 1661 case RTW89_DBG_PORT_SEL_RMAC_C1: 1662 info = &dbg_port_rmac_c1; 1663 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 1664 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 1665 B_AX_DBGSEL_TRXPTCL_MASK); 1666 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 1667 1668 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1669 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 1670 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 1671 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1672 1673 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1674 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1675 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1676 1677 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 1678 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 1679 B_AX_DBGSEL_TRXPTCL_MASK); 1680 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 1681 seq_puts(m, "Enable RMAC C1 dbgport.\n"); 1682 break; 1683 case RTW89_DBG_PORT_SEL_RMACST_C0: 1684 info = &dbg_port_rmacst_c0; 1685 seq_puts(m, "Enable RMAC state C0 dbgport.\n"); 1686 break; 1687 case RTW89_DBG_PORT_SEL_RMACST_C1: 1688 info = &dbg_port_rmacst_c1; 1689 seq_puts(m, "Enable RMAC state C1 dbgport.\n"); 1690 break; 1691 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 1692 info = &dbg_port_rmac_plcp_c0; 1693 seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n"); 1694 break; 1695 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 1696 info = &dbg_port_rmac_plcp_c1; 1697 seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n"); 1698 break; 1699 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 1700 info = &dbg_port_trxptcl_c0; 1701 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1702 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 1703 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 1704 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1705 1706 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1707 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1708 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1709 seq_puts(m, "Enable TRXPTCL C0 dbgport.\n"); 1710 break; 1711 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 1712 info = &dbg_port_trxptcl_c1; 1713 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1714 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 1715 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 1716 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1717 1718 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1719 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1720 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1721 seq_puts(m, "Enable TRXPTCL C1 dbgport.\n"); 1722 break; 1723 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 1724 info = &dbg_port_tx_infol_c0; 1725 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1726 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1727 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1728 seq_puts(m, "Enable tx infol dump.\n"); 1729 break; 1730 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 1731 info = &dbg_port_tx_infoh_c0; 1732 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1733 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1734 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1735 seq_puts(m, "Enable tx infoh dump.\n"); 1736 break; 1737 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 1738 info = &dbg_port_tx_infol_c1; 1739 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1740 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1741 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1742 seq_puts(m, "Enable tx infol dump.\n"); 1743 break; 1744 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 1745 info = &dbg_port_tx_infoh_c1; 1746 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1747 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1748 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1749 seq_puts(m, "Enable tx infoh dump.\n"); 1750 break; 1751 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 1752 info = &dbg_port_txtf_infol_c0; 1753 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1754 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1755 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1756 seq_puts(m, "Enable tx tf infol dump.\n"); 1757 break; 1758 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 1759 info = &dbg_port_txtf_infoh_c0; 1760 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1761 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1762 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1763 seq_puts(m, "Enable tx tf infoh dump.\n"); 1764 break; 1765 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 1766 info = &dbg_port_txtf_infol_c1; 1767 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1768 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1769 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1770 seq_puts(m, "Enable tx tf infol dump.\n"); 1771 break; 1772 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 1773 info = &dbg_port_txtf_infoh_c1; 1774 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1775 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1776 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1777 seq_puts(m, "Enable tx tf infoh dump.\n"); 1778 break; 1779 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 1780 info = &dbg_port_wde_bufmgn_freepg; 1781 seq_puts(m, "Enable wde bufmgn freepg dump.\n"); 1782 break; 1783 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 1784 info = &dbg_port_wde_bufmgn_quota; 1785 seq_puts(m, "Enable wde bufmgn quota dump.\n"); 1786 break; 1787 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 1788 info = &dbg_port_wde_bufmgn_pagellt; 1789 seq_puts(m, "Enable wde bufmgn pagellt dump.\n"); 1790 break; 1791 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 1792 info = &dbg_port_wde_bufmgn_pktinfo; 1793 seq_puts(m, "Enable wde bufmgn pktinfo dump.\n"); 1794 break; 1795 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 1796 info = &dbg_port_wde_quemgn_prepkt; 1797 seq_puts(m, "Enable wde quemgn prepkt dump.\n"); 1798 break; 1799 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 1800 info = &dbg_port_wde_quemgn_nxtpkt; 1801 seq_puts(m, "Enable wde quemgn nxtpkt dump.\n"); 1802 break; 1803 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 1804 info = &dbg_port_wde_quemgn_qlnktbl; 1805 seq_puts(m, "Enable wde quemgn qlnktbl dump.\n"); 1806 break; 1807 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 1808 info = &dbg_port_wde_quemgn_qempty; 1809 seq_puts(m, "Enable wde quemgn qempty dump.\n"); 1810 break; 1811 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 1812 info = &dbg_port_ple_bufmgn_freepg; 1813 seq_puts(m, "Enable ple bufmgn freepg dump.\n"); 1814 break; 1815 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 1816 info = &dbg_port_ple_bufmgn_quota; 1817 seq_puts(m, "Enable ple bufmgn quota dump.\n"); 1818 break; 1819 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 1820 info = &dbg_port_ple_bufmgn_pagellt; 1821 seq_puts(m, "Enable ple bufmgn pagellt dump.\n"); 1822 break; 1823 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 1824 info = &dbg_port_ple_bufmgn_pktinfo; 1825 seq_puts(m, "Enable ple bufmgn pktinfo dump.\n"); 1826 break; 1827 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 1828 info = &dbg_port_ple_quemgn_prepkt; 1829 seq_puts(m, "Enable ple quemgn prepkt dump.\n"); 1830 break; 1831 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 1832 info = &dbg_port_ple_quemgn_nxtpkt; 1833 seq_puts(m, "Enable ple quemgn nxtpkt dump.\n"); 1834 break; 1835 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 1836 info = &dbg_port_ple_quemgn_qlnktbl; 1837 seq_puts(m, "Enable ple quemgn qlnktbl dump.\n"); 1838 break; 1839 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 1840 info = &dbg_port_ple_quemgn_qempty; 1841 seq_puts(m, "Enable ple quemgn qempty dump.\n"); 1842 break; 1843 case RTW89_DBG_PORT_SEL_PKTINFO: 1844 info = &dbg_port_pktinfo; 1845 seq_puts(m, "Enable pktinfo dump.\n"); 1846 break; 1847 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 1848 info = &dbg_port_pcie_txdma; 1849 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1850 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 1851 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 1852 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1853 seq_puts(m, "Enable pcie txdma dump.\n"); 1854 break; 1855 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 1856 info = &dbg_port_pcie_rxdma; 1857 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1858 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 1859 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 1860 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1861 seq_puts(m, "Enable pcie rxdma dump.\n"); 1862 break; 1863 case RTW89_DBG_PORT_SEL_PCIE_CVT: 1864 info = &dbg_port_pcie_cvt; 1865 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1866 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 1867 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 1868 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1869 seq_puts(m, "Enable pcie cvt dump.\n"); 1870 break; 1871 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 1872 info = &dbg_port_pcie_cxpl; 1873 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1874 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 1875 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 1876 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1877 seq_puts(m, "Enable pcie cxpl dump.\n"); 1878 break; 1879 case RTW89_DBG_PORT_SEL_PCIE_IO: 1880 info = &dbg_port_pcie_io; 1881 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1882 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 1883 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 1884 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1885 seq_puts(m, "Enable pcie io dump.\n"); 1886 break; 1887 case RTW89_DBG_PORT_SEL_PCIE_MISC: 1888 info = &dbg_port_pcie_misc; 1889 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1890 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 1891 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 1892 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1893 seq_puts(m, "Enable pcie misc dump.\n"); 1894 break; 1895 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 1896 info = &dbg_port_pcie_misc2; 1897 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 1898 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 1899 B_AX_DBG_SEL_MASK); 1900 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 1901 seq_puts(m, "Enable pcie misc2 dump.\n"); 1902 break; 1903 default: 1904 seq_puts(m, "Dbg port select err\n"); 1905 return NULL; 1906 } 1907 1908 return info; 1909 } 1910 1911 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 1912 { 1913 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 1914 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 1915 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 1916 return false; 1917 if (rtwdev->chip->chip_id == RTL8852B && 1918 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 1919 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 1920 return false; 1921 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 1922 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 1923 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 1924 return false; 1925 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 1926 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 1927 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 1928 return false; 1929 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 1930 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 1931 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 1932 return false; 1933 1934 return true; 1935 } 1936 1937 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 1938 struct seq_file *m, u32 sel) 1939 { 1940 const struct rtw89_mac_dbg_port_info *info; 1941 u8 val8; 1942 u16 val16; 1943 u32 val32; 1944 u32 i; 1945 1946 info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel); 1947 if (!info) { 1948 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 1949 return -EINVAL; 1950 } 1951 1952 #define case_DBG_SEL(__sel) \ 1953 case RTW89_DBG_PORT_SEL_##__sel: \ 1954 seq_puts(m, "Dump debug port " #__sel ":\n"); \ 1955 break 1956 1957 switch (sel) { 1958 case_DBG_SEL(PTCL_C0); 1959 case_DBG_SEL(PTCL_C1); 1960 case_DBG_SEL(SCH_C0); 1961 case_DBG_SEL(SCH_C1); 1962 case_DBG_SEL(TMAC_C0); 1963 case_DBG_SEL(TMAC_C1); 1964 case_DBG_SEL(RMAC_C0); 1965 case_DBG_SEL(RMAC_C1); 1966 case_DBG_SEL(RMACST_C0); 1967 case_DBG_SEL(RMACST_C1); 1968 case_DBG_SEL(TRXPTCL_C0); 1969 case_DBG_SEL(TRXPTCL_C1); 1970 case_DBG_SEL(TX_INFOL_C0); 1971 case_DBG_SEL(TX_INFOH_C0); 1972 case_DBG_SEL(TX_INFOL_C1); 1973 case_DBG_SEL(TX_INFOH_C1); 1974 case_DBG_SEL(TXTF_INFOL_C0); 1975 case_DBG_SEL(TXTF_INFOH_C0); 1976 case_DBG_SEL(TXTF_INFOL_C1); 1977 case_DBG_SEL(TXTF_INFOH_C1); 1978 case_DBG_SEL(WDE_BUFMGN_FREEPG); 1979 case_DBG_SEL(WDE_BUFMGN_QUOTA); 1980 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 1981 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 1982 case_DBG_SEL(WDE_QUEMGN_PREPKT); 1983 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 1984 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 1985 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 1986 case_DBG_SEL(PLE_BUFMGN_FREEPG); 1987 case_DBG_SEL(PLE_BUFMGN_QUOTA); 1988 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 1989 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 1990 case_DBG_SEL(PLE_QUEMGN_PREPKT); 1991 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 1992 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 1993 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 1994 case_DBG_SEL(PKTINFO); 1995 case_DBG_SEL(PCIE_TXDMA); 1996 case_DBG_SEL(PCIE_RXDMA); 1997 case_DBG_SEL(PCIE_CVT); 1998 case_DBG_SEL(PCIE_CXPL); 1999 case_DBG_SEL(PCIE_IO); 2000 case_DBG_SEL(PCIE_MISC); 2001 case_DBG_SEL(PCIE_MISC2); 2002 } 2003 2004 #undef case_DBG_SEL 2005 2006 seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr); 2007 seq_printf(m, "Read addr = 0x%X\n", info->rd_addr); 2008 2009 for (i = info->srt; i <= info->end; i++) { 2010 switch (info->sel_byte) { 2011 case 1: 2012 default: 2013 rtw89_write8_mask(rtwdev, info->sel_addr, 2014 info->sel_msk, i); 2015 seq_printf(m, "0x%02X: ", i); 2016 break; 2017 case 2: 2018 rtw89_write16_mask(rtwdev, info->sel_addr, 2019 info->sel_msk, i); 2020 seq_printf(m, "0x%04X: ", i); 2021 break; 2022 case 4: 2023 rtw89_write32_mask(rtwdev, info->sel_addr, 2024 info->sel_msk, i); 2025 seq_printf(m, "0x%04X: ", i); 2026 break; 2027 } 2028 2029 udelay(10); 2030 2031 switch (info->rd_byte) { 2032 case 1: 2033 default: 2034 val8 = rtw89_read8_mask(rtwdev, 2035 info->rd_addr, info->rd_msk); 2036 seq_printf(m, "0x%02X\n", val8); 2037 break; 2038 case 2: 2039 val16 = rtw89_read16_mask(rtwdev, 2040 info->rd_addr, info->rd_msk); 2041 seq_printf(m, "0x%04X\n", val16); 2042 break; 2043 case 4: 2044 val32 = rtw89_read32_mask(rtwdev, 2045 info->rd_addr, info->rd_msk); 2046 seq_printf(m, "0x%08X\n", val32); 2047 break; 2048 } 2049 } 2050 2051 return 0; 2052 } 2053 2054 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 2055 struct seq_file *m) 2056 { 2057 u32 sel; 2058 int ret = 0; 2059 2060 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 2061 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 2062 if (!is_dbg_port_valid(rtwdev, sel)) 2063 continue; 2064 ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel); 2065 if (ret) { 2066 rtw89_err(rtwdev, 2067 "failed to dump debug port %d\n", sel); 2068 break; 2069 } 2070 } 2071 2072 return ret; 2073 } 2074 2075 static int 2076 rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v) 2077 { 2078 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2079 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2080 2081 if (debugfs_priv->dbgpkg_en.ss_dbg) 2082 rtw89_debug_mac_dump_ss_dbg(rtwdev, m); 2083 if (debugfs_priv->dbgpkg_en.dle_dbg) 2084 rtw89_debug_mac_dump_dle_dbg(rtwdev, m); 2085 if (debugfs_priv->dbgpkg_en.dmac_dbg) 2086 rtw89_debug_mac_dump_dmac_dbg(rtwdev, m); 2087 if (debugfs_priv->dbgpkg_en.cmac_dbg) 2088 rtw89_debug_mac_dump_cmac_dbg(rtwdev, m); 2089 if (debugfs_priv->dbgpkg_en.dbg_port) 2090 rtw89_debug_mac_dump_dbg_port(rtwdev, m); 2091 2092 return 0; 2093 }; 2094 2095 static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev, 2096 const char __user *user_buf, size_t count) 2097 { 2098 char *buf; 2099 u8 *bin; 2100 int num; 2101 int err = 0; 2102 2103 buf = memdup_user(user_buf, count); 2104 if (IS_ERR(buf)) 2105 return buf; 2106 2107 num = count / 2; 2108 bin = kmalloc(num, GFP_KERNEL); 2109 if (!bin) { 2110 err = -EFAULT; 2111 goto out; 2112 } 2113 2114 if (hex2bin(bin, buf, num)) { 2115 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 2116 kfree(bin); 2117 err = -EINVAL; 2118 } 2119 2120 out: 2121 kfree(buf); 2122 2123 return err ? ERR_PTR(err) : bin; 2124 } 2125 2126 static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp, 2127 const char __user *user_buf, 2128 size_t count, loff_t *loff) 2129 { 2130 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 2131 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2132 u8 *h2c; 2133 u16 h2c_len = count / 2; 2134 2135 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 2136 if (IS_ERR(h2c)) 2137 return -EFAULT; 2138 2139 rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 2140 2141 kfree(h2c); 2142 2143 return count; 2144 } 2145 2146 static int 2147 rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v) 2148 { 2149 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2150 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2151 struct rtw89_early_h2c *early_h2c; 2152 int seq = 0; 2153 2154 mutex_lock(&rtwdev->mutex); 2155 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 2156 seq_printf(m, "%d: %*ph\n", ++seq, early_h2c->h2c_len, early_h2c->h2c); 2157 mutex_unlock(&rtwdev->mutex); 2158 2159 return 0; 2160 } 2161 2162 static ssize_t 2163 rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf, 2164 size_t count, loff_t *loff) 2165 { 2166 struct seq_file *m = (struct seq_file *)filp->private_data; 2167 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2168 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2169 struct rtw89_early_h2c *early_h2c; 2170 u8 *h2c; 2171 u16 h2c_len = count / 2; 2172 2173 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 2174 if (IS_ERR(h2c)) 2175 return -EFAULT; 2176 2177 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 2178 kfree(h2c); 2179 rtw89_fw_free_all_early_h2c(rtwdev); 2180 goto out; 2181 } 2182 2183 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL); 2184 if (!early_h2c) { 2185 kfree(h2c); 2186 return -EFAULT; 2187 } 2188 2189 early_h2c->h2c = h2c; 2190 early_h2c->h2c_len = h2c_len; 2191 2192 mutex_lock(&rtwdev->mutex); 2193 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 2194 mutex_unlock(&rtwdev->mutex); 2195 2196 out: 2197 return count; 2198 } 2199 2200 static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v) 2201 { 2202 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2203 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2204 2205 rtw89_btc_dump_info(rtwdev, m); 2206 2207 return 0; 2208 } 2209 2210 static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp, 2211 const char __user *user_buf, 2212 size_t count, loff_t *loff) 2213 { 2214 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 2215 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2216 struct rtw89_btc *btc = &rtwdev->btc; 2217 bool btc_manual; 2218 2219 if (kstrtobool_from_user(user_buf, count, &btc_manual)) 2220 goto out; 2221 2222 btc->ctrl.manual = btc_manual; 2223 out: 2224 return count; 2225 } 2226 2227 static ssize_t rtw89_debug_fw_log_btc_manual_set(struct file *filp, 2228 const char __user *user_buf, 2229 size_t count, loff_t *loff) 2230 { 2231 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 2232 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2233 struct rtw89_fw_info *fw_info = &rtwdev->fw; 2234 bool fw_log_manual; 2235 2236 if (kstrtobool_from_user(user_buf, count, &fw_log_manual)) 2237 goto out; 2238 2239 mutex_lock(&rtwdev->mutex); 2240 fw_info->fw_log_enable = fw_log_manual; 2241 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 2242 mutex_unlock(&rtwdev->mutex); 2243 out: 2244 return count; 2245 } 2246 2247 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 2248 { 2249 static const char * const he_gi_str[] = { 2250 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 2251 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 2252 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 2253 }; 2254 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2255 struct rate_info *rate = &rtwsta->ra_report.txrate; 2256 struct ieee80211_rx_status *status = &rtwsta->rx_status; 2257 struct seq_file *m = (struct seq_file *)data; 2258 u8 rssi; 2259 2260 seq_printf(m, "TX rate [%d]: ", rtwsta->mac_id); 2261 2262 if (rate->flags & RATE_INFO_FLAGS_MCS) 2263 seq_printf(m, "HT MCS-%d%s", rate->mcs, 2264 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 2265 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 2266 seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs, 2267 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 2268 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 2269 seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs, 2270 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 2271 he_gi_str[rate->he_gi] : "N/A"); 2272 else 2273 seq_printf(m, "Legacy %d", rate->legacy); 2274 seq_printf(m, "\t(hw_rate=0x%x)", rtwsta->ra_report.hw_rate); 2275 seq_printf(m, "\t==> agg_wait=%d (%d)\n", rtwsta->max_agg_wait, 2276 sta->max_rc_amsdu_len); 2277 2278 seq_printf(m, "RX rate [%d]: ", rtwsta->mac_id); 2279 2280 switch (status->encoding) { 2281 case RX_ENC_LEGACY: 2282 seq_printf(m, "Legacy %d", status->rate_idx + 2283 (status->band == NL80211_BAND_5GHZ ? 4 : 0)); 2284 break; 2285 case RX_ENC_HT: 2286 seq_printf(m, "HT MCS-%d%s", status->rate_idx, 2287 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 2288 break; 2289 case RX_ENC_VHT: 2290 seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx, 2291 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 2292 break; 2293 case RX_ENC_HE: 2294 seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx, 2295 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 2296 he_gi_str[rate->he_gi] : "N/A"); 2297 break; 2298 } 2299 seq_printf(m, "\t(hw_rate=0x%x)\n", rtwsta->rx_hw_rate); 2300 2301 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 2302 seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d)\n", 2303 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta->prev_rssi); 2304 } 2305 2306 static void 2307 rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat, 2308 enum rtw89_hw_rate first_rate, int len) 2309 { 2310 int i; 2311 2312 for (i = 0; i < len; i++) 2313 seq_printf(m, "%s%u", i == 0 ? "" : ", ", 2314 pkt_stat->rx_rate_cnt[first_rate + i]); 2315 } 2316 2317 static const struct rtw89_rx_rate_cnt_info { 2318 enum rtw89_hw_rate first_rate; 2319 int len; 2320 const char *rate_mode; 2321 } rtw89_rx_rate_cnt_infos[] = { 2322 {RTW89_HW_RATE_CCK1, 4, "Legacy:"}, 2323 {RTW89_HW_RATE_OFDM6, 8, "OFDM:"}, 2324 {RTW89_HW_RATE_MCS0, 8, "HT 0:"}, 2325 {RTW89_HW_RATE_MCS8, 8, "HT 1:"}, 2326 {RTW89_HW_RATE_VHT_NSS1_MCS0, 10, "VHT 1SS:"}, 2327 {RTW89_HW_RATE_VHT_NSS2_MCS0, 10, "VHT 2SS:"}, 2328 {RTW89_HW_RATE_HE_NSS1_MCS0, 12, "HE 1SS:"}, 2329 {RTW89_HW_RATE_HE_NSS2_MCS0, 12, "HE 2ss:"}, 2330 }; 2331 2332 static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v) 2333 { 2334 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2335 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2336 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2337 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 2338 const struct rtw89_rx_rate_cnt_info *info; 2339 int i; 2340 2341 seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d), RX: %u [%u] Mbps (lv: %d)\n", 2342 stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv, 2343 stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv); 2344 seq_printf(m, "Beacon: %u\n", pkt_stat->beacon_nr); 2345 seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len, 2346 stats->rx_avg_len); 2347 2348 seq_puts(m, "RX count:\n"); 2349 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 2350 info = &rtw89_rx_rate_cnt_infos[i]; 2351 seq_printf(m, "%10s [", info->rate_mode); 2352 rtw89_debug_append_rx_rate(m, pkt_stat, 2353 info->first_rate, info->len); 2354 seq_puts(m, "]\n"); 2355 } 2356 2357 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m); 2358 2359 return 0; 2360 } 2361 2362 static struct rtw89_debugfs_priv rtw89_debug_priv_read_reg = { 2363 .cb_read = rtw89_debug_priv_read_reg_get, 2364 .cb_write = rtw89_debug_priv_read_reg_select, 2365 }; 2366 2367 static struct rtw89_debugfs_priv rtw89_debug_priv_write_reg = { 2368 .cb_write = rtw89_debug_priv_write_reg_set, 2369 }; 2370 2371 static struct rtw89_debugfs_priv rtw89_debug_priv_read_rf = { 2372 .cb_read = rtw89_debug_priv_read_rf_get, 2373 .cb_write = rtw89_debug_priv_read_rf_select, 2374 }; 2375 2376 static struct rtw89_debugfs_priv rtw89_debug_priv_write_rf = { 2377 .cb_write = rtw89_debug_priv_write_rf_set, 2378 }; 2379 2380 static struct rtw89_debugfs_priv rtw89_debug_priv_rf_reg_dump = { 2381 .cb_read = rtw89_debug_priv_rf_reg_dump_get, 2382 }; 2383 2384 static struct rtw89_debugfs_priv rtw89_debug_priv_txpwr_table = { 2385 .cb_read = rtw89_debug_priv_txpwr_table_get, 2386 }; 2387 2388 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_reg_dump = { 2389 .cb_read = rtw89_debug_priv_mac_reg_dump_get, 2390 .cb_write = rtw89_debug_priv_mac_reg_dump_select, 2391 }; 2392 2393 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_mem_dump = { 2394 .cb_read = rtw89_debug_priv_mac_mem_dump_get, 2395 .cb_write = rtw89_debug_priv_mac_mem_dump_select, 2396 }; 2397 2398 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_dbg_port_dump = { 2399 .cb_read = rtw89_debug_priv_mac_dbg_port_dump_get, 2400 .cb_write = rtw89_debug_priv_mac_dbg_port_dump_select, 2401 }; 2402 2403 static struct rtw89_debugfs_priv rtw89_debug_priv_send_h2c = { 2404 .cb_write = rtw89_debug_priv_send_h2c_set, 2405 }; 2406 2407 static struct rtw89_debugfs_priv rtw89_debug_priv_early_h2c = { 2408 .cb_read = rtw89_debug_priv_early_h2c_get, 2409 .cb_write = rtw89_debug_priv_early_h2c_set, 2410 }; 2411 2412 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_info = { 2413 .cb_read = rtw89_debug_priv_btc_info_get, 2414 }; 2415 2416 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_manual = { 2417 .cb_write = rtw89_debug_priv_btc_manual_set, 2418 }; 2419 2420 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_log_manual = { 2421 .cb_write = rtw89_debug_fw_log_btc_manual_set, 2422 }; 2423 2424 static struct rtw89_debugfs_priv rtw89_debug_priv_phy_info = { 2425 .cb_read = rtw89_debug_priv_phy_info_get, 2426 }; 2427 2428 #define rtw89_debugfs_add(name, mode, fopname, parent) \ 2429 do { \ 2430 rtw89_debug_priv_ ##name.rtwdev = rtwdev; \ 2431 if (!debugfs_create_file(#name, mode, \ 2432 parent, &rtw89_debug_priv_ ##name, \ 2433 &file_ops_ ##fopname)) \ 2434 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 2435 } while (0) 2436 2437 #define rtw89_debugfs_add_w(name) \ 2438 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 2439 #define rtw89_debugfs_add_rw(name) \ 2440 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 2441 #define rtw89_debugfs_add_r(name) \ 2442 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 2443 2444 void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 2445 { 2446 struct dentry *debugfs_topdir; 2447 2448 debugfs_topdir = debugfs_create_dir("rtw89", 2449 rtwdev->hw->wiphy->debugfsdir); 2450 2451 rtw89_debugfs_add_rw(read_reg); 2452 rtw89_debugfs_add_w(write_reg); 2453 rtw89_debugfs_add_rw(read_rf); 2454 rtw89_debugfs_add_w(write_rf); 2455 rtw89_debugfs_add_r(rf_reg_dump); 2456 rtw89_debugfs_add_r(txpwr_table); 2457 rtw89_debugfs_add_rw(mac_reg_dump); 2458 rtw89_debugfs_add_rw(mac_mem_dump); 2459 rtw89_debugfs_add_rw(mac_dbg_port_dump); 2460 rtw89_debugfs_add_w(send_h2c); 2461 rtw89_debugfs_add_rw(early_h2c); 2462 rtw89_debugfs_add_r(btc_info); 2463 rtw89_debugfs_add_w(btc_manual); 2464 rtw89_debugfs_add_w(fw_log_manual); 2465 rtw89_debugfs_add_r(phy_info); 2466 } 2467 #endif 2468 2469 #ifdef CONFIG_RTW89_DEBUGMSG 2470 void __rtw89_debug(struct rtw89_dev *rtwdev, 2471 enum rtw89_debug_mask mask, 2472 const char *fmt, ...) 2473 { 2474 struct va_format vaf = { 2475 .fmt = fmt, 2476 }; 2477 2478 va_list args; 2479 2480 va_start(args, fmt); 2481 vaf.va = &args; 2482 2483 if (rtw89_debug_mask & mask) 2484 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 2485 2486 va_end(args); 2487 } 2488 EXPORT_SYMBOL(__rtw89_debug); 2489 #endif 2490