1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 18 extern const struct ieee80211_ops rtw89_ops; 19 20 #define MASKBYTE0 0xff 21 #define MASKBYTE1 0xff00 22 #define MASKBYTE2 0xff0000 23 #define MASKBYTE3 0xff000000 24 #define MASKBYTE4 0xff00000000ULL 25 #define MASKHWORD 0xffff0000 26 #define MASKLWORD 0x0000ffff 27 #define MASKDWORD 0xffffffff 28 #define RFREG_MASK 0xfffff 29 #define INV_RF_DATA 0xffffffff 30 31 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 32 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 33 #define CFO_TRACK_MAX_USER 64 34 #define MAX_RSSI 110 35 #define RSSI_FACTOR 1 36 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 37 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 38 #define RTW89_RADIOTAP_ROOM ALIGN(sizeof(struct ieee80211_radiotap_he), 64) 39 40 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 41 #define RTW89_HTC_VARIANT_HE 3 42 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 43 #define RTW89_HTC_VARIANT_HE_CID_OM 1 44 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 45 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 46 47 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 48 enum htc_om_channel_width { 49 HTC_OM_CHANNEL_WIDTH_20 = 0, 50 HTC_OM_CHANNEL_WIDTH_40 = 1, 51 HTC_OM_CHANNEL_WIDTH_80 = 2, 52 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 53 }; 54 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 55 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 56 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 57 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 58 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 59 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 60 61 #define RTW89_TF_PAD GENMASK(11, 0) 62 #define RTW89_TF_BASIC_USER_INFO_SZ 6 63 64 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 65 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 66 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 67 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 68 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 69 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 70 71 enum rtw89_subband { 72 RTW89_CH_2G = 0, 73 RTW89_CH_5G_BAND_1 = 1, 74 /* RTW89_CH_5G_BAND_2 = 2, unused */ 75 RTW89_CH_5G_BAND_3 = 3, 76 RTW89_CH_5G_BAND_4 = 4, 77 78 RTW89_CH_6G_BAND_IDX0, /* Low */ 79 RTW89_CH_6G_BAND_IDX1, /* Low */ 80 RTW89_CH_6G_BAND_IDX2, /* Mid */ 81 RTW89_CH_6G_BAND_IDX3, /* Mid */ 82 RTW89_CH_6G_BAND_IDX4, /* High */ 83 RTW89_CH_6G_BAND_IDX5, /* High */ 84 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 85 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 86 87 RTW89_SUBBAND_NR, 88 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 89 }; 90 91 enum rtw89_gain_offset { 92 RTW89_GAIN_OFFSET_2G_CCK, 93 RTW89_GAIN_OFFSET_2G_OFDM, 94 RTW89_GAIN_OFFSET_5G_LOW, 95 RTW89_GAIN_OFFSET_5G_MID, 96 RTW89_GAIN_OFFSET_5G_HIGH, 97 98 RTW89_GAIN_OFFSET_NR, 99 }; 100 101 enum rtw89_hci_type { 102 RTW89_HCI_TYPE_PCIE, 103 RTW89_HCI_TYPE_USB, 104 RTW89_HCI_TYPE_SDIO, 105 }; 106 107 enum rtw89_core_chip_id { 108 RTL8852A, 109 RTL8852B, 110 RTL8852C, 111 RTL8851B, 112 }; 113 114 enum rtw89_cv { 115 CHIP_CAV, 116 CHIP_CBV, 117 CHIP_CCV, 118 CHIP_CDV, 119 CHIP_CEV, 120 CHIP_CFV, 121 CHIP_CV_MAX, 122 CHIP_CV_INVALID = CHIP_CV_MAX, 123 }; 124 125 enum rtw89_bacam_ver { 126 RTW89_BACAM_V0, 127 RTW89_BACAM_V1, 128 129 RTW89_BACAM_V0_EXT = 99, 130 }; 131 132 enum rtw89_core_tx_type { 133 RTW89_CORE_TX_TYPE_DATA, 134 RTW89_CORE_TX_TYPE_MGMT, 135 RTW89_CORE_TX_TYPE_FWCMD, 136 }; 137 138 enum rtw89_core_rx_type { 139 RTW89_CORE_RX_TYPE_WIFI = 0, 140 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 141 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 142 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 143 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 144 RTW89_CORE_RX_TYPE_SS2FW = 5, 145 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 146 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 147 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 148 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 149 RTW89_CORE_RX_TYPE_C2H = 10, 150 RTW89_CORE_RX_TYPE_CSI = 11, 151 RTW89_CORE_RX_TYPE_CQI = 12, 152 RTW89_CORE_RX_TYPE_H2C = 13, 153 RTW89_CORE_RX_TYPE_FWDL = 14, 154 }; 155 156 enum rtw89_txq_flags { 157 RTW89_TXQ_F_AMPDU = 0, 158 RTW89_TXQ_F_BLOCK_BA = 1, 159 RTW89_TXQ_F_FORBID_BA = 2, 160 }; 161 162 enum rtw89_net_type { 163 RTW89_NET_TYPE_NO_LINK = 0, 164 RTW89_NET_TYPE_AD_HOC = 1, 165 RTW89_NET_TYPE_INFRA = 2, 166 RTW89_NET_TYPE_AP_MODE = 3, 167 }; 168 169 enum rtw89_wifi_role { 170 RTW89_WIFI_ROLE_NONE, 171 RTW89_WIFI_ROLE_STATION, 172 RTW89_WIFI_ROLE_AP, 173 RTW89_WIFI_ROLE_AP_VLAN, 174 RTW89_WIFI_ROLE_ADHOC, 175 RTW89_WIFI_ROLE_ADHOC_MASTER, 176 RTW89_WIFI_ROLE_MESH_POINT, 177 RTW89_WIFI_ROLE_MONITOR, 178 RTW89_WIFI_ROLE_P2P_DEVICE, 179 RTW89_WIFI_ROLE_P2P_CLIENT, 180 RTW89_WIFI_ROLE_P2P_GO, 181 RTW89_WIFI_ROLE_NAN, 182 RTW89_WIFI_ROLE_MLME_MAX 183 }; 184 185 enum rtw89_upd_mode { 186 RTW89_ROLE_CREATE, 187 RTW89_ROLE_REMOVE, 188 RTW89_ROLE_TYPE_CHANGE, 189 RTW89_ROLE_INFO_CHANGE, 190 RTW89_ROLE_CON_DISCONN, 191 RTW89_ROLE_BAND_SW, 192 RTW89_ROLE_FW_RESTORE, 193 }; 194 195 enum rtw89_self_role { 196 RTW89_SELF_ROLE_CLIENT, 197 RTW89_SELF_ROLE_AP, 198 RTW89_SELF_ROLE_AP_CLIENT 199 }; 200 201 enum rtw89_msk_sO_el { 202 RTW89_NO_MSK, 203 RTW89_SMA, 204 RTW89_TMA, 205 RTW89_BSSID 206 }; 207 208 enum rtw89_sch_tx_sel { 209 RTW89_SCH_TX_SEL_ALL, 210 RTW89_SCH_TX_SEL_HIQ, 211 RTW89_SCH_TX_SEL_MG0, 212 RTW89_SCH_TX_SEL_MACID, 213 }; 214 215 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 216 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 217 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 218 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 219 */ 220 enum rtw89_add_cam_sec_mode { 221 RTW89_ADDR_CAM_SEC_NONE = 0, 222 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 223 RTW89_ADDR_CAM_SEC_NORMAL = 2, 224 RTW89_ADDR_CAM_SEC_4GROUP = 3, 225 }; 226 227 enum rtw89_sec_key_type { 228 RTW89_SEC_KEY_TYPE_NONE = 0, 229 RTW89_SEC_KEY_TYPE_WEP40 = 1, 230 RTW89_SEC_KEY_TYPE_WEP104 = 2, 231 RTW89_SEC_KEY_TYPE_TKIP = 3, 232 RTW89_SEC_KEY_TYPE_WAPI = 4, 233 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 234 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 235 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 236 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 237 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 238 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 239 }; 240 241 enum rtw89_port { 242 RTW89_PORT_0 = 0, 243 RTW89_PORT_1 = 1, 244 RTW89_PORT_2 = 2, 245 RTW89_PORT_3 = 3, 246 RTW89_PORT_4 = 4, 247 RTW89_PORT_NUM 248 }; 249 250 enum rtw89_band { 251 RTW89_BAND_2G = 0, 252 RTW89_BAND_5G = 1, 253 RTW89_BAND_6G = 2, 254 RTW89_BAND_MAX, 255 }; 256 257 enum rtw89_hw_rate { 258 RTW89_HW_RATE_CCK1 = 0x0, 259 RTW89_HW_RATE_CCK2 = 0x1, 260 RTW89_HW_RATE_CCK5_5 = 0x2, 261 RTW89_HW_RATE_CCK11 = 0x3, 262 RTW89_HW_RATE_OFDM6 = 0x4, 263 RTW89_HW_RATE_OFDM9 = 0x5, 264 RTW89_HW_RATE_OFDM12 = 0x6, 265 RTW89_HW_RATE_OFDM18 = 0x7, 266 RTW89_HW_RATE_OFDM24 = 0x8, 267 RTW89_HW_RATE_OFDM36 = 0x9, 268 RTW89_HW_RATE_OFDM48 = 0xA, 269 RTW89_HW_RATE_OFDM54 = 0xB, 270 RTW89_HW_RATE_MCS0 = 0x80, 271 RTW89_HW_RATE_MCS1 = 0x81, 272 RTW89_HW_RATE_MCS2 = 0x82, 273 RTW89_HW_RATE_MCS3 = 0x83, 274 RTW89_HW_RATE_MCS4 = 0x84, 275 RTW89_HW_RATE_MCS5 = 0x85, 276 RTW89_HW_RATE_MCS6 = 0x86, 277 RTW89_HW_RATE_MCS7 = 0x87, 278 RTW89_HW_RATE_MCS8 = 0x88, 279 RTW89_HW_RATE_MCS9 = 0x89, 280 RTW89_HW_RATE_MCS10 = 0x8A, 281 RTW89_HW_RATE_MCS11 = 0x8B, 282 RTW89_HW_RATE_MCS12 = 0x8C, 283 RTW89_HW_RATE_MCS13 = 0x8D, 284 RTW89_HW_RATE_MCS14 = 0x8E, 285 RTW89_HW_RATE_MCS15 = 0x8F, 286 RTW89_HW_RATE_MCS16 = 0x90, 287 RTW89_HW_RATE_MCS17 = 0x91, 288 RTW89_HW_RATE_MCS18 = 0x92, 289 RTW89_HW_RATE_MCS19 = 0x93, 290 RTW89_HW_RATE_MCS20 = 0x94, 291 RTW89_HW_RATE_MCS21 = 0x95, 292 RTW89_HW_RATE_MCS22 = 0x96, 293 RTW89_HW_RATE_MCS23 = 0x97, 294 RTW89_HW_RATE_MCS24 = 0x98, 295 RTW89_HW_RATE_MCS25 = 0x99, 296 RTW89_HW_RATE_MCS26 = 0x9A, 297 RTW89_HW_RATE_MCS27 = 0x9B, 298 RTW89_HW_RATE_MCS28 = 0x9C, 299 RTW89_HW_RATE_MCS29 = 0x9D, 300 RTW89_HW_RATE_MCS30 = 0x9E, 301 RTW89_HW_RATE_MCS31 = 0x9F, 302 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 303 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 304 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 305 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 306 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 307 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 308 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 309 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 310 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 311 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 312 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 313 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 314 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 315 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 316 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 317 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 318 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 319 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 320 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 321 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 322 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 323 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 324 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 325 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 326 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 327 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 328 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 329 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 330 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 331 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 332 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 333 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 334 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 335 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 336 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 337 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 338 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 339 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 340 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 341 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 342 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 343 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 344 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 345 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 346 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 347 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 348 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 349 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 350 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 351 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 352 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 353 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 354 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 355 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 356 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 357 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 358 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 359 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 360 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 361 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 362 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 363 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 364 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 365 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 366 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 367 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 368 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 369 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 370 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 371 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 372 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 373 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 374 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 375 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 376 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 377 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 378 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 379 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 380 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 381 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 382 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 383 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 384 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 385 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 386 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 387 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 388 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 389 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 390 RTW89_HW_RATE_NR, 391 392 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 393 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 394 }; 395 396 /* 2G channels, 397 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 398 */ 399 #define RTW89_2G_CH_NUM 14 400 401 /* 5G channels, 402 * 36, 38, 40, 42, 44, 46, 48, 50, 403 * 52, 54, 56, 58, 60, 62, 64, 404 * 100, 102, 104, 106, 108, 110, 112, 114, 405 * 116, 118, 120, 122, 124, 126, 128, 130, 406 * 132, 134, 136, 138, 140, 142, 144, 407 * 149, 151, 153, 155, 157, 159, 161, 163, 408 * 165, 167, 169, 171, 173, 175, 177 409 */ 410 #define RTW89_5G_CH_NUM 53 411 412 /* 6G channels, 413 * 1, 3, 5, 7, 9, 11, 13, 15, 414 * 17, 19, 21, 23, 25, 27, 29, 33, 415 * 35, 37, 39, 41, 43, 45, 47, 49, 416 * 51, 53, 55, 57, 59, 61, 65, 67, 417 * 69, 71, 73, 75, 77, 79, 81, 83, 418 * 85, 87, 89, 91, 93, 97, 99, 101, 419 * 103, 105, 107, 109, 111, 113, 115, 117, 420 * 119, 121, 123, 125, 129, 131, 133, 135, 421 * 137, 139, 141, 143, 145, 147, 149, 151, 422 * 153, 155, 157, 161, 163, 165, 167, 169, 423 * 171, 173, 175, 177, 179, 181, 183, 185, 424 * 187, 189, 193, 195, 197, 199, 201, 203, 425 * 205, 207, 209, 211, 213, 215, 217, 219, 426 * 221, 225, 227, 229, 231, 233, 235, 237, 427 * 239, 241, 243, 245, 247, 249, 251, 253, 428 */ 429 #define RTW89_6G_CH_NUM 120 430 431 enum rtw89_rate_section { 432 RTW89_RS_CCK, 433 RTW89_RS_OFDM, 434 RTW89_RS_MCS, /* for HT/VHT/HE */ 435 RTW89_RS_HEDCM, 436 RTW89_RS_OFFSET, 437 RTW89_RS_MAX, 438 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 439 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 440 }; 441 442 enum rtw89_rate_max { 443 RTW89_RATE_CCK_MAX = 4, 444 RTW89_RATE_OFDM_MAX = 8, 445 RTW89_RATE_MCS_MAX = 12, 446 RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */ 447 RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */ 448 }; 449 450 enum rtw89_nss { 451 RTW89_NSS_1 = 0, 452 RTW89_NSS_2 = 1, 453 /* HE DCM only support 1ss and 2ss */ 454 RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1, 455 RTW89_NSS_3 = 2, 456 RTW89_NSS_4 = 3, 457 RTW89_NSS_MAX, 458 }; 459 460 enum rtw89_ntx { 461 RTW89_1TX = 0, 462 RTW89_2TX = 1, 463 RTW89_NTX_NUM, 464 }; 465 466 enum rtw89_beamforming_type { 467 RTW89_NONBF = 0, 468 RTW89_BF = 1, 469 RTW89_BF_NUM, 470 }; 471 472 enum rtw89_regulation_type { 473 RTW89_WW = 0, 474 RTW89_ETSI = 1, 475 RTW89_FCC = 2, 476 RTW89_MKK = 3, 477 RTW89_NA = 4, 478 RTW89_IC = 5, 479 RTW89_KCC = 6, 480 RTW89_ACMA = 7, 481 RTW89_NCC = 8, 482 RTW89_MEXICO = 9, 483 RTW89_CHILE = 10, 484 RTW89_UKRAINE = 11, 485 RTW89_CN = 12, 486 RTW89_QATAR = 13, 487 RTW89_UK = 14, 488 RTW89_REGD_NUM, 489 }; 490 491 enum rtw89_fw_pkt_ofld_type { 492 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 493 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 494 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 495 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 496 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 497 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 498 RTW89_PKT_OFLD_TYPE_NDP = 6, 499 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 500 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 501 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 502 RTW89_PKT_OFLD_TYPE_NUM, 503 }; 504 505 struct rtw89_txpwr_byrate { 506 s8 cck[RTW89_RATE_CCK_MAX]; 507 s8 ofdm[RTW89_RATE_OFDM_MAX]; 508 s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX]; 509 s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX]; 510 s8 offset[RTW89_RATE_OFFSET_MAX]; 511 }; 512 513 enum rtw89_bandwidth_section_num { 514 RTW89_BW20_SEC_NUM = 8, 515 RTW89_BW40_SEC_NUM = 4, 516 RTW89_BW80_SEC_NUM = 2, 517 }; 518 519 #define RTW89_TXPWR_LMT_PAGE_SIZE 40 520 521 struct rtw89_txpwr_limit { 522 s8 cck_20m[RTW89_BF_NUM]; 523 s8 cck_40m[RTW89_BF_NUM]; 524 s8 ofdm[RTW89_BF_NUM]; 525 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM]; 526 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM]; 527 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM]; 528 s8 mcs_160m[RTW89_BF_NUM]; 529 s8 mcs_40m_0p5[RTW89_BF_NUM]; 530 s8 mcs_40m_2p5[RTW89_BF_NUM]; 531 }; 532 533 #define RTW89_RU_SEC_NUM 8 534 535 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE 24 536 537 struct rtw89_txpwr_limit_ru { 538 s8 ru26[RTW89_RU_SEC_NUM]; 539 s8 ru52[RTW89_RU_SEC_NUM]; 540 s8 ru106[RTW89_RU_SEC_NUM]; 541 }; 542 543 struct rtw89_rate_desc { 544 enum rtw89_nss nss; 545 enum rtw89_rate_section rs; 546 u8 idx; 547 }; 548 549 #define PHY_STS_HDR_LEN 8 550 #define RF_PATH_MAX 4 551 #define RTW89_MAX_PPDU_CNT 8 552 struct rtw89_rx_phy_ppdu { 553 u8 *buf; 554 u32 len; 555 u8 rssi_avg; 556 u8 rssi[RF_PATH_MAX]; 557 u8 mac_id; 558 u8 chan_idx; 559 u8 ie; 560 u16 rate; 561 struct { 562 bool has; 563 u8 avg_snr; 564 u8 evm_max; 565 u8 evm_min; 566 } ofdm; 567 bool to_self; 568 bool valid; 569 }; 570 571 enum rtw89_mac_idx { 572 RTW89_MAC_0 = 0, 573 RTW89_MAC_1 = 1, 574 }; 575 576 enum rtw89_phy_idx { 577 RTW89_PHY_0 = 0, 578 RTW89_PHY_1 = 1, 579 RTW89_PHY_MAX 580 }; 581 582 enum rtw89_sub_entity_idx { 583 RTW89_SUB_ENTITY_0 = 0, 584 585 NUM_OF_RTW89_SUB_ENTITY, 586 RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY, 587 }; 588 589 enum rtw89_rf_path { 590 RF_PATH_A = 0, 591 RF_PATH_B = 1, 592 RF_PATH_C = 2, 593 RF_PATH_D = 3, 594 RF_PATH_AB, 595 RF_PATH_AC, 596 RF_PATH_AD, 597 RF_PATH_BC, 598 RF_PATH_BD, 599 RF_PATH_CD, 600 RF_PATH_ABC, 601 RF_PATH_ABD, 602 RF_PATH_ACD, 603 RF_PATH_BCD, 604 RF_PATH_ABCD, 605 }; 606 607 enum rtw89_rf_path_bit { 608 RF_A = BIT(0), 609 RF_B = BIT(1), 610 RF_C = BIT(2), 611 RF_D = BIT(3), 612 613 RF_AB = (RF_A | RF_B), 614 RF_AC = (RF_A | RF_C), 615 RF_AD = (RF_A | RF_D), 616 RF_BC = (RF_B | RF_C), 617 RF_BD = (RF_B | RF_D), 618 RF_CD = (RF_C | RF_D), 619 620 RF_ABC = (RF_A | RF_B | RF_C), 621 RF_ABD = (RF_A | RF_B | RF_D), 622 RF_ACD = (RF_A | RF_C | RF_D), 623 RF_BCD = (RF_B | RF_C | RF_D), 624 625 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 626 }; 627 628 enum rtw89_bandwidth { 629 RTW89_CHANNEL_WIDTH_20 = 0, 630 RTW89_CHANNEL_WIDTH_40 = 1, 631 RTW89_CHANNEL_WIDTH_80 = 2, 632 RTW89_CHANNEL_WIDTH_160 = 3, 633 RTW89_CHANNEL_WIDTH_80_80 = 4, 634 RTW89_CHANNEL_WIDTH_5 = 5, 635 RTW89_CHANNEL_WIDTH_10 = 6, 636 }; 637 638 enum rtw89_ps_mode { 639 RTW89_PS_MODE_NONE = 0, 640 RTW89_PS_MODE_RFOFF = 1, 641 RTW89_PS_MODE_CLK_GATED = 2, 642 RTW89_PS_MODE_PWR_GATED = 3, 643 }; 644 645 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 646 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 647 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 648 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 649 650 enum rtw89_ru_bandwidth { 651 RTW89_RU26 = 0, 652 RTW89_RU52 = 1, 653 RTW89_RU106 = 2, 654 RTW89_RU_NUM, 655 }; 656 657 enum rtw89_sc_offset { 658 RTW89_SC_DONT_CARE = 0, 659 RTW89_SC_20_UPPER = 1, 660 RTW89_SC_20_LOWER = 2, 661 RTW89_SC_20_UPMOST = 3, 662 RTW89_SC_20_LOWEST = 4, 663 RTW89_SC_20_UP2X = 5, 664 RTW89_SC_20_LOW2X = 6, 665 RTW89_SC_20_UP3X = 7, 666 RTW89_SC_20_LOW3X = 8, 667 RTW89_SC_40_UPPER = 9, 668 RTW89_SC_40_LOWER = 10, 669 }; 670 671 enum rtw89_wow_flags { 672 RTW89_WOW_FLAG_EN_MAGIC_PKT, 673 RTW89_WOW_FLAG_EN_REKEY_PKT, 674 RTW89_WOW_FLAG_EN_DISCONNECT, 675 RTW89_WOW_FLAG_NUM, 676 }; 677 678 struct rtw89_chan { 679 u8 channel; 680 u8 primary_channel; 681 enum rtw89_band band_type; 682 enum rtw89_bandwidth band_width; 683 684 /* The follow-up are derived from the above. We must ensure that it 685 * is assigned correctly in rtw89_chan_create() if new one is added. 686 */ 687 u32 freq; 688 enum rtw89_subband subband_type; 689 enum rtw89_sc_offset pri_ch_idx; 690 }; 691 692 struct rtw89_chan_rcd { 693 u8 prev_primary_channel; 694 enum rtw89_band prev_band_type; 695 }; 696 697 struct rtw89_channel_help_params { 698 u32 tx_en; 699 }; 700 701 struct rtw89_port_reg { 702 u32 port_cfg; 703 u32 tbtt_prohib; 704 u32 bcn_area; 705 u32 bcn_early; 706 u32 tbtt_early; 707 u32 tbtt_agg; 708 u32 bcn_space; 709 u32 bcn_forcetx; 710 u32 bcn_err_cnt; 711 u32 bcn_err_flag; 712 u32 dtim_ctrl; 713 u32 tbtt_shift; 714 u32 bcn_cnt_tmr; 715 u32 tsftr_l; 716 u32 tsftr_h; 717 }; 718 719 struct rtw89_txwd_body { 720 __le32 dword0; 721 __le32 dword1; 722 __le32 dword2; 723 __le32 dword3; 724 __le32 dword4; 725 __le32 dword5; 726 } __packed; 727 728 struct rtw89_txwd_body_v1 { 729 __le32 dword0; 730 __le32 dword1; 731 __le32 dword2; 732 __le32 dword3; 733 __le32 dword4; 734 __le32 dword5; 735 __le32 dword6; 736 __le32 dword7; 737 } __packed; 738 739 struct rtw89_txwd_info { 740 __le32 dword0; 741 __le32 dword1; 742 __le32 dword2; 743 __le32 dword3; 744 __le32 dword4; 745 __le32 dword5; 746 } __packed; 747 748 struct rtw89_rx_desc_info { 749 u16 pkt_size; 750 u8 pkt_type; 751 u8 drv_info_size; 752 u8 shift; 753 u8 wl_hd_iv_len; 754 bool long_rxdesc; 755 bool bb_sel; 756 bool mac_info_valid; 757 u16 data_rate; 758 u8 gi_ltf; 759 u8 bw; 760 u32 free_run_cnt; 761 u8 user_id; 762 bool sr_en; 763 u8 ppdu_cnt; 764 u8 ppdu_type; 765 bool icv_err; 766 bool crc32_err; 767 bool hw_dec; 768 bool sw_dec; 769 bool addr1_match; 770 u8 frag; 771 u16 seq; 772 u8 frame_type; 773 u8 rx_pl_id; 774 bool addr_cam_valid; 775 u8 addr_cam_id; 776 u8 sec_cam_id; 777 u8 mac_id; 778 u16 offset; 779 bool ready; 780 }; 781 782 struct rtw89_rxdesc_short { 783 __le32 dword0; 784 __le32 dword1; 785 __le32 dword2; 786 __le32 dword3; 787 } __packed; 788 789 struct rtw89_rxdesc_long { 790 __le32 dword0; 791 __le32 dword1; 792 __le32 dword2; 793 __le32 dword3; 794 __le32 dword4; 795 __le32 dword5; 796 __le32 dword6; 797 __le32 dword7; 798 } __packed; 799 800 struct rtw89_tx_desc_info { 801 u16 pkt_size; 802 u8 wp_offset; 803 u8 mac_id; 804 u8 qsel; 805 u8 ch_dma; 806 u8 hdr_llc_len; 807 bool is_bmc; 808 bool en_wd_info; 809 bool wd_page; 810 bool use_rate; 811 bool dis_data_fb; 812 bool tid_indicate; 813 bool agg_en; 814 bool bk; 815 u8 ampdu_density; 816 u8 ampdu_num; 817 bool sec_en; 818 u8 addr_info_nr; 819 u8 sec_keyid; 820 u8 sec_type; 821 u8 sec_cam_idx; 822 u8 sec_seq[6]; 823 u16 data_rate; 824 u16 data_retry_lowest_rate; 825 bool fw_dl; 826 u16 seq; 827 bool a_ctrl_bsr; 828 u8 hw_ssn_sel; 829 #define RTW89_MGMT_HW_SSN_SEL 1 830 u8 hw_seq_mode; 831 #define RTW89_MGMT_HW_SEQ_MODE 1 832 bool hiq; 833 u8 port; 834 bool er_cap; 835 }; 836 837 struct rtw89_core_tx_request { 838 enum rtw89_core_tx_type tx_type; 839 840 struct sk_buff *skb; 841 struct ieee80211_vif *vif; 842 struct ieee80211_sta *sta; 843 struct rtw89_tx_desc_info desc_info; 844 }; 845 846 struct rtw89_txq { 847 struct list_head list; 848 unsigned long flags; 849 int wait_cnt; 850 }; 851 852 struct rtw89_mac_ax_gnt { 853 u8 gnt_bt_sw_en; 854 u8 gnt_bt; 855 u8 gnt_wl_sw_en; 856 u8 gnt_wl; 857 } __packed; 858 859 #define RTW89_MAC_AX_COEX_GNT_NR 2 860 struct rtw89_mac_ax_coex_gnt { 861 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 862 }; 863 864 enum rtw89_btc_ncnt { 865 BTC_NCNT_POWER_ON = 0x0, 866 BTC_NCNT_POWER_OFF, 867 BTC_NCNT_INIT_COEX, 868 BTC_NCNT_SCAN_START, 869 BTC_NCNT_SCAN_FINISH, 870 BTC_NCNT_SPECIAL_PACKET, 871 BTC_NCNT_SWITCH_BAND, 872 BTC_NCNT_RFK_TIMEOUT, 873 BTC_NCNT_SHOW_COEX_INFO, 874 BTC_NCNT_ROLE_INFO, 875 BTC_NCNT_CONTROL, 876 BTC_NCNT_RADIO_STATE, 877 BTC_NCNT_CUSTOMERIZE, 878 BTC_NCNT_WL_RFK, 879 BTC_NCNT_WL_STA, 880 BTC_NCNT_FWINFO, 881 BTC_NCNT_TIMER, 882 BTC_NCNT_NUM 883 }; 884 885 enum rtw89_btc_btinfo { 886 BTC_BTINFO_L0 = 0, 887 BTC_BTINFO_L1, 888 BTC_BTINFO_L2, 889 BTC_BTINFO_L3, 890 BTC_BTINFO_H0, 891 BTC_BTINFO_H1, 892 BTC_BTINFO_H2, 893 BTC_BTINFO_H3, 894 BTC_BTINFO_MAX 895 }; 896 897 enum rtw89_btc_dcnt { 898 BTC_DCNT_RUN = 0x0, 899 BTC_DCNT_CX_RUNINFO, 900 BTC_DCNT_RPT, 901 BTC_DCNT_RPT_HANG, 902 BTC_DCNT_CYCLE, 903 BTC_DCNT_CYCLE_HANG, 904 BTC_DCNT_W1, 905 BTC_DCNT_W1_HANG, 906 BTC_DCNT_B1, 907 BTC_DCNT_B1_HANG, 908 BTC_DCNT_TDMA_NONSYNC, 909 BTC_DCNT_SLOT_NONSYNC, 910 BTC_DCNT_BTCNT_HANG, 911 BTC_DCNT_WL_SLOT_DRIFT, 912 BTC_DCNT_WL_STA_LAST, 913 BTC_DCNT_BT_SLOT_DRIFT, 914 BTC_DCNT_BT_SLOT_FLOOD, 915 BTC_DCNT_FDDT_TRIG, 916 BTC_DCNT_E2G, 917 BTC_DCNT_E2G_HANG, 918 BTC_DCNT_NUM 919 }; 920 921 enum rtw89_btc_wl_state_cnt { 922 BTC_WCNT_SCANAP = 0x0, 923 BTC_WCNT_DHCP, 924 BTC_WCNT_EAPOL, 925 BTC_WCNT_ARP, 926 BTC_WCNT_SCBDUPDATE, 927 BTC_WCNT_RFK_REQ, 928 BTC_WCNT_RFK_GO, 929 BTC_WCNT_RFK_REJECT, 930 BTC_WCNT_RFK_TIMEOUT, 931 BTC_WCNT_CH_UPDATE, 932 BTC_WCNT_NUM 933 }; 934 935 enum rtw89_btc_bt_state_cnt { 936 BTC_BCNT_RETRY = 0x0, 937 BTC_BCNT_REINIT, 938 BTC_BCNT_REENABLE, 939 BTC_BCNT_SCBDREAD, 940 BTC_BCNT_RELINK, 941 BTC_BCNT_IGNOWL, 942 BTC_BCNT_INQPAG, 943 BTC_BCNT_INQ, 944 BTC_BCNT_PAGE, 945 BTC_BCNT_ROLESW, 946 BTC_BCNT_AFH, 947 BTC_BCNT_INFOUPDATE, 948 BTC_BCNT_INFOSAME, 949 BTC_BCNT_SCBDUPDATE, 950 BTC_BCNT_HIPRI_TX, 951 BTC_BCNT_HIPRI_RX, 952 BTC_BCNT_LOPRI_TX, 953 BTC_BCNT_LOPRI_RX, 954 BTC_BCNT_POLUT, 955 BTC_BCNT_RATECHG, 956 BTC_BCNT_NUM 957 }; 958 959 enum rtw89_btc_bt_profile { 960 BTC_BT_NOPROFILE = 0, 961 BTC_BT_HFP = BIT(0), 962 BTC_BT_HID = BIT(1), 963 BTC_BT_A2DP = BIT(2), 964 BTC_BT_PAN = BIT(3), 965 BTC_PROFILE_MAX = 4, 966 }; 967 968 struct rtw89_btc_ant_info { 969 u8 type; /* shared, dedicated */ 970 u8 num; 971 u8 isolation; 972 973 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 974 u8 diversity: 1; 975 u8 btg_pos: 2; 976 u8 stream_cnt: 4; 977 }; 978 979 enum rtw89_tfc_dir { 980 RTW89_TFC_UL, 981 RTW89_TFC_DL, 982 }; 983 984 struct rtw89_btc_wl_smap { 985 u32 busy: 1; 986 u32 scan: 1; 987 u32 connecting: 1; 988 u32 roaming: 1; 989 u32 _4way: 1; 990 u32 rf_off: 1; 991 u32 lps: 2; 992 u32 ips: 1; 993 u32 init_ok: 1; 994 u32 traffic_dir : 2; 995 u32 rf_off_pre: 1; 996 u32 lps_pre: 2; 997 }; 998 999 enum rtw89_tfc_lv { 1000 RTW89_TFC_IDLE, 1001 RTW89_TFC_ULTRA_LOW, 1002 RTW89_TFC_LOW, 1003 RTW89_TFC_MID, 1004 RTW89_TFC_HIGH, 1005 }; 1006 1007 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1008 DECLARE_EWMA(tp, 10, 2); 1009 1010 struct rtw89_traffic_stats { 1011 /* units in bytes */ 1012 u64 tx_unicast; 1013 u64 rx_unicast; 1014 u32 tx_avg_len; 1015 u32 rx_avg_len; 1016 1017 /* count for packets */ 1018 u64 tx_cnt; 1019 u64 rx_cnt; 1020 1021 /* units in Mbps */ 1022 u32 tx_throughput; 1023 u32 rx_throughput; 1024 u32 tx_throughput_raw; 1025 u32 rx_throughput_raw; 1026 1027 u32 rx_tf_acc; 1028 u32 rx_tf_periodic; 1029 1030 enum rtw89_tfc_lv tx_tfc_lv; 1031 enum rtw89_tfc_lv rx_tfc_lv; 1032 struct ewma_tp tx_ewma_tp; 1033 struct ewma_tp rx_ewma_tp; 1034 1035 u16 tx_rate; 1036 u16 rx_rate; 1037 }; 1038 1039 struct rtw89_btc_statistic { 1040 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1041 struct rtw89_traffic_stats traffic; 1042 }; 1043 1044 #define BTC_WL_RSSI_THMAX 4 1045 1046 struct rtw89_btc_wl_link_info { 1047 struct rtw89_btc_statistic stat; 1048 enum rtw89_tfc_dir dir; 1049 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1050 u8 mac_addr[ETH_ALEN]; 1051 u8 busy; 1052 u8 ch; 1053 u8 bw; 1054 u8 band; 1055 u8 role; 1056 u8 pid; 1057 u8 phy; 1058 u8 dtim_period; 1059 u8 mode; 1060 1061 u8 mac_id; 1062 u8 tx_retry; 1063 1064 u32 bcn_period; 1065 u32 busy_t; 1066 u32 tx_time; 1067 u32 client_cnt; 1068 u32 rx_rate_drop_cnt; 1069 1070 u32 active: 1; 1071 u32 noa: 1; 1072 u32 client_ps: 1; 1073 u32 connected: 2; 1074 }; 1075 1076 union rtw89_btc_wl_state_map { 1077 u32 val; 1078 struct rtw89_btc_wl_smap map; 1079 }; 1080 1081 struct rtw89_btc_bt_hfp_desc { 1082 u32 exist: 1; 1083 u32 type: 2; 1084 u32 rsvd: 29; 1085 }; 1086 1087 struct rtw89_btc_bt_hid_desc { 1088 u32 exist: 1; 1089 u32 slot_info: 2; 1090 u32 pair_cnt: 2; 1091 u32 type: 8; 1092 u32 rsvd: 19; 1093 }; 1094 1095 struct rtw89_btc_bt_a2dp_desc { 1096 u8 exist: 1; 1097 u8 exist_last: 1; 1098 u8 play_latency: 1; 1099 u8 type: 3; 1100 u8 active: 1; 1101 u8 sink: 1; 1102 1103 u8 bitpool; 1104 u16 vendor_id; 1105 u32 device_name; 1106 u32 flush_time; 1107 }; 1108 1109 struct rtw89_btc_bt_pan_desc { 1110 u32 exist: 1; 1111 u32 type: 1; 1112 u32 active: 1; 1113 u32 rsvd: 29; 1114 }; 1115 1116 struct rtw89_btc_bt_rfk_info { 1117 u32 run: 1; 1118 u32 req: 1; 1119 u32 timeout: 1; 1120 u32 rsvd: 29; 1121 }; 1122 1123 union rtw89_btc_bt_rfk_info_map { 1124 u32 val; 1125 struct rtw89_btc_bt_rfk_info map; 1126 }; 1127 1128 struct rtw89_btc_bt_ver_info { 1129 u32 fw_coex; /* match with which coex_ver */ 1130 u32 fw; 1131 }; 1132 1133 struct rtw89_btc_bool_sta_chg { 1134 u32 now: 1; 1135 u32 last: 1; 1136 u32 remain: 1; 1137 u32 srvd: 29; 1138 }; 1139 1140 struct rtw89_btc_u8_sta_chg { 1141 u8 now; 1142 u8 last; 1143 u8 remain; 1144 u8 rsvd; 1145 }; 1146 1147 struct rtw89_btc_wl_scan_info { 1148 u8 band[RTW89_PHY_MAX]; 1149 u8 phy_map; 1150 u8 rsvd; 1151 }; 1152 1153 struct rtw89_btc_wl_dbcc_info { 1154 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1155 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1156 u8 real_band[RTW89_PHY_MAX]; 1157 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1158 }; 1159 1160 struct rtw89_btc_wl_active_role { 1161 u8 connected: 1; 1162 u8 pid: 3; 1163 u8 phy: 1; 1164 u8 noa: 1; 1165 u8 band: 2; 1166 1167 u8 client_ps: 1; 1168 u8 bw: 7; 1169 1170 u8 role; 1171 u8 ch; 1172 1173 u16 tx_lvl; 1174 u16 rx_lvl; 1175 u16 tx_rate; 1176 u16 rx_rate; 1177 }; 1178 1179 struct rtw89_btc_wl_active_role_v1 { 1180 u8 connected: 1; 1181 u8 pid: 3; 1182 u8 phy: 1; 1183 u8 noa: 1; 1184 u8 band: 2; 1185 1186 u8 client_ps: 1; 1187 u8 bw: 7; 1188 1189 u8 role; 1190 u8 ch; 1191 1192 u16 tx_lvl; 1193 u16 rx_lvl; 1194 u16 tx_rate; 1195 u16 rx_rate; 1196 1197 u32 noa_duration; /* ms */ 1198 }; 1199 1200 struct rtw89_btc_wl_active_role_v2 { 1201 u8 connected: 1; 1202 u8 pid: 3; 1203 u8 phy: 1; 1204 u8 noa: 1; 1205 u8 band: 2; 1206 1207 u8 client_ps: 1; 1208 u8 bw: 7; 1209 1210 u8 role; 1211 u8 ch; 1212 1213 u32 noa_duration; /* ms */ 1214 }; 1215 1216 struct rtw89_btc_wl_role_info_bpos { 1217 u16 none: 1; 1218 u16 station: 1; 1219 u16 ap: 1; 1220 u16 vap: 1; 1221 u16 adhoc: 1; 1222 u16 adhoc_master: 1; 1223 u16 mesh: 1; 1224 u16 moniter: 1; 1225 u16 p2p_device: 1; 1226 u16 p2p_gc: 1; 1227 u16 p2p_go: 1; 1228 u16 nan: 1; 1229 }; 1230 1231 struct rtw89_btc_wl_scc_ctrl { 1232 u8 null_role1; 1233 u8 null_role2; 1234 u8 ebt_null; /* if tx null at EBT slot */ 1235 }; 1236 1237 union rtw89_btc_wl_role_info_map { 1238 u16 val; 1239 struct rtw89_btc_wl_role_info_bpos role; 1240 }; 1241 1242 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1243 u8 connect_cnt; 1244 u8 link_mode; 1245 union rtw89_btc_wl_role_info_map role_map; 1246 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1247 }; 1248 1249 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1250 u8 connect_cnt; 1251 u8 link_mode; 1252 union rtw89_btc_wl_role_info_map role_map; 1253 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1254 u32 mrole_type; /* btc_wl_mrole_type */ 1255 u32 mrole_noa_duration; /* ms */ 1256 1257 u32 dbcc_en: 1; 1258 u32 dbcc_chg: 1; 1259 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1260 u32 link_mode_chg: 1; 1261 u32 rsvd: 27; 1262 }; 1263 1264 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1265 u8 connect_cnt; 1266 u8 link_mode; 1267 union rtw89_btc_wl_role_info_map role_map; 1268 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1269 u32 mrole_type; /* btc_wl_mrole_type */ 1270 u32 mrole_noa_duration; /* ms */ 1271 1272 u32 dbcc_en: 1; 1273 u32 dbcc_chg: 1; 1274 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1275 u32 link_mode_chg: 1; 1276 u32 rsvd: 27; 1277 }; 1278 1279 struct rtw89_btc_wl_ver_info { 1280 u32 fw_coex; /* match with which coex_ver */ 1281 u32 fw; 1282 u32 mac; 1283 u32 bb; 1284 u32 rf; 1285 }; 1286 1287 struct rtw89_btc_wl_afh_info { 1288 u8 en; 1289 u8 ch; 1290 u8 bw; 1291 u8 rsvd; 1292 } __packed; 1293 1294 struct rtw89_btc_wl_rfk_info { 1295 u32 state: 2; 1296 u32 path_map: 4; 1297 u32 phy_map: 2; 1298 u32 band: 2; 1299 u32 type: 8; 1300 u32 rsvd: 14; 1301 }; 1302 1303 struct rtw89_btc_bt_smap { 1304 u32 connect: 1; 1305 u32 ble_connect: 1; 1306 u32 acl_busy: 1; 1307 u32 sco_busy: 1; 1308 u32 mesh_busy: 1; 1309 u32 inq_pag: 1; 1310 }; 1311 1312 union rtw89_btc_bt_state_map { 1313 u32 val; 1314 struct rtw89_btc_bt_smap map; 1315 }; 1316 1317 #define BTC_BT_RSSI_THMAX 4 1318 #define BTC_BT_AFH_GROUP 12 1319 #define BTC_BT_AFH_LE_GROUP 5 1320 1321 struct rtw89_btc_bt_link_info { 1322 struct rtw89_btc_u8_sta_chg profile_cnt; 1323 struct rtw89_btc_bool_sta_chg multi_link; 1324 struct rtw89_btc_bool_sta_chg relink; 1325 struct rtw89_btc_bt_hfp_desc hfp_desc; 1326 struct rtw89_btc_bt_hid_desc hid_desc; 1327 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1328 struct rtw89_btc_bt_pan_desc pan_desc; 1329 union rtw89_btc_bt_state_map status; 1330 1331 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1332 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1333 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1334 u8 afh_map[BTC_BT_AFH_GROUP]; 1335 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1336 1337 u32 role_sw: 1; 1338 u32 slave_role: 1; 1339 u32 afh_update: 1; 1340 u32 cqddr: 1; 1341 u32 rssi: 8; 1342 u32 tx_3m: 1; 1343 u32 rsvd: 19; 1344 }; 1345 1346 struct rtw89_btc_3rdcx_info { 1347 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1348 u8 hw_coex; 1349 u16 rsvd; 1350 }; 1351 1352 struct rtw89_btc_dm_emap { 1353 u32 init: 1; 1354 u32 pta_owner: 1; 1355 u32 wl_rfk_timeout: 1; 1356 u32 bt_rfk_timeout: 1; 1357 u32 wl_fw_hang: 1; 1358 u32 cycle_hang: 1; 1359 u32 w1_hang: 1; 1360 u32 b1_hang: 1; 1361 u32 tdma_no_sync: 1; 1362 u32 slot_no_sync: 1; 1363 u32 wl_slot_drift: 1; 1364 u32 bt_slot_drift: 1; 1365 u32 role_num_mismatch: 1; 1366 u32 null1_tx_late: 1; 1367 u32 bt_afh_conflict: 1; 1368 u32 bt_leafh_conflict: 1; 1369 u32 bt_slot_flood: 1; 1370 u32 wl_e2g_hang: 1; 1371 u32 wl_ver_mismatch: 1; 1372 u32 bt_ver_mismatch: 1; 1373 }; 1374 1375 union rtw89_btc_dm_error_map { 1376 u32 val; 1377 struct rtw89_btc_dm_emap map; 1378 }; 1379 1380 struct rtw89_btc_rf_para { 1381 u32 tx_pwr_freerun; 1382 u32 rx_gain_freerun; 1383 u32 tx_pwr_perpkt; 1384 u32 rx_gain_perpkt; 1385 }; 1386 1387 struct rtw89_btc_wl_nhm { 1388 u8 instant_wl_nhm_dbm; 1389 u8 instant_wl_nhm_per_mhz; 1390 u16 valid_record_times; 1391 s8 record_pwr[16]; 1392 u8 record_ratio[16]; 1393 s8 pwr; /* dbm_per_MHz */ 1394 u8 ratio; 1395 u8 current_status; 1396 u8 refresh; 1397 bool start_flag; 1398 u8 last_ccx_rpt_stamp; 1399 s8 pwr_max; 1400 s8 pwr_min; 1401 }; 1402 1403 struct rtw89_btc_wl_info { 1404 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1405 struct rtw89_btc_wl_rfk_info rfk_info; 1406 struct rtw89_btc_wl_ver_info ver_info; 1407 struct rtw89_btc_wl_afh_info afh_info; 1408 struct rtw89_btc_wl_role_info role_info; 1409 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1410 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1411 struct rtw89_btc_wl_scan_info scan_info; 1412 struct rtw89_btc_wl_dbcc_info dbcc_info; 1413 struct rtw89_btc_rf_para rf_para; 1414 struct rtw89_btc_wl_nhm nhm; 1415 union rtw89_btc_wl_state_map status; 1416 1417 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1418 u8 rssi_level; 1419 u8 cn_report; 1420 1421 bool scbd_change; 1422 u32 scbd; 1423 }; 1424 1425 struct rtw89_btc_module { 1426 struct rtw89_btc_ant_info ant; 1427 u8 rfe_type; 1428 u8 cv; 1429 1430 u8 bt_solo: 1; 1431 u8 bt_pos: 1; 1432 u8 switch_type: 1; 1433 u8 wa_type: 3; 1434 1435 u8 kt_ver_adie; 1436 }; 1437 1438 #define RTW89_BTC_DM_MAXSTEP 30 1439 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1440 1441 struct rtw89_btc_dm_step { 1442 u16 step[RTW89_BTC_DM_MAXSTEP]; 1443 u8 step_pos; 1444 bool step_ov; 1445 }; 1446 1447 struct rtw89_btc_init_info { 1448 struct rtw89_btc_module module; 1449 u8 wl_guard_ch; 1450 1451 u8 wl_only: 1; 1452 u8 wl_init_ok: 1; 1453 u8 dbcc_en: 1; 1454 u8 cx_other: 1; 1455 u8 bt_only: 1; 1456 1457 u16 rsvd; 1458 }; 1459 1460 struct rtw89_btc_wl_tx_limit_para { 1461 u16 enable; 1462 u32 tx_time; /* unit: us */ 1463 u16 tx_retry; 1464 }; 1465 1466 enum rtw89_btc_bt_scan_type { 1467 BTC_SCAN_INQ = 0, 1468 BTC_SCAN_PAGE, 1469 BTC_SCAN_BLE, 1470 BTC_SCAN_INIT, 1471 BTC_SCAN_TV, 1472 BTC_SCAN_ADV, 1473 BTC_SCAN_MAX1, 1474 }; 1475 1476 enum rtw89_btc_ble_scan_type { 1477 CXSCAN_BG = 0, 1478 CXSCAN_INIT, 1479 CXSCAN_LE, 1480 CXSCAN_MAX 1481 }; 1482 1483 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 1484 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 1485 1486 struct rtw89_btc_bt_scan_info_v1 { 1487 __le16 win; 1488 __le16 intvl; 1489 __le32 flags; 1490 } __packed; 1491 1492 struct rtw89_btc_bt_scan_info_v2 { 1493 __le16 win; 1494 __le16 intvl; 1495 } __packed; 1496 1497 struct rtw89_btc_fbtc_btscan_v1 { 1498 u8 fver; /* btc_ver::fcxbtscan */ 1499 u8 rsvd; 1500 __le16 rsvd2; 1501 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 1502 } __packed; 1503 1504 struct rtw89_btc_fbtc_btscan_v2 { 1505 u8 fver; /* btc_ver::fcxbtscan */ 1506 u8 type; 1507 __le16 rsvd2; 1508 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 1509 } __packed; 1510 1511 union rtw89_btc_fbtc_btscan { 1512 struct rtw89_btc_fbtc_btscan_v1 v1; 1513 struct rtw89_btc_fbtc_btscan_v2 v2; 1514 }; 1515 1516 struct rtw89_btc_bt_info { 1517 struct rtw89_btc_bt_link_info link_info; 1518 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 1519 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 1520 struct rtw89_btc_bt_ver_info ver_info; 1521 struct rtw89_btc_bool_sta_chg enable; 1522 struct rtw89_btc_bool_sta_chg inq_pag; 1523 struct rtw89_btc_rf_para rf_para; 1524 union rtw89_btc_bt_rfk_info_map rfk_info; 1525 1526 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1527 1528 u32 scbd; 1529 u32 feature; 1530 1531 u32 mbx_avl: 1; 1532 u32 whql_test: 1; 1533 u32 igno_wl: 1; 1534 u32 reinit: 1; 1535 u32 ble_scan_en: 1; 1536 u32 btg_type: 1; 1537 u32 inq: 1; 1538 u32 pag: 1; 1539 u32 run_patch_code: 1; 1540 u32 hi_lna_rx: 1; 1541 u32 scan_rx_low_pri: 1; 1542 u32 scan_info_update: 1; 1543 u32 rsvd: 20; 1544 }; 1545 1546 struct rtw89_btc_cx { 1547 struct rtw89_btc_wl_info wl; 1548 struct rtw89_btc_bt_info bt; 1549 struct rtw89_btc_3rdcx_info other; 1550 u32 state_map; 1551 u32 cnt_bt[BTC_BCNT_NUM]; 1552 u32 cnt_wl[BTC_WCNT_NUM]; 1553 }; 1554 1555 struct rtw89_btc_fbtc_tdma { 1556 u8 type; /* btc_ver::fcxtdma */ 1557 u8 rxflctrl; 1558 u8 txpause; 1559 u8 wtgle_n; 1560 u8 leak_n; 1561 u8 ext_ctrl; 1562 u8 rxflctrl_role; 1563 u8 option_ctrl; 1564 } __packed; 1565 1566 struct rtw89_btc_fbtc_tdma_v3 { 1567 u8 fver; /* btc_ver::fcxtdma */ 1568 u8 rsvd; 1569 __le16 rsvd1; 1570 struct rtw89_btc_fbtc_tdma tdma; 1571 } __packed; 1572 1573 union rtw89_btc_fbtc_tdma_le32 { 1574 struct rtw89_btc_fbtc_tdma v1; 1575 struct rtw89_btc_fbtc_tdma_v3 v3; 1576 }; 1577 1578 #define CXMREG_MAX 30 1579 #define CXMREG_MAX_V2 20 1580 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1581 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1582 1583 enum rtw89_btc_bt_sta_counter { 1584 BTC_BCNT_RFK_REQ = 0, 1585 BTC_BCNT_RFK_GO = 1, 1586 BTC_BCNT_RFK_REJECT = 2, 1587 BTC_BCNT_RFK_FAIL = 3, 1588 BTC_BCNT_RFK_TIMEOUT = 4, 1589 BTC_BCNT_HI_TX = 5, 1590 BTC_BCNT_HI_RX = 6, 1591 BTC_BCNT_LO_TX = 7, 1592 BTC_BCNT_LO_RX = 8, 1593 BTC_BCNT_POLLUTED = 9, 1594 BTC_BCNT_STA_MAX 1595 }; 1596 1597 enum rtw89_btc_bt_sta_counter_v105 { 1598 BTC_BCNT_RFK_REQ_V105 = 0, 1599 BTC_BCNT_HI_TX_V105 = 1, 1600 BTC_BCNT_HI_RX_V105 = 2, 1601 BTC_BCNT_LO_TX_V105 = 3, 1602 BTC_BCNT_LO_RX_V105 = 4, 1603 BTC_BCNT_POLLUTED_V105 = 5, 1604 BTC_BCNT_STA_MAX_V105 1605 }; 1606 1607 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 1608 u16 fver; /* btc_ver::fcxbtcrpt */ 1609 u16 rpt_cnt; /* tmr counters */ 1610 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1611 u32 wl_fw_cx_offload; 1612 u32 wl_fw_ver; 1613 u32 rpt_enable; 1614 u32 rpt_para; /* ms */ 1615 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1616 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1617 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1618 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1619 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1620 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1621 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 1622 u32 c2h_cnt; /* fw send c2h counter */ 1623 u32 h2c_cnt; /* fw recv h2c counter */ 1624 } __packed; 1625 1626 struct rtw89_btc_fbtc_rpt_ctrl_info { 1627 __le32 cnt; /* fw report counter */ 1628 __le32 en; /* report map */ 1629 __le32 para; /* not used */ 1630 1631 __le32 cnt_c2h; /* fw send c2h counter */ 1632 __le32 cnt_h2c; /* fw recv h2c counter */ 1633 __le32 len_c2h; /* The total length of the last C2H */ 1634 1635 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1636 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1637 } __packed; 1638 1639 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 1640 __le32 cx_ver; /* match which driver's coex version */ 1641 __le32 fw_ver; 1642 __le32 en; /* report map */ 1643 1644 __le16 cnt; /* fw report counter */ 1645 __le16 cnt_c2h; /* fw send c2h counter */ 1646 __le16 cnt_h2c; /* fw recv h2c counter */ 1647 __le16 len_c2h; /* The total length of the last C2H */ 1648 1649 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1650 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1651 } __packed; 1652 1653 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 1654 __le32 cx_ver; /* match which driver's coex version */ 1655 __le32 cx_offload; 1656 __le32 fw_ver; 1657 } __packed; 1658 1659 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 1660 __le32 cnt_empty; /* a2dp empty count */ 1661 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 1662 __le32 cnt_tx; 1663 __le32 cnt_ack; 1664 __le32 cnt_nack; 1665 } __packed; 1666 1667 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 1668 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 1669 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 1670 __le32 cnt_recv; /* fw recv mailbox counter */ 1671 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 1672 } __packed; 1673 1674 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 1675 u8 fver; 1676 u8 rsvd; 1677 __le16 rsvd1; 1678 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 1679 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 1680 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1681 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 1682 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 1683 } __packed; 1684 1685 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 1686 u8 fver; 1687 u8 rsvd; 1688 __le16 rsvd1; 1689 1690 u8 gnt_val[RTW89_PHY_MAX][4]; 1691 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 1692 1693 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1694 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1695 } __packed; 1696 1697 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 1698 u8 fver; 1699 u8 rsvd; 1700 __le16 rsvd1; 1701 1702 u8 gnt_val[RTW89_PHY_MAX][4]; 1703 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 1704 1705 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1706 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1707 } __packed; 1708 1709 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 1710 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 1711 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 1712 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 1713 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 1714 }; 1715 1716 enum rtw89_fbtc_ext_ctrl_type { 1717 CXECTL_OFF = 0x0, /* tdma off */ 1718 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 1719 CXECTL_EXT = 0x2, 1720 CXECTL_MAX 1721 }; 1722 1723 union rtw89_btc_fbtc_rxflct { 1724 u8 val; 1725 u8 type: 3; 1726 u8 tgln_n: 5; 1727 }; 1728 1729 enum rtw89_btc_cxst_state { 1730 CXST_OFF = 0x0, 1731 CXST_B2W = 0x1, 1732 CXST_W1 = 0x2, 1733 CXST_W2 = 0x3, 1734 CXST_W2B = 0x4, 1735 CXST_B1 = 0x5, 1736 CXST_B2 = 0x6, 1737 CXST_B3 = 0x7, 1738 CXST_B4 = 0x8, 1739 CXST_LK = 0x9, 1740 CXST_BLK = 0xa, 1741 CXST_E2G = 0xb, 1742 CXST_E5G = 0xc, 1743 CXST_EBT = 0xd, 1744 CXST_ENULL = 0xe, 1745 CXST_WLK = 0xf, 1746 CXST_W1FDD = 0x10, 1747 CXST_B1FDD = 0x11, 1748 CXST_MAX = 0x12, 1749 }; 1750 1751 enum rtw89_btc_cxevnt { 1752 CXEVNT_TDMA_ENTRY = 0x0, 1753 CXEVNT_WL_TMR, 1754 CXEVNT_B1_TMR, 1755 CXEVNT_B2_TMR, 1756 CXEVNT_B3_TMR, 1757 CXEVNT_B4_TMR, 1758 CXEVNT_W2B_TMR, 1759 CXEVNT_B2W_TMR, 1760 CXEVNT_BCN_EARLY, 1761 CXEVNT_A2DP_EMPTY, 1762 CXEVNT_LK_END, 1763 CXEVNT_RX_ISR, 1764 CXEVNT_RX_FC0, 1765 CXEVNT_RX_FC1, 1766 CXEVNT_BT_RELINK, 1767 CXEVNT_BT_RETRY, 1768 CXEVNT_E2G, 1769 CXEVNT_E5G, 1770 CXEVNT_EBT, 1771 CXEVNT_ENULL, 1772 CXEVNT_DRV_WLK, 1773 CXEVNT_BCN_OK, 1774 CXEVNT_BT_CHANGE, 1775 CXEVNT_EBT_EXTEND, 1776 CXEVNT_E2G_NULL1, 1777 CXEVNT_B1FDD_TMR, 1778 CXEVNT_MAX 1779 }; 1780 1781 enum { 1782 CXBCN_ALL = 0x0, 1783 CXBCN_ALL_OK, 1784 CXBCN_BT_SLOT, 1785 CXBCN_BT_OK, 1786 CXBCN_MAX 1787 }; 1788 1789 enum btc_slot_type { 1790 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 1791 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 1792 CXSTYPE_NUM, 1793 }; 1794 1795 enum { /* TIME */ 1796 CXT_BT = 0x0, 1797 CXT_WL = 0x1, 1798 CXT_MAX 1799 }; 1800 1801 enum { /* TIME-A2DP */ 1802 CXT_FLCTRL_OFF = 0x0, 1803 CXT_FLCTRL_ON = 0x1, 1804 CXT_FLCTRL_MAX 1805 }; 1806 1807 enum { /* STEP TYPE */ 1808 CXSTEP_NONE = 0x0, 1809 CXSTEP_EVNT = 0x1, 1810 CXSTEP_SLOT = 0x2, 1811 CXSTEP_MAX, 1812 }; 1813 1814 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 1815 RPT_BT_AFH_SEQ_LEGACY = 0x10, 1816 RPT_BT_AFH_SEQ_LE = 0x20 1817 }; 1818 1819 #define BTC_DBG_MAX1 32 1820 struct rtw89_btc_fbtc_gpio_dbg { 1821 u8 fver; /* btc_ver::fcxgpiodbg */ 1822 u8 rsvd; 1823 u16 rsvd2; 1824 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 1825 u32 pre_state; /* the debug signal is 1 or 0 */ 1826 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 1827 } __packed; 1828 1829 struct rtw89_btc_fbtc_mreg_val_v1 { 1830 u8 fver; /* btc_ver::fcxmreg */ 1831 u8 reg_num; 1832 __le16 rsvd; 1833 __le32 mreg_val[CXMREG_MAX]; 1834 } __packed; 1835 1836 struct rtw89_btc_fbtc_mreg_val_v2 { 1837 u8 fver; /* btc_ver::fcxmreg */ 1838 u8 reg_num; 1839 __le16 rsvd; 1840 __le32 mreg_val[CXMREG_MAX_V2]; 1841 } __packed; 1842 1843 union rtw89_btc_fbtc_mreg_val { 1844 struct rtw89_btc_fbtc_mreg_val_v1 v1; 1845 struct rtw89_btc_fbtc_mreg_val_v2 v2; 1846 }; 1847 1848 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 1849 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 1850 .offset = cpu_to_le32(__offset), } 1851 1852 struct rtw89_btc_fbtc_mreg { 1853 __le16 type; 1854 __le16 bytes; 1855 __le32 offset; 1856 } __packed; 1857 1858 struct rtw89_btc_fbtc_slot { 1859 __le16 dur; 1860 __le32 cxtbl; 1861 __le16 cxtype; 1862 } __packed; 1863 1864 struct rtw89_btc_fbtc_slots { 1865 u8 fver; /* btc_ver::fcxslots */ 1866 u8 tbl_num; 1867 __le16 rsvd; 1868 __le32 update_map; 1869 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1870 } __packed; 1871 1872 struct rtw89_btc_fbtc_step { 1873 u8 type; 1874 u8 val; 1875 __le16 difft; 1876 } __packed; 1877 1878 struct rtw89_btc_fbtc_steps_v2 { 1879 u8 fver; /* btc_ver::fcxstep */ 1880 u8 rsvd; 1881 __le16 cnt; 1882 __le16 pos_old; 1883 __le16 pos_new; 1884 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1885 } __packed; 1886 1887 struct rtw89_btc_fbtc_steps_v3 { 1888 u8 fver; 1889 u8 en; 1890 __le16 rsvd; 1891 __le32 cnt; 1892 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1893 } __packed; 1894 1895 union rtw89_btc_fbtc_steps_info { 1896 struct rtw89_btc_fbtc_steps_v2 v2; 1897 struct rtw89_btc_fbtc_steps_v3 v3; 1898 }; 1899 1900 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 1901 u8 fver; /* btc_ver::fcxcysta */ 1902 u8 rsvd; 1903 __le16 cycles; /* total cycle number */ 1904 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 1905 __le16 a2dpept; /* a2dp empty cnt */ 1906 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 1907 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 1908 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 1909 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1910 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 1911 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 1912 __le16 tavg_a2dpept; /* avg a2dp empty time */ 1913 __le16 tmax_a2dpept; /* max a2dp empty time */ 1914 __le16 tavg_lk; /* avg leak-slot time */ 1915 __le16 tmax_lk; /* max leak-slot time */ 1916 __le32 slot_cnt[CXST_MAX]; /* slot count */ 1917 __le32 bcn_cnt[CXBCN_MAX]; 1918 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 1919 __le32 collision_cnt; /* counter for event/timer occur at same time */ 1920 __le32 skip_cnt; 1921 __le32 exception; 1922 __le32 except_cnt; 1923 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 1924 } __packed; 1925 1926 struct rtw89_btc_fbtc_fdd_try_info { 1927 __le16 cycles[CXT_FLCTRL_MAX]; 1928 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 1929 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 1930 } __packed; 1931 1932 struct rtw89_btc_fbtc_cycle_time_info { 1933 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 1934 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 1935 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1936 } __packed; 1937 1938 struct rtw89_btc_fbtc_cycle_time_info_v5 { 1939 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 1940 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 1941 } __packed; 1942 1943 struct rtw89_btc_fbtc_a2dp_trx_stat { 1944 u8 empty_cnt; 1945 u8 retry_cnt; 1946 u8 tx_rate; 1947 u8 tx_cnt; 1948 u8 ack_cnt; 1949 u8 nack_cnt; 1950 u8 rsvd1; 1951 u8 rsvd2; 1952 } __packed; 1953 1954 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 1955 u8 empty_cnt; 1956 u8 retry_cnt; 1957 u8 tx_rate; 1958 u8 tx_cnt; 1959 u8 ack_cnt; 1960 u8 nack_cnt; 1961 u8 no_empty_cnt; 1962 u8 rsvd; 1963 } __packed; 1964 1965 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 1966 __le16 cnt; /* a2dp empty cnt */ 1967 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 1968 __le16 tavg; /* avg a2dp empty time */ 1969 __le16 tmax; /* max a2dp empty time */ 1970 } __packed; 1971 1972 struct rtw89_btc_fbtc_cycle_leak_info { 1973 __le32 cnt_rximr; /* the rximr occur at leak slot */ 1974 __le16 tavg; /* avg leak-slot time */ 1975 __le16 tmax; /* max leak-slot time */ 1976 } __packed; 1977 1978 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 1979 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 1980 1981 struct rtw89_btc_fbtc_cycle_fddt_info { 1982 __le16 train_cycle; 1983 __le16 tp; 1984 1985 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 1986 s8 bt_tx_power; /* decrease Tx power (dB) */ 1987 s8 bt_rx_gain; /* LNA constrain level */ 1988 u8 no_empty_cnt; 1989 1990 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 1991 u8 cn; /* condition_num */ 1992 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 1993 u8 train_result; /* refer to enum btc_fddt_check_map */ 1994 } __packed; 1995 1996 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 1997 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 1998 1999 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2000 __le16 train_cycle; 2001 __le16 tp; 2002 2003 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2004 s8 bt_tx_power; /* decrease Tx power (dB) */ 2005 s8 bt_rx_gain; /* LNA constrain level */ 2006 u8 no_empty_cnt; 2007 2008 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2009 u8 cn; /* condition_num */ 2010 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2011 u8 train_result; /* refer to enum btc_fddt_check_map */ 2012 } __packed; 2013 2014 struct rtw89_btc_fbtc_fddt_cell_status { 2015 s8 wl_tx_pwr; 2016 s8 bt_tx_pwr; 2017 s8 bt_rx_gain; 2018 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2019 } __packed; 2020 2021 struct rtw89_btc_fbtc_fddt_cell_status_v5 { 2022 s8 wl_tx_pwr; 2023 s8 bt_tx_pwr; 2024 s8 bt_rx_gain; 2025 } __packed; 2026 2027 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2028 u8 fver; 2029 u8 rsvd; 2030 __le16 cycles; /* total cycle number */ 2031 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2032 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2033 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2034 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2035 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2036 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2037 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2038 __le32 bcn_cnt[CXBCN_MAX]; 2039 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2040 __le32 skip_cnt; 2041 __le32 except_cnt; 2042 __le32 except_map; 2043 } __packed; 2044 2045 #define FDD_TRAIN_WL_DIRECTION 2 2046 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2047 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2048 2049 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2050 u8 fver; 2051 u8 rsvd; 2052 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2053 u8 except_cnt; 2054 2055 __le16 skip_cnt; 2056 __le16 cycles; /* total cycle number */ 2057 2058 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2059 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2060 __le16 bcn_cnt[CXBCN_MAX]; 2061 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2062 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2063 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2064 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2065 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2066 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2067 [FDD_TRAIN_WL_RSSI_LEVEL] 2068 [FDD_TRAIN_BT_RSSI_LEVEL]; 2069 __le32 except_map; 2070 } __packed; 2071 2072 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2073 u8 fver; 2074 u8 rsvd; 2075 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2076 u8 except_cnt; 2077 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2078 2079 __le16 skip_cnt; 2080 __le16 cycles; /* total cycle number */ 2081 2082 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2083 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2084 __le16 bcn_cnt[CXBCN_MAX]; 2085 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2086 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2087 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2088 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2089 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2090 struct rtw89_btc_fbtc_fddt_cell_status_v5 fddt_cells[FDD_TRAIN_WL_DIRECTION] 2091 [FDD_TRAIN_WL_RSSI_LEVEL] 2092 [FDD_TRAIN_BT_RSSI_LEVEL]; 2093 __le32 except_map; 2094 } __packed; 2095 2096 union rtw89_btc_fbtc_cysta_info { 2097 struct rtw89_btc_fbtc_cysta_v2 v2; 2098 struct rtw89_btc_fbtc_cysta_v3 v3; 2099 struct rtw89_btc_fbtc_cysta_v4 v4; 2100 struct rtw89_btc_fbtc_cysta_v5 v5; 2101 }; 2102 2103 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2104 u8 fver; /* btc_ver::fcxnullsta */ 2105 u8 rsvd; 2106 __le16 rsvd2; 2107 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2108 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2109 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2110 } __packed; 2111 2112 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2113 u8 fver; /* btc_ver::fcxnullsta */ 2114 u8 rsvd; 2115 __le16 rsvd2; 2116 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2117 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2118 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2119 } __packed; 2120 2121 union rtw89_btc_fbtc_cynullsta_info { 2122 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2123 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2124 }; 2125 2126 struct rtw89_btc_fbtc_btver { 2127 u8 fver; /* btc_ver::fcxbtver */ 2128 u8 rsvd; 2129 __le16 rsvd2; 2130 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2131 __le32 fw_ver; 2132 __le32 feature; 2133 } __packed; 2134 2135 struct rtw89_btc_fbtc_btafh { 2136 u8 fver; /* btc_ver::fcxbtafh */ 2137 u8 rsvd; 2138 __le16 rsvd2; 2139 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2140 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2141 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2142 } __packed; 2143 2144 struct rtw89_btc_fbtc_btafh_v2 { 2145 u8 fver; /* btc_ver::fcxbtafh */ 2146 u8 rsvd; 2147 u8 rsvd2; 2148 u8 map_type; 2149 u8 afh_l[4]; 2150 u8 afh_m[4]; 2151 u8 afh_h[4]; 2152 u8 afh_le_a[4]; 2153 u8 afh_le_b[4]; 2154 } __packed; 2155 2156 struct rtw89_btc_fbtc_btdevinfo { 2157 u8 fver; /* btc_ver::fcxbtdevinfo */ 2158 u8 rsvd; 2159 __le16 vendor_id; 2160 __le32 dev_name; /* only 24 bits valid */ 2161 __le32 flush_time; 2162 } __packed; 2163 2164 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2165 struct rtw89_btc_rf_trx_para { 2166 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2167 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2168 u8 bt_tx_power; /* decrease Tx power (dB) */ 2169 u8 bt_rx_gain; /* LNA constrain level */ 2170 }; 2171 2172 struct rtw89_btc_trx_info { 2173 u8 tx_lvl; 2174 u8 rx_lvl; 2175 u8 wl_rssi; 2176 u8 bt_rssi; 2177 2178 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2179 s8 rx_gain; /* rx gain table index (TBD.) */ 2180 s8 bt_tx_power; /* decrease Tx power (dB) */ 2181 s8 bt_rx_gain; /* LNA constrain level */ 2182 2183 u8 cn; /* condition_num */ 2184 s8 nhm; 2185 u8 bt_profile; 2186 u8 rsvd2; 2187 2188 u16 tx_rate; 2189 u16 rx_rate; 2190 2191 u32 tx_tp; 2192 u32 rx_tp; 2193 u32 rx_err_ratio; 2194 }; 2195 2196 struct rtw89_btc_dm { 2197 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2198 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 2199 struct rtw89_btc_fbtc_tdma tdma; 2200 struct rtw89_btc_fbtc_tdma tdma_now; 2201 struct rtw89_mac_ax_coex_gnt gnt; 2202 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 2203 struct rtw89_btc_rf_trx_para rf_trx_para; 2204 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2205 struct rtw89_btc_dm_step dm_step; 2206 struct rtw89_btc_wl_scc_ctrl wl_scc; 2207 struct rtw89_btc_trx_info trx_info; 2208 union rtw89_btc_dm_error_map error; 2209 u32 cnt_dm[BTC_DCNT_NUM]; 2210 u32 cnt_notify[BTC_NCNT_NUM]; 2211 2212 u32 update_slot_map; 2213 u32 set_ant_path; 2214 2215 u32 wl_only: 1; 2216 u32 wl_fw_cx_offload: 1; 2217 u32 freerun: 1; 2218 u32 fddt_train: 1; 2219 u32 wl_ps_ctrl: 2; 2220 u32 wl_mimo_ps: 1; 2221 u32 leak_ap: 1; 2222 u32 noisy_level: 3; 2223 u32 coex_info_map: 8; 2224 u32 bt_only: 1; 2225 u32 wl_btg_rx: 1; 2226 u32 trx_para_level: 8; 2227 u32 wl_stb_chg: 1; 2228 u32 pta_owner: 1; 2229 u32 tdma_instant_excute: 1; 2230 2231 u16 slot_dur[CXST_MAX]; 2232 2233 u8 run_reason; 2234 u8 run_action; 2235 2236 u8 wl_lna2: 1; 2237 }; 2238 2239 struct rtw89_btc_ctrl { 2240 u32 manual: 1; 2241 u32 igno_bt: 1; 2242 u32 always_freerun: 1; 2243 u32 trace_step: 16; 2244 u32 rsvd: 12; 2245 }; 2246 2247 struct rtw89_btc_dbg { 2248 /* cmd "rb" */ 2249 bool rb_done; 2250 u32 rb_val; 2251 }; 2252 2253 enum rtw89_btc_btf_fw_event { 2254 BTF_EVNT_RPT = 0, 2255 BTF_EVNT_BT_INFO = 1, 2256 BTF_EVNT_BT_SCBD = 2, 2257 BTF_EVNT_BT_REG = 3, 2258 BTF_EVNT_CX_RUNINFO = 4, 2259 BTF_EVNT_BT_PSD = 5, 2260 BTF_EVNT_BUF_OVERFLOW, 2261 BTF_EVNT_C2H_LOOPBACK, 2262 BTF_EVNT_MAX, 2263 }; 2264 2265 enum btf_fw_event_report { 2266 BTC_RPT_TYPE_CTRL = 0x0, 2267 BTC_RPT_TYPE_TDMA, 2268 BTC_RPT_TYPE_SLOT, 2269 BTC_RPT_TYPE_CYSTA, 2270 BTC_RPT_TYPE_STEP, 2271 BTC_RPT_TYPE_NULLSTA, 2272 BTC_RPT_TYPE_MREG, 2273 BTC_RPT_TYPE_GPIO_DBG, 2274 BTC_RPT_TYPE_BT_VER, 2275 BTC_RPT_TYPE_BT_SCAN, 2276 BTC_RPT_TYPE_BT_AFH, 2277 BTC_RPT_TYPE_BT_DEVICE, 2278 BTC_RPT_TYPE_TEST, 2279 BTC_RPT_TYPE_MAX = 31 2280 }; 2281 2282 enum rtw_btc_btf_reg_type { 2283 REG_MAC = 0x0, 2284 REG_BB = 0x1, 2285 REG_RF = 0x2, 2286 REG_BT_RF = 0x3, 2287 REG_BT_MODEM = 0x4, 2288 REG_BT_BLUEWIZE = 0x5, 2289 REG_BT_VENDOR = 0x6, 2290 REG_BT_LE = 0x7, 2291 REG_MAX_TYPE, 2292 }; 2293 2294 struct rtw89_btc_rpt_cmn_info { 2295 u32 rx_cnt; 2296 u32 rx_len; 2297 u32 req_len; /* expected rsp len */ 2298 u8 req_fver; /* expected rsp fver */ 2299 u8 rsp_fver; /* fver from fw */ 2300 u8 valid; 2301 } __packed; 2302 2303 union rtw89_btc_fbtc_btafh_info { 2304 struct rtw89_btc_fbtc_btafh v1; 2305 struct rtw89_btc_fbtc_btafh_v2 v2; 2306 }; 2307 2308 struct rtw89_btc_report_ctrl_state { 2309 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2310 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 2311 }; 2312 2313 struct rtw89_btc_rpt_fbtc_tdma { 2314 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2315 union rtw89_btc_fbtc_tdma_le32 finfo; 2316 }; 2317 2318 struct rtw89_btc_rpt_fbtc_slots { 2319 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2320 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 2321 }; 2322 2323 struct rtw89_btc_rpt_fbtc_cysta { 2324 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2325 union rtw89_btc_fbtc_cysta_info finfo; 2326 }; 2327 2328 struct rtw89_btc_rpt_fbtc_step { 2329 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2330 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 2331 }; 2332 2333 struct rtw89_btc_rpt_fbtc_nullsta { 2334 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2335 union rtw89_btc_fbtc_cynullsta_info finfo; 2336 }; 2337 2338 struct rtw89_btc_rpt_fbtc_mreg { 2339 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2340 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 2341 }; 2342 2343 struct rtw89_btc_rpt_fbtc_gpio_dbg { 2344 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2345 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 2346 }; 2347 2348 struct rtw89_btc_rpt_fbtc_btver { 2349 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2350 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 2351 }; 2352 2353 struct rtw89_btc_rpt_fbtc_btscan { 2354 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2355 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 2356 }; 2357 2358 struct rtw89_btc_rpt_fbtc_btafh { 2359 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2360 union rtw89_btc_fbtc_btafh_info finfo; 2361 }; 2362 2363 struct rtw89_btc_rpt_fbtc_btdev { 2364 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2365 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 2366 }; 2367 2368 enum rtw89_btc_btfre_type { 2369 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 2370 BTFRE_UNDEF_TYPE, 2371 BTFRE_EXCEPTION, 2372 BTFRE_MAX, 2373 }; 2374 2375 struct rtw89_btc_btf_fwinfo { 2376 u32 cnt_c2h; 2377 u32 cnt_h2c; 2378 u32 cnt_h2c_fail; 2379 u32 event[BTF_EVNT_MAX]; 2380 2381 u32 err[BTFRE_MAX]; 2382 u32 len_mismch; 2383 u32 fver_mismch; 2384 u32 rpt_en_map; 2385 2386 struct rtw89_btc_report_ctrl_state rpt_ctrl; 2387 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 2388 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 2389 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 2390 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 2391 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 2392 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 2393 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 2394 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 2395 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 2396 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 2397 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 2398 }; 2399 2400 struct rtw89_btc_ver { 2401 enum rtw89_core_chip_id chip_id; 2402 u32 fw_ver_code; 2403 2404 u8 fcxbtcrpt; 2405 u8 fcxtdma; 2406 u8 fcxslots; 2407 u8 fcxcysta; 2408 u8 fcxstep; 2409 u8 fcxnullsta; 2410 u8 fcxmreg; 2411 u8 fcxgpiodbg; 2412 u8 fcxbtver; 2413 u8 fcxbtscan; 2414 u8 fcxbtafh; 2415 u8 fcxbtdevinfo; 2416 u8 fwlrole; 2417 u8 frptmap; 2418 u8 fcxctrl; 2419 2420 u16 info_buf; 2421 u8 max_role_num; 2422 }; 2423 2424 #define RTW89_BTC_POLICY_MAXLEN 512 2425 2426 struct rtw89_btc { 2427 const struct rtw89_btc_ver *ver; 2428 2429 struct rtw89_btc_cx cx; 2430 struct rtw89_btc_dm dm; 2431 struct rtw89_btc_ctrl ctrl; 2432 struct rtw89_btc_module mdinfo; 2433 struct rtw89_btc_btf_fwinfo fwinfo; 2434 struct rtw89_btc_dbg dbg; 2435 2436 struct work_struct eapol_notify_work; 2437 struct work_struct arp_notify_work; 2438 struct work_struct dhcp_notify_work; 2439 struct work_struct icmp_notify_work; 2440 2441 u32 bt_req_len; 2442 2443 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 2444 u16 policy_len; 2445 u16 policy_type; 2446 bool bt_req_en; 2447 bool update_policy_force; 2448 bool lps; 2449 }; 2450 2451 enum rtw89_ra_mode { 2452 RTW89_RA_MODE_CCK = BIT(0), 2453 RTW89_RA_MODE_OFDM = BIT(1), 2454 RTW89_RA_MODE_HT = BIT(2), 2455 RTW89_RA_MODE_VHT = BIT(3), 2456 RTW89_RA_MODE_HE = BIT(4), 2457 }; 2458 2459 enum rtw89_ra_report_mode { 2460 RTW89_RA_RPT_MODE_LEGACY, 2461 RTW89_RA_RPT_MODE_HT, 2462 RTW89_RA_RPT_MODE_VHT, 2463 RTW89_RA_RPT_MODE_HE, 2464 }; 2465 2466 enum rtw89_dig_noisy_level { 2467 RTW89_DIG_NOISY_LEVEL0 = -1, 2468 RTW89_DIG_NOISY_LEVEL1 = 0, 2469 RTW89_DIG_NOISY_LEVEL2 = 1, 2470 RTW89_DIG_NOISY_LEVEL3 = 2, 2471 RTW89_DIG_NOISY_LEVEL_MAX = 3, 2472 }; 2473 2474 enum rtw89_gi_ltf { 2475 RTW89_GILTF_LGI_4XHE32 = 0, 2476 RTW89_GILTF_SGI_4XHE08 = 1, 2477 RTW89_GILTF_2XHE16 = 2, 2478 RTW89_GILTF_2XHE08 = 3, 2479 RTW89_GILTF_1XHE16 = 4, 2480 RTW89_GILTF_1XHE08 = 5, 2481 RTW89_GILTF_MAX 2482 }; 2483 2484 enum rtw89_rx_frame_type { 2485 RTW89_RX_TYPE_MGNT = 0, 2486 RTW89_RX_TYPE_CTRL = 1, 2487 RTW89_RX_TYPE_DATA = 2, 2488 RTW89_RX_TYPE_RSVD = 3, 2489 }; 2490 2491 struct rtw89_ra_info { 2492 u8 is_dis_ra:1; 2493 /* Bit0 : CCK 2494 * Bit1 : OFDM 2495 * Bit2 : HT 2496 * Bit3 : VHT 2497 * Bit4 : HE 2498 */ 2499 u8 mode_ctrl:5; 2500 u8 bw_cap:2; 2501 u8 macid; 2502 u8 dcm_cap:1; 2503 u8 er_cap:1; 2504 u8 init_rate_lv:2; 2505 u8 upd_all:1; 2506 u8 en_sgi:1; 2507 u8 ldpc_cap:1; 2508 u8 stbc_cap:1; 2509 u8 ss_num:3; 2510 u8 giltf:3; 2511 u8 upd_bw_nss_mask:1; 2512 u8 upd_mask:1; 2513 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 2514 /* BFee CSI */ 2515 u8 band_num; 2516 u8 ra_csi_rate_en:1; 2517 u8 fixed_csi_rate_en:1; 2518 u8 cr_tbl_sel:1; 2519 u8 fix_giltf_en:1; 2520 u8 fix_giltf:3; 2521 u8 rsvd2:1; 2522 u8 csi_mcs_ss_idx; 2523 u8 csi_mode:2; 2524 u8 csi_gi_ltf:3; 2525 u8 csi_bw:3; 2526 }; 2527 2528 #define RTW89_PPDU_MAX_USR 4 2529 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 2530 #define RTW89_PPDU_MAC_INFO_SIZE 8 2531 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 2532 2533 #define RTW89_MAX_RX_AGG_NUM 64 2534 #define RTW89_MAX_TX_AGG_NUM 128 2535 2536 struct rtw89_ampdu_params { 2537 u16 agg_num; 2538 bool amsdu; 2539 }; 2540 2541 struct rtw89_ra_report { 2542 struct rate_info txrate; 2543 u32 bit_rate; 2544 u16 hw_rate; 2545 bool might_fallback_legacy; 2546 }; 2547 2548 DECLARE_EWMA(rssi, 10, 16); 2549 DECLARE_EWMA(evm, 10, 16); 2550 DECLARE_EWMA(snr, 10, 16); 2551 2552 struct rtw89_ba_cam_entry { 2553 struct list_head list; 2554 u8 tid; 2555 }; 2556 2557 #define RTW89_MAX_ADDR_CAM_NUM 128 2558 #define RTW89_MAX_BSSID_CAM_NUM 20 2559 #define RTW89_MAX_SEC_CAM_NUM 128 2560 #define RTW89_MAX_BA_CAM_NUM 8 2561 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 2562 2563 struct rtw89_addr_cam_entry { 2564 u8 addr_cam_idx; 2565 u8 offset; 2566 u8 len; 2567 u8 valid : 1; 2568 u8 addr_mask : 6; 2569 u8 wapi : 1; 2570 u8 mask_sel : 2; 2571 u8 bssid_cam_idx: 6; 2572 2573 u8 sec_ent_mode; 2574 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 2575 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 2576 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 2577 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 2578 }; 2579 2580 struct rtw89_bssid_cam_entry { 2581 u8 bssid[ETH_ALEN]; 2582 u8 phy_idx; 2583 u8 bssid_cam_idx; 2584 u8 offset; 2585 u8 len; 2586 u8 valid : 1; 2587 u8 num; 2588 }; 2589 2590 struct rtw89_sec_cam_entry { 2591 u8 sec_cam_idx; 2592 u8 offset; 2593 u8 len; 2594 u8 type : 4; 2595 u8 ext_key : 1; 2596 u8 spp_mode : 1; 2597 /* 256 bits */ 2598 u8 key[32]; 2599 }; 2600 2601 struct rtw89_sta { 2602 u8 mac_id; 2603 bool disassoc; 2604 bool er_cap; 2605 struct rtw89_dev *rtwdev; 2606 struct rtw89_vif *rtwvif; 2607 struct rtw89_ra_info ra; 2608 struct rtw89_ra_report ra_report; 2609 int max_agg_wait; 2610 u8 prev_rssi; 2611 struct ewma_rssi avg_rssi; 2612 struct ewma_rssi rssi[RF_PATH_MAX]; 2613 struct ewma_snr avg_snr; 2614 struct ewma_evm evm_min[RF_PATH_MAX]; 2615 struct ewma_evm evm_max[RF_PATH_MAX]; 2616 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 2617 struct ieee80211_rx_status rx_status; 2618 u16 rx_hw_rate; 2619 __le32 htc_template; 2620 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 2621 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 2622 struct list_head ba_cam_list; 2623 struct sk_buff_head roc_queue; 2624 2625 bool use_cfg_mask; 2626 struct cfg80211_bitrate_mask mask; 2627 2628 bool cctl_tx_time; 2629 u32 ampdu_max_time:4; 2630 bool cctl_tx_retry_limit; 2631 u32 data_tx_cnt_lmt:6; 2632 }; 2633 2634 struct rtw89_efuse { 2635 bool valid; 2636 bool power_k_valid; 2637 u8 xtal_cap; 2638 u8 addr[ETH_ALEN]; 2639 u8 rfe_type; 2640 char country_code[2]; 2641 }; 2642 2643 struct rtw89_phy_rate_pattern { 2644 u64 ra_mask; 2645 u16 rate; 2646 u8 ra_mode; 2647 bool enable; 2648 }; 2649 2650 struct rtw89_tx_wait_info { 2651 struct rcu_head rcu_head; 2652 struct completion completion; 2653 bool tx_done; 2654 }; 2655 2656 struct rtw89_tx_skb_data { 2657 struct rtw89_tx_wait_info __rcu *wait; 2658 u8 hci_priv[]; 2659 }; 2660 2661 #define RTW89_ROC_IDLE_TIMEOUT 500 2662 #define RTW89_ROC_TX_TIMEOUT 30 2663 enum rtw89_roc_state { 2664 RTW89_ROC_IDLE, 2665 RTW89_ROC_NORMAL, 2666 RTW89_ROC_MGMT, 2667 }; 2668 2669 struct rtw89_roc { 2670 struct ieee80211_channel chan; 2671 struct delayed_work roc_work; 2672 enum ieee80211_roc_type type; 2673 enum rtw89_roc_state state; 2674 int duration; 2675 }; 2676 2677 #define RTW89_P2P_MAX_NOA_NUM 2 2678 2679 struct rtw89_vif { 2680 struct list_head list; 2681 struct rtw89_dev *rtwdev; 2682 struct rtw89_roc roc; 2683 enum rtw89_sub_entity_idx sub_entity_idx; 2684 2685 u8 mac_id; 2686 u8 port; 2687 u8 mac_addr[ETH_ALEN]; 2688 u8 bssid[ETH_ALEN]; 2689 u8 phy_idx; 2690 u8 mac_idx; 2691 u8 net_type; 2692 u8 wifi_role; 2693 u8 self_role; 2694 u8 wmm; 2695 u8 bcn_hit_cond; 2696 u8 hit_rule; 2697 u8 last_noa_nr; 2698 bool offchan; 2699 bool trigger; 2700 bool lsig_txop; 2701 u8 tgt_ind; 2702 u8 frm_tgt_ind; 2703 bool wowlan_pattern; 2704 bool wowlan_uc; 2705 bool wowlan_magic; 2706 bool is_hesta; 2707 bool last_a_ctrl; 2708 bool dyn_tb_bedge_en; 2709 u8 def_tri_idx; 2710 u32 tdls_peer; 2711 struct work_struct update_beacon_work; 2712 struct rtw89_addr_cam_entry addr_cam; 2713 struct rtw89_bssid_cam_entry bssid_cam; 2714 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 2715 struct rtw89_traffic_stats stats; 2716 struct rtw89_phy_rate_pattern rate_pattern; 2717 struct cfg80211_scan_request *scan_req; 2718 struct ieee80211_scan_ies *scan_ies; 2719 struct list_head general_pkt_list; 2720 }; 2721 2722 enum rtw89_lv1_rcvy_step { 2723 RTW89_LV1_RCVY_STEP_1, 2724 RTW89_LV1_RCVY_STEP_2, 2725 }; 2726 2727 struct rtw89_hci_ops { 2728 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 2729 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 2730 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 2731 void (*reset)(struct rtw89_dev *rtwdev); 2732 int (*start)(struct rtw89_dev *rtwdev); 2733 void (*stop)(struct rtw89_dev *rtwdev); 2734 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 2735 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 2736 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 2737 2738 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 2739 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 2740 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 2741 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 2742 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 2743 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 2744 2745 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 2746 int (*mac_post_init)(struct rtw89_dev *rtwdev); 2747 int (*deinit)(struct rtw89_dev *rtwdev); 2748 2749 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 2750 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 2751 void (*dump_err_status)(struct rtw89_dev *rtwdev); 2752 int (*napi_poll)(struct napi_struct *napi, int budget); 2753 2754 /* Deal with locks inside recovery_start and recovery_complete callbacks 2755 * by hci instance, and handle things which need to consider under SER. 2756 * e.g. turn on/off interrupts except for the one for halt notification. 2757 */ 2758 void (*recovery_start)(struct rtw89_dev *rtwdev); 2759 void (*recovery_complete)(struct rtw89_dev *rtwdev); 2760 2761 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 2762 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 2763 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 2764 int (*poll_txdma_ch)(struct rtw89_dev *rtwdev); 2765 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 2766 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 2767 void (*disable_intr)(struct rtw89_dev *rtwdev); 2768 void (*enable_intr)(struct rtw89_dev *rtwdev); 2769 int (*rst_bdram)(struct rtw89_dev *rtwdev); 2770 }; 2771 2772 struct rtw89_hci_info { 2773 const struct rtw89_hci_ops *ops; 2774 enum rtw89_hci_type type; 2775 u32 rpwm_addr; 2776 u32 cpwm_addr; 2777 bool paused; 2778 }; 2779 2780 struct rtw89_chip_ops { 2781 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 2782 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 2783 void (*bb_reset)(struct rtw89_dev *rtwdev, 2784 enum rtw89_phy_idx phy_idx); 2785 void (*bb_sethw)(struct rtw89_dev *rtwdev); 2786 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2787 u32 addr, u32 mask); 2788 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2789 u32 addr, u32 mask, u32 data); 2790 void (*set_channel)(struct rtw89_dev *rtwdev, 2791 const struct rtw89_chan *chan, 2792 enum rtw89_mac_idx mac_idx, 2793 enum rtw89_phy_idx phy_idx); 2794 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 2795 struct rtw89_channel_help_params *p, 2796 const struct rtw89_chan *chan, 2797 enum rtw89_mac_idx mac_idx, 2798 enum rtw89_phy_idx phy_idx); 2799 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map); 2800 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 2801 void (*fem_setup)(struct rtw89_dev *rtwdev); 2802 void (*rfk_init)(struct rtw89_dev *rtwdev); 2803 void (*rfk_channel)(struct rtw89_dev *rtwdev); 2804 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 2805 enum rtw89_phy_idx phy_idx); 2806 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 2807 void (*rfk_track)(struct rtw89_dev *rtwdev); 2808 void (*power_trim)(struct rtw89_dev *rtwdev); 2809 void (*set_txpwr)(struct rtw89_dev *rtwdev, 2810 const struct rtw89_chan *chan, 2811 enum rtw89_phy_idx phy_idx); 2812 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 2813 enum rtw89_phy_idx phy_idx); 2814 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 2815 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 2816 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg); 2817 void (*query_ppdu)(struct rtw89_dev *rtwdev, 2818 struct rtw89_rx_phy_ppdu *phy_ppdu, 2819 struct ieee80211_rx_status *status); 2820 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en); 2821 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 2822 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 2823 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 2824 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 2825 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 2826 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 2827 struct rtw89_tx_desc_info *desc_info, 2828 void *txdesc); 2829 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 2830 struct rtw89_tx_desc_info *desc_info, 2831 void *txdesc); 2832 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 2833 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 2834 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 2835 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 2836 u32 *tx_en, enum rtw89_sch_tx_sel sel); 2837 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 2838 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 2839 struct rtw89_vif *rtwvif, 2840 struct rtw89_sta *rtwsta); 2841 2842 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 2843 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 2844 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 2845 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 2846 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 2847 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 2848 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 2849 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 2850 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 2851 }; 2852 2853 enum rtw89_dma_ch { 2854 RTW89_DMA_ACH0 = 0, 2855 RTW89_DMA_ACH1 = 1, 2856 RTW89_DMA_ACH2 = 2, 2857 RTW89_DMA_ACH3 = 3, 2858 RTW89_DMA_ACH4 = 4, 2859 RTW89_DMA_ACH5 = 5, 2860 RTW89_DMA_ACH6 = 6, 2861 RTW89_DMA_ACH7 = 7, 2862 RTW89_DMA_B0MG = 8, 2863 RTW89_DMA_B0HI = 9, 2864 RTW89_DMA_B1MG = 10, 2865 RTW89_DMA_B1HI = 11, 2866 RTW89_DMA_H2C = 12, 2867 RTW89_DMA_CH_NUM = 13 2868 }; 2869 2870 enum rtw89_qta_mode { 2871 RTW89_QTA_SCC, 2872 RTW89_QTA_DLFW, 2873 RTW89_QTA_WOW, 2874 2875 /* keep last */ 2876 RTW89_QTA_INVALID, 2877 }; 2878 2879 struct rtw89_hfc_ch_cfg { 2880 u16 min; 2881 u16 max; 2882 #define grp_0 0 2883 #define grp_1 1 2884 #define grp_num 2 2885 u8 grp; 2886 }; 2887 2888 struct rtw89_hfc_ch_info { 2889 u16 aval; 2890 u16 used; 2891 }; 2892 2893 struct rtw89_hfc_pub_cfg { 2894 u16 grp0; 2895 u16 grp1; 2896 u16 pub_max; 2897 u16 wp_thrd; 2898 }; 2899 2900 struct rtw89_hfc_pub_info { 2901 u16 g0_used; 2902 u16 g1_used; 2903 u16 g0_aval; 2904 u16 g1_aval; 2905 u16 pub_aval; 2906 u16 wp_aval; 2907 }; 2908 2909 struct rtw89_hfc_prec_cfg { 2910 u16 ch011_prec; 2911 u16 h2c_prec; 2912 u16 wp_ch07_prec; 2913 u16 wp_ch811_prec; 2914 u8 ch011_full_cond; 2915 u8 h2c_full_cond; 2916 u8 wp_ch07_full_cond; 2917 u8 wp_ch811_full_cond; 2918 }; 2919 2920 struct rtw89_hfc_param { 2921 bool en; 2922 bool h2c_en; 2923 u8 mode; 2924 const struct rtw89_hfc_ch_cfg *ch_cfg; 2925 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 2926 struct rtw89_hfc_pub_cfg pub_cfg; 2927 struct rtw89_hfc_pub_info pub_info; 2928 struct rtw89_hfc_prec_cfg prec_cfg; 2929 }; 2930 2931 struct rtw89_hfc_param_ini { 2932 const struct rtw89_hfc_ch_cfg *ch_cfg; 2933 const struct rtw89_hfc_pub_cfg *pub_cfg; 2934 const struct rtw89_hfc_prec_cfg *prec_cfg; 2935 u8 mode; 2936 }; 2937 2938 struct rtw89_dle_size { 2939 u16 pge_size; 2940 u16 lnk_pge_num; 2941 u16 unlnk_pge_num; 2942 }; 2943 2944 struct rtw89_wde_quota { 2945 u16 hif; 2946 u16 wcpu; 2947 u16 pkt_in; 2948 u16 cpu_io; 2949 }; 2950 2951 struct rtw89_ple_quota { 2952 u16 cma0_tx; 2953 u16 cma1_tx; 2954 u16 c2h; 2955 u16 h2c; 2956 u16 wcpu; 2957 u16 mpdu_proc; 2958 u16 cma0_dma; 2959 u16 cma1_dma; 2960 u16 bb_rpt; 2961 u16 wd_rel; 2962 u16 cpu_io; 2963 u16 tx_rpt; 2964 }; 2965 2966 struct rtw89_dle_mem { 2967 enum rtw89_qta_mode mode; 2968 const struct rtw89_dle_size *wde_size; 2969 const struct rtw89_dle_size *ple_size; 2970 const struct rtw89_wde_quota *wde_min_qt; 2971 const struct rtw89_wde_quota *wde_max_qt; 2972 const struct rtw89_ple_quota *ple_min_qt; 2973 const struct rtw89_ple_quota *ple_max_qt; 2974 }; 2975 2976 struct rtw89_reg_def { 2977 u32 addr; 2978 u32 mask; 2979 }; 2980 2981 struct rtw89_reg2_def { 2982 u32 addr; 2983 u32 data; 2984 }; 2985 2986 struct rtw89_reg3_def { 2987 u32 addr; 2988 u32 mask; 2989 u32 data; 2990 }; 2991 2992 struct rtw89_reg5_def { 2993 u8 flag; /* recognized by parsers */ 2994 u8 path; 2995 u32 addr; 2996 u32 mask; 2997 u32 data; 2998 }; 2999 3000 struct rtw89_phy_table { 3001 const struct rtw89_reg2_def *regs; 3002 u32 n_regs; 3003 enum rtw89_rf_path rf_path; 3004 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3005 enum rtw89_rf_path rf_path, void *data); 3006 }; 3007 3008 struct rtw89_txpwr_table { 3009 const void *data; 3010 u32 size; 3011 void (*load)(struct rtw89_dev *rtwdev, 3012 const struct rtw89_txpwr_table *tbl); 3013 }; 3014 3015 struct rtw89_txpwr_rule_2ghz { 3016 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3017 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3018 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3019 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3020 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3021 }; 3022 3023 struct rtw89_txpwr_rule_5ghz { 3024 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3025 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3026 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3027 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3028 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3029 }; 3030 3031 struct rtw89_txpwr_rule_6ghz { 3032 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3033 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3034 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 3035 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3036 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 3037 }; 3038 3039 struct rtw89_rfe_parms { 3040 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3041 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3042 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3043 }; 3044 3045 struct rtw89_rfe_parms_conf { 3046 const struct rtw89_rfe_parms *rfe_parms; 3047 u8 rfe_type; 3048 }; 3049 3050 struct rtw89_page_regs { 3051 u32 hci_fc_ctrl; 3052 u32 ch_page_ctrl; 3053 u32 ach_page_ctrl; 3054 u32 ach_page_info; 3055 u32 pub_page_info3; 3056 u32 pub_page_ctrl1; 3057 u32 pub_page_ctrl2; 3058 u32 pub_page_info1; 3059 u32 pub_page_info2; 3060 u32 wp_page_ctrl1; 3061 u32 wp_page_ctrl2; 3062 u32 wp_page_info1; 3063 }; 3064 3065 struct rtw89_imr_info { 3066 u32 wdrls_imr_set; 3067 u32 wsec_imr_reg; 3068 u32 wsec_imr_set; 3069 u32 mpdu_tx_imr_set; 3070 u32 mpdu_rx_imr_set; 3071 u32 sta_sch_imr_set; 3072 u32 txpktctl_imr_b0_reg; 3073 u32 txpktctl_imr_b0_clr; 3074 u32 txpktctl_imr_b0_set; 3075 u32 txpktctl_imr_b1_reg; 3076 u32 txpktctl_imr_b1_clr; 3077 u32 txpktctl_imr_b1_set; 3078 u32 wde_imr_clr; 3079 u32 wde_imr_set; 3080 u32 ple_imr_clr; 3081 u32 ple_imr_set; 3082 u32 host_disp_imr_clr; 3083 u32 host_disp_imr_set; 3084 u32 cpu_disp_imr_clr; 3085 u32 cpu_disp_imr_set; 3086 u32 other_disp_imr_clr; 3087 u32 other_disp_imr_set; 3088 u32 bbrpt_com_err_imr_reg; 3089 u32 bbrpt_chinfo_err_imr_reg; 3090 u32 bbrpt_err_imr_set; 3091 u32 bbrpt_dfs_err_imr_reg; 3092 u32 ptcl_imr_clr; 3093 u32 ptcl_imr_set; 3094 u32 cdma_imr_0_reg; 3095 u32 cdma_imr_0_clr; 3096 u32 cdma_imr_0_set; 3097 u32 cdma_imr_1_reg; 3098 u32 cdma_imr_1_clr; 3099 u32 cdma_imr_1_set; 3100 u32 phy_intf_imr_reg; 3101 u32 phy_intf_imr_clr; 3102 u32 phy_intf_imr_set; 3103 u32 rmac_imr_reg; 3104 u32 rmac_imr_clr; 3105 u32 rmac_imr_set; 3106 u32 tmac_imr_reg; 3107 u32 tmac_imr_clr; 3108 u32 tmac_imr_set; 3109 }; 3110 3111 struct rtw89_xtal_info { 3112 u32 xcap_reg; 3113 u32 sc_xo_mask; 3114 u32 sc_xi_mask; 3115 }; 3116 3117 struct rtw89_rrsr_cfgs { 3118 struct rtw89_reg3_def ref_rate; 3119 struct rtw89_reg3_def rsc; 3120 }; 3121 3122 struct rtw89_dig_regs { 3123 u32 seg0_pd_reg; 3124 u32 pd_lower_bound_mask; 3125 u32 pd_spatial_reuse_en; 3126 struct rtw89_reg_def p0_lna_init; 3127 struct rtw89_reg_def p1_lna_init; 3128 struct rtw89_reg_def p0_tia_init; 3129 struct rtw89_reg_def p1_tia_init; 3130 struct rtw89_reg_def p0_rxb_init; 3131 struct rtw89_reg_def p1_rxb_init; 3132 struct rtw89_reg_def p0_p20_pagcugc_en; 3133 struct rtw89_reg_def p0_s20_pagcugc_en; 3134 struct rtw89_reg_def p1_p20_pagcugc_en; 3135 struct rtw89_reg_def p1_s20_pagcugc_en; 3136 }; 3137 3138 struct rtw89_phy_ul_tb_info { 3139 bool dyn_tb_tri_en; 3140 u8 def_if_bandedge; 3141 }; 3142 3143 struct rtw89_antdiv_stats { 3144 struct ewma_rssi cck_rssi_avg; 3145 struct ewma_rssi ofdm_rssi_avg; 3146 struct ewma_rssi non_legacy_rssi_avg; 3147 u16 pkt_cnt_cck; 3148 u16 pkt_cnt_ofdm; 3149 u16 pkt_cnt_non_legacy; 3150 u32 evm; 3151 }; 3152 3153 struct rtw89_antdiv_info { 3154 struct rtw89_antdiv_stats target_stats; 3155 struct rtw89_antdiv_stats main_stats; 3156 struct rtw89_antdiv_stats aux_stats; 3157 u8 training_count; 3158 u8 rssi_pre; 3159 bool get_stats; 3160 }; 3161 3162 struct rtw89_chip_info { 3163 enum rtw89_core_chip_id chip_id; 3164 const struct rtw89_chip_ops *ops; 3165 const char *fw_basename; 3166 u8 fw_format_max; 3167 bool try_ce_fw; 3168 u32 fifo_size; 3169 bool small_fifo_size; 3170 u32 dle_scc_rsvd_size; 3171 u16 max_amsdu_limit; 3172 bool dis_2g_40m_ul_ofdma; 3173 u32 rsvd_ple_ofst; 3174 const struct rtw89_hfc_param_ini *hfc_param_ini; 3175 const struct rtw89_dle_mem *dle_mem; 3176 u8 wde_qempty_acq_num; 3177 u8 wde_qempty_mgq_sel; 3178 u32 rf_base_addr[2]; 3179 u8 support_chanctx_num; 3180 u8 support_bands; 3181 bool support_bw160; 3182 bool support_unii4; 3183 bool support_ul_tb_ctrl; 3184 bool hw_sec_hdr; 3185 u8 rf_path_num; 3186 u8 tx_nss; 3187 u8 rx_nss; 3188 u8 acam_num; 3189 u8 bcam_num; 3190 u8 scam_num; 3191 u8 bacam_num; 3192 u8 bacam_dynamic_num; 3193 enum rtw89_bacam_ver bacam_ver; 3194 3195 u8 sec_ctrl_efuse_size; 3196 u32 physical_efuse_size; 3197 u32 logical_efuse_size; 3198 u32 limit_efuse_size; 3199 u32 dav_phy_efuse_size; 3200 u32 dav_log_efuse_size; 3201 u32 phycap_addr; 3202 u32 phycap_size; 3203 3204 const struct rtw89_pwr_cfg * const *pwr_on_seq; 3205 const struct rtw89_pwr_cfg * const *pwr_off_seq; 3206 const struct rtw89_phy_table *bb_table; 3207 const struct rtw89_phy_table *bb_gain_table; 3208 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 3209 const struct rtw89_phy_table *nctl_table; 3210 const struct rtw89_rfk_tbl *nctl_post_table; 3211 const struct rtw89_txpwr_table *byr_table; 3212 const struct rtw89_phy_dig_gain_table *dig_table; 3213 const struct rtw89_dig_regs *dig_regs; 3214 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 3215 3216 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 3217 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 3218 const struct rtw89_rfe_parms *dflt_parms; 3219 3220 u8 txpwr_factor_rf; 3221 u8 txpwr_factor_mac; 3222 3223 u32 para_ver; 3224 u32 wlcx_desired; 3225 u8 btcx_desired; 3226 u8 scbd; 3227 u8 mailbox; 3228 3229 u8 afh_guard_ch; 3230 const u8 *wl_rssi_thres; 3231 const u8 *bt_rssi_thres; 3232 u8 rssi_tol; 3233 3234 u8 mon_reg_num; 3235 const struct rtw89_btc_fbtc_mreg *mon_reg; 3236 u8 rf_para_ulink_num; 3237 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 3238 u8 rf_para_dlink_num; 3239 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 3240 u8 ps_mode_supported; 3241 u8 low_power_hci_modes; 3242 3243 u32 h2c_cctl_func_id; 3244 u32 hci_func_en_addr; 3245 u32 h2c_desc_size; 3246 u32 txwd_body_size; 3247 u32 h2c_ctrl_reg; 3248 const u32 *h2c_regs; 3249 struct rtw89_reg_def h2c_counter_reg; 3250 u32 c2h_ctrl_reg; 3251 const u32 *c2h_regs; 3252 struct rtw89_reg_def c2h_counter_reg; 3253 const struct rtw89_page_regs *page_regs; 3254 bool cfo_src_fd; 3255 bool cfo_hw_comp; 3256 const struct rtw89_reg_def *dcfo_comp; 3257 u8 dcfo_comp_sft; 3258 const struct rtw89_imr_info *imr_info; 3259 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 3260 u32 bss_clr_map_reg; 3261 u32 dma_ch_mask; 3262 u32 edcca_lvl_reg; 3263 const struct wiphy_wowlan_support *wowlan_stub; 3264 const struct rtw89_xtal_info *xtal_info; 3265 }; 3266 3267 union rtw89_bus_info { 3268 const struct rtw89_pci_info *pci; 3269 }; 3270 3271 struct rtw89_driver_info { 3272 const struct rtw89_chip_info *chip; 3273 union rtw89_bus_info bus; 3274 }; 3275 3276 enum rtw89_hcifc_mode { 3277 RTW89_HCIFC_POH = 0, 3278 RTW89_HCIFC_STF = 1, 3279 RTW89_HCIFC_SDIO = 2, 3280 3281 /* keep last */ 3282 RTW89_HCIFC_MODE_INVALID, 3283 }; 3284 3285 struct rtw89_dle_info { 3286 enum rtw89_qta_mode qta_mode; 3287 u16 wde_pg_size; 3288 u16 ple_pg_size; 3289 u16 c0_rx_qta; 3290 u16 c1_rx_qta; 3291 }; 3292 3293 enum rtw89_host_rpr_mode { 3294 RTW89_RPR_MODE_POH = 0, 3295 RTW89_RPR_MODE_STF 3296 }; 3297 3298 #define RTW89_COMPLETION_BUF_SIZE 24 3299 #define RTW89_WAIT_COND_IDLE UINT_MAX 3300 3301 struct rtw89_completion_data { 3302 bool err; 3303 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 3304 }; 3305 3306 struct rtw89_wait_info { 3307 atomic_t cond; 3308 struct completion completion; 3309 struct rtw89_completion_data data; 3310 }; 3311 3312 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 3313 3314 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 3315 { 3316 init_completion(&wait->completion); 3317 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 3318 } 3319 3320 struct rtw89_mac_info { 3321 struct rtw89_dle_info dle_info; 3322 struct rtw89_hfc_param hfc_param; 3323 enum rtw89_qta_mode qta_mode; 3324 u8 rpwm_seq_num; 3325 u8 cpwm_seq_num; 3326 3327 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 3328 struct rtw89_wait_info fw_ofld_wait; 3329 }; 3330 3331 enum rtw89_fw_type { 3332 RTW89_FW_NORMAL = 1, 3333 RTW89_FW_WOWLAN = 3, 3334 RTW89_FW_NORMAL_CE = 5, 3335 }; 3336 3337 enum rtw89_fw_feature { 3338 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 3339 RTW89_FW_FEATURE_SCAN_OFFLOAD, 3340 RTW89_FW_FEATURE_TX_WAKE, 3341 RTW89_FW_FEATURE_CRASH_TRIGGER, 3342 RTW89_FW_FEATURE_NO_PACKET_DROP, 3343 RTW89_FW_FEATURE_NO_DEEP_PS, 3344 RTW89_FW_FEATURE_NO_LPS_PG, 3345 RTW89_FW_FEATURE_BEACON_FILTER, 3346 }; 3347 3348 struct rtw89_fw_suit { 3349 const u8 *data; 3350 u32 size; 3351 u8 major_ver; 3352 u8 minor_ver; 3353 u8 sub_ver; 3354 u8 sub_idex; 3355 u16 build_year; 3356 u16 build_mon; 3357 u16 build_date; 3358 u16 build_hour; 3359 u16 build_min; 3360 u8 cmd_ver; 3361 }; 3362 3363 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 3364 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 3365 #define RTW89_FW_SUIT_VER_CODE(s) \ 3366 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 3367 3368 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 3369 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 3370 (mfw_hdr)->ver.minor, \ 3371 (mfw_hdr)->ver.sub, \ 3372 (mfw_hdr)->ver.idx) 3373 3374 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 3375 RTW89_FW_VER_CODE(GET_FW_HDR_MAJOR_VERSION(fw_hdr), \ 3376 GET_FW_HDR_MINOR_VERSION(fw_hdr), \ 3377 GET_FW_HDR_SUBVERSION(fw_hdr), \ 3378 GET_FW_HDR_SUBINDEX(fw_hdr)) 3379 3380 struct rtw89_fw_req_info { 3381 const struct firmware *firmware; 3382 struct completion completion; 3383 }; 3384 3385 struct rtw89_fw_info { 3386 struct rtw89_fw_req_info req; 3387 int fw_format; 3388 u8 h2c_seq; 3389 u8 rec_seq; 3390 u8 h2c_counter; 3391 u8 c2h_counter; 3392 struct rtw89_fw_suit normal; 3393 struct rtw89_fw_suit wowlan; 3394 bool fw_log_enable; 3395 u32 feature_map; 3396 }; 3397 3398 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 3399 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 3400 3401 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 3402 ((_fw)->feature_map |= BIT(_fw_feature)) 3403 3404 struct rtw89_cam_info { 3405 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 3406 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 3407 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 3408 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 3409 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 3410 }; 3411 3412 enum rtw89_sar_sources { 3413 RTW89_SAR_SOURCE_NONE, 3414 RTW89_SAR_SOURCE_COMMON, 3415 3416 RTW89_SAR_SOURCE_NR, 3417 }; 3418 3419 enum rtw89_sar_subband { 3420 RTW89_SAR_2GHZ_SUBBAND, 3421 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 3422 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 3423 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 3424 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 3425 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 3426 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 3427 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 3428 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 3429 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 3430 3431 RTW89_SAR_SUBBAND_NR, 3432 }; 3433 3434 struct rtw89_sar_cfg_common { 3435 bool set[RTW89_SAR_SUBBAND_NR]; 3436 s32 cfg[RTW89_SAR_SUBBAND_NR]; 3437 }; 3438 3439 struct rtw89_sar_info { 3440 /* used to decide how to acces SAR cfg union */ 3441 enum rtw89_sar_sources src; 3442 3443 /* reserved for different knids of SAR cfg struct. 3444 * supposed that a single cfg struct cannot handle various SAR sources. 3445 */ 3446 union { 3447 struct rtw89_sar_cfg_common cfg_common; 3448 }; 3449 }; 3450 3451 struct rtw89_chanctx_cfg { 3452 enum rtw89_sub_entity_idx idx; 3453 }; 3454 3455 enum rtw89_entity_mode { 3456 RTW89_ENTITY_MODE_SCC, 3457 }; 3458 3459 struct rtw89_sub_entity { 3460 struct cfg80211_chan_def chandef; 3461 struct rtw89_chan chan; 3462 struct rtw89_chan_rcd rcd; 3463 struct rtw89_chanctx_cfg *cfg; 3464 }; 3465 3466 struct rtw89_hal { 3467 u32 rx_fltr; 3468 u8 cv; 3469 u8 acv; 3470 u32 sw_amsdu_max_size; 3471 u32 antenna_tx; 3472 u32 antenna_rx; 3473 u8 tx_nss; 3474 u8 rx_nss; 3475 bool tx_path_diversity; 3476 bool ant_diversity; 3477 bool ant_diversity_fixed; 3478 bool support_cckpd; 3479 bool support_igi; 3480 atomic_t roc_entity_idx; 3481 3482 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 3483 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY]; 3484 struct cfg80211_chan_def roc_chandef; 3485 3486 bool entity_active; 3487 enum rtw89_entity_mode entity_mode; 3488 3489 u32 edcca_bak; 3490 }; 3491 3492 #define RTW89_MAX_MAC_ID_NUM 128 3493 #define RTW89_MAX_PKT_OFLD_NUM 255 3494 3495 enum rtw89_flags { 3496 RTW89_FLAG_POWERON, 3497 RTW89_FLAG_FW_RDY, 3498 RTW89_FLAG_RUNNING, 3499 RTW89_FLAG_BFEE_MON, 3500 RTW89_FLAG_BFEE_EN, 3501 RTW89_FLAG_BFEE_TIMER_KEEP, 3502 RTW89_FLAG_NAPI_RUNNING, 3503 RTW89_FLAG_LEISURE_PS, 3504 RTW89_FLAG_LOW_POWER_MODE, 3505 RTW89_FLAG_INACTIVE_PS, 3506 RTW89_FLAG_CRASH_SIMULATING, 3507 RTW89_FLAG_WOWLAN, 3508 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 3509 RTW89_FLAG_CHANGING_INTERFACE, 3510 3511 NUM_OF_RTW89_FLAGS, 3512 }; 3513 3514 enum rtw89_pkt_drop_sel { 3515 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 3516 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 3517 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 3518 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 3519 RTW89_PKT_DROP_SEL_MACID_ALL, 3520 RTW89_PKT_DROP_SEL_MG0_ONCE, 3521 RTW89_PKT_DROP_SEL_HIQ_ONCE, 3522 RTW89_PKT_DROP_SEL_HIQ_PORT, 3523 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 3524 RTW89_PKT_DROP_SEL_BAND, 3525 RTW89_PKT_DROP_SEL_BAND_ONCE, 3526 RTW89_PKT_DROP_SEL_REL_MACID, 3527 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 3528 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 3529 }; 3530 3531 struct rtw89_pkt_drop_params { 3532 enum rtw89_pkt_drop_sel sel; 3533 enum rtw89_mac_idx mac_band; 3534 u8 macid; 3535 u8 port; 3536 u8 mbssid; 3537 bool tf_trs; 3538 u32 macid_band_sel[4]; 3539 }; 3540 3541 struct rtw89_pkt_stat { 3542 u16 beacon_nr; 3543 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 3544 }; 3545 3546 DECLARE_EWMA(thermal, 4, 4); 3547 3548 struct rtw89_phy_stat { 3549 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 3550 struct rtw89_pkt_stat cur_pkt_stat; 3551 struct rtw89_pkt_stat last_pkt_stat; 3552 }; 3553 3554 #define RTW89_DACK_PATH_NR 2 3555 #define RTW89_DACK_IDX_NR 2 3556 #define RTW89_DACK_MSBK_NR 16 3557 struct rtw89_dack_info { 3558 bool dack_done; 3559 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 3560 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3561 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3562 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3563 u32 dack_cnt; 3564 bool addck_timeout[RTW89_DACK_PATH_NR]; 3565 bool dadck_timeout[RTW89_DACK_PATH_NR]; 3566 bool msbk_timeout[RTW89_DACK_PATH_NR]; 3567 }; 3568 3569 #define RTW89_IQK_CHS_NR 2 3570 #define RTW89_IQK_PATH_NR 4 3571 3572 struct rtw89_rfk_mcc_info { 3573 u8 ch[RTW89_IQK_CHS_NR]; 3574 u8 band[RTW89_IQK_CHS_NR]; 3575 u8 table_idx; 3576 }; 3577 3578 struct rtw89_lck_info { 3579 u8 thermal[RF_PATH_MAX]; 3580 }; 3581 3582 struct rtw89_rx_dck_info { 3583 u8 thermal[RF_PATH_MAX]; 3584 }; 3585 3586 struct rtw89_iqk_info { 3587 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3588 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3589 bool lok_fail[RTW89_IQK_PATH_NR]; 3590 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3591 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3592 u32 iqk_fail_cnt; 3593 bool is_iqk_init; 3594 u32 iqk_channel[RTW89_IQK_CHS_NR]; 3595 u8 iqk_band[RTW89_IQK_PATH_NR]; 3596 u8 iqk_ch[RTW89_IQK_PATH_NR]; 3597 u8 iqk_bw[RTW89_IQK_PATH_NR]; 3598 u8 kcount; 3599 u8 iqk_times; 3600 u8 version; 3601 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 3602 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 3603 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 3604 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 3605 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 3606 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 3607 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 3608 bool is_nbiqk; 3609 bool iqk_fft_en; 3610 bool iqk_xym_en; 3611 bool iqk_sram_en; 3612 bool iqk_cfir_en; 3613 u8 thermal[RTW89_IQK_PATH_NR]; 3614 bool thermal_rek_en; 3615 u32 syn1to2; 3616 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3617 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 3618 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3619 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3620 }; 3621 3622 #define RTW89_DPK_RF_PATH 2 3623 #define RTW89_DPK_AVG_THERMAL_NUM 8 3624 #define RTW89_DPK_BKUP_NUM 2 3625 struct rtw89_dpk_bkup_para { 3626 enum rtw89_band band; 3627 enum rtw89_bandwidth bw; 3628 u8 ch; 3629 bool path_ok; 3630 u8 mdpd_en; 3631 u8 txagc_dpk; 3632 u8 ther_dpk; 3633 u8 gs; 3634 u16 pwsf; 3635 }; 3636 3637 struct rtw89_dpk_info { 3638 bool is_dpk_enable; 3639 bool is_dpk_reload_en; 3640 u8 dpk_gs[RTW89_PHY_MAX]; 3641 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3642 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3643 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3644 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3645 u8 cur_idx[RTW89_DPK_RF_PATH]; 3646 u8 cur_k_set; 3647 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3648 }; 3649 3650 struct rtw89_fem_info { 3651 bool elna_2g; 3652 bool elna_5g; 3653 bool epa_2g; 3654 bool epa_5g; 3655 bool epa_6g; 3656 }; 3657 3658 struct rtw89_phy_ch_info { 3659 u8 rssi_min; 3660 u16 rssi_min_macid; 3661 u8 pre_rssi_min; 3662 u8 rssi_max; 3663 u16 rssi_max_macid; 3664 u8 rxsc_160; 3665 u8 rxsc_80; 3666 u8 rxsc_40; 3667 u8 rxsc_20; 3668 u8 rxsc_l; 3669 u8 is_noisy; 3670 }; 3671 3672 struct rtw89_agc_gaincode_set { 3673 u8 lna_idx; 3674 u8 tia_idx; 3675 u8 rxb_idx; 3676 }; 3677 3678 #define IGI_RSSI_TH_NUM 5 3679 #define FA_TH_NUM 4 3680 #define LNA_GAIN_NUM 7 3681 #define TIA_GAIN_NUM 2 3682 struct rtw89_dig_info { 3683 struct rtw89_agc_gaincode_set cur_gaincode; 3684 bool force_gaincode_idx_en; 3685 struct rtw89_agc_gaincode_set force_gaincode; 3686 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 3687 u16 fa_th[FA_TH_NUM]; 3688 u8 igi_rssi; 3689 u8 igi_fa_rssi; 3690 u8 fa_rssi_ofst; 3691 u8 dyn_igi_max; 3692 u8 dyn_igi_min; 3693 bool dyn_pd_th_en; 3694 u8 dyn_pd_th_max; 3695 u8 pd_low_th_ofst; 3696 u8 ib_pbk; 3697 s8 ib_pkpwr; 3698 s8 lna_gain_a[LNA_GAIN_NUM]; 3699 s8 lna_gain_g[LNA_GAIN_NUM]; 3700 s8 *lna_gain; 3701 s8 tia_gain_a[TIA_GAIN_NUM]; 3702 s8 tia_gain_g[TIA_GAIN_NUM]; 3703 s8 *tia_gain; 3704 bool is_linked_pre; 3705 bool bypass_dig; 3706 }; 3707 3708 enum rtw89_multi_cfo_mode { 3709 RTW89_PKT_BASED_AVG_MODE = 0, 3710 RTW89_ENTRY_BASED_AVG_MODE = 1, 3711 RTW89_TP_BASED_AVG_MODE = 2, 3712 }; 3713 3714 enum rtw89_phy_cfo_status { 3715 RTW89_PHY_DCFO_STATE_NORMAL = 0, 3716 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 3717 RTW89_PHY_DCFO_STATE_HOLD = 2, 3718 RTW89_PHY_DCFO_STATE_MAX 3719 }; 3720 3721 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 3722 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 3723 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 3724 }; 3725 3726 struct rtw89_cfo_tracking_info { 3727 u16 cfo_timer_ms; 3728 bool cfo_trig_by_timer_en; 3729 enum rtw89_phy_cfo_status phy_cfo_status; 3730 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 3731 u8 phy_cfo_trk_cnt; 3732 bool is_adjust; 3733 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 3734 bool apply_compensation; 3735 u8 crystal_cap; 3736 u8 crystal_cap_default; 3737 u8 def_x_cap; 3738 s8 x_cap_ofst; 3739 u32 sta_cfo_tolerance; 3740 s32 cfo_tail[CFO_TRACK_MAX_USER]; 3741 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 3742 s32 cfo_avg_pre; 3743 s32 cfo_avg[CFO_TRACK_MAX_USER]; 3744 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 3745 s32 dcfo_avg; 3746 s32 dcfo_avg_pre; 3747 u32 packet_count; 3748 u32 packet_count_pre; 3749 s32 residual_cfo_acc; 3750 u8 phy_cfotrk_state; 3751 u8 phy_cfotrk_cnt; 3752 bool divergence_lock_en; 3753 u8 x_cap_lb; 3754 u8 x_cap_ub; 3755 u8 lock_cnt; 3756 }; 3757 3758 enum rtw89_tssi_alimk_band { 3759 TSSI_ALIMK_2G = 0, 3760 TSSI_ALIMK_5GL, 3761 TSSI_ALIMK_5GM, 3762 TSSI_ALIMK_5GH, 3763 TSSI_ALIMK_MAX 3764 }; 3765 3766 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 3767 #define TSSI_TRIM_CH_GROUP_NUM 8 3768 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 3769 3770 #define TSSI_CCK_CH_GROUP_NUM 6 3771 #define TSSI_MCS_2G_CH_GROUP_NUM 5 3772 #define TSSI_MCS_5G_CH_GROUP_NUM 14 3773 #define TSSI_MCS_6G_CH_GROUP_NUM 32 3774 #define TSSI_MCS_CH_GROUP_NUM \ 3775 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 3776 #define TSSI_MAX_CH_NUM 67 3777 #define TSSI_ALIMK_VALUE_NUM 8 3778 3779 struct rtw89_tssi_info { 3780 u8 thermal[RF_PATH_MAX]; 3781 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 3782 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 3783 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 3784 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 3785 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 3786 s8 extra_ofst[RF_PATH_MAX]; 3787 bool tssi_tracking_check[RF_PATH_MAX]; 3788 u8 default_txagc_offset[RF_PATH_MAX]; 3789 u32 base_thermal[RF_PATH_MAX]; 3790 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 3791 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 3792 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 3793 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 3794 u32 tssi_alimk_time; 3795 }; 3796 3797 struct rtw89_power_trim_info { 3798 bool pg_thermal_trim; 3799 bool pg_pa_bias_trim; 3800 u8 thermal_trim[RF_PATH_MAX]; 3801 u8 pa_bias_trim[RF_PATH_MAX]; 3802 }; 3803 3804 struct rtw89_regulatory { 3805 char alpha2[3]; 3806 u8 txpwr_regd[RTW89_BAND_MAX]; 3807 }; 3808 3809 enum rtw89_ifs_clm_application { 3810 RTW89_IFS_CLM_INIT = 0, 3811 RTW89_IFS_CLM_BACKGROUND = 1, 3812 RTW89_IFS_CLM_ACS = 2, 3813 RTW89_IFS_CLM_DIG = 3, 3814 RTW89_IFS_CLM_TDMA_DIG = 4, 3815 RTW89_IFS_CLM_DBG = 5, 3816 RTW89_IFS_CLM_DBG_MANUAL = 6 3817 }; 3818 3819 enum rtw89_env_racing_lv { 3820 RTW89_RAC_RELEASE = 0, 3821 RTW89_RAC_LV_1 = 1, 3822 RTW89_RAC_LV_2 = 2, 3823 RTW89_RAC_LV_3 = 3, 3824 RTW89_RAC_LV_4 = 4, 3825 RTW89_RAC_MAX_NUM = 5 3826 }; 3827 3828 struct rtw89_ccx_para_info { 3829 enum rtw89_env_racing_lv rac_lv; 3830 u16 mntr_time; 3831 u8 nhm_manual_th_ofst; 3832 u8 nhm_manual_th0; 3833 enum rtw89_ifs_clm_application ifs_clm_app; 3834 u32 ifs_clm_manual_th_times; 3835 u32 ifs_clm_manual_th0; 3836 u8 fahm_manual_th_ofst; 3837 u8 fahm_manual_th0; 3838 u8 fahm_numer_opt; 3839 u8 fahm_denom_opt; 3840 }; 3841 3842 enum rtw89_ccx_edcca_opt_sc_idx { 3843 RTW89_CCX_EDCCA_SEG0_P0 = 0, 3844 RTW89_CCX_EDCCA_SEG0_S1 = 1, 3845 RTW89_CCX_EDCCA_SEG0_S2 = 2, 3846 RTW89_CCX_EDCCA_SEG0_S3 = 3, 3847 RTW89_CCX_EDCCA_SEG1_P0 = 4, 3848 RTW89_CCX_EDCCA_SEG1_S1 = 5, 3849 RTW89_CCX_EDCCA_SEG1_S2 = 6, 3850 RTW89_CCX_EDCCA_SEG1_S3 = 7 3851 }; 3852 3853 enum rtw89_ccx_edcca_opt_bw_idx { 3854 RTW89_CCX_EDCCA_BW20_0 = 0, 3855 RTW89_CCX_EDCCA_BW20_1 = 1, 3856 RTW89_CCX_EDCCA_BW20_2 = 2, 3857 RTW89_CCX_EDCCA_BW20_3 = 3, 3858 RTW89_CCX_EDCCA_BW20_4 = 4, 3859 RTW89_CCX_EDCCA_BW20_5 = 5, 3860 RTW89_CCX_EDCCA_BW20_6 = 6, 3861 RTW89_CCX_EDCCA_BW20_7 = 7 3862 }; 3863 3864 #define RTW89_NHM_TH_NUM 11 3865 #define RTW89_FAHM_TH_NUM 11 3866 #define RTW89_NHM_RPT_NUM 12 3867 #define RTW89_FAHM_RPT_NUM 12 3868 #define RTW89_IFS_CLM_NUM 4 3869 struct rtw89_env_monitor_info { 3870 u32 ccx_trigger_time; 3871 u64 start_time; 3872 u8 ccx_rpt_stamp; 3873 u8 ccx_watchdog_result; 3874 bool ccx_ongoing; 3875 u8 ccx_rac_lv; 3876 bool ccx_manual_ctrl; 3877 u8 ccx_pre_rssi; 3878 u16 clm_mntr_time; 3879 u16 nhm_mntr_time; 3880 u16 ifs_clm_mntr_time; 3881 enum rtw89_ifs_clm_application ifs_clm_app; 3882 u16 fahm_mntr_time; 3883 u16 edcca_clm_mntr_time; 3884 u16 ccx_period; 3885 u8 ccx_unit_idx; 3886 enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx; 3887 u8 nhm_th[RTW89_NHM_TH_NUM]; 3888 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 3889 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 3890 u8 fahm_numer_opt; 3891 u8 fahm_denom_opt; 3892 u8 fahm_th[RTW89_FAHM_TH_NUM]; 3893 u16 clm_result; 3894 u16 nhm_result[RTW89_NHM_RPT_NUM]; 3895 u8 nhm_wgt[RTW89_NHM_RPT_NUM]; 3896 u16 nhm_tx_cnt; 3897 u16 nhm_cca_cnt; 3898 u16 nhm_idle_cnt; 3899 u16 ifs_clm_tx; 3900 u16 ifs_clm_edcca_excl_cca; 3901 u16 ifs_clm_ofdmfa; 3902 u16 ifs_clm_ofdmcca_excl_fa; 3903 u16 ifs_clm_cckfa; 3904 u16 ifs_clm_cckcca_excl_fa; 3905 u16 ifs_clm_total_ifs; 3906 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 3907 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 3908 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 3909 u16 fahm_result[RTW89_FAHM_RPT_NUM]; 3910 u16 fahm_denom_result; 3911 u16 edcca_clm_result; 3912 u8 clm_ratio; 3913 u8 nhm_rpt[RTW89_NHM_RPT_NUM]; 3914 u8 nhm_tx_ratio; 3915 u8 nhm_cca_ratio; 3916 u8 nhm_idle_ratio; 3917 u8 nhm_ratio; 3918 u16 nhm_result_sum; 3919 u8 nhm_pwr; 3920 u8 ifs_clm_tx_ratio; 3921 u8 ifs_clm_edcca_excl_cca_ratio; 3922 u8 ifs_clm_cck_fa_ratio; 3923 u8 ifs_clm_ofdm_fa_ratio; 3924 u8 ifs_clm_cck_cca_excl_fa_ratio; 3925 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 3926 u16 ifs_clm_cck_fa_permil; 3927 u16 ifs_clm_ofdm_fa_permil; 3928 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 3929 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 3930 u8 fahm_rpt[RTW89_FAHM_RPT_NUM]; 3931 u16 fahm_result_sum; 3932 u8 fahm_ratio; 3933 u8 fahm_denom_ratio; 3934 u8 fahm_pwr; 3935 u8 edcca_clm_ratio; 3936 }; 3937 3938 enum rtw89_ser_rcvy_step { 3939 RTW89_SER_DRV_STOP_TX, 3940 RTW89_SER_DRV_STOP_RX, 3941 RTW89_SER_DRV_STOP_RUN, 3942 RTW89_SER_HAL_STOP_DMA, 3943 RTW89_SER_SUPPRESS_LOG, 3944 RTW89_NUM_OF_SER_FLAGS 3945 }; 3946 3947 struct rtw89_ser { 3948 u8 state; 3949 u8 alarm_event; 3950 bool prehandle_l1; 3951 3952 struct work_struct ser_hdl_work; 3953 struct delayed_work ser_alarm_work; 3954 const struct state_ent *st_tbl; 3955 const struct event_ent *ev_tbl; 3956 struct list_head msg_q; 3957 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 3958 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 3959 }; 3960 3961 enum rtw89_mac_ax_ps_mode { 3962 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 3963 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 3964 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 3965 RTW89_MAC_AX_PS_MODE_MAX = 3, 3966 }; 3967 3968 enum rtw89_last_rpwm_mode { 3969 RTW89_LAST_RPWM_PS = 0x0, 3970 RTW89_LAST_RPWM_ACTIVE = 0x6, 3971 }; 3972 3973 struct rtw89_lps_parm { 3974 u8 macid; 3975 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 3976 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 3977 }; 3978 3979 struct rtw89_ppdu_sts_info { 3980 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 3981 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 3982 }; 3983 3984 struct rtw89_early_h2c { 3985 struct list_head list; 3986 u8 *h2c; 3987 u16 h2c_len; 3988 }; 3989 3990 struct rtw89_hw_scan_info { 3991 struct ieee80211_vif *scanning_vif; 3992 struct list_head pkt_list[NUM_NL80211_BANDS]; 3993 struct rtw89_chan op_chan; 3994 u32 last_chan_idx; 3995 }; 3996 3997 enum rtw89_phy_bb_gain_band { 3998 RTW89_BB_GAIN_BAND_2G = 0, 3999 RTW89_BB_GAIN_BAND_5G_L = 1, 4000 RTW89_BB_GAIN_BAND_5G_M = 2, 4001 RTW89_BB_GAIN_BAND_5G_H = 3, 4002 RTW89_BB_GAIN_BAND_6G_L = 4, 4003 RTW89_BB_GAIN_BAND_6G_M = 5, 4004 RTW89_BB_GAIN_BAND_6G_H = 6, 4005 RTW89_BB_GAIN_BAND_6G_UH = 7, 4006 4007 RTW89_BB_GAIN_BAND_NR, 4008 }; 4009 4010 enum rtw89_phy_bb_rxsc_num { 4011 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 4012 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 4013 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 4014 }; 4015 4016 struct rtw89_phy_bb_gain_info { 4017 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4018 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 4019 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4020 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4021 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4022 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 4023 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 4024 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4025 [RTW89_BB_RXSC_NUM_40]; 4026 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4027 [RTW89_BB_RXSC_NUM_80]; 4028 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4029 [RTW89_BB_RXSC_NUM_160]; 4030 }; 4031 4032 struct rtw89_phy_efuse_gain { 4033 bool offset_valid; 4034 bool comp_valid; 4035 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 4036 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 4037 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 4038 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 4039 }; 4040 4041 #define RTW89_MAX_PATTERN_NUM 18 4042 #define RTW89_MAX_PATTERN_MASK_SIZE 4 4043 #define RTW89_MAX_PATTERN_SIZE 128 4044 4045 struct rtw89_wow_cam_info { 4046 bool r_w; 4047 u8 idx; 4048 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 4049 u16 crc; 4050 bool negative_pattern_match; 4051 bool skip_mac_hdr; 4052 bool uc; 4053 bool mc; 4054 bool bc; 4055 bool valid; 4056 }; 4057 4058 struct rtw89_wow_param { 4059 struct ieee80211_vif *wow_vif; 4060 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 4061 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 4062 u8 pattern_cnt; 4063 }; 4064 4065 struct rtw89_mcc_info { 4066 struct rtw89_wait_info wait; 4067 }; 4068 4069 struct rtw89_dev { 4070 struct ieee80211_hw *hw; 4071 struct device *dev; 4072 const struct ieee80211_ops *ops; 4073 4074 bool dbcc_en; 4075 struct rtw89_hw_scan_info scan_info; 4076 const struct rtw89_chip_info *chip; 4077 const struct rtw89_pci_info *pci_info; 4078 const struct rtw89_rfe_parms *rfe_parms; 4079 struct rtw89_hal hal; 4080 struct rtw89_mcc_info mcc; 4081 struct rtw89_mac_info mac; 4082 struct rtw89_fw_info fw; 4083 struct rtw89_hci_info hci; 4084 struct rtw89_efuse efuse; 4085 struct rtw89_traffic_stats stats; 4086 4087 /* ensures exclusive access from mac80211 callbacks */ 4088 struct mutex mutex; 4089 struct list_head rtwvifs_list; 4090 /* used to protect rf read write */ 4091 struct mutex rf_mutex; 4092 struct workqueue_struct *txq_wq; 4093 struct work_struct txq_work; 4094 struct delayed_work txq_reinvoke_work; 4095 /* used to protect ba_list and forbid_ba_list */ 4096 spinlock_t ba_lock; 4097 /* txqs to setup ba session */ 4098 struct list_head ba_list; 4099 /* txqs to forbid ba session */ 4100 struct list_head forbid_ba_list; 4101 struct work_struct ba_work; 4102 /* used to protect rpwm */ 4103 spinlock_t rpwm_lock; 4104 4105 struct rtw89_cam_info cam_info; 4106 4107 struct sk_buff_head c2h_queue; 4108 struct work_struct c2h_work; 4109 struct work_struct ips_work; 4110 struct work_struct load_firmware_work; 4111 struct work_struct cancel_6ghz_probe_work; 4112 4113 struct list_head early_h2c_list; 4114 4115 struct rtw89_ser ser; 4116 4117 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 4118 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 4119 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 4120 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 4121 4122 struct rtw89_phy_stat phystat; 4123 struct rtw89_dack_info dack; 4124 struct rtw89_iqk_info iqk; 4125 struct rtw89_dpk_info dpk; 4126 struct rtw89_rfk_mcc_info rfk_mcc; 4127 struct rtw89_lck_info lck; 4128 struct rtw89_rx_dck_info rx_dck; 4129 bool is_tssi_mode[RF_PATH_MAX]; 4130 bool is_bt_iqk_timeout; 4131 4132 struct rtw89_fem_info fem; 4133 struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX]; 4134 struct rtw89_tssi_info tssi; 4135 struct rtw89_power_trim_info pwr_trim; 4136 4137 struct rtw89_cfo_tracking_info cfo_tracking; 4138 struct rtw89_env_monitor_info env_monitor; 4139 struct rtw89_dig_info dig; 4140 struct rtw89_phy_ch_info ch_info; 4141 struct rtw89_phy_bb_gain_info bb_gain; 4142 struct rtw89_phy_efuse_gain efuse_gain; 4143 struct rtw89_phy_ul_tb_info ul_tb_info; 4144 struct rtw89_antdiv_info antdiv; 4145 4146 struct delayed_work track_work; 4147 struct delayed_work coex_act1_work; 4148 struct delayed_work coex_bt_devinfo_work; 4149 struct delayed_work coex_rfk_chk_work; 4150 struct delayed_work cfo_track_work; 4151 struct delayed_work forbid_ba_work; 4152 struct delayed_work roc_work; 4153 struct delayed_work antdiv_work; 4154 struct rtw89_ppdu_sts_info ppdu_sts; 4155 u8 total_sta_assoc; 4156 bool scanning; 4157 4158 const struct rtw89_regulatory *regd; 4159 struct rtw89_sar_info sar; 4160 4161 struct rtw89_btc btc; 4162 enum rtw89_ps_mode ps_mode; 4163 bool lps_enabled; 4164 4165 struct rtw89_wow_param wow; 4166 4167 /* napi structure */ 4168 struct net_device netdev; 4169 struct napi_struct napi; 4170 int napi_budget_countdown; 4171 4172 /* HCI related data, keep last */ 4173 u8 priv[] __aligned(sizeof(void *)); 4174 }; 4175 4176 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 4177 struct rtw89_core_tx_request *tx_req) 4178 { 4179 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 4180 } 4181 4182 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 4183 { 4184 rtwdev->hci.ops->reset(rtwdev); 4185 } 4186 4187 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 4188 { 4189 return rtwdev->hci.ops->start(rtwdev); 4190 } 4191 4192 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 4193 { 4194 rtwdev->hci.ops->stop(rtwdev); 4195 } 4196 4197 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 4198 { 4199 return rtwdev->hci.ops->deinit(rtwdev); 4200 } 4201 4202 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 4203 { 4204 rtwdev->hci.ops->pause(rtwdev, pause); 4205 } 4206 4207 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 4208 { 4209 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 4210 } 4211 4212 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 4213 { 4214 rtwdev->hci.ops->recalc_int_mit(rtwdev); 4215 } 4216 4217 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 4218 { 4219 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 4220 } 4221 4222 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 4223 { 4224 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 4225 } 4226 4227 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 4228 bool drop) 4229 { 4230 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4231 return; 4232 4233 if (rtwdev->hci.ops->flush_queues) 4234 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 4235 } 4236 4237 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 4238 { 4239 if (rtwdev->hci.ops->recovery_start) 4240 rtwdev->hci.ops->recovery_start(rtwdev); 4241 } 4242 4243 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 4244 { 4245 if (rtwdev->hci.ops->recovery_complete) 4246 rtwdev->hci.ops->recovery_complete(rtwdev); 4247 } 4248 4249 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 4250 { 4251 if (rtwdev->hci.ops->enable_intr) 4252 rtwdev->hci.ops->enable_intr(rtwdev); 4253 } 4254 4255 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 4256 { 4257 if (rtwdev->hci.ops->disable_intr) 4258 rtwdev->hci.ops->disable_intr(rtwdev); 4259 } 4260 4261 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 4262 { 4263 if (rtwdev->hci.ops->ctrl_txdma_ch) 4264 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 4265 } 4266 4267 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 4268 { 4269 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 4270 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 4271 } 4272 4273 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 4274 { 4275 if (rtwdev->hci.ops->ctrl_trxhci) 4276 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 4277 } 4278 4279 static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev) 4280 { 4281 int ret = 0; 4282 4283 if (rtwdev->hci.ops->poll_txdma_ch) 4284 ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev); 4285 return ret; 4286 } 4287 4288 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 4289 { 4290 if (rtwdev->hci.ops->clr_idx_all) 4291 rtwdev->hci.ops->clr_idx_all(rtwdev); 4292 } 4293 4294 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 4295 { 4296 int ret = 0; 4297 4298 if (rtwdev->hci.ops->rst_bdram) 4299 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 4300 return ret; 4301 } 4302 4303 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 4304 { 4305 if (rtwdev->hci.ops->clear) 4306 rtwdev->hci.ops->clear(rtwdev, pdev); 4307 } 4308 4309 static inline 4310 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 4311 { 4312 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 4313 4314 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 4315 } 4316 4317 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 4318 { 4319 return rtwdev->hci.ops->read8(rtwdev, addr); 4320 } 4321 4322 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 4323 { 4324 return rtwdev->hci.ops->read16(rtwdev, addr); 4325 } 4326 4327 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 4328 { 4329 return rtwdev->hci.ops->read32(rtwdev, addr); 4330 } 4331 4332 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 4333 { 4334 rtwdev->hci.ops->write8(rtwdev, addr, data); 4335 } 4336 4337 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 4338 { 4339 rtwdev->hci.ops->write16(rtwdev, addr, data); 4340 } 4341 4342 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 4343 { 4344 rtwdev->hci.ops->write32(rtwdev, addr, data); 4345 } 4346 4347 static inline void 4348 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 4349 { 4350 u8 val; 4351 4352 val = rtw89_read8(rtwdev, addr); 4353 rtw89_write8(rtwdev, addr, val | bit); 4354 } 4355 4356 static inline void 4357 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 4358 { 4359 u16 val; 4360 4361 val = rtw89_read16(rtwdev, addr); 4362 rtw89_write16(rtwdev, addr, val | bit); 4363 } 4364 4365 static inline void 4366 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 4367 { 4368 u32 val; 4369 4370 val = rtw89_read32(rtwdev, addr); 4371 rtw89_write32(rtwdev, addr, val | bit); 4372 } 4373 4374 static inline void 4375 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 4376 { 4377 u8 val; 4378 4379 val = rtw89_read8(rtwdev, addr); 4380 rtw89_write8(rtwdev, addr, val & ~bit); 4381 } 4382 4383 static inline void 4384 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 4385 { 4386 u16 val; 4387 4388 val = rtw89_read16(rtwdev, addr); 4389 rtw89_write16(rtwdev, addr, val & ~bit); 4390 } 4391 4392 static inline void 4393 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 4394 { 4395 u32 val; 4396 4397 val = rtw89_read32(rtwdev, addr); 4398 rtw89_write32(rtwdev, addr, val & ~bit); 4399 } 4400 4401 static inline u32 4402 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4403 { 4404 u32 shift = __ffs(mask); 4405 u32 orig; 4406 u32 ret; 4407 4408 orig = rtw89_read32(rtwdev, addr); 4409 ret = (orig & mask) >> shift; 4410 4411 return ret; 4412 } 4413 4414 static inline u16 4415 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4416 { 4417 u32 shift = __ffs(mask); 4418 u32 orig; 4419 u32 ret; 4420 4421 orig = rtw89_read16(rtwdev, addr); 4422 ret = (orig & mask) >> shift; 4423 4424 return ret; 4425 } 4426 4427 static inline u8 4428 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4429 { 4430 u32 shift = __ffs(mask); 4431 u32 orig; 4432 u32 ret; 4433 4434 orig = rtw89_read8(rtwdev, addr); 4435 ret = (orig & mask) >> shift; 4436 4437 return ret; 4438 } 4439 4440 static inline void 4441 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 4442 { 4443 u32 shift = __ffs(mask); 4444 u32 orig; 4445 u32 set; 4446 4447 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 4448 4449 orig = rtw89_read32(rtwdev, addr); 4450 set = (orig & ~mask) | ((data << shift) & mask); 4451 rtw89_write32(rtwdev, addr, set); 4452 } 4453 4454 static inline void 4455 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 4456 { 4457 u32 shift; 4458 u16 orig, set; 4459 4460 mask &= 0xffff; 4461 shift = __ffs(mask); 4462 4463 orig = rtw89_read16(rtwdev, addr); 4464 set = (orig & ~mask) | ((data << shift) & mask); 4465 rtw89_write16(rtwdev, addr, set); 4466 } 4467 4468 static inline void 4469 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 4470 { 4471 u32 shift; 4472 u8 orig, set; 4473 4474 mask &= 0xff; 4475 shift = __ffs(mask); 4476 4477 orig = rtw89_read8(rtwdev, addr); 4478 set = (orig & ~mask) | ((data << shift) & mask); 4479 rtw89_write8(rtwdev, addr, set); 4480 } 4481 4482 static inline u32 4483 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 4484 u32 addr, u32 mask) 4485 { 4486 u32 val; 4487 4488 mutex_lock(&rtwdev->rf_mutex); 4489 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 4490 mutex_unlock(&rtwdev->rf_mutex); 4491 4492 return val; 4493 } 4494 4495 static inline void 4496 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 4497 u32 addr, u32 mask, u32 data) 4498 { 4499 mutex_lock(&rtwdev->rf_mutex); 4500 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 4501 mutex_unlock(&rtwdev->rf_mutex); 4502 } 4503 4504 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 4505 { 4506 void *p = rtwtxq; 4507 4508 return container_of(p, struct ieee80211_txq, drv_priv); 4509 } 4510 4511 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 4512 struct ieee80211_txq *txq) 4513 { 4514 struct rtw89_txq *rtwtxq; 4515 4516 if (!txq) 4517 return; 4518 4519 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 4520 INIT_LIST_HEAD(&rtwtxq->list); 4521 } 4522 4523 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 4524 { 4525 void *p = rtwvif; 4526 4527 return container_of(p, struct ieee80211_vif, drv_priv); 4528 } 4529 4530 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 4531 { 4532 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 4533 } 4534 4535 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 4536 { 4537 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 4538 } 4539 4540 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 4541 { 4542 void *p = rtwsta; 4543 4544 return container_of(p, struct ieee80211_sta, drv_priv); 4545 } 4546 4547 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 4548 { 4549 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 4550 } 4551 4552 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 4553 { 4554 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 4555 } 4556 4557 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 4558 { 4559 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 4560 return RATE_INFO_BW_160; 4561 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 4562 return RATE_INFO_BW_80; 4563 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 4564 return RATE_INFO_BW_40; 4565 else 4566 return RATE_INFO_BW_20; 4567 } 4568 4569 static inline 4570 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 4571 { 4572 switch (hw_band) { 4573 default: 4574 case RTW89_BAND_2G: 4575 return NL80211_BAND_2GHZ; 4576 case RTW89_BAND_5G: 4577 return NL80211_BAND_5GHZ; 4578 case RTW89_BAND_6G: 4579 return NL80211_BAND_6GHZ; 4580 } 4581 } 4582 4583 static inline 4584 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 4585 { 4586 switch (nl_band) { 4587 default: 4588 case NL80211_BAND_2GHZ: 4589 return RTW89_BAND_2G; 4590 case NL80211_BAND_5GHZ: 4591 return RTW89_BAND_5G; 4592 case NL80211_BAND_6GHZ: 4593 return RTW89_BAND_6G; 4594 } 4595 } 4596 4597 static inline 4598 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 4599 { 4600 switch (width) { 4601 default: 4602 WARN(1, "Not support bandwidth %d\n", width); 4603 fallthrough; 4604 case NL80211_CHAN_WIDTH_20_NOHT: 4605 case NL80211_CHAN_WIDTH_20: 4606 return RTW89_CHANNEL_WIDTH_20; 4607 case NL80211_CHAN_WIDTH_40: 4608 return RTW89_CHANNEL_WIDTH_40; 4609 case NL80211_CHAN_WIDTH_80: 4610 return RTW89_CHANNEL_WIDTH_80; 4611 case NL80211_CHAN_WIDTH_160: 4612 return RTW89_CHANNEL_WIDTH_160; 4613 } 4614 } 4615 4616 static inline 4617 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 4618 struct rtw89_sta *rtwsta) 4619 { 4620 if (rtwsta) { 4621 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 4622 4623 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 4624 return &rtwsta->addr_cam; 4625 } 4626 return &rtwvif->addr_cam; 4627 } 4628 4629 static inline 4630 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 4631 struct rtw89_sta *rtwsta) 4632 { 4633 if (rtwsta) { 4634 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 4635 4636 if (sta->tdls) 4637 return &rtwsta->bssid_cam; 4638 } 4639 return &rtwvif->bssid_cam; 4640 } 4641 4642 static inline 4643 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 4644 struct rtw89_channel_help_params *p, 4645 const struct rtw89_chan *chan, 4646 enum rtw89_mac_idx mac_idx, 4647 enum rtw89_phy_idx phy_idx) 4648 { 4649 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 4650 mac_idx, phy_idx); 4651 } 4652 4653 static inline 4654 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 4655 struct rtw89_channel_help_params *p, 4656 const struct rtw89_chan *chan, 4657 enum rtw89_mac_idx mac_idx, 4658 enum rtw89_phy_idx phy_idx) 4659 { 4660 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 4661 mac_idx, phy_idx); 4662 } 4663 4664 static inline 4665 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 4666 enum rtw89_sub_entity_idx idx) 4667 { 4668 struct rtw89_hal *hal = &rtwdev->hal; 4669 enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx); 4670 4671 if (roc_idx == idx) 4672 return &hal->roc_chandef; 4673 4674 return &hal->sub[idx].chandef; 4675 } 4676 4677 static inline 4678 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 4679 enum rtw89_sub_entity_idx idx) 4680 { 4681 struct rtw89_hal *hal = &rtwdev->hal; 4682 4683 return &hal->sub[idx].chan; 4684 } 4685 4686 static inline 4687 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 4688 enum rtw89_sub_entity_idx idx) 4689 { 4690 struct rtw89_hal *hal = &rtwdev->hal; 4691 4692 return &hal->sub[idx].rcd; 4693 } 4694 4695 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 4696 { 4697 const struct rtw89_chip_info *chip = rtwdev->chip; 4698 4699 if (chip->ops->fem_setup) 4700 chip->ops->fem_setup(rtwdev); 4701 } 4702 4703 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 4704 { 4705 const struct rtw89_chip_info *chip = rtwdev->chip; 4706 4707 if (chip->ops->bb_sethw) 4708 chip->ops->bb_sethw(rtwdev); 4709 } 4710 4711 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 4712 { 4713 const struct rtw89_chip_info *chip = rtwdev->chip; 4714 4715 if (chip->ops->rfk_init) 4716 chip->ops->rfk_init(rtwdev); 4717 } 4718 4719 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 4720 { 4721 const struct rtw89_chip_info *chip = rtwdev->chip; 4722 4723 if (chip->ops->rfk_channel) 4724 chip->ops->rfk_channel(rtwdev); 4725 } 4726 4727 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 4728 enum rtw89_phy_idx phy_idx) 4729 { 4730 const struct rtw89_chip_info *chip = rtwdev->chip; 4731 4732 if (chip->ops->rfk_band_changed) 4733 chip->ops->rfk_band_changed(rtwdev, phy_idx); 4734 } 4735 4736 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 4737 { 4738 const struct rtw89_chip_info *chip = rtwdev->chip; 4739 4740 if (chip->ops->rfk_scan) 4741 chip->ops->rfk_scan(rtwdev, start); 4742 } 4743 4744 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 4745 { 4746 const struct rtw89_chip_info *chip = rtwdev->chip; 4747 4748 if (chip->ops->rfk_track) 4749 chip->ops->rfk_track(rtwdev); 4750 } 4751 4752 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 4753 { 4754 const struct rtw89_chip_info *chip = rtwdev->chip; 4755 4756 if (chip->ops->set_txpwr_ctrl) 4757 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 4758 } 4759 4760 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 4761 { 4762 const struct rtw89_chip_info *chip = rtwdev->chip; 4763 4764 if (chip->ops->power_trim) 4765 chip->ops->power_trim(rtwdev); 4766 } 4767 4768 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 4769 enum rtw89_phy_idx phy_idx) 4770 { 4771 const struct rtw89_chip_info *chip = rtwdev->chip; 4772 4773 if (chip->ops->init_txpwr_unit) 4774 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 4775 } 4776 4777 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 4778 enum rtw89_rf_path rf_path) 4779 { 4780 const struct rtw89_chip_info *chip = rtwdev->chip; 4781 4782 if (!chip->ops->get_thermal) 4783 return 0x10; 4784 4785 return chip->ops->get_thermal(rtwdev, rf_path); 4786 } 4787 4788 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 4789 struct rtw89_rx_phy_ppdu *phy_ppdu, 4790 struct ieee80211_rx_status *status) 4791 { 4792 const struct rtw89_chip_info *chip = rtwdev->chip; 4793 4794 if (chip->ops->query_ppdu) 4795 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 4796 } 4797 4798 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, 4799 bool bt_en) 4800 { 4801 const struct rtw89_chip_info *chip = rtwdev->chip; 4802 4803 if (chip->ops->bb_ctrl_btc_preagc) 4804 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en); 4805 } 4806 4807 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 4808 { 4809 const struct rtw89_chip_info *chip = rtwdev->chip; 4810 4811 if (chip->ops->cfg_txrx_path) 4812 chip->ops->cfg_txrx_path(rtwdev); 4813 } 4814 4815 static inline 4816 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 4817 struct ieee80211_vif *vif) 4818 { 4819 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4820 const struct rtw89_chip_info *chip = rtwdev->chip; 4821 4822 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 4823 return; 4824 4825 if (chip->ops->set_txpwr_ul_tb_offset) 4826 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 4827 } 4828 4829 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 4830 const struct rtw89_txpwr_table *tbl) 4831 { 4832 tbl->load(rtwdev, tbl); 4833 } 4834 4835 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 4836 { 4837 return rtwdev->regd->txpwr_regd[band]; 4838 } 4839 4840 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 4841 { 4842 const struct rtw89_chip_info *chip = rtwdev->chip; 4843 4844 if (chip->ops->ctrl_btg) 4845 chip->ops->ctrl_btg(rtwdev, btg); 4846 } 4847 4848 static inline 4849 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 4850 struct rtw89_tx_desc_info *desc_info, 4851 void *txdesc) 4852 { 4853 const struct rtw89_chip_info *chip = rtwdev->chip; 4854 4855 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 4856 } 4857 4858 static inline 4859 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 4860 struct rtw89_tx_desc_info *desc_info, 4861 void *txdesc) 4862 { 4863 const struct rtw89_chip_info *chip = rtwdev->chip; 4864 4865 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 4866 } 4867 4868 static inline 4869 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 4870 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4871 { 4872 const struct rtw89_chip_info *chip = rtwdev->chip; 4873 4874 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 4875 } 4876 4877 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 4878 { 4879 const struct rtw89_chip_info *chip = rtwdev->chip; 4880 4881 chip->ops->cfg_ctrl_path(rtwdev, wl); 4882 } 4883 4884 static inline 4885 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 4886 u32 *tx_en, enum rtw89_sch_tx_sel sel) 4887 { 4888 const struct rtw89_chip_info *chip = rtwdev->chip; 4889 4890 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 4891 } 4892 4893 static inline 4894 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 4895 { 4896 const struct rtw89_chip_info *chip = rtwdev->chip; 4897 4898 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 4899 } 4900 4901 static inline 4902 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 4903 struct rtw89_vif *rtwvif, 4904 struct rtw89_sta *rtwsta) 4905 { 4906 const struct rtw89_chip_info *chip = rtwdev->chip; 4907 4908 if (!chip->ops->h2c_dctl_sec_cam) 4909 return 0; 4910 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 4911 } 4912 4913 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 4914 { 4915 __le16 fc = hdr->frame_control; 4916 4917 if (ieee80211_has_tods(fc)) 4918 return hdr->addr1; 4919 else if (ieee80211_has_fromds(fc)) 4920 return hdr->addr2; 4921 else 4922 return hdr->addr3; 4923 } 4924 4925 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 4926 { 4927 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 4928 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 4929 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 4930 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 4931 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 4932 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 4933 return true; 4934 return false; 4935 } 4936 4937 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 4938 enum rtw89_fw_type type) 4939 { 4940 struct rtw89_fw_info *fw_info = &rtwdev->fw; 4941 4942 if (type == RTW89_FW_WOWLAN) 4943 return &fw_info->wowlan; 4944 return &fw_info->normal; 4945 } 4946 4947 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 4948 unsigned int length) 4949 { 4950 struct sk_buff *skb; 4951 4952 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 4953 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 4954 if (!skb) 4955 return NULL; 4956 4957 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 4958 return skb; 4959 } 4960 4961 return dev_alloc_skb(length); 4962 } 4963 4964 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 4965 struct rtw89_tx_skb_data *skb_data, 4966 bool tx_done) 4967 { 4968 struct rtw89_tx_wait_info *wait; 4969 4970 rcu_read_lock(); 4971 4972 wait = rcu_dereference(skb_data->wait); 4973 if (!wait) 4974 goto out; 4975 4976 wait->tx_done = tx_done; 4977 complete(&wait->completion); 4978 4979 out: 4980 rcu_read_unlock(); 4981 } 4982 4983 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4984 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 4985 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 4986 struct sk_buff *skb, bool fwdl); 4987 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 4988 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4989 int qsel, unsigned int timeout); 4990 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 4991 struct rtw89_tx_desc_info *desc_info, 4992 void *txdesc); 4993 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 4994 struct rtw89_tx_desc_info *desc_info, 4995 void *txdesc); 4996 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 4997 struct rtw89_tx_desc_info *desc_info, 4998 void *txdesc); 4999 void rtw89_core_rx(struct rtw89_dev *rtwdev, 5000 struct rtw89_rx_desc_info *desc_info, 5001 struct sk_buff *skb); 5002 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 5003 struct rtw89_rx_desc_info *desc_info, 5004 u8 *data, u32 data_offset); 5005 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 5006 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 5007 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 5008 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 5009 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 5010 struct ieee80211_vif *vif, 5011 struct ieee80211_sta *sta); 5012 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 5013 struct ieee80211_vif *vif, 5014 struct ieee80211_sta *sta); 5015 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 5016 struct ieee80211_vif *vif, 5017 struct ieee80211_sta *sta); 5018 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 5019 struct ieee80211_vif *vif, 5020 struct ieee80211_sta *sta); 5021 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 5022 struct ieee80211_vif *vif, 5023 struct ieee80211_sta *sta); 5024 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 5025 struct ieee80211_sta *sta, 5026 struct cfg80211_tid_config *tid_config); 5027 int rtw89_core_init(struct rtw89_dev *rtwdev); 5028 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 5029 int rtw89_core_register(struct rtw89_dev *rtwdev); 5030 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 5031 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 5032 u32 bus_data_size, 5033 const struct rtw89_chip_info *chip); 5034 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 5035 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 5036 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 5037 void rtw89_set_channel(struct rtw89_dev *rtwdev); 5038 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5039 struct rtw89_chan *chan); 5040 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 5041 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 5042 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 5043 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 5044 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 5045 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 5046 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 5047 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 5048 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 5049 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 5050 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 5051 int rtw89_regd_init(struct rtw89_dev *rtwdev, 5052 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 5053 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 5054 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 5055 struct rtw89_traffic_stats *stats); 5056 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 5057 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 5058 const struct rtw89_completion_data *data); 5059 int rtw89_core_start(struct rtw89_dev *rtwdev); 5060 void rtw89_core_stop(struct rtw89_dev *rtwdev); 5061 void rtw89_core_update_beacon_work(struct work_struct *work); 5062 void rtw89_roc_work(struct work_struct *work); 5063 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 5064 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 5065 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5066 const u8 *mac_addr, bool hw_scan); 5067 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 5068 struct ieee80211_vif *vif, bool hw_scan); 5069 5070 #endif 5071