1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 18 extern const struct ieee80211_ops rtw89_ops; 19 20 #define MASKBYTE0 0xff 21 #define MASKBYTE1 0xff00 22 #define MASKBYTE2 0xff0000 23 #define MASKBYTE3 0xff000000 24 #define MASKBYTE4 0xff00000000ULL 25 #define MASKHWORD 0xffff0000 26 #define MASKLWORD 0x0000ffff 27 #define MASKDWORD 0xffffffff 28 #define RFREG_MASK 0xfffff 29 #define INV_RF_DATA 0xffffffff 30 31 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 32 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 33 #define CFO_TRACK_MAX_USER 64 34 #define MAX_RSSI 110 35 #define RSSI_FACTOR 1 36 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 37 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 38 #define RTW89_RADIOTAP_ROOM ALIGN(sizeof(struct ieee80211_radiotap_he), 64) 39 40 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 41 #define RTW89_HTC_VARIANT_HE 3 42 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 43 #define RTW89_HTC_VARIANT_HE_CID_OM 1 44 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 45 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 46 47 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 48 enum htc_om_channel_width { 49 HTC_OM_CHANNEL_WIDTH_20 = 0, 50 HTC_OM_CHANNEL_WIDTH_40 = 1, 51 HTC_OM_CHANNEL_WIDTH_80 = 2, 52 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 53 }; 54 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 55 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 56 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 57 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 58 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 59 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 60 61 #define RTW89_TF_PAD GENMASK(11, 0) 62 #define RTW89_TF_BASIC_USER_INFO_SZ 6 63 64 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 65 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 66 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 67 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 68 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 69 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 70 71 enum rtw89_subband { 72 RTW89_CH_2G = 0, 73 RTW89_CH_5G_BAND_1 = 1, 74 /* RTW89_CH_5G_BAND_2 = 2, unused */ 75 RTW89_CH_5G_BAND_3 = 3, 76 RTW89_CH_5G_BAND_4 = 4, 77 78 RTW89_CH_6G_BAND_IDX0, /* Low */ 79 RTW89_CH_6G_BAND_IDX1, /* Low */ 80 RTW89_CH_6G_BAND_IDX2, /* Mid */ 81 RTW89_CH_6G_BAND_IDX3, /* Mid */ 82 RTW89_CH_6G_BAND_IDX4, /* High */ 83 RTW89_CH_6G_BAND_IDX5, /* High */ 84 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 85 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 86 87 RTW89_SUBBAND_NR, 88 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 89 }; 90 91 enum rtw89_gain_offset { 92 RTW89_GAIN_OFFSET_2G_CCK, 93 RTW89_GAIN_OFFSET_2G_OFDM, 94 RTW89_GAIN_OFFSET_5G_LOW, 95 RTW89_GAIN_OFFSET_5G_MID, 96 RTW89_GAIN_OFFSET_5G_HIGH, 97 98 RTW89_GAIN_OFFSET_NR, 99 }; 100 101 enum rtw89_hci_type { 102 RTW89_HCI_TYPE_PCIE, 103 RTW89_HCI_TYPE_USB, 104 RTW89_HCI_TYPE_SDIO, 105 }; 106 107 enum rtw89_core_chip_id { 108 RTL8852A, 109 RTL8852B, 110 RTL8852C, 111 }; 112 113 enum rtw89_cv { 114 CHIP_CAV, 115 CHIP_CBV, 116 CHIP_CCV, 117 CHIP_CDV, 118 CHIP_CEV, 119 CHIP_CFV, 120 CHIP_CV_MAX, 121 CHIP_CV_INVALID = CHIP_CV_MAX, 122 }; 123 124 enum rtw89_core_tx_type { 125 RTW89_CORE_TX_TYPE_DATA, 126 RTW89_CORE_TX_TYPE_MGMT, 127 RTW89_CORE_TX_TYPE_FWCMD, 128 }; 129 130 enum rtw89_core_rx_type { 131 RTW89_CORE_RX_TYPE_WIFI = 0, 132 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 133 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 134 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 135 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 136 RTW89_CORE_RX_TYPE_SS2FW = 5, 137 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 138 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 139 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 140 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 141 RTW89_CORE_RX_TYPE_C2H = 10, 142 RTW89_CORE_RX_TYPE_CSI = 11, 143 RTW89_CORE_RX_TYPE_CQI = 12, 144 RTW89_CORE_RX_TYPE_H2C = 13, 145 RTW89_CORE_RX_TYPE_FWDL = 14, 146 }; 147 148 enum rtw89_txq_flags { 149 RTW89_TXQ_F_AMPDU = 0, 150 RTW89_TXQ_F_BLOCK_BA = 1, 151 RTW89_TXQ_F_FORBID_BA = 2, 152 }; 153 154 enum rtw89_net_type { 155 RTW89_NET_TYPE_NO_LINK = 0, 156 RTW89_NET_TYPE_AD_HOC = 1, 157 RTW89_NET_TYPE_INFRA = 2, 158 RTW89_NET_TYPE_AP_MODE = 3, 159 }; 160 161 enum rtw89_wifi_role { 162 RTW89_WIFI_ROLE_NONE, 163 RTW89_WIFI_ROLE_STATION, 164 RTW89_WIFI_ROLE_AP, 165 RTW89_WIFI_ROLE_AP_VLAN, 166 RTW89_WIFI_ROLE_ADHOC, 167 RTW89_WIFI_ROLE_ADHOC_MASTER, 168 RTW89_WIFI_ROLE_MESH_POINT, 169 RTW89_WIFI_ROLE_MONITOR, 170 RTW89_WIFI_ROLE_P2P_DEVICE, 171 RTW89_WIFI_ROLE_P2P_CLIENT, 172 RTW89_WIFI_ROLE_P2P_GO, 173 RTW89_WIFI_ROLE_NAN, 174 RTW89_WIFI_ROLE_MLME_MAX 175 }; 176 177 enum rtw89_upd_mode { 178 RTW89_ROLE_CREATE, 179 RTW89_ROLE_REMOVE, 180 RTW89_ROLE_TYPE_CHANGE, 181 RTW89_ROLE_INFO_CHANGE, 182 RTW89_ROLE_CON_DISCONN, 183 RTW89_ROLE_BAND_SW, 184 RTW89_ROLE_FW_RESTORE, 185 }; 186 187 enum rtw89_self_role { 188 RTW89_SELF_ROLE_CLIENT, 189 RTW89_SELF_ROLE_AP, 190 RTW89_SELF_ROLE_AP_CLIENT 191 }; 192 193 enum rtw89_msk_sO_el { 194 RTW89_NO_MSK, 195 RTW89_SMA, 196 RTW89_TMA, 197 RTW89_BSSID 198 }; 199 200 enum rtw89_sch_tx_sel { 201 RTW89_SCH_TX_SEL_ALL, 202 RTW89_SCH_TX_SEL_HIQ, 203 RTW89_SCH_TX_SEL_MG0, 204 RTW89_SCH_TX_SEL_MACID, 205 }; 206 207 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 208 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 209 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 210 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 211 */ 212 enum rtw89_add_cam_sec_mode { 213 RTW89_ADDR_CAM_SEC_NONE = 0, 214 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 215 RTW89_ADDR_CAM_SEC_NORMAL = 2, 216 RTW89_ADDR_CAM_SEC_4GROUP = 3, 217 }; 218 219 enum rtw89_sec_key_type { 220 RTW89_SEC_KEY_TYPE_NONE = 0, 221 RTW89_SEC_KEY_TYPE_WEP40 = 1, 222 RTW89_SEC_KEY_TYPE_WEP104 = 2, 223 RTW89_SEC_KEY_TYPE_TKIP = 3, 224 RTW89_SEC_KEY_TYPE_WAPI = 4, 225 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 226 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 227 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 228 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 229 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 230 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 231 }; 232 233 enum rtw89_port { 234 RTW89_PORT_0 = 0, 235 RTW89_PORT_1 = 1, 236 RTW89_PORT_2 = 2, 237 RTW89_PORT_3 = 3, 238 RTW89_PORT_4 = 4, 239 RTW89_PORT_NUM 240 }; 241 242 enum rtw89_band { 243 RTW89_BAND_2G = 0, 244 RTW89_BAND_5G = 1, 245 RTW89_BAND_6G = 2, 246 RTW89_BAND_MAX, 247 }; 248 249 enum rtw89_hw_rate { 250 RTW89_HW_RATE_CCK1 = 0x0, 251 RTW89_HW_RATE_CCK2 = 0x1, 252 RTW89_HW_RATE_CCK5_5 = 0x2, 253 RTW89_HW_RATE_CCK11 = 0x3, 254 RTW89_HW_RATE_OFDM6 = 0x4, 255 RTW89_HW_RATE_OFDM9 = 0x5, 256 RTW89_HW_RATE_OFDM12 = 0x6, 257 RTW89_HW_RATE_OFDM18 = 0x7, 258 RTW89_HW_RATE_OFDM24 = 0x8, 259 RTW89_HW_RATE_OFDM36 = 0x9, 260 RTW89_HW_RATE_OFDM48 = 0xA, 261 RTW89_HW_RATE_OFDM54 = 0xB, 262 RTW89_HW_RATE_MCS0 = 0x80, 263 RTW89_HW_RATE_MCS1 = 0x81, 264 RTW89_HW_RATE_MCS2 = 0x82, 265 RTW89_HW_RATE_MCS3 = 0x83, 266 RTW89_HW_RATE_MCS4 = 0x84, 267 RTW89_HW_RATE_MCS5 = 0x85, 268 RTW89_HW_RATE_MCS6 = 0x86, 269 RTW89_HW_RATE_MCS7 = 0x87, 270 RTW89_HW_RATE_MCS8 = 0x88, 271 RTW89_HW_RATE_MCS9 = 0x89, 272 RTW89_HW_RATE_MCS10 = 0x8A, 273 RTW89_HW_RATE_MCS11 = 0x8B, 274 RTW89_HW_RATE_MCS12 = 0x8C, 275 RTW89_HW_RATE_MCS13 = 0x8D, 276 RTW89_HW_RATE_MCS14 = 0x8E, 277 RTW89_HW_RATE_MCS15 = 0x8F, 278 RTW89_HW_RATE_MCS16 = 0x90, 279 RTW89_HW_RATE_MCS17 = 0x91, 280 RTW89_HW_RATE_MCS18 = 0x92, 281 RTW89_HW_RATE_MCS19 = 0x93, 282 RTW89_HW_RATE_MCS20 = 0x94, 283 RTW89_HW_RATE_MCS21 = 0x95, 284 RTW89_HW_RATE_MCS22 = 0x96, 285 RTW89_HW_RATE_MCS23 = 0x97, 286 RTW89_HW_RATE_MCS24 = 0x98, 287 RTW89_HW_RATE_MCS25 = 0x99, 288 RTW89_HW_RATE_MCS26 = 0x9A, 289 RTW89_HW_RATE_MCS27 = 0x9B, 290 RTW89_HW_RATE_MCS28 = 0x9C, 291 RTW89_HW_RATE_MCS29 = 0x9D, 292 RTW89_HW_RATE_MCS30 = 0x9E, 293 RTW89_HW_RATE_MCS31 = 0x9F, 294 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 295 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 296 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 297 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 298 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 299 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 300 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 301 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 302 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 303 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 304 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 305 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 306 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 307 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 308 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 309 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 310 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 311 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 312 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 313 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 314 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 315 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 316 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 317 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 318 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 319 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 320 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 321 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 322 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 323 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 324 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 325 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 326 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 327 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 328 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 329 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 330 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 331 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 332 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 333 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 334 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 335 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 336 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 337 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 338 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 339 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 340 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 341 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 342 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 343 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 344 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 345 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 346 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 347 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 348 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 349 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 350 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 351 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 352 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 353 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 354 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 355 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 356 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 357 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 358 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 359 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 360 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 361 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 362 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 363 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 364 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 365 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 366 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 367 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 368 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 369 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 370 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 371 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 372 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 373 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 374 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 375 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 376 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 377 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 378 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 379 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 380 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 381 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 382 RTW89_HW_RATE_NR, 383 384 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 385 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 386 }; 387 388 /* 2G channels, 389 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 390 */ 391 #define RTW89_2G_CH_NUM 14 392 393 /* 5G channels, 394 * 36, 38, 40, 42, 44, 46, 48, 50, 395 * 52, 54, 56, 58, 60, 62, 64, 396 * 100, 102, 104, 106, 108, 110, 112, 114, 397 * 116, 118, 120, 122, 124, 126, 128, 130, 398 * 132, 134, 136, 138, 140, 142, 144, 399 * 149, 151, 153, 155, 157, 159, 161, 163, 400 * 165, 167, 169, 171, 173, 175, 177 401 */ 402 #define RTW89_5G_CH_NUM 53 403 404 /* 6G channels, 405 * 1, 3, 5, 7, 9, 11, 13, 15, 406 * 17, 19, 21, 23, 25, 27, 29, 33, 407 * 35, 37, 39, 41, 43, 45, 47, 49, 408 * 51, 53, 55, 57, 59, 61, 65, 67, 409 * 69, 71, 73, 75, 77, 79, 81, 83, 410 * 85, 87, 89, 91, 93, 97, 99, 101, 411 * 103, 105, 107, 109, 111, 113, 115, 117, 412 * 119, 121, 123, 125, 129, 131, 133, 135, 413 * 137, 139, 141, 143, 145, 147, 149, 151, 414 * 153, 155, 157, 161, 163, 165, 167, 169, 415 * 171, 173, 175, 177, 179, 181, 183, 185, 416 * 187, 189, 193, 195, 197, 199, 201, 203, 417 * 205, 207, 209, 211, 213, 215, 217, 219, 418 * 221, 225, 227, 229, 231, 233, 235, 237, 419 * 239, 241, 243, 245, 247, 249, 251, 253, 420 */ 421 #define RTW89_6G_CH_NUM 120 422 423 enum rtw89_rate_section { 424 RTW89_RS_CCK, 425 RTW89_RS_OFDM, 426 RTW89_RS_MCS, /* for HT/VHT/HE */ 427 RTW89_RS_HEDCM, 428 RTW89_RS_OFFSET, 429 RTW89_RS_MAX, 430 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 431 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 432 }; 433 434 enum rtw89_rate_max { 435 RTW89_RATE_CCK_MAX = 4, 436 RTW89_RATE_OFDM_MAX = 8, 437 RTW89_RATE_MCS_MAX = 12, 438 RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */ 439 RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */ 440 }; 441 442 enum rtw89_nss { 443 RTW89_NSS_1 = 0, 444 RTW89_NSS_2 = 1, 445 /* HE DCM only support 1ss and 2ss */ 446 RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1, 447 RTW89_NSS_3 = 2, 448 RTW89_NSS_4 = 3, 449 RTW89_NSS_MAX, 450 }; 451 452 enum rtw89_ntx { 453 RTW89_1TX = 0, 454 RTW89_2TX = 1, 455 RTW89_NTX_NUM, 456 }; 457 458 enum rtw89_beamforming_type { 459 RTW89_NONBF = 0, 460 RTW89_BF = 1, 461 RTW89_BF_NUM, 462 }; 463 464 enum rtw89_regulation_type { 465 RTW89_WW = 0, 466 RTW89_ETSI = 1, 467 RTW89_FCC = 2, 468 RTW89_MKK = 3, 469 RTW89_NA = 4, 470 RTW89_IC = 5, 471 RTW89_KCC = 6, 472 RTW89_ACMA = 7, 473 RTW89_NCC = 8, 474 RTW89_MEXICO = 9, 475 RTW89_CHILE = 10, 476 RTW89_UKRAINE = 11, 477 RTW89_CN = 12, 478 RTW89_QATAR = 13, 479 RTW89_UK = 14, 480 RTW89_REGD_NUM, 481 }; 482 483 enum rtw89_fw_pkt_ofld_type { 484 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 485 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 486 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 487 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 488 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 489 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 490 RTW89_PKT_OFLD_TYPE_NDP = 6, 491 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 492 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 493 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 494 RTW89_PKT_OFLD_TYPE_NUM, 495 }; 496 497 struct rtw89_txpwr_byrate { 498 s8 cck[RTW89_RATE_CCK_MAX]; 499 s8 ofdm[RTW89_RATE_OFDM_MAX]; 500 s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX]; 501 s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX]; 502 s8 offset[RTW89_RATE_OFFSET_MAX]; 503 }; 504 505 enum rtw89_bandwidth_section_num { 506 RTW89_BW20_SEC_NUM = 8, 507 RTW89_BW40_SEC_NUM = 4, 508 RTW89_BW80_SEC_NUM = 2, 509 }; 510 511 #define RTW89_TXPWR_LMT_PAGE_SIZE 40 512 513 struct rtw89_txpwr_limit { 514 s8 cck_20m[RTW89_BF_NUM]; 515 s8 cck_40m[RTW89_BF_NUM]; 516 s8 ofdm[RTW89_BF_NUM]; 517 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM]; 518 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM]; 519 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM]; 520 s8 mcs_160m[RTW89_BF_NUM]; 521 s8 mcs_40m_0p5[RTW89_BF_NUM]; 522 s8 mcs_40m_2p5[RTW89_BF_NUM]; 523 }; 524 525 #define RTW89_RU_SEC_NUM 8 526 527 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE 24 528 529 struct rtw89_txpwr_limit_ru { 530 s8 ru26[RTW89_RU_SEC_NUM]; 531 s8 ru52[RTW89_RU_SEC_NUM]; 532 s8 ru106[RTW89_RU_SEC_NUM]; 533 }; 534 535 struct rtw89_rate_desc { 536 enum rtw89_nss nss; 537 enum rtw89_rate_section rs; 538 u8 idx; 539 }; 540 541 #define PHY_STS_HDR_LEN 8 542 #define RF_PATH_MAX 4 543 #define RTW89_MAX_PPDU_CNT 8 544 struct rtw89_rx_phy_ppdu { 545 u8 *buf; 546 u32 len; 547 u8 rssi_avg; 548 u8 rssi[RF_PATH_MAX]; 549 u8 mac_id; 550 u8 chan_idx; 551 u8 ie; 552 u16 rate; 553 bool to_self; 554 bool valid; 555 }; 556 557 enum rtw89_mac_idx { 558 RTW89_MAC_0 = 0, 559 RTW89_MAC_1 = 1, 560 }; 561 562 enum rtw89_phy_idx { 563 RTW89_PHY_0 = 0, 564 RTW89_PHY_1 = 1, 565 RTW89_PHY_MAX 566 }; 567 568 enum rtw89_sub_entity_idx { 569 RTW89_SUB_ENTITY_0 = 0, 570 571 NUM_OF_RTW89_SUB_ENTITY, 572 }; 573 574 enum rtw89_rf_path { 575 RF_PATH_A = 0, 576 RF_PATH_B = 1, 577 RF_PATH_C = 2, 578 RF_PATH_D = 3, 579 RF_PATH_AB, 580 RF_PATH_AC, 581 RF_PATH_AD, 582 RF_PATH_BC, 583 RF_PATH_BD, 584 RF_PATH_CD, 585 RF_PATH_ABC, 586 RF_PATH_ABD, 587 RF_PATH_ACD, 588 RF_PATH_BCD, 589 RF_PATH_ABCD, 590 }; 591 592 enum rtw89_rf_path_bit { 593 RF_A = BIT(0), 594 RF_B = BIT(1), 595 RF_C = BIT(2), 596 RF_D = BIT(3), 597 598 RF_AB = (RF_A | RF_B), 599 RF_AC = (RF_A | RF_C), 600 RF_AD = (RF_A | RF_D), 601 RF_BC = (RF_B | RF_C), 602 RF_BD = (RF_B | RF_D), 603 RF_CD = (RF_C | RF_D), 604 605 RF_ABC = (RF_A | RF_B | RF_C), 606 RF_ABD = (RF_A | RF_B | RF_D), 607 RF_ACD = (RF_A | RF_C | RF_D), 608 RF_BCD = (RF_B | RF_C | RF_D), 609 610 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 611 }; 612 613 enum rtw89_bandwidth { 614 RTW89_CHANNEL_WIDTH_20 = 0, 615 RTW89_CHANNEL_WIDTH_40 = 1, 616 RTW89_CHANNEL_WIDTH_80 = 2, 617 RTW89_CHANNEL_WIDTH_160 = 3, 618 RTW89_CHANNEL_WIDTH_80_80 = 4, 619 RTW89_CHANNEL_WIDTH_5 = 5, 620 RTW89_CHANNEL_WIDTH_10 = 6, 621 }; 622 623 enum rtw89_ps_mode { 624 RTW89_PS_MODE_NONE = 0, 625 RTW89_PS_MODE_RFOFF = 1, 626 RTW89_PS_MODE_CLK_GATED = 2, 627 RTW89_PS_MODE_PWR_GATED = 3, 628 }; 629 630 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 631 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 632 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 633 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 634 635 enum rtw89_ru_bandwidth { 636 RTW89_RU26 = 0, 637 RTW89_RU52 = 1, 638 RTW89_RU106 = 2, 639 RTW89_RU_NUM, 640 }; 641 642 enum rtw89_sc_offset { 643 RTW89_SC_DONT_CARE = 0, 644 RTW89_SC_20_UPPER = 1, 645 RTW89_SC_20_LOWER = 2, 646 RTW89_SC_20_UPMOST = 3, 647 RTW89_SC_20_LOWEST = 4, 648 RTW89_SC_20_UP2X = 5, 649 RTW89_SC_20_LOW2X = 6, 650 RTW89_SC_20_UP3X = 7, 651 RTW89_SC_20_LOW3X = 8, 652 RTW89_SC_40_UPPER = 9, 653 RTW89_SC_40_LOWER = 10, 654 }; 655 656 enum rtw89_wow_flags { 657 RTW89_WOW_FLAG_EN_MAGIC_PKT, 658 RTW89_WOW_FLAG_EN_REKEY_PKT, 659 RTW89_WOW_FLAG_EN_DISCONNECT, 660 RTW89_WOW_FLAG_NUM, 661 }; 662 663 struct rtw89_chan { 664 u8 channel; 665 u8 primary_channel; 666 enum rtw89_band band_type; 667 enum rtw89_bandwidth band_width; 668 669 /* The follow-up are derived from the above. We must ensure that it 670 * is assigned correctly in rtw89_chan_create() if new one is added. 671 */ 672 u32 freq; 673 enum rtw89_subband subband_type; 674 enum rtw89_sc_offset pri_ch_idx; 675 }; 676 677 struct rtw89_chan_rcd { 678 u8 prev_primary_channel; 679 enum rtw89_band prev_band_type; 680 }; 681 682 struct rtw89_channel_help_params { 683 u32 tx_en; 684 }; 685 686 struct rtw89_port_reg { 687 u32 port_cfg; 688 u32 tbtt_prohib; 689 u32 bcn_area; 690 u32 bcn_early; 691 u32 tbtt_early; 692 u32 tbtt_agg; 693 u32 bcn_space; 694 u32 bcn_forcetx; 695 u32 bcn_err_cnt; 696 u32 bcn_err_flag; 697 u32 dtim_ctrl; 698 u32 tbtt_shift; 699 u32 bcn_cnt_tmr; 700 u32 tsftr_l; 701 u32 tsftr_h; 702 }; 703 704 struct rtw89_txwd_body { 705 __le32 dword0; 706 __le32 dword1; 707 __le32 dword2; 708 __le32 dword3; 709 __le32 dword4; 710 __le32 dword5; 711 } __packed; 712 713 struct rtw89_txwd_body_v1 { 714 __le32 dword0; 715 __le32 dword1; 716 __le32 dword2; 717 __le32 dword3; 718 __le32 dword4; 719 __le32 dword5; 720 __le32 dword6; 721 __le32 dword7; 722 } __packed; 723 724 struct rtw89_txwd_info { 725 __le32 dword0; 726 __le32 dword1; 727 __le32 dword2; 728 __le32 dword3; 729 __le32 dword4; 730 __le32 dword5; 731 } __packed; 732 733 struct rtw89_rx_desc_info { 734 u16 pkt_size; 735 u8 pkt_type; 736 u8 drv_info_size; 737 u8 shift; 738 u8 wl_hd_iv_len; 739 bool long_rxdesc; 740 bool bb_sel; 741 bool mac_info_valid; 742 u16 data_rate; 743 u8 gi_ltf; 744 u8 bw; 745 u32 free_run_cnt; 746 u8 user_id; 747 bool sr_en; 748 u8 ppdu_cnt; 749 u8 ppdu_type; 750 bool icv_err; 751 bool crc32_err; 752 bool hw_dec; 753 bool sw_dec; 754 bool addr1_match; 755 u8 frag; 756 u16 seq; 757 u8 frame_type; 758 u8 rx_pl_id; 759 bool addr_cam_valid; 760 u8 addr_cam_id; 761 u8 sec_cam_id; 762 u8 mac_id; 763 u16 offset; 764 bool ready; 765 }; 766 767 struct rtw89_rxdesc_short { 768 __le32 dword0; 769 __le32 dword1; 770 __le32 dword2; 771 __le32 dword3; 772 } __packed; 773 774 struct rtw89_rxdesc_long { 775 __le32 dword0; 776 __le32 dword1; 777 __le32 dword2; 778 __le32 dword3; 779 __le32 dword4; 780 __le32 dword5; 781 __le32 dword6; 782 __le32 dword7; 783 } __packed; 784 785 struct rtw89_tx_desc_info { 786 u16 pkt_size; 787 u8 wp_offset; 788 u8 mac_id; 789 u8 qsel; 790 u8 ch_dma; 791 u8 hdr_llc_len; 792 bool is_bmc; 793 bool en_wd_info; 794 bool wd_page; 795 bool use_rate; 796 bool dis_data_fb; 797 bool tid_indicate; 798 bool agg_en; 799 bool bk; 800 u8 ampdu_density; 801 u8 ampdu_num; 802 bool sec_en; 803 u8 addr_info_nr; 804 u8 sec_keyid; 805 u8 sec_type; 806 u8 sec_cam_idx; 807 u8 sec_seq[6]; 808 u16 data_rate; 809 u16 data_retry_lowest_rate; 810 bool fw_dl; 811 u16 seq; 812 bool a_ctrl_bsr; 813 u8 hw_ssn_sel; 814 #define RTW89_MGMT_HW_SSN_SEL 1 815 u8 hw_seq_mode; 816 #define RTW89_MGMT_HW_SEQ_MODE 1 817 bool hiq; 818 u8 port; 819 bool er_cap; 820 }; 821 822 struct rtw89_core_tx_request { 823 enum rtw89_core_tx_type tx_type; 824 825 struct sk_buff *skb; 826 struct ieee80211_vif *vif; 827 struct ieee80211_sta *sta; 828 struct rtw89_tx_desc_info desc_info; 829 }; 830 831 struct rtw89_txq { 832 struct list_head list; 833 unsigned long flags; 834 int wait_cnt; 835 }; 836 837 struct rtw89_mac_ax_gnt { 838 u8 gnt_bt_sw_en; 839 u8 gnt_bt; 840 u8 gnt_wl_sw_en; 841 u8 gnt_wl; 842 } __packed; 843 844 #define RTW89_MAC_AX_COEX_GNT_NR 2 845 struct rtw89_mac_ax_coex_gnt { 846 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 847 }; 848 849 enum rtw89_btc_ncnt { 850 BTC_NCNT_POWER_ON = 0x0, 851 BTC_NCNT_POWER_OFF, 852 BTC_NCNT_INIT_COEX, 853 BTC_NCNT_SCAN_START, 854 BTC_NCNT_SCAN_FINISH, 855 BTC_NCNT_SPECIAL_PACKET, 856 BTC_NCNT_SWITCH_BAND, 857 BTC_NCNT_RFK_TIMEOUT, 858 BTC_NCNT_SHOW_COEX_INFO, 859 BTC_NCNT_ROLE_INFO, 860 BTC_NCNT_CONTROL, 861 BTC_NCNT_RADIO_STATE, 862 BTC_NCNT_CUSTOMERIZE, 863 BTC_NCNT_WL_RFK, 864 BTC_NCNT_WL_STA, 865 BTC_NCNT_FWINFO, 866 BTC_NCNT_TIMER, 867 BTC_NCNT_NUM 868 }; 869 870 enum rtw89_btc_btinfo { 871 BTC_BTINFO_L0 = 0, 872 BTC_BTINFO_L1, 873 BTC_BTINFO_L2, 874 BTC_BTINFO_L3, 875 BTC_BTINFO_H0, 876 BTC_BTINFO_H1, 877 BTC_BTINFO_H2, 878 BTC_BTINFO_H3, 879 BTC_BTINFO_MAX 880 }; 881 882 enum rtw89_btc_dcnt { 883 BTC_DCNT_RUN = 0x0, 884 BTC_DCNT_CX_RUNINFO, 885 BTC_DCNT_RPT, 886 BTC_DCNT_RPT_FREEZE, 887 BTC_DCNT_CYCLE, 888 BTC_DCNT_CYCLE_FREEZE, 889 BTC_DCNT_W1, 890 BTC_DCNT_W1_FREEZE, 891 BTC_DCNT_B1, 892 BTC_DCNT_B1_FREEZE, 893 BTC_DCNT_TDMA_NONSYNC, 894 BTC_DCNT_SLOT_NONSYNC, 895 BTC_DCNT_BTCNT_FREEZE, 896 BTC_DCNT_WL_SLOT_DRIFT, 897 BTC_DCNT_BT_SLOT_DRIFT, 898 BTC_DCNT_WL_STA_LAST, 899 BTC_DCNT_NUM, 900 }; 901 902 enum rtw89_btc_wl_state_cnt { 903 BTC_WCNT_SCANAP = 0x0, 904 BTC_WCNT_DHCP, 905 BTC_WCNT_EAPOL, 906 BTC_WCNT_ARP, 907 BTC_WCNT_SCBDUPDATE, 908 BTC_WCNT_RFK_REQ, 909 BTC_WCNT_RFK_GO, 910 BTC_WCNT_RFK_REJECT, 911 BTC_WCNT_RFK_TIMEOUT, 912 BTC_WCNT_CH_UPDATE, 913 BTC_WCNT_NUM 914 }; 915 916 enum rtw89_btc_bt_state_cnt { 917 BTC_BCNT_RETRY = 0x0, 918 BTC_BCNT_REINIT, 919 BTC_BCNT_REENABLE, 920 BTC_BCNT_SCBDREAD, 921 BTC_BCNT_RELINK, 922 BTC_BCNT_IGNOWL, 923 BTC_BCNT_INQPAG, 924 BTC_BCNT_INQ, 925 BTC_BCNT_PAGE, 926 BTC_BCNT_ROLESW, 927 BTC_BCNT_AFH, 928 BTC_BCNT_INFOUPDATE, 929 BTC_BCNT_INFOSAME, 930 BTC_BCNT_SCBDUPDATE, 931 BTC_BCNT_HIPRI_TX, 932 BTC_BCNT_HIPRI_RX, 933 BTC_BCNT_LOPRI_TX, 934 BTC_BCNT_LOPRI_RX, 935 BTC_BCNT_POLUT, 936 BTC_BCNT_RATECHG, 937 BTC_BCNT_NUM 938 }; 939 940 enum rtw89_btc_bt_profile { 941 BTC_BT_NOPROFILE = 0, 942 BTC_BT_HFP = BIT(0), 943 BTC_BT_HID = BIT(1), 944 BTC_BT_A2DP = BIT(2), 945 BTC_BT_PAN = BIT(3), 946 BTC_PROFILE_MAX = 4, 947 }; 948 949 struct rtw89_btc_ant_info { 950 u8 type; /* shared, dedicated */ 951 u8 num; 952 u8 isolation; 953 954 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 955 u8 diversity: 1; 956 }; 957 958 enum rtw89_tfc_dir { 959 RTW89_TFC_UL, 960 RTW89_TFC_DL, 961 }; 962 963 struct rtw89_btc_wl_smap { 964 u32 busy: 1; 965 u32 scan: 1; 966 u32 connecting: 1; 967 u32 roaming: 1; 968 u32 _4way: 1; 969 u32 rf_off: 1; 970 u32 lps: 2; 971 u32 ips: 1; 972 u32 init_ok: 1; 973 u32 traffic_dir : 2; 974 u32 rf_off_pre: 1; 975 u32 lps_pre: 2; 976 }; 977 978 enum rtw89_tfc_lv { 979 RTW89_TFC_IDLE, 980 RTW89_TFC_ULTRA_LOW, 981 RTW89_TFC_LOW, 982 RTW89_TFC_MID, 983 RTW89_TFC_HIGH, 984 }; 985 986 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 987 DECLARE_EWMA(tp, 10, 2); 988 989 struct rtw89_traffic_stats { 990 /* units in bytes */ 991 u64 tx_unicast; 992 u64 rx_unicast; 993 u32 tx_avg_len; 994 u32 rx_avg_len; 995 996 /* count for packets */ 997 u64 tx_cnt; 998 u64 rx_cnt; 999 1000 /* units in Mbps */ 1001 u32 tx_throughput; 1002 u32 rx_throughput; 1003 u32 tx_throughput_raw; 1004 u32 rx_throughput_raw; 1005 1006 u32 rx_tf_acc; 1007 u32 rx_tf_periodic; 1008 1009 enum rtw89_tfc_lv tx_tfc_lv; 1010 enum rtw89_tfc_lv rx_tfc_lv; 1011 struct ewma_tp tx_ewma_tp; 1012 struct ewma_tp rx_ewma_tp; 1013 1014 u16 tx_rate; 1015 u16 rx_rate; 1016 }; 1017 1018 struct rtw89_btc_statistic { 1019 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1020 struct rtw89_traffic_stats traffic; 1021 }; 1022 1023 #define BTC_WL_RSSI_THMAX 4 1024 1025 struct rtw89_btc_wl_link_info { 1026 struct rtw89_btc_statistic stat; 1027 enum rtw89_tfc_dir dir; 1028 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1029 u8 mac_addr[ETH_ALEN]; 1030 u8 busy; 1031 u8 ch; 1032 u8 bw; 1033 u8 band; 1034 u8 role; 1035 u8 pid; 1036 u8 phy; 1037 u8 dtim_period; 1038 u8 mode; 1039 1040 u8 mac_id; 1041 u8 tx_retry; 1042 1043 u32 bcn_period; 1044 u32 busy_t; 1045 u32 tx_time; 1046 u32 client_cnt; 1047 u32 rx_rate_drop_cnt; 1048 1049 u32 active: 1; 1050 u32 noa: 1; 1051 u32 client_ps: 1; 1052 u32 connected: 2; 1053 }; 1054 1055 union rtw89_btc_wl_state_map { 1056 u32 val; 1057 struct rtw89_btc_wl_smap map; 1058 }; 1059 1060 struct rtw89_btc_bt_hfp_desc { 1061 u32 exist: 1; 1062 u32 type: 2; 1063 u32 rsvd: 29; 1064 }; 1065 1066 struct rtw89_btc_bt_hid_desc { 1067 u32 exist: 1; 1068 u32 slot_info: 2; 1069 u32 pair_cnt: 2; 1070 u32 type: 8; 1071 u32 rsvd: 19; 1072 }; 1073 1074 struct rtw89_btc_bt_a2dp_desc { 1075 u8 exist: 1; 1076 u8 exist_last: 1; 1077 u8 play_latency: 1; 1078 u8 type: 3; 1079 u8 active: 1; 1080 u8 sink: 1; 1081 1082 u8 bitpool; 1083 u16 vendor_id; 1084 u32 device_name; 1085 u32 flush_time; 1086 }; 1087 1088 struct rtw89_btc_bt_pan_desc { 1089 u32 exist: 1; 1090 u32 type: 1; 1091 u32 active: 1; 1092 u32 rsvd: 29; 1093 }; 1094 1095 struct rtw89_btc_bt_rfk_info { 1096 u32 run: 1; 1097 u32 req: 1; 1098 u32 timeout: 1; 1099 u32 rsvd: 29; 1100 }; 1101 1102 union rtw89_btc_bt_rfk_info_map { 1103 u32 val; 1104 struct rtw89_btc_bt_rfk_info map; 1105 }; 1106 1107 struct rtw89_btc_bt_ver_info { 1108 u32 fw_coex; /* match with which coex_ver */ 1109 u32 fw; 1110 }; 1111 1112 struct rtw89_btc_bool_sta_chg { 1113 u32 now: 1; 1114 u32 last: 1; 1115 u32 remain: 1; 1116 u32 srvd: 29; 1117 }; 1118 1119 struct rtw89_btc_u8_sta_chg { 1120 u8 now; 1121 u8 last; 1122 u8 remain; 1123 u8 rsvd; 1124 }; 1125 1126 struct rtw89_btc_wl_scan_info { 1127 u8 band[RTW89_PHY_MAX]; 1128 u8 phy_map; 1129 u8 rsvd; 1130 }; 1131 1132 struct rtw89_btc_wl_dbcc_info { 1133 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1134 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1135 u8 real_band[RTW89_PHY_MAX]; 1136 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1137 }; 1138 1139 struct rtw89_btc_wl_active_role { 1140 u8 connected: 1; 1141 u8 pid: 3; 1142 u8 phy: 1; 1143 u8 noa: 1; 1144 u8 band: 2; 1145 1146 u8 client_ps: 1; 1147 u8 bw: 7; 1148 1149 u8 role; 1150 u8 ch; 1151 1152 u16 tx_lvl; 1153 u16 rx_lvl; 1154 u16 tx_rate; 1155 u16 rx_rate; 1156 }; 1157 1158 struct rtw89_btc_wl_active_role_v1 { 1159 u8 connected: 1; 1160 u8 pid: 3; 1161 u8 phy: 1; 1162 u8 noa: 1; 1163 u8 band: 2; 1164 1165 u8 client_ps: 1; 1166 u8 bw: 7; 1167 1168 u8 role; 1169 u8 ch; 1170 1171 u16 tx_lvl; 1172 u16 rx_lvl; 1173 u16 tx_rate; 1174 u16 rx_rate; 1175 1176 u32 noa_duration; /* ms */ 1177 }; 1178 1179 struct rtw89_btc_wl_role_info_bpos { 1180 u16 none: 1; 1181 u16 station: 1; 1182 u16 ap: 1; 1183 u16 vap: 1; 1184 u16 adhoc: 1; 1185 u16 adhoc_master: 1; 1186 u16 mesh: 1; 1187 u16 moniter: 1; 1188 u16 p2p_device: 1; 1189 u16 p2p_gc: 1; 1190 u16 p2p_go: 1; 1191 u16 nan: 1; 1192 }; 1193 1194 struct rtw89_btc_wl_scc_ctrl { 1195 u8 null_role1; 1196 u8 null_role2; 1197 u8 ebt_null; /* if tx null at EBT slot */ 1198 }; 1199 1200 union rtw89_btc_wl_role_info_map { 1201 u16 val; 1202 struct rtw89_btc_wl_role_info_bpos role; 1203 }; 1204 1205 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1206 u8 connect_cnt; 1207 u8 link_mode; 1208 union rtw89_btc_wl_role_info_map role_map; 1209 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1210 }; 1211 1212 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1213 u8 connect_cnt; 1214 u8 link_mode; 1215 union rtw89_btc_wl_role_info_map role_map; 1216 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1217 u32 mrole_type; /* btc_wl_mrole_type */ 1218 u32 mrole_noa_duration; /* ms */ 1219 1220 u32 dbcc_en: 1; 1221 u32 dbcc_chg: 1; 1222 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1223 u32 link_mode_chg: 1; 1224 u32 rsvd: 27; 1225 }; 1226 1227 struct rtw89_btc_wl_ver_info { 1228 u32 fw_coex; /* match with which coex_ver */ 1229 u32 fw; 1230 u32 mac; 1231 u32 bb; 1232 u32 rf; 1233 }; 1234 1235 struct rtw89_btc_wl_afh_info { 1236 u8 en; 1237 u8 ch; 1238 u8 bw; 1239 u8 rsvd; 1240 } __packed; 1241 1242 struct rtw89_btc_wl_rfk_info { 1243 u32 state: 2; 1244 u32 path_map: 4; 1245 u32 phy_map: 2; 1246 u32 band: 2; 1247 u32 type: 8; 1248 u32 rsvd: 14; 1249 }; 1250 1251 struct rtw89_btc_bt_smap { 1252 u32 connect: 1; 1253 u32 ble_connect: 1; 1254 u32 acl_busy: 1; 1255 u32 sco_busy: 1; 1256 u32 mesh_busy: 1; 1257 u32 inq_pag: 1; 1258 }; 1259 1260 union rtw89_btc_bt_state_map { 1261 u32 val; 1262 struct rtw89_btc_bt_smap map; 1263 }; 1264 1265 #define BTC_BT_RSSI_THMAX 4 1266 #define BTC_BT_AFH_GROUP 12 1267 #define BTC_BT_AFH_LE_GROUP 5 1268 1269 struct rtw89_btc_bt_link_info { 1270 struct rtw89_btc_u8_sta_chg profile_cnt; 1271 struct rtw89_btc_bool_sta_chg multi_link; 1272 struct rtw89_btc_bool_sta_chg relink; 1273 struct rtw89_btc_bt_hfp_desc hfp_desc; 1274 struct rtw89_btc_bt_hid_desc hid_desc; 1275 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1276 struct rtw89_btc_bt_pan_desc pan_desc; 1277 union rtw89_btc_bt_state_map status; 1278 1279 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1280 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1281 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1282 u8 afh_map[BTC_BT_AFH_GROUP]; 1283 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1284 1285 u32 role_sw: 1; 1286 u32 slave_role: 1; 1287 u32 afh_update: 1; 1288 u32 cqddr: 1; 1289 u32 rssi: 8; 1290 u32 tx_3m: 1; 1291 u32 rsvd: 19; 1292 }; 1293 1294 struct rtw89_btc_3rdcx_info { 1295 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1296 u8 hw_coex; 1297 u16 rsvd; 1298 }; 1299 1300 struct rtw89_btc_dm_emap { 1301 u32 init: 1; 1302 u32 pta_owner: 1; 1303 u32 wl_rfk_timeout: 1; 1304 u32 bt_rfk_timeout: 1; 1305 1306 u32 wl_fw_hang: 1; 1307 u32 offload_mismatch: 1; 1308 u32 cycle_hang: 1; 1309 u32 w1_hang: 1; 1310 1311 u32 b1_hang: 1; 1312 u32 tdma_no_sync: 1; 1313 u32 wl_slot_drift: 1; 1314 }; 1315 1316 union rtw89_btc_dm_error_map { 1317 u32 val; 1318 struct rtw89_btc_dm_emap map; 1319 }; 1320 1321 struct rtw89_btc_rf_para { 1322 u32 tx_pwr_freerun; 1323 u32 rx_gain_freerun; 1324 u32 tx_pwr_perpkt; 1325 u32 rx_gain_perpkt; 1326 }; 1327 1328 struct rtw89_btc_wl_info { 1329 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1330 struct rtw89_btc_wl_rfk_info rfk_info; 1331 struct rtw89_btc_wl_ver_info ver_info; 1332 struct rtw89_btc_wl_afh_info afh_info; 1333 struct rtw89_btc_wl_role_info role_info; 1334 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1335 struct rtw89_btc_wl_scan_info scan_info; 1336 struct rtw89_btc_wl_dbcc_info dbcc_info; 1337 struct rtw89_btc_rf_para rf_para; 1338 union rtw89_btc_wl_state_map status; 1339 1340 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1341 u8 rssi_level; 1342 1343 bool scbd_change; 1344 u32 scbd; 1345 }; 1346 1347 struct rtw89_btc_module { 1348 struct rtw89_btc_ant_info ant; 1349 u8 rfe_type; 1350 u8 cv; 1351 1352 u8 bt_solo: 1; 1353 u8 bt_pos: 1; 1354 u8 switch_type: 1; 1355 1356 u8 rsvd; 1357 }; 1358 1359 #define RTW89_BTC_DM_MAXSTEP 30 1360 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1361 1362 struct rtw89_btc_dm_step { 1363 u16 step[RTW89_BTC_DM_MAXSTEP]; 1364 u8 step_pos; 1365 bool step_ov; 1366 }; 1367 1368 struct rtw89_btc_init_info { 1369 struct rtw89_btc_module module; 1370 u8 wl_guard_ch; 1371 1372 u8 wl_only: 1; 1373 u8 wl_init_ok: 1; 1374 u8 dbcc_en: 1; 1375 u8 cx_other: 1; 1376 u8 bt_only: 1; 1377 1378 u16 rsvd; 1379 }; 1380 1381 struct rtw89_btc_wl_tx_limit_para { 1382 u16 enable; 1383 u32 tx_time; /* unit: us */ 1384 u16 tx_retry; 1385 }; 1386 1387 struct rtw89_btc_bt_scan_info { 1388 u16 win; 1389 u16 intvl; 1390 u32 enable: 1; 1391 u32 interlace: 1; 1392 u32 rsvd: 30; 1393 }; 1394 1395 enum rtw89_btc_bt_scan_type { 1396 BTC_SCAN_INQ = 0, 1397 BTC_SCAN_PAGE, 1398 BTC_SCAN_BLE, 1399 BTC_SCAN_INIT, 1400 BTC_SCAN_TV, 1401 BTC_SCAN_ADV, 1402 BTC_SCAN_MAX1, 1403 }; 1404 1405 struct rtw89_btc_bt_info { 1406 struct rtw89_btc_bt_link_info link_info; 1407 struct rtw89_btc_bt_scan_info scan_info[BTC_SCAN_MAX1]; 1408 struct rtw89_btc_bt_ver_info ver_info; 1409 struct rtw89_btc_bool_sta_chg enable; 1410 struct rtw89_btc_bool_sta_chg inq_pag; 1411 struct rtw89_btc_rf_para rf_para; 1412 union rtw89_btc_bt_rfk_info_map rfk_info; 1413 1414 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1415 1416 u32 scbd; 1417 u32 feature; 1418 1419 u32 mbx_avl: 1; 1420 u32 whql_test: 1; 1421 u32 igno_wl: 1; 1422 u32 reinit: 1; 1423 u32 ble_scan_en: 1; 1424 u32 btg_type: 1; 1425 u32 inq: 1; 1426 u32 pag: 1; 1427 u32 run_patch_code: 1; 1428 u32 hi_lna_rx: 1; 1429 u32 scan_rx_low_pri: 1; 1430 u32 rsvd: 21; 1431 }; 1432 1433 struct rtw89_btc_cx { 1434 struct rtw89_btc_wl_info wl; 1435 struct rtw89_btc_bt_info bt; 1436 struct rtw89_btc_3rdcx_info other; 1437 u32 state_map; 1438 u32 cnt_bt[BTC_BCNT_NUM]; 1439 u32 cnt_wl[BTC_WCNT_NUM]; 1440 }; 1441 1442 struct rtw89_btc_fbtc_tdma { 1443 u8 type; /* btc_ver::fcxtdma */ 1444 u8 rxflctrl; 1445 u8 txpause; 1446 u8 wtgle_n; 1447 u8 leak_n; 1448 u8 ext_ctrl; 1449 u8 rxflctrl_role; 1450 u8 option_ctrl; 1451 } __packed; 1452 1453 struct rtw89_btc_fbtc_tdma_v3 { 1454 u8 fver; /* btc_ver::fcxtdma */ 1455 u8 rsvd; 1456 __le16 rsvd1; 1457 struct rtw89_btc_fbtc_tdma tdma; 1458 } __packed; 1459 1460 union rtw89_btc_fbtc_tdma_le32 { 1461 struct rtw89_btc_fbtc_tdma v1; 1462 struct rtw89_btc_fbtc_tdma_v3 v3; 1463 }; 1464 1465 #define CXMREG_MAX 30 1466 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1467 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1468 1469 enum rtw89_btc_bt_sta_counter { 1470 BTC_BCNT_RFK_REQ = 0, 1471 BTC_BCNT_RFK_GO = 1, 1472 BTC_BCNT_RFK_REJECT = 2, 1473 BTC_BCNT_RFK_FAIL = 3, 1474 BTC_BCNT_RFK_TIMEOUT = 4, 1475 BTC_BCNT_HI_TX = 5, 1476 BTC_BCNT_HI_RX = 6, 1477 BTC_BCNT_LO_TX = 7, 1478 BTC_BCNT_LO_RX = 8, 1479 BTC_BCNT_POLLUTED = 9, 1480 BTC_BCNT_STA_MAX 1481 }; 1482 1483 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 1484 u16 fver; /* btc_ver::fcxbtcrpt */ 1485 u16 rpt_cnt; /* tmr counters */ 1486 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1487 u32 wl_fw_cx_offload; 1488 u32 wl_fw_ver; 1489 u32 rpt_enable; 1490 u32 rpt_para; /* ms */ 1491 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1492 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1493 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1494 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1495 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1496 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1497 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 1498 u32 c2h_cnt; /* fw send c2h counter */ 1499 u32 h2c_cnt; /* fw recv h2c counter */ 1500 } __packed; 1501 1502 struct rtw89_btc_fbtc_rpt_ctrl_info { 1503 __le32 cnt; /* fw report counter */ 1504 __le32 en; /* report map */ 1505 __le32 para; /* not used */ 1506 1507 __le32 cnt_c2h; /* fw send c2h counter */ 1508 __le32 cnt_h2c; /* fw recv h2c counter */ 1509 __le32 len_c2h; /* The total length of the last C2H */ 1510 1511 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1512 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1513 } __packed; 1514 1515 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 1516 __le32 cx_ver; /* match which driver's coex version */ 1517 __le32 fw_ver; 1518 __le32 en; /* report map */ 1519 1520 __le16 cnt; /* fw report counter */ 1521 __le16 cnt_c2h; /* fw send c2h counter */ 1522 __le16 cnt_h2c; /* fw recv h2c counter */ 1523 __le16 len_c2h; /* The total length of the last C2H */ 1524 1525 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1526 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1527 } __packed; 1528 1529 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 1530 __le32 cx_ver; /* match which driver's coex version */ 1531 __le32 cx_offload; 1532 __le32 fw_ver; 1533 } __packed; 1534 1535 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 1536 __le32 cnt_empty; /* a2dp empty count */ 1537 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 1538 __le32 cnt_tx; 1539 __le32 cnt_ack; 1540 __le32 cnt_nack; 1541 } __packed; 1542 1543 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 1544 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 1545 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 1546 __le32 cnt_recv; /* fw recv mailbox counter */ 1547 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 1548 } __packed; 1549 1550 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 1551 u8 fver; 1552 u8 rsvd; 1553 __le16 rsvd1; 1554 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 1555 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 1556 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1557 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 1558 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 1559 } __packed; 1560 1561 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 1562 u8 fver; 1563 u8 rsvd; 1564 __le16 rsvd1; 1565 1566 u8 gnt_val[RTW89_PHY_MAX][4]; 1567 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 1568 1569 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1570 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1571 } __packed; 1572 1573 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 1574 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 1575 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 1576 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 1577 }; 1578 1579 enum rtw89_fbtc_ext_ctrl_type { 1580 CXECTL_OFF = 0x0, /* tdma off */ 1581 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 1582 CXECTL_EXT = 0x2, 1583 CXECTL_MAX 1584 }; 1585 1586 union rtw89_btc_fbtc_rxflct { 1587 u8 val; 1588 u8 type: 3; 1589 u8 tgln_n: 5; 1590 }; 1591 1592 enum rtw89_btc_cxst_state { 1593 CXST_OFF = 0x0, 1594 CXST_B2W = 0x1, 1595 CXST_W1 = 0x2, 1596 CXST_W2 = 0x3, 1597 CXST_W2B = 0x4, 1598 CXST_B1 = 0x5, 1599 CXST_B2 = 0x6, 1600 CXST_B3 = 0x7, 1601 CXST_B4 = 0x8, 1602 CXST_LK = 0x9, 1603 CXST_BLK = 0xa, 1604 CXST_E2G = 0xb, 1605 CXST_E5G = 0xc, 1606 CXST_EBT = 0xd, 1607 CXST_ENULL = 0xe, 1608 CXST_WLK = 0xf, 1609 CXST_W1FDD = 0x10, 1610 CXST_B1FDD = 0x11, 1611 CXST_MAX = 0x12, 1612 }; 1613 1614 enum rtw89_btc_cxevnt { 1615 CXEVNT_TDMA_ENTRY = 0x0, 1616 CXEVNT_WL_TMR, 1617 CXEVNT_B1_TMR, 1618 CXEVNT_B2_TMR, 1619 CXEVNT_B3_TMR, 1620 CXEVNT_B4_TMR, 1621 CXEVNT_W2B_TMR, 1622 CXEVNT_B2W_TMR, 1623 CXEVNT_BCN_EARLY, 1624 CXEVNT_A2DP_EMPTY, 1625 CXEVNT_LK_END, 1626 CXEVNT_RX_ISR, 1627 CXEVNT_RX_FC0, 1628 CXEVNT_RX_FC1, 1629 CXEVNT_BT_RELINK, 1630 CXEVNT_BT_RETRY, 1631 CXEVNT_E2G, 1632 CXEVNT_E5G, 1633 CXEVNT_EBT, 1634 CXEVNT_ENULL, 1635 CXEVNT_DRV_WLK, 1636 CXEVNT_BCN_OK, 1637 CXEVNT_BT_CHANGE, 1638 CXEVNT_EBT_EXTEND, 1639 CXEVNT_E2G_NULL1, 1640 CXEVNT_B1FDD_TMR, 1641 CXEVNT_MAX 1642 }; 1643 1644 enum { 1645 CXBCN_ALL = 0x0, 1646 CXBCN_ALL_OK, 1647 CXBCN_BT_SLOT, 1648 CXBCN_BT_OK, 1649 CXBCN_MAX 1650 }; 1651 1652 enum btc_slot_type { 1653 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 1654 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 1655 CXSTYPE_NUM, 1656 }; 1657 1658 enum { /* TIME */ 1659 CXT_BT = 0x0, 1660 CXT_WL = 0x1, 1661 CXT_MAX 1662 }; 1663 1664 enum { /* TIME-A2DP */ 1665 CXT_FLCTRL_OFF = 0x0, 1666 CXT_FLCTRL_ON = 0x1, 1667 CXT_FLCTRL_MAX 1668 }; 1669 1670 enum { /* STEP TYPE */ 1671 CXSTEP_NONE = 0x0, 1672 CXSTEP_EVNT = 0x1, 1673 CXSTEP_SLOT = 0x2, 1674 CXSTEP_MAX, 1675 }; 1676 1677 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 1678 RPT_BT_AFH_SEQ_LEGACY = 0x10, 1679 RPT_BT_AFH_SEQ_LE = 0x20 1680 }; 1681 1682 #define BTC_DBG_MAX1 32 1683 struct rtw89_btc_fbtc_gpio_dbg { 1684 u8 fver; /* btc_ver::fcxgpiodbg */ 1685 u8 rsvd; 1686 u16 rsvd2; 1687 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 1688 u32 pre_state; /* the debug signal is 1 or 0 */ 1689 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 1690 } __packed; 1691 1692 struct rtw89_btc_fbtc_mreg_val { 1693 u8 fver; /* btc_ver::fcxmreg */ 1694 u8 reg_num; 1695 __le16 rsvd; 1696 __le32 mreg_val[CXMREG_MAX]; 1697 } __packed; 1698 1699 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 1700 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 1701 .offset = cpu_to_le32(__offset), } 1702 1703 struct rtw89_btc_fbtc_mreg { 1704 __le16 type; 1705 __le16 bytes; 1706 __le32 offset; 1707 } __packed; 1708 1709 struct rtw89_btc_fbtc_slot { 1710 __le16 dur; 1711 __le32 cxtbl; 1712 __le16 cxtype; 1713 } __packed; 1714 1715 struct rtw89_btc_fbtc_slots { 1716 u8 fver; /* btc_ver::fcxslots */ 1717 u8 tbl_num; 1718 __le16 rsvd; 1719 __le32 update_map; 1720 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1721 } __packed; 1722 1723 struct rtw89_btc_fbtc_step { 1724 u8 type; 1725 u8 val; 1726 __le16 difft; 1727 } __packed; 1728 1729 struct rtw89_btc_fbtc_steps_v2 { 1730 u8 fver; /* btc_ver::fcxstep */ 1731 u8 rsvd; 1732 __le16 cnt; 1733 __le16 pos_old; 1734 __le16 pos_new; 1735 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1736 } __packed; 1737 1738 struct rtw89_btc_fbtc_steps_v3 { 1739 u8 fver; 1740 u8 en; 1741 __le16 rsvd; 1742 __le32 cnt; 1743 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1744 } __packed; 1745 1746 union rtw89_btc_fbtc_steps_info { 1747 struct rtw89_btc_fbtc_steps_v2 v2; 1748 struct rtw89_btc_fbtc_steps_v3 v3; 1749 }; 1750 1751 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 1752 u8 fver; /* btc_ver::fcxcysta */ 1753 u8 rsvd; 1754 __le16 cycles; /* total cycle number */ 1755 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 1756 __le16 a2dpept; /* a2dp empty cnt */ 1757 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 1758 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 1759 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 1760 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1761 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 1762 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 1763 __le16 tavg_a2dpept; /* avg a2dp empty time */ 1764 __le16 tmax_a2dpept; /* max a2dp empty time */ 1765 __le16 tavg_lk; /* avg leak-slot time */ 1766 __le16 tmax_lk; /* max leak-slot time */ 1767 __le32 slot_cnt[CXST_MAX]; /* slot count */ 1768 __le32 bcn_cnt[CXBCN_MAX]; 1769 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 1770 __le32 collision_cnt; /* counter for event/timer occur at same time */ 1771 __le32 skip_cnt; 1772 __le32 exception; 1773 __le32 except_cnt; 1774 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 1775 } __packed; 1776 1777 struct rtw89_btc_fbtc_fdd_try_info { 1778 __le16 cycles[CXT_FLCTRL_MAX]; 1779 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 1780 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 1781 } __packed; 1782 1783 struct rtw89_btc_fbtc_cycle_time_info { 1784 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 1785 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 1786 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1787 } __packed; 1788 1789 struct rtw89_btc_fbtc_a2dp_trx_stat { 1790 u8 empty_cnt; 1791 u8 retry_cnt; 1792 u8 tx_rate; 1793 u8 tx_cnt; 1794 u8 ack_cnt; 1795 u8 nack_cnt; 1796 u8 rsvd1; 1797 u8 rsvd2; 1798 } __packed; 1799 1800 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 1801 u8 empty_cnt; 1802 u8 retry_cnt; 1803 u8 tx_rate; 1804 u8 tx_cnt; 1805 u8 ack_cnt; 1806 u8 nack_cnt; 1807 u8 no_empty_cnt; 1808 u8 rsvd; 1809 } __packed; 1810 1811 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 1812 __le16 cnt; /* a2dp empty cnt */ 1813 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 1814 __le16 tavg; /* avg a2dp empty time */ 1815 __le16 tmax; /* max a2dp empty time */ 1816 } __packed; 1817 1818 struct rtw89_btc_fbtc_cycle_leak_info { 1819 __le32 cnt_rximr; /* the rximr occur at leak slot */ 1820 __le16 tavg; /* avg leak-slot time */ 1821 __le16 tmax; /* max leak-slot time */ 1822 } __packed; 1823 1824 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 1825 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 1826 1827 struct rtw89_btc_fbtc_cycle_fddt_info { 1828 __le16 train_cycle; 1829 __le16 tp; 1830 1831 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 1832 s8 bt_tx_power; /* decrease Tx power (dB) */ 1833 s8 bt_rx_gain; /* LNA constrain level */ 1834 u8 no_empty_cnt; 1835 1836 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 1837 u8 cn; /* condition_num */ 1838 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 1839 u8 train_result; /* refer to enum btc_fddt_check_map */ 1840 } __packed; 1841 1842 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 1843 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 1844 1845 struct rtw89_btc_fbtc_fddt_cell_status { 1846 s8 wl_tx_pwr; 1847 s8 bt_tx_pwr; 1848 s8 bt_rx_gain; 1849 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 1850 } __packed; 1851 1852 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 1853 u8 fver; 1854 u8 rsvd; 1855 __le16 cycles; /* total cycle number */ 1856 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 1857 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 1858 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 1859 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 1860 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 1861 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 1862 __le32 slot_cnt[CXST_MAX]; /* slot count */ 1863 __le32 bcn_cnt[CXBCN_MAX]; 1864 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 1865 __le32 skip_cnt; 1866 __le32 except_cnt; 1867 __le32 except_map; 1868 } __packed; 1869 1870 #define FDD_TRAIN_WL_DIRECTION 2 1871 #define FDD_TRAIN_WL_RSSI_LEVEL 5 1872 #define FDD_TRAIN_BT_RSSI_LEVEL 5 1873 1874 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 1875 u8 fver; 1876 u8 rsvd; 1877 u8 collision_cnt; /* counter for event/timer occur at the same time */ 1878 u8 except_cnt; 1879 1880 __le16 skip_cnt; 1881 __le16 cycles; /* total cycle number */ 1882 1883 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 1884 __le16 slot_cnt[CXST_MAX]; /* slot count */ 1885 __le16 bcn_cnt[CXBCN_MAX]; 1886 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 1887 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 1888 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 1889 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 1890 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 1891 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 1892 [FDD_TRAIN_WL_RSSI_LEVEL] 1893 [FDD_TRAIN_BT_RSSI_LEVEL]; 1894 __le32 except_map; 1895 } __packed; 1896 1897 union rtw89_btc_fbtc_cysta_info { 1898 struct rtw89_btc_fbtc_cysta_v2 v2; 1899 struct rtw89_btc_fbtc_cysta_v3 v3; 1900 struct rtw89_btc_fbtc_cysta_v4 v4; 1901 }; 1902 1903 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 1904 u8 fver; /* btc_ver::fcxnullsta */ 1905 u8 rsvd; 1906 __le16 rsvd2; 1907 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 1908 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 1909 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 1910 } __packed; 1911 1912 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 1913 u8 fver; /* btc_ver::fcxnullsta */ 1914 u8 rsvd; 1915 __le16 rsvd2; 1916 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 1917 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 1918 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 1919 } __packed; 1920 1921 union rtw89_btc_fbtc_cynullsta_info { 1922 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 1923 struct rtw89_btc_fbtc_cynullsta_v2 v2; 1924 }; 1925 1926 struct rtw89_btc_fbtc_btver { 1927 u8 fver; /* btc_ver::fcxbtver */ 1928 u8 rsvd; 1929 __le16 rsvd2; 1930 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 1931 __le32 fw_ver; 1932 __le32 feature; 1933 } __packed; 1934 1935 struct rtw89_btc_fbtc_btscan { 1936 u8 fver; /* btc_ver::fcxbtscan */ 1937 u8 rsvd; 1938 __le16 rsvd2; 1939 u8 scan[6]; 1940 } __packed; 1941 1942 struct rtw89_btc_fbtc_btafh { 1943 u8 fver; /* btc_ver::fcxbtafh */ 1944 u8 rsvd; 1945 __le16 rsvd2; 1946 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 1947 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 1948 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 1949 } __packed; 1950 1951 struct rtw89_btc_fbtc_btafh_v2 { 1952 u8 fver; /* btc_ver::fcxbtafh */ 1953 u8 rsvd; 1954 u8 rsvd2; 1955 u8 map_type; 1956 u8 afh_l[4]; 1957 u8 afh_m[4]; 1958 u8 afh_h[4]; 1959 u8 afh_le_a[4]; 1960 u8 afh_le_b[4]; 1961 } __packed; 1962 1963 struct rtw89_btc_fbtc_btdevinfo { 1964 u8 fver; /* btc_ver::fcxbtdevinfo */ 1965 u8 rsvd; 1966 __le16 vendor_id; 1967 __le32 dev_name; /* only 24 bits valid */ 1968 __le32 flush_time; 1969 } __packed; 1970 1971 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 1972 struct rtw89_btc_rf_trx_para { 1973 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 1974 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 1975 u8 bt_tx_power; /* decrease Tx power (dB) */ 1976 u8 bt_rx_gain; /* LNA constrain level */ 1977 }; 1978 1979 struct rtw89_btc_dm { 1980 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1981 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 1982 struct rtw89_btc_fbtc_tdma tdma; 1983 struct rtw89_btc_fbtc_tdma tdma_now; 1984 struct rtw89_mac_ax_coex_gnt gnt; 1985 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 1986 struct rtw89_btc_rf_trx_para rf_trx_para; 1987 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 1988 struct rtw89_btc_dm_step dm_step; 1989 struct rtw89_btc_wl_scc_ctrl wl_scc; 1990 union rtw89_btc_dm_error_map error; 1991 u32 cnt_dm[BTC_DCNT_NUM]; 1992 u32 cnt_notify[BTC_NCNT_NUM]; 1993 1994 u32 update_slot_map; 1995 u32 set_ant_path; 1996 1997 u32 wl_only: 1; 1998 u32 wl_fw_cx_offload: 1; 1999 u32 freerun: 1; 2000 u32 wl_ps_ctrl: 2; 2001 u32 wl_mimo_ps: 1; 2002 u32 leak_ap: 1; 2003 u32 noisy_level: 3; 2004 u32 coex_info_map: 8; 2005 u32 bt_only: 1; 2006 u32 wl_btg_rx: 1; 2007 u32 trx_para_level: 8; 2008 u32 wl_stb_chg: 1; 2009 u32 pta_owner: 1; 2010 u32 tdma_instant_excute: 1; 2011 u32 rsvd: 1; 2012 2013 u16 slot_dur[CXST_MAX]; 2014 2015 u8 run_reason; 2016 u8 run_action; 2017 }; 2018 2019 struct rtw89_btc_ctrl { 2020 u32 manual: 1; 2021 u32 igno_bt: 1; 2022 u32 always_freerun: 1; 2023 u32 trace_step: 16; 2024 u32 rsvd: 12; 2025 }; 2026 2027 struct rtw89_btc_dbg { 2028 /* cmd "rb" */ 2029 bool rb_done; 2030 u32 rb_val; 2031 }; 2032 2033 enum rtw89_btc_btf_fw_event { 2034 BTF_EVNT_RPT = 0, 2035 BTF_EVNT_BT_INFO = 1, 2036 BTF_EVNT_BT_SCBD = 2, 2037 BTF_EVNT_BT_REG = 3, 2038 BTF_EVNT_CX_RUNINFO = 4, 2039 BTF_EVNT_BT_PSD = 5, 2040 BTF_EVNT_BUF_OVERFLOW, 2041 BTF_EVNT_C2H_LOOPBACK, 2042 BTF_EVNT_MAX, 2043 }; 2044 2045 enum btf_fw_event_report { 2046 BTC_RPT_TYPE_CTRL = 0x0, 2047 BTC_RPT_TYPE_TDMA, 2048 BTC_RPT_TYPE_SLOT, 2049 BTC_RPT_TYPE_CYSTA, 2050 BTC_RPT_TYPE_STEP, 2051 BTC_RPT_TYPE_NULLSTA, 2052 BTC_RPT_TYPE_MREG, 2053 BTC_RPT_TYPE_GPIO_DBG, 2054 BTC_RPT_TYPE_BT_VER, 2055 BTC_RPT_TYPE_BT_SCAN, 2056 BTC_RPT_TYPE_BT_AFH, 2057 BTC_RPT_TYPE_BT_DEVICE, 2058 BTC_RPT_TYPE_TEST, 2059 BTC_RPT_TYPE_MAX = 31 2060 }; 2061 2062 enum rtw_btc_btf_reg_type { 2063 REG_MAC = 0x0, 2064 REG_BB = 0x1, 2065 REG_RF = 0x2, 2066 REG_BT_RF = 0x3, 2067 REG_BT_MODEM = 0x4, 2068 REG_BT_BLUEWIZE = 0x5, 2069 REG_BT_VENDOR = 0x6, 2070 REG_BT_LE = 0x7, 2071 REG_MAX_TYPE, 2072 }; 2073 2074 struct rtw89_btc_rpt_cmn_info { 2075 u32 rx_cnt; 2076 u32 rx_len; 2077 u32 req_len; /* expected rsp len */ 2078 u8 req_fver; /* expected rsp fver */ 2079 u8 rsp_fver; /* fver from fw */ 2080 u8 valid; 2081 } __packed; 2082 2083 union rtw89_btc_fbtc_btafh_info { 2084 struct rtw89_btc_fbtc_btafh v1; 2085 struct rtw89_btc_fbtc_btafh_v2 v2; 2086 }; 2087 2088 struct rtw89_btc_report_ctrl_state { 2089 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2090 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 2091 }; 2092 2093 struct rtw89_btc_rpt_fbtc_tdma { 2094 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2095 union rtw89_btc_fbtc_tdma_le32 finfo; 2096 }; 2097 2098 struct rtw89_btc_rpt_fbtc_slots { 2099 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2100 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 2101 }; 2102 2103 struct rtw89_btc_rpt_fbtc_cysta { 2104 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2105 union rtw89_btc_fbtc_cysta_info finfo; 2106 }; 2107 2108 struct rtw89_btc_rpt_fbtc_step { 2109 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2110 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 2111 }; 2112 2113 struct rtw89_btc_rpt_fbtc_nullsta { 2114 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2115 union rtw89_btc_fbtc_cynullsta_info finfo; 2116 }; 2117 2118 struct rtw89_btc_rpt_fbtc_mreg { 2119 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2120 struct rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 2121 }; 2122 2123 struct rtw89_btc_rpt_fbtc_gpio_dbg { 2124 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2125 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 2126 }; 2127 2128 struct rtw89_btc_rpt_fbtc_btver { 2129 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2130 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 2131 }; 2132 2133 struct rtw89_btc_rpt_fbtc_btscan { 2134 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2135 struct rtw89_btc_fbtc_btscan finfo; /* info from fw */ 2136 }; 2137 2138 struct rtw89_btc_rpt_fbtc_btafh { 2139 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2140 union rtw89_btc_fbtc_btafh_info finfo; 2141 }; 2142 2143 struct rtw89_btc_rpt_fbtc_btdev { 2144 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2145 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 2146 }; 2147 2148 enum rtw89_btc_btfre_type { 2149 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 2150 BTFRE_UNDEF_TYPE, 2151 BTFRE_EXCEPTION, 2152 BTFRE_MAX, 2153 }; 2154 2155 struct rtw89_btc_btf_fwinfo { 2156 u32 cnt_c2h; 2157 u32 cnt_h2c; 2158 u32 cnt_h2c_fail; 2159 u32 event[BTF_EVNT_MAX]; 2160 2161 u32 err[BTFRE_MAX]; 2162 u32 len_mismch; 2163 u32 fver_mismch; 2164 u32 rpt_en_map; 2165 2166 struct rtw89_btc_report_ctrl_state rpt_ctrl; 2167 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 2168 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 2169 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 2170 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 2171 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 2172 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 2173 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 2174 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 2175 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 2176 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 2177 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 2178 }; 2179 2180 struct rtw89_btc_ver { 2181 enum rtw89_core_chip_id chip_id; 2182 u32 fw_ver_code; 2183 2184 u8 fcxbtcrpt; 2185 u8 fcxtdma; 2186 u8 fcxslots; 2187 u8 fcxcysta; 2188 u8 fcxstep; 2189 u8 fcxnullsta; 2190 u8 fcxmreg; 2191 u8 fcxgpiodbg; 2192 u8 fcxbtver; 2193 u8 fcxbtscan; 2194 u8 fcxbtafh; 2195 u8 fcxbtdevinfo; 2196 u8 fwlrole; 2197 u8 frptmap; 2198 u8 fcxctrl; 2199 2200 u16 info_buf; 2201 u8 max_role_num; 2202 }; 2203 2204 #define RTW89_BTC_POLICY_MAXLEN 512 2205 2206 struct rtw89_btc { 2207 const struct rtw89_btc_ver *ver; 2208 2209 struct rtw89_btc_cx cx; 2210 struct rtw89_btc_dm dm; 2211 struct rtw89_btc_ctrl ctrl; 2212 struct rtw89_btc_module mdinfo; 2213 struct rtw89_btc_btf_fwinfo fwinfo; 2214 struct rtw89_btc_dbg dbg; 2215 2216 struct work_struct eapol_notify_work; 2217 struct work_struct arp_notify_work; 2218 struct work_struct dhcp_notify_work; 2219 struct work_struct icmp_notify_work; 2220 2221 u32 bt_req_len; 2222 2223 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 2224 u16 policy_len; 2225 u16 policy_type; 2226 bool bt_req_en; 2227 bool update_policy_force; 2228 bool lps; 2229 }; 2230 2231 enum rtw89_ra_mode { 2232 RTW89_RA_MODE_CCK = BIT(0), 2233 RTW89_RA_MODE_OFDM = BIT(1), 2234 RTW89_RA_MODE_HT = BIT(2), 2235 RTW89_RA_MODE_VHT = BIT(3), 2236 RTW89_RA_MODE_HE = BIT(4), 2237 }; 2238 2239 enum rtw89_ra_report_mode { 2240 RTW89_RA_RPT_MODE_LEGACY, 2241 RTW89_RA_RPT_MODE_HT, 2242 RTW89_RA_RPT_MODE_VHT, 2243 RTW89_RA_RPT_MODE_HE, 2244 }; 2245 2246 enum rtw89_dig_noisy_level { 2247 RTW89_DIG_NOISY_LEVEL0 = -1, 2248 RTW89_DIG_NOISY_LEVEL1 = 0, 2249 RTW89_DIG_NOISY_LEVEL2 = 1, 2250 RTW89_DIG_NOISY_LEVEL3 = 2, 2251 RTW89_DIG_NOISY_LEVEL_MAX = 3, 2252 }; 2253 2254 enum rtw89_gi_ltf { 2255 RTW89_GILTF_LGI_4XHE32 = 0, 2256 RTW89_GILTF_SGI_4XHE08 = 1, 2257 RTW89_GILTF_2XHE16 = 2, 2258 RTW89_GILTF_2XHE08 = 3, 2259 RTW89_GILTF_1XHE16 = 4, 2260 RTW89_GILTF_1XHE08 = 5, 2261 RTW89_GILTF_MAX 2262 }; 2263 2264 enum rtw89_rx_frame_type { 2265 RTW89_RX_TYPE_MGNT = 0, 2266 RTW89_RX_TYPE_CTRL = 1, 2267 RTW89_RX_TYPE_DATA = 2, 2268 RTW89_RX_TYPE_RSVD = 3, 2269 }; 2270 2271 struct rtw89_ra_info { 2272 u8 is_dis_ra:1; 2273 /* Bit0 : CCK 2274 * Bit1 : OFDM 2275 * Bit2 : HT 2276 * Bit3 : VHT 2277 * Bit4 : HE 2278 */ 2279 u8 mode_ctrl:5; 2280 u8 bw_cap:2; 2281 u8 macid; 2282 u8 dcm_cap:1; 2283 u8 er_cap:1; 2284 u8 init_rate_lv:2; 2285 u8 upd_all:1; 2286 u8 en_sgi:1; 2287 u8 ldpc_cap:1; 2288 u8 stbc_cap:1; 2289 u8 ss_num:3; 2290 u8 giltf:3; 2291 u8 upd_bw_nss_mask:1; 2292 u8 upd_mask:1; 2293 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 2294 /* BFee CSI */ 2295 u8 band_num; 2296 u8 ra_csi_rate_en:1; 2297 u8 fixed_csi_rate_en:1; 2298 u8 cr_tbl_sel:1; 2299 u8 fix_giltf_en:1; 2300 u8 fix_giltf:3; 2301 u8 rsvd2:1; 2302 u8 csi_mcs_ss_idx; 2303 u8 csi_mode:2; 2304 u8 csi_gi_ltf:3; 2305 u8 csi_bw:3; 2306 }; 2307 2308 #define RTW89_PPDU_MAX_USR 4 2309 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 2310 #define RTW89_PPDU_MAC_INFO_SIZE 8 2311 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 2312 2313 #define RTW89_MAX_RX_AGG_NUM 64 2314 #define RTW89_MAX_TX_AGG_NUM 128 2315 2316 struct rtw89_ampdu_params { 2317 u16 agg_num; 2318 bool amsdu; 2319 }; 2320 2321 struct rtw89_ra_report { 2322 struct rate_info txrate; 2323 u32 bit_rate; 2324 u16 hw_rate; 2325 bool might_fallback_legacy; 2326 }; 2327 2328 DECLARE_EWMA(rssi, 10, 16); 2329 2330 struct rtw89_ba_cam_entry { 2331 struct list_head list; 2332 u8 tid; 2333 }; 2334 2335 #define RTW89_MAX_ADDR_CAM_NUM 128 2336 #define RTW89_MAX_BSSID_CAM_NUM 20 2337 #define RTW89_MAX_SEC_CAM_NUM 128 2338 #define RTW89_MAX_BA_CAM_NUM 8 2339 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 2340 2341 struct rtw89_addr_cam_entry { 2342 u8 addr_cam_idx; 2343 u8 offset; 2344 u8 len; 2345 u8 valid : 1; 2346 u8 addr_mask : 6; 2347 u8 wapi : 1; 2348 u8 mask_sel : 2; 2349 u8 bssid_cam_idx: 6; 2350 2351 u8 sec_ent_mode; 2352 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 2353 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 2354 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 2355 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 2356 }; 2357 2358 struct rtw89_bssid_cam_entry { 2359 u8 bssid[ETH_ALEN]; 2360 u8 phy_idx; 2361 u8 bssid_cam_idx; 2362 u8 offset; 2363 u8 len; 2364 u8 valid : 1; 2365 u8 num; 2366 }; 2367 2368 struct rtw89_sec_cam_entry { 2369 u8 sec_cam_idx; 2370 u8 offset; 2371 u8 len; 2372 u8 type : 4; 2373 u8 ext_key : 1; 2374 u8 spp_mode : 1; 2375 /* 256 bits */ 2376 u8 key[32]; 2377 }; 2378 2379 struct rtw89_sta { 2380 u8 mac_id; 2381 bool disassoc; 2382 bool er_cap; 2383 struct rtw89_dev *rtwdev; 2384 struct rtw89_vif *rtwvif; 2385 struct rtw89_ra_info ra; 2386 struct rtw89_ra_report ra_report; 2387 int max_agg_wait; 2388 u8 prev_rssi; 2389 struct ewma_rssi avg_rssi; 2390 struct ewma_rssi rssi[RF_PATH_MAX]; 2391 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 2392 struct ieee80211_rx_status rx_status; 2393 u16 rx_hw_rate; 2394 __le32 htc_template; 2395 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 2396 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 2397 struct list_head ba_cam_list; 2398 2399 bool use_cfg_mask; 2400 struct cfg80211_bitrate_mask mask; 2401 2402 bool cctl_tx_time; 2403 u32 ampdu_max_time:4; 2404 bool cctl_tx_retry_limit; 2405 u32 data_tx_cnt_lmt:6; 2406 }; 2407 2408 struct rtw89_efuse { 2409 bool valid; 2410 bool power_k_valid; 2411 u8 xtal_cap; 2412 u8 addr[ETH_ALEN]; 2413 u8 rfe_type; 2414 char country_code[2]; 2415 }; 2416 2417 struct rtw89_phy_rate_pattern { 2418 u64 ra_mask; 2419 u16 rate; 2420 u8 ra_mode; 2421 bool enable; 2422 }; 2423 2424 #define RTW89_P2P_MAX_NOA_NUM 2 2425 2426 struct rtw89_vif { 2427 struct list_head list; 2428 struct rtw89_dev *rtwdev; 2429 enum rtw89_sub_entity_idx sub_entity_idx; 2430 2431 u8 mac_id; 2432 u8 port; 2433 u8 mac_addr[ETH_ALEN]; 2434 u8 bssid[ETH_ALEN]; 2435 u8 phy_idx; 2436 u8 mac_idx; 2437 u8 net_type; 2438 u8 wifi_role; 2439 u8 self_role; 2440 u8 wmm; 2441 u8 bcn_hit_cond; 2442 u8 hit_rule; 2443 u8 last_noa_nr; 2444 bool trigger; 2445 bool lsig_txop; 2446 u8 tgt_ind; 2447 u8 frm_tgt_ind; 2448 bool wowlan_pattern; 2449 bool wowlan_uc; 2450 bool wowlan_magic; 2451 bool is_hesta; 2452 bool last_a_ctrl; 2453 bool dyn_tb_bedge_en; 2454 u8 def_tri_idx; 2455 u32 tdls_peer; 2456 struct work_struct update_beacon_work; 2457 struct rtw89_addr_cam_entry addr_cam; 2458 struct rtw89_bssid_cam_entry bssid_cam; 2459 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 2460 struct rtw89_traffic_stats stats; 2461 struct rtw89_phy_rate_pattern rate_pattern; 2462 struct cfg80211_scan_request *scan_req; 2463 struct ieee80211_scan_ies *scan_ies; 2464 struct list_head general_pkt_list; 2465 }; 2466 2467 enum rtw89_lv1_rcvy_step { 2468 RTW89_LV1_RCVY_STEP_1, 2469 RTW89_LV1_RCVY_STEP_2, 2470 }; 2471 2472 struct rtw89_hci_ops { 2473 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 2474 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 2475 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 2476 void (*reset)(struct rtw89_dev *rtwdev); 2477 int (*start)(struct rtw89_dev *rtwdev); 2478 void (*stop)(struct rtw89_dev *rtwdev); 2479 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 2480 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 2481 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 2482 2483 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 2484 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 2485 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 2486 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 2487 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 2488 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 2489 2490 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 2491 int (*mac_post_init)(struct rtw89_dev *rtwdev); 2492 int (*deinit)(struct rtw89_dev *rtwdev); 2493 2494 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 2495 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 2496 void (*dump_err_status)(struct rtw89_dev *rtwdev); 2497 int (*napi_poll)(struct napi_struct *napi, int budget); 2498 2499 /* Deal with locks inside recovery_start and recovery_complete callbacks 2500 * by hci instance, and handle things which need to consider under SER. 2501 * e.g. turn on/off interrupts except for the one for halt notification. 2502 */ 2503 void (*recovery_start)(struct rtw89_dev *rtwdev); 2504 void (*recovery_complete)(struct rtw89_dev *rtwdev); 2505 2506 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 2507 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 2508 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 2509 int (*poll_txdma_ch)(struct rtw89_dev *rtwdev); 2510 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 2511 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 2512 void (*disable_intr)(struct rtw89_dev *rtwdev); 2513 void (*enable_intr)(struct rtw89_dev *rtwdev); 2514 int (*rst_bdram)(struct rtw89_dev *rtwdev); 2515 }; 2516 2517 struct rtw89_hci_info { 2518 const struct rtw89_hci_ops *ops; 2519 enum rtw89_hci_type type; 2520 u32 rpwm_addr; 2521 u32 cpwm_addr; 2522 bool paused; 2523 }; 2524 2525 struct rtw89_chip_ops { 2526 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 2527 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 2528 void (*bb_reset)(struct rtw89_dev *rtwdev, 2529 enum rtw89_phy_idx phy_idx); 2530 void (*bb_sethw)(struct rtw89_dev *rtwdev); 2531 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2532 u32 addr, u32 mask); 2533 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2534 u32 addr, u32 mask, u32 data); 2535 void (*set_channel)(struct rtw89_dev *rtwdev, 2536 const struct rtw89_chan *chan, 2537 enum rtw89_mac_idx mac_idx, 2538 enum rtw89_phy_idx phy_idx); 2539 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 2540 struct rtw89_channel_help_params *p, 2541 const struct rtw89_chan *chan, 2542 enum rtw89_mac_idx mac_idx, 2543 enum rtw89_phy_idx phy_idx); 2544 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map); 2545 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 2546 void (*fem_setup)(struct rtw89_dev *rtwdev); 2547 void (*rfk_init)(struct rtw89_dev *rtwdev); 2548 void (*rfk_channel)(struct rtw89_dev *rtwdev); 2549 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 2550 enum rtw89_phy_idx phy_idx); 2551 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 2552 void (*rfk_track)(struct rtw89_dev *rtwdev); 2553 void (*power_trim)(struct rtw89_dev *rtwdev); 2554 void (*set_txpwr)(struct rtw89_dev *rtwdev, 2555 const struct rtw89_chan *chan, 2556 enum rtw89_phy_idx phy_idx); 2557 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 2558 enum rtw89_phy_idx phy_idx); 2559 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 2560 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 2561 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg); 2562 void (*query_ppdu)(struct rtw89_dev *rtwdev, 2563 struct rtw89_rx_phy_ppdu *phy_ppdu, 2564 struct ieee80211_rx_status *status); 2565 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en); 2566 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 2567 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 2568 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 2569 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 2570 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 2571 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 2572 struct rtw89_tx_desc_info *desc_info, 2573 void *txdesc); 2574 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 2575 struct rtw89_tx_desc_info *desc_info, 2576 void *txdesc); 2577 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 2578 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 2579 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 2580 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 2581 u32 *tx_en, enum rtw89_sch_tx_sel sel); 2582 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 2583 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 2584 struct rtw89_vif *rtwvif, 2585 struct rtw89_sta *rtwsta); 2586 2587 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 2588 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 2589 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 2590 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 2591 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 2592 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 2593 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 2594 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 2595 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 2596 }; 2597 2598 enum rtw89_dma_ch { 2599 RTW89_DMA_ACH0 = 0, 2600 RTW89_DMA_ACH1 = 1, 2601 RTW89_DMA_ACH2 = 2, 2602 RTW89_DMA_ACH3 = 3, 2603 RTW89_DMA_ACH4 = 4, 2604 RTW89_DMA_ACH5 = 5, 2605 RTW89_DMA_ACH6 = 6, 2606 RTW89_DMA_ACH7 = 7, 2607 RTW89_DMA_B0MG = 8, 2608 RTW89_DMA_B0HI = 9, 2609 RTW89_DMA_B1MG = 10, 2610 RTW89_DMA_B1HI = 11, 2611 RTW89_DMA_H2C = 12, 2612 RTW89_DMA_CH_NUM = 13 2613 }; 2614 2615 enum rtw89_qta_mode { 2616 RTW89_QTA_SCC, 2617 RTW89_QTA_DLFW, 2618 RTW89_QTA_WOW, 2619 2620 /* keep last */ 2621 RTW89_QTA_INVALID, 2622 }; 2623 2624 struct rtw89_hfc_ch_cfg { 2625 u16 min; 2626 u16 max; 2627 #define grp_0 0 2628 #define grp_1 1 2629 #define grp_num 2 2630 u8 grp; 2631 }; 2632 2633 struct rtw89_hfc_ch_info { 2634 u16 aval; 2635 u16 used; 2636 }; 2637 2638 struct rtw89_hfc_pub_cfg { 2639 u16 grp0; 2640 u16 grp1; 2641 u16 pub_max; 2642 u16 wp_thrd; 2643 }; 2644 2645 struct rtw89_hfc_pub_info { 2646 u16 g0_used; 2647 u16 g1_used; 2648 u16 g0_aval; 2649 u16 g1_aval; 2650 u16 pub_aval; 2651 u16 wp_aval; 2652 }; 2653 2654 struct rtw89_hfc_prec_cfg { 2655 u16 ch011_prec; 2656 u16 h2c_prec; 2657 u16 wp_ch07_prec; 2658 u16 wp_ch811_prec; 2659 u8 ch011_full_cond; 2660 u8 h2c_full_cond; 2661 u8 wp_ch07_full_cond; 2662 u8 wp_ch811_full_cond; 2663 }; 2664 2665 struct rtw89_hfc_param { 2666 bool en; 2667 bool h2c_en; 2668 u8 mode; 2669 const struct rtw89_hfc_ch_cfg *ch_cfg; 2670 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 2671 struct rtw89_hfc_pub_cfg pub_cfg; 2672 struct rtw89_hfc_pub_info pub_info; 2673 struct rtw89_hfc_prec_cfg prec_cfg; 2674 }; 2675 2676 struct rtw89_hfc_param_ini { 2677 const struct rtw89_hfc_ch_cfg *ch_cfg; 2678 const struct rtw89_hfc_pub_cfg *pub_cfg; 2679 const struct rtw89_hfc_prec_cfg *prec_cfg; 2680 u8 mode; 2681 }; 2682 2683 struct rtw89_dle_size { 2684 u16 pge_size; 2685 u16 lnk_pge_num; 2686 u16 unlnk_pge_num; 2687 }; 2688 2689 struct rtw89_wde_quota { 2690 u16 hif; 2691 u16 wcpu; 2692 u16 pkt_in; 2693 u16 cpu_io; 2694 }; 2695 2696 struct rtw89_ple_quota { 2697 u16 cma0_tx; 2698 u16 cma1_tx; 2699 u16 c2h; 2700 u16 h2c; 2701 u16 wcpu; 2702 u16 mpdu_proc; 2703 u16 cma0_dma; 2704 u16 cma1_dma; 2705 u16 bb_rpt; 2706 u16 wd_rel; 2707 u16 cpu_io; 2708 u16 tx_rpt; 2709 }; 2710 2711 struct rtw89_dle_mem { 2712 enum rtw89_qta_mode mode; 2713 const struct rtw89_dle_size *wde_size; 2714 const struct rtw89_dle_size *ple_size; 2715 const struct rtw89_wde_quota *wde_min_qt; 2716 const struct rtw89_wde_quota *wde_max_qt; 2717 const struct rtw89_ple_quota *ple_min_qt; 2718 const struct rtw89_ple_quota *ple_max_qt; 2719 }; 2720 2721 struct rtw89_reg_def { 2722 u32 addr; 2723 u32 mask; 2724 }; 2725 2726 struct rtw89_reg2_def { 2727 u32 addr; 2728 u32 data; 2729 }; 2730 2731 struct rtw89_reg3_def { 2732 u32 addr; 2733 u32 mask; 2734 u32 data; 2735 }; 2736 2737 struct rtw89_reg5_def { 2738 u8 flag; /* recognized by parsers */ 2739 u8 path; 2740 u32 addr; 2741 u32 mask; 2742 u32 data; 2743 }; 2744 2745 struct rtw89_phy_table { 2746 const struct rtw89_reg2_def *regs; 2747 u32 n_regs; 2748 enum rtw89_rf_path rf_path; 2749 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 2750 enum rtw89_rf_path rf_path, void *data); 2751 }; 2752 2753 struct rtw89_txpwr_table { 2754 const void *data; 2755 u32 size; 2756 void (*load)(struct rtw89_dev *rtwdev, 2757 const struct rtw89_txpwr_table *tbl); 2758 }; 2759 2760 struct rtw89_page_regs { 2761 u32 hci_fc_ctrl; 2762 u32 ch_page_ctrl; 2763 u32 ach_page_ctrl; 2764 u32 ach_page_info; 2765 u32 pub_page_info3; 2766 u32 pub_page_ctrl1; 2767 u32 pub_page_ctrl2; 2768 u32 pub_page_info1; 2769 u32 pub_page_info2; 2770 u32 wp_page_ctrl1; 2771 u32 wp_page_ctrl2; 2772 u32 wp_page_info1; 2773 }; 2774 2775 struct rtw89_imr_info { 2776 u32 wdrls_imr_set; 2777 u32 wsec_imr_reg; 2778 u32 wsec_imr_set; 2779 u32 mpdu_tx_imr_set; 2780 u32 mpdu_rx_imr_set; 2781 u32 sta_sch_imr_set; 2782 u32 txpktctl_imr_b0_reg; 2783 u32 txpktctl_imr_b0_clr; 2784 u32 txpktctl_imr_b0_set; 2785 u32 txpktctl_imr_b1_reg; 2786 u32 txpktctl_imr_b1_clr; 2787 u32 txpktctl_imr_b1_set; 2788 u32 wde_imr_clr; 2789 u32 wde_imr_set; 2790 u32 ple_imr_clr; 2791 u32 ple_imr_set; 2792 u32 host_disp_imr_clr; 2793 u32 host_disp_imr_set; 2794 u32 cpu_disp_imr_clr; 2795 u32 cpu_disp_imr_set; 2796 u32 other_disp_imr_clr; 2797 u32 other_disp_imr_set; 2798 u32 bbrpt_com_err_imr_reg; 2799 u32 bbrpt_chinfo_err_imr_reg; 2800 u32 bbrpt_err_imr_set; 2801 u32 bbrpt_dfs_err_imr_reg; 2802 u32 ptcl_imr_clr; 2803 u32 ptcl_imr_set; 2804 u32 cdma_imr_0_reg; 2805 u32 cdma_imr_0_clr; 2806 u32 cdma_imr_0_set; 2807 u32 cdma_imr_1_reg; 2808 u32 cdma_imr_1_clr; 2809 u32 cdma_imr_1_set; 2810 u32 phy_intf_imr_reg; 2811 u32 phy_intf_imr_clr; 2812 u32 phy_intf_imr_set; 2813 u32 rmac_imr_reg; 2814 u32 rmac_imr_clr; 2815 u32 rmac_imr_set; 2816 u32 tmac_imr_reg; 2817 u32 tmac_imr_clr; 2818 u32 tmac_imr_set; 2819 }; 2820 2821 struct rtw89_rrsr_cfgs { 2822 struct rtw89_reg3_def ref_rate; 2823 struct rtw89_reg3_def rsc; 2824 }; 2825 2826 struct rtw89_dig_regs { 2827 u32 seg0_pd_reg; 2828 u32 pd_lower_bound_mask; 2829 u32 pd_spatial_reuse_en; 2830 struct rtw89_reg_def p0_lna_init; 2831 struct rtw89_reg_def p1_lna_init; 2832 struct rtw89_reg_def p0_tia_init; 2833 struct rtw89_reg_def p1_tia_init; 2834 struct rtw89_reg_def p0_rxb_init; 2835 struct rtw89_reg_def p1_rxb_init; 2836 struct rtw89_reg_def p0_p20_pagcugc_en; 2837 struct rtw89_reg_def p0_s20_pagcugc_en; 2838 struct rtw89_reg_def p1_p20_pagcugc_en; 2839 struct rtw89_reg_def p1_s20_pagcugc_en; 2840 }; 2841 2842 struct rtw89_phy_ul_tb_info { 2843 bool dyn_tb_tri_en; 2844 u8 def_if_bandedge; 2845 }; 2846 2847 struct rtw89_chip_info { 2848 enum rtw89_core_chip_id chip_id; 2849 const struct rtw89_chip_ops *ops; 2850 const char *fw_name; 2851 bool try_ce_fw; 2852 u32 fifo_size; 2853 u32 dle_scc_rsvd_size; 2854 u16 max_amsdu_limit; 2855 bool dis_2g_40m_ul_ofdma; 2856 u32 rsvd_ple_ofst; 2857 const struct rtw89_hfc_param_ini *hfc_param_ini; 2858 const struct rtw89_dle_mem *dle_mem; 2859 u8 wde_qempty_acq_num; 2860 u8 wde_qempty_mgq_sel; 2861 u32 rf_base_addr[2]; 2862 u8 support_chanctx_num; 2863 u8 support_bands; 2864 bool support_bw160; 2865 bool support_ul_tb_ctrl; 2866 bool hw_sec_hdr; 2867 u8 rf_path_num; 2868 u8 tx_nss; 2869 u8 rx_nss; 2870 u8 acam_num; 2871 u8 bcam_num; 2872 u8 scam_num; 2873 u8 bacam_num; 2874 u8 bacam_dynamic_num; 2875 bool bacam_v1; 2876 2877 u8 sec_ctrl_efuse_size; 2878 u32 physical_efuse_size; 2879 u32 logical_efuse_size; 2880 u32 limit_efuse_size; 2881 u32 dav_phy_efuse_size; 2882 u32 dav_log_efuse_size; 2883 u32 phycap_addr; 2884 u32 phycap_size; 2885 2886 const struct rtw89_pwr_cfg * const *pwr_on_seq; 2887 const struct rtw89_pwr_cfg * const *pwr_off_seq; 2888 const struct rtw89_phy_table *bb_table; 2889 const struct rtw89_phy_table *bb_gain_table; 2890 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 2891 const struct rtw89_phy_table *nctl_table; 2892 const struct rtw89_txpwr_table *byr_table; 2893 const struct rtw89_phy_dig_gain_table *dig_table; 2894 const struct rtw89_dig_regs *dig_regs; 2895 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 2896 const s8 (*txpwr_lmt_2g)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 2897 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2898 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 2899 const s8 (*txpwr_lmt_5g)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 2900 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2901 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 2902 const s8 (*txpwr_lmt_6g)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 2903 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2904 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 2905 const s8 (*txpwr_lmt_ru_2g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2906 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 2907 const s8 (*txpwr_lmt_ru_5g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2908 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 2909 const s8 (*txpwr_lmt_ru_6g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2910 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 2911 2912 u8 txpwr_factor_rf; 2913 u8 txpwr_factor_mac; 2914 2915 u32 para_ver; 2916 u32 wlcx_desired; 2917 u8 btcx_desired; 2918 u8 scbd; 2919 u8 mailbox; 2920 2921 u8 afh_guard_ch; 2922 const u8 *wl_rssi_thres; 2923 const u8 *bt_rssi_thres; 2924 u8 rssi_tol; 2925 2926 u8 mon_reg_num; 2927 const struct rtw89_btc_fbtc_mreg *mon_reg; 2928 u8 rf_para_ulink_num; 2929 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 2930 u8 rf_para_dlink_num; 2931 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 2932 u8 ps_mode_supported; 2933 u8 low_power_hci_modes; 2934 2935 u32 h2c_cctl_func_id; 2936 u32 hci_func_en_addr; 2937 u32 h2c_desc_size; 2938 u32 txwd_body_size; 2939 u32 h2c_ctrl_reg; 2940 const u32 *h2c_regs; 2941 u32 c2h_ctrl_reg; 2942 const u32 *c2h_regs; 2943 const struct rtw89_page_regs *page_regs; 2944 bool cfo_src_fd; 2945 const struct rtw89_reg_def *dcfo_comp; 2946 u8 dcfo_comp_sft; 2947 const struct rtw89_imr_info *imr_info; 2948 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 2949 u32 bss_clr_map_reg; 2950 u32 dma_ch_mask; 2951 const struct wiphy_wowlan_support *wowlan_stub; 2952 }; 2953 2954 union rtw89_bus_info { 2955 const struct rtw89_pci_info *pci; 2956 }; 2957 2958 struct rtw89_driver_info { 2959 const struct rtw89_chip_info *chip; 2960 union rtw89_bus_info bus; 2961 }; 2962 2963 enum rtw89_hcifc_mode { 2964 RTW89_HCIFC_POH = 0, 2965 RTW89_HCIFC_STF = 1, 2966 RTW89_HCIFC_SDIO = 2, 2967 2968 /* keep last */ 2969 RTW89_HCIFC_MODE_INVALID, 2970 }; 2971 2972 struct rtw89_dle_info { 2973 enum rtw89_qta_mode qta_mode; 2974 u16 wde_pg_size; 2975 u16 ple_pg_size; 2976 u16 c0_rx_qta; 2977 u16 c1_rx_qta; 2978 }; 2979 2980 enum rtw89_host_rpr_mode { 2981 RTW89_RPR_MODE_POH = 0, 2982 RTW89_RPR_MODE_STF 2983 }; 2984 2985 struct rtw89_mac_info { 2986 struct rtw89_dle_info dle_info; 2987 struct rtw89_hfc_param hfc_param; 2988 enum rtw89_qta_mode qta_mode; 2989 u8 rpwm_seq_num; 2990 u8 cpwm_seq_num; 2991 }; 2992 2993 #define RTW89_COMPLETION_BUF_SIZE 24 2994 #define RTW89_WAIT_COND_IDLE UINT_MAX 2995 2996 struct rtw89_completion_data { 2997 bool err; 2998 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 2999 }; 3000 3001 struct rtw89_wait_info { 3002 atomic_t cond; 3003 struct completion completion; 3004 struct rtw89_completion_data data; 3005 }; 3006 3007 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 3008 3009 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 3010 { 3011 init_completion(&wait->completion); 3012 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 3013 } 3014 3015 enum rtw89_fw_type { 3016 RTW89_FW_NORMAL = 1, 3017 RTW89_FW_WOWLAN = 3, 3018 RTW89_FW_NORMAL_CE = 5, 3019 }; 3020 3021 enum rtw89_fw_feature { 3022 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 3023 RTW89_FW_FEATURE_SCAN_OFFLOAD, 3024 RTW89_FW_FEATURE_TX_WAKE, 3025 RTW89_FW_FEATURE_CRASH_TRIGGER, 3026 RTW89_FW_FEATURE_PACKET_DROP, 3027 RTW89_FW_FEATURE_NO_DEEP_PS, 3028 RTW89_FW_FEATURE_NO_LPS_PG, 3029 }; 3030 3031 struct rtw89_fw_suit { 3032 const u8 *data; 3033 u32 size; 3034 u8 major_ver; 3035 u8 minor_ver; 3036 u8 sub_ver; 3037 u8 sub_idex; 3038 u16 build_year; 3039 u16 build_mon; 3040 u16 build_date; 3041 u16 build_hour; 3042 u16 build_min; 3043 u8 cmd_ver; 3044 }; 3045 3046 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 3047 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 3048 #define RTW89_FW_SUIT_VER_CODE(s) \ 3049 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 3050 3051 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 3052 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 3053 (mfw_hdr)->ver.minor, \ 3054 (mfw_hdr)->ver.sub, \ 3055 (mfw_hdr)->ver.idx) 3056 3057 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 3058 RTW89_FW_VER_CODE(GET_FW_HDR_MAJOR_VERSION(fw_hdr), \ 3059 GET_FW_HDR_MINOR_VERSION(fw_hdr), \ 3060 GET_FW_HDR_SUBVERSION(fw_hdr), \ 3061 GET_FW_HDR_SUBINDEX(fw_hdr)) 3062 3063 struct rtw89_fw_info { 3064 const struct firmware *firmware; 3065 struct rtw89_dev *rtwdev; 3066 struct completion completion; 3067 u8 h2c_seq; 3068 u8 rec_seq; 3069 struct rtw89_fw_suit normal; 3070 struct rtw89_fw_suit wowlan; 3071 bool fw_log_enable; 3072 u32 feature_map; 3073 }; 3074 3075 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 3076 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 3077 3078 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 3079 ((_fw)->feature_map |= BIT(_fw_feature)) 3080 3081 struct rtw89_cam_info { 3082 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 3083 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 3084 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 3085 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 3086 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 3087 }; 3088 3089 enum rtw89_sar_sources { 3090 RTW89_SAR_SOURCE_NONE, 3091 RTW89_SAR_SOURCE_COMMON, 3092 3093 RTW89_SAR_SOURCE_NR, 3094 }; 3095 3096 enum rtw89_sar_subband { 3097 RTW89_SAR_2GHZ_SUBBAND, 3098 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 3099 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 3100 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 3101 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 3102 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 3103 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 3104 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 3105 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 3106 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 3107 3108 RTW89_SAR_SUBBAND_NR, 3109 }; 3110 3111 struct rtw89_sar_cfg_common { 3112 bool set[RTW89_SAR_SUBBAND_NR]; 3113 s32 cfg[RTW89_SAR_SUBBAND_NR]; 3114 }; 3115 3116 struct rtw89_sar_info { 3117 /* used to decide how to acces SAR cfg union */ 3118 enum rtw89_sar_sources src; 3119 3120 /* reserved for different knids of SAR cfg struct. 3121 * supposed that a single cfg struct cannot handle various SAR sources. 3122 */ 3123 union { 3124 struct rtw89_sar_cfg_common cfg_common; 3125 }; 3126 }; 3127 3128 struct rtw89_chanctx_cfg { 3129 enum rtw89_sub_entity_idx idx; 3130 }; 3131 3132 enum rtw89_entity_mode { 3133 RTW89_ENTITY_MODE_SCC, 3134 }; 3135 3136 struct rtw89_sub_entity { 3137 struct cfg80211_chan_def chandef; 3138 struct rtw89_chan chan; 3139 struct rtw89_chan_rcd rcd; 3140 struct rtw89_chanctx_cfg *cfg; 3141 }; 3142 3143 struct rtw89_hal { 3144 u32 rx_fltr; 3145 u8 cv; 3146 u32 sw_amsdu_max_size; 3147 u32 antenna_tx; 3148 u32 antenna_rx; 3149 u8 tx_nss; 3150 u8 rx_nss; 3151 bool tx_path_diversity; 3152 bool support_cckpd; 3153 bool support_igi; 3154 3155 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 3156 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY]; 3157 3158 bool entity_active; 3159 enum rtw89_entity_mode entity_mode; 3160 }; 3161 3162 #define RTW89_MAX_MAC_ID_NUM 128 3163 #define RTW89_MAX_PKT_OFLD_NUM 255 3164 3165 enum rtw89_flags { 3166 RTW89_FLAG_POWERON, 3167 RTW89_FLAG_FW_RDY, 3168 RTW89_FLAG_RUNNING, 3169 RTW89_FLAG_BFEE_MON, 3170 RTW89_FLAG_BFEE_EN, 3171 RTW89_FLAG_NAPI_RUNNING, 3172 RTW89_FLAG_LEISURE_PS, 3173 RTW89_FLAG_LOW_POWER_MODE, 3174 RTW89_FLAG_INACTIVE_PS, 3175 RTW89_FLAG_CRASH_SIMULATING, 3176 RTW89_FLAG_WOWLAN, 3177 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 3178 RTW89_FLAG_CHANGING_INTERFACE, 3179 3180 NUM_OF_RTW89_FLAGS, 3181 }; 3182 3183 enum rtw89_pkt_drop_sel { 3184 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 3185 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 3186 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 3187 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 3188 RTW89_PKT_DROP_SEL_MACID_ALL, 3189 RTW89_PKT_DROP_SEL_MG0_ONCE, 3190 RTW89_PKT_DROP_SEL_HIQ_ONCE, 3191 RTW89_PKT_DROP_SEL_HIQ_PORT, 3192 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 3193 RTW89_PKT_DROP_SEL_BAND, 3194 RTW89_PKT_DROP_SEL_BAND_ONCE, 3195 RTW89_PKT_DROP_SEL_REL_MACID, 3196 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 3197 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 3198 }; 3199 3200 struct rtw89_pkt_drop_params { 3201 enum rtw89_pkt_drop_sel sel; 3202 enum rtw89_mac_idx mac_band; 3203 u8 macid; 3204 u8 port; 3205 u8 mbssid; 3206 bool tf_trs; 3207 u32 macid_band_sel[4]; 3208 }; 3209 3210 struct rtw89_pkt_stat { 3211 u16 beacon_nr; 3212 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 3213 }; 3214 3215 DECLARE_EWMA(thermal, 4, 4); 3216 3217 struct rtw89_phy_stat { 3218 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 3219 struct rtw89_pkt_stat cur_pkt_stat; 3220 struct rtw89_pkt_stat last_pkt_stat; 3221 }; 3222 3223 #define RTW89_DACK_PATH_NR 2 3224 #define RTW89_DACK_IDX_NR 2 3225 #define RTW89_DACK_MSBK_NR 16 3226 struct rtw89_dack_info { 3227 bool dack_done; 3228 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 3229 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3230 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3231 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3232 u32 dack_cnt; 3233 bool addck_timeout[RTW89_DACK_PATH_NR]; 3234 bool dadck_timeout[RTW89_DACK_PATH_NR]; 3235 bool msbk_timeout[RTW89_DACK_PATH_NR]; 3236 }; 3237 3238 #define RTW89_IQK_CHS_NR 2 3239 #define RTW89_IQK_PATH_NR 4 3240 3241 struct rtw89_rfk_mcc_info { 3242 u8 ch[RTW89_IQK_CHS_NR]; 3243 u8 band[RTW89_IQK_CHS_NR]; 3244 u8 table_idx; 3245 }; 3246 3247 struct rtw89_lck_info { 3248 u8 thermal[RF_PATH_MAX]; 3249 }; 3250 3251 struct rtw89_rx_dck_info { 3252 u8 thermal[RF_PATH_MAX]; 3253 }; 3254 3255 struct rtw89_iqk_info { 3256 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3257 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3258 bool lok_fail[RTW89_IQK_PATH_NR]; 3259 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3260 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3261 u32 iqk_fail_cnt; 3262 bool is_iqk_init; 3263 u32 iqk_channel[RTW89_IQK_CHS_NR]; 3264 u8 iqk_band[RTW89_IQK_PATH_NR]; 3265 u8 iqk_ch[RTW89_IQK_PATH_NR]; 3266 u8 iqk_bw[RTW89_IQK_PATH_NR]; 3267 u8 kcount; 3268 u8 iqk_times; 3269 u8 version; 3270 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 3271 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 3272 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 3273 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 3274 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 3275 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 3276 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 3277 bool is_nbiqk; 3278 bool iqk_fft_en; 3279 bool iqk_xym_en; 3280 bool iqk_sram_en; 3281 bool iqk_cfir_en; 3282 u8 thermal[RTW89_IQK_PATH_NR]; 3283 bool thermal_rek_en; 3284 u32 syn1to2; 3285 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3286 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 3287 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3288 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3289 }; 3290 3291 #define RTW89_DPK_RF_PATH 2 3292 #define RTW89_DPK_AVG_THERMAL_NUM 8 3293 #define RTW89_DPK_BKUP_NUM 2 3294 struct rtw89_dpk_bkup_para { 3295 enum rtw89_band band; 3296 enum rtw89_bandwidth bw; 3297 u8 ch; 3298 bool path_ok; 3299 u8 mdpd_en; 3300 u8 txagc_dpk; 3301 u8 ther_dpk; 3302 u8 gs; 3303 u16 pwsf; 3304 }; 3305 3306 struct rtw89_dpk_info { 3307 bool is_dpk_enable; 3308 bool is_dpk_reload_en; 3309 u8 dpk_gs[RTW89_PHY_MAX]; 3310 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3311 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3312 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3313 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3314 u8 cur_idx[RTW89_DPK_RF_PATH]; 3315 u8 cur_k_set; 3316 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3317 }; 3318 3319 struct rtw89_fem_info { 3320 bool elna_2g; 3321 bool elna_5g; 3322 bool epa_2g; 3323 bool epa_5g; 3324 bool epa_6g; 3325 }; 3326 3327 struct rtw89_phy_ch_info { 3328 u8 rssi_min; 3329 u16 rssi_min_macid; 3330 u8 pre_rssi_min; 3331 u8 rssi_max; 3332 u16 rssi_max_macid; 3333 u8 rxsc_160; 3334 u8 rxsc_80; 3335 u8 rxsc_40; 3336 u8 rxsc_20; 3337 u8 rxsc_l; 3338 u8 is_noisy; 3339 }; 3340 3341 struct rtw89_agc_gaincode_set { 3342 u8 lna_idx; 3343 u8 tia_idx; 3344 u8 rxb_idx; 3345 }; 3346 3347 #define IGI_RSSI_TH_NUM 5 3348 #define FA_TH_NUM 4 3349 #define LNA_GAIN_NUM 7 3350 #define TIA_GAIN_NUM 2 3351 struct rtw89_dig_info { 3352 struct rtw89_agc_gaincode_set cur_gaincode; 3353 bool force_gaincode_idx_en; 3354 struct rtw89_agc_gaincode_set force_gaincode; 3355 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 3356 u16 fa_th[FA_TH_NUM]; 3357 u8 igi_rssi; 3358 u8 igi_fa_rssi; 3359 u8 fa_rssi_ofst; 3360 u8 dyn_igi_max; 3361 u8 dyn_igi_min; 3362 bool dyn_pd_th_en; 3363 u8 dyn_pd_th_max; 3364 u8 pd_low_th_ofst; 3365 u8 ib_pbk; 3366 s8 ib_pkpwr; 3367 s8 lna_gain_a[LNA_GAIN_NUM]; 3368 s8 lna_gain_g[LNA_GAIN_NUM]; 3369 s8 *lna_gain; 3370 s8 tia_gain_a[TIA_GAIN_NUM]; 3371 s8 tia_gain_g[TIA_GAIN_NUM]; 3372 s8 *tia_gain; 3373 bool is_linked_pre; 3374 bool bypass_dig; 3375 }; 3376 3377 enum rtw89_multi_cfo_mode { 3378 RTW89_PKT_BASED_AVG_MODE = 0, 3379 RTW89_ENTRY_BASED_AVG_MODE = 1, 3380 RTW89_TP_BASED_AVG_MODE = 2, 3381 }; 3382 3383 enum rtw89_phy_cfo_status { 3384 RTW89_PHY_DCFO_STATE_NORMAL = 0, 3385 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 3386 RTW89_PHY_DCFO_STATE_HOLD = 2, 3387 RTW89_PHY_DCFO_STATE_MAX 3388 }; 3389 3390 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 3391 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 3392 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 3393 }; 3394 3395 struct rtw89_cfo_tracking_info { 3396 u16 cfo_timer_ms; 3397 bool cfo_trig_by_timer_en; 3398 enum rtw89_phy_cfo_status phy_cfo_status; 3399 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 3400 u8 phy_cfo_trk_cnt; 3401 bool is_adjust; 3402 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 3403 bool apply_compensation; 3404 u8 crystal_cap; 3405 u8 crystal_cap_default; 3406 u8 def_x_cap; 3407 s8 x_cap_ofst; 3408 u32 sta_cfo_tolerance; 3409 s32 cfo_tail[CFO_TRACK_MAX_USER]; 3410 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 3411 s32 cfo_avg_pre; 3412 s32 cfo_avg[CFO_TRACK_MAX_USER]; 3413 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 3414 u32 packet_count; 3415 u32 packet_count_pre; 3416 s32 residual_cfo_acc; 3417 u8 phy_cfotrk_state; 3418 u8 phy_cfotrk_cnt; 3419 bool divergence_lock_en; 3420 u8 x_cap_lb; 3421 u8 x_cap_ub; 3422 u8 lock_cnt; 3423 }; 3424 3425 enum rtw89_tssi_alimk_band { 3426 TSSI_ALIMK_2G = 0, 3427 TSSI_ALIMK_5GL, 3428 TSSI_ALIMK_5GM, 3429 TSSI_ALIMK_5GH, 3430 TSSI_ALIMK_MAX 3431 }; 3432 3433 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 3434 #define TSSI_TRIM_CH_GROUP_NUM 8 3435 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 3436 3437 #define TSSI_CCK_CH_GROUP_NUM 6 3438 #define TSSI_MCS_2G_CH_GROUP_NUM 5 3439 #define TSSI_MCS_5G_CH_GROUP_NUM 14 3440 #define TSSI_MCS_6G_CH_GROUP_NUM 32 3441 #define TSSI_MCS_CH_GROUP_NUM \ 3442 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 3443 #define TSSI_MAX_CH_NUM 67 3444 #define TSSI_ALIMK_VALUE_NUM 8 3445 3446 struct rtw89_tssi_info { 3447 u8 thermal[RF_PATH_MAX]; 3448 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 3449 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 3450 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 3451 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 3452 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 3453 s8 extra_ofst[RF_PATH_MAX]; 3454 bool tssi_tracking_check[RF_PATH_MAX]; 3455 u8 default_txagc_offset[RF_PATH_MAX]; 3456 u32 base_thermal[RF_PATH_MAX]; 3457 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 3458 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 3459 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 3460 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 3461 u32 tssi_alimk_time; 3462 }; 3463 3464 struct rtw89_power_trim_info { 3465 bool pg_thermal_trim; 3466 bool pg_pa_bias_trim; 3467 u8 thermal_trim[RF_PATH_MAX]; 3468 u8 pa_bias_trim[RF_PATH_MAX]; 3469 }; 3470 3471 struct rtw89_regulatory { 3472 char alpha2[3]; 3473 u8 txpwr_regd[RTW89_BAND_MAX]; 3474 }; 3475 3476 enum rtw89_ifs_clm_application { 3477 RTW89_IFS_CLM_INIT = 0, 3478 RTW89_IFS_CLM_BACKGROUND = 1, 3479 RTW89_IFS_CLM_ACS = 2, 3480 RTW89_IFS_CLM_DIG = 3, 3481 RTW89_IFS_CLM_TDMA_DIG = 4, 3482 RTW89_IFS_CLM_DBG = 5, 3483 RTW89_IFS_CLM_DBG_MANUAL = 6 3484 }; 3485 3486 enum rtw89_env_racing_lv { 3487 RTW89_RAC_RELEASE = 0, 3488 RTW89_RAC_LV_1 = 1, 3489 RTW89_RAC_LV_2 = 2, 3490 RTW89_RAC_LV_3 = 3, 3491 RTW89_RAC_LV_4 = 4, 3492 RTW89_RAC_MAX_NUM = 5 3493 }; 3494 3495 struct rtw89_ccx_para_info { 3496 enum rtw89_env_racing_lv rac_lv; 3497 u16 mntr_time; 3498 u8 nhm_manual_th_ofst; 3499 u8 nhm_manual_th0; 3500 enum rtw89_ifs_clm_application ifs_clm_app; 3501 u32 ifs_clm_manual_th_times; 3502 u32 ifs_clm_manual_th0; 3503 u8 fahm_manual_th_ofst; 3504 u8 fahm_manual_th0; 3505 u8 fahm_numer_opt; 3506 u8 fahm_denom_opt; 3507 }; 3508 3509 enum rtw89_ccx_edcca_opt_sc_idx { 3510 RTW89_CCX_EDCCA_SEG0_P0 = 0, 3511 RTW89_CCX_EDCCA_SEG0_S1 = 1, 3512 RTW89_CCX_EDCCA_SEG0_S2 = 2, 3513 RTW89_CCX_EDCCA_SEG0_S3 = 3, 3514 RTW89_CCX_EDCCA_SEG1_P0 = 4, 3515 RTW89_CCX_EDCCA_SEG1_S1 = 5, 3516 RTW89_CCX_EDCCA_SEG1_S2 = 6, 3517 RTW89_CCX_EDCCA_SEG1_S3 = 7 3518 }; 3519 3520 enum rtw89_ccx_edcca_opt_bw_idx { 3521 RTW89_CCX_EDCCA_BW20_0 = 0, 3522 RTW89_CCX_EDCCA_BW20_1 = 1, 3523 RTW89_CCX_EDCCA_BW20_2 = 2, 3524 RTW89_CCX_EDCCA_BW20_3 = 3, 3525 RTW89_CCX_EDCCA_BW20_4 = 4, 3526 RTW89_CCX_EDCCA_BW20_5 = 5, 3527 RTW89_CCX_EDCCA_BW20_6 = 6, 3528 RTW89_CCX_EDCCA_BW20_7 = 7 3529 }; 3530 3531 #define RTW89_NHM_TH_NUM 11 3532 #define RTW89_FAHM_TH_NUM 11 3533 #define RTW89_NHM_RPT_NUM 12 3534 #define RTW89_FAHM_RPT_NUM 12 3535 #define RTW89_IFS_CLM_NUM 4 3536 struct rtw89_env_monitor_info { 3537 u32 ccx_trigger_time; 3538 u64 start_time; 3539 u8 ccx_rpt_stamp; 3540 u8 ccx_watchdog_result; 3541 bool ccx_ongoing; 3542 u8 ccx_rac_lv; 3543 bool ccx_manual_ctrl; 3544 u8 ccx_pre_rssi; 3545 u16 clm_mntr_time; 3546 u16 nhm_mntr_time; 3547 u16 ifs_clm_mntr_time; 3548 enum rtw89_ifs_clm_application ifs_clm_app; 3549 u16 fahm_mntr_time; 3550 u16 edcca_clm_mntr_time; 3551 u16 ccx_period; 3552 u8 ccx_unit_idx; 3553 enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx; 3554 u8 nhm_th[RTW89_NHM_TH_NUM]; 3555 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 3556 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 3557 u8 fahm_numer_opt; 3558 u8 fahm_denom_opt; 3559 u8 fahm_th[RTW89_FAHM_TH_NUM]; 3560 u16 clm_result; 3561 u16 nhm_result[RTW89_NHM_RPT_NUM]; 3562 u8 nhm_wgt[RTW89_NHM_RPT_NUM]; 3563 u16 nhm_tx_cnt; 3564 u16 nhm_cca_cnt; 3565 u16 nhm_idle_cnt; 3566 u16 ifs_clm_tx; 3567 u16 ifs_clm_edcca_excl_cca; 3568 u16 ifs_clm_ofdmfa; 3569 u16 ifs_clm_ofdmcca_excl_fa; 3570 u16 ifs_clm_cckfa; 3571 u16 ifs_clm_cckcca_excl_fa; 3572 u16 ifs_clm_total_ifs; 3573 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 3574 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 3575 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 3576 u16 fahm_result[RTW89_FAHM_RPT_NUM]; 3577 u16 fahm_denom_result; 3578 u16 edcca_clm_result; 3579 u8 clm_ratio; 3580 u8 nhm_rpt[RTW89_NHM_RPT_NUM]; 3581 u8 nhm_tx_ratio; 3582 u8 nhm_cca_ratio; 3583 u8 nhm_idle_ratio; 3584 u8 nhm_ratio; 3585 u16 nhm_result_sum; 3586 u8 nhm_pwr; 3587 u8 ifs_clm_tx_ratio; 3588 u8 ifs_clm_edcca_excl_cca_ratio; 3589 u8 ifs_clm_cck_fa_ratio; 3590 u8 ifs_clm_ofdm_fa_ratio; 3591 u8 ifs_clm_cck_cca_excl_fa_ratio; 3592 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 3593 u16 ifs_clm_cck_fa_permil; 3594 u16 ifs_clm_ofdm_fa_permil; 3595 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 3596 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 3597 u8 fahm_rpt[RTW89_FAHM_RPT_NUM]; 3598 u16 fahm_result_sum; 3599 u8 fahm_ratio; 3600 u8 fahm_denom_ratio; 3601 u8 fahm_pwr; 3602 u8 edcca_clm_ratio; 3603 }; 3604 3605 enum rtw89_ser_rcvy_step { 3606 RTW89_SER_DRV_STOP_TX, 3607 RTW89_SER_DRV_STOP_RX, 3608 RTW89_SER_DRV_STOP_RUN, 3609 RTW89_SER_HAL_STOP_DMA, 3610 RTW89_NUM_OF_SER_FLAGS 3611 }; 3612 3613 struct rtw89_ser { 3614 u8 state; 3615 u8 alarm_event; 3616 3617 struct work_struct ser_hdl_work; 3618 struct delayed_work ser_alarm_work; 3619 const struct state_ent *st_tbl; 3620 const struct event_ent *ev_tbl; 3621 struct list_head msg_q; 3622 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 3623 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 3624 }; 3625 3626 enum rtw89_mac_ax_ps_mode { 3627 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 3628 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 3629 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 3630 RTW89_MAC_AX_PS_MODE_MAX = 3, 3631 }; 3632 3633 enum rtw89_last_rpwm_mode { 3634 RTW89_LAST_RPWM_PS = 0x0, 3635 RTW89_LAST_RPWM_ACTIVE = 0x6, 3636 }; 3637 3638 struct rtw89_lps_parm { 3639 u8 macid; 3640 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 3641 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 3642 }; 3643 3644 struct rtw89_ppdu_sts_info { 3645 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 3646 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 3647 }; 3648 3649 struct rtw89_early_h2c { 3650 struct list_head list; 3651 u8 *h2c; 3652 u16 h2c_len; 3653 }; 3654 3655 struct rtw89_hw_scan_info { 3656 struct ieee80211_vif *scanning_vif; 3657 struct list_head pkt_list[NUM_NL80211_BANDS]; 3658 u8 op_pri_ch; 3659 u8 op_chan; 3660 u8 op_bw; 3661 u8 op_band; 3662 u32 last_chan_idx; 3663 }; 3664 3665 enum rtw89_phy_bb_gain_band { 3666 RTW89_BB_GAIN_BAND_2G = 0, 3667 RTW89_BB_GAIN_BAND_5G_L = 1, 3668 RTW89_BB_GAIN_BAND_5G_M = 2, 3669 RTW89_BB_GAIN_BAND_5G_H = 3, 3670 RTW89_BB_GAIN_BAND_6G_L = 4, 3671 RTW89_BB_GAIN_BAND_6G_M = 5, 3672 RTW89_BB_GAIN_BAND_6G_H = 6, 3673 RTW89_BB_GAIN_BAND_6G_UH = 7, 3674 3675 RTW89_BB_GAIN_BAND_NR, 3676 }; 3677 3678 enum rtw89_phy_bb_rxsc_num { 3679 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 3680 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 3681 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 3682 }; 3683 3684 struct rtw89_phy_bb_gain_info { 3685 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3686 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 3687 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3688 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3689 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3690 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 3691 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 3692 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3693 [RTW89_BB_RXSC_NUM_40]; 3694 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3695 [RTW89_BB_RXSC_NUM_80]; 3696 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3697 [RTW89_BB_RXSC_NUM_160]; 3698 }; 3699 3700 struct rtw89_phy_efuse_gain { 3701 bool offset_valid; 3702 bool comp_valid; 3703 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 3704 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 3705 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 3706 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 3707 }; 3708 3709 #define RTW89_MAX_PATTERN_NUM 18 3710 #define RTW89_MAX_PATTERN_MASK_SIZE 4 3711 #define RTW89_MAX_PATTERN_SIZE 128 3712 3713 struct rtw89_wow_cam_info { 3714 bool r_w; 3715 u8 idx; 3716 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 3717 u16 crc; 3718 bool negative_pattern_match; 3719 bool skip_mac_hdr; 3720 bool uc; 3721 bool mc; 3722 bool bc; 3723 bool valid; 3724 }; 3725 3726 struct rtw89_wow_param { 3727 struct ieee80211_vif *wow_vif; 3728 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 3729 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 3730 u8 pattern_cnt; 3731 }; 3732 3733 struct rtw89_mcc_info { 3734 struct rtw89_wait_info wait; 3735 }; 3736 3737 struct rtw89_dev { 3738 struct ieee80211_hw *hw; 3739 struct device *dev; 3740 const struct ieee80211_ops *ops; 3741 3742 bool dbcc_en; 3743 struct rtw89_hw_scan_info scan_info; 3744 const struct rtw89_chip_info *chip; 3745 const struct rtw89_pci_info *pci_info; 3746 struct rtw89_hal hal; 3747 struct rtw89_mcc_info mcc; 3748 struct rtw89_mac_info mac; 3749 struct rtw89_fw_info fw; 3750 struct rtw89_hci_info hci; 3751 struct rtw89_efuse efuse; 3752 struct rtw89_traffic_stats stats; 3753 3754 /* ensures exclusive access from mac80211 callbacks */ 3755 struct mutex mutex; 3756 struct list_head rtwvifs_list; 3757 /* used to protect rf read write */ 3758 struct mutex rf_mutex; 3759 struct workqueue_struct *txq_wq; 3760 struct work_struct txq_work; 3761 struct delayed_work txq_reinvoke_work; 3762 /* used to protect ba_list and forbid_ba_list */ 3763 spinlock_t ba_lock; 3764 /* txqs to setup ba session */ 3765 struct list_head ba_list; 3766 /* txqs to forbid ba session */ 3767 struct list_head forbid_ba_list; 3768 struct work_struct ba_work; 3769 /* used to protect rpwm */ 3770 spinlock_t rpwm_lock; 3771 3772 struct rtw89_cam_info cam_info; 3773 3774 struct sk_buff_head c2h_queue; 3775 struct work_struct c2h_work; 3776 struct work_struct ips_work; 3777 3778 struct list_head early_h2c_list; 3779 3780 struct rtw89_ser ser; 3781 3782 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 3783 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 3784 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 3785 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 3786 3787 struct rtw89_phy_stat phystat; 3788 struct rtw89_dack_info dack; 3789 struct rtw89_iqk_info iqk; 3790 struct rtw89_dpk_info dpk; 3791 struct rtw89_rfk_mcc_info rfk_mcc; 3792 struct rtw89_lck_info lck; 3793 struct rtw89_rx_dck_info rx_dck; 3794 bool is_tssi_mode[RF_PATH_MAX]; 3795 bool is_bt_iqk_timeout; 3796 3797 struct rtw89_fem_info fem; 3798 struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX]; 3799 struct rtw89_tssi_info tssi; 3800 struct rtw89_power_trim_info pwr_trim; 3801 3802 struct rtw89_cfo_tracking_info cfo_tracking; 3803 struct rtw89_env_monitor_info env_monitor; 3804 struct rtw89_dig_info dig; 3805 struct rtw89_phy_ch_info ch_info; 3806 struct rtw89_phy_bb_gain_info bb_gain; 3807 struct rtw89_phy_efuse_gain efuse_gain; 3808 struct rtw89_phy_ul_tb_info ul_tb_info; 3809 3810 struct delayed_work track_work; 3811 struct delayed_work coex_act1_work; 3812 struct delayed_work coex_bt_devinfo_work; 3813 struct delayed_work coex_rfk_chk_work; 3814 struct delayed_work cfo_track_work; 3815 struct delayed_work forbid_ba_work; 3816 struct rtw89_ppdu_sts_info ppdu_sts; 3817 u8 total_sta_assoc; 3818 bool scanning; 3819 3820 const struct rtw89_regulatory *regd; 3821 struct rtw89_sar_info sar; 3822 3823 struct rtw89_btc btc; 3824 enum rtw89_ps_mode ps_mode; 3825 bool lps_enabled; 3826 3827 struct rtw89_wow_param wow; 3828 3829 /* napi structure */ 3830 struct net_device netdev; 3831 struct napi_struct napi; 3832 int napi_budget_countdown; 3833 3834 /* HCI related data, keep last */ 3835 u8 priv[] __aligned(sizeof(void *)); 3836 }; 3837 3838 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 3839 struct rtw89_core_tx_request *tx_req) 3840 { 3841 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 3842 } 3843 3844 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 3845 { 3846 rtwdev->hci.ops->reset(rtwdev); 3847 } 3848 3849 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 3850 { 3851 return rtwdev->hci.ops->start(rtwdev); 3852 } 3853 3854 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 3855 { 3856 rtwdev->hci.ops->stop(rtwdev); 3857 } 3858 3859 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 3860 { 3861 return rtwdev->hci.ops->deinit(rtwdev); 3862 } 3863 3864 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 3865 { 3866 rtwdev->hci.ops->pause(rtwdev, pause); 3867 } 3868 3869 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 3870 { 3871 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 3872 } 3873 3874 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 3875 { 3876 rtwdev->hci.ops->recalc_int_mit(rtwdev); 3877 } 3878 3879 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 3880 { 3881 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 3882 } 3883 3884 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 3885 { 3886 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 3887 } 3888 3889 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 3890 bool drop) 3891 { 3892 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3893 return; 3894 3895 if (rtwdev->hci.ops->flush_queues) 3896 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 3897 } 3898 3899 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 3900 { 3901 if (rtwdev->hci.ops->recovery_start) 3902 rtwdev->hci.ops->recovery_start(rtwdev); 3903 } 3904 3905 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 3906 { 3907 if (rtwdev->hci.ops->recovery_complete) 3908 rtwdev->hci.ops->recovery_complete(rtwdev); 3909 } 3910 3911 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 3912 { 3913 if (rtwdev->hci.ops->enable_intr) 3914 rtwdev->hci.ops->enable_intr(rtwdev); 3915 } 3916 3917 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 3918 { 3919 if (rtwdev->hci.ops->disable_intr) 3920 rtwdev->hci.ops->disable_intr(rtwdev); 3921 } 3922 3923 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 3924 { 3925 if (rtwdev->hci.ops->ctrl_txdma_ch) 3926 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 3927 } 3928 3929 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 3930 { 3931 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 3932 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 3933 } 3934 3935 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 3936 { 3937 if (rtwdev->hci.ops->ctrl_trxhci) 3938 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 3939 } 3940 3941 static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev) 3942 { 3943 int ret = 0; 3944 3945 if (rtwdev->hci.ops->poll_txdma_ch) 3946 ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev); 3947 return ret; 3948 } 3949 3950 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 3951 { 3952 if (rtwdev->hci.ops->clr_idx_all) 3953 rtwdev->hci.ops->clr_idx_all(rtwdev); 3954 } 3955 3956 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 3957 { 3958 int ret = 0; 3959 3960 if (rtwdev->hci.ops->rst_bdram) 3961 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 3962 return ret; 3963 } 3964 3965 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 3966 { 3967 if (rtwdev->hci.ops->clear) 3968 rtwdev->hci.ops->clear(rtwdev, pdev); 3969 } 3970 3971 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 3972 { 3973 return rtwdev->hci.ops->read8(rtwdev, addr); 3974 } 3975 3976 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 3977 { 3978 return rtwdev->hci.ops->read16(rtwdev, addr); 3979 } 3980 3981 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 3982 { 3983 return rtwdev->hci.ops->read32(rtwdev, addr); 3984 } 3985 3986 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 3987 { 3988 rtwdev->hci.ops->write8(rtwdev, addr, data); 3989 } 3990 3991 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 3992 { 3993 rtwdev->hci.ops->write16(rtwdev, addr, data); 3994 } 3995 3996 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 3997 { 3998 rtwdev->hci.ops->write32(rtwdev, addr, data); 3999 } 4000 4001 static inline void 4002 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 4003 { 4004 u8 val; 4005 4006 val = rtw89_read8(rtwdev, addr); 4007 rtw89_write8(rtwdev, addr, val | bit); 4008 } 4009 4010 static inline void 4011 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 4012 { 4013 u16 val; 4014 4015 val = rtw89_read16(rtwdev, addr); 4016 rtw89_write16(rtwdev, addr, val | bit); 4017 } 4018 4019 static inline void 4020 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 4021 { 4022 u32 val; 4023 4024 val = rtw89_read32(rtwdev, addr); 4025 rtw89_write32(rtwdev, addr, val | bit); 4026 } 4027 4028 static inline void 4029 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 4030 { 4031 u8 val; 4032 4033 val = rtw89_read8(rtwdev, addr); 4034 rtw89_write8(rtwdev, addr, val & ~bit); 4035 } 4036 4037 static inline void 4038 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 4039 { 4040 u16 val; 4041 4042 val = rtw89_read16(rtwdev, addr); 4043 rtw89_write16(rtwdev, addr, val & ~bit); 4044 } 4045 4046 static inline void 4047 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 4048 { 4049 u32 val; 4050 4051 val = rtw89_read32(rtwdev, addr); 4052 rtw89_write32(rtwdev, addr, val & ~bit); 4053 } 4054 4055 static inline u32 4056 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4057 { 4058 u32 shift = __ffs(mask); 4059 u32 orig; 4060 u32 ret; 4061 4062 orig = rtw89_read32(rtwdev, addr); 4063 ret = (orig & mask) >> shift; 4064 4065 return ret; 4066 } 4067 4068 static inline u16 4069 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4070 { 4071 u32 shift = __ffs(mask); 4072 u32 orig; 4073 u32 ret; 4074 4075 orig = rtw89_read16(rtwdev, addr); 4076 ret = (orig & mask) >> shift; 4077 4078 return ret; 4079 } 4080 4081 static inline u8 4082 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4083 { 4084 u32 shift = __ffs(mask); 4085 u32 orig; 4086 u32 ret; 4087 4088 orig = rtw89_read8(rtwdev, addr); 4089 ret = (orig & mask) >> shift; 4090 4091 return ret; 4092 } 4093 4094 static inline void 4095 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 4096 { 4097 u32 shift = __ffs(mask); 4098 u32 orig; 4099 u32 set; 4100 4101 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 4102 4103 orig = rtw89_read32(rtwdev, addr); 4104 set = (orig & ~mask) | ((data << shift) & mask); 4105 rtw89_write32(rtwdev, addr, set); 4106 } 4107 4108 static inline void 4109 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 4110 { 4111 u32 shift; 4112 u16 orig, set; 4113 4114 mask &= 0xffff; 4115 shift = __ffs(mask); 4116 4117 orig = rtw89_read16(rtwdev, addr); 4118 set = (orig & ~mask) | ((data << shift) & mask); 4119 rtw89_write16(rtwdev, addr, set); 4120 } 4121 4122 static inline void 4123 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 4124 { 4125 u32 shift; 4126 u8 orig, set; 4127 4128 mask &= 0xff; 4129 shift = __ffs(mask); 4130 4131 orig = rtw89_read8(rtwdev, addr); 4132 set = (orig & ~mask) | ((data << shift) & mask); 4133 rtw89_write8(rtwdev, addr, set); 4134 } 4135 4136 static inline u32 4137 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 4138 u32 addr, u32 mask) 4139 { 4140 u32 val; 4141 4142 mutex_lock(&rtwdev->rf_mutex); 4143 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 4144 mutex_unlock(&rtwdev->rf_mutex); 4145 4146 return val; 4147 } 4148 4149 static inline void 4150 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 4151 u32 addr, u32 mask, u32 data) 4152 { 4153 mutex_lock(&rtwdev->rf_mutex); 4154 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 4155 mutex_unlock(&rtwdev->rf_mutex); 4156 } 4157 4158 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 4159 { 4160 void *p = rtwtxq; 4161 4162 return container_of(p, struct ieee80211_txq, drv_priv); 4163 } 4164 4165 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 4166 struct ieee80211_txq *txq) 4167 { 4168 struct rtw89_txq *rtwtxq; 4169 4170 if (!txq) 4171 return; 4172 4173 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 4174 INIT_LIST_HEAD(&rtwtxq->list); 4175 } 4176 4177 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 4178 { 4179 void *p = rtwvif; 4180 4181 return container_of(p, struct ieee80211_vif, drv_priv); 4182 } 4183 4184 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 4185 { 4186 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 4187 } 4188 4189 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 4190 { 4191 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 4192 } 4193 4194 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 4195 { 4196 void *p = rtwsta; 4197 4198 return container_of(p, struct ieee80211_sta, drv_priv); 4199 } 4200 4201 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 4202 { 4203 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 4204 } 4205 4206 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 4207 { 4208 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 4209 } 4210 4211 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 4212 { 4213 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 4214 return RATE_INFO_BW_160; 4215 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 4216 return RATE_INFO_BW_80; 4217 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 4218 return RATE_INFO_BW_40; 4219 else 4220 return RATE_INFO_BW_20; 4221 } 4222 4223 static inline 4224 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 4225 { 4226 switch (hw_band) { 4227 default: 4228 case RTW89_BAND_2G: 4229 return NL80211_BAND_2GHZ; 4230 case RTW89_BAND_5G: 4231 return NL80211_BAND_5GHZ; 4232 case RTW89_BAND_6G: 4233 return NL80211_BAND_6GHZ; 4234 } 4235 } 4236 4237 static inline 4238 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 4239 { 4240 switch (nl_band) { 4241 default: 4242 case NL80211_BAND_2GHZ: 4243 return RTW89_BAND_2G; 4244 case NL80211_BAND_5GHZ: 4245 return RTW89_BAND_5G; 4246 case NL80211_BAND_6GHZ: 4247 return RTW89_BAND_6G; 4248 } 4249 } 4250 4251 static inline 4252 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 4253 { 4254 switch (width) { 4255 default: 4256 WARN(1, "Not support bandwidth %d\n", width); 4257 fallthrough; 4258 case NL80211_CHAN_WIDTH_20_NOHT: 4259 case NL80211_CHAN_WIDTH_20: 4260 return RTW89_CHANNEL_WIDTH_20; 4261 case NL80211_CHAN_WIDTH_40: 4262 return RTW89_CHANNEL_WIDTH_40; 4263 case NL80211_CHAN_WIDTH_80: 4264 return RTW89_CHANNEL_WIDTH_80; 4265 case NL80211_CHAN_WIDTH_160: 4266 return RTW89_CHANNEL_WIDTH_160; 4267 } 4268 } 4269 4270 static inline 4271 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 4272 struct rtw89_sta *rtwsta) 4273 { 4274 if (rtwsta) { 4275 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 4276 4277 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 4278 return &rtwsta->addr_cam; 4279 } 4280 return &rtwvif->addr_cam; 4281 } 4282 4283 static inline 4284 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 4285 struct rtw89_sta *rtwsta) 4286 { 4287 if (rtwsta) { 4288 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 4289 4290 if (sta->tdls) 4291 return &rtwsta->bssid_cam; 4292 } 4293 return &rtwvif->bssid_cam; 4294 } 4295 4296 static inline 4297 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 4298 struct rtw89_channel_help_params *p, 4299 const struct rtw89_chan *chan, 4300 enum rtw89_mac_idx mac_idx, 4301 enum rtw89_phy_idx phy_idx) 4302 { 4303 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 4304 mac_idx, phy_idx); 4305 } 4306 4307 static inline 4308 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 4309 struct rtw89_channel_help_params *p, 4310 const struct rtw89_chan *chan, 4311 enum rtw89_mac_idx mac_idx, 4312 enum rtw89_phy_idx phy_idx) 4313 { 4314 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 4315 mac_idx, phy_idx); 4316 } 4317 4318 static inline 4319 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 4320 enum rtw89_sub_entity_idx idx) 4321 { 4322 struct rtw89_hal *hal = &rtwdev->hal; 4323 4324 return &hal->sub[idx].chandef; 4325 } 4326 4327 static inline 4328 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 4329 enum rtw89_sub_entity_idx idx) 4330 { 4331 struct rtw89_hal *hal = &rtwdev->hal; 4332 4333 return &hal->sub[idx].chan; 4334 } 4335 4336 static inline 4337 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 4338 enum rtw89_sub_entity_idx idx) 4339 { 4340 struct rtw89_hal *hal = &rtwdev->hal; 4341 4342 return &hal->sub[idx].rcd; 4343 } 4344 4345 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 4346 { 4347 const struct rtw89_chip_info *chip = rtwdev->chip; 4348 4349 if (chip->ops->fem_setup) 4350 chip->ops->fem_setup(rtwdev); 4351 } 4352 4353 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 4354 { 4355 const struct rtw89_chip_info *chip = rtwdev->chip; 4356 4357 if (chip->ops->bb_sethw) 4358 chip->ops->bb_sethw(rtwdev); 4359 } 4360 4361 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 4362 { 4363 const struct rtw89_chip_info *chip = rtwdev->chip; 4364 4365 if (chip->ops->rfk_init) 4366 chip->ops->rfk_init(rtwdev); 4367 } 4368 4369 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 4370 { 4371 const struct rtw89_chip_info *chip = rtwdev->chip; 4372 4373 if (chip->ops->rfk_channel) 4374 chip->ops->rfk_channel(rtwdev); 4375 } 4376 4377 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 4378 enum rtw89_phy_idx phy_idx) 4379 { 4380 const struct rtw89_chip_info *chip = rtwdev->chip; 4381 4382 if (chip->ops->rfk_band_changed) 4383 chip->ops->rfk_band_changed(rtwdev, phy_idx); 4384 } 4385 4386 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 4387 { 4388 const struct rtw89_chip_info *chip = rtwdev->chip; 4389 4390 if (chip->ops->rfk_scan) 4391 chip->ops->rfk_scan(rtwdev, start); 4392 } 4393 4394 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 4395 { 4396 const struct rtw89_chip_info *chip = rtwdev->chip; 4397 4398 if (chip->ops->rfk_track) 4399 chip->ops->rfk_track(rtwdev); 4400 } 4401 4402 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 4403 { 4404 const struct rtw89_chip_info *chip = rtwdev->chip; 4405 4406 if (chip->ops->set_txpwr_ctrl) 4407 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 4408 } 4409 4410 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 4411 { 4412 const struct rtw89_chip_info *chip = rtwdev->chip; 4413 4414 if (chip->ops->power_trim) 4415 chip->ops->power_trim(rtwdev); 4416 } 4417 4418 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 4419 enum rtw89_phy_idx phy_idx) 4420 { 4421 const struct rtw89_chip_info *chip = rtwdev->chip; 4422 4423 if (chip->ops->init_txpwr_unit) 4424 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 4425 } 4426 4427 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 4428 enum rtw89_rf_path rf_path) 4429 { 4430 const struct rtw89_chip_info *chip = rtwdev->chip; 4431 4432 if (!chip->ops->get_thermal) 4433 return 0x10; 4434 4435 return chip->ops->get_thermal(rtwdev, rf_path); 4436 } 4437 4438 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 4439 struct rtw89_rx_phy_ppdu *phy_ppdu, 4440 struct ieee80211_rx_status *status) 4441 { 4442 const struct rtw89_chip_info *chip = rtwdev->chip; 4443 4444 if (chip->ops->query_ppdu) 4445 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 4446 } 4447 4448 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, 4449 bool bt_en) 4450 { 4451 const struct rtw89_chip_info *chip = rtwdev->chip; 4452 4453 if (chip->ops->bb_ctrl_btc_preagc) 4454 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en); 4455 } 4456 4457 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 4458 { 4459 const struct rtw89_chip_info *chip = rtwdev->chip; 4460 4461 if (chip->ops->cfg_txrx_path) 4462 chip->ops->cfg_txrx_path(rtwdev); 4463 } 4464 4465 static inline 4466 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 4467 struct ieee80211_vif *vif) 4468 { 4469 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4470 const struct rtw89_chip_info *chip = rtwdev->chip; 4471 4472 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 4473 return; 4474 4475 if (chip->ops->set_txpwr_ul_tb_offset) 4476 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 4477 } 4478 4479 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 4480 const struct rtw89_txpwr_table *tbl) 4481 { 4482 tbl->load(rtwdev, tbl); 4483 } 4484 4485 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 4486 { 4487 return rtwdev->regd->txpwr_regd[band]; 4488 } 4489 4490 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 4491 { 4492 const struct rtw89_chip_info *chip = rtwdev->chip; 4493 4494 if (chip->ops->ctrl_btg) 4495 chip->ops->ctrl_btg(rtwdev, btg); 4496 } 4497 4498 static inline 4499 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 4500 struct rtw89_tx_desc_info *desc_info, 4501 void *txdesc) 4502 { 4503 const struct rtw89_chip_info *chip = rtwdev->chip; 4504 4505 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 4506 } 4507 4508 static inline 4509 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 4510 struct rtw89_tx_desc_info *desc_info, 4511 void *txdesc) 4512 { 4513 const struct rtw89_chip_info *chip = rtwdev->chip; 4514 4515 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 4516 } 4517 4518 static inline 4519 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 4520 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4521 { 4522 const struct rtw89_chip_info *chip = rtwdev->chip; 4523 4524 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 4525 } 4526 4527 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 4528 { 4529 const struct rtw89_chip_info *chip = rtwdev->chip; 4530 4531 chip->ops->cfg_ctrl_path(rtwdev, wl); 4532 } 4533 4534 static inline 4535 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 4536 u32 *tx_en, enum rtw89_sch_tx_sel sel) 4537 { 4538 const struct rtw89_chip_info *chip = rtwdev->chip; 4539 4540 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 4541 } 4542 4543 static inline 4544 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 4545 { 4546 const struct rtw89_chip_info *chip = rtwdev->chip; 4547 4548 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 4549 } 4550 4551 static inline 4552 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 4553 struct rtw89_vif *rtwvif, 4554 struct rtw89_sta *rtwsta) 4555 { 4556 const struct rtw89_chip_info *chip = rtwdev->chip; 4557 4558 if (!chip->ops->h2c_dctl_sec_cam) 4559 return 0; 4560 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 4561 } 4562 4563 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 4564 { 4565 __le16 fc = hdr->frame_control; 4566 4567 if (ieee80211_has_tods(fc)) 4568 return hdr->addr1; 4569 else if (ieee80211_has_fromds(fc)) 4570 return hdr->addr2; 4571 else 4572 return hdr->addr3; 4573 } 4574 4575 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 4576 { 4577 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 4578 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 4579 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 4580 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 4581 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 4582 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 4583 return true; 4584 return false; 4585 } 4586 4587 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 4588 enum rtw89_fw_type type) 4589 { 4590 struct rtw89_fw_info *fw_info = &rtwdev->fw; 4591 4592 if (type == RTW89_FW_WOWLAN) 4593 return &fw_info->wowlan; 4594 return &fw_info->normal; 4595 } 4596 4597 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 4598 unsigned int length) 4599 { 4600 struct sk_buff *skb; 4601 4602 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 4603 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 4604 if (!skb) 4605 return NULL; 4606 4607 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 4608 return skb; 4609 } 4610 4611 return dev_alloc_skb(length); 4612 } 4613 4614 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4615 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 4616 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 4617 struct sk_buff *skb, bool fwdl); 4618 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 4619 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 4620 struct rtw89_tx_desc_info *desc_info, 4621 void *txdesc); 4622 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 4623 struct rtw89_tx_desc_info *desc_info, 4624 void *txdesc); 4625 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 4626 struct rtw89_tx_desc_info *desc_info, 4627 void *txdesc); 4628 void rtw89_core_rx(struct rtw89_dev *rtwdev, 4629 struct rtw89_rx_desc_info *desc_info, 4630 struct sk_buff *skb); 4631 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 4632 struct rtw89_rx_desc_info *desc_info, 4633 u8 *data, u32 data_offset); 4634 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 4635 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 4636 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 4637 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 4638 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 4639 struct ieee80211_vif *vif, 4640 struct ieee80211_sta *sta); 4641 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 4642 struct ieee80211_vif *vif, 4643 struct ieee80211_sta *sta); 4644 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 4645 struct ieee80211_vif *vif, 4646 struct ieee80211_sta *sta); 4647 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 4648 struct ieee80211_vif *vif, 4649 struct ieee80211_sta *sta); 4650 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 4651 struct ieee80211_vif *vif, 4652 struct ieee80211_sta *sta); 4653 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 4654 struct ieee80211_sta *sta, 4655 struct cfg80211_tid_config *tid_config); 4656 int rtw89_core_init(struct rtw89_dev *rtwdev); 4657 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 4658 int rtw89_core_register(struct rtw89_dev *rtwdev); 4659 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 4660 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 4661 u32 bus_data_size, 4662 const struct rtw89_chip_info *chip); 4663 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 4664 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 4665 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 4666 void rtw89_set_channel(struct rtw89_dev *rtwdev); 4667 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 4668 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 4669 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 4670 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 4671 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 4672 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 4673 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 4674 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 4675 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 4676 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 4677 int rtw89_regd_init(struct rtw89_dev *rtwdev, 4678 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 4679 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 4680 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 4681 struct rtw89_traffic_stats *stats); 4682 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 4683 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 4684 const struct rtw89_completion_data *data); 4685 int rtw89_core_start(struct rtw89_dev *rtwdev); 4686 void rtw89_core_stop(struct rtw89_dev *rtwdev); 4687 void rtw89_core_update_beacon_work(struct work_struct *work); 4688 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4689 const u8 *mac_addr, bool hw_scan); 4690 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 4691 struct ieee80211_vif *vif, bool hw_scan); 4692 4693 #endif 4694