1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 18 extern const struct ieee80211_ops rtw89_ops; 19 20 #define MASKBYTE0 0xff 21 #define MASKBYTE1 0xff00 22 #define MASKBYTE2 0xff0000 23 #define MASKBYTE3 0xff000000 24 #define MASKBYTE4 0xff00000000ULL 25 #define MASKHWORD 0xffff0000 26 #define MASKLWORD 0x0000ffff 27 #define MASKDWORD 0xffffffff 28 #define RFREG_MASK 0xfffff 29 #define INV_RF_DATA 0xffffffff 30 31 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 32 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 33 #define CFO_TRACK_MAX_USER 64 34 #define MAX_RSSI 110 35 #define RSSI_FACTOR 1 36 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 37 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 38 #define RTW89_RADIOTAP_ROOM ALIGN(sizeof(struct ieee80211_radiotap_he), 64) 39 40 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 41 #define RTW89_HTC_VARIANT_HE 3 42 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 43 #define RTW89_HTC_VARIANT_HE_CID_OM 1 44 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 45 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 46 47 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 48 enum htc_om_channel_width { 49 HTC_OM_CHANNEL_WIDTH_20 = 0, 50 HTC_OM_CHANNEL_WIDTH_40 = 1, 51 HTC_OM_CHANNEL_WIDTH_80 = 2, 52 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 53 }; 54 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 55 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 56 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 57 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 58 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 59 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 60 61 #define RTW89_TF_PAD GENMASK(11, 0) 62 #define RTW89_TF_BASIC_USER_INFO_SZ 6 63 64 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 65 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 66 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 67 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 68 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 69 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 70 71 enum rtw89_subband { 72 RTW89_CH_2G = 0, 73 RTW89_CH_5G_BAND_1 = 1, 74 /* RTW89_CH_5G_BAND_2 = 2, unused */ 75 RTW89_CH_5G_BAND_3 = 3, 76 RTW89_CH_5G_BAND_4 = 4, 77 78 RTW89_CH_6G_BAND_IDX0, /* Low */ 79 RTW89_CH_6G_BAND_IDX1, /* Low */ 80 RTW89_CH_6G_BAND_IDX2, /* Mid */ 81 RTW89_CH_6G_BAND_IDX3, /* Mid */ 82 RTW89_CH_6G_BAND_IDX4, /* High */ 83 RTW89_CH_6G_BAND_IDX5, /* High */ 84 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 85 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 86 87 RTW89_SUBBAND_NR, 88 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 89 }; 90 91 enum rtw89_gain_offset { 92 RTW89_GAIN_OFFSET_2G_CCK, 93 RTW89_GAIN_OFFSET_2G_OFDM, 94 RTW89_GAIN_OFFSET_5G_LOW, 95 RTW89_GAIN_OFFSET_5G_MID, 96 RTW89_GAIN_OFFSET_5G_HIGH, 97 98 RTW89_GAIN_OFFSET_NR, 99 }; 100 101 enum rtw89_hci_type { 102 RTW89_HCI_TYPE_PCIE, 103 RTW89_HCI_TYPE_USB, 104 RTW89_HCI_TYPE_SDIO, 105 }; 106 107 enum rtw89_core_chip_id { 108 RTL8852A, 109 RTL8852B, 110 RTL8852C, 111 RTL8851B, 112 RTL8922A, 113 }; 114 115 enum rtw89_chip_gen { 116 RTW89_CHIP_AX, 117 RTW89_CHIP_BE, 118 119 RTW89_CHIP_GEN_NUM, 120 }; 121 122 enum rtw89_cv { 123 CHIP_CAV, 124 CHIP_CBV, 125 CHIP_CCV, 126 CHIP_CDV, 127 CHIP_CEV, 128 CHIP_CFV, 129 CHIP_CV_MAX, 130 CHIP_CV_INVALID = CHIP_CV_MAX, 131 }; 132 133 enum rtw89_bacam_ver { 134 RTW89_BACAM_V0, 135 RTW89_BACAM_V1, 136 137 RTW89_BACAM_V0_EXT = 99, 138 }; 139 140 enum rtw89_core_tx_type { 141 RTW89_CORE_TX_TYPE_DATA, 142 RTW89_CORE_TX_TYPE_MGMT, 143 RTW89_CORE_TX_TYPE_FWCMD, 144 }; 145 146 enum rtw89_core_rx_type { 147 RTW89_CORE_RX_TYPE_WIFI = 0, 148 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 149 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 150 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 151 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 152 RTW89_CORE_RX_TYPE_SS2FW = 5, 153 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 154 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 155 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 156 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 157 RTW89_CORE_RX_TYPE_C2H = 10, 158 RTW89_CORE_RX_TYPE_CSI = 11, 159 RTW89_CORE_RX_TYPE_CQI = 12, 160 RTW89_CORE_RX_TYPE_H2C = 13, 161 RTW89_CORE_RX_TYPE_FWDL = 14, 162 }; 163 164 enum rtw89_txq_flags { 165 RTW89_TXQ_F_AMPDU = 0, 166 RTW89_TXQ_F_BLOCK_BA = 1, 167 RTW89_TXQ_F_FORBID_BA = 2, 168 }; 169 170 enum rtw89_net_type { 171 RTW89_NET_TYPE_NO_LINK = 0, 172 RTW89_NET_TYPE_AD_HOC = 1, 173 RTW89_NET_TYPE_INFRA = 2, 174 RTW89_NET_TYPE_AP_MODE = 3, 175 }; 176 177 enum rtw89_wifi_role { 178 RTW89_WIFI_ROLE_NONE, 179 RTW89_WIFI_ROLE_STATION, 180 RTW89_WIFI_ROLE_AP, 181 RTW89_WIFI_ROLE_AP_VLAN, 182 RTW89_WIFI_ROLE_ADHOC, 183 RTW89_WIFI_ROLE_ADHOC_MASTER, 184 RTW89_WIFI_ROLE_MESH_POINT, 185 RTW89_WIFI_ROLE_MONITOR, 186 RTW89_WIFI_ROLE_P2P_DEVICE, 187 RTW89_WIFI_ROLE_P2P_CLIENT, 188 RTW89_WIFI_ROLE_P2P_GO, 189 RTW89_WIFI_ROLE_NAN, 190 RTW89_WIFI_ROLE_MLME_MAX 191 }; 192 193 enum rtw89_upd_mode { 194 RTW89_ROLE_CREATE, 195 RTW89_ROLE_REMOVE, 196 RTW89_ROLE_TYPE_CHANGE, 197 RTW89_ROLE_INFO_CHANGE, 198 RTW89_ROLE_CON_DISCONN, 199 RTW89_ROLE_BAND_SW, 200 RTW89_ROLE_FW_RESTORE, 201 }; 202 203 enum rtw89_self_role { 204 RTW89_SELF_ROLE_CLIENT, 205 RTW89_SELF_ROLE_AP, 206 RTW89_SELF_ROLE_AP_CLIENT 207 }; 208 209 enum rtw89_msk_sO_el { 210 RTW89_NO_MSK, 211 RTW89_SMA, 212 RTW89_TMA, 213 RTW89_BSSID 214 }; 215 216 enum rtw89_sch_tx_sel { 217 RTW89_SCH_TX_SEL_ALL, 218 RTW89_SCH_TX_SEL_HIQ, 219 RTW89_SCH_TX_SEL_MG0, 220 RTW89_SCH_TX_SEL_MACID, 221 }; 222 223 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 224 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 225 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 226 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 227 */ 228 enum rtw89_add_cam_sec_mode { 229 RTW89_ADDR_CAM_SEC_NONE = 0, 230 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 231 RTW89_ADDR_CAM_SEC_NORMAL = 2, 232 RTW89_ADDR_CAM_SEC_4GROUP = 3, 233 }; 234 235 enum rtw89_sec_key_type { 236 RTW89_SEC_KEY_TYPE_NONE = 0, 237 RTW89_SEC_KEY_TYPE_WEP40 = 1, 238 RTW89_SEC_KEY_TYPE_WEP104 = 2, 239 RTW89_SEC_KEY_TYPE_TKIP = 3, 240 RTW89_SEC_KEY_TYPE_WAPI = 4, 241 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 242 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 243 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 244 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 245 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 246 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 247 }; 248 249 enum rtw89_port { 250 RTW89_PORT_0 = 0, 251 RTW89_PORT_1 = 1, 252 RTW89_PORT_2 = 2, 253 RTW89_PORT_3 = 3, 254 RTW89_PORT_4 = 4, 255 RTW89_PORT_NUM 256 }; 257 258 enum rtw89_band { 259 RTW89_BAND_2G = 0, 260 RTW89_BAND_5G = 1, 261 RTW89_BAND_6G = 2, 262 RTW89_BAND_NUM, 263 }; 264 265 enum rtw89_hw_rate { 266 RTW89_HW_RATE_CCK1 = 0x0, 267 RTW89_HW_RATE_CCK2 = 0x1, 268 RTW89_HW_RATE_CCK5_5 = 0x2, 269 RTW89_HW_RATE_CCK11 = 0x3, 270 RTW89_HW_RATE_OFDM6 = 0x4, 271 RTW89_HW_RATE_OFDM9 = 0x5, 272 RTW89_HW_RATE_OFDM12 = 0x6, 273 RTW89_HW_RATE_OFDM18 = 0x7, 274 RTW89_HW_RATE_OFDM24 = 0x8, 275 RTW89_HW_RATE_OFDM36 = 0x9, 276 RTW89_HW_RATE_OFDM48 = 0xA, 277 RTW89_HW_RATE_OFDM54 = 0xB, 278 RTW89_HW_RATE_MCS0 = 0x80, 279 RTW89_HW_RATE_MCS1 = 0x81, 280 RTW89_HW_RATE_MCS2 = 0x82, 281 RTW89_HW_RATE_MCS3 = 0x83, 282 RTW89_HW_RATE_MCS4 = 0x84, 283 RTW89_HW_RATE_MCS5 = 0x85, 284 RTW89_HW_RATE_MCS6 = 0x86, 285 RTW89_HW_RATE_MCS7 = 0x87, 286 RTW89_HW_RATE_MCS8 = 0x88, 287 RTW89_HW_RATE_MCS9 = 0x89, 288 RTW89_HW_RATE_MCS10 = 0x8A, 289 RTW89_HW_RATE_MCS11 = 0x8B, 290 RTW89_HW_RATE_MCS12 = 0x8C, 291 RTW89_HW_RATE_MCS13 = 0x8D, 292 RTW89_HW_RATE_MCS14 = 0x8E, 293 RTW89_HW_RATE_MCS15 = 0x8F, 294 RTW89_HW_RATE_MCS16 = 0x90, 295 RTW89_HW_RATE_MCS17 = 0x91, 296 RTW89_HW_RATE_MCS18 = 0x92, 297 RTW89_HW_RATE_MCS19 = 0x93, 298 RTW89_HW_RATE_MCS20 = 0x94, 299 RTW89_HW_RATE_MCS21 = 0x95, 300 RTW89_HW_RATE_MCS22 = 0x96, 301 RTW89_HW_RATE_MCS23 = 0x97, 302 RTW89_HW_RATE_MCS24 = 0x98, 303 RTW89_HW_RATE_MCS25 = 0x99, 304 RTW89_HW_RATE_MCS26 = 0x9A, 305 RTW89_HW_RATE_MCS27 = 0x9B, 306 RTW89_HW_RATE_MCS28 = 0x9C, 307 RTW89_HW_RATE_MCS29 = 0x9D, 308 RTW89_HW_RATE_MCS30 = 0x9E, 309 RTW89_HW_RATE_MCS31 = 0x9F, 310 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 311 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 312 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 313 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 314 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 315 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 316 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 317 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 318 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 319 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 320 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 321 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 322 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 323 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 324 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 325 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 326 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 327 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 328 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 329 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 330 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 331 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 332 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 333 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 334 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 335 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 336 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 337 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 338 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 339 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 340 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 341 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 342 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 343 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 344 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 345 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 346 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 347 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 348 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 349 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 350 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 351 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 352 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 353 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 354 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 355 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 356 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 357 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 358 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 359 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 360 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 361 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 362 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 363 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 364 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 365 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 366 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 367 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 368 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 369 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 370 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 371 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 372 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 373 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 374 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 375 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 376 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 377 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 378 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 379 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 380 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 381 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 382 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 383 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 384 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 385 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 386 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 387 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 388 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 389 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 390 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 391 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 392 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 393 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 394 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 395 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 396 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 397 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 398 399 RTW89_HW_RATE_V1_MCS0 = 0x100, 400 RTW89_HW_RATE_V1_MCS1 = 0x101, 401 RTW89_HW_RATE_V1_MCS2 = 0x102, 402 RTW89_HW_RATE_V1_MCS3 = 0x103, 403 RTW89_HW_RATE_V1_MCS4 = 0x104, 404 RTW89_HW_RATE_V1_MCS5 = 0x105, 405 RTW89_HW_RATE_V1_MCS6 = 0x106, 406 RTW89_HW_RATE_V1_MCS7 = 0x107, 407 RTW89_HW_RATE_V1_MCS8 = 0x108, 408 RTW89_HW_RATE_V1_MCS9 = 0x109, 409 RTW89_HW_RATE_V1_MCS10 = 0x10A, 410 RTW89_HW_RATE_V1_MCS11 = 0x10B, 411 RTW89_HW_RATE_V1_MCS12 = 0x10C, 412 RTW89_HW_RATE_V1_MCS13 = 0x10D, 413 RTW89_HW_RATE_V1_MCS14 = 0x10E, 414 RTW89_HW_RATE_V1_MCS15 = 0x10F, 415 RTW89_HW_RATE_V1_MCS16 = 0x110, 416 RTW89_HW_RATE_V1_MCS17 = 0x111, 417 RTW89_HW_RATE_V1_MCS18 = 0x112, 418 RTW89_HW_RATE_V1_MCS19 = 0x113, 419 RTW89_HW_RATE_V1_MCS20 = 0x114, 420 RTW89_HW_RATE_V1_MCS21 = 0x115, 421 RTW89_HW_RATE_V1_MCS22 = 0x116, 422 RTW89_HW_RATE_V1_MCS23 = 0x117, 423 RTW89_HW_RATE_V1_MCS24 = 0x118, 424 RTW89_HW_RATE_V1_MCS25 = 0x119, 425 RTW89_HW_RATE_V1_MCS26 = 0x11A, 426 RTW89_HW_RATE_V1_MCS27 = 0x11B, 427 RTW89_HW_RATE_V1_MCS28 = 0x11C, 428 RTW89_HW_RATE_V1_MCS29 = 0x11D, 429 RTW89_HW_RATE_V1_MCS30 = 0x11E, 430 RTW89_HW_RATE_V1_MCS31 = 0x11F, 431 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 432 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 433 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 434 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 435 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 436 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 437 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 438 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 439 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 440 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 441 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 442 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 443 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 444 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 445 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 446 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 447 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 448 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 449 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 450 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 451 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 452 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 453 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 454 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 455 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 456 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 457 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 458 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 459 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 460 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 461 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 462 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 463 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 464 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 465 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 466 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 467 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 468 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 469 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 470 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 471 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 472 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 473 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 474 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 475 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 476 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 477 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 478 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 479 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 480 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 481 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 482 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 483 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 484 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 485 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 486 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 487 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 488 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 489 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 490 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 491 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 492 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 493 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 494 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 495 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 496 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 497 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 498 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 499 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 500 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 501 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 502 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 503 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 504 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 505 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 506 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 507 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 508 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 509 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 510 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 511 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 512 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 513 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 514 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 515 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 516 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 517 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 518 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 519 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 520 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 521 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 522 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 523 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 524 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 525 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 526 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 527 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 528 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 529 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 530 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 531 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 532 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 533 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 534 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 535 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 536 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 537 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 538 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 539 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 540 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 541 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 542 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 543 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 544 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 545 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 546 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 547 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 548 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 549 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 550 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 551 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 552 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 553 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 554 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 555 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 556 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 557 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 558 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 559 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 560 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 561 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 562 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 563 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 564 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 565 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 566 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 567 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 568 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 569 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 570 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 571 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 572 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 573 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 574 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 575 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 576 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 577 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 578 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 579 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 580 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 581 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 582 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 583 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 584 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 585 586 RTW89_HW_RATE_NR, 587 RTW89_HW_RATE_INVAL, 588 589 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 590 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 591 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 592 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 593 }; 594 595 /* 2G channels, 596 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 597 */ 598 #define RTW89_2G_CH_NUM 14 599 600 /* 5G channels, 601 * 36, 38, 40, 42, 44, 46, 48, 50, 602 * 52, 54, 56, 58, 60, 62, 64, 603 * 100, 102, 104, 106, 108, 110, 112, 114, 604 * 116, 118, 120, 122, 124, 126, 128, 130, 605 * 132, 134, 136, 138, 140, 142, 144, 606 * 149, 151, 153, 155, 157, 159, 161, 163, 607 * 165, 167, 169, 171, 173, 175, 177 608 */ 609 #define RTW89_5G_CH_NUM 53 610 611 /* 6G channels, 612 * 1, 3, 5, 7, 9, 11, 13, 15, 613 * 17, 19, 21, 23, 25, 27, 29, 33, 614 * 35, 37, 39, 41, 43, 45, 47, 49, 615 * 51, 53, 55, 57, 59, 61, 65, 67, 616 * 69, 71, 73, 75, 77, 79, 81, 83, 617 * 85, 87, 89, 91, 93, 97, 99, 101, 618 * 103, 105, 107, 109, 111, 113, 115, 117, 619 * 119, 121, 123, 125, 129, 131, 133, 135, 620 * 137, 139, 141, 143, 145, 147, 149, 151, 621 * 153, 155, 157, 161, 163, 165, 167, 169, 622 * 171, 173, 175, 177, 179, 181, 183, 185, 623 * 187, 189, 193, 195, 197, 199, 201, 203, 624 * 205, 207, 209, 211, 213, 215, 217, 219, 625 * 221, 225, 227, 229, 231, 233, 235, 237, 626 * 239, 241, 243, 245, 247, 249, 251, 253, 627 */ 628 #define RTW89_6G_CH_NUM 120 629 630 enum rtw89_rate_section { 631 RTW89_RS_CCK, 632 RTW89_RS_OFDM, 633 RTW89_RS_MCS, /* for HT/VHT/HE */ 634 RTW89_RS_HEDCM, 635 RTW89_RS_OFFSET, 636 RTW89_RS_NUM, 637 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 638 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 639 }; 640 641 enum rtw89_rate_num { 642 RTW89_RATE_CCK_NUM = 4, 643 RTW89_RATE_OFDM_NUM = 8, 644 RTW89_RATE_MCS_NUM = 12, 645 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 646 RTW89_RATE_OFFSET_NUM = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */ 647 }; 648 649 enum rtw89_nss { 650 RTW89_NSS_1 = 0, 651 RTW89_NSS_2 = 1, 652 /* HE DCM only support 1ss and 2ss */ 653 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 654 RTW89_NSS_3 = 2, 655 RTW89_NSS_4 = 3, 656 RTW89_NSS_NUM, 657 }; 658 659 enum rtw89_ntx { 660 RTW89_1TX = 0, 661 RTW89_2TX = 1, 662 RTW89_NTX_NUM, 663 }; 664 665 enum rtw89_beamforming_type { 666 RTW89_NONBF = 0, 667 RTW89_BF = 1, 668 RTW89_BF_NUM, 669 }; 670 671 enum rtw89_regulation_type { 672 RTW89_WW = 0, 673 RTW89_ETSI = 1, 674 RTW89_FCC = 2, 675 RTW89_MKK = 3, 676 RTW89_NA = 4, 677 RTW89_IC = 5, 678 RTW89_KCC = 6, 679 RTW89_ACMA = 7, 680 RTW89_NCC = 8, 681 RTW89_MEXICO = 9, 682 RTW89_CHILE = 10, 683 RTW89_UKRAINE = 11, 684 RTW89_CN = 12, 685 RTW89_QATAR = 13, 686 RTW89_UK = 14, 687 RTW89_REGD_NUM, 688 }; 689 690 enum rtw89_reg_6ghz_power { 691 RTW89_REG_6GHZ_POWER_VLP = 0, 692 RTW89_REG_6GHZ_POWER_LPI = 1, 693 RTW89_REG_6GHZ_POWER_STD = 2, 694 695 NUM_OF_RTW89_REG_6GHZ_POWER, 696 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 697 }; 698 699 enum rtw89_fw_pkt_ofld_type { 700 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 701 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 702 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 703 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 704 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 705 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 706 RTW89_PKT_OFLD_TYPE_NDP = 6, 707 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 708 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 709 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 710 RTW89_PKT_OFLD_TYPE_NUM, 711 }; 712 713 struct rtw89_txpwr_byrate { 714 s8 cck[RTW89_RATE_CCK_NUM]; 715 s8 ofdm[RTW89_RATE_OFDM_NUM]; 716 s8 mcs[RTW89_NSS_NUM][RTW89_RATE_MCS_NUM]; 717 s8 hedcm[RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 718 s8 offset[RTW89_RATE_OFFSET_NUM]; 719 }; 720 721 enum rtw89_bandwidth_section_num { 722 RTW89_BW20_SEC_NUM = 8, 723 RTW89_BW40_SEC_NUM = 4, 724 RTW89_BW80_SEC_NUM = 2, 725 }; 726 727 #define RTW89_TXPWR_LMT_PAGE_SIZE 40 728 729 struct rtw89_txpwr_limit { 730 s8 cck_20m[RTW89_BF_NUM]; 731 s8 cck_40m[RTW89_BF_NUM]; 732 s8 ofdm[RTW89_BF_NUM]; 733 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM]; 734 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM]; 735 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM]; 736 s8 mcs_160m[RTW89_BF_NUM]; 737 s8 mcs_40m_0p5[RTW89_BF_NUM]; 738 s8 mcs_40m_2p5[RTW89_BF_NUM]; 739 }; 740 741 #define RTW89_RU_SEC_NUM 8 742 743 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE 24 744 745 struct rtw89_txpwr_limit_ru { 746 s8 ru26[RTW89_RU_SEC_NUM]; 747 s8 ru52[RTW89_RU_SEC_NUM]; 748 s8 ru106[RTW89_RU_SEC_NUM]; 749 }; 750 751 struct rtw89_rate_desc { 752 enum rtw89_nss nss; 753 enum rtw89_rate_section rs; 754 u8 idx; 755 }; 756 757 #define PHY_STS_HDR_LEN 8 758 #define RF_PATH_MAX 4 759 #define RTW89_MAX_PPDU_CNT 8 760 struct rtw89_rx_phy_ppdu { 761 void *buf; 762 u32 len; 763 u8 rssi_avg; 764 u8 rssi[RF_PATH_MAX]; 765 u8 mac_id; 766 u8 chan_idx; 767 u8 ie; 768 u16 rate; 769 struct { 770 bool has; 771 u8 avg_snr; 772 u8 evm_max; 773 u8 evm_min; 774 } ofdm; 775 bool to_self; 776 bool valid; 777 }; 778 779 enum rtw89_mac_idx { 780 RTW89_MAC_0 = 0, 781 RTW89_MAC_1 = 1, 782 }; 783 784 enum rtw89_phy_idx { 785 RTW89_PHY_0 = 0, 786 RTW89_PHY_1 = 1, 787 RTW89_PHY_MAX 788 }; 789 790 enum rtw89_sub_entity_idx { 791 RTW89_SUB_ENTITY_0 = 0, 792 793 NUM_OF_RTW89_SUB_ENTITY, 794 RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY, 795 }; 796 797 enum rtw89_rf_path { 798 RF_PATH_A = 0, 799 RF_PATH_B = 1, 800 RF_PATH_C = 2, 801 RF_PATH_D = 3, 802 RF_PATH_AB, 803 RF_PATH_AC, 804 RF_PATH_AD, 805 RF_PATH_BC, 806 RF_PATH_BD, 807 RF_PATH_CD, 808 RF_PATH_ABC, 809 RF_PATH_ABD, 810 RF_PATH_ACD, 811 RF_PATH_BCD, 812 RF_PATH_ABCD, 813 }; 814 815 enum rtw89_rf_path_bit { 816 RF_A = BIT(0), 817 RF_B = BIT(1), 818 RF_C = BIT(2), 819 RF_D = BIT(3), 820 821 RF_AB = (RF_A | RF_B), 822 RF_AC = (RF_A | RF_C), 823 RF_AD = (RF_A | RF_D), 824 RF_BC = (RF_B | RF_C), 825 RF_BD = (RF_B | RF_D), 826 RF_CD = (RF_C | RF_D), 827 828 RF_ABC = (RF_A | RF_B | RF_C), 829 RF_ABD = (RF_A | RF_B | RF_D), 830 RF_ACD = (RF_A | RF_C | RF_D), 831 RF_BCD = (RF_B | RF_C | RF_D), 832 833 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 834 }; 835 836 enum rtw89_bandwidth { 837 RTW89_CHANNEL_WIDTH_20 = 0, 838 RTW89_CHANNEL_WIDTH_40 = 1, 839 RTW89_CHANNEL_WIDTH_80 = 2, 840 RTW89_CHANNEL_WIDTH_160 = 3, 841 RTW89_CHANNEL_WIDTH_80_80 = 4, 842 RTW89_CHANNEL_WIDTH_5 = 5, 843 RTW89_CHANNEL_WIDTH_10 = 6, 844 }; 845 846 enum rtw89_ps_mode { 847 RTW89_PS_MODE_NONE = 0, 848 RTW89_PS_MODE_RFOFF = 1, 849 RTW89_PS_MODE_CLK_GATED = 2, 850 RTW89_PS_MODE_PWR_GATED = 3, 851 }; 852 853 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 854 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 855 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 856 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 857 858 enum rtw89_ru_bandwidth { 859 RTW89_RU26 = 0, 860 RTW89_RU52 = 1, 861 RTW89_RU106 = 2, 862 RTW89_RU_NUM, 863 }; 864 865 enum rtw89_sc_offset { 866 RTW89_SC_DONT_CARE = 0, 867 RTW89_SC_20_UPPER = 1, 868 RTW89_SC_20_LOWER = 2, 869 RTW89_SC_20_UPMOST = 3, 870 RTW89_SC_20_LOWEST = 4, 871 RTW89_SC_20_UP2X = 5, 872 RTW89_SC_20_LOW2X = 6, 873 RTW89_SC_20_UP3X = 7, 874 RTW89_SC_20_LOW3X = 8, 875 RTW89_SC_40_UPPER = 9, 876 RTW89_SC_40_LOWER = 10, 877 }; 878 879 enum rtw89_wow_flags { 880 RTW89_WOW_FLAG_EN_MAGIC_PKT, 881 RTW89_WOW_FLAG_EN_REKEY_PKT, 882 RTW89_WOW_FLAG_EN_DISCONNECT, 883 RTW89_WOW_FLAG_NUM, 884 }; 885 886 struct rtw89_chan { 887 u8 channel; 888 u8 primary_channel; 889 enum rtw89_band band_type; 890 enum rtw89_bandwidth band_width; 891 892 /* The follow-up are derived from the above. We must ensure that it 893 * is assigned correctly in rtw89_chan_create() if new one is added. 894 */ 895 u32 freq; 896 enum rtw89_subband subband_type; 897 enum rtw89_sc_offset pri_ch_idx; 898 }; 899 900 struct rtw89_chan_rcd { 901 u8 prev_primary_channel; 902 enum rtw89_band prev_band_type; 903 }; 904 905 struct rtw89_channel_help_params { 906 u32 tx_en; 907 }; 908 909 struct rtw89_port_reg { 910 u32 port_cfg; 911 u32 tbtt_prohib; 912 u32 bcn_area; 913 u32 bcn_early; 914 u32 tbtt_early; 915 u32 tbtt_agg; 916 u32 bcn_space; 917 u32 bcn_forcetx; 918 u32 bcn_err_cnt; 919 u32 bcn_err_flag; 920 u32 dtim_ctrl; 921 u32 tbtt_shift; 922 u32 bcn_cnt_tmr; 923 u32 tsftr_l; 924 u32 tsftr_h; 925 }; 926 927 struct rtw89_txwd_body { 928 __le32 dword0; 929 __le32 dword1; 930 __le32 dword2; 931 __le32 dword3; 932 __le32 dword4; 933 __le32 dword5; 934 } __packed; 935 936 struct rtw89_txwd_body_v1 { 937 __le32 dword0; 938 __le32 dword1; 939 __le32 dword2; 940 __le32 dword3; 941 __le32 dword4; 942 __le32 dword5; 943 __le32 dword6; 944 __le32 dword7; 945 } __packed; 946 947 struct rtw89_txwd_info { 948 __le32 dword0; 949 __le32 dword1; 950 __le32 dword2; 951 __le32 dword3; 952 __le32 dword4; 953 __le32 dword5; 954 } __packed; 955 956 struct rtw89_rx_desc_info { 957 u16 pkt_size; 958 u8 pkt_type; 959 u8 drv_info_size; 960 u8 shift; 961 u8 wl_hd_iv_len; 962 bool long_rxdesc; 963 bool bb_sel; 964 bool mac_info_valid; 965 u16 data_rate; 966 u8 gi_ltf; 967 u8 bw; 968 u32 free_run_cnt; 969 u8 user_id; 970 bool sr_en; 971 u8 ppdu_cnt; 972 u8 ppdu_type; 973 bool icv_err; 974 bool crc32_err; 975 bool hw_dec; 976 bool sw_dec; 977 bool addr1_match; 978 u8 frag; 979 u16 seq; 980 u8 frame_type; 981 u8 rx_pl_id; 982 bool addr_cam_valid; 983 u8 addr_cam_id; 984 u8 sec_cam_id; 985 u8 mac_id; 986 u16 offset; 987 u16 rxd_len; 988 bool ready; 989 }; 990 991 struct rtw89_rxdesc_short { 992 __le32 dword0; 993 __le32 dword1; 994 __le32 dword2; 995 __le32 dword3; 996 } __packed; 997 998 struct rtw89_rxdesc_long { 999 __le32 dword0; 1000 __le32 dword1; 1001 __le32 dword2; 1002 __le32 dword3; 1003 __le32 dword4; 1004 __le32 dword5; 1005 __le32 dword6; 1006 __le32 dword7; 1007 } __packed; 1008 1009 struct rtw89_tx_desc_info { 1010 u16 pkt_size; 1011 u8 wp_offset; 1012 u8 mac_id; 1013 u8 qsel; 1014 u8 ch_dma; 1015 u8 hdr_llc_len; 1016 bool is_bmc; 1017 bool en_wd_info; 1018 bool wd_page; 1019 bool use_rate; 1020 bool dis_data_fb; 1021 bool tid_indicate; 1022 bool agg_en; 1023 bool bk; 1024 u8 ampdu_density; 1025 u8 ampdu_num; 1026 bool sec_en; 1027 u8 addr_info_nr; 1028 u8 sec_keyid; 1029 u8 sec_type; 1030 u8 sec_cam_idx; 1031 u8 sec_seq[6]; 1032 u16 data_rate; 1033 u16 data_retry_lowest_rate; 1034 bool fw_dl; 1035 u16 seq; 1036 bool a_ctrl_bsr; 1037 u8 hw_ssn_sel; 1038 #define RTW89_MGMT_HW_SSN_SEL 1 1039 u8 hw_seq_mode; 1040 #define RTW89_MGMT_HW_SEQ_MODE 1 1041 bool hiq; 1042 u8 port; 1043 bool er_cap; 1044 }; 1045 1046 struct rtw89_core_tx_request { 1047 enum rtw89_core_tx_type tx_type; 1048 1049 struct sk_buff *skb; 1050 struct ieee80211_vif *vif; 1051 struct ieee80211_sta *sta; 1052 struct rtw89_tx_desc_info desc_info; 1053 }; 1054 1055 struct rtw89_txq { 1056 struct list_head list; 1057 unsigned long flags; 1058 int wait_cnt; 1059 }; 1060 1061 struct rtw89_mac_ax_gnt { 1062 u8 gnt_bt_sw_en; 1063 u8 gnt_bt; 1064 u8 gnt_wl_sw_en; 1065 u8 gnt_wl; 1066 } __packed; 1067 1068 #define RTW89_MAC_AX_COEX_GNT_NR 2 1069 struct rtw89_mac_ax_coex_gnt { 1070 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1071 }; 1072 1073 enum rtw89_btc_ncnt { 1074 BTC_NCNT_POWER_ON = 0x0, 1075 BTC_NCNT_POWER_OFF, 1076 BTC_NCNT_INIT_COEX, 1077 BTC_NCNT_SCAN_START, 1078 BTC_NCNT_SCAN_FINISH, 1079 BTC_NCNT_SPECIAL_PACKET, 1080 BTC_NCNT_SWITCH_BAND, 1081 BTC_NCNT_RFK_TIMEOUT, 1082 BTC_NCNT_SHOW_COEX_INFO, 1083 BTC_NCNT_ROLE_INFO, 1084 BTC_NCNT_CONTROL, 1085 BTC_NCNT_RADIO_STATE, 1086 BTC_NCNT_CUSTOMERIZE, 1087 BTC_NCNT_WL_RFK, 1088 BTC_NCNT_WL_STA, 1089 BTC_NCNT_FWINFO, 1090 BTC_NCNT_TIMER, 1091 BTC_NCNT_NUM 1092 }; 1093 1094 enum rtw89_btc_btinfo { 1095 BTC_BTINFO_L0 = 0, 1096 BTC_BTINFO_L1, 1097 BTC_BTINFO_L2, 1098 BTC_BTINFO_L3, 1099 BTC_BTINFO_H0, 1100 BTC_BTINFO_H1, 1101 BTC_BTINFO_H2, 1102 BTC_BTINFO_H3, 1103 BTC_BTINFO_MAX 1104 }; 1105 1106 enum rtw89_btc_dcnt { 1107 BTC_DCNT_RUN = 0x0, 1108 BTC_DCNT_CX_RUNINFO, 1109 BTC_DCNT_RPT, 1110 BTC_DCNT_RPT_HANG, 1111 BTC_DCNT_CYCLE, 1112 BTC_DCNT_CYCLE_HANG, 1113 BTC_DCNT_W1, 1114 BTC_DCNT_W1_HANG, 1115 BTC_DCNT_B1, 1116 BTC_DCNT_B1_HANG, 1117 BTC_DCNT_TDMA_NONSYNC, 1118 BTC_DCNT_SLOT_NONSYNC, 1119 BTC_DCNT_BTCNT_HANG, 1120 BTC_DCNT_WL_SLOT_DRIFT, 1121 BTC_DCNT_WL_STA_LAST, 1122 BTC_DCNT_BT_SLOT_DRIFT, 1123 BTC_DCNT_BT_SLOT_FLOOD, 1124 BTC_DCNT_FDDT_TRIG, 1125 BTC_DCNT_E2G, 1126 BTC_DCNT_E2G_HANG, 1127 BTC_DCNT_NUM 1128 }; 1129 1130 enum rtw89_btc_wl_state_cnt { 1131 BTC_WCNT_SCANAP = 0x0, 1132 BTC_WCNT_DHCP, 1133 BTC_WCNT_EAPOL, 1134 BTC_WCNT_ARP, 1135 BTC_WCNT_SCBDUPDATE, 1136 BTC_WCNT_RFK_REQ, 1137 BTC_WCNT_RFK_GO, 1138 BTC_WCNT_RFK_REJECT, 1139 BTC_WCNT_RFK_TIMEOUT, 1140 BTC_WCNT_CH_UPDATE, 1141 BTC_WCNT_NUM 1142 }; 1143 1144 enum rtw89_btc_bt_state_cnt { 1145 BTC_BCNT_RETRY = 0x0, 1146 BTC_BCNT_REINIT, 1147 BTC_BCNT_REENABLE, 1148 BTC_BCNT_SCBDREAD, 1149 BTC_BCNT_RELINK, 1150 BTC_BCNT_IGNOWL, 1151 BTC_BCNT_INQPAG, 1152 BTC_BCNT_INQ, 1153 BTC_BCNT_PAGE, 1154 BTC_BCNT_ROLESW, 1155 BTC_BCNT_AFH, 1156 BTC_BCNT_INFOUPDATE, 1157 BTC_BCNT_INFOSAME, 1158 BTC_BCNT_SCBDUPDATE, 1159 BTC_BCNT_HIPRI_TX, 1160 BTC_BCNT_HIPRI_RX, 1161 BTC_BCNT_LOPRI_TX, 1162 BTC_BCNT_LOPRI_RX, 1163 BTC_BCNT_POLUT, 1164 BTC_BCNT_RATECHG, 1165 BTC_BCNT_NUM 1166 }; 1167 1168 enum rtw89_btc_bt_profile { 1169 BTC_BT_NOPROFILE = 0, 1170 BTC_BT_HFP = BIT(0), 1171 BTC_BT_HID = BIT(1), 1172 BTC_BT_A2DP = BIT(2), 1173 BTC_BT_PAN = BIT(3), 1174 BTC_PROFILE_MAX = 4, 1175 }; 1176 1177 struct rtw89_btc_ant_info { 1178 u8 type; /* shared, dedicated */ 1179 u8 num; 1180 u8 isolation; 1181 1182 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1183 u8 diversity: 1; 1184 u8 btg_pos: 2; 1185 u8 stream_cnt: 4; 1186 }; 1187 1188 enum rtw89_tfc_dir { 1189 RTW89_TFC_UL, 1190 RTW89_TFC_DL, 1191 }; 1192 1193 struct rtw89_btc_wl_smap { 1194 u32 busy: 1; 1195 u32 scan: 1; 1196 u32 connecting: 1; 1197 u32 roaming: 1; 1198 u32 _4way: 1; 1199 u32 rf_off: 1; 1200 u32 lps: 2; 1201 u32 ips: 1; 1202 u32 init_ok: 1; 1203 u32 traffic_dir : 2; 1204 u32 rf_off_pre: 1; 1205 u32 lps_pre: 2; 1206 }; 1207 1208 enum rtw89_tfc_lv { 1209 RTW89_TFC_IDLE, 1210 RTW89_TFC_ULTRA_LOW, 1211 RTW89_TFC_LOW, 1212 RTW89_TFC_MID, 1213 RTW89_TFC_HIGH, 1214 }; 1215 1216 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1217 DECLARE_EWMA(tp, 10, 2); 1218 1219 struct rtw89_traffic_stats { 1220 /* units in bytes */ 1221 u64 tx_unicast; 1222 u64 rx_unicast; 1223 u32 tx_avg_len; 1224 u32 rx_avg_len; 1225 1226 /* count for packets */ 1227 u64 tx_cnt; 1228 u64 rx_cnt; 1229 1230 /* units in Mbps */ 1231 u32 tx_throughput; 1232 u32 rx_throughput; 1233 u32 tx_throughput_raw; 1234 u32 rx_throughput_raw; 1235 1236 u32 rx_tf_acc; 1237 u32 rx_tf_periodic; 1238 1239 enum rtw89_tfc_lv tx_tfc_lv; 1240 enum rtw89_tfc_lv rx_tfc_lv; 1241 struct ewma_tp tx_ewma_tp; 1242 struct ewma_tp rx_ewma_tp; 1243 1244 u16 tx_rate; 1245 u16 rx_rate; 1246 }; 1247 1248 struct rtw89_btc_statistic { 1249 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1250 struct rtw89_traffic_stats traffic; 1251 }; 1252 1253 #define BTC_WL_RSSI_THMAX 4 1254 1255 struct rtw89_btc_wl_link_info { 1256 struct rtw89_btc_statistic stat; 1257 enum rtw89_tfc_dir dir; 1258 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1259 u8 mac_addr[ETH_ALEN]; 1260 u8 busy; 1261 u8 ch; 1262 u8 bw; 1263 u8 band; 1264 u8 role; 1265 u8 pid; 1266 u8 phy; 1267 u8 dtim_period; 1268 u8 mode; 1269 1270 u8 mac_id; 1271 u8 tx_retry; 1272 1273 u32 bcn_period; 1274 u32 busy_t; 1275 u32 tx_time; 1276 u32 client_cnt; 1277 u32 rx_rate_drop_cnt; 1278 1279 u32 active: 1; 1280 u32 noa: 1; 1281 u32 client_ps: 1; 1282 u32 connected: 2; 1283 }; 1284 1285 union rtw89_btc_wl_state_map { 1286 u32 val; 1287 struct rtw89_btc_wl_smap map; 1288 }; 1289 1290 struct rtw89_btc_bt_hfp_desc { 1291 u32 exist: 1; 1292 u32 type: 2; 1293 u32 rsvd: 29; 1294 }; 1295 1296 struct rtw89_btc_bt_hid_desc { 1297 u32 exist: 1; 1298 u32 slot_info: 2; 1299 u32 pair_cnt: 2; 1300 u32 type: 8; 1301 u32 rsvd: 19; 1302 }; 1303 1304 struct rtw89_btc_bt_a2dp_desc { 1305 u8 exist: 1; 1306 u8 exist_last: 1; 1307 u8 play_latency: 1; 1308 u8 type: 3; 1309 u8 active: 1; 1310 u8 sink: 1; 1311 1312 u8 bitpool; 1313 u16 vendor_id; 1314 u32 device_name; 1315 u32 flush_time; 1316 }; 1317 1318 struct rtw89_btc_bt_pan_desc { 1319 u32 exist: 1; 1320 u32 type: 1; 1321 u32 active: 1; 1322 u32 rsvd: 29; 1323 }; 1324 1325 struct rtw89_btc_bt_rfk_info { 1326 u32 run: 1; 1327 u32 req: 1; 1328 u32 timeout: 1; 1329 u32 rsvd: 29; 1330 }; 1331 1332 union rtw89_btc_bt_rfk_info_map { 1333 u32 val; 1334 struct rtw89_btc_bt_rfk_info map; 1335 }; 1336 1337 struct rtw89_btc_bt_ver_info { 1338 u32 fw_coex; /* match with which coex_ver */ 1339 u32 fw; 1340 }; 1341 1342 struct rtw89_btc_bool_sta_chg { 1343 u32 now: 1; 1344 u32 last: 1; 1345 u32 remain: 1; 1346 u32 srvd: 29; 1347 }; 1348 1349 struct rtw89_btc_u8_sta_chg { 1350 u8 now; 1351 u8 last; 1352 u8 remain; 1353 u8 rsvd; 1354 }; 1355 1356 struct rtw89_btc_wl_scan_info { 1357 u8 band[RTW89_PHY_MAX]; 1358 u8 phy_map; 1359 u8 rsvd; 1360 }; 1361 1362 struct rtw89_btc_wl_dbcc_info { 1363 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1364 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1365 u8 real_band[RTW89_PHY_MAX]; 1366 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1367 }; 1368 1369 struct rtw89_btc_wl_active_role { 1370 u8 connected: 1; 1371 u8 pid: 3; 1372 u8 phy: 1; 1373 u8 noa: 1; 1374 u8 band: 2; 1375 1376 u8 client_ps: 1; 1377 u8 bw: 7; 1378 1379 u8 role; 1380 u8 ch; 1381 1382 u16 tx_lvl; 1383 u16 rx_lvl; 1384 u16 tx_rate; 1385 u16 rx_rate; 1386 }; 1387 1388 struct rtw89_btc_wl_active_role_v1 { 1389 u8 connected: 1; 1390 u8 pid: 3; 1391 u8 phy: 1; 1392 u8 noa: 1; 1393 u8 band: 2; 1394 1395 u8 client_ps: 1; 1396 u8 bw: 7; 1397 1398 u8 role; 1399 u8 ch; 1400 1401 u16 tx_lvl; 1402 u16 rx_lvl; 1403 u16 tx_rate; 1404 u16 rx_rate; 1405 1406 u32 noa_duration; /* ms */ 1407 }; 1408 1409 struct rtw89_btc_wl_active_role_v2 { 1410 u8 connected: 1; 1411 u8 pid: 3; 1412 u8 phy: 1; 1413 u8 noa: 1; 1414 u8 band: 2; 1415 1416 u8 client_ps: 1; 1417 u8 bw: 7; 1418 1419 u8 role; 1420 u8 ch; 1421 1422 u32 noa_duration; /* ms */ 1423 }; 1424 1425 struct rtw89_btc_wl_role_info_bpos { 1426 u16 none: 1; 1427 u16 station: 1; 1428 u16 ap: 1; 1429 u16 vap: 1; 1430 u16 adhoc: 1; 1431 u16 adhoc_master: 1; 1432 u16 mesh: 1; 1433 u16 moniter: 1; 1434 u16 p2p_device: 1; 1435 u16 p2p_gc: 1; 1436 u16 p2p_go: 1; 1437 u16 nan: 1; 1438 }; 1439 1440 struct rtw89_btc_wl_scc_ctrl { 1441 u8 null_role1; 1442 u8 null_role2; 1443 u8 ebt_null; /* if tx null at EBT slot */ 1444 }; 1445 1446 union rtw89_btc_wl_role_info_map { 1447 u16 val; 1448 struct rtw89_btc_wl_role_info_bpos role; 1449 }; 1450 1451 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1452 u8 connect_cnt; 1453 u8 link_mode; 1454 union rtw89_btc_wl_role_info_map role_map; 1455 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1456 }; 1457 1458 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1459 u8 connect_cnt; 1460 u8 link_mode; 1461 union rtw89_btc_wl_role_info_map role_map; 1462 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1463 u32 mrole_type; /* btc_wl_mrole_type */ 1464 u32 mrole_noa_duration; /* ms */ 1465 1466 u32 dbcc_en: 1; 1467 u32 dbcc_chg: 1; 1468 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1469 u32 link_mode_chg: 1; 1470 u32 rsvd: 27; 1471 }; 1472 1473 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1474 u8 connect_cnt; 1475 u8 link_mode; 1476 union rtw89_btc_wl_role_info_map role_map; 1477 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1478 u32 mrole_type; /* btc_wl_mrole_type */ 1479 u32 mrole_noa_duration; /* ms */ 1480 1481 u32 dbcc_en: 1; 1482 u32 dbcc_chg: 1; 1483 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1484 u32 link_mode_chg: 1; 1485 u32 rsvd: 27; 1486 }; 1487 1488 struct rtw89_btc_wl_ver_info { 1489 u32 fw_coex; /* match with which coex_ver */ 1490 u32 fw; 1491 u32 mac; 1492 u32 bb; 1493 u32 rf; 1494 }; 1495 1496 struct rtw89_btc_wl_afh_info { 1497 u8 en; 1498 u8 ch; 1499 u8 bw; 1500 u8 rsvd; 1501 } __packed; 1502 1503 struct rtw89_btc_wl_rfk_info { 1504 u32 state: 2; 1505 u32 path_map: 4; 1506 u32 phy_map: 2; 1507 u32 band: 2; 1508 u32 type: 8; 1509 u32 rsvd: 14; 1510 }; 1511 1512 struct rtw89_btc_bt_smap { 1513 u32 connect: 1; 1514 u32 ble_connect: 1; 1515 u32 acl_busy: 1; 1516 u32 sco_busy: 1; 1517 u32 mesh_busy: 1; 1518 u32 inq_pag: 1; 1519 }; 1520 1521 union rtw89_btc_bt_state_map { 1522 u32 val; 1523 struct rtw89_btc_bt_smap map; 1524 }; 1525 1526 #define BTC_BT_RSSI_THMAX 4 1527 #define BTC_BT_AFH_GROUP 12 1528 #define BTC_BT_AFH_LE_GROUP 5 1529 1530 struct rtw89_btc_bt_link_info { 1531 struct rtw89_btc_u8_sta_chg profile_cnt; 1532 struct rtw89_btc_bool_sta_chg multi_link; 1533 struct rtw89_btc_bool_sta_chg relink; 1534 struct rtw89_btc_bt_hfp_desc hfp_desc; 1535 struct rtw89_btc_bt_hid_desc hid_desc; 1536 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1537 struct rtw89_btc_bt_pan_desc pan_desc; 1538 union rtw89_btc_bt_state_map status; 1539 1540 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1541 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1542 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1543 u8 afh_map[BTC_BT_AFH_GROUP]; 1544 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1545 1546 u32 role_sw: 1; 1547 u32 slave_role: 1; 1548 u32 afh_update: 1; 1549 u32 cqddr: 1; 1550 u32 rssi: 8; 1551 u32 tx_3m: 1; 1552 u32 rsvd: 19; 1553 }; 1554 1555 struct rtw89_btc_3rdcx_info { 1556 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1557 u8 hw_coex; 1558 u16 rsvd; 1559 }; 1560 1561 struct rtw89_btc_dm_emap { 1562 u32 init: 1; 1563 u32 pta_owner: 1; 1564 u32 wl_rfk_timeout: 1; 1565 u32 bt_rfk_timeout: 1; 1566 u32 wl_fw_hang: 1; 1567 u32 cycle_hang: 1; 1568 u32 w1_hang: 1; 1569 u32 b1_hang: 1; 1570 u32 tdma_no_sync: 1; 1571 u32 slot_no_sync: 1; 1572 u32 wl_slot_drift: 1; 1573 u32 bt_slot_drift: 1; 1574 u32 role_num_mismatch: 1; 1575 u32 null1_tx_late: 1; 1576 u32 bt_afh_conflict: 1; 1577 u32 bt_leafh_conflict: 1; 1578 u32 bt_slot_flood: 1; 1579 u32 wl_e2g_hang: 1; 1580 u32 wl_ver_mismatch: 1; 1581 u32 bt_ver_mismatch: 1; 1582 }; 1583 1584 union rtw89_btc_dm_error_map { 1585 u32 val; 1586 struct rtw89_btc_dm_emap map; 1587 }; 1588 1589 struct rtw89_btc_rf_para { 1590 u32 tx_pwr_freerun; 1591 u32 rx_gain_freerun; 1592 u32 tx_pwr_perpkt; 1593 u32 rx_gain_perpkt; 1594 }; 1595 1596 struct rtw89_btc_wl_nhm { 1597 u8 instant_wl_nhm_dbm; 1598 u8 instant_wl_nhm_per_mhz; 1599 u16 valid_record_times; 1600 s8 record_pwr[16]; 1601 u8 record_ratio[16]; 1602 s8 pwr; /* dbm_per_MHz */ 1603 u8 ratio; 1604 u8 current_status; 1605 u8 refresh; 1606 bool start_flag; 1607 s8 pwr_max; 1608 s8 pwr_min; 1609 }; 1610 1611 struct rtw89_btc_wl_info { 1612 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1613 struct rtw89_btc_wl_rfk_info rfk_info; 1614 struct rtw89_btc_wl_ver_info ver_info; 1615 struct rtw89_btc_wl_afh_info afh_info; 1616 struct rtw89_btc_wl_role_info role_info; 1617 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1618 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1619 struct rtw89_btc_wl_scan_info scan_info; 1620 struct rtw89_btc_wl_dbcc_info dbcc_info; 1621 struct rtw89_btc_rf_para rf_para; 1622 struct rtw89_btc_wl_nhm nhm; 1623 union rtw89_btc_wl_state_map status; 1624 1625 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1626 u8 rssi_level; 1627 u8 cn_report; 1628 1629 bool scbd_change; 1630 u32 scbd; 1631 }; 1632 1633 struct rtw89_btc_module { 1634 struct rtw89_btc_ant_info ant; 1635 u8 rfe_type; 1636 u8 cv; 1637 1638 u8 bt_solo: 1; 1639 u8 bt_pos: 1; 1640 u8 switch_type: 1; 1641 u8 wa_type: 3; 1642 1643 u8 kt_ver_adie; 1644 }; 1645 1646 #define RTW89_BTC_DM_MAXSTEP 30 1647 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1648 1649 struct rtw89_btc_dm_step { 1650 u16 step[RTW89_BTC_DM_MAXSTEP]; 1651 u8 step_pos; 1652 bool step_ov; 1653 }; 1654 1655 struct rtw89_btc_init_info { 1656 struct rtw89_btc_module module; 1657 u8 wl_guard_ch; 1658 1659 u8 wl_only: 1; 1660 u8 wl_init_ok: 1; 1661 u8 dbcc_en: 1; 1662 u8 cx_other: 1; 1663 u8 bt_only: 1; 1664 1665 u16 rsvd; 1666 }; 1667 1668 struct rtw89_btc_wl_tx_limit_para { 1669 u16 enable; 1670 u32 tx_time; /* unit: us */ 1671 u16 tx_retry; 1672 }; 1673 1674 enum rtw89_btc_bt_scan_type { 1675 BTC_SCAN_INQ = 0, 1676 BTC_SCAN_PAGE, 1677 BTC_SCAN_BLE, 1678 BTC_SCAN_INIT, 1679 BTC_SCAN_TV, 1680 BTC_SCAN_ADV, 1681 BTC_SCAN_MAX1, 1682 }; 1683 1684 enum rtw89_btc_ble_scan_type { 1685 CXSCAN_BG = 0, 1686 CXSCAN_INIT, 1687 CXSCAN_LE, 1688 CXSCAN_MAX 1689 }; 1690 1691 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 1692 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 1693 1694 struct rtw89_btc_bt_scan_info_v1 { 1695 __le16 win; 1696 __le16 intvl; 1697 __le32 flags; 1698 } __packed; 1699 1700 struct rtw89_btc_bt_scan_info_v2 { 1701 __le16 win; 1702 __le16 intvl; 1703 } __packed; 1704 1705 struct rtw89_btc_fbtc_btscan_v1 { 1706 u8 fver; /* btc_ver::fcxbtscan */ 1707 u8 rsvd; 1708 __le16 rsvd2; 1709 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 1710 } __packed; 1711 1712 struct rtw89_btc_fbtc_btscan_v2 { 1713 u8 fver; /* btc_ver::fcxbtscan */ 1714 u8 type; 1715 __le16 rsvd2; 1716 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 1717 } __packed; 1718 1719 union rtw89_btc_fbtc_btscan { 1720 struct rtw89_btc_fbtc_btscan_v1 v1; 1721 struct rtw89_btc_fbtc_btscan_v2 v2; 1722 }; 1723 1724 struct rtw89_btc_bt_info { 1725 struct rtw89_btc_bt_link_info link_info; 1726 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 1727 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 1728 struct rtw89_btc_bt_ver_info ver_info; 1729 struct rtw89_btc_bool_sta_chg enable; 1730 struct rtw89_btc_bool_sta_chg inq_pag; 1731 struct rtw89_btc_rf_para rf_para; 1732 union rtw89_btc_bt_rfk_info_map rfk_info; 1733 1734 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1735 1736 u32 scbd; 1737 u32 feature; 1738 1739 u32 mbx_avl: 1; 1740 u32 whql_test: 1; 1741 u32 igno_wl: 1; 1742 u32 reinit: 1; 1743 u32 ble_scan_en: 1; 1744 u32 btg_type: 1; 1745 u32 inq: 1; 1746 u32 pag: 1; 1747 u32 run_patch_code: 1; 1748 u32 hi_lna_rx: 1; 1749 u32 scan_rx_low_pri: 1; 1750 u32 scan_info_update: 1; 1751 u32 rsvd: 20; 1752 }; 1753 1754 struct rtw89_btc_cx { 1755 struct rtw89_btc_wl_info wl; 1756 struct rtw89_btc_bt_info bt; 1757 struct rtw89_btc_3rdcx_info other; 1758 u32 state_map; 1759 u32 cnt_bt[BTC_BCNT_NUM]; 1760 u32 cnt_wl[BTC_WCNT_NUM]; 1761 }; 1762 1763 struct rtw89_btc_fbtc_tdma { 1764 u8 type; /* btc_ver::fcxtdma */ 1765 u8 rxflctrl; 1766 u8 txpause; 1767 u8 wtgle_n; 1768 u8 leak_n; 1769 u8 ext_ctrl; 1770 u8 rxflctrl_role; 1771 u8 option_ctrl; 1772 } __packed; 1773 1774 struct rtw89_btc_fbtc_tdma_v3 { 1775 u8 fver; /* btc_ver::fcxtdma */ 1776 u8 rsvd; 1777 __le16 rsvd1; 1778 struct rtw89_btc_fbtc_tdma tdma; 1779 } __packed; 1780 1781 union rtw89_btc_fbtc_tdma_le32 { 1782 struct rtw89_btc_fbtc_tdma v1; 1783 struct rtw89_btc_fbtc_tdma_v3 v3; 1784 }; 1785 1786 #define CXMREG_MAX 30 1787 #define CXMREG_MAX_V2 20 1788 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1789 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1790 1791 enum rtw89_btc_bt_sta_counter { 1792 BTC_BCNT_RFK_REQ = 0, 1793 BTC_BCNT_RFK_GO = 1, 1794 BTC_BCNT_RFK_REJECT = 2, 1795 BTC_BCNT_RFK_FAIL = 3, 1796 BTC_BCNT_RFK_TIMEOUT = 4, 1797 BTC_BCNT_HI_TX = 5, 1798 BTC_BCNT_HI_RX = 6, 1799 BTC_BCNT_LO_TX = 7, 1800 BTC_BCNT_LO_RX = 8, 1801 BTC_BCNT_POLLUTED = 9, 1802 BTC_BCNT_STA_MAX 1803 }; 1804 1805 enum rtw89_btc_bt_sta_counter_v105 { 1806 BTC_BCNT_RFK_REQ_V105 = 0, 1807 BTC_BCNT_HI_TX_V105 = 1, 1808 BTC_BCNT_HI_RX_V105 = 2, 1809 BTC_BCNT_LO_TX_V105 = 3, 1810 BTC_BCNT_LO_RX_V105 = 4, 1811 BTC_BCNT_POLLUTED_V105 = 5, 1812 BTC_BCNT_STA_MAX_V105 1813 }; 1814 1815 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 1816 u16 fver; /* btc_ver::fcxbtcrpt */ 1817 u16 rpt_cnt; /* tmr counters */ 1818 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1819 u32 wl_fw_cx_offload; 1820 u32 wl_fw_ver; 1821 u32 rpt_enable; 1822 u32 rpt_para; /* ms */ 1823 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1824 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1825 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1826 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1827 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1828 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1829 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 1830 u32 c2h_cnt; /* fw send c2h counter */ 1831 u32 h2c_cnt; /* fw recv h2c counter */ 1832 } __packed; 1833 1834 struct rtw89_btc_fbtc_rpt_ctrl_info { 1835 __le32 cnt; /* fw report counter */ 1836 __le32 en; /* report map */ 1837 __le32 para; /* not used */ 1838 1839 __le32 cnt_c2h; /* fw send c2h counter */ 1840 __le32 cnt_h2c; /* fw recv h2c counter */ 1841 __le32 len_c2h; /* The total length of the last C2H */ 1842 1843 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1844 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1845 } __packed; 1846 1847 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 1848 __le32 cx_ver; /* match which driver's coex version */ 1849 __le32 fw_ver; 1850 __le32 en; /* report map */ 1851 1852 __le16 cnt; /* fw report counter */ 1853 __le16 cnt_c2h; /* fw send c2h counter */ 1854 __le16 cnt_h2c; /* fw recv h2c counter */ 1855 __le16 len_c2h; /* The total length of the last C2H */ 1856 1857 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1858 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1859 } __packed; 1860 1861 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 1862 __le32 cx_ver; /* match which driver's coex version */ 1863 __le32 cx_offload; 1864 __le32 fw_ver; 1865 } __packed; 1866 1867 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 1868 __le32 cnt_empty; /* a2dp empty count */ 1869 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 1870 __le32 cnt_tx; 1871 __le32 cnt_ack; 1872 __le32 cnt_nack; 1873 } __packed; 1874 1875 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 1876 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 1877 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 1878 __le32 cnt_recv; /* fw recv mailbox counter */ 1879 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 1880 } __packed; 1881 1882 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 1883 u8 fver; 1884 u8 rsvd; 1885 __le16 rsvd1; 1886 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 1887 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 1888 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1889 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 1890 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 1891 } __packed; 1892 1893 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 1894 u8 fver; 1895 u8 rsvd; 1896 __le16 rsvd1; 1897 1898 u8 gnt_val[RTW89_PHY_MAX][4]; 1899 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 1900 1901 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1902 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1903 } __packed; 1904 1905 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 1906 u8 fver; 1907 u8 rsvd; 1908 __le16 rsvd1; 1909 1910 u8 gnt_val[RTW89_PHY_MAX][4]; 1911 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 1912 1913 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1914 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1915 } __packed; 1916 1917 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 1918 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 1919 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 1920 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 1921 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 1922 }; 1923 1924 enum rtw89_fbtc_ext_ctrl_type { 1925 CXECTL_OFF = 0x0, /* tdma off */ 1926 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 1927 CXECTL_EXT = 0x2, 1928 CXECTL_MAX 1929 }; 1930 1931 union rtw89_btc_fbtc_rxflct { 1932 u8 val; 1933 u8 type: 3; 1934 u8 tgln_n: 5; 1935 }; 1936 1937 enum rtw89_btc_cxst_state { 1938 CXST_OFF = 0x0, 1939 CXST_B2W = 0x1, 1940 CXST_W1 = 0x2, 1941 CXST_W2 = 0x3, 1942 CXST_W2B = 0x4, 1943 CXST_B1 = 0x5, 1944 CXST_B2 = 0x6, 1945 CXST_B3 = 0x7, 1946 CXST_B4 = 0x8, 1947 CXST_LK = 0x9, 1948 CXST_BLK = 0xa, 1949 CXST_E2G = 0xb, 1950 CXST_E5G = 0xc, 1951 CXST_EBT = 0xd, 1952 CXST_ENULL = 0xe, 1953 CXST_WLK = 0xf, 1954 CXST_W1FDD = 0x10, 1955 CXST_B1FDD = 0x11, 1956 CXST_MAX = 0x12, 1957 }; 1958 1959 enum rtw89_btc_cxevnt { 1960 CXEVNT_TDMA_ENTRY = 0x0, 1961 CXEVNT_WL_TMR, 1962 CXEVNT_B1_TMR, 1963 CXEVNT_B2_TMR, 1964 CXEVNT_B3_TMR, 1965 CXEVNT_B4_TMR, 1966 CXEVNT_W2B_TMR, 1967 CXEVNT_B2W_TMR, 1968 CXEVNT_BCN_EARLY, 1969 CXEVNT_A2DP_EMPTY, 1970 CXEVNT_LK_END, 1971 CXEVNT_RX_ISR, 1972 CXEVNT_RX_FC0, 1973 CXEVNT_RX_FC1, 1974 CXEVNT_BT_RELINK, 1975 CXEVNT_BT_RETRY, 1976 CXEVNT_E2G, 1977 CXEVNT_E5G, 1978 CXEVNT_EBT, 1979 CXEVNT_ENULL, 1980 CXEVNT_DRV_WLK, 1981 CXEVNT_BCN_OK, 1982 CXEVNT_BT_CHANGE, 1983 CXEVNT_EBT_EXTEND, 1984 CXEVNT_E2G_NULL1, 1985 CXEVNT_B1FDD_TMR, 1986 CXEVNT_MAX 1987 }; 1988 1989 enum { 1990 CXBCN_ALL = 0x0, 1991 CXBCN_ALL_OK, 1992 CXBCN_BT_SLOT, 1993 CXBCN_BT_OK, 1994 CXBCN_MAX 1995 }; 1996 1997 enum btc_slot_type { 1998 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 1999 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2000 CXSTYPE_NUM, 2001 }; 2002 2003 enum { /* TIME */ 2004 CXT_BT = 0x0, 2005 CXT_WL = 0x1, 2006 CXT_MAX 2007 }; 2008 2009 enum { /* TIME-A2DP */ 2010 CXT_FLCTRL_OFF = 0x0, 2011 CXT_FLCTRL_ON = 0x1, 2012 CXT_FLCTRL_MAX 2013 }; 2014 2015 enum { /* STEP TYPE */ 2016 CXSTEP_NONE = 0x0, 2017 CXSTEP_EVNT = 0x1, 2018 CXSTEP_SLOT = 0x2, 2019 CXSTEP_MAX, 2020 }; 2021 2022 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2023 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2024 RPT_BT_AFH_SEQ_LE = 0x20 2025 }; 2026 2027 #define BTC_DBG_MAX1 32 2028 struct rtw89_btc_fbtc_gpio_dbg { 2029 u8 fver; /* btc_ver::fcxgpiodbg */ 2030 u8 rsvd; 2031 u16 rsvd2; 2032 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2033 u32 pre_state; /* the debug signal is 1 or 0 */ 2034 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2035 } __packed; 2036 2037 struct rtw89_btc_fbtc_mreg_val_v1 { 2038 u8 fver; /* btc_ver::fcxmreg */ 2039 u8 reg_num; 2040 __le16 rsvd; 2041 __le32 mreg_val[CXMREG_MAX]; 2042 } __packed; 2043 2044 struct rtw89_btc_fbtc_mreg_val_v2 { 2045 u8 fver; /* btc_ver::fcxmreg */ 2046 u8 reg_num; 2047 __le16 rsvd; 2048 __le32 mreg_val[CXMREG_MAX_V2]; 2049 } __packed; 2050 2051 union rtw89_btc_fbtc_mreg_val { 2052 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2053 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2054 }; 2055 2056 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2057 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2058 .offset = cpu_to_le32(__offset), } 2059 2060 struct rtw89_btc_fbtc_mreg { 2061 __le16 type; 2062 __le16 bytes; 2063 __le32 offset; 2064 } __packed; 2065 2066 struct rtw89_btc_fbtc_slot { 2067 __le16 dur; 2068 __le32 cxtbl; 2069 __le16 cxtype; 2070 } __packed; 2071 2072 struct rtw89_btc_fbtc_slots { 2073 u8 fver; /* btc_ver::fcxslots */ 2074 u8 tbl_num; 2075 __le16 rsvd; 2076 __le32 update_map; 2077 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2078 } __packed; 2079 2080 struct rtw89_btc_fbtc_step { 2081 u8 type; 2082 u8 val; 2083 __le16 difft; 2084 } __packed; 2085 2086 struct rtw89_btc_fbtc_steps_v2 { 2087 u8 fver; /* btc_ver::fcxstep */ 2088 u8 rsvd; 2089 __le16 cnt; 2090 __le16 pos_old; 2091 __le16 pos_new; 2092 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2093 } __packed; 2094 2095 struct rtw89_btc_fbtc_steps_v3 { 2096 u8 fver; 2097 u8 en; 2098 __le16 rsvd; 2099 __le32 cnt; 2100 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2101 } __packed; 2102 2103 union rtw89_btc_fbtc_steps_info { 2104 struct rtw89_btc_fbtc_steps_v2 v2; 2105 struct rtw89_btc_fbtc_steps_v3 v3; 2106 }; 2107 2108 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2109 u8 fver; /* btc_ver::fcxcysta */ 2110 u8 rsvd; 2111 __le16 cycles; /* total cycle number */ 2112 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2113 __le16 a2dpept; /* a2dp empty cnt */ 2114 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2115 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2116 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2117 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2118 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2119 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2120 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2121 __le16 tmax_a2dpept; /* max a2dp empty time */ 2122 __le16 tavg_lk; /* avg leak-slot time */ 2123 __le16 tmax_lk; /* max leak-slot time */ 2124 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2125 __le32 bcn_cnt[CXBCN_MAX]; 2126 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2127 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2128 __le32 skip_cnt; 2129 __le32 exception; 2130 __le32 except_cnt; 2131 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2132 } __packed; 2133 2134 struct rtw89_btc_fbtc_fdd_try_info { 2135 __le16 cycles[CXT_FLCTRL_MAX]; 2136 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2137 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2138 } __packed; 2139 2140 struct rtw89_btc_fbtc_cycle_time_info { 2141 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2142 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2143 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2144 } __packed; 2145 2146 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2147 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2148 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2149 } __packed; 2150 2151 struct rtw89_btc_fbtc_a2dp_trx_stat { 2152 u8 empty_cnt; 2153 u8 retry_cnt; 2154 u8 tx_rate; 2155 u8 tx_cnt; 2156 u8 ack_cnt; 2157 u8 nack_cnt; 2158 u8 rsvd1; 2159 u8 rsvd2; 2160 } __packed; 2161 2162 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2163 u8 empty_cnt; 2164 u8 retry_cnt; 2165 u8 tx_rate; 2166 u8 tx_cnt; 2167 u8 ack_cnt; 2168 u8 nack_cnt; 2169 u8 no_empty_cnt; 2170 u8 rsvd; 2171 } __packed; 2172 2173 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2174 __le16 cnt; /* a2dp empty cnt */ 2175 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2176 __le16 tavg; /* avg a2dp empty time */ 2177 __le16 tmax; /* max a2dp empty time */ 2178 } __packed; 2179 2180 struct rtw89_btc_fbtc_cycle_leak_info { 2181 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2182 __le16 tavg; /* avg leak-slot time */ 2183 __le16 tmax; /* max leak-slot time */ 2184 } __packed; 2185 2186 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2187 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2188 2189 struct rtw89_btc_fbtc_cycle_fddt_info { 2190 __le16 train_cycle; 2191 __le16 tp; 2192 2193 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2194 s8 bt_tx_power; /* decrease Tx power (dB) */ 2195 s8 bt_rx_gain; /* LNA constrain level */ 2196 u8 no_empty_cnt; 2197 2198 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2199 u8 cn; /* condition_num */ 2200 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2201 u8 train_result; /* refer to enum btc_fddt_check_map */ 2202 } __packed; 2203 2204 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2205 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2206 2207 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2208 __le16 train_cycle; 2209 __le16 tp; 2210 2211 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2212 s8 bt_tx_power; /* decrease Tx power (dB) */ 2213 s8 bt_rx_gain; /* LNA constrain level */ 2214 u8 no_empty_cnt; 2215 2216 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2217 u8 cn; /* condition_num */ 2218 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2219 u8 train_result; /* refer to enum btc_fddt_check_map */ 2220 } __packed; 2221 2222 struct rtw89_btc_fbtc_fddt_cell_status { 2223 s8 wl_tx_pwr; 2224 s8 bt_tx_pwr; 2225 s8 bt_rx_gain; 2226 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2227 } __packed; 2228 2229 struct rtw89_btc_fbtc_fddt_cell_status_v5 { 2230 s8 wl_tx_pwr; 2231 s8 bt_tx_pwr; 2232 s8 bt_rx_gain; 2233 } __packed; 2234 2235 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2236 u8 fver; 2237 u8 rsvd; 2238 __le16 cycles; /* total cycle number */ 2239 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2240 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2241 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2242 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2243 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2244 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2245 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2246 __le32 bcn_cnt[CXBCN_MAX]; 2247 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2248 __le32 skip_cnt; 2249 __le32 except_cnt; 2250 __le32 except_map; 2251 } __packed; 2252 2253 #define FDD_TRAIN_WL_DIRECTION 2 2254 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2255 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2256 2257 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2258 u8 fver; 2259 u8 rsvd; 2260 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2261 u8 except_cnt; 2262 2263 __le16 skip_cnt; 2264 __le16 cycles; /* total cycle number */ 2265 2266 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2267 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2268 __le16 bcn_cnt[CXBCN_MAX]; 2269 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2270 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2271 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2272 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2273 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2274 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2275 [FDD_TRAIN_WL_RSSI_LEVEL] 2276 [FDD_TRAIN_BT_RSSI_LEVEL]; 2277 __le32 except_map; 2278 } __packed; 2279 2280 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2281 u8 fver; 2282 u8 rsvd; 2283 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2284 u8 except_cnt; 2285 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2286 2287 __le16 skip_cnt; 2288 __le16 cycles; /* total cycle number */ 2289 2290 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2291 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2292 __le16 bcn_cnt[CXBCN_MAX]; 2293 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2294 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2295 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2296 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2297 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2298 struct rtw89_btc_fbtc_fddt_cell_status_v5 fddt_cells[FDD_TRAIN_WL_DIRECTION] 2299 [FDD_TRAIN_WL_RSSI_LEVEL] 2300 [FDD_TRAIN_BT_RSSI_LEVEL]; 2301 __le32 except_map; 2302 } __packed; 2303 2304 union rtw89_btc_fbtc_cysta_info { 2305 struct rtw89_btc_fbtc_cysta_v2 v2; 2306 struct rtw89_btc_fbtc_cysta_v3 v3; 2307 struct rtw89_btc_fbtc_cysta_v4 v4; 2308 struct rtw89_btc_fbtc_cysta_v5 v5; 2309 }; 2310 2311 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2312 u8 fver; /* btc_ver::fcxnullsta */ 2313 u8 rsvd; 2314 __le16 rsvd2; 2315 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2316 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2317 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2318 } __packed; 2319 2320 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2321 u8 fver; /* btc_ver::fcxnullsta */ 2322 u8 rsvd; 2323 __le16 rsvd2; 2324 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2325 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2326 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2327 } __packed; 2328 2329 union rtw89_btc_fbtc_cynullsta_info { 2330 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2331 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2332 }; 2333 2334 struct rtw89_btc_fbtc_btver { 2335 u8 fver; /* btc_ver::fcxbtver */ 2336 u8 rsvd; 2337 __le16 rsvd2; 2338 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2339 __le32 fw_ver; 2340 __le32 feature; 2341 } __packed; 2342 2343 struct rtw89_btc_fbtc_btafh { 2344 u8 fver; /* btc_ver::fcxbtafh */ 2345 u8 rsvd; 2346 __le16 rsvd2; 2347 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2348 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2349 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2350 } __packed; 2351 2352 struct rtw89_btc_fbtc_btafh_v2 { 2353 u8 fver; /* btc_ver::fcxbtafh */ 2354 u8 rsvd; 2355 u8 rsvd2; 2356 u8 map_type; 2357 u8 afh_l[4]; 2358 u8 afh_m[4]; 2359 u8 afh_h[4]; 2360 u8 afh_le_a[4]; 2361 u8 afh_le_b[4]; 2362 } __packed; 2363 2364 struct rtw89_btc_fbtc_btdevinfo { 2365 u8 fver; /* btc_ver::fcxbtdevinfo */ 2366 u8 rsvd; 2367 __le16 vendor_id; 2368 __le32 dev_name; /* only 24 bits valid */ 2369 __le32 flush_time; 2370 } __packed; 2371 2372 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2373 struct rtw89_btc_rf_trx_para { 2374 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2375 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2376 u8 bt_tx_power; /* decrease Tx power (dB) */ 2377 u8 bt_rx_gain; /* LNA constrain level */ 2378 }; 2379 2380 struct rtw89_btc_trx_info { 2381 u8 tx_lvl; 2382 u8 rx_lvl; 2383 u8 wl_rssi; 2384 u8 bt_rssi; 2385 2386 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2387 s8 rx_gain; /* rx gain table index (TBD.) */ 2388 s8 bt_tx_power; /* decrease Tx power (dB) */ 2389 s8 bt_rx_gain; /* LNA constrain level */ 2390 2391 u8 cn; /* condition_num */ 2392 s8 nhm; 2393 u8 bt_profile; 2394 u8 rsvd2; 2395 2396 u16 tx_rate; 2397 u16 rx_rate; 2398 2399 u32 tx_tp; 2400 u32 rx_tp; 2401 u32 rx_err_ratio; 2402 }; 2403 2404 struct rtw89_btc_dm { 2405 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2406 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 2407 struct rtw89_btc_fbtc_tdma tdma; 2408 struct rtw89_btc_fbtc_tdma tdma_now; 2409 struct rtw89_mac_ax_coex_gnt gnt; 2410 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 2411 struct rtw89_btc_rf_trx_para rf_trx_para; 2412 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2413 struct rtw89_btc_dm_step dm_step; 2414 struct rtw89_btc_wl_scc_ctrl wl_scc; 2415 struct rtw89_btc_trx_info trx_info; 2416 union rtw89_btc_dm_error_map error; 2417 u32 cnt_dm[BTC_DCNT_NUM]; 2418 u32 cnt_notify[BTC_NCNT_NUM]; 2419 2420 u32 update_slot_map; 2421 u32 set_ant_path; 2422 2423 u32 wl_only: 1; 2424 u32 wl_fw_cx_offload: 1; 2425 u32 freerun: 1; 2426 u32 fddt_train: 1; 2427 u32 wl_ps_ctrl: 2; 2428 u32 wl_mimo_ps: 1; 2429 u32 leak_ap: 1; 2430 u32 noisy_level: 3; 2431 u32 coex_info_map: 8; 2432 u32 bt_only: 1; 2433 u32 wl_btg_rx: 1; 2434 u32 trx_para_level: 8; 2435 u32 wl_stb_chg: 1; 2436 u32 pta_owner: 1; 2437 u32 tdma_instant_excute: 1; 2438 2439 u16 slot_dur[CXST_MAX]; 2440 2441 u8 run_reason; 2442 u8 run_action; 2443 2444 u8 wl_lna2: 1; 2445 }; 2446 2447 struct rtw89_btc_ctrl { 2448 u32 manual: 1; 2449 u32 igno_bt: 1; 2450 u32 always_freerun: 1; 2451 u32 trace_step: 16; 2452 u32 rsvd: 12; 2453 }; 2454 2455 struct rtw89_btc_dbg { 2456 /* cmd "rb" */ 2457 bool rb_done; 2458 u32 rb_val; 2459 }; 2460 2461 enum rtw89_btc_btf_fw_event { 2462 BTF_EVNT_RPT = 0, 2463 BTF_EVNT_BT_INFO = 1, 2464 BTF_EVNT_BT_SCBD = 2, 2465 BTF_EVNT_BT_REG = 3, 2466 BTF_EVNT_CX_RUNINFO = 4, 2467 BTF_EVNT_BT_PSD = 5, 2468 BTF_EVNT_BUF_OVERFLOW, 2469 BTF_EVNT_C2H_LOOPBACK, 2470 BTF_EVNT_MAX, 2471 }; 2472 2473 enum btf_fw_event_report { 2474 BTC_RPT_TYPE_CTRL = 0x0, 2475 BTC_RPT_TYPE_TDMA, 2476 BTC_RPT_TYPE_SLOT, 2477 BTC_RPT_TYPE_CYSTA, 2478 BTC_RPT_TYPE_STEP, 2479 BTC_RPT_TYPE_NULLSTA, 2480 BTC_RPT_TYPE_MREG, 2481 BTC_RPT_TYPE_GPIO_DBG, 2482 BTC_RPT_TYPE_BT_VER, 2483 BTC_RPT_TYPE_BT_SCAN, 2484 BTC_RPT_TYPE_BT_AFH, 2485 BTC_RPT_TYPE_BT_DEVICE, 2486 BTC_RPT_TYPE_TEST, 2487 BTC_RPT_TYPE_MAX = 31 2488 }; 2489 2490 enum rtw_btc_btf_reg_type { 2491 REG_MAC = 0x0, 2492 REG_BB = 0x1, 2493 REG_RF = 0x2, 2494 REG_BT_RF = 0x3, 2495 REG_BT_MODEM = 0x4, 2496 REG_BT_BLUEWIZE = 0x5, 2497 REG_BT_VENDOR = 0x6, 2498 REG_BT_LE = 0x7, 2499 REG_MAX_TYPE, 2500 }; 2501 2502 struct rtw89_btc_rpt_cmn_info { 2503 u32 rx_cnt; 2504 u32 rx_len; 2505 u32 req_len; /* expected rsp len */ 2506 u8 req_fver; /* expected rsp fver */ 2507 u8 rsp_fver; /* fver from fw */ 2508 u8 valid; 2509 } __packed; 2510 2511 union rtw89_btc_fbtc_btafh_info { 2512 struct rtw89_btc_fbtc_btafh v1; 2513 struct rtw89_btc_fbtc_btafh_v2 v2; 2514 }; 2515 2516 struct rtw89_btc_report_ctrl_state { 2517 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2518 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 2519 }; 2520 2521 struct rtw89_btc_rpt_fbtc_tdma { 2522 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2523 union rtw89_btc_fbtc_tdma_le32 finfo; 2524 }; 2525 2526 struct rtw89_btc_rpt_fbtc_slots { 2527 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2528 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 2529 }; 2530 2531 struct rtw89_btc_rpt_fbtc_cysta { 2532 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2533 union rtw89_btc_fbtc_cysta_info finfo; 2534 }; 2535 2536 struct rtw89_btc_rpt_fbtc_step { 2537 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2538 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 2539 }; 2540 2541 struct rtw89_btc_rpt_fbtc_nullsta { 2542 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2543 union rtw89_btc_fbtc_cynullsta_info finfo; 2544 }; 2545 2546 struct rtw89_btc_rpt_fbtc_mreg { 2547 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2548 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 2549 }; 2550 2551 struct rtw89_btc_rpt_fbtc_gpio_dbg { 2552 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2553 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 2554 }; 2555 2556 struct rtw89_btc_rpt_fbtc_btver { 2557 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2558 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 2559 }; 2560 2561 struct rtw89_btc_rpt_fbtc_btscan { 2562 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2563 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 2564 }; 2565 2566 struct rtw89_btc_rpt_fbtc_btafh { 2567 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2568 union rtw89_btc_fbtc_btafh_info finfo; 2569 }; 2570 2571 struct rtw89_btc_rpt_fbtc_btdev { 2572 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2573 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 2574 }; 2575 2576 enum rtw89_btc_btfre_type { 2577 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 2578 BTFRE_UNDEF_TYPE, 2579 BTFRE_EXCEPTION, 2580 BTFRE_MAX, 2581 }; 2582 2583 struct rtw89_btc_btf_fwinfo { 2584 u32 cnt_c2h; 2585 u32 cnt_h2c; 2586 u32 cnt_h2c_fail; 2587 u32 event[BTF_EVNT_MAX]; 2588 2589 u32 err[BTFRE_MAX]; 2590 u32 len_mismch; 2591 u32 fver_mismch; 2592 u32 rpt_en_map; 2593 2594 struct rtw89_btc_report_ctrl_state rpt_ctrl; 2595 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 2596 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 2597 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 2598 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 2599 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 2600 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 2601 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 2602 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 2603 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 2604 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 2605 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 2606 }; 2607 2608 struct rtw89_btc_ver { 2609 enum rtw89_core_chip_id chip_id; 2610 u32 fw_ver_code; 2611 2612 u8 fcxbtcrpt; 2613 u8 fcxtdma; 2614 u8 fcxslots; 2615 u8 fcxcysta; 2616 u8 fcxstep; 2617 u8 fcxnullsta; 2618 u8 fcxmreg; 2619 u8 fcxgpiodbg; 2620 u8 fcxbtver; 2621 u8 fcxbtscan; 2622 u8 fcxbtafh; 2623 u8 fcxbtdevinfo; 2624 u8 fwlrole; 2625 u8 frptmap; 2626 u8 fcxctrl; 2627 2628 u16 info_buf; 2629 u8 max_role_num; 2630 }; 2631 2632 #define RTW89_BTC_POLICY_MAXLEN 512 2633 2634 struct rtw89_btc { 2635 const struct rtw89_btc_ver *ver; 2636 2637 struct rtw89_btc_cx cx; 2638 struct rtw89_btc_dm dm; 2639 struct rtw89_btc_ctrl ctrl; 2640 struct rtw89_btc_module mdinfo; 2641 struct rtw89_btc_btf_fwinfo fwinfo; 2642 struct rtw89_btc_dbg dbg; 2643 2644 struct work_struct eapol_notify_work; 2645 struct work_struct arp_notify_work; 2646 struct work_struct dhcp_notify_work; 2647 struct work_struct icmp_notify_work; 2648 2649 u32 bt_req_len; 2650 2651 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 2652 u16 policy_len; 2653 u16 policy_type; 2654 bool bt_req_en; 2655 bool update_policy_force; 2656 bool lps; 2657 }; 2658 2659 enum rtw89_ra_mode { 2660 RTW89_RA_MODE_CCK = BIT(0), 2661 RTW89_RA_MODE_OFDM = BIT(1), 2662 RTW89_RA_MODE_HT = BIT(2), 2663 RTW89_RA_MODE_VHT = BIT(3), 2664 RTW89_RA_MODE_HE = BIT(4), 2665 }; 2666 2667 enum rtw89_ra_report_mode { 2668 RTW89_RA_RPT_MODE_LEGACY, 2669 RTW89_RA_RPT_MODE_HT, 2670 RTW89_RA_RPT_MODE_VHT, 2671 RTW89_RA_RPT_MODE_HE, 2672 }; 2673 2674 enum rtw89_dig_noisy_level { 2675 RTW89_DIG_NOISY_LEVEL0 = -1, 2676 RTW89_DIG_NOISY_LEVEL1 = 0, 2677 RTW89_DIG_NOISY_LEVEL2 = 1, 2678 RTW89_DIG_NOISY_LEVEL3 = 2, 2679 RTW89_DIG_NOISY_LEVEL_MAX = 3, 2680 }; 2681 2682 enum rtw89_gi_ltf { 2683 RTW89_GILTF_LGI_4XHE32 = 0, 2684 RTW89_GILTF_SGI_4XHE08 = 1, 2685 RTW89_GILTF_2XHE16 = 2, 2686 RTW89_GILTF_2XHE08 = 3, 2687 RTW89_GILTF_1XHE16 = 4, 2688 RTW89_GILTF_1XHE08 = 5, 2689 RTW89_GILTF_MAX 2690 }; 2691 2692 enum rtw89_rx_frame_type { 2693 RTW89_RX_TYPE_MGNT = 0, 2694 RTW89_RX_TYPE_CTRL = 1, 2695 RTW89_RX_TYPE_DATA = 2, 2696 RTW89_RX_TYPE_RSVD = 3, 2697 }; 2698 2699 struct rtw89_ra_info { 2700 u8 is_dis_ra:1; 2701 /* Bit0 : CCK 2702 * Bit1 : OFDM 2703 * Bit2 : HT 2704 * Bit3 : VHT 2705 * Bit4 : HE 2706 * Bit5 : EHT 2707 */ 2708 u8 mode_ctrl:6; 2709 u8 bw_cap:3; /* enum rtw89_bandwidth */ 2710 u8 macid; 2711 u8 dcm_cap:1; 2712 u8 er_cap:1; 2713 u8 init_rate_lv:2; 2714 u8 upd_all:1; 2715 u8 en_sgi:1; 2716 u8 ldpc_cap:1; 2717 u8 stbc_cap:1; 2718 u8 ss_num:3; 2719 u8 giltf:3; 2720 u8 upd_bw_nss_mask:1; 2721 u8 upd_mask:1; 2722 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 2723 /* BFee CSI */ 2724 u8 band_num; 2725 u8 ra_csi_rate_en:1; 2726 u8 fixed_csi_rate_en:1; 2727 u8 cr_tbl_sel:1; 2728 u8 fix_giltf_en:1; 2729 u8 fix_giltf:3; 2730 u8 rsvd2:1; 2731 u8 csi_mcs_ss_idx; 2732 u8 csi_mode:2; 2733 u8 csi_gi_ltf:3; 2734 u8 csi_bw:3; 2735 }; 2736 2737 #define RTW89_PPDU_MAX_USR 4 2738 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 2739 #define RTW89_PPDU_MAC_INFO_SIZE 8 2740 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 2741 2742 #define RTW89_MAX_RX_AGG_NUM 64 2743 #define RTW89_MAX_TX_AGG_NUM 128 2744 2745 struct rtw89_ampdu_params { 2746 u16 agg_num; 2747 bool amsdu; 2748 }; 2749 2750 struct rtw89_ra_report { 2751 struct rate_info txrate; 2752 u32 bit_rate; 2753 u16 hw_rate; 2754 bool might_fallback_legacy; 2755 }; 2756 2757 DECLARE_EWMA(rssi, 10, 16); 2758 DECLARE_EWMA(evm, 10, 16); 2759 DECLARE_EWMA(snr, 10, 16); 2760 2761 struct rtw89_ba_cam_entry { 2762 struct list_head list; 2763 u8 tid; 2764 }; 2765 2766 #define RTW89_MAX_ADDR_CAM_NUM 128 2767 #define RTW89_MAX_BSSID_CAM_NUM 20 2768 #define RTW89_MAX_SEC_CAM_NUM 128 2769 #define RTW89_MAX_BA_CAM_NUM 8 2770 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 2771 2772 struct rtw89_addr_cam_entry { 2773 u8 addr_cam_idx; 2774 u8 offset; 2775 u8 len; 2776 u8 valid : 1; 2777 u8 addr_mask : 6; 2778 u8 wapi : 1; 2779 u8 mask_sel : 2; 2780 u8 bssid_cam_idx: 6; 2781 2782 u8 sec_ent_mode; 2783 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 2784 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 2785 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 2786 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 2787 }; 2788 2789 struct rtw89_bssid_cam_entry { 2790 u8 bssid[ETH_ALEN]; 2791 u8 phy_idx; 2792 u8 bssid_cam_idx; 2793 u8 offset; 2794 u8 len; 2795 u8 valid : 1; 2796 u8 num; 2797 }; 2798 2799 struct rtw89_sec_cam_entry { 2800 u8 sec_cam_idx; 2801 u8 offset; 2802 u8 len; 2803 u8 type : 4; 2804 u8 ext_key : 1; 2805 u8 spp_mode : 1; 2806 /* 256 bits */ 2807 u8 key[32]; 2808 }; 2809 2810 struct rtw89_sta { 2811 u8 mac_id; 2812 bool disassoc; 2813 bool er_cap; 2814 struct rtw89_dev *rtwdev; 2815 struct rtw89_vif *rtwvif; 2816 struct rtw89_ra_info ra; 2817 struct rtw89_ra_report ra_report; 2818 int max_agg_wait; 2819 u8 prev_rssi; 2820 struct ewma_rssi avg_rssi; 2821 struct ewma_rssi rssi[RF_PATH_MAX]; 2822 struct ewma_snr avg_snr; 2823 struct ewma_evm evm_min[RF_PATH_MAX]; 2824 struct ewma_evm evm_max[RF_PATH_MAX]; 2825 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 2826 struct ieee80211_rx_status rx_status; 2827 u16 rx_hw_rate; 2828 __le32 htc_template; 2829 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 2830 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 2831 struct list_head ba_cam_list; 2832 struct sk_buff_head roc_queue; 2833 2834 bool use_cfg_mask; 2835 struct cfg80211_bitrate_mask mask; 2836 2837 bool cctl_tx_time; 2838 u32 ampdu_max_time:4; 2839 bool cctl_tx_retry_limit; 2840 u32 data_tx_cnt_lmt:6; 2841 }; 2842 2843 struct rtw89_efuse { 2844 bool valid; 2845 bool power_k_valid; 2846 u8 xtal_cap; 2847 u8 addr[ETH_ALEN]; 2848 u8 rfe_type; 2849 char country_code[2]; 2850 }; 2851 2852 struct rtw89_phy_rate_pattern { 2853 u64 ra_mask; 2854 u16 rate; 2855 u8 ra_mode; 2856 bool enable; 2857 }; 2858 2859 struct rtw89_tx_wait_info { 2860 struct rcu_head rcu_head; 2861 struct completion completion; 2862 bool tx_done; 2863 }; 2864 2865 struct rtw89_tx_skb_data { 2866 struct rtw89_tx_wait_info __rcu *wait; 2867 u8 hci_priv[]; 2868 }; 2869 2870 #define RTW89_ROC_IDLE_TIMEOUT 500 2871 #define RTW89_ROC_TX_TIMEOUT 30 2872 enum rtw89_roc_state { 2873 RTW89_ROC_IDLE, 2874 RTW89_ROC_NORMAL, 2875 RTW89_ROC_MGMT, 2876 }; 2877 2878 struct rtw89_roc { 2879 struct ieee80211_channel chan; 2880 struct delayed_work roc_work; 2881 enum ieee80211_roc_type type; 2882 enum rtw89_roc_state state; 2883 int duration; 2884 }; 2885 2886 #define RTW89_P2P_MAX_NOA_NUM 2 2887 2888 struct rtw89_vif { 2889 struct list_head list; 2890 struct rtw89_dev *rtwdev; 2891 struct rtw89_roc roc; 2892 enum rtw89_sub_entity_idx sub_entity_idx; 2893 enum rtw89_reg_6ghz_power reg_6ghz_power; 2894 2895 u8 mac_id; 2896 u8 port; 2897 u8 mac_addr[ETH_ALEN]; 2898 u8 bssid[ETH_ALEN]; 2899 u8 phy_idx; 2900 u8 mac_idx; 2901 u8 net_type; 2902 u8 wifi_role; 2903 u8 self_role; 2904 u8 wmm; 2905 u8 bcn_hit_cond; 2906 u8 hit_rule; 2907 u8 last_noa_nr; 2908 bool offchan; 2909 bool trigger; 2910 bool lsig_txop; 2911 u8 tgt_ind; 2912 u8 frm_tgt_ind; 2913 bool wowlan_pattern; 2914 bool wowlan_uc; 2915 bool wowlan_magic; 2916 bool is_hesta; 2917 bool last_a_ctrl; 2918 bool dyn_tb_bedge_en; 2919 u8 def_tri_idx; 2920 u32 tdls_peer; 2921 struct work_struct update_beacon_work; 2922 struct rtw89_addr_cam_entry addr_cam; 2923 struct rtw89_bssid_cam_entry bssid_cam; 2924 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 2925 struct rtw89_traffic_stats stats; 2926 struct rtw89_phy_rate_pattern rate_pattern; 2927 struct cfg80211_scan_request *scan_req; 2928 struct ieee80211_scan_ies *scan_ies; 2929 struct list_head general_pkt_list; 2930 }; 2931 2932 enum rtw89_lv1_rcvy_step { 2933 RTW89_LV1_RCVY_STEP_1, 2934 RTW89_LV1_RCVY_STEP_2, 2935 }; 2936 2937 struct rtw89_hci_ops { 2938 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 2939 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 2940 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 2941 void (*reset)(struct rtw89_dev *rtwdev); 2942 int (*start)(struct rtw89_dev *rtwdev); 2943 void (*stop)(struct rtw89_dev *rtwdev); 2944 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 2945 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 2946 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 2947 2948 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 2949 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 2950 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 2951 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 2952 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 2953 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 2954 2955 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 2956 int (*mac_post_init)(struct rtw89_dev *rtwdev); 2957 int (*deinit)(struct rtw89_dev *rtwdev); 2958 2959 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 2960 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 2961 void (*dump_err_status)(struct rtw89_dev *rtwdev); 2962 int (*napi_poll)(struct napi_struct *napi, int budget); 2963 2964 /* Deal with locks inside recovery_start and recovery_complete callbacks 2965 * by hci instance, and handle things which need to consider under SER. 2966 * e.g. turn on/off interrupts except for the one for halt notification. 2967 */ 2968 void (*recovery_start)(struct rtw89_dev *rtwdev); 2969 void (*recovery_complete)(struct rtw89_dev *rtwdev); 2970 2971 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 2972 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 2973 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 2974 int (*poll_txdma_ch)(struct rtw89_dev *rtwdev); 2975 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 2976 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 2977 void (*disable_intr)(struct rtw89_dev *rtwdev); 2978 void (*enable_intr)(struct rtw89_dev *rtwdev); 2979 int (*rst_bdram)(struct rtw89_dev *rtwdev); 2980 }; 2981 2982 struct rtw89_hci_info { 2983 const struct rtw89_hci_ops *ops; 2984 enum rtw89_hci_type type; 2985 u32 rpwm_addr; 2986 u32 cpwm_addr; 2987 bool paused; 2988 }; 2989 2990 struct rtw89_chip_ops { 2991 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 2992 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 2993 void (*bb_reset)(struct rtw89_dev *rtwdev, 2994 enum rtw89_phy_idx phy_idx); 2995 void (*bb_sethw)(struct rtw89_dev *rtwdev); 2996 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2997 u32 addr, u32 mask); 2998 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2999 u32 addr, u32 mask, u32 data); 3000 void (*set_channel)(struct rtw89_dev *rtwdev, 3001 const struct rtw89_chan *chan, 3002 enum rtw89_mac_idx mac_idx, 3003 enum rtw89_phy_idx phy_idx); 3004 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3005 struct rtw89_channel_help_params *p, 3006 const struct rtw89_chan *chan, 3007 enum rtw89_mac_idx mac_idx, 3008 enum rtw89_phy_idx phy_idx); 3009 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map); 3010 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3011 void (*fem_setup)(struct rtw89_dev *rtwdev); 3012 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3013 void (*rfk_init)(struct rtw89_dev *rtwdev); 3014 void (*rfk_channel)(struct rtw89_dev *rtwdev); 3015 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3016 enum rtw89_phy_idx phy_idx); 3017 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 3018 void (*rfk_track)(struct rtw89_dev *rtwdev); 3019 void (*power_trim)(struct rtw89_dev *rtwdev); 3020 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3021 const struct rtw89_chan *chan, 3022 enum rtw89_phy_idx phy_idx); 3023 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3024 enum rtw89_phy_idx phy_idx); 3025 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3026 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3027 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg); 3028 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3029 struct rtw89_rx_phy_ppdu *phy_ppdu, 3030 struct ieee80211_rx_status *status); 3031 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en); 3032 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3033 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3034 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3035 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3036 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3037 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3038 struct rtw89_rx_desc_info *desc_info, 3039 u8 *data, u32 data_offset); 3040 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3041 struct rtw89_tx_desc_info *desc_info, 3042 void *txdesc); 3043 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3044 struct rtw89_tx_desc_info *desc_info, 3045 void *txdesc); 3046 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3047 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3048 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3049 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3050 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3051 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3052 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3053 struct rtw89_vif *rtwvif, 3054 struct rtw89_sta *rtwsta); 3055 3056 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3057 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3058 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3059 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3060 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3061 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3062 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3063 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3064 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3065 }; 3066 3067 enum rtw89_dma_ch { 3068 RTW89_DMA_ACH0 = 0, 3069 RTW89_DMA_ACH1 = 1, 3070 RTW89_DMA_ACH2 = 2, 3071 RTW89_DMA_ACH3 = 3, 3072 RTW89_DMA_ACH4 = 4, 3073 RTW89_DMA_ACH5 = 5, 3074 RTW89_DMA_ACH6 = 6, 3075 RTW89_DMA_ACH7 = 7, 3076 RTW89_DMA_B0MG = 8, 3077 RTW89_DMA_B0HI = 9, 3078 RTW89_DMA_B1MG = 10, 3079 RTW89_DMA_B1HI = 11, 3080 RTW89_DMA_H2C = 12, 3081 RTW89_DMA_CH_NUM = 13 3082 }; 3083 3084 enum rtw89_qta_mode { 3085 RTW89_QTA_SCC, 3086 RTW89_QTA_DLFW, 3087 RTW89_QTA_WOW, 3088 3089 /* keep last */ 3090 RTW89_QTA_INVALID, 3091 }; 3092 3093 struct rtw89_hfc_ch_cfg { 3094 u16 min; 3095 u16 max; 3096 #define grp_0 0 3097 #define grp_1 1 3098 #define grp_num 2 3099 u8 grp; 3100 }; 3101 3102 struct rtw89_hfc_ch_info { 3103 u16 aval; 3104 u16 used; 3105 }; 3106 3107 struct rtw89_hfc_pub_cfg { 3108 u16 grp0; 3109 u16 grp1; 3110 u16 pub_max; 3111 u16 wp_thrd; 3112 }; 3113 3114 struct rtw89_hfc_pub_info { 3115 u16 g0_used; 3116 u16 g1_used; 3117 u16 g0_aval; 3118 u16 g1_aval; 3119 u16 pub_aval; 3120 u16 wp_aval; 3121 }; 3122 3123 struct rtw89_hfc_prec_cfg { 3124 u16 ch011_prec; 3125 u16 h2c_prec; 3126 u16 wp_ch07_prec; 3127 u16 wp_ch811_prec; 3128 u8 ch011_full_cond; 3129 u8 h2c_full_cond; 3130 u8 wp_ch07_full_cond; 3131 u8 wp_ch811_full_cond; 3132 }; 3133 3134 struct rtw89_hfc_param { 3135 bool en; 3136 bool h2c_en; 3137 u8 mode; 3138 const struct rtw89_hfc_ch_cfg *ch_cfg; 3139 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3140 struct rtw89_hfc_pub_cfg pub_cfg; 3141 struct rtw89_hfc_pub_info pub_info; 3142 struct rtw89_hfc_prec_cfg prec_cfg; 3143 }; 3144 3145 struct rtw89_hfc_param_ini { 3146 const struct rtw89_hfc_ch_cfg *ch_cfg; 3147 const struct rtw89_hfc_pub_cfg *pub_cfg; 3148 const struct rtw89_hfc_prec_cfg *prec_cfg; 3149 u8 mode; 3150 }; 3151 3152 struct rtw89_dle_size { 3153 u16 pge_size; 3154 u16 lnk_pge_num; 3155 u16 unlnk_pge_num; 3156 }; 3157 3158 struct rtw89_wde_quota { 3159 u16 hif; 3160 u16 wcpu; 3161 u16 pkt_in; 3162 u16 cpu_io; 3163 }; 3164 3165 struct rtw89_ple_quota { 3166 u16 cma0_tx; 3167 u16 cma1_tx; 3168 u16 c2h; 3169 u16 h2c; 3170 u16 wcpu; 3171 u16 mpdu_proc; 3172 u16 cma0_dma; 3173 u16 cma1_dma; 3174 u16 bb_rpt; 3175 u16 wd_rel; 3176 u16 cpu_io; 3177 u16 tx_rpt; 3178 }; 3179 3180 struct rtw89_dle_mem { 3181 enum rtw89_qta_mode mode; 3182 const struct rtw89_dle_size *wde_size; 3183 const struct rtw89_dle_size *ple_size; 3184 const struct rtw89_wde_quota *wde_min_qt; 3185 const struct rtw89_wde_quota *wde_max_qt; 3186 const struct rtw89_ple_quota *ple_min_qt; 3187 const struct rtw89_ple_quota *ple_max_qt; 3188 }; 3189 3190 struct rtw89_reg_def { 3191 u32 addr; 3192 u32 mask; 3193 }; 3194 3195 struct rtw89_reg2_def { 3196 u32 addr; 3197 u32 data; 3198 }; 3199 3200 struct rtw89_reg3_def { 3201 u32 addr; 3202 u32 mask; 3203 u32 data; 3204 }; 3205 3206 struct rtw89_reg5_def { 3207 u8 flag; /* recognized by parsers */ 3208 u8 path; 3209 u32 addr; 3210 u32 mask; 3211 u32 data; 3212 }; 3213 3214 struct rtw89_phy_table { 3215 const struct rtw89_reg2_def *regs; 3216 u32 n_regs; 3217 enum rtw89_rf_path rf_path; 3218 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3219 enum rtw89_rf_path rf_path, void *data); 3220 }; 3221 3222 struct rtw89_txpwr_table { 3223 const void *data; 3224 u32 size; 3225 void (*load)(struct rtw89_dev *rtwdev, 3226 const struct rtw89_txpwr_table *tbl); 3227 }; 3228 3229 struct rtw89_txpwr_rule_2ghz { 3230 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3231 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3232 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3233 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3234 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3235 }; 3236 3237 struct rtw89_txpwr_rule_5ghz { 3238 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3239 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3240 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3241 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3242 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3243 }; 3244 3245 struct rtw89_txpwr_rule_6ghz { 3246 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3247 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3248 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3249 [RTW89_6G_CH_NUM]; 3250 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3251 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3252 [RTW89_6G_CH_NUM]; 3253 }; 3254 3255 struct rtw89_rfe_parms { 3256 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3257 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3258 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3259 }; 3260 3261 struct rtw89_rfe_parms_conf { 3262 const struct rtw89_rfe_parms *rfe_parms; 3263 u8 rfe_type; 3264 }; 3265 3266 struct rtw89_page_regs { 3267 u32 hci_fc_ctrl; 3268 u32 ch_page_ctrl; 3269 u32 ach_page_ctrl; 3270 u32 ach_page_info; 3271 u32 pub_page_info3; 3272 u32 pub_page_ctrl1; 3273 u32 pub_page_ctrl2; 3274 u32 pub_page_info1; 3275 u32 pub_page_info2; 3276 u32 wp_page_ctrl1; 3277 u32 wp_page_ctrl2; 3278 u32 wp_page_info1; 3279 }; 3280 3281 struct rtw89_imr_info { 3282 u32 wdrls_imr_set; 3283 u32 wsec_imr_reg; 3284 u32 wsec_imr_set; 3285 u32 mpdu_tx_imr_set; 3286 u32 mpdu_rx_imr_set; 3287 u32 sta_sch_imr_set; 3288 u32 txpktctl_imr_b0_reg; 3289 u32 txpktctl_imr_b0_clr; 3290 u32 txpktctl_imr_b0_set; 3291 u32 txpktctl_imr_b1_reg; 3292 u32 txpktctl_imr_b1_clr; 3293 u32 txpktctl_imr_b1_set; 3294 u32 wde_imr_clr; 3295 u32 wde_imr_set; 3296 u32 ple_imr_clr; 3297 u32 ple_imr_set; 3298 u32 host_disp_imr_clr; 3299 u32 host_disp_imr_set; 3300 u32 cpu_disp_imr_clr; 3301 u32 cpu_disp_imr_set; 3302 u32 other_disp_imr_clr; 3303 u32 other_disp_imr_set; 3304 u32 bbrpt_com_err_imr_reg; 3305 u32 bbrpt_chinfo_err_imr_reg; 3306 u32 bbrpt_err_imr_set; 3307 u32 bbrpt_dfs_err_imr_reg; 3308 u32 ptcl_imr_clr; 3309 u32 ptcl_imr_set; 3310 u32 cdma_imr_0_reg; 3311 u32 cdma_imr_0_clr; 3312 u32 cdma_imr_0_set; 3313 u32 cdma_imr_1_reg; 3314 u32 cdma_imr_1_clr; 3315 u32 cdma_imr_1_set; 3316 u32 phy_intf_imr_reg; 3317 u32 phy_intf_imr_clr; 3318 u32 phy_intf_imr_set; 3319 u32 rmac_imr_reg; 3320 u32 rmac_imr_clr; 3321 u32 rmac_imr_set; 3322 u32 tmac_imr_reg; 3323 u32 tmac_imr_clr; 3324 u32 tmac_imr_set; 3325 }; 3326 3327 struct rtw89_xtal_info { 3328 u32 xcap_reg; 3329 u32 sc_xo_mask; 3330 u32 sc_xi_mask; 3331 }; 3332 3333 struct rtw89_rrsr_cfgs { 3334 struct rtw89_reg3_def ref_rate; 3335 struct rtw89_reg3_def rsc; 3336 }; 3337 3338 struct rtw89_dig_regs { 3339 u32 seg0_pd_reg; 3340 u32 pd_lower_bound_mask; 3341 u32 pd_spatial_reuse_en; 3342 struct rtw89_reg_def p0_lna_init; 3343 struct rtw89_reg_def p1_lna_init; 3344 struct rtw89_reg_def p0_tia_init; 3345 struct rtw89_reg_def p1_tia_init; 3346 struct rtw89_reg_def p0_rxb_init; 3347 struct rtw89_reg_def p1_rxb_init; 3348 struct rtw89_reg_def p0_p20_pagcugc_en; 3349 struct rtw89_reg_def p0_s20_pagcugc_en; 3350 struct rtw89_reg_def p1_p20_pagcugc_en; 3351 struct rtw89_reg_def p1_s20_pagcugc_en; 3352 }; 3353 3354 struct rtw89_phy_ul_tb_info { 3355 bool dyn_tb_tri_en; 3356 u8 def_if_bandedge; 3357 }; 3358 3359 struct rtw89_antdiv_stats { 3360 struct ewma_rssi cck_rssi_avg; 3361 struct ewma_rssi ofdm_rssi_avg; 3362 struct ewma_rssi non_legacy_rssi_avg; 3363 u16 pkt_cnt_cck; 3364 u16 pkt_cnt_ofdm; 3365 u16 pkt_cnt_non_legacy; 3366 u32 evm; 3367 }; 3368 3369 struct rtw89_antdiv_info { 3370 struct rtw89_antdiv_stats target_stats; 3371 struct rtw89_antdiv_stats main_stats; 3372 struct rtw89_antdiv_stats aux_stats; 3373 u8 training_count; 3374 u8 rssi_pre; 3375 bool get_stats; 3376 }; 3377 3378 struct rtw89_chip_info { 3379 enum rtw89_core_chip_id chip_id; 3380 enum rtw89_chip_gen chip_gen; 3381 const struct rtw89_chip_ops *ops; 3382 const char *fw_basename; 3383 u8 fw_format_max; 3384 bool try_ce_fw; 3385 u32 fifo_size; 3386 bool small_fifo_size; 3387 u32 dle_scc_rsvd_size; 3388 u16 max_amsdu_limit; 3389 bool dis_2g_40m_ul_ofdma; 3390 u32 rsvd_ple_ofst; 3391 const struct rtw89_hfc_param_ini *hfc_param_ini; 3392 const struct rtw89_dle_mem *dle_mem; 3393 u8 wde_qempty_acq_num; 3394 u8 wde_qempty_mgq_sel; 3395 u32 rf_base_addr[2]; 3396 u8 support_chanctx_num; 3397 u8 support_bands; 3398 bool support_bw160; 3399 bool support_unii4; 3400 bool support_ul_tb_ctrl; 3401 bool hw_sec_hdr; 3402 u8 rf_path_num; 3403 u8 tx_nss; 3404 u8 rx_nss; 3405 u8 acam_num; 3406 u8 bcam_num; 3407 u8 scam_num; 3408 u8 bacam_num; 3409 u8 bacam_dynamic_num; 3410 enum rtw89_bacam_ver bacam_ver; 3411 3412 u8 sec_ctrl_efuse_size; 3413 u32 physical_efuse_size; 3414 u32 logical_efuse_size; 3415 u32 limit_efuse_size; 3416 u32 dav_phy_efuse_size; 3417 u32 dav_log_efuse_size; 3418 u32 phycap_addr; 3419 u32 phycap_size; 3420 3421 const struct rtw89_pwr_cfg * const *pwr_on_seq; 3422 const struct rtw89_pwr_cfg * const *pwr_off_seq; 3423 const struct rtw89_phy_table *bb_table; 3424 const struct rtw89_phy_table *bb_gain_table; 3425 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 3426 const struct rtw89_phy_table *nctl_table; 3427 const struct rtw89_rfk_tbl *nctl_post_table; 3428 const struct rtw89_txpwr_table *byr_table; 3429 const struct rtw89_phy_dig_gain_table *dig_table; 3430 const struct rtw89_dig_regs *dig_regs; 3431 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 3432 3433 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 3434 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 3435 const struct rtw89_rfe_parms *dflt_parms; 3436 3437 u8 txpwr_factor_rf; 3438 u8 txpwr_factor_mac; 3439 3440 u32 para_ver; 3441 u32 wlcx_desired; 3442 u8 btcx_desired; 3443 u8 scbd; 3444 u8 mailbox; 3445 3446 u8 afh_guard_ch; 3447 const u8 *wl_rssi_thres; 3448 const u8 *bt_rssi_thres; 3449 u8 rssi_tol; 3450 3451 u8 mon_reg_num; 3452 const struct rtw89_btc_fbtc_mreg *mon_reg; 3453 u8 rf_para_ulink_num; 3454 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 3455 u8 rf_para_dlink_num; 3456 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 3457 u8 ps_mode_supported; 3458 u8 low_power_hci_modes; 3459 3460 u32 h2c_cctl_func_id; 3461 u32 hci_func_en_addr; 3462 u32 h2c_desc_size; 3463 u32 txwd_body_size; 3464 u32 h2c_ctrl_reg; 3465 const u32 *h2c_regs; 3466 struct rtw89_reg_def h2c_counter_reg; 3467 u32 c2h_ctrl_reg; 3468 const u32 *c2h_regs; 3469 struct rtw89_reg_def c2h_counter_reg; 3470 const struct rtw89_page_regs *page_regs; 3471 bool cfo_src_fd; 3472 bool cfo_hw_comp; 3473 const struct rtw89_reg_def *dcfo_comp; 3474 u8 dcfo_comp_sft; 3475 const struct rtw89_imr_info *imr_info; 3476 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 3477 u32 bss_clr_map_reg; 3478 u32 dma_ch_mask; 3479 u32 edcca_lvl_reg; 3480 const struct wiphy_wowlan_support *wowlan_stub; 3481 const struct rtw89_xtal_info *xtal_info; 3482 }; 3483 3484 union rtw89_bus_info { 3485 const struct rtw89_pci_info *pci; 3486 }; 3487 3488 struct rtw89_driver_info { 3489 const struct rtw89_chip_info *chip; 3490 union rtw89_bus_info bus; 3491 }; 3492 3493 enum rtw89_hcifc_mode { 3494 RTW89_HCIFC_POH = 0, 3495 RTW89_HCIFC_STF = 1, 3496 RTW89_HCIFC_SDIO = 2, 3497 3498 /* keep last */ 3499 RTW89_HCIFC_MODE_INVALID, 3500 }; 3501 3502 struct rtw89_dle_info { 3503 enum rtw89_qta_mode qta_mode; 3504 u16 ple_pg_size; 3505 u16 c0_rx_qta; 3506 u16 c1_rx_qta; 3507 }; 3508 3509 enum rtw89_host_rpr_mode { 3510 RTW89_RPR_MODE_POH = 0, 3511 RTW89_RPR_MODE_STF 3512 }; 3513 3514 #define RTW89_COMPLETION_BUF_SIZE 24 3515 #define RTW89_WAIT_COND_IDLE UINT_MAX 3516 3517 struct rtw89_completion_data { 3518 bool err; 3519 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 3520 }; 3521 3522 struct rtw89_wait_info { 3523 atomic_t cond; 3524 struct completion completion; 3525 struct rtw89_completion_data data; 3526 }; 3527 3528 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 3529 3530 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 3531 { 3532 init_completion(&wait->completion); 3533 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 3534 } 3535 3536 struct rtw89_mac_info { 3537 struct rtw89_dle_info dle_info; 3538 struct rtw89_hfc_param hfc_param; 3539 enum rtw89_qta_mode qta_mode; 3540 u8 rpwm_seq_num; 3541 u8 cpwm_seq_num; 3542 3543 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 3544 struct rtw89_wait_info fw_ofld_wait; 3545 }; 3546 3547 enum rtw89_fw_type { 3548 RTW89_FW_NORMAL = 1, 3549 RTW89_FW_WOWLAN = 3, 3550 RTW89_FW_NORMAL_CE = 5, 3551 }; 3552 3553 enum rtw89_fw_feature { 3554 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 3555 RTW89_FW_FEATURE_SCAN_OFFLOAD, 3556 RTW89_FW_FEATURE_TX_WAKE, 3557 RTW89_FW_FEATURE_CRASH_TRIGGER, 3558 RTW89_FW_FEATURE_NO_PACKET_DROP, 3559 RTW89_FW_FEATURE_NO_DEEP_PS, 3560 RTW89_FW_FEATURE_NO_LPS_PG, 3561 RTW89_FW_FEATURE_BEACON_FILTER, 3562 }; 3563 3564 struct rtw89_fw_suit { 3565 const u8 *data; 3566 u32 size; 3567 u8 major_ver; 3568 u8 minor_ver; 3569 u8 sub_ver; 3570 u8 sub_idex; 3571 u16 build_year; 3572 u16 build_mon; 3573 u16 build_date; 3574 u16 build_hour; 3575 u16 build_min; 3576 u8 cmd_ver; 3577 }; 3578 3579 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 3580 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 3581 #define RTW89_FW_SUIT_VER_CODE(s) \ 3582 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 3583 3584 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 3585 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 3586 (mfw_hdr)->ver.minor, \ 3587 (mfw_hdr)->ver.sub, \ 3588 (mfw_hdr)->ver.idx) 3589 3590 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 3591 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 3592 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 3593 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 3594 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 3595 3596 struct rtw89_fw_req_info { 3597 const struct firmware *firmware; 3598 struct completion completion; 3599 }; 3600 3601 struct rtw89_fw_info { 3602 struct rtw89_fw_req_info req; 3603 int fw_format; 3604 u8 h2c_seq; 3605 u8 rec_seq; 3606 u8 h2c_counter; 3607 u8 c2h_counter; 3608 struct rtw89_fw_suit normal; 3609 struct rtw89_fw_suit wowlan; 3610 bool fw_log_enable; 3611 u32 feature_map; 3612 }; 3613 3614 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 3615 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 3616 3617 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 3618 ((_fw)->feature_map |= BIT(_fw_feature)) 3619 3620 struct rtw89_cam_info { 3621 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 3622 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 3623 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 3624 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 3625 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 3626 }; 3627 3628 enum rtw89_sar_sources { 3629 RTW89_SAR_SOURCE_NONE, 3630 RTW89_SAR_SOURCE_COMMON, 3631 3632 RTW89_SAR_SOURCE_NR, 3633 }; 3634 3635 enum rtw89_sar_subband { 3636 RTW89_SAR_2GHZ_SUBBAND, 3637 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 3638 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 3639 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 3640 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 3641 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 3642 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 3643 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 3644 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 3645 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 3646 3647 RTW89_SAR_SUBBAND_NR, 3648 }; 3649 3650 struct rtw89_sar_cfg_common { 3651 bool set[RTW89_SAR_SUBBAND_NR]; 3652 s32 cfg[RTW89_SAR_SUBBAND_NR]; 3653 }; 3654 3655 struct rtw89_sar_info { 3656 /* used to decide how to acces SAR cfg union */ 3657 enum rtw89_sar_sources src; 3658 3659 /* reserved for different knids of SAR cfg struct. 3660 * supposed that a single cfg struct cannot handle various SAR sources. 3661 */ 3662 union { 3663 struct rtw89_sar_cfg_common cfg_common; 3664 }; 3665 }; 3666 3667 struct rtw89_chanctx_cfg { 3668 enum rtw89_sub_entity_idx idx; 3669 }; 3670 3671 enum rtw89_entity_mode { 3672 RTW89_ENTITY_MODE_SCC, 3673 }; 3674 3675 struct rtw89_sub_entity { 3676 struct cfg80211_chan_def chandef; 3677 struct rtw89_chan chan; 3678 struct rtw89_chan_rcd rcd; 3679 struct rtw89_chanctx_cfg *cfg; 3680 }; 3681 3682 struct rtw89_hal { 3683 u32 rx_fltr; 3684 u8 cv; 3685 u8 acv; 3686 u32 antenna_tx; 3687 u32 antenna_rx; 3688 u8 tx_nss; 3689 u8 rx_nss; 3690 bool tx_path_diversity; 3691 bool ant_diversity; 3692 bool ant_diversity_fixed; 3693 bool support_cckpd; 3694 bool support_igi; 3695 atomic_t roc_entity_idx; 3696 3697 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 3698 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY]; 3699 struct cfg80211_chan_def roc_chandef; 3700 3701 bool entity_active; 3702 enum rtw89_entity_mode entity_mode; 3703 3704 u32 edcca_bak; 3705 }; 3706 3707 #define RTW89_MAX_MAC_ID_NUM 128 3708 #define RTW89_MAX_PKT_OFLD_NUM 255 3709 3710 enum rtw89_flags { 3711 RTW89_FLAG_POWERON, 3712 RTW89_FLAG_FW_RDY, 3713 RTW89_FLAG_RUNNING, 3714 RTW89_FLAG_BFEE_MON, 3715 RTW89_FLAG_BFEE_EN, 3716 RTW89_FLAG_BFEE_TIMER_KEEP, 3717 RTW89_FLAG_NAPI_RUNNING, 3718 RTW89_FLAG_LEISURE_PS, 3719 RTW89_FLAG_LOW_POWER_MODE, 3720 RTW89_FLAG_INACTIVE_PS, 3721 RTW89_FLAG_CRASH_SIMULATING, 3722 RTW89_FLAG_SER_HANDLING, 3723 RTW89_FLAG_WOWLAN, 3724 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 3725 RTW89_FLAG_CHANGING_INTERFACE, 3726 3727 NUM_OF_RTW89_FLAGS, 3728 }; 3729 3730 enum rtw89_pkt_drop_sel { 3731 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 3732 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 3733 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 3734 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 3735 RTW89_PKT_DROP_SEL_MACID_ALL, 3736 RTW89_PKT_DROP_SEL_MG0_ONCE, 3737 RTW89_PKT_DROP_SEL_HIQ_ONCE, 3738 RTW89_PKT_DROP_SEL_HIQ_PORT, 3739 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 3740 RTW89_PKT_DROP_SEL_BAND, 3741 RTW89_PKT_DROP_SEL_BAND_ONCE, 3742 RTW89_PKT_DROP_SEL_REL_MACID, 3743 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 3744 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 3745 }; 3746 3747 struct rtw89_pkt_drop_params { 3748 enum rtw89_pkt_drop_sel sel; 3749 enum rtw89_mac_idx mac_band; 3750 u8 macid; 3751 u8 port; 3752 u8 mbssid; 3753 bool tf_trs; 3754 u32 macid_band_sel[4]; 3755 }; 3756 3757 struct rtw89_pkt_stat { 3758 u16 beacon_nr; 3759 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 3760 }; 3761 3762 DECLARE_EWMA(thermal, 4, 4); 3763 3764 struct rtw89_phy_stat { 3765 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 3766 struct rtw89_pkt_stat cur_pkt_stat; 3767 struct rtw89_pkt_stat last_pkt_stat; 3768 }; 3769 3770 #define RTW89_DACK_PATH_NR 2 3771 #define RTW89_DACK_IDX_NR 2 3772 #define RTW89_DACK_MSBK_NR 16 3773 struct rtw89_dack_info { 3774 bool dack_done; 3775 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 3776 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3777 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3778 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3779 u32 dack_cnt; 3780 bool addck_timeout[RTW89_DACK_PATH_NR]; 3781 bool dadck_timeout[RTW89_DACK_PATH_NR]; 3782 bool msbk_timeout[RTW89_DACK_PATH_NR]; 3783 }; 3784 3785 #define RTW89_IQK_CHS_NR 2 3786 #define RTW89_IQK_PATH_NR 4 3787 3788 struct rtw89_rfk_mcc_info { 3789 u8 ch[RTW89_IQK_CHS_NR]; 3790 u8 band[RTW89_IQK_CHS_NR]; 3791 u8 table_idx; 3792 }; 3793 3794 struct rtw89_lck_info { 3795 u8 thermal[RF_PATH_MAX]; 3796 }; 3797 3798 struct rtw89_rx_dck_info { 3799 u8 thermal[RF_PATH_MAX]; 3800 }; 3801 3802 struct rtw89_iqk_info { 3803 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3804 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3805 bool lok_fail[RTW89_IQK_PATH_NR]; 3806 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3807 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3808 u32 iqk_fail_cnt; 3809 bool is_iqk_init; 3810 u32 iqk_channel[RTW89_IQK_CHS_NR]; 3811 u8 iqk_band[RTW89_IQK_PATH_NR]; 3812 u8 iqk_ch[RTW89_IQK_PATH_NR]; 3813 u8 iqk_bw[RTW89_IQK_PATH_NR]; 3814 u8 iqk_times; 3815 u8 version; 3816 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 3817 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 3818 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 3819 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 3820 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 3821 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 3822 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 3823 bool is_nbiqk; 3824 bool iqk_fft_en; 3825 bool iqk_xym_en; 3826 bool iqk_sram_en; 3827 bool iqk_cfir_en; 3828 u32 syn1to2; 3829 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3830 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 3831 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3832 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3833 }; 3834 3835 #define RTW89_DPK_RF_PATH 2 3836 #define RTW89_DPK_AVG_THERMAL_NUM 8 3837 #define RTW89_DPK_BKUP_NUM 2 3838 struct rtw89_dpk_bkup_para { 3839 enum rtw89_band band; 3840 enum rtw89_bandwidth bw; 3841 u8 ch; 3842 bool path_ok; 3843 u8 mdpd_en; 3844 u8 txagc_dpk; 3845 u8 ther_dpk; 3846 u8 gs; 3847 u16 pwsf; 3848 }; 3849 3850 struct rtw89_dpk_info { 3851 bool is_dpk_enable; 3852 bool is_dpk_reload_en; 3853 u8 dpk_gs[RTW89_PHY_MAX]; 3854 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3855 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3856 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3857 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3858 u8 cur_idx[RTW89_DPK_RF_PATH]; 3859 u8 cur_k_set; 3860 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3861 }; 3862 3863 struct rtw89_fem_info { 3864 bool elna_2g; 3865 bool elna_5g; 3866 bool epa_2g; 3867 bool epa_5g; 3868 bool epa_6g; 3869 }; 3870 3871 struct rtw89_phy_ch_info { 3872 u8 rssi_min; 3873 u16 rssi_min_macid; 3874 u8 pre_rssi_min; 3875 u8 rssi_max; 3876 u16 rssi_max_macid; 3877 u8 rxsc_160; 3878 u8 rxsc_80; 3879 u8 rxsc_40; 3880 u8 rxsc_20; 3881 u8 rxsc_l; 3882 u8 is_noisy; 3883 }; 3884 3885 struct rtw89_agc_gaincode_set { 3886 u8 lna_idx; 3887 u8 tia_idx; 3888 u8 rxb_idx; 3889 }; 3890 3891 #define IGI_RSSI_TH_NUM 5 3892 #define FA_TH_NUM 4 3893 #define LNA_GAIN_NUM 7 3894 #define TIA_GAIN_NUM 2 3895 struct rtw89_dig_info { 3896 struct rtw89_agc_gaincode_set cur_gaincode; 3897 bool force_gaincode_idx_en; 3898 struct rtw89_agc_gaincode_set force_gaincode; 3899 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 3900 u16 fa_th[FA_TH_NUM]; 3901 u8 igi_rssi; 3902 u8 igi_fa_rssi; 3903 u8 fa_rssi_ofst; 3904 u8 dyn_igi_max; 3905 u8 dyn_igi_min; 3906 bool dyn_pd_th_en; 3907 u8 dyn_pd_th_max; 3908 u8 pd_low_th_ofst; 3909 u8 ib_pbk; 3910 s8 ib_pkpwr; 3911 s8 lna_gain_a[LNA_GAIN_NUM]; 3912 s8 lna_gain_g[LNA_GAIN_NUM]; 3913 s8 *lna_gain; 3914 s8 tia_gain_a[TIA_GAIN_NUM]; 3915 s8 tia_gain_g[TIA_GAIN_NUM]; 3916 s8 *tia_gain; 3917 bool is_linked_pre; 3918 bool bypass_dig; 3919 }; 3920 3921 enum rtw89_multi_cfo_mode { 3922 RTW89_PKT_BASED_AVG_MODE = 0, 3923 RTW89_ENTRY_BASED_AVG_MODE = 1, 3924 RTW89_TP_BASED_AVG_MODE = 2, 3925 }; 3926 3927 enum rtw89_phy_cfo_status { 3928 RTW89_PHY_DCFO_STATE_NORMAL = 0, 3929 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 3930 RTW89_PHY_DCFO_STATE_HOLD = 2, 3931 RTW89_PHY_DCFO_STATE_MAX 3932 }; 3933 3934 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 3935 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 3936 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 3937 }; 3938 3939 struct rtw89_cfo_tracking_info { 3940 u16 cfo_timer_ms; 3941 bool cfo_trig_by_timer_en; 3942 enum rtw89_phy_cfo_status phy_cfo_status; 3943 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 3944 u8 phy_cfo_trk_cnt; 3945 bool is_adjust; 3946 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 3947 bool apply_compensation; 3948 u8 crystal_cap; 3949 u8 crystal_cap_default; 3950 u8 def_x_cap; 3951 s8 x_cap_ofst; 3952 u32 sta_cfo_tolerance; 3953 s32 cfo_tail[CFO_TRACK_MAX_USER]; 3954 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 3955 s32 cfo_avg_pre; 3956 s32 cfo_avg[CFO_TRACK_MAX_USER]; 3957 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 3958 s32 dcfo_avg; 3959 s32 dcfo_avg_pre; 3960 u32 packet_count; 3961 u32 packet_count_pre; 3962 s32 residual_cfo_acc; 3963 u8 phy_cfotrk_state; 3964 u8 phy_cfotrk_cnt; 3965 bool divergence_lock_en; 3966 u8 x_cap_lb; 3967 u8 x_cap_ub; 3968 u8 lock_cnt; 3969 }; 3970 3971 enum rtw89_tssi_alimk_band { 3972 TSSI_ALIMK_2G = 0, 3973 TSSI_ALIMK_5GL, 3974 TSSI_ALIMK_5GM, 3975 TSSI_ALIMK_5GH, 3976 TSSI_ALIMK_MAX 3977 }; 3978 3979 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 3980 #define TSSI_TRIM_CH_GROUP_NUM 8 3981 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 3982 3983 #define TSSI_CCK_CH_GROUP_NUM 6 3984 #define TSSI_MCS_2G_CH_GROUP_NUM 5 3985 #define TSSI_MCS_5G_CH_GROUP_NUM 14 3986 #define TSSI_MCS_6G_CH_GROUP_NUM 32 3987 #define TSSI_MCS_CH_GROUP_NUM \ 3988 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 3989 #define TSSI_MAX_CH_NUM 67 3990 #define TSSI_ALIMK_VALUE_NUM 8 3991 3992 struct rtw89_tssi_info { 3993 u8 thermal[RF_PATH_MAX]; 3994 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 3995 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 3996 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 3997 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 3998 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 3999 s8 extra_ofst[RF_PATH_MAX]; 4000 bool tssi_tracking_check[RF_PATH_MAX]; 4001 u8 default_txagc_offset[RF_PATH_MAX]; 4002 u32 base_thermal[RF_PATH_MAX]; 4003 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 4004 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 4005 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 4006 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 4007 u32 tssi_alimk_time; 4008 }; 4009 4010 struct rtw89_power_trim_info { 4011 bool pg_thermal_trim; 4012 bool pg_pa_bias_trim; 4013 u8 thermal_trim[RF_PATH_MAX]; 4014 u8 pa_bias_trim[RF_PATH_MAX]; 4015 }; 4016 4017 struct rtw89_regd { 4018 char alpha2[3]; 4019 u8 txpwr_regd[RTW89_BAND_NUM]; 4020 }; 4021 4022 struct rtw89_regulatory_info { 4023 const struct rtw89_regd *regd; 4024 enum rtw89_reg_6ghz_power reg_6ghz_power; 4025 }; 4026 4027 enum rtw89_ifs_clm_application { 4028 RTW89_IFS_CLM_INIT = 0, 4029 RTW89_IFS_CLM_BACKGROUND = 1, 4030 RTW89_IFS_CLM_ACS = 2, 4031 RTW89_IFS_CLM_DIG = 3, 4032 RTW89_IFS_CLM_TDMA_DIG = 4, 4033 RTW89_IFS_CLM_DBG = 5, 4034 RTW89_IFS_CLM_DBG_MANUAL = 6 4035 }; 4036 4037 enum rtw89_env_racing_lv { 4038 RTW89_RAC_RELEASE = 0, 4039 RTW89_RAC_LV_1 = 1, 4040 RTW89_RAC_LV_2 = 2, 4041 RTW89_RAC_LV_3 = 3, 4042 RTW89_RAC_LV_4 = 4, 4043 RTW89_RAC_MAX_NUM = 5 4044 }; 4045 4046 struct rtw89_ccx_para_info { 4047 enum rtw89_env_racing_lv rac_lv; 4048 u16 mntr_time; 4049 u8 nhm_manual_th_ofst; 4050 u8 nhm_manual_th0; 4051 enum rtw89_ifs_clm_application ifs_clm_app; 4052 u32 ifs_clm_manual_th_times; 4053 u32 ifs_clm_manual_th0; 4054 u8 fahm_manual_th_ofst; 4055 u8 fahm_manual_th0; 4056 u8 fahm_numer_opt; 4057 u8 fahm_denom_opt; 4058 }; 4059 4060 enum rtw89_ccx_edcca_opt_sc_idx { 4061 RTW89_CCX_EDCCA_SEG0_P0 = 0, 4062 RTW89_CCX_EDCCA_SEG0_S1 = 1, 4063 RTW89_CCX_EDCCA_SEG0_S2 = 2, 4064 RTW89_CCX_EDCCA_SEG0_S3 = 3, 4065 RTW89_CCX_EDCCA_SEG1_P0 = 4, 4066 RTW89_CCX_EDCCA_SEG1_S1 = 5, 4067 RTW89_CCX_EDCCA_SEG1_S2 = 6, 4068 RTW89_CCX_EDCCA_SEG1_S3 = 7 4069 }; 4070 4071 enum rtw89_ccx_edcca_opt_bw_idx { 4072 RTW89_CCX_EDCCA_BW20_0 = 0, 4073 RTW89_CCX_EDCCA_BW20_1 = 1, 4074 RTW89_CCX_EDCCA_BW20_2 = 2, 4075 RTW89_CCX_EDCCA_BW20_3 = 3, 4076 RTW89_CCX_EDCCA_BW20_4 = 4, 4077 RTW89_CCX_EDCCA_BW20_5 = 5, 4078 RTW89_CCX_EDCCA_BW20_6 = 6, 4079 RTW89_CCX_EDCCA_BW20_7 = 7 4080 }; 4081 4082 #define RTW89_NHM_TH_NUM 11 4083 #define RTW89_FAHM_TH_NUM 11 4084 #define RTW89_NHM_RPT_NUM 12 4085 #define RTW89_FAHM_RPT_NUM 12 4086 #define RTW89_IFS_CLM_NUM 4 4087 struct rtw89_env_monitor_info { 4088 u8 ccx_watchdog_result; 4089 bool ccx_ongoing; 4090 u8 ccx_rac_lv; 4091 bool ccx_manual_ctrl; 4092 u16 ifs_clm_mntr_time; 4093 enum rtw89_ifs_clm_application ifs_clm_app; 4094 u16 ccx_period; 4095 u8 ccx_unit_idx; 4096 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 4097 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 4098 u16 ifs_clm_tx; 4099 u16 ifs_clm_edcca_excl_cca; 4100 u16 ifs_clm_ofdmfa; 4101 u16 ifs_clm_ofdmcca_excl_fa; 4102 u16 ifs_clm_cckfa; 4103 u16 ifs_clm_cckcca_excl_fa; 4104 u16 ifs_clm_total_ifs; 4105 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 4106 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 4107 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 4108 u8 ifs_clm_tx_ratio; 4109 u8 ifs_clm_edcca_excl_cca_ratio; 4110 u8 ifs_clm_cck_fa_ratio; 4111 u8 ifs_clm_ofdm_fa_ratio; 4112 u8 ifs_clm_cck_cca_excl_fa_ratio; 4113 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 4114 u16 ifs_clm_cck_fa_permil; 4115 u16 ifs_clm_ofdm_fa_permil; 4116 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 4117 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 4118 }; 4119 4120 enum rtw89_ser_rcvy_step { 4121 RTW89_SER_DRV_STOP_TX, 4122 RTW89_SER_DRV_STOP_RX, 4123 RTW89_SER_DRV_STOP_RUN, 4124 RTW89_SER_HAL_STOP_DMA, 4125 RTW89_SER_SUPPRESS_LOG, 4126 RTW89_NUM_OF_SER_FLAGS 4127 }; 4128 4129 struct rtw89_ser { 4130 u8 state; 4131 u8 alarm_event; 4132 bool prehandle_l1; 4133 4134 struct work_struct ser_hdl_work; 4135 struct delayed_work ser_alarm_work; 4136 const struct state_ent *st_tbl; 4137 const struct event_ent *ev_tbl; 4138 struct list_head msg_q; 4139 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 4140 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 4141 }; 4142 4143 enum rtw89_mac_ax_ps_mode { 4144 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 4145 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 4146 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 4147 RTW89_MAC_AX_PS_MODE_MAX = 3, 4148 }; 4149 4150 enum rtw89_last_rpwm_mode { 4151 RTW89_LAST_RPWM_PS = 0x0, 4152 RTW89_LAST_RPWM_ACTIVE = 0x6, 4153 }; 4154 4155 struct rtw89_lps_parm { 4156 u8 macid; 4157 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 4158 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 4159 }; 4160 4161 struct rtw89_ppdu_sts_info { 4162 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 4163 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 4164 }; 4165 4166 struct rtw89_early_h2c { 4167 struct list_head list; 4168 u8 *h2c; 4169 u16 h2c_len; 4170 }; 4171 4172 struct rtw89_hw_scan_info { 4173 struct ieee80211_vif *scanning_vif; 4174 struct list_head pkt_list[NUM_NL80211_BANDS]; 4175 struct rtw89_chan op_chan; 4176 u32 last_chan_idx; 4177 }; 4178 4179 enum rtw89_phy_bb_gain_band { 4180 RTW89_BB_GAIN_BAND_2G = 0, 4181 RTW89_BB_GAIN_BAND_5G_L = 1, 4182 RTW89_BB_GAIN_BAND_5G_M = 2, 4183 RTW89_BB_GAIN_BAND_5G_H = 3, 4184 RTW89_BB_GAIN_BAND_6G_L = 4, 4185 RTW89_BB_GAIN_BAND_6G_M = 5, 4186 RTW89_BB_GAIN_BAND_6G_H = 6, 4187 RTW89_BB_GAIN_BAND_6G_UH = 7, 4188 4189 RTW89_BB_GAIN_BAND_NR, 4190 }; 4191 4192 enum rtw89_phy_bb_rxsc_num { 4193 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 4194 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 4195 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 4196 }; 4197 4198 struct rtw89_phy_bb_gain_info { 4199 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4200 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 4201 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4202 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4203 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4204 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 4205 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 4206 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4207 [RTW89_BB_RXSC_NUM_40]; 4208 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4209 [RTW89_BB_RXSC_NUM_80]; 4210 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4211 [RTW89_BB_RXSC_NUM_160]; 4212 }; 4213 4214 struct rtw89_phy_efuse_gain { 4215 bool offset_valid; 4216 bool comp_valid; 4217 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 4218 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 4219 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 4220 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 4221 }; 4222 4223 #define RTW89_MAX_PATTERN_NUM 18 4224 #define RTW89_MAX_PATTERN_MASK_SIZE 4 4225 #define RTW89_MAX_PATTERN_SIZE 128 4226 4227 struct rtw89_wow_cam_info { 4228 bool r_w; 4229 u8 idx; 4230 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 4231 u16 crc; 4232 bool negative_pattern_match; 4233 bool skip_mac_hdr; 4234 bool uc; 4235 bool mc; 4236 bool bc; 4237 bool valid; 4238 }; 4239 4240 struct rtw89_wow_param { 4241 struct ieee80211_vif *wow_vif; 4242 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 4243 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 4244 u8 pattern_cnt; 4245 }; 4246 4247 struct rtw89_mcc_info { 4248 struct rtw89_wait_info wait; 4249 }; 4250 4251 struct rtw89_dev { 4252 struct ieee80211_hw *hw; 4253 struct device *dev; 4254 const struct ieee80211_ops *ops; 4255 4256 bool dbcc_en; 4257 struct rtw89_hw_scan_info scan_info; 4258 const struct rtw89_chip_info *chip; 4259 const struct rtw89_pci_info *pci_info; 4260 const struct rtw89_rfe_parms *rfe_parms; 4261 struct rtw89_hal hal; 4262 struct rtw89_mcc_info mcc; 4263 struct rtw89_mac_info mac; 4264 struct rtw89_fw_info fw; 4265 struct rtw89_hci_info hci; 4266 struct rtw89_efuse efuse; 4267 struct rtw89_traffic_stats stats; 4268 4269 /* ensures exclusive access from mac80211 callbacks */ 4270 struct mutex mutex; 4271 struct list_head rtwvifs_list; 4272 /* used to protect rf read write */ 4273 struct mutex rf_mutex; 4274 struct workqueue_struct *txq_wq; 4275 struct work_struct txq_work; 4276 struct delayed_work txq_reinvoke_work; 4277 /* used to protect ba_list and forbid_ba_list */ 4278 spinlock_t ba_lock; 4279 /* txqs to setup ba session */ 4280 struct list_head ba_list; 4281 /* txqs to forbid ba session */ 4282 struct list_head forbid_ba_list; 4283 struct work_struct ba_work; 4284 /* used to protect rpwm */ 4285 spinlock_t rpwm_lock; 4286 4287 struct rtw89_cam_info cam_info; 4288 4289 struct sk_buff_head c2h_queue; 4290 struct work_struct c2h_work; 4291 struct work_struct ips_work; 4292 struct work_struct load_firmware_work; 4293 struct work_struct cancel_6ghz_probe_work; 4294 4295 struct list_head early_h2c_list; 4296 4297 struct rtw89_ser ser; 4298 4299 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 4300 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 4301 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 4302 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 4303 4304 struct rtw89_phy_stat phystat; 4305 struct rtw89_dack_info dack; 4306 struct rtw89_iqk_info iqk; 4307 struct rtw89_dpk_info dpk; 4308 struct rtw89_rfk_mcc_info rfk_mcc; 4309 struct rtw89_lck_info lck; 4310 struct rtw89_rx_dck_info rx_dck; 4311 bool is_tssi_mode[RF_PATH_MAX]; 4312 bool is_bt_iqk_timeout; 4313 4314 struct rtw89_fem_info fem; 4315 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM]; 4316 struct rtw89_tssi_info tssi; 4317 struct rtw89_power_trim_info pwr_trim; 4318 4319 struct rtw89_cfo_tracking_info cfo_tracking; 4320 struct rtw89_env_monitor_info env_monitor; 4321 struct rtw89_dig_info dig; 4322 struct rtw89_phy_ch_info ch_info; 4323 struct rtw89_phy_bb_gain_info bb_gain; 4324 struct rtw89_phy_efuse_gain efuse_gain; 4325 struct rtw89_phy_ul_tb_info ul_tb_info; 4326 struct rtw89_antdiv_info antdiv; 4327 4328 struct delayed_work track_work; 4329 struct delayed_work coex_act1_work; 4330 struct delayed_work coex_bt_devinfo_work; 4331 struct delayed_work coex_rfk_chk_work; 4332 struct delayed_work cfo_track_work; 4333 struct delayed_work forbid_ba_work; 4334 struct delayed_work roc_work; 4335 struct delayed_work antdiv_work; 4336 struct rtw89_ppdu_sts_info ppdu_sts; 4337 u8 total_sta_assoc; 4338 bool scanning; 4339 4340 struct rtw89_regulatory_info regulatory; 4341 struct rtw89_sar_info sar; 4342 4343 struct rtw89_btc btc; 4344 enum rtw89_ps_mode ps_mode; 4345 bool lps_enabled; 4346 4347 struct rtw89_wow_param wow; 4348 4349 /* napi structure */ 4350 struct net_device netdev; 4351 struct napi_struct napi; 4352 int napi_budget_countdown; 4353 4354 /* HCI related data, keep last */ 4355 u8 priv[] __aligned(sizeof(void *)); 4356 }; 4357 4358 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 4359 struct rtw89_core_tx_request *tx_req) 4360 { 4361 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 4362 } 4363 4364 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 4365 { 4366 rtwdev->hci.ops->reset(rtwdev); 4367 } 4368 4369 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 4370 { 4371 return rtwdev->hci.ops->start(rtwdev); 4372 } 4373 4374 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 4375 { 4376 rtwdev->hci.ops->stop(rtwdev); 4377 } 4378 4379 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 4380 { 4381 return rtwdev->hci.ops->deinit(rtwdev); 4382 } 4383 4384 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 4385 { 4386 rtwdev->hci.ops->pause(rtwdev, pause); 4387 } 4388 4389 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 4390 { 4391 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 4392 } 4393 4394 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 4395 { 4396 rtwdev->hci.ops->recalc_int_mit(rtwdev); 4397 } 4398 4399 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 4400 { 4401 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 4402 } 4403 4404 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 4405 { 4406 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 4407 } 4408 4409 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 4410 bool drop) 4411 { 4412 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4413 return; 4414 4415 if (rtwdev->hci.ops->flush_queues) 4416 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 4417 } 4418 4419 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 4420 { 4421 if (rtwdev->hci.ops->recovery_start) 4422 rtwdev->hci.ops->recovery_start(rtwdev); 4423 } 4424 4425 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 4426 { 4427 if (rtwdev->hci.ops->recovery_complete) 4428 rtwdev->hci.ops->recovery_complete(rtwdev); 4429 } 4430 4431 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 4432 { 4433 if (rtwdev->hci.ops->enable_intr) 4434 rtwdev->hci.ops->enable_intr(rtwdev); 4435 } 4436 4437 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 4438 { 4439 if (rtwdev->hci.ops->disable_intr) 4440 rtwdev->hci.ops->disable_intr(rtwdev); 4441 } 4442 4443 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 4444 { 4445 if (rtwdev->hci.ops->ctrl_txdma_ch) 4446 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 4447 } 4448 4449 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 4450 { 4451 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 4452 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 4453 } 4454 4455 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 4456 { 4457 if (rtwdev->hci.ops->ctrl_trxhci) 4458 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 4459 } 4460 4461 static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev) 4462 { 4463 int ret = 0; 4464 4465 if (rtwdev->hci.ops->poll_txdma_ch) 4466 ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev); 4467 return ret; 4468 } 4469 4470 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 4471 { 4472 if (rtwdev->hci.ops->clr_idx_all) 4473 rtwdev->hci.ops->clr_idx_all(rtwdev); 4474 } 4475 4476 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 4477 { 4478 int ret = 0; 4479 4480 if (rtwdev->hci.ops->rst_bdram) 4481 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 4482 return ret; 4483 } 4484 4485 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 4486 { 4487 if (rtwdev->hci.ops->clear) 4488 rtwdev->hci.ops->clear(rtwdev, pdev); 4489 } 4490 4491 static inline 4492 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 4493 { 4494 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 4495 4496 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 4497 } 4498 4499 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 4500 { 4501 return rtwdev->hci.ops->read8(rtwdev, addr); 4502 } 4503 4504 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 4505 { 4506 return rtwdev->hci.ops->read16(rtwdev, addr); 4507 } 4508 4509 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 4510 { 4511 return rtwdev->hci.ops->read32(rtwdev, addr); 4512 } 4513 4514 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 4515 { 4516 rtwdev->hci.ops->write8(rtwdev, addr, data); 4517 } 4518 4519 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 4520 { 4521 rtwdev->hci.ops->write16(rtwdev, addr, data); 4522 } 4523 4524 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 4525 { 4526 rtwdev->hci.ops->write32(rtwdev, addr, data); 4527 } 4528 4529 static inline void 4530 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 4531 { 4532 u8 val; 4533 4534 val = rtw89_read8(rtwdev, addr); 4535 rtw89_write8(rtwdev, addr, val | bit); 4536 } 4537 4538 static inline void 4539 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 4540 { 4541 u16 val; 4542 4543 val = rtw89_read16(rtwdev, addr); 4544 rtw89_write16(rtwdev, addr, val | bit); 4545 } 4546 4547 static inline void 4548 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 4549 { 4550 u32 val; 4551 4552 val = rtw89_read32(rtwdev, addr); 4553 rtw89_write32(rtwdev, addr, val | bit); 4554 } 4555 4556 static inline void 4557 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 4558 { 4559 u8 val; 4560 4561 val = rtw89_read8(rtwdev, addr); 4562 rtw89_write8(rtwdev, addr, val & ~bit); 4563 } 4564 4565 static inline void 4566 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 4567 { 4568 u16 val; 4569 4570 val = rtw89_read16(rtwdev, addr); 4571 rtw89_write16(rtwdev, addr, val & ~bit); 4572 } 4573 4574 static inline void 4575 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 4576 { 4577 u32 val; 4578 4579 val = rtw89_read32(rtwdev, addr); 4580 rtw89_write32(rtwdev, addr, val & ~bit); 4581 } 4582 4583 static inline u32 4584 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4585 { 4586 u32 shift = __ffs(mask); 4587 u32 orig; 4588 u32 ret; 4589 4590 orig = rtw89_read32(rtwdev, addr); 4591 ret = (orig & mask) >> shift; 4592 4593 return ret; 4594 } 4595 4596 static inline u16 4597 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4598 { 4599 u32 shift = __ffs(mask); 4600 u32 orig; 4601 u32 ret; 4602 4603 orig = rtw89_read16(rtwdev, addr); 4604 ret = (orig & mask) >> shift; 4605 4606 return ret; 4607 } 4608 4609 static inline u8 4610 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4611 { 4612 u32 shift = __ffs(mask); 4613 u32 orig; 4614 u32 ret; 4615 4616 orig = rtw89_read8(rtwdev, addr); 4617 ret = (orig & mask) >> shift; 4618 4619 return ret; 4620 } 4621 4622 static inline void 4623 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 4624 { 4625 u32 shift = __ffs(mask); 4626 u32 orig; 4627 u32 set; 4628 4629 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 4630 4631 orig = rtw89_read32(rtwdev, addr); 4632 set = (orig & ~mask) | ((data << shift) & mask); 4633 rtw89_write32(rtwdev, addr, set); 4634 } 4635 4636 static inline void 4637 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 4638 { 4639 u32 shift; 4640 u16 orig, set; 4641 4642 mask &= 0xffff; 4643 shift = __ffs(mask); 4644 4645 orig = rtw89_read16(rtwdev, addr); 4646 set = (orig & ~mask) | ((data << shift) & mask); 4647 rtw89_write16(rtwdev, addr, set); 4648 } 4649 4650 static inline void 4651 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 4652 { 4653 u32 shift; 4654 u8 orig, set; 4655 4656 mask &= 0xff; 4657 shift = __ffs(mask); 4658 4659 orig = rtw89_read8(rtwdev, addr); 4660 set = (orig & ~mask) | ((data << shift) & mask); 4661 rtw89_write8(rtwdev, addr, set); 4662 } 4663 4664 static inline u32 4665 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 4666 u32 addr, u32 mask) 4667 { 4668 u32 val; 4669 4670 mutex_lock(&rtwdev->rf_mutex); 4671 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 4672 mutex_unlock(&rtwdev->rf_mutex); 4673 4674 return val; 4675 } 4676 4677 static inline void 4678 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 4679 u32 addr, u32 mask, u32 data) 4680 { 4681 mutex_lock(&rtwdev->rf_mutex); 4682 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 4683 mutex_unlock(&rtwdev->rf_mutex); 4684 } 4685 4686 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 4687 { 4688 void *p = rtwtxq; 4689 4690 return container_of(p, struct ieee80211_txq, drv_priv); 4691 } 4692 4693 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 4694 struct ieee80211_txq *txq) 4695 { 4696 struct rtw89_txq *rtwtxq; 4697 4698 if (!txq) 4699 return; 4700 4701 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 4702 INIT_LIST_HEAD(&rtwtxq->list); 4703 } 4704 4705 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 4706 { 4707 void *p = rtwvif; 4708 4709 return container_of(p, struct ieee80211_vif, drv_priv); 4710 } 4711 4712 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 4713 { 4714 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 4715 } 4716 4717 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 4718 { 4719 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 4720 } 4721 4722 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 4723 { 4724 void *p = rtwsta; 4725 4726 return container_of(p, struct ieee80211_sta, drv_priv); 4727 } 4728 4729 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 4730 { 4731 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 4732 } 4733 4734 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 4735 { 4736 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 4737 } 4738 4739 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 4740 { 4741 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 4742 return RATE_INFO_BW_160; 4743 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 4744 return RATE_INFO_BW_80; 4745 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 4746 return RATE_INFO_BW_40; 4747 else 4748 return RATE_INFO_BW_20; 4749 } 4750 4751 static inline 4752 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 4753 { 4754 switch (hw_band) { 4755 default: 4756 case RTW89_BAND_2G: 4757 return NL80211_BAND_2GHZ; 4758 case RTW89_BAND_5G: 4759 return NL80211_BAND_5GHZ; 4760 case RTW89_BAND_6G: 4761 return NL80211_BAND_6GHZ; 4762 } 4763 } 4764 4765 static inline 4766 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 4767 { 4768 switch (nl_band) { 4769 default: 4770 case NL80211_BAND_2GHZ: 4771 return RTW89_BAND_2G; 4772 case NL80211_BAND_5GHZ: 4773 return RTW89_BAND_5G; 4774 case NL80211_BAND_6GHZ: 4775 return RTW89_BAND_6G; 4776 } 4777 } 4778 4779 static inline 4780 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 4781 { 4782 switch (width) { 4783 default: 4784 WARN(1, "Not support bandwidth %d\n", width); 4785 fallthrough; 4786 case NL80211_CHAN_WIDTH_20_NOHT: 4787 case NL80211_CHAN_WIDTH_20: 4788 return RTW89_CHANNEL_WIDTH_20; 4789 case NL80211_CHAN_WIDTH_40: 4790 return RTW89_CHANNEL_WIDTH_40; 4791 case NL80211_CHAN_WIDTH_80: 4792 return RTW89_CHANNEL_WIDTH_80; 4793 case NL80211_CHAN_WIDTH_160: 4794 return RTW89_CHANNEL_WIDTH_160; 4795 } 4796 } 4797 4798 static inline 4799 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 4800 struct rtw89_sta *rtwsta) 4801 { 4802 if (rtwsta) { 4803 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 4804 4805 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 4806 return &rtwsta->addr_cam; 4807 } 4808 return &rtwvif->addr_cam; 4809 } 4810 4811 static inline 4812 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 4813 struct rtw89_sta *rtwsta) 4814 { 4815 if (rtwsta) { 4816 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 4817 4818 if (sta->tdls) 4819 return &rtwsta->bssid_cam; 4820 } 4821 return &rtwvif->bssid_cam; 4822 } 4823 4824 static inline 4825 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 4826 struct rtw89_channel_help_params *p, 4827 const struct rtw89_chan *chan, 4828 enum rtw89_mac_idx mac_idx, 4829 enum rtw89_phy_idx phy_idx) 4830 { 4831 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 4832 mac_idx, phy_idx); 4833 } 4834 4835 static inline 4836 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 4837 struct rtw89_channel_help_params *p, 4838 const struct rtw89_chan *chan, 4839 enum rtw89_mac_idx mac_idx, 4840 enum rtw89_phy_idx phy_idx) 4841 { 4842 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 4843 mac_idx, phy_idx); 4844 } 4845 4846 static inline 4847 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 4848 enum rtw89_sub_entity_idx idx) 4849 { 4850 struct rtw89_hal *hal = &rtwdev->hal; 4851 enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx); 4852 4853 if (roc_idx == idx) 4854 return &hal->roc_chandef; 4855 4856 return &hal->sub[idx].chandef; 4857 } 4858 4859 static inline 4860 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 4861 enum rtw89_sub_entity_idx idx) 4862 { 4863 struct rtw89_hal *hal = &rtwdev->hal; 4864 4865 return &hal->sub[idx].chan; 4866 } 4867 4868 static inline 4869 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 4870 enum rtw89_sub_entity_idx idx) 4871 { 4872 struct rtw89_hal *hal = &rtwdev->hal; 4873 4874 return &hal->sub[idx].rcd; 4875 } 4876 4877 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 4878 { 4879 const struct rtw89_chip_info *chip = rtwdev->chip; 4880 4881 if (chip->ops->fem_setup) 4882 chip->ops->fem_setup(rtwdev); 4883 } 4884 4885 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 4886 { 4887 const struct rtw89_chip_info *chip = rtwdev->chip; 4888 4889 if (chip->ops->rfe_gpio) 4890 chip->ops->rfe_gpio(rtwdev); 4891 } 4892 4893 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 4894 { 4895 const struct rtw89_chip_info *chip = rtwdev->chip; 4896 4897 if (chip->ops->bb_sethw) 4898 chip->ops->bb_sethw(rtwdev); 4899 } 4900 4901 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 4902 { 4903 const struct rtw89_chip_info *chip = rtwdev->chip; 4904 4905 if (chip->ops->rfk_init) 4906 chip->ops->rfk_init(rtwdev); 4907 } 4908 4909 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 4910 { 4911 const struct rtw89_chip_info *chip = rtwdev->chip; 4912 4913 if (chip->ops->rfk_channel) 4914 chip->ops->rfk_channel(rtwdev); 4915 } 4916 4917 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 4918 enum rtw89_phy_idx phy_idx) 4919 { 4920 const struct rtw89_chip_info *chip = rtwdev->chip; 4921 4922 if (chip->ops->rfk_band_changed) 4923 chip->ops->rfk_band_changed(rtwdev, phy_idx); 4924 } 4925 4926 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 4927 { 4928 const struct rtw89_chip_info *chip = rtwdev->chip; 4929 4930 if (chip->ops->rfk_scan) 4931 chip->ops->rfk_scan(rtwdev, start); 4932 } 4933 4934 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 4935 { 4936 const struct rtw89_chip_info *chip = rtwdev->chip; 4937 4938 if (chip->ops->rfk_track) 4939 chip->ops->rfk_track(rtwdev); 4940 } 4941 4942 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 4943 { 4944 const struct rtw89_chip_info *chip = rtwdev->chip; 4945 4946 if (chip->ops->set_txpwr_ctrl) 4947 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 4948 } 4949 4950 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 4951 { 4952 const struct rtw89_chip_info *chip = rtwdev->chip; 4953 4954 if (chip->ops->power_trim) 4955 chip->ops->power_trim(rtwdev); 4956 } 4957 4958 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 4959 enum rtw89_phy_idx phy_idx) 4960 { 4961 const struct rtw89_chip_info *chip = rtwdev->chip; 4962 4963 if (chip->ops->init_txpwr_unit) 4964 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 4965 } 4966 4967 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 4968 enum rtw89_rf_path rf_path) 4969 { 4970 const struct rtw89_chip_info *chip = rtwdev->chip; 4971 4972 if (!chip->ops->get_thermal) 4973 return 0x10; 4974 4975 return chip->ops->get_thermal(rtwdev, rf_path); 4976 } 4977 4978 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 4979 struct rtw89_rx_phy_ppdu *phy_ppdu, 4980 struct ieee80211_rx_status *status) 4981 { 4982 const struct rtw89_chip_info *chip = rtwdev->chip; 4983 4984 if (chip->ops->query_ppdu) 4985 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 4986 } 4987 4988 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, 4989 bool bt_en) 4990 { 4991 const struct rtw89_chip_info *chip = rtwdev->chip; 4992 4993 if (chip->ops->bb_ctrl_btc_preagc) 4994 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en); 4995 } 4996 4997 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 4998 { 4999 const struct rtw89_chip_info *chip = rtwdev->chip; 5000 5001 if (chip->ops->cfg_txrx_path) 5002 chip->ops->cfg_txrx_path(rtwdev); 5003 } 5004 5005 static inline 5006 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 5007 struct ieee80211_vif *vif) 5008 { 5009 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5010 const struct rtw89_chip_info *chip = rtwdev->chip; 5011 5012 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 5013 return; 5014 5015 if (chip->ops->set_txpwr_ul_tb_offset) 5016 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 5017 } 5018 5019 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 5020 const struct rtw89_txpwr_table *tbl) 5021 { 5022 tbl->load(rtwdev, tbl); 5023 } 5024 5025 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 5026 { 5027 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 5028 5029 return regd->txpwr_regd[band]; 5030 } 5031 5032 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 5033 { 5034 const struct rtw89_chip_info *chip = rtwdev->chip; 5035 5036 if (chip->ops->ctrl_btg) 5037 chip->ops->ctrl_btg(rtwdev, btg); 5038 } 5039 5040 static inline 5041 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 5042 struct rtw89_rx_desc_info *desc_info, 5043 u8 *data, u32 data_offset) 5044 { 5045 const struct rtw89_chip_info *chip = rtwdev->chip; 5046 5047 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 5048 } 5049 5050 static inline 5051 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 5052 struct rtw89_tx_desc_info *desc_info, 5053 void *txdesc) 5054 { 5055 const struct rtw89_chip_info *chip = rtwdev->chip; 5056 5057 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 5058 } 5059 5060 static inline 5061 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 5062 struct rtw89_tx_desc_info *desc_info, 5063 void *txdesc) 5064 { 5065 const struct rtw89_chip_info *chip = rtwdev->chip; 5066 5067 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 5068 } 5069 5070 static inline 5071 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5072 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5073 { 5074 const struct rtw89_chip_info *chip = rtwdev->chip; 5075 5076 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 5077 } 5078 5079 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5080 { 5081 const struct rtw89_chip_info *chip = rtwdev->chip; 5082 5083 chip->ops->cfg_ctrl_path(rtwdev, wl); 5084 } 5085 5086 static inline 5087 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 5088 u32 *tx_en, enum rtw89_sch_tx_sel sel) 5089 { 5090 const struct rtw89_chip_info *chip = rtwdev->chip; 5091 5092 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 5093 } 5094 5095 static inline 5096 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 5097 { 5098 const struct rtw89_chip_info *chip = rtwdev->chip; 5099 5100 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 5101 } 5102 5103 static inline 5104 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 5105 struct rtw89_vif *rtwvif, 5106 struct rtw89_sta *rtwsta) 5107 { 5108 const struct rtw89_chip_info *chip = rtwdev->chip; 5109 5110 if (!chip->ops->h2c_dctl_sec_cam) 5111 return 0; 5112 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 5113 } 5114 5115 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 5116 { 5117 __le16 fc = hdr->frame_control; 5118 5119 if (ieee80211_has_tods(fc)) 5120 return hdr->addr1; 5121 else if (ieee80211_has_fromds(fc)) 5122 return hdr->addr2; 5123 else 5124 return hdr->addr3; 5125 } 5126 5127 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 5128 { 5129 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5130 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 5131 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 5132 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5133 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 5134 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 5135 return true; 5136 return false; 5137 } 5138 5139 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 5140 enum rtw89_fw_type type) 5141 { 5142 struct rtw89_fw_info *fw_info = &rtwdev->fw; 5143 5144 if (type == RTW89_FW_WOWLAN) 5145 return &fw_info->wowlan; 5146 return &fw_info->normal; 5147 } 5148 5149 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 5150 unsigned int length) 5151 { 5152 struct sk_buff *skb; 5153 5154 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 5155 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 5156 if (!skb) 5157 return NULL; 5158 5159 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 5160 return skb; 5161 } 5162 5163 return dev_alloc_skb(length); 5164 } 5165 5166 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 5167 struct rtw89_tx_skb_data *skb_data, 5168 bool tx_done) 5169 { 5170 struct rtw89_tx_wait_info *wait; 5171 5172 rcu_read_lock(); 5173 5174 wait = rcu_dereference(skb_data->wait); 5175 if (!wait) 5176 goto out; 5177 5178 wait->tx_done = tx_done; 5179 complete(&wait->completion); 5180 5181 out: 5182 rcu_read_unlock(); 5183 } 5184 5185 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5186 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 5187 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 5188 struct sk_buff *skb, bool fwdl); 5189 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 5190 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5191 int qsel, unsigned int timeout); 5192 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 5193 struct rtw89_tx_desc_info *desc_info, 5194 void *txdesc); 5195 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 5196 struct rtw89_tx_desc_info *desc_info, 5197 void *txdesc); 5198 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 5199 struct rtw89_tx_desc_info *desc_info, 5200 void *txdesc); 5201 void rtw89_core_rx(struct rtw89_dev *rtwdev, 5202 struct rtw89_rx_desc_info *desc_info, 5203 struct sk_buff *skb); 5204 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 5205 struct rtw89_rx_desc_info *desc_info, 5206 u8 *data, u32 data_offset); 5207 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 5208 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 5209 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 5210 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 5211 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 5212 struct ieee80211_vif *vif, 5213 struct ieee80211_sta *sta); 5214 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 5215 struct ieee80211_vif *vif, 5216 struct ieee80211_sta *sta); 5217 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 5218 struct ieee80211_vif *vif, 5219 struct ieee80211_sta *sta); 5220 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 5221 struct ieee80211_vif *vif, 5222 struct ieee80211_sta *sta); 5223 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 5224 struct ieee80211_vif *vif, 5225 struct ieee80211_sta *sta); 5226 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 5227 struct ieee80211_sta *sta, 5228 struct cfg80211_tid_config *tid_config); 5229 int rtw89_core_init(struct rtw89_dev *rtwdev); 5230 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 5231 int rtw89_core_register(struct rtw89_dev *rtwdev); 5232 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 5233 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 5234 u32 bus_data_size, 5235 const struct rtw89_chip_info *chip); 5236 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 5237 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 5238 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 5239 void rtw89_set_channel(struct rtw89_dev *rtwdev); 5240 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5241 struct rtw89_chan *chan); 5242 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 5243 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 5244 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 5245 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 5246 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 5247 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 5248 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 5249 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 5250 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 5251 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 5252 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 5253 int rtw89_regd_init(struct rtw89_dev *rtwdev, 5254 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 5255 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 5256 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 5257 struct rtw89_traffic_stats *stats); 5258 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 5259 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 5260 const struct rtw89_completion_data *data); 5261 int rtw89_core_start(struct rtw89_dev *rtwdev); 5262 void rtw89_core_stop(struct rtw89_dev *rtwdev); 5263 void rtw89_core_update_beacon_work(struct work_struct *work); 5264 void rtw89_roc_work(struct work_struct *work); 5265 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 5266 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 5267 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5268 const u8 *mac_addr, bool hw_scan); 5269 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 5270 struct ieee80211_vif *vif, bool hw_scan); 5271 void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev, 5272 struct rtw89_vif *rtwvif, bool active); 5273 5274 #endif 5275