1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 18 extern const struct ieee80211_ops rtw89_ops; 19 20 #define MASKBYTE0 0xff 21 #define MASKBYTE1 0xff00 22 #define MASKBYTE2 0xff0000 23 #define MASKBYTE3 0xff000000 24 #define MASKBYTE4 0xff00000000ULL 25 #define MASKHWORD 0xffff0000 26 #define MASKLWORD 0x0000ffff 27 #define MASKDWORD 0xffffffff 28 #define RFREG_MASK 0xfffff 29 #define INV_RF_DATA 0xffffffff 30 31 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 32 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 33 #define CFO_TRACK_MAX_USER 64 34 #define MAX_RSSI 110 35 #define RSSI_FACTOR 1 36 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 37 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 38 39 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 40 #define RTW89_HTC_VARIANT_HE 3 41 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 42 #define RTW89_HTC_VARIANT_HE_CID_OM 1 43 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 44 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 45 46 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 47 enum htc_om_channel_width { 48 HTC_OM_CHANNEL_WIDTH_20 = 0, 49 HTC_OM_CHANNEL_WIDTH_40 = 1, 50 HTC_OM_CHANNEL_WIDTH_80 = 2, 51 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 52 }; 53 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 54 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 55 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 56 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 57 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 58 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 59 60 #define RTW89_TF_PAD GENMASK(11, 0) 61 #define RTW89_TF_BASIC_USER_INFO_SZ 6 62 63 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 64 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 65 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 66 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 67 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 68 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 69 70 enum rtw89_subband { 71 RTW89_CH_2G = 0, 72 RTW89_CH_5G_BAND_1 = 1, 73 /* RTW89_CH_5G_BAND_2 = 2, unused */ 74 RTW89_CH_5G_BAND_3 = 3, 75 RTW89_CH_5G_BAND_4 = 4, 76 77 RTW89_CH_6G_BAND_IDX0, /* Low */ 78 RTW89_CH_6G_BAND_IDX1, /* Low */ 79 RTW89_CH_6G_BAND_IDX2, /* Mid */ 80 RTW89_CH_6G_BAND_IDX3, /* Mid */ 81 RTW89_CH_6G_BAND_IDX4, /* High */ 82 RTW89_CH_6G_BAND_IDX5, /* High */ 83 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 84 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 85 86 RTW89_SUBBAND_NR, 87 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 88 }; 89 90 enum rtw89_gain_offset { 91 RTW89_GAIN_OFFSET_2G_CCK, 92 RTW89_GAIN_OFFSET_2G_OFDM, 93 RTW89_GAIN_OFFSET_5G_LOW, 94 RTW89_GAIN_OFFSET_5G_MID, 95 RTW89_GAIN_OFFSET_5G_HIGH, 96 97 RTW89_GAIN_OFFSET_NR, 98 }; 99 100 enum rtw89_hci_type { 101 RTW89_HCI_TYPE_PCIE, 102 RTW89_HCI_TYPE_USB, 103 RTW89_HCI_TYPE_SDIO, 104 }; 105 106 enum rtw89_core_chip_id { 107 RTL8852A, 108 RTL8852B, 109 RTL8852C, 110 }; 111 112 enum rtw89_cv { 113 CHIP_CAV, 114 CHIP_CBV, 115 CHIP_CCV, 116 CHIP_CDV, 117 CHIP_CEV, 118 CHIP_CFV, 119 CHIP_CV_MAX, 120 CHIP_CV_INVALID = CHIP_CV_MAX, 121 }; 122 123 enum rtw89_core_tx_type { 124 RTW89_CORE_TX_TYPE_DATA, 125 RTW89_CORE_TX_TYPE_MGMT, 126 RTW89_CORE_TX_TYPE_FWCMD, 127 }; 128 129 enum rtw89_core_rx_type { 130 RTW89_CORE_RX_TYPE_WIFI = 0, 131 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 132 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 133 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 134 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 135 RTW89_CORE_RX_TYPE_SS2FW = 5, 136 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 137 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 138 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 139 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 140 RTW89_CORE_RX_TYPE_C2H = 10, 141 RTW89_CORE_RX_TYPE_CSI = 11, 142 RTW89_CORE_RX_TYPE_CQI = 12, 143 RTW89_CORE_RX_TYPE_H2C = 13, 144 RTW89_CORE_RX_TYPE_FWDL = 14, 145 }; 146 147 enum rtw89_txq_flags { 148 RTW89_TXQ_F_AMPDU = 0, 149 RTW89_TXQ_F_BLOCK_BA = 1, 150 RTW89_TXQ_F_FORBID_BA = 2, 151 }; 152 153 enum rtw89_net_type { 154 RTW89_NET_TYPE_NO_LINK = 0, 155 RTW89_NET_TYPE_AD_HOC = 1, 156 RTW89_NET_TYPE_INFRA = 2, 157 RTW89_NET_TYPE_AP_MODE = 3, 158 }; 159 160 enum rtw89_wifi_role { 161 RTW89_WIFI_ROLE_NONE, 162 RTW89_WIFI_ROLE_STATION, 163 RTW89_WIFI_ROLE_AP, 164 RTW89_WIFI_ROLE_AP_VLAN, 165 RTW89_WIFI_ROLE_ADHOC, 166 RTW89_WIFI_ROLE_ADHOC_MASTER, 167 RTW89_WIFI_ROLE_MESH_POINT, 168 RTW89_WIFI_ROLE_MONITOR, 169 RTW89_WIFI_ROLE_P2P_DEVICE, 170 RTW89_WIFI_ROLE_P2P_CLIENT, 171 RTW89_WIFI_ROLE_P2P_GO, 172 RTW89_WIFI_ROLE_NAN, 173 RTW89_WIFI_ROLE_MLME_MAX 174 }; 175 176 enum rtw89_upd_mode { 177 RTW89_ROLE_CREATE, 178 RTW89_ROLE_REMOVE, 179 RTW89_ROLE_TYPE_CHANGE, 180 RTW89_ROLE_INFO_CHANGE, 181 RTW89_ROLE_CON_DISCONN 182 }; 183 184 enum rtw89_self_role { 185 RTW89_SELF_ROLE_CLIENT, 186 RTW89_SELF_ROLE_AP, 187 RTW89_SELF_ROLE_AP_CLIENT 188 }; 189 190 enum rtw89_msk_sO_el { 191 RTW89_NO_MSK, 192 RTW89_SMA, 193 RTW89_TMA, 194 RTW89_BSSID 195 }; 196 197 enum rtw89_sch_tx_sel { 198 RTW89_SCH_TX_SEL_ALL, 199 RTW89_SCH_TX_SEL_HIQ, 200 RTW89_SCH_TX_SEL_MG0, 201 RTW89_SCH_TX_SEL_MACID, 202 }; 203 204 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 205 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 206 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 207 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 208 */ 209 enum rtw89_add_cam_sec_mode { 210 RTW89_ADDR_CAM_SEC_NONE = 0, 211 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 212 RTW89_ADDR_CAM_SEC_NORMAL = 2, 213 RTW89_ADDR_CAM_SEC_4GROUP = 3, 214 }; 215 216 enum rtw89_sec_key_type { 217 RTW89_SEC_KEY_TYPE_NONE = 0, 218 RTW89_SEC_KEY_TYPE_WEP40 = 1, 219 RTW89_SEC_KEY_TYPE_WEP104 = 2, 220 RTW89_SEC_KEY_TYPE_TKIP = 3, 221 RTW89_SEC_KEY_TYPE_WAPI = 4, 222 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 223 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 224 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 225 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 226 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 227 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 228 }; 229 230 enum rtw89_port { 231 RTW89_PORT_0 = 0, 232 RTW89_PORT_1 = 1, 233 RTW89_PORT_2 = 2, 234 RTW89_PORT_3 = 3, 235 RTW89_PORT_4 = 4, 236 RTW89_PORT_NUM 237 }; 238 239 enum rtw89_band { 240 RTW89_BAND_2G = 0, 241 RTW89_BAND_5G = 1, 242 RTW89_BAND_6G = 2, 243 RTW89_BAND_MAX, 244 }; 245 246 enum rtw89_hw_rate { 247 RTW89_HW_RATE_CCK1 = 0x0, 248 RTW89_HW_RATE_CCK2 = 0x1, 249 RTW89_HW_RATE_CCK5_5 = 0x2, 250 RTW89_HW_RATE_CCK11 = 0x3, 251 RTW89_HW_RATE_OFDM6 = 0x4, 252 RTW89_HW_RATE_OFDM9 = 0x5, 253 RTW89_HW_RATE_OFDM12 = 0x6, 254 RTW89_HW_RATE_OFDM18 = 0x7, 255 RTW89_HW_RATE_OFDM24 = 0x8, 256 RTW89_HW_RATE_OFDM36 = 0x9, 257 RTW89_HW_RATE_OFDM48 = 0xA, 258 RTW89_HW_RATE_OFDM54 = 0xB, 259 RTW89_HW_RATE_MCS0 = 0x80, 260 RTW89_HW_RATE_MCS1 = 0x81, 261 RTW89_HW_RATE_MCS2 = 0x82, 262 RTW89_HW_RATE_MCS3 = 0x83, 263 RTW89_HW_RATE_MCS4 = 0x84, 264 RTW89_HW_RATE_MCS5 = 0x85, 265 RTW89_HW_RATE_MCS6 = 0x86, 266 RTW89_HW_RATE_MCS7 = 0x87, 267 RTW89_HW_RATE_MCS8 = 0x88, 268 RTW89_HW_RATE_MCS9 = 0x89, 269 RTW89_HW_RATE_MCS10 = 0x8A, 270 RTW89_HW_RATE_MCS11 = 0x8B, 271 RTW89_HW_RATE_MCS12 = 0x8C, 272 RTW89_HW_RATE_MCS13 = 0x8D, 273 RTW89_HW_RATE_MCS14 = 0x8E, 274 RTW89_HW_RATE_MCS15 = 0x8F, 275 RTW89_HW_RATE_MCS16 = 0x90, 276 RTW89_HW_RATE_MCS17 = 0x91, 277 RTW89_HW_RATE_MCS18 = 0x92, 278 RTW89_HW_RATE_MCS19 = 0x93, 279 RTW89_HW_RATE_MCS20 = 0x94, 280 RTW89_HW_RATE_MCS21 = 0x95, 281 RTW89_HW_RATE_MCS22 = 0x96, 282 RTW89_HW_RATE_MCS23 = 0x97, 283 RTW89_HW_RATE_MCS24 = 0x98, 284 RTW89_HW_RATE_MCS25 = 0x99, 285 RTW89_HW_RATE_MCS26 = 0x9A, 286 RTW89_HW_RATE_MCS27 = 0x9B, 287 RTW89_HW_RATE_MCS28 = 0x9C, 288 RTW89_HW_RATE_MCS29 = 0x9D, 289 RTW89_HW_RATE_MCS30 = 0x9E, 290 RTW89_HW_RATE_MCS31 = 0x9F, 291 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 292 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 293 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 294 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 295 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 296 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 297 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 298 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 299 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 300 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 301 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 302 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 303 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 304 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 305 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 306 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 307 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 308 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 309 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 310 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 311 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 312 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 313 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 314 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 315 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 316 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 317 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 318 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 319 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 320 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 321 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 322 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 323 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 324 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 325 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 326 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 327 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 328 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 329 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 330 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 331 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 332 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 333 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 334 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 335 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 336 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 337 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 338 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 339 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 340 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 341 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 342 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 343 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 344 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 345 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 346 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 347 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 348 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 349 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 350 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 351 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 352 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 353 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 354 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 355 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 356 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 357 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 358 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 359 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 360 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 361 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 362 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 363 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 364 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 365 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 366 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 367 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 368 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 369 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 370 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 371 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 372 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 373 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 374 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 375 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 376 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 377 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 378 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 379 RTW89_HW_RATE_NR, 380 381 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 382 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 383 }; 384 385 /* 2G channels, 386 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 387 */ 388 #define RTW89_2G_CH_NUM 14 389 390 /* 5G channels, 391 * 36, 38, 40, 42, 44, 46, 48, 50, 392 * 52, 54, 56, 58, 60, 62, 64, 393 * 100, 102, 104, 106, 108, 110, 112, 114, 394 * 116, 118, 120, 122, 124, 126, 128, 130, 395 * 132, 134, 136, 138, 140, 142, 144, 396 * 149, 151, 153, 155, 157, 159, 161, 163, 397 * 165, 167, 169, 171, 173, 175, 177 398 */ 399 #define RTW89_5G_CH_NUM 53 400 401 /* 6G channels, 402 * 1, 3, 5, 7, 9, 11, 13, 15, 403 * 17, 19, 21, 23, 25, 27, 29, 33, 404 * 35, 37, 39, 41, 43, 45, 47, 49, 405 * 51, 53, 55, 57, 59, 61, 65, 67, 406 * 69, 71, 73, 75, 77, 79, 81, 83, 407 * 85, 87, 89, 91, 93, 97, 99, 101, 408 * 103, 105, 107, 109, 111, 113, 115, 117, 409 * 119, 121, 123, 125, 129, 131, 133, 135, 410 * 137, 139, 141, 143, 145, 147, 149, 151, 411 * 153, 155, 157, 161, 163, 165, 167, 169, 412 * 171, 173, 175, 177, 179, 181, 183, 185, 413 * 187, 189, 193, 195, 197, 199, 201, 203, 414 * 205, 207, 209, 211, 213, 215, 217, 219, 415 * 221, 225, 227, 229, 231, 233, 235, 237, 416 * 239, 241, 243, 245, 247, 249, 251, 253, 417 */ 418 #define RTW89_6G_CH_NUM 120 419 420 enum rtw89_rate_section { 421 RTW89_RS_CCK, 422 RTW89_RS_OFDM, 423 RTW89_RS_MCS, /* for HT/VHT/HE */ 424 RTW89_RS_HEDCM, 425 RTW89_RS_OFFSET, 426 RTW89_RS_MAX, 427 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 428 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 429 }; 430 431 enum rtw89_rate_max { 432 RTW89_RATE_CCK_MAX = 4, 433 RTW89_RATE_OFDM_MAX = 8, 434 RTW89_RATE_MCS_MAX = 12, 435 RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */ 436 RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */ 437 }; 438 439 enum rtw89_nss { 440 RTW89_NSS_1 = 0, 441 RTW89_NSS_2 = 1, 442 /* HE DCM only support 1ss and 2ss */ 443 RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1, 444 RTW89_NSS_3 = 2, 445 RTW89_NSS_4 = 3, 446 RTW89_NSS_MAX, 447 }; 448 449 enum rtw89_ntx { 450 RTW89_1TX = 0, 451 RTW89_2TX = 1, 452 RTW89_NTX_NUM, 453 }; 454 455 enum rtw89_beamforming_type { 456 RTW89_NONBF = 0, 457 RTW89_BF = 1, 458 RTW89_BF_NUM, 459 }; 460 461 enum rtw89_regulation_type { 462 RTW89_WW = 0, 463 RTW89_ETSI = 1, 464 RTW89_FCC = 2, 465 RTW89_MKK = 3, 466 RTW89_NA = 4, 467 RTW89_IC = 5, 468 RTW89_KCC = 6, 469 RTW89_ACMA = 7, 470 RTW89_NCC = 8, 471 RTW89_MEXICO = 9, 472 RTW89_CHILE = 10, 473 RTW89_UKRAINE = 11, 474 RTW89_CN = 12, 475 RTW89_QATAR = 13, 476 RTW89_UK = 14, 477 RTW89_REGD_NUM, 478 }; 479 480 struct rtw89_txpwr_byrate { 481 s8 cck[RTW89_RATE_CCK_MAX]; 482 s8 ofdm[RTW89_RATE_OFDM_MAX]; 483 s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX]; 484 s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX]; 485 s8 offset[RTW89_RATE_OFFSET_MAX]; 486 }; 487 488 enum rtw89_bandwidth_section_num { 489 RTW89_BW20_SEC_NUM = 8, 490 RTW89_BW40_SEC_NUM = 4, 491 RTW89_BW80_SEC_NUM = 2, 492 }; 493 494 #define RTW89_TXPWR_LMT_PAGE_SIZE 40 495 496 struct rtw89_txpwr_limit { 497 s8 cck_20m[RTW89_BF_NUM]; 498 s8 cck_40m[RTW89_BF_NUM]; 499 s8 ofdm[RTW89_BF_NUM]; 500 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM]; 501 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM]; 502 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM]; 503 s8 mcs_160m[RTW89_BF_NUM]; 504 s8 mcs_40m_0p5[RTW89_BF_NUM]; 505 s8 mcs_40m_2p5[RTW89_BF_NUM]; 506 }; 507 508 #define RTW89_RU_SEC_NUM 8 509 510 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE 24 511 512 struct rtw89_txpwr_limit_ru { 513 s8 ru26[RTW89_RU_SEC_NUM]; 514 s8 ru52[RTW89_RU_SEC_NUM]; 515 s8 ru106[RTW89_RU_SEC_NUM]; 516 }; 517 518 struct rtw89_rate_desc { 519 enum rtw89_nss nss; 520 enum rtw89_rate_section rs; 521 u8 idx; 522 }; 523 524 #define PHY_STS_HDR_LEN 8 525 #define RF_PATH_MAX 4 526 #define RTW89_MAX_PPDU_CNT 8 527 struct rtw89_rx_phy_ppdu { 528 u8 *buf; 529 u32 len; 530 u8 rssi_avg; 531 u8 rssi[RF_PATH_MAX]; 532 u8 mac_id; 533 u8 chan_idx; 534 u8 ie; 535 u16 rate; 536 bool to_self; 537 bool valid; 538 }; 539 540 enum rtw89_mac_idx { 541 RTW89_MAC_0 = 0, 542 RTW89_MAC_1 = 1, 543 }; 544 545 enum rtw89_phy_idx { 546 RTW89_PHY_0 = 0, 547 RTW89_PHY_1 = 1, 548 RTW89_PHY_MAX 549 }; 550 551 enum rtw89_sub_entity_idx { 552 RTW89_SUB_ENTITY_0 = 0, 553 554 NUM_OF_RTW89_SUB_ENTITY, 555 }; 556 557 enum rtw89_rf_path { 558 RF_PATH_A = 0, 559 RF_PATH_B = 1, 560 RF_PATH_C = 2, 561 RF_PATH_D = 3, 562 RF_PATH_AB, 563 RF_PATH_AC, 564 RF_PATH_AD, 565 RF_PATH_BC, 566 RF_PATH_BD, 567 RF_PATH_CD, 568 RF_PATH_ABC, 569 RF_PATH_ABD, 570 RF_PATH_ACD, 571 RF_PATH_BCD, 572 RF_PATH_ABCD, 573 }; 574 575 enum rtw89_rf_path_bit { 576 RF_A = BIT(0), 577 RF_B = BIT(1), 578 RF_C = BIT(2), 579 RF_D = BIT(3), 580 581 RF_AB = (RF_A | RF_B), 582 RF_AC = (RF_A | RF_C), 583 RF_AD = (RF_A | RF_D), 584 RF_BC = (RF_B | RF_C), 585 RF_BD = (RF_B | RF_D), 586 RF_CD = (RF_C | RF_D), 587 588 RF_ABC = (RF_A | RF_B | RF_C), 589 RF_ABD = (RF_A | RF_B | RF_D), 590 RF_ACD = (RF_A | RF_C | RF_D), 591 RF_BCD = (RF_B | RF_C | RF_D), 592 593 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 594 }; 595 596 enum rtw89_bandwidth { 597 RTW89_CHANNEL_WIDTH_20 = 0, 598 RTW89_CHANNEL_WIDTH_40 = 1, 599 RTW89_CHANNEL_WIDTH_80 = 2, 600 RTW89_CHANNEL_WIDTH_160 = 3, 601 RTW89_CHANNEL_WIDTH_80_80 = 4, 602 RTW89_CHANNEL_WIDTH_5 = 5, 603 RTW89_CHANNEL_WIDTH_10 = 6, 604 }; 605 606 enum rtw89_ps_mode { 607 RTW89_PS_MODE_NONE = 0, 608 RTW89_PS_MODE_RFOFF = 1, 609 RTW89_PS_MODE_CLK_GATED = 2, 610 RTW89_PS_MODE_PWR_GATED = 3, 611 }; 612 613 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 614 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 615 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 616 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 617 618 enum rtw89_ru_bandwidth { 619 RTW89_RU26 = 0, 620 RTW89_RU52 = 1, 621 RTW89_RU106 = 2, 622 RTW89_RU_NUM, 623 }; 624 625 enum rtw89_sc_offset { 626 RTW89_SC_DONT_CARE = 0, 627 RTW89_SC_20_UPPER = 1, 628 RTW89_SC_20_LOWER = 2, 629 RTW89_SC_20_UPMOST = 3, 630 RTW89_SC_20_LOWEST = 4, 631 RTW89_SC_20_UP2X = 5, 632 RTW89_SC_20_LOW2X = 6, 633 RTW89_SC_20_UP3X = 7, 634 RTW89_SC_20_LOW3X = 8, 635 RTW89_SC_40_UPPER = 9, 636 RTW89_SC_40_LOWER = 10, 637 }; 638 639 struct rtw89_chan { 640 u8 channel; 641 u8 primary_channel; 642 enum rtw89_band band_type; 643 enum rtw89_bandwidth band_width; 644 645 /* The follow-up are derived from the above. We must ensure that it 646 * is assigned correctly in rtw89_chan_create() if new one is added. 647 */ 648 u32 freq; 649 enum rtw89_subband subband_type; 650 enum rtw89_sc_offset pri_ch_idx; 651 }; 652 653 struct rtw89_chan_rcd { 654 u8 prev_primary_channel; 655 enum rtw89_band prev_band_type; 656 }; 657 658 struct rtw89_channel_help_params { 659 u32 tx_en; 660 }; 661 662 struct rtw89_port_reg { 663 u32 port_cfg; 664 u32 tbtt_prohib; 665 u32 bcn_area; 666 u32 bcn_early; 667 u32 tbtt_early; 668 u32 tbtt_agg; 669 u32 bcn_space; 670 u32 bcn_forcetx; 671 u32 bcn_err_cnt; 672 u32 bcn_err_flag; 673 u32 dtim_ctrl; 674 u32 tbtt_shift; 675 u32 bcn_cnt_tmr; 676 u32 tsftr_l; 677 u32 tsftr_h; 678 }; 679 680 struct rtw89_txwd_body { 681 __le32 dword0; 682 __le32 dword1; 683 __le32 dword2; 684 __le32 dword3; 685 __le32 dword4; 686 __le32 dword5; 687 } __packed; 688 689 struct rtw89_txwd_body_v1 { 690 __le32 dword0; 691 __le32 dword1; 692 __le32 dword2; 693 __le32 dword3; 694 __le32 dword4; 695 __le32 dword5; 696 __le32 dword6; 697 __le32 dword7; 698 } __packed; 699 700 struct rtw89_txwd_info { 701 __le32 dword0; 702 __le32 dword1; 703 __le32 dword2; 704 __le32 dword3; 705 __le32 dword4; 706 __le32 dword5; 707 } __packed; 708 709 struct rtw89_rx_desc_info { 710 u16 pkt_size; 711 u8 pkt_type; 712 u8 drv_info_size; 713 u8 shift; 714 u8 wl_hd_iv_len; 715 bool long_rxdesc; 716 bool bb_sel; 717 bool mac_info_valid; 718 u16 data_rate; 719 u8 gi_ltf; 720 u8 bw; 721 u32 free_run_cnt; 722 u8 user_id; 723 bool sr_en; 724 u8 ppdu_cnt; 725 u8 ppdu_type; 726 bool icv_err; 727 bool crc32_err; 728 bool hw_dec; 729 bool sw_dec; 730 bool addr1_match; 731 u8 frag; 732 u16 seq; 733 u8 frame_type; 734 u8 rx_pl_id; 735 bool addr_cam_valid; 736 u8 addr_cam_id; 737 u8 sec_cam_id; 738 u8 mac_id; 739 u16 offset; 740 bool ready; 741 }; 742 743 struct rtw89_rxdesc_short { 744 __le32 dword0; 745 __le32 dword1; 746 __le32 dword2; 747 __le32 dword3; 748 } __packed; 749 750 struct rtw89_rxdesc_long { 751 __le32 dword0; 752 __le32 dword1; 753 __le32 dword2; 754 __le32 dword3; 755 __le32 dword4; 756 __le32 dword5; 757 __le32 dword6; 758 __le32 dword7; 759 } __packed; 760 761 struct rtw89_tx_desc_info { 762 u16 pkt_size; 763 u8 wp_offset; 764 u8 mac_id; 765 u8 qsel; 766 u8 ch_dma; 767 u8 hdr_llc_len; 768 bool is_bmc; 769 bool en_wd_info; 770 bool wd_page; 771 bool use_rate; 772 bool dis_data_fb; 773 bool tid_indicate; 774 bool agg_en; 775 bool bk; 776 u8 ampdu_density; 777 u8 ampdu_num; 778 bool sec_en; 779 u8 addr_info_nr; 780 u8 sec_keyid; 781 u8 sec_type; 782 u8 sec_cam_idx; 783 u8 sec_seq[6]; 784 u16 data_rate; 785 u16 data_retry_lowest_rate; 786 bool fw_dl; 787 u16 seq; 788 bool a_ctrl_bsr; 789 u8 hw_ssn_sel; 790 #define RTW89_MGMT_HW_SSN_SEL 1 791 u8 hw_seq_mode; 792 #define RTW89_MGMT_HW_SEQ_MODE 1 793 bool hiq; 794 u8 port; 795 }; 796 797 struct rtw89_core_tx_request { 798 enum rtw89_core_tx_type tx_type; 799 800 struct sk_buff *skb; 801 struct ieee80211_vif *vif; 802 struct ieee80211_sta *sta; 803 struct rtw89_tx_desc_info desc_info; 804 }; 805 806 struct rtw89_txq { 807 struct list_head list; 808 unsigned long flags; 809 int wait_cnt; 810 }; 811 812 struct rtw89_mac_ax_gnt { 813 u8 gnt_bt_sw_en; 814 u8 gnt_bt; 815 u8 gnt_wl_sw_en; 816 u8 gnt_wl; 817 } __packed; 818 819 #define RTW89_MAC_AX_COEX_GNT_NR 2 820 struct rtw89_mac_ax_coex_gnt { 821 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 822 }; 823 824 enum rtw89_btc_ncnt { 825 BTC_NCNT_POWER_ON = 0x0, 826 BTC_NCNT_POWER_OFF, 827 BTC_NCNT_INIT_COEX, 828 BTC_NCNT_SCAN_START, 829 BTC_NCNT_SCAN_FINISH, 830 BTC_NCNT_SPECIAL_PACKET, 831 BTC_NCNT_SWITCH_BAND, 832 BTC_NCNT_RFK_TIMEOUT, 833 BTC_NCNT_SHOW_COEX_INFO, 834 BTC_NCNT_ROLE_INFO, 835 BTC_NCNT_CONTROL, 836 BTC_NCNT_RADIO_STATE, 837 BTC_NCNT_CUSTOMERIZE, 838 BTC_NCNT_WL_RFK, 839 BTC_NCNT_WL_STA, 840 BTC_NCNT_FWINFO, 841 BTC_NCNT_TIMER, 842 BTC_NCNT_NUM 843 }; 844 845 enum rtw89_btc_btinfo { 846 BTC_BTINFO_L0 = 0, 847 BTC_BTINFO_L1, 848 BTC_BTINFO_L2, 849 BTC_BTINFO_L3, 850 BTC_BTINFO_H0, 851 BTC_BTINFO_H1, 852 BTC_BTINFO_H2, 853 BTC_BTINFO_H3, 854 BTC_BTINFO_MAX 855 }; 856 857 enum rtw89_btc_dcnt { 858 BTC_DCNT_RUN = 0x0, 859 BTC_DCNT_CX_RUNINFO, 860 BTC_DCNT_RPT, 861 BTC_DCNT_RPT_FREEZE, 862 BTC_DCNT_CYCLE, 863 BTC_DCNT_CYCLE_FREEZE, 864 BTC_DCNT_W1, 865 BTC_DCNT_W1_FREEZE, 866 BTC_DCNT_B1, 867 BTC_DCNT_B1_FREEZE, 868 BTC_DCNT_TDMA_NONSYNC, 869 BTC_DCNT_SLOT_NONSYNC, 870 BTC_DCNT_BTCNT_FREEZE, 871 BTC_DCNT_WL_SLOT_DRIFT, 872 BTC_DCNT_BT_SLOT_DRIFT, 873 BTC_DCNT_WL_STA_LAST, 874 BTC_DCNT_NUM, 875 }; 876 877 enum rtw89_btc_wl_state_cnt { 878 BTC_WCNT_SCANAP = 0x0, 879 BTC_WCNT_DHCP, 880 BTC_WCNT_EAPOL, 881 BTC_WCNT_ARP, 882 BTC_WCNT_SCBDUPDATE, 883 BTC_WCNT_RFK_REQ, 884 BTC_WCNT_RFK_GO, 885 BTC_WCNT_RFK_REJECT, 886 BTC_WCNT_RFK_TIMEOUT, 887 BTC_WCNT_CH_UPDATE, 888 BTC_WCNT_NUM 889 }; 890 891 enum rtw89_btc_bt_state_cnt { 892 BTC_BCNT_RETRY = 0x0, 893 BTC_BCNT_REINIT, 894 BTC_BCNT_REENABLE, 895 BTC_BCNT_SCBDREAD, 896 BTC_BCNT_RELINK, 897 BTC_BCNT_IGNOWL, 898 BTC_BCNT_INQPAG, 899 BTC_BCNT_INQ, 900 BTC_BCNT_PAGE, 901 BTC_BCNT_ROLESW, 902 BTC_BCNT_AFH, 903 BTC_BCNT_INFOUPDATE, 904 BTC_BCNT_INFOSAME, 905 BTC_BCNT_SCBDUPDATE, 906 BTC_BCNT_HIPRI_TX, 907 BTC_BCNT_HIPRI_RX, 908 BTC_BCNT_LOPRI_TX, 909 BTC_BCNT_LOPRI_RX, 910 BTC_BCNT_POLUT, 911 BTC_BCNT_RATECHG, 912 BTC_BCNT_NUM 913 }; 914 915 enum rtw89_btc_bt_profile { 916 BTC_BT_NOPROFILE = 0, 917 BTC_BT_HFP = BIT(0), 918 BTC_BT_HID = BIT(1), 919 BTC_BT_A2DP = BIT(2), 920 BTC_BT_PAN = BIT(3), 921 BTC_PROFILE_MAX = 4, 922 }; 923 924 struct rtw89_btc_ant_info { 925 u8 type; /* shared, dedicated */ 926 u8 num; 927 u8 isolation; 928 929 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 930 u8 diversity: 1; 931 }; 932 933 enum rtw89_tfc_dir { 934 RTW89_TFC_UL, 935 RTW89_TFC_DL, 936 }; 937 938 struct rtw89_btc_wl_smap { 939 u32 busy: 1; 940 u32 scan: 1; 941 u32 connecting: 1; 942 u32 roaming: 1; 943 u32 _4way: 1; 944 u32 rf_off: 1; 945 u32 lps: 2; 946 u32 ips: 1; 947 u32 init_ok: 1; 948 u32 traffic_dir : 2; 949 u32 rf_off_pre: 1; 950 u32 lps_pre: 2; 951 }; 952 953 enum rtw89_tfc_lv { 954 RTW89_TFC_IDLE, 955 RTW89_TFC_ULTRA_LOW, 956 RTW89_TFC_LOW, 957 RTW89_TFC_MID, 958 RTW89_TFC_HIGH, 959 }; 960 961 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 962 DECLARE_EWMA(tp, 10, 2); 963 964 struct rtw89_traffic_stats { 965 /* units in bytes */ 966 u64 tx_unicast; 967 u64 rx_unicast; 968 u32 tx_avg_len; 969 u32 rx_avg_len; 970 971 /* count for packets */ 972 u64 tx_cnt; 973 u64 rx_cnt; 974 975 /* units in Mbps */ 976 u32 tx_throughput; 977 u32 rx_throughput; 978 u32 tx_throughput_raw; 979 u32 rx_throughput_raw; 980 981 u32 rx_tf_acc; 982 u32 rx_tf_periodic; 983 984 enum rtw89_tfc_lv tx_tfc_lv; 985 enum rtw89_tfc_lv rx_tfc_lv; 986 struct ewma_tp tx_ewma_tp; 987 struct ewma_tp rx_ewma_tp; 988 989 u16 tx_rate; 990 u16 rx_rate; 991 }; 992 993 struct rtw89_btc_statistic { 994 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 995 struct rtw89_traffic_stats traffic; 996 }; 997 998 #define BTC_WL_RSSI_THMAX 4 999 1000 struct rtw89_btc_wl_link_info { 1001 struct rtw89_btc_statistic stat; 1002 enum rtw89_tfc_dir dir; 1003 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1004 u8 mac_addr[ETH_ALEN]; 1005 u8 busy; 1006 u8 ch; 1007 u8 bw; 1008 u8 band; 1009 u8 role; 1010 u8 pid; 1011 u8 phy; 1012 u8 dtim_period; 1013 u8 mode; 1014 1015 u8 mac_id; 1016 u8 tx_retry; 1017 1018 u32 bcn_period; 1019 u32 busy_t; 1020 u32 tx_time; 1021 u32 client_cnt; 1022 u32 rx_rate_drop_cnt; 1023 1024 u32 active: 1; 1025 u32 noa: 1; 1026 u32 client_ps: 1; 1027 u32 connected: 2; 1028 }; 1029 1030 union rtw89_btc_wl_state_map { 1031 u32 val; 1032 struct rtw89_btc_wl_smap map; 1033 }; 1034 1035 struct rtw89_btc_bt_hfp_desc { 1036 u32 exist: 1; 1037 u32 type: 2; 1038 u32 rsvd: 29; 1039 }; 1040 1041 struct rtw89_btc_bt_hid_desc { 1042 u32 exist: 1; 1043 u32 slot_info: 2; 1044 u32 pair_cnt: 2; 1045 u32 type: 8; 1046 u32 rsvd: 19; 1047 }; 1048 1049 struct rtw89_btc_bt_a2dp_desc { 1050 u8 exist: 1; 1051 u8 exist_last: 1; 1052 u8 play_latency: 1; 1053 u8 type: 3; 1054 u8 active: 1; 1055 u8 sink: 1; 1056 1057 u8 bitpool; 1058 u16 vendor_id; 1059 u32 device_name; 1060 u32 flush_time; 1061 }; 1062 1063 struct rtw89_btc_bt_pan_desc { 1064 u32 exist: 1; 1065 u32 type: 1; 1066 u32 active: 1; 1067 u32 rsvd: 29; 1068 }; 1069 1070 struct rtw89_btc_bt_rfk_info { 1071 u32 run: 1; 1072 u32 req: 1; 1073 u32 timeout: 1; 1074 u32 rsvd: 29; 1075 }; 1076 1077 union rtw89_btc_bt_rfk_info_map { 1078 u32 val; 1079 struct rtw89_btc_bt_rfk_info map; 1080 }; 1081 1082 struct rtw89_btc_bt_ver_info { 1083 u32 fw_coex; /* match with which coex_ver */ 1084 u32 fw; 1085 }; 1086 1087 struct rtw89_btc_bool_sta_chg { 1088 u32 now: 1; 1089 u32 last: 1; 1090 u32 remain: 1; 1091 u32 srvd: 29; 1092 }; 1093 1094 struct rtw89_btc_u8_sta_chg { 1095 u8 now; 1096 u8 last; 1097 u8 remain; 1098 u8 rsvd; 1099 }; 1100 1101 struct rtw89_btc_wl_scan_info { 1102 u8 band[RTW89_PHY_MAX]; 1103 u8 phy_map; 1104 u8 rsvd; 1105 }; 1106 1107 struct rtw89_btc_wl_dbcc_info { 1108 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1109 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1110 u8 real_band[RTW89_PHY_MAX]; 1111 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1112 }; 1113 1114 struct rtw89_btc_wl_active_role { 1115 u8 connected: 1; 1116 u8 pid: 3; 1117 u8 phy: 1; 1118 u8 noa: 1; 1119 u8 band: 2; 1120 1121 u8 client_ps: 1; 1122 u8 bw: 7; 1123 1124 u8 role; 1125 u8 ch; 1126 1127 u16 tx_lvl; 1128 u16 rx_lvl; 1129 u16 tx_rate; 1130 u16 rx_rate; 1131 }; 1132 1133 struct rtw89_btc_wl_active_role_v1 { 1134 u8 connected: 1; 1135 u8 pid: 3; 1136 u8 phy: 1; 1137 u8 noa: 1; 1138 u8 band: 2; 1139 1140 u8 client_ps: 1; 1141 u8 bw: 7; 1142 1143 u8 role; 1144 u8 ch; 1145 1146 u16 tx_lvl; 1147 u16 rx_lvl; 1148 u16 tx_rate; 1149 u16 rx_rate; 1150 1151 u32 noa_duration; /* ms */ 1152 }; 1153 1154 struct rtw89_btc_wl_role_info_bpos { 1155 u16 none: 1; 1156 u16 station: 1; 1157 u16 ap: 1; 1158 u16 vap: 1; 1159 u16 adhoc: 1; 1160 u16 adhoc_master: 1; 1161 u16 mesh: 1; 1162 u16 moniter: 1; 1163 u16 p2p_device: 1; 1164 u16 p2p_gc: 1; 1165 u16 p2p_go: 1; 1166 u16 nan: 1; 1167 }; 1168 1169 struct rtw89_btc_wl_scc_ctrl { 1170 u8 null_role1; 1171 u8 null_role2; 1172 u8 ebt_null; /* if tx null at EBT slot */ 1173 }; 1174 1175 union rtw89_btc_wl_role_info_map { 1176 u16 val; 1177 struct rtw89_btc_wl_role_info_bpos role; 1178 }; 1179 1180 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1181 u8 connect_cnt; 1182 u8 link_mode; 1183 union rtw89_btc_wl_role_info_map role_map; 1184 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1185 }; 1186 1187 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1188 u8 connect_cnt; 1189 u8 link_mode; 1190 union rtw89_btc_wl_role_info_map role_map; 1191 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1192 u32 mrole_type; /* btc_wl_mrole_type */ 1193 u32 mrole_noa_duration; /* ms */ 1194 1195 u32 dbcc_en: 1; 1196 u32 dbcc_chg: 1; 1197 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1198 u32 link_mode_chg: 1; 1199 u32 rsvd: 27; 1200 }; 1201 1202 struct rtw89_btc_wl_ver_info { 1203 u32 fw_coex; /* match with which coex_ver */ 1204 u32 fw; 1205 u32 mac; 1206 u32 bb; 1207 u32 rf; 1208 }; 1209 1210 struct rtw89_btc_wl_afh_info { 1211 u8 en; 1212 u8 ch; 1213 u8 bw; 1214 u8 rsvd; 1215 } __packed; 1216 1217 struct rtw89_btc_wl_rfk_info { 1218 u32 state: 2; 1219 u32 path_map: 4; 1220 u32 phy_map: 2; 1221 u32 band: 2; 1222 u32 type: 8; 1223 u32 rsvd: 14; 1224 }; 1225 1226 struct rtw89_btc_bt_smap { 1227 u32 connect: 1; 1228 u32 ble_connect: 1; 1229 u32 acl_busy: 1; 1230 u32 sco_busy: 1; 1231 u32 mesh_busy: 1; 1232 u32 inq_pag: 1; 1233 }; 1234 1235 union rtw89_btc_bt_state_map { 1236 u32 val; 1237 struct rtw89_btc_bt_smap map; 1238 }; 1239 1240 #define BTC_BT_RSSI_THMAX 4 1241 #define BTC_BT_AFH_GROUP 12 1242 1243 struct rtw89_btc_bt_link_info { 1244 struct rtw89_btc_u8_sta_chg profile_cnt; 1245 struct rtw89_btc_bool_sta_chg multi_link; 1246 struct rtw89_btc_bool_sta_chg relink; 1247 struct rtw89_btc_bt_hfp_desc hfp_desc; 1248 struct rtw89_btc_bt_hid_desc hid_desc; 1249 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1250 struct rtw89_btc_bt_pan_desc pan_desc; 1251 union rtw89_btc_bt_state_map status; 1252 1253 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1254 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1255 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1256 u8 afh_map[BTC_BT_AFH_GROUP]; 1257 1258 u32 role_sw: 1; 1259 u32 slave_role: 1; 1260 u32 afh_update: 1; 1261 u32 cqddr: 1; 1262 u32 rssi: 8; 1263 u32 tx_3m: 1; 1264 u32 rsvd: 19; 1265 }; 1266 1267 struct rtw89_btc_3rdcx_info { 1268 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1269 u8 hw_coex; 1270 u16 rsvd; 1271 }; 1272 1273 struct rtw89_btc_dm_emap { 1274 u32 init: 1; 1275 u32 pta_owner: 1; 1276 u32 wl_rfk_timeout: 1; 1277 u32 bt_rfk_timeout: 1; 1278 1279 u32 wl_fw_hang: 1; 1280 u32 offload_mismatch: 1; 1281 u32 cycle_hang: 1; 1282 u32 w1_hang: 1; 1283 1284 u32 b1_hang: 1; 1285 u32 tdma_no_sync: 1; 1286 u32 wl_slot_drift: 1; 1287 }; 1288 1289 union rtw89_btc_dm_error_map { 1290 u32 val; 1291 struct rtw89_btc_dm_emap map; 1292 }; 1293 1294 struct rtw89_btc_rf_para { 1295 u32 tx_pwr_freerun; 1296 u32 rx_gain_freerun; 1297 u32 tx_pwr_perpkt; 1298 u32 rx_gain_perpkt; 1299 }; 1300 1301 struct rtw89_btc_wl_info { 1302 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1303 struct rtw89_btc_wl_rfk_info rfk_info; 1304 struct rtw89_btc_wl_ver_info ver_info; 1305 struct rtw89_btc_wl_afh_info afh_info; 1306 struct rtw89_btc_wl_role_info role_info; 1307 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1308 struct rtw89_btc_wl_scan_info scan_info; 1309 struct rtw89_btc_wl_dbcc_info dbcc_info; 1310 struct rtw89_btc_rf_para rf_para; 1311 union rtw89_btc_wl_state_map status; 1312 1313 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1314 u8 rssi_level; 1315 1316 bool scbd_change; 1317 u32 scbd; 1318 }; 1319 1320 struct rtw89_btc_module { 1321 struct rtw89_btc_ant_info ant; 1322 u8 rfe_type; 1323 u8 cv; 1324 1325 u8 bt_solo: 1; 1326 u8 bt_pos: 1; 1327 u8 switch_type: 1; 1328 1329 u8 rsvd; 1330 }; 1331 1332 #define RTW89_BTC_DM_MAXSTEP 30 1333 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1334 1335 struct rtw89_btc_dm_step { 1336 u16 step[RTW89_BTC_DM_MAXSTEP]; 1337 u8 step_pos; 1338 bool step_ov; 1339 }; 1340 1341 struct rtw89_btc_init_info { 1342 struct rtw89_btc_module module; 1343 u8 wl_guard_ch; 1344 1345 u8 wl_only: 1; 1346 u8 wl_init_ok: 1; 1347 u8 dbcc_en: 1; 1348 u8 cx_other: 1; 1349 u8 bt_only: 1; 1350 1351 u16 rsvd; 1352 }; 1353 1354 struct rtw89_btc_wl_tx_limit_para { 1355 u16 enable; 1356 u32 tx_time; /* unit: us */ 1357 u16 tx_retry; 1358 }; 1359 1360 struct rtw89_btc_bt_scan_info { 1361 u16 win; 1362 u16 intvl; 1363 u32 enable: 1; 1364 u32 interlace: 1; 1365 u32 rsvd: 30; 1366 }; 1367 1368 enum rtw89_btc_bt_scan_type { 1369 BTC_SCAN_INQ = 0, 1370 BTC_SCAN_PAGE, 1371 BTC_SCAN_BLE, 1372 BTC_SCAN_INIT, 1373 BTC_SCAN_TV, 1374 BTC_SCAN_ADV, 1375 BTC_SCAN_MAX1, 1376 }; 1377 1378 struct rtw89_btc_bt_info { 1379 struct rtw89_btc_bt_link_info link_info; 1380 struct rtw89_btc_bt_scan_info scan_info[BTC_SCAN_MAX1]; 1381 struct rtw89_btc_bt_ver_info ver_info; 1382 struct rtw89_btc_bool_sta_chg enable; 1383 struct rtw89_btc_bool_sta_chg inq_pag; 1384 struct rtw89_btc_rf_para rf_para; 1385 union rtw89_btc_bt_rfk_info_map rfk_info; 1386 1387 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1388 1389 u32 scbd; 1390 u32 feature; 1391 1392 u32 mbx_avl: 1; 1393 u32 whql_test: 1; 1394 u32 igno_wl: 1; 1395 u32 reinit: 1; 1396 u32 ble_scan_en: 1; 1397 u32 btg_type: 1; 1398 u32 inq: 1; 1399 u32 pag: 1; 1400 u32 run_patch_code: 1; 1401 u32 hi_lna_rx: 1; 1402 u32 scan_rx_low_pri: 1; 1403 u32 rsvd: 21; 1404 }; 1405 1406 struct rtw89_btc_cx { 1407 struct rtw89_btc_wl_info wl; 1408 struct rtw89_btc_bt_info bt; 1409 struct rtw89_btc_3rdcx_info other; 1410 u32 state_map; 1411 u32 cnt_bt[BTC_BCNT_NUM]; 1412 u32 cnt_wl[BTC_WCNT_NUM]; 1413 }; 1414 1415 struct rtw89_btc_fbtc_tdma { 1416 u8 type; /* chip_info::fcxtdma_ver */ 1417 u8 rxflctrl; 1418 u8 txpause; 1419 u8 wtgle_n; 1420 u8 leak_n; 1421 u8 ext_ctrl; 1422 u8 rxflctrl_role; 1423 u8 option_ctrl; 1424 } __packed; 1425 1426 struct rtw89_btc_fbtc_tdma_v1 { 1427 u8 fver; /* chip_info::fcxtdma_ver */ 1428 u8 rsvd; 1429 __le16 rsvd1; 1430 struct rtw89_btc_fbtc_tdma tdma; 1431 } __packed; 1432 1433 #define CXMREG_MAX 30 1434 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1435 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1436 1437 enum rtw89_btc_bt_sta_counter { 1438 BTC_BCNT_RFK_REQ = 0, 1439 BTC_BCNT_RFK_GO = 1, 1440 BTC_BCNT_RFK_REJECT = 2, 1441 BTC_BCNT_RFK_FAIL = 3, 1442 BTC_BCNT_RFK_TIMEOUT = 4, 1443 BTC_BCNT_HI_TX = 5, 1444 BTC_BCNT_HI_RX = 6, 1445 BTC_BCNT_LO_TX = 7, 1446 BTC_BCNT_LO_RX = 8, 1447 BTC_BCNT_POLLUTED = 9, 1448 BTC_BCNT_STA_MAX 1449 }; 1450 1451 struct rtw89_btc_fbtc_rpt_ctrl { 1452 u16 fver; /* chip_info::fcxbtcrpt_ver */ 1453 u16 rpt_cnt; /* tmr counters */ 1454 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1455 u32 wl_fw_cx_offload; 1456 u32 wl_fw_ver; 1457 u32 rpt_enable; 1458 u32 rpt_para; /* ms */ 1459 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1460 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1461 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1462 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1463 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1464 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1465 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 1466 u32 c2h_cnt; /* fw send c2h counter */ 1467 u32 h2c_cnt; /* fw recv h2c counter */ 1468 } __packed; 1469 1470 struct rtw89_btc_fbtc_rpt_ctrl_info { 1471 __le32 cnt; /* fw report counter */ 1472 __le32 en; /* report map */ 1473 __le32 para; /* not used */ 1474 1475 __le32 cnt_c2h; /* fw send c2h counter */ 1476 __le32 cnt_h2c; /* fw recv h2c counter */ 1477 __le32 len_c2h; /* The total length of the last C2H */ 1478 1479 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1480 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1481 } __packed; 1482 1483 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 1484 __le32 cx_ver; /* match which driver's coex version */ 1485 __le32 cx_offload; 1486 __le32 fw_ver; 1487 } __packed; 1488 1489 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 1490 __le32 cnt_empty; /* a2dp empty count */ 1491 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 1492 __le32 cnt_tx; 1493 __le32 cnt_ack; 1494 __le32 cnt_nack; 1495 } __packed; 1496 1497 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 1498 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 1499 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 1500 __le32 cnt_recv; /* fw recv mailbox counter */ 1501 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 1502 } __packed; 1503 1504 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 1505 u8 fver; 1506 u8 rsvd; 1507 __le16 rsvd1; 1508 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 1509 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 1510 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1511 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 1512 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 1513 } __packed; 1514 1515 enum rtw89_fbtc_ext_ctrl_type { 1516 CXECTL_OFF = 0x0, /* tdma off */ 1517 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 1518 CXECTL_EXT = 0x2, 1519 CXECTL_MAX 1520 }; 1521 1522 union rtw89_btc_fbtc_rxflct { 1523 u8 val; 1524 u8 type: 3; 1525 u8 tgln_n: 5; 1526 }; 1527 1528 enum rtw89_btc_cxst_state { 1529 CXST_OFF = 0x0, 1530 CXST_B2W = 0x1, 1531 CXST_W1 = 0x2, 1532 CXST_W2 = 0x3, 1533 CXST_W2B = 0x4, 1534 CXST_B1 = 0x5, 1535 CXST_B2 = 0x6, 1536 CXST_B3 = 0x7, 1537 CXST_B4 = 0x8, 1538 CXST_LK = 0x9, 1539 CXST_BLK = 0xa, 1540 CXST_E2G = 0xb, 1541 CXST_E5G = 0xc, 1542 CXST_EBT = 0xd, 1543 CXST_ENULL = 0xe, 1544 CXST_WLK = 0xf, 1545 CXST_W1FDD = 0x10, 1546 CXST_B1FDD = 0x11, 1547 CXST_MAX = 0x12, 1548 }; 1549 1550 enum { 1551 CXBCN_ALL = 0x0, 1552 CXBCN_ALL_OK, 1553 CXBCN_BT_SLOT, 1554 CXBCN_BT_OK, 1555 CXBCN_MAX 1556 }; 1557 1558 enum btc_slot_type { 1559 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 1560 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 1561 CXSTYPE_NUM, 1562 }; 1563 1564 enum { /* TIME */ 1565 CXT_BT = 0x0, 1566 CXT_WL = 0x1, 1567 CXT_MAX 1568 }; 1569 1570 enum { /* TIME-A2DP */ 1571 CXT_FLCTRL_OFF = 0x0, 1572 CXT_FLCTRL_ON = 0x1, 1573 CXT_FLCTRL_MAX 1574 }; 1575 1576 enum { /* STEP TYPE */ 1577 CXSTEP_NONE = 0x0, 1578 CXSTEP_EVNT = 0x1, 1579 CXSTEP_SLOT = 0x2, 1580 CXSTEP_MAX, 1581 }; 1582 1583 #define BTC_DBG_MAX1 32 1584 struct rtw89_btc_fbtc_gpio_dbg { 1585 u8 fver; /* chip_info::fcxgpiodbg_ver */ 1586 u8 rsvd; 1587 u16 rsvd2; 1588 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 1589 u32 pre_state; /* the debug signal is 1 or 0 */ 1590 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 1591 } __packed; 1592 1593 struct rtw89_btc_fbtc_mreg_val { 1594 u8 fver; /* chip_info::fcxmreg_ver */ 1595 u8 reg_num; 1596 __le16 rsvd; 1597 __le32 mreg_val[CXMREG_MAX]; 1598 } __packed; 1599 1600 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 1601 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 1602 .offset = cpu_to_le32(__offset), } 1603 1604 struct rtw89_btc_fbtc_mreg { 1605 __le16 type; 1606 __le16 bytes; 1607 __le32 offset; 1608 } __packed; 1609 1610 struct rtw89_btc_fbtc_slot { 1611 __le16 dur; 1612 __le32 cxtbl; 1613 __le16 cxtype; 1614 } __packed; 1615 1616 struct rtw89_btc_fbtc_slots { 1617 u8 fver; /* chip_info::fcxslots_ver */ 1618 u8 tbl_num; 1619 __le16 rsvd; 1620 __le32 update_map; 1621 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1622 } __packed; 1623 1624 struct rtw89_btc_fbtc_step { 1625 u8 type; 1626 u8 val; 1627 __le16 difft; 1628 } __packed; 1629 1630 struct rtw89_btc_fbtc_steps { 1631 u8 fver; /* chip_info::fcxstep_ver */ 1632 u8 rsvd; 1633 __le16 cnt; 1634 __le16 pos_old; 1635 __le16 pos_new; 1636 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1637 } __packed; 1638 1639 struct rtw89_btc_fbtc_steps_v1 { 1640 u8 fver; 1641 u8 en; 1642 __le16 rsvd; 1643 __le32 cnt; 1644 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1645 } __packed; 1646 1647 struct rtw89_btc_fbtc_cysta { /* statistics for cycles */ 1648 u8 fver; /* chip_info::fcxcysta_ver */ 1649 u8 rsvd; 1650 __le16 cycles; /* total cycle number */ 1651 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 1652 __le16 a2dpept; /* a2dp empty cnt */ 1653 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 1654 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 1655 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 1656 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1657 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 1658 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 1659 __le16 tavg_a2dpept; /* avg a2dp empty time */ 1660 __le16 tmax_a2dpept; /* max a2dp empty time */ 1661 __le16 tavg_lk; /* avg leak-slot time */ 1662 __le16 tmax_lk; /* max leak-slot time */ 1663 __le32 slot_cnt[CXST_MAX]; /* slot count */ 1664 __le32 bcn_cnt[CXBCN_MAX]; 1665 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 1666 __le32 collision_cnt; /* counter for event/timer occur at same time */ 1667 __le32 skip_cnt; 1668 __le32 exception; 1669 __le32 except_cnt; 1670 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 1671 } __packed; 1672 1673 struct rtw89_btc_fbtc_fdd_try_info { 1674 __le16 cycles[CXT_FLCTRL_MAX]; 1675 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 1676 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 1677 } __packed; 1678 1679 struct rtw89_btc_fbtc_cycle_time_info { 1680 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 1681 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 1682 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1683 } __packed; 1684 1685 struct rtw89_btc_fbtc_a2dp_trx_stat { 1686 u8 empty_cnt; 1687 u8 retry_cnt; 1688 u8 tx_rate; 1689 u8 tx_cnt; 1690 u8 ack_cnt; 1691 u8 nack_cnt; 1692 u8 rsvd1; 1693 u8 rsvd2; 1694 } __packed; 1695 1696 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 1697 __le16 cnt; /* a2dp empty cnt */ 1698 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 1699 __le16 tavg; /* avg a2dp empty time */ 1700 __le16 tmax; /* max a2dp empty time */ 1701 } __packed; 1702 1703 struct rtw89_btc_fbtc_cycle_leak_info { 1704 __le32 cnt_rximr; /* the rximr occur at leak slot */ 1705 __le16 tavg; /* avg leak-slot time */ 1706 __le16 tmax; /* max leak-slot time */ 1707 } __packed; 1708 1709 struct rtw89_btc_fbtc_cysta_v1 { /* statistics for cycles */ 1710 u8 fver; 1711 u8 rsvd; 1712 __le16 cycles; /* total cycle number */ 1713 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 1714 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 1715 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 1716 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 1717 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 1718 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 1719 __le32 slot_cnt[CXST_MAX]; /* slot count */ 1720 __le32 bcn_cnt[CXBCN_MAX]; 1721 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 1722 __le32 skip_cnt; 1723 __le32 except_cnt; 1724 __le32 except_map; 1725 } __packed; 1726 1727 struct rtw89_btc_fbtc_cynullsta { /* cycle null statistics */ 1728 u8 fver; /* chip_info::fcxnullsta_ver */ 1729 u8 rsvd; 1730 __le16 rsvd2; 1731 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 1732 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 1733 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 1734 } __packed; 1735 1736 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 1737 u8 fver; /* chip_info::fcxnullsta_ver */ 1738 u8 rsvd; 1739 __le16 rsvd2; 1740 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 1741 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 1742 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 1743 } __packed; 1744 1745 struct rtw89_btc_fbtc_btver { 1746 u8 fver; /* chip_info::fcxbtver_ver */ 1747 u8 rsvd; 1748 __le16 rsvd2; 1749 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 1750 __le32 fw_ver; 1751 __le32 feature; 1752 } __packed; 1753 1754 struct rtw89_btc_fbtc_btscan { 1755 u8 fver; /* chip_info::fcxbtscan_ver */ 1756 u8 rsvd; 1757 __le16 rsvd2; 1758 u8 scan[6]; 1759 } __packed; 1760 1761 struct rtw89_btc_fbtc_btafh { 1762 u8 fver; /* chip_info::fcxbtafh_ver */ 1763 u8 rsvd; 1764 __le16 rsvd2; 1765 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 1766 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 1767 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 1768 } __packed; 1769 1770 struct rtw89_btc_fbtc_btdevinfo { 1771 u8 fver; /* chip_info::fcxbtdevinfo_ver */ 1772 u8 rsvd; 1773 __le16 vendor_id; 1774 __le32 dev_name; /* only 24 bits valid */ 1775 __le32 flush_time; 1776 } __packed; 1777 1778 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 1779 struct rtw89_btc_rf_trx_para { 1780 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 1781 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 1782 u8 bt_tx_power; /* decrease Tx power (dB) */ 1783 u8 bt_rx_gain; /* LNA constrain level */ 1784 }; 1785 1786 struct rtw89_btc_dm { 1787 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1788 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 1789 struct rtw89_btc_fbtc_tdma tdma; 1790 struct rtw89_btc_fbtc_tdma tdma_now; 1791 struct rtw89_mac_ax_coex_gnt gnt; 1792 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 1793 struct rtw89_btc_rf_trx_para rf_trx_para; 1794 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 1795 struct rtw89_btc_dm_step dm_step; 1796 struct rtw89_btc_wl_scc_ctrl wl_scc; 1797 union rtw89_btc_dm_error_map error; 1798 u32 cnt_dm[BTC_DCNT_NUM]; 1799 u32 cnt_notify[BTC_NCNT_NUM]; 1800 1801 u32 update_slot_map; 1802 u32 set_ant_path; 1803 1804 u32 wl_only: 1; 1805 u32 wl_fw_cx_offload: 1; 1806 u32 freerun: 1; 1807 u32 wl_ps_ctrl: 2; 1808 u32 wl_mimo_ps: 1; 1809 u32 leak_ap: 1; 1810 u32 noisy_level: 3; 1811 u32 coex_info_map: 8; 1812 u32 bt_only: 1; 1813 u32 wl_btg_rx: 1; 1814 u32 trx_para_level: 8; 1815 u32 wl_stb_chg: 1; 1816 u32 pta_owner: 1; 1817 u32 tdma_instant_excute: 1; 1818 u32 rsvd: 1; 1819 1820 u16 slot_dur[CXST_MAX]; 1821 1822 u8 run_reason; 1823 u8 run_action; 1824 }; 1825 1826 struct rtw89_btc_ctrl { 1827 u32 manual: 1; 1828 u32 igno_bt: 1; 1829 u32 always_freerun: 1; 1830 u32 trace_step: 16; 1831 u32 rsvd: 12; 1832 }; 1833 1834 struct rtw89_btc_dbg { 1835 /* cmd "rb" */ 1836 bool rb_done; 1837 u32 rb_val; 1838 }; 1839 1840 enum rtw89_btc_btf_fw_event { 1841 BTF_EVNT_RPT = 0, 1842 BTF_EVNT_BT_INFO = 1, 1843 BTF_EVNT_BT_SCBD = 2, 1844 BTF_EVNT_BT_REG = 3, 1845 BTF_EVNT_CX_RUNINFO = 4, 1846 BTF_EVNT_BT_PSD = 5, 1847 BTF_EVNT_BUF_OVERFLOW, 1848 BTF_EVNT_C2H_LOOPBACK, 1849 BTF_EVNT_MAX, 1850 }; 1851 1852 enum btf_fw_event_report { 1853 BTC_RPT_TYPE_CTRL = 0x0, 1854 BTC_RPT_TYPE_TDMA, 1855 BTC_RPT_TYPE_SLOT, 1856 BTC_RPT_TYPE_CYSTA, 1857 BTC_RPT_TYPE_STEP, 1858 BTC_RPT_TYPE_NULLSTA, 1859 BTC_RPT_TYPE_MREG, 1860 BTC_RPT_TYPE_GPIO_DBG, 1861 BTC_RPT_TYPE_BT_VER, 1862 BTC_RPT_TYPE_BT_SCAN, 1863 BTC_RPT_TYPE_BT_AFH, 1864 BTC_RPT_TYPE_BT_DEVICE, 1865 BTC_RPT_TYPE_TEST, 1866 BTC_RPT_TYPE_MAX = 31 1867 }; 1868 1869 enum rtw_btc_btf_reg_type { 1870 REG_MAC = 0x0, 1871 REG_BB = 0x1, 1872 REG_RF = 0x2, 1873 REG_BT_RF = 0x3, 1874 REG_BT_MODEM = 0x4, 1875 REG_BT_BLUEWIZE = 0x5, 1876 REG_BT_VENDOR = 0x6, 1877 REG_BT_LE = 0x7, 1878 REG_MAX_TYPE, 1879 }; 1880 1881 struct rtw89_btc_rpt_cmn_info { 1882 u32 rx_cnt; 1883 u32 rx_len; 1884 u32 req_len; /* expected rsp len */ 1885 u8 req_fver; /* expected rsp fver */ 1886 u8 rsp_fver; /* fver from fw */ 1887 u8 valid; 1888 } __packed; 1889 1890 struct rtw89_btc_report_ctrl_state { 1891 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1892 union { 1893 struct rtw89_btc_fbtc_rpt_ctrl finfo; /* info from fw for 52A*/ 1894 struct rtw89_btc_fbtc_rpt_ctrl_v1 finfo_v1; /* info from fw for 52C*/ 1895 }; 1896 }; 1897 1898 struct rtw89_btc_rpt_fbtc_tdma { 1899 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1900 union { 1901 struct rtw89_btc_fbtc_tdma finfo; /* info from fw */ 1902 struct rtw89_btc_fbtc_tdma_v1 finfo_v1; /* info from fw for 52C*/ 1903 }; 1904 }; 1905 1906 struct rtw89_btc_rpt_fbtc_slots { 1907 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1908 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 1909 }; 1910 1911 struct rtw89_btc_rpt_fbtc_cysta { 1912 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1913 union { 1914 struct rtw89_btc_fbtc_cysta finfo; /* info from fw for 52A*/ 1915 struct rtw89_btc_fbtc_cysta_v1 finfo_v1; /* info from fw for 52C*/ 1916 }; 1917 }; 1918 1919 struct rtw89_btc_rpt_fbtc_step { 1920 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1921 union { 1922 struct rtw89_btc_fbtc_steps finfo; /* info from fw */ 1923 struct rtw89_btc_fbtc_steps_v1 finfo_v1; /* info from fw */ 1924 }; 1925 }; 1926 1927 struct rtw89_btc_rpt_fbtc_nullsta { 1928 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1929 union { 1930 struct rtw89_btc_fbtc_cynullsta finfo; /* info from fw */ 1931 struct rtw89_btc_fbtc_cynullsta_v1 finfo_v1; /* info from fw */ 1932 }; 1933 }; 1934 1935 struct rtw89_btc_rpt_fbtc_mreg { 1936 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1937 struct rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 1938 }; 1939 1940 struct rtw89_btc_rpt_fbtc_gpio_dbg { 1941 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1942 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 1943 }; 1944 1945 struct rtw89_btc_rpt_fbtc_btver { 1946 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1947 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 1948 }; 1949 1950 struct rtw89_btc_rpt_fbtc_btscan { 1951 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1952 struct rtw89_btc_fbtc_btscan finfo; /* info from fw */ 1953 }; 1954 1955 struct rtw89_btc_rpt_fbtc_btafh { 1956 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1957 struct rtw89_btc_fbtc_btafh finfo; /* info from fw */ 1958 }; 1959 1960 struct rtw89_btc_rpt_fbtc_btdev { 1961 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1962 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 1963 }; 1964 1965 enum rtw89_btc_btfre_type { 1966 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 1967 BTFRE_UNDEF_TYPE, 1968 BTFRE_EXCEPTION, 1969 BTFRE_MAX, 1970 }; 1971 1972 struct rtw89_btc_btf_fwinfo { 1973 u32 cnt_c2h; 1974 u32 cnt_h2c; 1975 u32 cnt_h2c_fail; 1976 u32 event[BTF_EVNT_MAX]; 1977 1978 u32 err[BTFRE_MAX]; 1979 u32 len_mismch; 1980 u32 fver_mismch; 1981 u32 rpt_en_map; 1982 1983 struct rtw89_btc_report_ctrl_state rpt_ctrl; 1984 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 1985 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 1986 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 1987 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 1988 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 1989 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 1990 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 1991 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 1992 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 1993 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 1994 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 1995 }; 1996 1997 #define RTW89_BTC_POLICY_MAXLEN 512 1998 1999 struct rtw89_btc { 2000 struct rtw89_btc_cx cx; 2001 struct rtw89_btc_dm dm; 2002 struct rtw89_btc_ctrl ctrl; 2003 struct rtw89_btc_module mdinfo; 2004 struct rtw89_btc_btf_fwinfo fwinfo; 2005 struct rtw89_btc_dbg dbg; 2006 2007 struct work_struct eapol_notify_work; 2008 struct work_struct arp_notify_work; 2009 struct work_struct dhcp_notify_work; 2010 struct work_struct icmp_notify_work; 2011 2012 u32 bt_req_len; 2013 2014 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 2015 u16 policy_len; 2016 u16 policy_type; 2017 bool bt_req_en; 2018 bool update_policy_force; 2019 bool lps; 2020 }; 2021 2022 enum rtw89_ra_mode { 2023 RTW89_RA_MODE_CCK = BIT(0), 2024 RTW89_RA_MODE_OFDM = BIT(1), 2025 RTW89_RA_MODE_HT = BIT(2), 2026 RTW89_RA_MODE_VHT = BIT(3), 2027 RTW89_RA_MODE_HE = BIT(4), 2028 }; 2029 2030 enum rtw89_ra_report_mode { 2031 RTW89_RA_RPT_MODE_LEGACY, 2032 RTW89_RA_RPT_MODE_HT, 2033 RTW89_RA_RPT_MODE_VHT, 2034 RTW89_RA_RPT_MODE_HE, 2035 }; 2036 2037 enum rtw89_dig_noisy_level { 2038 RTW89_DIG_NOISY_LEVEL0 = -1, 2039 RTW89_DIG_NOISY_LEVEL1 = 0, 2040 RTW89_DIG_NOISY_LEVEL2 = 1, 2041 RTW89_DIG_NOISY_LEVEL3 = 2, 2042 RTW89_DIG_NOISY_LEVEL_MAX = 3, 2043 }; 2044 2045 enum rtw89_gi_ltf { 2046 RTW89_GILTF_LGI_4XHE32 = 0, 2047 RTW89_GILTF_SGI_4XHE08 = 1, 2048 RTW89_GILTF_2XHE16 = 2, 2049 RTW89_GILTF_2XHE08 = 3, 2050 RTW89_GILTF_1XHE16 = 4, 2051 RTW89_GILTF_1XHE08 = 5, 2052 RTW89_GILTF_MAX 2053 }; 2054 2055 enum rtw89_rx_frame_type { 2056 RTW89_RX_TYPE_MGNT = 0, 2057 RTW89_RX_TYPE_CTRL = 1, 2058 RTW89_RX_TYPE_DATA = 2, 2059 RTW89_RX_TYPE_RSVD = 3, 2060 }; 2061 2062 struct rtw89_ra_info { 2063 u8 is_dis_ra:1; 2064 /* Bit0 : CCK 2065 * Bit1 : OFDM 2066 * Bit2 : HT 2067 * Bit3 : VHT 2068 * Bit4 : HE 2069 */ 2070 u8 mode_ctrl:5; 2071 u8 bw_cap:2; 2072 u8 macid; 2073 u8 dcm_cap:1; 2074 u8 er_cap:1; 2075 u8 init_rate_lv:2; 2076 u8 upd_all:1; 2077 u8 en_sgi:1; 2078 u8 ldpc_cap:1; 2079 u8 stbc_cap:1; 2080 u8 ss_num:3; 2081 u8 giltf:3; 2082 u8 upd_bw_nss_mask:1; 2083 u8 upd_mask:1; 2084 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 2085 /* BFee CSI */ 2086 u8 band_num; 2087 u8 ra_csi_rate_en:1; 2088 u8 fixed_csi_rate_en:1; 2089 u8 cr_tbl_sel:1; 2090 u8 fix_giltf_en:1; 2091 u8 fix_giltf:3; 2092 u8 rsvd2:1; 2093 u8 csi_mcs_ss_idx; 2094 u8 csi_mode:2; 2095 u8 csi_gi_ltf:3; 2096 u8 csi_bw:3; 2097 }; 2098 2099 #define RTW89_PPDU_MAX_USR 4 2100 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 2101 #define RTW89_PPDU_MAC_INFO_SIZE 8 2102 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 2103 2104 #define RTW89_MAX_RX_AGG_NUM 64 2105 #define RTW89_MAX_TX_AGG_NUM 128 2106 2107 struct rtw89_ampdu_params { 2108 u16 agg_num; 2109 bool amsdu; 2110 }; 2111 2112 struct rtw89_ra_report { 2113 struct rate_info txrate; 2114 u32 bit_rate; 2115 u16 hw_rate; 2116 bool might_fallback_legacy; 2117 }; 2118 2119 DECLARE_EWMA(rssi, 10, 16); 2120 2121 struct rtw89_ba_cam_entry { 2122 struct list_head list; 2123 u8 tid; 2124 }; 2125 2126 #define RTW89_MAX_ADDR_CAM_NUM 128 2127 #define RTW89_MAX_BSSID_CAM_NUM 20 2128 #define RTW89_MAX_SEC_CAM_NUM 128 2129 #define RTW89_MAX_BA_CAM_NUM 8 2130 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 2131 2132 struct rtw89_addr_cam_entry { 2133 u8 addr_cam_idx; 2134 u8 offset; 2135 u8 len; 2136 u8 valid : 1; 2137 u8 addr_mask : 6; 2138 u8 wapi : 1; 2139 u8 mask_sel : 2; 2140 u8 bssid_cam_idx: 6; 2141 2142 u8 sec_ent_mode; 2143 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 2144 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 2145 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 2146 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 2147 }; 2148 2149 struct rtw89_bssid_cam_entry { 2150 u8 bssid[ETH_ALEN]; 2151 u8 phy_idx; 2152 u8 bssid_cam_idx; 2153 u8 offset; 2154 u8 len; 2155 u8 valid : 1; 2156 u8 num; 2157 }; 2158 2159 struct rtw89_sec_cam_entry { 2160 u8 sec_cam_idx; 2161 u8 offset; 2162 u8 len; 2163 u8 type : 4; 2164 u8 ext_key : 1; 2165 u8 spp_mode : 1; 2166 /* 256 bits */ 2167 u8 key[32]; 2168 }; 2169 2170 struct rtw89_sta { 2171 u8 mac_id; 2172 bool disassoc; 2173 struct rtw89_dev *rtwdev; 2174 struct rtw89_vif *rtwvif; 2175 struct rtw89_ra_info ra; 2176 struct rtw89_ra_report ra_report; 2177 int max_agg_wait; 2178 u8 prev_rssi; 2179 struct ewma_rssi avg_rssi; 2180 struct ewma_rssi rssi[RF_PATH_MAX]; 2181 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 2182 struct ieee80211_rx_status rx_status; 2183 u16 rx_hw_rate; 2184 __le32 htc_template; 2185 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 2186 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 2187 struct list_head ba_cam_list; 2188 2189 bool use_cfg_mask; 2190 struct cfg80211_bitrate_mask mask; 2191 2192 bool cctl_tx_time; 2193 u32 ampdu_max_time:4; 2194 bool cctl_tx_retry_limit; 2195 u32 data_tx_cnt_lmt:6; 2196 }; 2197 2198 struct rtw89_efuse { 2199 bool valid; 2200 bool power_k_valid; 2201 u8 xtal_cap; 2202 u8 addr[ETH_ALEN]; 2203 u8 rfe_type; 2204 char country_code[2]; 2205 }; 2206 2207 struct rtw89_phy_rate_pattern { 2208 u64 ra_mask; 2209 u16 rate; 2210 u8 ra_mode; 2211 bool enable; 2212 }; 2213 2214 #define RTW89_P2P_MAX_NOA_NUM 2 2215 2216 struct rtw89_vif { 2217 struct list_head list; 2218 struct rtw89_dev *rtwdev; 2219 u8 mac_id; 2220 u8 port; 2221 u8 mac_addr[ETH_ALEN]; 2222 u8 bssid[ETH_ALEN]; 2223 u8 phy_idx; 2224 u8 mac_idx; 2225 u8 net_type; 2226 u8 wifi_role; 2227 u8 self_role; 2228 u8 wmm; 2229 u8 bcn_hit_cond; 2230 u8 hit_rule; 2231 u8 last_noa_nr; 2232 bool trigger; 2233 bool lsig_txop; 2234 u8 tgt_ind; 2235 u8 frm_tgt_ind; 2236 bool wowlan_pattern; 2237 bool wowlan_uc; 2238 bool wowlan_magic; 2239 bool is_hesta; 2240 bool last_a_ctrl; 2241 struct work_struct update_beacon_work; 2242 struct rtw89_addr_cam_entry addr_cam; 2243 struct rtw89_bssid_cam_entry bssid_cam; 2244 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 2245 struct rtw89_traffic_stats stats; 2246 struct rtw89_phy_rate_pattern rate_pattern; 2247 struct cfg80211_scan_request *scan_req; 2248 struct ieee80211_scan_ies *scan_ies; 2249 }; 2250 2251 enum rtw89_lv1_rcvy_step { 2252 RTW89_LV1_RCVY_STEP_1, 2253 RTW89_LV1_RCVY_STEP_2, 2254 }; 2255 2256 struct rtw89_hci_ops { 2257 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 2258 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 2259 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 2260 void (*reset)(struct rtw89_dev *rtwdev); 2261 int (*start)(struct rtw89_dev *rtwdev); 2262 void (*stop)(struct rtw89_dev *rtwdev); 2263 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 2264 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 2265 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 2266 2267 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 2268 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 2269 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 2270 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 2271 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 2272 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 2273 2274 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 2275 int (*mac_post_init)(struct rtw89_dev *rtwdev); 2276 int (*deinit)(struct rtw89_dev *rtwdev); 2277 2278 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 2279 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 2280 void (*dump_err_status)(struct rtw89_dev *rtwdev); 2281 int (*napi_poll)(struct napi_struct *napi, int budget); 2282 2283 /* Deal with locks inside recovery_start and recovery_complete callbacks 2284 * by hci instance, and handle things which need to consider under SER. 2285 * e.g. turn on/off interrupts except for the one for halt notification. 2286 */ 2287 void (*recovery_start)(struct rtw89_dev *rtwdev); 2288 void (*recovery_complete)(struct rtw89_dev *rtwdev); 2289 }; 2290 2291 struct rtw89_hci_info { 2292 const struct rtw89_hci_ops *ops; 2293 enum rtw89_hci_type type; 2294 u32 rpwm_addr; 2295 u32 cpwm_addr; 2296 bool paused; 2297 }; 2298 2299 struct rtw89_chip_ops { 2300 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 2301 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 2302 void (*bb_reset)(struct rtw89_dev *rtwdev, 2303 enum rtw89_phy_idx phy_idx); 2304 void (*bb_sethw)(struct rtw89_dev *rtwdev); 2305 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2306 u32 addr, u32 mask); 2307 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2308 u32 addr, u32 mask, u32 data); 2309 void (*set_channel)(struct rtw89_dev *rtwdev, 2310 const struct rtw89_chan *chan, 2311 enum rtw89_mac_idx mac_idx, 2312 enum rtw89_phy_idx phy_idx); 2313 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 2314 struct rtw89_channel_help_params *p, 2315 const struct rtw89_chan *chan, 2316 enum rtw89_mac_idx mac_idx, 2317 enum rtw89_phy_idx phy_idx); 2318 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map); 2319 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 2320 void (*fem_setup)(struct rtw89_dev *rtwdev); 2321 void (*rfk_init)(struct rtw89_dev *rtwdev); 2322 void (*rfk_channel)(struct rtw89_dev *rtwdev); 2323 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 2324 enum rtw89_phy_idx phy_idx); 2325 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 2326 void (*rfk_track)(struct rtw89_dev *rtwdev); 2327 void (*power_trim)(struct rtw89_dev *rtwdev); 2328 void (*set_txpwr)(struct rtw89_dev *rtwdev, 2329 const struct rtw89_chan *chan, 2330 enum rtw89_phy_idx phy_idx); 2331 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 2332 enum rtw89_phy_idx phy_idx); 2333 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 2334 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 2335 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg); 2336 void (*query_ppdu)(struct rtw89_dev *rtwdev, 2337 struct rtw89_rx_phy_ppdu *phy_ppdu, 2338 struct ieee80211_rx_status *status); 2339 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en); 2340 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 2341 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 2342 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 2343 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 2344 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 2345 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 2346 struct rtw89_tx_desc_info *desc_info, 2347 void *txdesc); 2348 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 2349 struct rtw89_tx_desc_info *desc_info, 2350 void *txdesc); 2351 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 2352 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 2353 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 2354 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 2355 u32 *tx_en, enum rtw89_sch_tx_sel sel); 2356 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 2357 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 2358 struct rtw89_vif *rtwvif, 2359 struct rtw89_sta *rtwsta); 2360 2361 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 2362 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 2363 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 2364 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 2365 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 2366 void (*btc_bt_aci_imp)(struct rtw89_dev *rtwdev); 2367 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 2368 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 2369 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 2370 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 2371 }; 2372 2373 enum rtw89_dma_ch { 2374 RTW89_DMA_ACH0 = 0, 2375 RTW89_DMA_ACH1 = 1, 2376 RTW89_DMA_ACH2 = 2, 2377 RTW89_DMA_ACH3 = 3, 2378 RTW89_DMA_ACH4 = 4, 2379 RTW89_DMA_ACH5 = 5, 2380 RTW89_DMA_ACH6 = 6, 2381 RTW89_DMA_ACH7 = 7, 2382 RTW89_DMA_B0MG = 8, 2383 RTW89_DMA_B0HI = 9, 2384 RTW89_DMA_B1MG = 10, 2385 RTW89_DMA_B1HI = 11, 2386 RTW89_DMA_H2C = 12, 2387 RTW89_DMA_CH_NUM = 13 2388 }; 2389 2390 enum rtw89_qta_mode { 2391 RTW89_QTA_SCC, 2392 RTW89_QTA_DLFW, 2393 2394 /* keep last */ 2395 RTW89_QTA_INVALID, 2396 }; 2397 2398 struct rtw89_hfc_ch_cfg { 2399 u16 min; 2400 u16 max; 2401 #define grp_0 0 2402 #define grp_1 1 2403 #define grp_num 2 2404 u8 grp; 2405 }; 2406 2407 struct rtw89_hfc_ch_info { 2408 u16 aval; 2409 u16 used; 2410 }; 2411 2412 struct rtw89_hfc_pub_cfg { 2413 u16 grp0; 2414 u16 grp1; 2415 u16 pub_max; 2416 u16 wp_thrd; 2417 }; 2418 2419 struct rtw89_hfc_pub_info { 2420 u16 g0_used; 2421 u16 g1_used; 2422 u16 g0_aval; 2423 u16 g1_aval; 2424 u16 pub_aval; 2425 u16 wp_aval; 2426 }; 2427 2428 struct rtw89_hfc_prec_cfg { 2429 u16 ch011_prec; 2430 u16 h2c_prec; 2431 u16 wp_ch07_prec; 2432 u16 wp_ch811_prec; 2433 u8 ch011_full_cond; 2434 u8 h2c_full_cond; 2435 u8 wp_ch07_full_cond; 2436 u8 wp_ch811_full_cond; 2437 }; 2438 2439 struct rtw89_hfc_param { 2440 bool en; 2441 bool h2c_en; 2442 u8 mode; 2443 const struct rtw89_hfc_ch_cfg *ch_cfg; 2444 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 2445 struct rtw89_hfc_pub_cfg pub_cfg; 2446 struct rtw89_hfc_pub_info pub_info; 2447 struct rtw89_hfc_prec_cfg prec_cfg; 2448 }; 2449 2450 struct rtw89_hfc_param_ini { 2451 const struct rtw89_hfc_ch_cfg *ch_cfg; 2452 const struct rtw89_hfc_pub_cfg *pub_cfg; 2453 const struct rtw89_hfc_prec_cfg *prec_cfg; 2454 u8 mode; 2455 }; 2456 2457 struct rtw89_dle_size { 2458 u16 pge_size; 2459 u16 lnk_pge_num; 2460 u16 unlnk_pge_num; 2461 }; 2462 2463 struct rtw89_wde_quota { 2464 u16 hif; 2465 u16 wcpu; 2466 u16 pkt_in; 2467 u16 cpu_io; 2468 }; 2469 2470 struct rtw89_ple_quota { 2471 u16 cma0_tx; 2472 u16 cma1_tx; 2473 u16 c2h; 2474 u16 h2c; 2475 u16 wcpu; 2476 u16 mpdu_proc; 2477 u16 cma0_dma; 2478 u16 cma1_dma; 2479 u16 bb_rpt; 2480 u16 wd_rel; 2481 u16 cpu_io; 2482 u16 tx_rpt; 2483 }; 2484 2485 struct rtw89_dle_mem { 2486 enum rtw89_qta_mode mode; 2487 const struct rtw89_dle_size *wde_size; 2488 const struct rtw89_dle_size *ple_size; 2489 const struct rtw89_wde_quota *wde_min_qt; 2490 const struct rtw89_wde_quota *wde_max_qt; 2491 const struct rtw89_ple_quota *ple_min_qt; 2492 const struct rtw89_ple_quota *ple_max_qt; 2493 }; 2494 2495 struct rtw89_reg_def { 2496 u32 addr; 2497 u32 mask; 2498 }; 2499 2500 struct rtw89_reg2_def { 2501 u32 addr; 2502 u32 data; 2503 }; 2504 2505 struct rtw89_reg3_def { 2506 u32 addr; 2507 u32 mask; 2508 u32 data; 2509 }; 2510 2511 struct rtw89_reg5_def { 2512 u8 flag; /* recognized by parsers */ 2513 u8 path; 2514 u32 addr; 2515 u32 mask; 2516 u32 data; 2517 }; 2518 2519 struct rtw89_phy_table { 2520 const struct rtw89_reg2_def *regs; 2521 u32 n_regs; 2522 enum rtw89_rf_path rf_path; 2523 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 2524 enum rtw89_rf_path rf_path, void *data); 2525 }; 2526 2527 struct rtw89_txpwr_table { 2528 const void *data; 2529 u32 size; 2530 void (*load)(struct rtw89_dev *rtwdev, 2531 const struct rtw89_txpwr_table *tbl); 2532 }; 2533 2534 struct rtw89_page_regs { 2535 u32 hci_fc_ctrl; 2536 u32 ch_page_ctrl; 2537 u32 ach_page_ctrl; 2538 u32 ach_page_info; 2539 u32 pub_page_info3; 2540 u32 pub_page_ctrl1; 2541 u32 pub_page_ctrl2; 2542 u32 pub_page_info1; 2543 u32 pub_page_info2; 2544 u32 wp_page_ctrl1; 2545 u32 wp_page_ctrl2; 2546 u32 wp_page_info1; 2547 }; 2548 2549 struct rtw89_imr_info { 2550 u32 wdrls_imr_set; 2551 u32 wsec_imr_reg; 2552 u32 wsec_imr_set; 2553 u32 mpdu_tx_imr_set; 2554 u32 mpdu_rx_imr_set; 2555 u32 sta_sch_imr_set; 2556 u32 txpktctl_imr_b0_reg; 2557 u32 txpktctl_imr_b0_clr; 2558 u32 txpktctl_imr_b0_set; 2559 u32 txpktctl_imr_b1_reg; 2560 u32 txpktctl_imr_b1_clr; 2561 u32 txpktctl_imr_b1_set; 2562 u32 wde_imr_clr; 2563 u32 wde_imr_set; 2564 u32 ple_imr_clr; 2565 u32 ple_imr_set; 2566 u32 host_disp_imr_clr; 2567 u32 host_disp_imr_set; 2568 u32 cpu_disp_imr_clr; 2569 u32 cpu_disp_imr_set; 2570 u32 other_disp_imr_clr; 2571 u32 other_disp_imr_set; 2572 u32 bbrpt_com_err_imr_reg; 2573 u32 bbrpt_chinfo_err_imr_reg; 2574 u32 bbrpt_err_imr_set; 2575 u32 bbrpt_dfs_err_imr_reg; 2576 u32 ptcl_imr_clr; 2577 u32 ptcl_imr_set; 2578 u32 cdma_imr_0_reg; 2579 u32 cdma_imr_0_clr; 2580 u32 cdma_imr_0_set; 2581 u32 cdma_imr_1_reg; 2582 u32 cdma_imr_1_clr; 2583 u32 cdma_imr_1_set; 2584 u32 phy_intf_imr_reg; 2585 u32 phy_intf_imr_clr; 2586 u32 phy_intf_imr_set; 2587 u32 rmac_imr_reg; 2588 u32 rmac_imr_clr; 2589 u32 rmac_imr_set; 2590 u32 tmac_imr_reg; 2591 u32 tmac_imr_clr; 2592 u32 tmac_imr_set; 2593 }; 2594 2595 struct rtw89_rrsr_cfgs { 2596 struct rtw89_reg3_def ref_rate; 2597 struct rtw89_reg3_def rsc; 2598 }; 2599 2600 struct rtw89_dig_regs { 2601 u32 seg0_pd_reg; 2602 u32 pd_lower_bound_mask; 2603 u32 pd_spatial_reuse_en; 2604 struct rtw89_reg_def p0_lna_init; 2605 struct rtw89_reg_def p1_lna_init; 2606 struct rtw89_reg_def p0_tia_init; 2607 struct rtw89_reg_def p1_tia_init; 2608 struct rtw89_reg_def p0_rxb_init; 2609 struct rtw89_reg_def p1_rxb_init; 2610 struct rtw89_reg_def p0_p20_pagcugc_en; 2611 struct rtw89_reg_def p0_s20_pagcugc_en; 2612 struct rtw89_reg_def p1_p20_pagcugc_en; 2613 struct rtw89_reg_def p1_s20_pagcugc_en; 2614 }; 2615 2616 struct rtw89_chip_info { 2617 enum rtw89_core_chip_id chip_id; 2618 const struct rtw89_chip_ops *ops; 2619 const char *fw_name; 2620 u32 fifo_size; 2621 u32 dle_scc_rsvd_size; 2622 u16 max_amsdu_limit; 2623 bool dis_2g_40m_ul_ofdma; 2624 u32 rsvd_ple_ofst; 2625 const struct rtw89_hfc_param_ini *hfc_param_ini; 2626 const struct rtw89_dle_mem *dle_mem; 2627 u32 rf_base_addr[2]; 2628 u8 support_chanctx_num; 2629 u8 support_bands; 2630 bool support_bw160; 2631 bool hw_sec_hdr; 2632 u8 rf_path_num; 2633 u8 tx_nss; 2634 u8 rx_nss; 2635 u8 acam_num; 2636 u8 bcam_num; 2637 u8 scam_num; 2638 u8 bacam_num; 2639 u8 bacam_dynamic_num; 2640 bool bacam_v1; 2641 2642 u8 sec_ctrl_efuse_size; 2643 u32 physical_efuse_size; 2644 u32 logical_efuse_size; 2645 u32 limit_efuse_size; 2646 u32 dav_phy_efuse_size; 2647 u32 dav_log_efuse_size; 2648 u32 phycap_addr; 2649 u32 phycap_size; 2650 2651 const struct rtw89_pwr_cfg * const *pwr_on_seq; 2652 const struct rtw89_pwr_cfg * const *pwr_off_seq; 2653 const struct rtw89_phy_table *bb_table; 2654 const struct rtw89_phy_table *bb_gain_table; 2655 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 2656 const struct rtw89_phy_table *nctl_table; 2657 const struct rtw89_txpwr_table *byr_table; 2658 const struct rtw89_phy_dig_gain_table *dig_table; 2659 const struct rtw89_dig_regs *dig_regs; 2660 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 2661 const s8 (*txpwr_lmt_2g)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 2662 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2663 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 2664 const s8 (*txpwr_lmt_5g)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 2665 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2666 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 2667 const s8 (*txpwr_lmt_6g)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 2668 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2669 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 2670 const s8 (*txpwr_lmt_ru_2g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2671 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 2672 const s8 (*txpwr_lmt_ru_5g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2673 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 2674 const s8 (*txpwr_lmt_ru_6g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2675 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 2676 2677 u8 txpwr_factor_rf; 2678 u8 txpwr_factor_mac; 2679 2680 u32 para_ver; 2681 u32 wlcx_desired; 2682 u8 btcx_desired; 2683 u8 scbd; 2684 u8 mailbox; 2685 u16 btc_fwinfo_buf; 2686 2687 u8 fcxbtcrpt_ver; 2688 u8 fcxtdma_ver; 2689 u8 fcxslots_ver; 2690 u8 fcxcysta_ver; 2691 u8 fcxstep_ver; 2692 u8 fcxnullsta_ver; 2693 u8 fcxmreg_ver; 2694 u8 fcxgpiodbg_ver; 2695 u8 fcxbtver_ver; 2696 u8 fcxbtscan_ver; 2697 u8 fcxbtafh_ver; 2698 u8 fcxbtdevinfo_ver; 2699 2700 u8 afh_guard_ch; 2701 const u8 *wl_rssi_thres; 2702 const u8 *bt_rssi_thres; 2703 u8 rssi_tol; 2704 2705 u8 mon_reg_num; 2706 const struct rtw89_btc_fbtc_mreg *mon_reg; 2707 u8 rf_para_ulink_num; 2708 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 2709 u8 rf_para_dlink_num; 2710 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 2711 u8 ps_mode_supported; 2712 u8 low_power_hci_modes; 2713 2714 u32 h2c_cctl_func_id; 2715 u32 hci_func_en_addr; 2716 u32 h2c_desc_size; 2717 u32 txwd_body_size; 2718 u32 h2c_ctrl_reg; 2719 const u32 *h2c_regs; 2720 u32 c2h_ctrl_reg; 2721 const u32 *c2h_regs; 2722 const struct rtw89_page_regs *page_regs; 2723 const struct rtw89_reg_def *dcfo_comp; 2724 u8 dcfo_comp_sft; 2725 const struct rtw89_imr_info *imr_info; 2726 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 2727 u32 dma_ch_mask; 2728 }; 2729 2730 union rtw89_bus_info { 2731 const struct rtw89_pci_info *pci; 2732 }; 2733 2734 struct rtw89_driver_info { 2735 const struct rtw89_chip_info *chip; 2736 union rtw89_bus_info bus; 2737 }; 2738 2739 enum rtw89_hcifc_mode { 2740 RTW89_HCIFC_POH = 0, 2741 RTW89_HCIFC_STF = 1, 2742 RTW89_HCIFC_SDIO = 2, 2743 2744 /* keep last */ 2745 RTW89_HCIFC_MODE_INVALID, 2746 }; 2747 2748 struct rtw89_dle_info { 2749 enum rtw89_qta_mode qta_mode; 2750 u16 wde_pg_size; 2751 u16 ple_pg_size; 2752 u16 c0_rx_qta; 2753 u16 c1_rx_qta; 2754 }; 2755 2756 enum rtw89_host_rpr_mode { 2757 RTW89_RPR_MODE_POH = 0, 2758 RTW89_RPR_MODE_STF 2759 }; 2760 2761 struct rtw89_mac_info { 2762 struct rtw89_dle_info dle_info; 2763 struct rtw89_hfc_param hfc_param; 2764 enum rtw89_qta_mode qta_mode; 2765 u8 rpwm_seq_num; 2766 u8 cpwm_seq_num; 2767 }; 2768 2769 enum rtw89_fw_type { 2770 RTW89_FW_NORMAL = 1, 2771 RTW89_FW_WOWLAN = 3, 2772 }; 2773 2774 enum rtw89_fw_feature { 2775 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 2776 RTW89_FW_FEATURE_SCAN_OFFLOAD, 2777 RTW89_FW_FEATURE_TX_WAKE, 2778 RTW89_FW_FEATURE_CRASH_TRIGGER, 2779 RTW89_FW_FEATURE_PACKET_DROP, 2780 RTW89_FW_FEATURE_NO_DEEP_PS, 2781 }; 2782 2783 struct rtw89_fw_suit { 2784 const u8 *data; 2785 u32 size; 2786 u8 major_ver; 2787 u8 minor_ver; 2788 u8 sub_ver; 2789 u8 sub_idex; 2790 u16 build_year; 2791 u16 build_mon; 2792 u16 build_date; 2793 u16 build_hour; 2794 u16 build_min; 2795 u8 cmd_ver; 2796 }; 2797 2798 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 2799 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 2800 #define RTW89_FW_SUIT_VER_CODE(s) \ 2801 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 2802 2803 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 2804 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 2805 (mfw_hdr)->ver.minor, \ 2806 (mfw_hdr)->ver.sub, \ 2807 (mfw_hdr)->ver.idx) 2808 2809 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 2810 RTW89_FW_VER_CODE(GET_FW_HDR_MAJOR_VERSION(fw_hdr), \ 2811 GET_FW_HDR_MINOR_VERSION(fw_hdr), \ 2812 GET_FW_HDR_SUBVERSION(fw_hdr), \ 2813 GET_FW_HDR_SUBINDEX(fw_hdr)) 2814 2815 struct rtw89_fw_info { 2816 const struct firmware *firmware; 2817 struct rtw89_dev *rtwdev; 2818 struct completion completion; 2819 u8 h2c_seq; 2820 u8 rec_seq; 2821 struct rtw89_fw_suit normal; 2822 struct rtw89_fw_suit wowlan; 2823 bool fw_log_enable; 2824 u32 feature_map; 2825 }; 2826 2827 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 2828 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 2829 2830 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 2831 ((_fw)->feature_map |= BIT(_fw_feature)) 2832 2833 struct rtw89_cam_info { 2834 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 2835 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 2836 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 2837 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 2838 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 2839 }; 2840 2841 enum rtw89_sar_sources { 2842 RTW89_SAR_SOURCE_NONE, 2843 RTW89_SAR_SOURCE_COMMON, 2844 2845 RTW89_SAR_SOURCE_NR, 2846 }; 2847 2848 enum rtw89_sar_subband { 2849 RTW89_SAR_2GHZ_SUBBAND, 2850 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 2851 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 2852 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 2853 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 2854 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 2855 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 2856 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 2857 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 2858 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 2859 2860 RTW89_SAR_SUBBAND_NR, 2861 }; 2862 2863 struct rtw89_sar_cfg_common { 2864 bool set[RTW89_SAR_SUBBAND_NR]; 2865 s32 cfg[RTW89_SAR_SUBBAND_NR]; 2866 }; 2867 2868 struct rtw89_sar_info { 2869 /* used to decide how to acces SAR cfg union */ 2870 enum rtw89_sar_sources src; 2871 2872 /* reserved for different knids of SAR cfg struct. 2873 * supposed that a single cfg struct cannot handle various SAR sources. 2874 */ 2875 union { 2876 struct rtw89_sar_cfg_common cfg_common; 2877 }; 2878 }; 2879 2880 struct rtw89_chanctx_cfg { 2881 enum rtw89_sub_entity_idx idx; 2882 }; 2883 2884 enum rtw89_entity_mode { 2885 RTW89_ENTITY_MODE_SCC, 2886 }; 2887 2888 struct rtw89_hal { 2889 u32 rx_fltr; 2890 u8 cv; 2891 u32 sw_amsdu_max_size; 2892 u32 antenna_tx; 2893 u32 antenna_rx; 2894 u8 tx_nss; 2895 u8 rx_nss; 2896 bool tx_path_diversity; 2897 bool support_cckpd; 2898 bool support_igi; 2899 2900 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 2901 struct cfg80211_chan_def chandef[NUM_OF_RTW89_SUB_ENTITY]; 2902 2903 bool entity_active; 2904 enum rtw89_entity_mode entity_mode; 2905 2906 struct rtw89_chan chan[NUM_OF_RTW89_SUB_ENTITY]; 2907 struct rtw89_chan_rcd chan_rcd[NUM_OF_RTW89_SUB_ENTITY]; 2908 }; 2909 2910 #define RTW89_MAX_MAC_ID_NUM 128 2911 #define RTW89_MAX_PKT_OFLD_NUM 255 2912 2913 enum rtw89_flags { 2914 RTW89_FLAG_POWERON, 2915 RTW89_FLAG_FW_RDY, 2916 RTW89_FLAG_RUNNING, 2917 RTW89_FLAG_BFEE_MON, 2918 RTW89_FLAG_BFEE_EN, 2919 RTW89_FLAG_NAPI_RUNNING, 2920 RTW89_FLAG_LEISURE_PS, 2921 RTW89_FLAG_LOW_POWER_MODE, 2922 RTW89_FLAG_INACTIVE_PS, 2923 RTW89_FLAG_CRASH_SIMULATING, 2924 2925 NUM_OF_RTW89_FLAGS, 2926 }; 2927 2928 enum rtw89_pkt_drop_sel { 2929 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 2930 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 2931 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 2932 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 2933 RTW89_PKT_DROP_SEL_MACID_ALL, 2934 RTW89_PKT_DROP_SEL_MG0_ONCE, 2935 RTW89_PKT_DROP_SEL_HIQ_ONCE, 2936 RTW89_PKT_DROP_SEL_HIQ_PORT, 2937 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 2938 RTW89_PKT_DROP_SEL_BAND, 2939 RTW89_PKT_DROP_SEL_BAND_ONCE, 2940 RTW89_PKT_DROP_SEL_REL_MACID, 2941 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 2942 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 2943 }; 2944 2945 struct rtw89_pkt_drop_params { 2946 enum rtw89_pkt_drop_sel sel; 2947 enum rtw89_mac_idx mac_band; 2948 u8 macid; 2949 u8 port; 2950 u8 mbssid; 2951 bool tf_trs; 2952 }; 2953 2954 struct rtw89_pkt_stat { 2955 u16 beacon_nr; 2956 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 2957 }; 2958 2959 DECLARE_EWMA(thermal, 4, 4); 2960 2961 struct rtw89_phy_stat { 2962 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 2963 struct rtw89_pkt_stat cur_pkt_stat; 2964 struct rtw89_pkt_stat last_pkt_stat; 2965 }; 2966 2967 #define RTW89_DACK_PATH_NR 2 2968 #define RTW89_DACK_IDX_NR 2 2969 #define RTW89_DACK_MSBK_NR 16 2970 struct rtw89_dack_info { 2971 bool dack_done; 2972 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 2973 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2974 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2975 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2976 u32 dack_cnt; 2977 bool addck_timeout[RTW89_DACK_PATH_NR]; 2978 bool dadck_timeout[RTW89_DACK_PATH_NR]; 2979 bool msbk_timeout[RTW89_DACK_PATH_NR]; 2980 }; 2981 2982 #define RTW89_IQK_CHS_NR 2 2983 #define RTW89_IQK_PATH_NR 4 2984 2985 struct rtw89_mcc_info { 2986 u8 ch[RTW89_IQK_CHS_NR]; 2987 u8 band[RTW89_IQK_CHS_NR]; 2988 u8 table_idx; 2989 }; 2990 2991 struct rtw89_lck_info { 2992 u8 thermal[RF_PATH_MAX]; 2993 }; 2994 2995 struct rtw89_rx_dck_info { 2996 u8 thermal[RF_PATH_MAX]; 2997 }; 2998 2999 struct rtw89_iqk_info { 3000 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3001 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3002 bool lok_fail[RTW89_IQK_PATH_NR]; 3003 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3004 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3005 u32 iqk_fail_cnt; 3006 bool is_iqk_init; 3007 u32 iqk_channel[RTW89_IQK_CHS_NR]; 3008 u8 iqk_band[RTW89_IQK_PATH_NR]; 3009 u8 iqk_ch[RTW89_IQK_PATH_NR]; 3010 u8 iqk_bw[RTW89_IQK_PATH_NR]; 3011 u8 kcount; 3012 u8 iqk_times; 3013 u8 version; 3014 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 3015 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 3016 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 3017 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 3018 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 3019 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 3020 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 3021 bool is_nbiqk; 3022 bool iqk_fft_en; 3023 bool iqk_xym_en; 3024 bool iqk_sram_en; 3025 bool iqk_cfir_en; 3026 u8 thermal[RTW89_IQK_PATH_NR]; 3027 bool thermal_rek_en; 3028 u32 syn1to2; 3029 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3030 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 3031 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3032 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3033 }; 3034 3035 #define RTW89_DPK_RF_PATH 2 3036 #define RTW89_DPK_AVG_THERMAL_NUM 8 3037 #define RTW89_DPK_BKUP_NUM 2 3038 struct rtw89_dpk_bkup_para { 3039 enum rtw89_band band; 3040 enum rtw89_bandwidth bw; 3041 u8 ch; 3042 bool path_ok; 3043 u8 mdpd_en; 3044 u8 txagc_dpk; 3045 u8 ther_dpk; 3046 u8 gs; 3047 u16 pwsf; 3048 }; 3049 3050 struct rtw89_dpk_info { 3051 bool is_dpk_enable; 3052 bool is_dpk_reload_en; 3053 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3054 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3055 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3056 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3057 u8 cur_idx[RTW89_DPK_RF_PATH]; 3058 u8 cur_k_set; 3059 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3060 }; 3061 3062 struct rtw89_fem_info { 3063 bool elna_2g; 3064 bool elna_5g; 3065 bool epa_2g; 3066 bool epa_5g; 3067 bool epa_6g; 3068 }; 3069 3070 struct rtw89_phy_ch_info { 3071 u8 rssi_min; 3072 u16 rssi_min_macid; 3073 u8 pre_rssi_min; 3074 u8 rssi_max; 3075 u16 rssi_max_macid; 3076 u8 rxsc_160; 3077 u8 rxsc_80; 3078 u8 rxsc_40; 3079 u8 rxsc_20; 3080 u8 rxsc_l; 3081 u8 is_noisy; 3082 }; 3083 3084 struct rtw89_agc_gaincode_set { 3085 u8 lna_idx; 3086 u8 tia_idx; 3087 u8 rxb_idx; 3088 }; 3089 3090 #define IGI_RSSI_TH_NUM 5 3091 #define FA_TH_NUM 4 3092 #define LNA_GAIN_NUM 7 3093 #define TIA_GAIN_NUM 2 3094 struct rtw89_dig_info { 3095 struct rtw89_agc_gaincode_set cur_gaincode; 3096 bool force_gaincode_idx_en; 3097 struct rtw89_agc_gaincode_set force_gaincode; 3098 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 3099 u16 fa_th[FA_TH_NUM]; 3100 u8 igi_rssi; 3101 u8 igi_fa_rssi; 3102 u8 fa_rssi_ofst; 3103 u8 dyn_igi_max; 3104 u8 dyn_igi_min; 3105 bool dyn_pd_th_en; 3106 u8 dyn_pd_th_max; 3107 u8 pd_low_th_ofst; 3108 u8 ib_pbk; 3109 s8 ib_pkpwr; 3110 s8 lna_gain_a[LNA_GAIN_NUM]; 3111 s8 lna_gain_g[LNA_GAIN_NUM]; 3112 s8 *lna_gain; 3113 s8 tia_gain_a[TIA_GAIN_NUM]; 3114 s8 tia_gain_g[TIA_GAIN_NUM]; 3115 s8 *tia_gain; 3116 bool is_linked_pre; 3117 bool bypass_dig; 3118 }; 3119 3120 enum rtw89_multi_cfo_mode { 3121 RTW89_PKT_BASED_AVG_MODE = 0, 3122 RTW89_ENTRY_BASED_AVG_MODE = 1, 3123 RTW89_TP_BASED_AVG_MODE = 2, 3124 }; 3125 3126 enum rtw89_phy_cfo_status { 3127 RTW89_PHY_DCFO_STATE_NORMAL = 0, 3128 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 3129 RTW89_PHY_DCFO_STATE_HOLD = 2, 3130 RTW89_PHY_DCFO_STATE_MAX 3131 }; 3132 3133 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 3134 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 3135 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 3136 }; 3137 3138 struct rtw89_cfo_tracking_info { 3139 u16 cfo_timer_ms; 3140 bool cfo_trig_by_timer_en; 3141 enum rtw89_phy_cfo_status phy_cfo_status; 3142 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 3143 u8 phy_cfo_trk_cnt; 3144 bool is_adjust; 3145 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 3146 bool apply_compensation; 3147 u8 crystal_cap; 3148 u8 crystal_cap_default; 3149 u8 def_x_cap; 3150 s8 x_cap_ofst; 3151 u32 sta_cfo_tolerance; 3152 s32 cfo_tail[CFO_TRACK_MAX_USER]; 3153 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 3154 s32 cfo_avg_pre; 3155 s32 cfo_avg[CFO_TRACK_MAX_USER]; 3156 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 3157 u32 packet_count; 3158 u32 packet_count_pre; 3159 s32 residual_cfo_acc; 3160 u8 phy_cfotrk_state; 3161 u8 phy_cfotrk_cnt; 3162 bool divergence_lock_en; 3163 u8 x_cap_lb; 3164 u8 x_cap_ub; 3165 u8 lock_cnt; 3166 }; 3167 3168 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 3169 #define TSSI_TRIM_CH_GROUP_NUM 8 3170 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 3171 3172 #define TSSI_CCK_CH_GROUP_NUM 6 3173 #define TSSI_MCS_2G_CH_GROUP_NUM 5 3174 #define TSSI_MCS_5G_CH_GROUP_NUM 14 3175 #define TSSI_MCS_6G_CH_GROUP_NUM 32 3176 #define TSSI_MCS_CH_GROUP_NUM \ 3177 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 3178 3179 struct rtw89_tssi_info { 3180 u8 thermal[RF_PATH_MAX]; 3181 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 3182 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 3183 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 3184 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 3185 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 3186 s8 extra_ofst[RF_PATH_MAX]; 3187 bool tssi_tracking_check[RF_PATH_MAX]; 3188 u8 default_txagc_offset[RF_PATH_MAX]; 3189 u32 base_thermal[RF_PATH_MAX]; 3190 }; 3191 3192 struct rtw89_power_trim_info { 3193 bool pg_thermal_trim; 3194 bool pg_pa_bias_trim; 3195 u8 thermal_trim[RF_PATH_MAX]; 3196 u8 pa_bias_trim[RF_PATH_MAX]; 3197 }; 3198 3199 struct rtw89_regulatory { 3200 char alpha2[3]; 3201 u8 txpwr_regd[RTW89_BAND_MAX]; 3202 }; 3203 3204 enum rtw89_ifs_clm_application { 3205 RTW89_IFS_CLM_INIT = 0, 3206 RTW89_IFS_CLM_BACKGROUND = 1, 3207 RTW89_IFS_CLM_ACS = 2, 3208 RTW89_IFS_CLM_DIG = 3, 3209 RTW89_IFS_CLM_TDMA_DIG = 4, 3210 RTW89_IFS_CLM_DBG = 5, 3211 RTW89_IFS_CLM_DBG_MANUAL = 6 3212 }; 3213 3214 enum rtw89_env_racing_lv { 3215 RTW89_RAC_RELEASE = 0, 3216 RTW89_RAC_LV_1 = 1, 3217 RTW89_RAC_LV_2 = 2, 3218 RTW89_RAC_LV_3 = 3, 3219 RTW89_RAC_LV_4 = 4, 3220 RTW89_RAC_MAX_NUM = 5 3221 }; 3222 3223 struct rtw89_ccx_para_info { 3224 enum rtw89_env_racing_lv rac_lv; 3225 u16 mntr_time; 3226 u8 nhm_manual_th_ofst; 3227 u8 nhm_manual_th0; 3228 enum rtw89_ifs_clm_application ifs_clm_app; 3229 u32 ifs_clm_manual_th_times; 3230 u32 ifs_clm_manual_th0; 3231 u8 fahm_manual_th_ofst; 3232 u8 fahm_manual_th0; 3233 u8 fahm_numer_opt; 3234 u8 fahm_denom_opt; 3235 }; 3236 3237 enum rtw89_ccx_edcca_opt_sc_idx { 3238 RTW89_CCX_EDCCA_SEG0_P0 = 0, 3239 RTW89_CCX_EDCCA_SEG0_S1 = 1, 3240 RTW89_CCX_EDCCA_SEG0_S2 = 2, 3241 RTW89_CCX_EDCCA_SEG0_S3 = 3, 3242 RTW89_CCX_EDCCA_SEG1_P0 = 4, 3243 RTW89_CCX_EDCCA_SEG1_S1 = 5, 3244 RTW89_CCX_EDCCA_SEG1_S2 = 6, 3245 RTW89_CCX_EDCCA_SEG1_S3 = 7 3246 }; 3247 3248 enum rtw89_ccx_edcca_opt_bw_idx { 3249 RTW89_CCX_EDCCA_BW20_0 = 0, 3250 RTW89_CCX_EDCCA_BW20_1 = 1, 3251 RTW89_CCX_EDCCA_BW20_2 = 2, 3252 RTW89_CCX_EDCCA_BW20_3 = 3, 3253 RTW89_CCX_EDCCA_BW20_4 = 4, 3254 RTW89_CCX_EDCCA_BW20_5 = 5, 3255 RTW89_CCX_EDCCA_BW20_6 = 6, 3256 RTW89_CCX_EDCCA_BW20_7 = 7 3257 }; 3258 3259 #define RTW89_NHM_TH_NUM 11 3260 #define RTW89_FAHM_TH_NUM 11 3261 #define RTW89_NHM_RPT_NUM 12 3262 #define RTW89_FAHM_RPT_NUM 12 3263 #define RTW89_IFS_CLM_NUM 4 3264 struct rtw89_env_monitor_info { 3265 u32 ccx_trigger_time; 3266 u64 start_time; 3267 u8 ccx_rpt_stamp; 3268 u8 ccx_watchdog_result; 3269 bool ccx_ongoing; 3270 u8 ccx_rac_lv; 3271 bool ccx_manual_ctrl; 3272 u8 ccx_pre_rssi; 3273 u16 clm_mntr_time; 3274 u16 nhm_mntr_time; 3275 u16 ifs_clm_mntr_time; 3276 enum rtw89_ifs_clm_application ifs_clm_app; 3277 u16 fahm_mntr_time; 3278 u16 edcca_clm_mntr_time; 3279 u16 ccx_period; 3280 u8 ccx_unit_idx; 3281 enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx; 3282 u8 nhm_th[RTW89_NHM_TH_NUM]; 3283 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 3284 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 3285 u8 fahm_numer_opt; 3286 u8 fahm_denom_opt; 3287 u8 fahm_th[RTW89_FAHM_TH_NUM]; 3288 u16 clm_result; 3289 u16 nhm_result[RTW89_NHM_RPT_NUM]; 3290 u8 nhm_wgt[RTW89_NHM_RPT_NUM]; 3291 u16 nhm_tx_cnt; 3292 u16 nhm_cca_cnt; 3293 u16 nhm_idle_cnt; 3294 u16 ifs_clm_tx; 3295 u16 ifs_clm_edcca_excl_cca; 3296 u16 ifs_clm_ofdmfa; 3297 u16 ifs_clm_ofdmcca_excl_fa; 3298 u16 ifs_clm_cckfa; 3299 u16 ifs_clm_cckcca_excl_fa; 3300 u16 ifs_clm_total_ifs; 3301 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 3302 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 3303 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 3304 u16 fahm_result[RTW89_FAHM_RPT_NUM]; 3305 u16 fahm_denom_result; 3306 u16 edcca_clm_result; 3307 u8 clm_ratio; 3308 u8 nhm_rpt[RTW89_NHM_RPT_NUM]; 3309 u8 nhm_tx_ratio; 3310 u8 nhm_cca_ratio; 3311 u8 nhm_idle_ratio; 3312 u8 nhm_ratio; 3313 u16 nhm_result_sum; 3314 u8 nhm_pwr; 3315 u8 ifs_clm_tx_ratio; 3316 u8 ifs_clm_edcca_excl_cca_ratio; 3317 u8 ifs_clm_cck_fa_ratio; 3318 u8 ifs_clm_ofdm_fa_ratio; 3319 u8 ifs_clm_cck_cca_excl_fa_ratio; 3320 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 3321 u16 ifs_clm_cck_fa_permil; 3322 u16 ifs_clm_ofdm_fa_permil; 3323 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 3324 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 3325 u8 fahm_rpt[RTW89_FAHM_RPT_NUM]; 3326 u16 fahm_result_sum; 3327 u8 fahm_ratio; 3328 u8 fahm_denom_ratio; 3329 u8 fahm_pwr; 3330 u8 edcca_clm_ratio; 3331 }; 3332 3333 enum rtw89_ser_rcvy_step { 3334 RTW89_SER_DRV_STOP_TX, 3335 RTW89_SER_DRV_STOP_RX, 3336 RTW89_SER_DRV_STOP_RUN, 3337 RTW89_SER_HAL_STOP_DMA, 3338 RTW89_NUM_OF_SER_FLAGS 3339 }; 3340 3341 struct rtw89_ser { 3342 u8 state; 3343 u8 alarm_event; 3344 3345 struct work_struct ser_hdl_work; 3346 struct delayed_work ser_alarm_work; 3347 const struct state_ent *st_tbl; 3348 const struct event_ent *ev_tbl; 3349 struct list_head msg_q; 3350 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 3351 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 3352 }; 3353 3354 enum rtw89_mac_ax_ps_mode { 3355 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 3356 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 3357 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 3358 RTW89_MAC_AX_PS_MODE_MAX = 3, 3359 }; 3360 3361 enum rtw89_last_rpwm_mode { 3362 RTW89_LAST_RPWM_PS = 0x0, 3363 RTW89_LAST_RPWM_ACTIVE = 0x6, 3364 }; 3365 3366 struct rtw89_lps_parm { 3367 u8 macid; 3368 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 3369 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 3370 }; 3371 3372 struct rtw89_ppdu_sts_info { 3373 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 3374 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 3375 }; 3376 3377 struct rtw89_early_h2c { 3378 struct list_head list; 3379 u8 *h2c; 3380 u16 h2c_len; 3381 }; 3382 3383 struct rtw89_hw_scan_info { 3384 struct ieee80211_vif *scanning_vif; 3385 struct list_head pkt_list[NUM_NL80211_BANDS]; 3386 u8 op_pri_ch; 3387 u8 op_chan; 3388 u8 op_bw; 3389 u8 op_band; 3390 u32 last_chan_idx; 3391 }; 3392 3393 enum rtw89_phy_bb_gain_band { 3394 RTW89_BB_GAIN_BAND_2G = 0, 3395 RTW89_BB_GAIN_BAND_5G_L = 1, 3396 RTW89_BB_GAIN_BAND_5G_M = 2, 3397 RTW89_BB_GAIN_BAND_5G_H = 3, 3398 RTW89_BB_GAIN_BAND_6G_L = 4, 3399 RTW89_BB_GAIN_BAND_6G_M = 5, 3400 RTW89_BB_GAIN_BAND_6G_H = 6, 3401 RTW89_BB_GAIN_BAND_6G_UH = 7, 3402 3403 RTW89_BB_GAIN_BAND_NR, 3404 }; 3405 3406 enum rtw89_phy_bb_rxsc_num { 3407 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 3408 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 3409 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 3410 }; 3411 3412 struct rtw89_phy_bb_gain_info { 3413 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3414 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 3415 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3416 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 3417 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3418 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 3419 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 3420 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3421 [RTW89_BB_RXSC_NUM_40]; 3422 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3423 [RTW89_BB_RXSC_NUM_80]; 3424 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 3425 [RTW89_BB_RXSC_NUM_160]; 3426 }; 3427 3428 struct rtw89_phy_efuse_gain { 3429 bool offset_valid; 3430 bool comp_valid; 3431 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 3432 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 3433 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 3434 }; 3435 3436 struct rtw89_dev { 3437 struct ieee80211_hw *hw; 3438 struct device *dev; 3439 const struct ieee80211_ops *ops; 3440 3441 bool dbcc_en; 3442 struct rtw89_hw_scan_info scan_info; 3443 const struct rtw89_chip_info *chip; 3444 const struct rtw89_pci_info *pci_info; 3445 struct rtw89_hal hal; 3446 struct rtw89_mac_info mac; 3447 struct rtw89_fw_info fw; 3448 struct rtw89_hci_info hci; 3449 struct rtw89_efuse efuse; 3450 struct rtw89_traffic_stats stats; 3451 3452 /* ensures exclusive access from mac80211 callbacks */ 3453 struct mutex mutex; 3454 struct list_head rtwvifs_list; 3455 /* used to protect rf read write */ 3456 struct mutex rf_mutex; 3457 struct workqueue_struct *txq_wq; 3458 struct work_struct txq_work; 3459 struct delayed_work txq_reinvoke_work; 3460 /* used to protect ba_list and forbid_ba_list */ 3461 spinlock_t ba_lock; 3462 /* txqs to setup ba session */ 3463 struct list_head ba_list; 3464 /* txqs to forbid ba session */ 3465 struct list_head forbid_ba_list; 3466 struct work_struct ba_work; 3467 /* used to protect rpwm */ 3468 spinlock_t rpwm_lock; 3469 3470 struct rtw89_cam_info cam_info; 3471 3472 struct sk_buff_head c2h_queue; 3473 struct work_struct c2h_work; 3474 struct work_struct ips_work; 3475 3476 struct list_head early_h2c_list; 3477 3478 struct rtw89_ser ser; 3479 3480 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 3481 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 3482 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 3483 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 3484 3485 struct rtw89_phy_stat phystat; 3486 struct rtw89_dack_info dack; 3487 struct rtw89_iqk_info iqk; 3488 struct rtw89_dpk_info dpk; 3489 struct rtw89_mcc_info mcc; 3490 struct rtw89_lck_info lck; 3491 struct rtw89_rx_dck_info rx_dck; 3492 bool is_tssi_mode[RF_PATH_MAX]; 3493 bool is_bt_iqk_timeout; 3494 3495 struct rtw89_fem_info fem; 3496 struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX]; 3497 struct rtw89_tssi_info tssi; 3498 struct rtw89_power_trim_info pwr_trim; 3499 3500 struct rtw89_cfo_tracking_info cfo_tracking; 3501 struct rtw89_env_monitor_info env_monitor; 3502 struct rtw89_dig_info dig; 3503 struct rtw89_phy_ch_info ch_info; 3504 struct rtw89_phy_bb_gain_info bb_gain; 3505 struct rtw89_phy_efuse_gain efuse_gain; 3506 3507 struct delayed_work track_work; 3508 struct delayed_work coex_act1_work; 3509 struct delayed_work coex_bt_devinfo_work; 3510 struct delayed_work coex_rfk_chk_work; 3511 struct delayed_work cfo_track_work; 3512 struct delayed_work forbid_ba_work; 3513 struct rtw89_ppdu_sts_info ppdu_sts; 3514 u8 total_sta_assoc; 3515 bool scanning; 3516 3517 const struct rtw89_regulatory *regd; 3518 struct rtw89_sar_info sar; 3519 3520 struct rtw89_btc btc; 3521 enum rtw89_ps_mode ps_mode; 3522 bool lps_enabled; 3523 3524 /* napi structure */ 3525 struct net_device netdev; 3526 struct napi_struct napi; 3527 int napi_budget_countdown; 3528 3529 /* HCI related data, keep last */ 3530 u8 priv[] __aligned(sizeof(void *)); 3531 }; 3532 3533 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 3534 struct rtw89_core_tx_request *tx_req) 3535 { 3536 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 3537 } 3538 3539 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 3540 { 3541 rtwdev->hci.ops->reset(rtwdev); 3542 } 3543 3544 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 3545 { 3546 return rtwdev->hci.ops->start(rtwdev); 3547 } 3548 3549 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 3550 { 3551 rtwdev->hci.ops->stop(rtwdev); 3552 } 3553 3554 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 3555 { 3556 return rtwdev->hci.ops->deinit(rtwdev); 3557 } 3558 3559 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 3560 { 3561 rtwdev->hci.ops->pause(rtwdev, pause); 3562 } 3563 3564 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 3565 { 3566 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 3567 } 3568 3569 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 3570 { 3571 rtwdev->hci.ops->recalc_int_mit(rtwdev); 3572 } 3573 3574 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 3575 { 3576 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 3577 } 3578 3579 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 3580 { 3581 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 3582 } 3583 3584 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 3585 bool drop) 3586 { 3587 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 3588 return; 3589 3590 if (rtwdev->hci.ops->flush_queues) 3591 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 3592 } 3593 3594 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 3595 { 3596 if (rtwdev->hci.ops->recovery_start) 3597 rtwdev->hci.ops->recovery_start(rtwdev); 3598 } 3599 3600 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 3601 { 3602 if (rtwdev->hci.ops->recovery_complete) 3603 rtwdev->hci.ops->recovery_complete(rtwdev); 3604 } 3605 3606 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 3607 { 3608 return rtwdev->hci.ops->read8(rtwdev, addr); 3609 } 3610 3611 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 3612 { 3613 return rtwdev->hci.ops->read16(rtwdev, addr); 3614 } 3615 3616 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 3617 { 3618 return rtwdev->hci.ops->read32(rtwdev, addr); 3619 } 3620 3621 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 3622 { 3623 rtwdev->hci.ops->write8(rtwdev, addr, data); 3624 } 3625 3626 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 3627 { 3628 rtwdev->hci.ops->write16(rtwdev, addr, data); 3629 } 3630 3631 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 3632 { 3633 rtwdev->hci.ops->write32(rtwdev, addr, data); 3634 } 3635 3636 static inline void 3637 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 3638 { 3639 u8 val; 3640 3641 val = rtw89_read8(rtwdev, addr); 3642 rtw89_write8(rtwdev, addr, val | bit); 3643 } 3644 3645 static inline void 3646 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 3647 { 3648 u16 val; 3649 3650 val = rtw89_read16(rtwdev, addr); 3651 rtw89_write16(rtwdev, addr, val | bit); 3652 } 3653 3654 static inline void 3655 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 3656 { 3657 u32 val; 3658 3659 val = rtw89_read32(rtwdev, addr); 3660 rtw89_write32(rtwdev, addr, val | bit); 3661 } 3662 3663 static inline void 3664 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 3665 { 3666 u8 val; 3667 3668 val = rtw89_read8(rtwdev, addr); 3669 rtw89_write8(rtwdev, addr, val & ~bit); 3670 } 3671 3672 static inline void 3673 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 3674 { 3675 u16 val; 3676 3677 val = rtw89_read16(rtwdev, addr); 3678 rtw89_write16(rtwdev, addr, val & ~bit); 3679 } 3680 3681 static inline void 3682 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 3683 { 3684 u32 val; 3685 3686 val = rtw89_read32(rtwdev, addr); 3687 rtw89_write32(rtwdev, addr, val & ~bit); 3688 } 3689 3690 static inline u32 3691 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3692 { 3693 u32 shift = __ffs(mask); 3694 u32 orig; 3695 u32 ret; 3696 3697 orig = rtw89_read32(rtwdev, addr); 3698 ret = (orig & mask) >> shift; 3699 3700 return ret; 3701 } 3702 3703 static inline u16 3704 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3705 { 3706 u32 shift = __ffs(mask); 3707 u32 orig; 3708 u32 ret; 3709 3710 orig = rtw89_read16(rtwdev, addr); 3711 ret = (orig & mask) >> shift; 3712 3713 return ret; 3714 } 3715 3716 static inline u8 3717 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3718 { 3719 u32 shift = __ffs(mask); 3720 u32 orig; 3721 u32 ret; 3722 3723 orig = rtw89_read8(rtwdev, addr); 3724 ret = (orig & mask) >> shift; 3725 3726 return ret; 3727 } 3728 3729 static inline void 3730 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 3731 { 3732 u32 shift = __ffs(mask); 3733 u32 orig; 3734 u32 set; 3735 3736 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 3737 3738 orig = rtw89_read32(rtwdev, addr); 3739 set = (orig & ~mask) | ((data << shift) & mask); 3740 rtw89_write32(rtwdev, addr, set); 3741 } 3742 3743 static inline void 3744 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 3745 { 3746 u32 shift; 3747 u16 orig, set; 3748 3749 mask &= 0xffff; 3750 shift = __ffs(mask); 3751 3752 orig = rtw89_read16(rtwdev, addr); 3753 set = (orig & ~mask) | ((data << shift) & mask); 3754 rtw89_write16(rtwdev, addr, set); 3755 } 3756 3757 static inline void 3758 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 3759 { 3760 u32 shift; 3761 u8 orig, set; 3762 3763 mask &= 0xff; 3764 shift = __ffs(mask); 3765 3766 orig = rtw89_read8(rtwdev, addr); 3767 set = (orig & ~mask) | ((data << shift) & mask); 3768 rtw89_write8(rtwdev, addr, set); 3769 } 3770 3771 static inline u32 3772 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3773 u32 addr, u32 mask) 3774 { 3775 u32 val; 3776 3777 mutex_lock(&rtwdev->rf_mutex); 3778 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 3779 mutex_unlock(&rtwdev->rf_mutex); 3780 3781 return val; 3782 } 3783 3784 static inline void 3785 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3786 u32 addr, u32 mask, u32 data) 3787 { 3788 mutex_lock(&rtwdev->rf_mutex); 3789 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 3790 mutex_unlock(&rtwdev->rf_mutex); 3791 } 3792 3793 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 3794 { 3795 void *p = rtwtxq; 3796 3797 return container_of(p, struct ieee80211_txq, drv_priv); 3798 } 3799 3800 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 3801 struct ieee80211_txq *txq) 3802 { 3803 struct rtw89_txq *rtwtxq; 3804 3805 if (!txq) 3806 return; 3807 3808 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3809 INIT_LIST_HEAD(&rtwtxq->list); 3810 } 3811 3812 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 3813 { 3814 void *p = rtwvif; 3815 3816 return container_of(p, struct ieee80211_vif, drv_priv); 3817 } 3818 3819 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 3820 { 3821 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 3822 } 3823 3824 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 3825 { 3826 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 3827 } 3828 3829 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 3830 { 3831 void *p = rtwsta; 3832 3833 return container_of(p, struct ieee80211_sta, drv_priv); 3834 } 3835 3836 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 3837 { 3838 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 3839 } 3840 3841 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 3842 { 3843 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 3844 } 3845 3846 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 3847 { 3848 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 3849 return RATE_INFO_BW_160; 3850 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 3851 return RATE_INFO_BW_80; 3852 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 3853 return RATE_INFO_BW_40; 3854 else 3855 return RATE_INFO_BW_20; 3856 } 3857 3858 static inline 3859 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 3860 { 3861 switch (hw_band) { 3862 default: 3863 case RTW89_BAND_2G: 3864 return NL80211_BAND_2GHZ; 3865 case RTW89_BAND_5G: 3866 return NL80211_BAND_5GHZ; 3867 case RTW89_BAND_6G: 3868 return NL80211_BAND_6GHZ; 3869 } 3870 } 3871 3872 static inline 3873 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 3874 { 3875 switch (nl_band) { 3876 default: 3877 case NL80211_BAND_2GHZ: 3878 return RTW89_BAND_2G; 3879 case NL80211_BAND_5GHZ: 3880 return RTW89_BAND_5G; 3881 case NL80211_BAND_6GHZ: 3882 return RTW89_BAND_6G; 3883 } 3884 } 3885 3886 static inline 3887 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 3888 { 3889 switch (width) { 3890 default: 3891 WARN(1, "Not support bandwidth %d\n", width); 3892 fallthrough; 3893 case NL80211_CHAN_WIDTH_20_NOHT: 3894 case NL80211_CHAN_WIDTH_20: 3895 return RTW89_CHANNEL_WIDTH_20; 3896 case NL80211_CHAN_WIDTH_40: 3897 return RTW89_CHANNEL_WIDTH_40; 3898 case NL80211_CHAN_WIDTH_80: 3899 return RTW89_CHANNEL_WIDTH_80; 3900 case NL80211_CHAN_WIDTH_160: 3901 return RTW89_CHANNEL_WIDTH_160; 3902 } 3903 } 3904 3905 static inline 3906 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 3907 struct rtw89_sta *rtwsta) 3908 { 3909 if (rtwsta) { 3910 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 3911 3912 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 3913 return &rtwsta->addr_cam; 3914 } 3915 return &rtwvif->addr_cam; 3916 } 3917 3918 static inline 3919 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 3920 struct rtw89_sta *rtwsta) 3921 { 3922 if (rtwsta) { 3923 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 3924 3925 if (sta->tdls) 3926 return &rtwsta->bssid_cam; 3927 } 3928 return &rtwvif->bssid_cam; 3929 } 3930 3931 static inline 3932 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 3933 struct rtw89_channel_help_params *p, 3934 const struct rtw89_chan *chan, 3935 enum rtw89_mac_idx mac_idx, 3936 enum rtw89_phy_idx phy_idx) 3937 { 3938 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 3939 mac_idx, phy_idx); 3940 } 3941 3942 static inline 3943 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 3944 struct rtw89_channel_help_params *p, 3945 const struct rtw89_chan *chan, 3946 enum rtw89_mac_idx mac_idx, 3947 enum rtw89_phy_idx phy_idx) 3948 { 3949 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 3950 mac_idx, phy_idx); 3951 } 3952 3953 static inline 3954 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 3955 enum rtw89_sub_entity_idx idx) 3956 { 3957 struct rtw89_hal *hal = &rtwdev->hal; 3958 3959 return &hal->chandef[idx]; 3960 } 3961 3962 static inline 3963 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 3964 enum rtw89_sub_entity_idx idx) 3965 { 3966 struct rtw89_hal *hal = &rtwdev->hal; 3967 3968 return &hal->chan[idx]; 3969 } 3970 3971 static inline 3972 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 3973 enum rtw89_sub_entity_idx idx) 3974 { 3975 struct rtw89_hal *hal = &rtwdev->hal; 3976 3977 return &hal->chan_rcd[idx]; 3978 } 3979 3980 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 3981 { 3982 const struct rtw89_chip_info *chip = rtwdev->chip; 3983 3984 if (chip->ops->fem_setup) 3985 chip->ops->fem_setup(rtwdev); 3986 } 3987 3988 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 3989 { 3990 const struct rtw89_chip_info *chip = rtwdev->chip; 3991 3992 if (chip->ops->bb_sethw) 3993 chip->ops->bb_sethw(rtwdev); 3994 } 3995 3996 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 3997 { 3998 const struct rtw89_chip_info *chip = rtwdev->chip; 3999 4000 if (chip->ops->rfk_init) 4001 chip->ops->rfk_init(rtwdev); 4002 } 4003 4004 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 4005 { 4006 const struct rtw89_chip_info *chip = rtwdev->chip; 4007 4008 if (chip->ops->rfk_channel) 4009 chip->ops->rfk_channel(rtwdev); 4010 } 4011 4012 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 4013 enum rtw89_phy_idx phy_idx) 4014 { 4015 const struct rtw89_chip_info *chip = rtwdev->chip; 4016 4017 if (chip->ops->rfk_band_changed) 4018 chip->ops->rfk_band_changed(rtwdev, phy_idx); 4019 } 4020 4021 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 4022 { 4023 const struct rtw89_chip_info *chip = rtwdev->chip; 4024 4025 if (chip->ops->rfk_scan) 4026 chip->ops->rfk_scan(rtwdev, start); 4027 } 4028 4029 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 4030 { 4031 const struct rtw89_chip_info *chip = rtwdev->chip; 4032 4033 if (chip->ops->rfk_track) 4034 chip->ops->rfk_track(rtwdev); 4035 } 4036 4037 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 4038 { 4039 const struct rtw89_chip_info *chip = rtwdev->chip; 4040 4041 if (chip->ops->set_txpwr_ctrl) 4042 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 4043 } 4044 4045 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 4046 { 4047 const struct rtw89_chip_info *chip = rtwdev->chip; 4048 4049 if (chip->ops->power_trim) 4050 chip->ops->power_trim(rtwdev); 4051 } 4052 4053 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 4054 enum rtw89_phy_idx phy_idx) 4055 { 4056 const struct rtw89_chip_info *chip = rtwdev->chip; 4057 4058 if (chip->ops->init_txpwr_unit) 4059 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 4060 } 4061 4062 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 4063 enum rtw89_rf_path rf_path) 4064 { 4065 const struct rtw89_chip_info *chip = rtwdev->chip; 4066 4067 if (!chip->ops->get_thermal) 4068 return 0x10; 4069 4070 return chip->ops->get_thermal(rtwdev, rf_path); 4071 } 4072 4073 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 4074 struct rtw89_rx_phy_ppdu *phy_ppdu, 4075 struct ieee80211_rx_status *status) 4076 { 4077 const struct rtw89_chip_info *chip = rtwdev->chip; 4078 4079 if (chip->ops->query_ppdu) 4080 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 4081 } 4082 4083 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, 4084 bool bt_en) 4085 { 4086 const struct rtw89_chip_info *chip = rtwdev->chip; 4087 4088 if (chip->ops->bb_ctrl_btc_preagc) 4089 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en); 4090 } 4091 4092 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 4093 { 4094 const struct rtw89_chip_info *chip = rtwdev->chip; 4095 4096 if (chip->ops->cfg_txrx_path) 4097 chip->ops->cfg_txrx_path(rtwdev); 4098 } 4099 4100 static inline 4101 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 4102 struct ieee80211_vif *vif) 4103 { 4104 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4105 const struct rtw89_chip_info *chip = rtwdev->chip; 4106 4107 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 4108 return; 4109 4110 if (chip->ops->set_txpwr_ul_tb_offset) 4111 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 4112 } 4113 4114 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 4115 const struct rtw89_txpwr_table *tbl) 4116 { 4117 tbl->load(rtwdev, tbl); 4118 } 4119 4120 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 4121 { 4122 return rtwdev->regd->txpwr_regd[band]; 4123 } 4124 4125 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 4126 { 4127 const struct rtw89_chip_info *chip = rtwdev->chip; 4128 4129 if (chip->ops->ctrl_btg) 4130 chip->ops->ctrl_btg(rtwdev, btg); 4131 } 4132 4133 static inline 4134 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 4135 struct rtw89_tx_desc_info *desc_info, 4136 void *txdesc) 4137 { 4138 const struct rtw89_chip_info *chip = rtwdev->chip; 4139 4140 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 4141 } 4142 4143 static inline 4144 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 4145 struct rtw89_tx_desc_info *desc_info, 4146 void *txdesc) 4147 { 4148 const struct rtw89_chip_info *chip = rtwdev->chip; 4149 4150 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 4151 } 4152 4153 static inline 4154 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 4155 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4156 { 4157 const struct rtw89_chip_info *chip = rtwdev->chip; 4158 4159 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 4160 } 4161 4162 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 4163 { 4164 const struct rtw89_chip_info *chip = rtwdev->chip; 4165 4166 chip->ops->cfg_ctrl_path(rtwdev, wl); 4167 } 4168 4169 static inline 4170 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 4171 u32 *tx_en, enum rtw89_sch_tx_sel sel) 4172 { 4173 const struct rtw89_chip_info *chip = rtwdev->chip; 4174 4175 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 4176 } 4177 4178 static inline 4179 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 4180 { 4181 const struct rtw89_chip_info *chip = rtwdev->chip; 4182 4183 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 4184 } 4185 4186 static inline 4187 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 4188 struct rtw89_vif *rtwvif, 4189 struct rtw89_sta *rtwsta) 4190 { 4191 const struct rtw89_chip_info *chip = rtwdev->chip; 4192 4193 if (!chip->ops->h2c_dctl_sec_cam) 4194 return 0; 4195 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 4196 } 4197 4198 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 4199 { 4200 __le16 fc = hdr->frame_control; 4201 4202 if (ieee80211_has_tods(fc)) 4203 return hdr->addr1; 4204 else if (ieee80211_has_fromds(fc)) 4205 return hdr->addr2; 4206 else 4207 return hdr->addr3; 4208 } 4209 4210 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 4211 { 4212 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 4213 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 4214 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 4215 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 4216 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 4217 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 4218 return true; 4219 return false; 4220 } 4221 4222 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 4223 enum rtw89_fw_type type) 4224 { 4225 struct rtw89_fw_info *fw_info = &rtwdev->fw; 4226 4227 if (type == RTW89_FW_WOWLAN) 4228 return &fw_info->wowlan; 4229 return &fw_info->normal; 4230 } 4231 4232 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 4233 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 4234 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 4235 struct sk_buff *skb, bool fwdl); 4236 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 4237 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 4238 struct rtw89_tx_desc_info *desc_info, 4239 void *txdesc); 4240 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 4241 struct rtw89_tx_desc_info *desc_info, 4242 void *txdesc); 4243 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 4244 struct rtw89_tx_desc_info *desc_info, 4245 void *txdesc); 4246 void rtw89_core_rx(struct rtw89_dev *rtwdev, 4247 struct rtw89_rx_desc_info *desc_info, 4248 struct sk_buff *skb); 4249 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 4250 struct rtw89_rx_desc_info *desc_info, 4251 u8 *data, u32 data_offset); 4252 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 4253 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 4254 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 4255 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 4256 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 4257 struct ieee80211_vif *vif, 4258 struct ieee80211_sta *sta); 4259 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 4260 struct ieee80211_vif *vif, 4261 struct ieee80211_sta *sta); 4262 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 4263 struct ieee80211_vif *vif, 4264 struct ieee80211_sta *sta); 4265 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 4266 struct ieee80211_vif *vif, 4267 struct ieee80211_sta *sta); 4268 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 4269 struct ieee80211_vif *vif, 4270 struct ieee80211_sta *sta); 4271 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 4272 struct ieee80211_sta *sta, 4273 struct cfg80211_tid_config *tid_config); 4274 int rtw89_core_init(struct rtw89_dev *rtwdev); 4275 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 4276 int rtw89_core_register(struct rtw89_dev *rtwdev); 4277 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 4278 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 4279 u32 bus_data_size, 4280 const struct rtw89_chip_info *chip); 4281 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 4282 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 4283 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 4284 void rtw89_set_channel(struct rtw89_dev *rtwdev); 4285 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 4286 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 4287 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 4288 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 4289 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 4290 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 4291 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 4292 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 4293 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 4294 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 4295 int rtw89_regd_init(struct rtw89_dev *rtwdev, 4296 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 4297 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 4298 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 4299 struct rtw89_traffic_stats *stats); 4300 int rtw89_core_start(struct rtw89_dev *rtwdev); 4301 void rtw89_core_stop(struct rtw89_dev *rtwdev); 4302 void rtw89_core_update_beacon_work(struct work_struct *work); 4303 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4304 const u8 *mac_addr, bool hw_scan); 4305 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 4306 struct ieee80211_vif *vif, bool hw_scan); 4307 4308 #endif 4309